CS4412A-CNZR - Cirrus Logic Inc.

http://www.cirrus.com

Advance Product Information This document contains information for a new product.

Cirrus Logic reserves the right to modify this product without notice.

30 W Quad Half-Bridge Digital Amplifier Power Stage

Features

Configurable Outputs (10% THD+N)

– 2 x 15 W into 8 Ω, Full-Bridge

– 1 x 30 W into 4 Ω, Parallel Full-Bridge

– 4 x 7.5 W into 4 Ω, Half-Bridge

– 2 x 7.5 W into 4 Ω, Half-Bridge + 1 x 15 W

into 8 Ω, Full-Bridge

Space-Efficient Thermally-Enhanced QFN

– No External Heat Sink Required

> 100 dB Dynamic Range - System Level

< 0.1% THD+N @ 1 W - System Level

Built-In Protection with Error Reporting

– Over-Current

– Thermal Warning and Overload

– Under-Voltage

+8 V to +18 V High Voltage Supply

PWM Popguard® Technology for Quiet Startup

No Bootstrap Required

Low Quiescent Current

Low Power Standby Mode

Common Applications

Integrated Digital Televisions

Portable Media Player Docking Stations

Mini/Micro Shelf Systems

Powered Desktop Speakers

General Description

The CS4412A is a high-efficiency power stage for digital

Class-D amplifiers designed to input PWM signa ls from

a modulator such as the CS4525. The power stage out-

puts can be configured as four half-bridge channels, two

half-bridge channels and one full-bridge channel, two

full-bridge channels, or one parallel full-bridge channel.

The CS4412A integrates on-chip over-current, under-

voltage, over-temperature protection, and error report-

ing as well as a thermal warning indicator. The low

RDS(ON) outputs can source up to 2.5 A peak current,

delivering high efficiency which allows small device

package and lower power supplies.

The CS4412A is available in a 48-pin QFN package in

Commercial grade (-10°C to +70°C). The CRD4412A

customer reference design is also available. Please re-

fer to “Ordering Information” on page 23 for complete

ordering information.

VP Amplifier

Out 1

Amplifier

Out 2

PGND

Amplifier

Out 3

Amplifier

Out 4

Gate

Drive

Gate

Drive

Gate

Drive

Gate

Drive

2.5 V to 5 V 8 V to 18 V

In 1 Non-Overlap

Time Insertion

Non-Overlap

Time Insertion

Non-Overlap

Time Insertion

Non-Overlap

Time Insertion

Protection &

Error Reporting

In 2

In 3

In 4

Current &

Thermal Data

Control Logic

Hardware

Configuration

Reset

Mode

Configuration

JUN '08

DS786A2

CS4412A

2DS786A2

CS4412A

TABLE OF CONTENTS

1. PIN DESCRIPTION ................................................................................................................................. 3

2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 5

RECOMMENDED OPERATING CONDITIONS .................................................................................... 5

ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 5

PWM POWER OUTPUT CHARACTERISTICS ..................................................................................... 6

DC ELECTRICAL CHARACTERISTICS ................................................................................................ 7

DIGITAL INTERFACE SPECIFICATIONS ............................................................................................. 7

DIGITAL I/O PIN CHARACTERISTICS ................................................................................................. 8

3. TYPICAL CONNECTION DIAGRAMS ................................................................................................. 9

4. APPLICATIONS ................................................................................................................................... 13

4.1 Overview ........................................................................................................................................ 13

4.2 Reset and Power-Up .. .... ... ... ... .... ................... ... ... .... ... ... ................... .... ... ... ... .... ... ......................... 13

4.2.1 PWM Popguard Transient Control ..................... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ... 13

4.2.2 Initial Pulse Edge Delay ................. .................... ... ... .................... ... ... ................... .... ... ......... 14

4.2.3 Recommended Power-Up Sequence .................................................................................... 14

4.2.4 Recommended Power-Down Sequence ............................................................................... 14

4.3 Output Mode Configuration ............................................................................................................ 15

4.4 Output Filters ................................................................................................................................. 16

4.4.1 Half-Bridge Output Filter ........................................................................................................ 16

4.4.2 Full-Bridge Output Filter (Stereo or Parallel) ......................................................................... 18

4.5 Device Protection and Error Reporting .......................................................................................... 19

4.5.1 Over-Current Protection ........................ ................... .... ... ... ... .................... ... ... ... ... ................ 19

4.5.2 Thermal Warning, Thermal Error, and Under-Voltage Error ................................................. 19

5. POWER SUPPLY, GROUNDING, AND PCB LAYOUT ....................................................................... 20

5.1 Power Supply and Grounding ........................................................................................................ 20

5.1.1 Integrated VD Regulator ........................................................................................................ 20

5.2 QFN Thermal Pad .......................................................................................................................... 20

6. PARAMETER DEFINITIONS ................................................................................................................ 21

7. PACKAGE DIMENSIONS .................................................................................................................... 22

8. THERMAL CHARACTERISTICS ......................................................................................................... 23

8.1 Thermal Flag .................................................................................................................................. 23

9. ORDERING INFORMATION ................................................................................................................ 23

10. REVISION HISTORY .......................................................................................................................... 23

LIST OF FIGURES

Figure 1.Stereo Full-Bridge Typical Connection Diagram ........................................................................... 9

Figure 2.2.1 Channel Typical Connection Diagram .................................................................................. 10

Figure 3.4 Channel Half-Bridge Typical Connection Diagram .................................................................. 11

Figure 4.Parallel Full-Bridge Typical Connection Diagram .......... .... ... ... ... ... .... ... ... ................... .... ... ... ... ...12

Figure 5.Output Filter - Half-Bridge ........................................................................................................... 16

Figure 6.Output Filter - Full-Bridge ............................................................................................................ 18

LIST OF TABLES

Table 1. I/O Power Rails.............................................................................................................................. 8

Table 2. Typical Ramp Times for Typical VP Voltages.............................................................................. 13

Table 3. Output Mode Configuration Options... .......................................................................................... 15

Table 4. Low-Pass Filter Components - Half-Bridge.................................................................................. 16

Table 5. DC-Blocking Capacitors Values - Half-Bridge.............................................................................. 17

Table 6. Low-Pass Filter Components - Full-Bridge .................................................................................. 18

Table 7. Over-Current Error Conditions..................................................................................................... 19

Table 8. Thermal and Under-Voltage Error Conditions.............................................................................. 19

Table 9. Power Supply Configuration and Settings.................................................................................... 20

DS786A2 3

CS4412A

1. PIN DESCRIPTION

Pin Name Pin # Pin Description

CNFG0

CNFG1

CNFG2

Out Configuratio n Select (Input) - Used to set the PWM output configuration mode. See “Output

Mode Configuration” on page 15.

IN1

IN2

IN3

IN4

PWM Input (Input) - Logic-level switching inputs from a PWM modulator.

RST12

RST34 8

46 Reset Input (Input) - Reset inputs for channels 1/2 and 3/4, respectively. Active low.

LVD 9VD Voltage Level Indicator (Input) - Identifies the voltage level attached to VD. When applying

5.0 V to VD, LVD must be connected to VD. When applying 2.5 V or 3.3 V to VD, LVD must be

GND.

VD_REG 11 Core Digital Power (Output) - Internally generated low voltage power supply for digital logic.

VD 12 Digita l Power (Input) - Positive power supply for the internal regulators and digital I/O.

OCREF 21 Over-current Reference (Input) - Sets over-current trigger level. Connect pin through a resistor

to GND. See “Device Protection and Error Reporting” on page 19. This pin should not be left float-

ing.

Top-Down (Through Package) View

48-Pin QFN Package

1413 15 16 17 18 19 20 21 22 23 24

4748 46 45 44 43 42 41 40 39 38 37

GND

RST34

RAMP

ERROC34

ERROC12

TWR

GND

CNFG0

CNFG1

CNFG2

IN1

IN2

RST12

OUT1

PGND

OUT2

OUT3

LVD

VD_REG

PGND

OUT4

OCREF

PGND

RAMP_CAP

ERRUVTE

IN3

IN4

GND

Thermal Pad

4DS786A2

CS4412A

RAMP_CAP 24 Output Ramp Capacitor (Input) - Used by the PWM PopGu ard T ransi ent Control to suppress th e

initial pop in half-bridge-configured outputs.

GND

10,13

14,15

16,17

18,19

20,47

Ground (Input) - Ground for the internal logic and I/O. These pins should be connected to the

common system ground.

VP 25,30

31,36 High Voltage Output Power (Input) - High voltage power sup ply for the individual output power

half-bridge devices.

PGND

22,23

27,28

33,34

37,38

39,40

Power Ground (Input) - Ground for the individual output power half-bridge devices. These pins

should be connected to the common system ground.

OUT4

OUT3

OUT2

OUT1

PWM Output (Output) - Amplified PWM power outputs.

TWR 41 Thermal Warning Output (Output) - Thermal warning output. Open drain, active low. See

“Device Protection and Error Reporting” on page 19.

ERRUVTE 42 Thermal and Under-voltage Error Output (Output) - Error flag for thermal shutdown and under-

voltage. Open drain, active low. See “Device Protection and Error Reporting” on page 19

ERROC12

ERROC34 43

44 Over-current Error Output (Output) - Over-current error flag for the associated outputs. Open

drain, active low. See “Device Protection and Erro r Reporting” on page 19.

RAMP 45 Ramp-up/down Sele ct (Input) - Set high to enable ramping. When set low, ramping is disabled.

See “PWM Popguard Transient Control” on page 13.

Thermal Pad -Thermal Pad - Thermal relief pad for optimized heat dissipation. See “QFN Thermal Pad” on

page 20 for more information.

Pin Name Pin # Pin Description

DS786A2 5

CS4412A

2. CHARACTERISTICS AND SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

GND = PGND = 0 V, all voltages with respect to ground.

ABSOLUTE MAXIMUM RATINGS

GND = PGND = 0 V; all voltages with respect to ground.

WARNING:Operation beyond these limits may result in permanent damage to the device. Normal operation is not

guaranteed at these extremes.

Notes: 1. Any pin except supplies. Transient currents of up to ±100 mA on the PWM input pins will not cause

SCR latch-up.

2. The maximum over/under voltage is limited by the input current.

Parameters Symbol Min Nom Max Units

DC Power Supply

Digital Core VD 2.375 2.5 2.625 V

VD 3.135 3.3 3.465 V

VD 4.75 5.0 5.25 V

Power Stage VP 8.0 18.0 V

Temperature

Ambient Temperature Commercial TA-10 - +70 °C

Junction Temperature TJ-10 - +125 °C

Parameters Symbol Min Max Units

DC Power Supply

Power St age Outputs Switching and Under Load

Power Stage No Output Switching

Digital Core

-0.3

19.8

23.0

6.0

Inputs

Input Current (Note 1)I

in -±10mA

Digital Input Voltage (Note 2)V

IND -0.3 VD + 0.4 V

Temperature

Ambient Operating Temper ature - Power Applied Commercial TA-20 +85 °C

Storage Temperature Tstg -65 +150 °C

6DS786A2

CS4412A

PWM POWER OUTPUT CHARACTERISTICS

Test Conditions (unless otherwise specified): GND = PGND = 0 V; All voltages with respect to ground; TA= 25°C;

VD = 3.3 V; VP = 18 V; RL=8Ω for full-bridge, RL=4Ω for half-bridge and parallel full- bridge; PWM Switch

Rate = 384 kHz; 10 Hz to 20 kHz Measurement Bandwidth; Input source is CS4525 PWM_SIG outputs; Perfor-

mance measurements taken with a full-scale 997 Hz sine wave, an AES17 measurement filter; Half-Bridge mea-

surements taken through the Half-Bridg e Output Filter shown in Figure 5; Stereo Full-Bridge and Parallel Full-

Bridge measure m en ts take n th ro ug h th e Full- Brid ge Out pu t Filt er sho wn in Figure 6;.

Parameters Symbol Conditions Min Typ Max Units

Power Output per Channel Stereo Full-Bridge

Half-Bridge

Parallel Full-Bridge

THD+N < 10%

THD+N < 1%

THD+N < 10%

THD+N < 1%

THD+N < 10%

THD+N < 1%

7.5

5.5

23.5

Total Harmonic Distortion + Noise

Stereo Full-Bridge

Half-Bridge

Parallel Full-Bridge

THD+N

PO = 1 W

PO = 0 dBFS = 11.3 W

PO = 1 W

PO = 0 dBFS = 5.0 W

PO = 1 W

PO = 0 dBFS = 22.6 W

0.08

0.10

0.12

0.19

0.1

0.3

Dynamic Range Stereo Full-Bridge

Half-Bridge

Parallel Full-Bridge

DYR

PO = -60 dBFS, A-Weighted

PO = -60 dBFS, Unweighted

PO = -60 dBFS, A-Weighted

PO = -60 dBFS, Unweighted

PO = -60 dBFS, A-Weighted

PO = -60 dBFS, Unweighted

102

MOSFET On Resistance RDS(ON) Id= 0.5 A, TJ=50°C - 280 - mΩ

Efficiency h PO = 2 x 15 W, RL = 8 Ω-85-%

Minimum Output Pulse Width PWmin No Load - 25 - ns

Rise Time of OUTx trResistive Load - 10 - ns

Fall Time of OUTx tfResistive Load - 5 - ns

PWM Output Over-Current Error Trigger Point ICE

TA=25°C, OCREF = 16.2 kΩ

TA=25°C, OCREF = 18 kΩ

TA=25°C, OCREF = 22 kΩ

2.5

2.1

1.7

Junction Thermal Warning Trigger Point TTW - 105 - °C

Junction Thermal Error Trigger Point TTE - 125 - °C

VP Under-Voltage Error Falling Trigger Point VUVFALL TA=25°C-4.74.9V

VP Under-Voltage Error Rising Trigger Point VUVRISE TA=25°C - 4.95 5.4 V

DS786A2 7

CS4412A

DC ELECTRICAL CHARACTERISTICS

GND = PGND = 0 V; All voltages with respect to gr ound; PWM switch rate = 384 kHz; Unless otherwise specified.

Notes: 3. Normal operation is defined as RST12 and RST34 = HI.

4. Power-Down Mode is defined as RST12 and RST 34 = LOW with all input lines held static.

5. Power supply current increases with increasing PWM switching rates.

DIGITAL INTERFACE SPECIFICATIONS

GND = PGND = 0 V; All voltages with respect to gr ound; Unless otherwise specified.

Parameters Min Typ Max Units

Normal Operation (Notes 3, 5)

Power Supply Current VD = 3.3 V - 20 - mA

Power Dissipation VD = 3.3 V - 66 - mW

Power-Down Mode (Note 4)

Power Supply Current VD = 3 .3 V - 2 - mA

VD_REG Characteristics

Nominal Voltage

DC current source 2.25

-2.5

-2.75

Parameters Symbol Min Max Units

High-Level Input Voltage VIH 0.7*VD_REG VD V

Low-Level Input Voltage VIL - 0.20*VD_REG V

High-Level Output Voltage Io=2mA VOH 0.90*VD - V

Input Leakage Current Iin -±10µA

Input Capacitance - 8 pF

8DS786A2

CS4412A

DIGITAL I/O PIN CHARACTERISTICS

The logic level for each input is set by its corresponding powe r supply and should not exceed the maximum ratings.

Power

Supply Pin

Number Pin Name I/O Driver Receiver

VD 1 CNFG0 Input - 2.5 V - 5.0 V

2 CNFG1 Input - 2.5 V- 5.0 V

3 CNFG2 Input - 2.5 V- 5.0 V

4 IN1 Input - 2.5 V- 5.0 V

5 IN2 Input - 2.5 V- 5.0 V

6 IN3 Input - 2.5 V- 5.0 V

7IN4 Input - 2.5 V- 5.0 V

8RST12Input - 2.5 V - 5.0 V

9 LVD Input - 2.5 V- 5.0 V

41 TWR Output 2.5 V- 5.0 V, Open Drain -

42 ERRUVTE Output 2.5 V - 5.0 V, Open Drain -

43 ERROC12 Output 2.5 V - 5.0 V, Open Drain -

44 ERROC34 Output 2.5 V - 5.0 V, Open Drain -

45 RAMP Input - 2.5 V - 5.0 V

46 RST34 Input - 2.5 V- 5.0 V

VP 35 OUT1 Output 8 V - 18 V Power MOSFET -

32 OUT2 Output 8 V - 18 V Power MOSFET -

29 OUT3 Output 8 V - 18 V Power MOSFET -

26 OUT4 Output 8 V - 18 V Power MOSFET -

Table 1. I/O Power Rails

DS786A2 9

CS4412A

3. TYPICAL CONNECTION DIAGRAMS

313025

0.1 µF10 µF

+3.3 V or +5.0 V

IN1

7IN4

IN2

IN3

RAMP_CAP

Ch1_PWM

Ch2_PWM

OUT1 35

OUT2 32

OUT3 29

OUT4 26

RAMP

CNFG2

CNFG1

CNFG0

LVD

System

Control

Logic

43 ERROC12

ERROC34

ERRUVTE

TWR

RST12

46 RST34

22 kΩ

470 µF 0.1 µF 0.1 µF 0.1 µF 0.1 µF 470 µF +8 V to +18 V

22 28 34 37 38 39 4033

PGND

GND 13

GND 16

GND 17

GND 14

GND 15

VD_REG

0.1 µF10 µF

OCREF

16.2 k

GND 18

GND 19

GND 47

GND 48

PGND

GND 20

Thermal Pad

GND 10

Full-Bridge

Output Filter

Channel 2

Audio

Output

Full-Bridge

Output Filter

Channel 1

Audio

Output

* Since ramping is disabled for full-

bridge applications, this capacitor

can be omitted and RAMP_CAP can

be connected directly to VP.

Ω

Connect LVD to :

VD if VD = 5 V

GND if VD = 3.3 V

Figure 1. Stereo Full-Bridge Typical Connection Diagram

CS4412A

See Section 5.1.1

for details.

See Section 4.2.1 for details.

See Figure 6.

10 DS786A2

CS4412A

313025

0.1 µF

10 µF

+3.3 V or +5.0 V

IN1

7IN4

IN2

IN3

RAMP_CAP

Ch1_PWM

Ch2_PWM

Ch3_PWM

OUT3 29

OUT4 26

OUT1 35

OUT2 32

System

Control

Logic

43 ERROC12

ERROC34

ERRUVTE

TWR

RST12

46 RST34

22 kΩ

RAMP

CNFG2

CNFG1

CNFG0

LVD

Full-Bridge

Output Filter

Half-Bridge

Output Filter

Half-Bridge

Output Filter

470 µF 0.1 µF 0.1 µF 0.1 µF 0.1 µF

33 nF

470 µF +8 V to +18 V

22 28 34 37 38 39 4033

PGND

GND 13

GND 16

GND 17

GND 14

GND 15

VD_REG

0.1 µF10 µF

OCREF

16.2 k

GND 18

GND 19

GND 47

GND 48

PGND

GND 20

Thermal Pad

GND 10

Channel 2

Audio

Output

Channel 1

Audio

Output

Channel 3

Audio

Output

Ω

Connect LVD to :

VD if VD = 5 V

GND if VD = 3.3 V

Figure 2. 2.1 Channel Typical Connection Diagram

CS4412A

See Section 5.1.1

for details.

See Figure 6.

See Figure 5.

DS786A2 11

CS4412A

313025

0.1 µF

10 µF

+3.3 V or +5.0 V

22 28 34 37 38 39 4033

PGND

IN1

GND 13

GND 16

GND 17

GND 14

GND 15

VD_REG

0.1 µF10 µF

7IN4

IN2

IN3

RAMP_CAP

OCREF

16.2 k

GND 18

GND 19

GND 47

GND 48

PGND

GND 20

Ch1_PWM

Ch2_PWM

Ch3_PWM

Ch4_PWM

OUT1 35

OUT2 32

OUT3 29

OUT4 26

RAMP

CNFG2

CNFG1

CNFG0

LVD

System

Control

Logic

43 ERROC12

ERROC34

ERRUVTE

TWR

RST12

46 RST34

22 kΩ

Half-Bridge

Output Filter

Half-Bridge

Output Filter

Half-Bridge

Output Filter

Half-Bridge

Output Filter

470 µF 0.1 µF 0.1 µF 0.1 µF 0.1 µF

33 nF

470 µF +8 V to +18 V

Thermal Pad

GND 10

Channel 1

Audio

Output

Channel 2

Audio

Output

Channel 3

Audio

Output

Channel 4

Audio

Output

Ω

Connect LVD to :

VD if VD = 5 V

GND if VD = 3.3 V

Figure 3. 4 Channel Half-Bridge Ty pical Connection Diagram

CS4412A See Figure 5.

See Figure 5.

See Section 5.1.1

for details.

12 DS786A2

CS4412A

+8 V to +18 V

313025

470 µF 0.1 µF 0.1 µF 0.1 µF 0.1 µF

0.1 µF

10 µF

+3.3 V or +5.0 V

IN1

7IN4

IN2

IN3

RAMP_CAP

PWM

OUT1 35

OUT2 32

System

Control

Logic

43 ERROC12

ERROC34

ERRUVTE

TWR

RST12

46 RST34

22 kΩ

RAMP

CNFG2

CNFG1

CNFG0

LVD

470 µF

22 28 34 37 38 39 4033

PGND

VD_REG

0.1 µF10 µF

OCREF

16.2 k

PGND

Thermal Pad

* Since ramping is disabled for full-

bridge applicat ions , this capacitor

can be omitted and RAMP_CAP can

be connected directly to VP.

Full-Bridge

Output Filter Audio

Output

Ω

Connect LVD to :

VD if VD = 5 V

GND if VD = 3.3 V

GND 13

GND 16

GND 17

GND 14

GND 15

GND 18

GND 19

GND 47

GND 48

GND 20

GND 10

OUT3 29

OUT4 26

See Section 4.2.1 for details.

CS4412A

See Figure 6.

See Section 5.1.1

for details.

Figure 4. Parallel Full-Bridge Typical Connection Diagram

DS786A2 13

CS4412A

4. APPLICATIONS

4.1 Overview

The CS4412A is a high-efficiency power stage for digital Class-D amplifiers designed to be configured as

four half-bridge channels, two half-bridge channels an d one full-bridge channel, two full- bridge channels, or

one parallel full-bridge channel.

The CS4412A inte grates on-chip over-curre nt, under-voltage, over-temper ature protection and error report-

ing as well as a thermal warning indicator. The low RDS(ON) outputs can source up to 2.5 A peak current,

delivering 85% efficiency. This efficiency provides for a smaller device package, smaller power supplies,

and no external heat sink.

4.2 Reset and Power-Up

Reliable power-up can be accomplished b y keeping the de vice in reset un til the power supplies and config-

uration pins are stable. It is also recommended that the RST12 and RST34 pins be activated if the voltage

supplies drop below the recomme nded operating condition to prevent power-glitch related issues.

When the RST12 or RST34 are low, the corresp onding channe ls of the CS44 12A enter a lo w-power mode.

All of the channels’ internal states are reset, and the corresponding power output pins are held in a high-

impedance state. When RST12 or RST34 are high, th e corres pondin g outpu ts begin n ormal op eration ac-

cording to the RAMP, CNFG[2:0], and IN1 - IN4 pins.

4.2.1 PWM Popguard Transient Control

The CS4412A uses PWM Pop guard technology to minimize the effects of output tr ansients during power-

up and power-down for half-b ridge configurations. This technique re duces the audio transients commo nly

produced by half-bridge, single-supply amplifiers when implemented with external DC-blocking capacitors

connected in series with the audio outputs.

WARNING:The Pop guard feature can not be used for the CS4412A in applica tions where VP exceeds 12 V. Doing

so could result in permanent damage to the CS4412A. The RAMP pin must always be tied low in ap-

plications where VP exceeds 12 V.

When the device is configured for ramping (RAMP set high) and RST12 or RST34 is set high, the corre-

sponding power outputs will ramp-up to the bias point (VP/2). This gradual voltage ramping allows time

for the extern al DC-block ing capac itor to charge to the quiescent voltage, minimizing the power-up tran-

sient. The corresponding outputs will not begin normal operation until the ramp has reached the bias point.

The time it takes to complete a ramp-up sequence will vary slightly from the applied VP voltage; typical

ramp-up speeds achieved with a 1000 µF DC blocking capacitor are listed in Table 2. These times scale

with the value of the capa cito r.

VP Voltage Typical Ramp Time*

8 V 2.20 seconds

12 V 1.25 seconds

* With 1000 µF DC Blocking Capacitor.

Table 2. Typical Ramp Times for Typical VP Voltages

14 DS786A2

CS4412A

When the device is configured for ramping (RAMP set high) and RST12 or RST34 is set low, the corre-

sponding outputs will begin to slowly ramp down from the bias point to PG ND, allowing the DC-blocking

capacitor to discharge.

The ramp feature is intended for use with half-bridge outputs. For “2.1 channel” applications with stereo

half-bridge and mono full-bridge (CNFG[2:0] = 001 or 101), the ramp will only be applied to OUT1 and

OUT2 (the half-bridge channels); OUT3 and OUT4 (the full-bridge channel) will not ramp.

The ramp feat ure requires a 33 nF capacitor on the RAMP_ CAP pin to VP. For application s that do not

enable the ramping feature, RAMP_CAP can be connected directly to VP.

It is not necessary to complete a ramp-up/down sequence before ramping up/down again.

4.2.2 Initial Pulse Edge Delay

After RST12 or RST34 is released, th e CS4412A continues to hold the corresponding power output pins

in a high-impedance state until a pulse edge is sensed on a corresponding PWM input pin. This is done

to prevent a possible DC output condition on the speakers if the PWM inputs are not yet modulating im-

mediately following the release of the corresponding reset signal. This initial transition delay is indepen-

dent for each input/output pin pair; each output corresponding to an inactive input will remain in a high-

impedance state until its input receives a pulse edge even if other inputs are activated. The pulse edge

must be from a digital low state to a digital high state. Once a pulse edge is detected, the corresponding

output pin will activate and switch as dictated by the output mode configuration described in Section 4.3

on page 15 until either an error condition is detected or until its reset pin is set low.

If the outputs are configured for ramping, the CS4412A will perform a ramp-up sequence on OUT1/2 im-

mediately following the release of RST12 and a ramp sequence on OUT3/4 immediately followin g the re-

lease of RST34. See Section 4.2.1 on page 13 for more inform ation on outpu t rampin g. If a pulse ed ge is

detected on an in put before the ramp-up sequen ce finishes on its corresponding outpu t pin, the CS4412A

continues the ramp sequence and begins normal output operation immediately following its completion.

If a pulse edge is not detected on an input by the time the ramp-up sequence has finished on its corre-

sponding output pin, the output pin is placed into and remains in a high-impedance state until a pulse edge

is detected on the corresponding input.

4.2.3 Recommended Power-Up Sequence

1. Turn on the system power.

2. Hold RST1 2 and RST34 low until the power supply is stable. In this state, all associated outputs are

held in a high-impedance state.

3. Release RST12 and RST34 high.

4. Start the PWM modu lator output.

4.2.4 Recommended Power-Down Sequence

1. Mute the logic-level PWM inputs present on IN1 - IN4 by applying 50% duty-cycle input signals.

2. Hold RST12 and RST34 low.

3. Power down the remainder of the system.

DS786A2 15

CS4412A

4.3 Output Mode Configuration

Each OUTx pin will switch in association with the corresponding INx pin. For most configurations, OUTx will

be non-inverted from INx; however, some INx pins can be configured for internal inversion to allow one

PWM input to drive both the positive and negative sides of a full-bridge output. Unused OUTx pins must

have their correspondin g INx pin tied to ground.

Table 3 shows the setting of the CNFG[2:0] inputs and the corresponding mode of operation. These pins

should remain static during operation (RST12 or RST34 set high).

In Stereo Half-Br idge and Mono Full-Bridge configu rations, the PWM Popguard Transient Control only af-

fects the two half-bridge outputs, OUT1 and OUT2. The full-bridge output will not ramp regardless of the

state of the RAMP pin. See Section 4.2.1 on pa ge 13 for more deta ils about PWM Popguard Transient Con-

trol.

CNFG2 CNFG1 CNFG0 Description Necessary Input Connections

000

Stereo Full-Bridge

Tied Loads

IN1 must provide the PWM data for the first full-bridge.

IN2 must be inverted from IN1 for full-bridge operation.

IN3 must provide the PWM data for the second full-bridge.

IN4 must be inverted from IN3 for full-bridge operation.

001

S tereo Half-Bridge

& Mono Full-Bridge

Tied Loads*

IN1 must provide the PWM data for the first half-bridge.

IN2 must provide the PWM data for the second half-bridge.

IN3 must provide the PWM data for the mono full-bridge.

IN4 must be inverted from IN3 for full-bridge operation.

010

Mono Parallel Full-

Bridge Tied Load

IN1 must provide the PWM data for the mono full-bridge.

IN2 must be wired directly to IN1 for parallel full-bridge operation.

IN3 must be inverted from IN1 for parallel full-bridge operation.

IN4 must be wired to IN3 for parallel full-bridge operation.

011

Quad Half-Bridge

Tied Loads

IN1 must provide the PWM data for the first half-bridge.

IN2 must provide the PWM data for the second half-bridge.

IN3 must provide the PWM data for the third half-bridge.

IN4 must provide the PWM data for the fourth half-bridge.

100

Stereo Full-Bridge

Tied Loads

With Inversion

IN1 must provide the PWM data for the first full-bridge.

IN2 must be wired to IN1; the CS4412A will internally invert IN2.

IN3 must provide the PWM data for the second full-bridge.

IN4 must be wired to IN3; the CS4412A will internally invert IN4.

101

S tereo Half-Bridge

& Mono Full-Bridge

Tied Loads

With Inversion*

IN1 must provide the PWM data for the first half-bridge.

IN2 must provide the PWM data for the second half-bridge.

IN3 must provide the PWM data for the mono full-bridge.

IN4 must be wired to IN3; the CS4412A will internally invert IN4.

110

Mono Parallel Full-

Bridge Tied Load

With Inversion

IN1 must be provided for half-bridge operati on.

IN2 must be wired to IN1 for parallel full-bridge operation.

IN3 must be wired to IN1; the CS4412A will internally invert IN3.

IN4 must be wired to IN1; the CS4412A will internally invert IN4.

1 1 1 Reserved The input connections are not applicable.

* PWM Popguard Transient Control only affects OUT1 and OUT2.

Table 3. Output Mode Configuration Options

16 DS786A2

CS4412A

4.4 Output Filters

The filter placed after the PWM outputs can greatly affect the output performance. The filter not only reduces

radiated EMI (snubber filter) but also filters high frequency content from the switching output before going

to the speaker (low-pass LC filter).

4.4.1 Half-Bridge Output Filter

Figure 5 shows the output filter for a half-bridge configuration. The transient-voltage suppression circuit

(snubber circuit) is compr ised of a capacitors (680 pF) and a resistor (5.6 Ω, 1/8 W) and should be placed

as close as possible to the corresponding PWM output pin to greatly reduce radiated EMI.

Each output pin must be connected to two Schottky diodes—one to ground and one to the VP supply.

These diodes should be placed within 12 mm of the corresponding OUTx pin. The requirements of this

diode are:

1. Rated IF (average rectifier forward current) is greater than or equ al to 1.0 A.

2. Support up to 8 0°C o f lead temp er ature with V F dro p (forward voltage ) less than or equal to 480 mV

at the correspondin g IF.

3. VR (reverse voltage) is greater than or equal to 20 V.

The inductor, L1, and capacitor, C1, compr ise the low-pass filter. Along with the no minal load impedance

of the speake r, these values set the cut-off frequency of the filter. Table 4 shows the component values

for L1 and C1 based on nominal speaker (load) imped ance for a corner frequency (- 3 dB point) of approx-

imately 35 kHz.

Load L1 C1

4Ω22 µH 1.0 µF

6Ω33 µH 0.68 µF

8Ω47 µH 0.47 µF

Table 4. Low-Pass Filter Components - Half-Bridge

OUTx

680 pF C1

5.6 Ω

L1 C2

*Diode is Rohm

RB160M-30 or

equivalent

Figure 5. Output Filter - Half-Bridge

DS786A2 17

CS4412A

C2 is the DC-blocking capacitor. Table 5 shows the comp onent values fo r C2 ba sed on corne r frequency

(-3 dB point) and a nominal speaker (load) impedances of 4 Ω, 6Ω, and 8Ω. This capacitor should also

be chosen to have a ripple current rating above the amount of current that will passed through it.

Load Corner Frequency C2

4Ω40 Hz 1000 µF

58 Hz 680 µF

120 Hz 330 µF

6Ω39 Hz 680 µF

68 Hz 390 µF

120 Hz 220 µF

8Ω42 Hz 470 µF

60 Hz 330 µF

110 Hz 180 µF

Table 5. DC-Blocking Capacitors Values - Half-Bridge

18 DS786A2

CS4412A

4.4.2 Full-Bridge Output Filter (Stereo or Parallel)

Figure 6 shows the output filter for a full-bridge configuration. The transient-voltage suppression circuit

(snubber circuit) is com prised of a capacitor (680 pF) and a resistor (5.6 Ω) on each output pin and should

be placed as close as possible to the corresponding PWM output pins to grea tly reduce radiated EMI. The

inductors, L1 and L2, and capacito r, C1, comprise the l ow-pass filter. Along with the nominal load impe d-

ance of the speake r, these values set the cutoff frequen cy of the filter. Table 6 shows the component val-

ues based on nominal speaker (load) impedance for a corner frequency (-3 dB point) of approximately

35 kHz.

Each output pin must be connected to two Schottky diodes—one to ground and one to the VP supply.

These diodes should be placed within 12 mm of the corresponding OUTx pin. The requirements of this

diode are:

1. Rated IF (average rectifier forward current) is greater than or equ al to 1.0 A.

2. Support up to 8 0°C o f lead temp er ature with V F dro p (forward voltage ) less than or equal to 480 mV

at the correspondin g IF.

3. VR (reverse voltage) is greater than or equal to 20 V.

Load L1, L2 C1

4Ω10 µH 1.0 µF

6Ω15 µH 0.47 µF

8Ω22 µH 0.47 µF

Table 6. Low-Pass Filter Components - Full-Bridge

Figure 6. Output Filter - Ful l-Bridg e

OUTX+

OUTX-

*Diode is Rohm

RB160M-30 or

equivalent

680 pF

5.6 Ω

680 pF

5.6 Ω

DS786A2 19

CS4412A

4.5 Device Protection and Error Reporting

The CS4412A has built-in protection circuitry for over-current, under-voltage, and thermal warning/over-

load conditions. The levels of the over-current error, thermal error, and VP under-voltage trigger points

are listed in the PWM Power Output Characteristics table on page 6. Automatic sh ut-down occu rs when-

ever any of these preset thresholds, other than thermal warning, are crossed.

Each error and warning pin implements an active-low open-drain driver and requires an external 22 kΩ

pull-up resistor for proper operation.

4.5.1 Over-Current Protection

An over-current error condition occurs if the peak output current exceeds the Over-Current Error trigger

point. Over-current errors for OUT1/2 and OUT3/4 are reported on the ERROC12 and ERROC34 pins,

respectively. The power output of the channel that is reporting the over-current condition will be set to

high-impedance un til the error condition has been removed and the reset signal for that channel has been

toggled from low to high.

4.5.2 Thermal Warning, Thermal Error, and Under-Voltage Error

Table 8 shows the behavior of the TWR an d ERRUVTE pins. When the junction temperature exceeds the

junction thermal warning trigger point, the TWR pin is set low. If the junction temperature continues to in-

crease beyond the junction thermal er ror trigger poin t, the ERRUVTE pin will be set low. If the voltage on

VP falls below the VP under-voltage error trigger point, ERRUVTE will be set low.

When the thermal error or VP under-voltage trigger point is crossed, all power outputs will be set in a high-

impedance state un til the error condition has been removed and both the RST12 and RST34 signals have

been toggled from low to hig h.

ERROCxy Reported Condition

0 Over-current error on channel x or channel y

1 Operating current of channel x and y within allowable limits

Table 7. Over-Current Error Conditions

TWR ERRUVTE Reported Condition

0 0 Thermal warning and thermal error and/or under-voltage error

0 1 Thermal warning only

1 0 Under-voltage error

1 1 Junction temp erature and VP voltage within normal limits

Table 8. Thermal and Und er -Voltage Erro r Con ditions

20 DS786A2

CS4412A

5. POWER SUPPLY, GROUNDING, AND PCB LAYOUT

5.1 Power Supply and Grounding

The CS4412A requires careful attention to power supply and gro unding arrangemen ts if its potentia l perfor-

mance is to be realized.

Extensive use of power and ground planes, ground plane fill in unused areas, and surface mount decoupling

capacitors are recommended. It is necessary to decouple the power supply b y placing capacitors directly

between the power and ground of the CS4412A. Decoupling capacitors should be as c lose to the pins of

the CS4412A as possible. The lowest value ceramic capacitor should be closest to the pin and should be

mounted on the same side of the board as the CS4412A to minimize inductance effects. The CRD4412A

reference design demonstrates the optimum layout and power supply arrangements.

5.1.1 Integrated VD Regulator

The CS4412A includes an inte rnal linear regulator to provide a fixed 2.5 V su pply from the VD supply volt-

age for its internal digital logic. The LVD pin must be set to indicate the voltage present on the VD pin as

shown in Table 9 below.

Table 9. Power Supply Configuration and Settings

The output of the di gital regulator is p resented on the VD_ REG pin and may be used to provide a n exter-

nal device with up to 3mA of current at its nominal outpu t voltage of 2.5 V.

If a nominal supply voltage of 2.5 V is used as th e VD supply (see the Recommended Operating Condi-

tions table on page 5), the VD and VD_REG must be con nected to the VD supply source . In this config-

uration, the internal regulator is bypassed and the external supply source is used to directly drive the

internal digital logic.

5.2 QFN Thermal Pad

The CS4412A is available in a compact QFN package. The underside of th e QFN package reveal s a large

metal pad that serves as a thermal relief to provide for ma ximum he at dissipa tion. This pad must mate with

an equally dimensioned copper pad on the PCB and must be electrically connected to ground. A series of

thermal vias should be used to co nnect this cop per pad to one or more la rg er g round pla nes on other PCB

layers; the copper in these ground planes will act as a heat sink for the CS4412A. The CRD4412A reference

design demonstrates the optimum thermal pad and via configuration.

VD Connection VD_REG Conne ction LVD Connection

5 V Supply Bypass Capacitors Only VD

3.3 V Supply Bypass Capacitors Only GND

2.5 V Supply VD and Bypass Capacitors GND

DS786A2 21

CS4412A

6. PARAMETER DEFINITIONS

Dynamic Range (DYR)

The ratio of the rms valu e of th e signa l to th e rms sum o f all ot her sp ectral c ompon ents ove r the specified

bandwidth, typically 20 Hz to 20 kHz. Dynamic Range is a signa l-to-noise ratio measurement over the spec-

ified band w idth mad e with a -60 dBFS signal; then , 60 dB is added to the resulting measurement to refer

the measurement to full-scale. This technique ensures that the distortion components are below the noise

level and do not effect the measurement. This measurement technique has been accepted by the Audio

Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Ex-

pressed in decib els .

Total Harmonic Distortion + Noise (THD+N)

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified

band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured

at -1 and -20 dBFS as suggested in AES17-1991 Annex A.

22 DS786A2

CS4412A

7. PACKAGE DIMENSIONS

Notes: 1. Dimensioning and tolerance per ASME Y4.5M - 19 94.

2. Dimensioning lead width applies to the plated terminal and is measured between 0.20 mm and

0.25 mm from the terminal tip.

INCHES MILLIMETERS NOTE

DIM MIN NOM MAX MIN NOM MAX

A -- -- 0.0354 -- -- 0.90 1

A1 0.0000 -- 0.0020 0.00 -- 0.05 1

b 0.0118 0.0138 0.0157 0.30 0.35 0.40 1,2

D 0.3543 BSC 9.00 BSC 1

D2 0.2618 0.2677 0.2736 6.65 6.80 6.95 1

E 0.3543 BSC 9.00 BSC 1

E2 0.2618 0.2677 0.2736 6.65 6.80 6.95 1

e 0.0256 BSC 0.65 BSC 1

L 0.0177 0.0217 0.0276 0.45 0.55 0.70 1

JEDEC #: MO-220

Controlling Dimension is Millimeters.

Side View

Bottom View

Top View

Pin #1 ID

bePin #1 ID

48L QFN (9 × 9 MM BODY) PACKAGE DRAWING

DS786A2 23

CS4412A

8. THERMAL CHARACTERISTICS

8.1 Thermal Flag

This device is designed to have the metal flag on the bottom of the device soldered directly to a metal plane

on the PCB. To enhance the thermal dissipation capabilities of the system, this metal plane should be cou-

pled with vias to a large metal plane on the backside (and inner ground layer , if applicable) of the PCB.

In either case, it is beneficial to use copper fill in any unused regions inside the PCB layout, especially those

immediately surrounding the CS4412 A. In addition to improving in electrical performance, this practice also

aids in heat dissipation.

The heat dissipation capability required of the metal plane for a given output power can be calculated as

follows:

θCA = [(TJ(MAX) - TA) / PD] - θJC

where,

θCA = Thermal resistance of the metal plane in °C/Watt

TJ(MAX) = Maximum rated operating junction temperature in °C, equal to 150°C

TA = Ambient temperature in °C

PD = RMS power dissipation of the device, equal to 0.15*PIN,RMS or 0.177*POUT,RMS (assuming 85% effi-

ciency)

θJC = Junction-to-c ase thermal resista n ce of the device in °C/Watt

9. ORDERING INFORMATION

10.REVISION HISTORY

Parameter Symbol Min Typ Max Units

Junction to Case Thermal Impedance θJC -1-°C/Watt

Product Description Package Pb-Free Grade Temp Range Container Order#

CS4412A 30 W Quad Half-Bridge

Digital Amplifier

Power Stage 48-QFN Yes Commercial -10°C to +70°C Rail CS4412A-CNZ

Tape and

Reel CS4412A-CNZR

CRD4412A 4 Layer / 3oz. Copper

Reference Design

Daughter Card - - - - - CRD4412A

CRD4525-Q1 4 Layer / 1oz. Copper

Reference Design

Main Board - - - - - CRD4525-Q1

Release Changes

A1 Initial Release

The following item s were update:

“PWM Power Output Characteristics” on page 6

Section 4.4.1 “Half-Bridge Output Filter” on page 16

Section 4.4.2 “Full-Bridge Output Filter (Stereo or Parallel)” on page 18

Section 8.1 “Thermal Flag” on page 23

Section 9. “Ordering Information” on page 23

24 DS786A2

CS4412A

Contacting Cirrus Logic Support

For all product questions and inquiries, contact a Cirrus Logic Sales Representative.

To find one nearest you, go to www.cirrus.com.

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