LMH6672MR/NOPB - NATIONAL SEMICONDUCTOR

Note: Supply and Bypassing not shown.

1/2

LMH6672

Rf1

VIN

Rf2

1/2

LMH6672

AVVIN

12.5

1:N

(1.2)

12.5

(VPP)Rg VOUT

RL = 100:

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LMH6672

SNOS957H –APRIL 2001–REVISED AUGUST 2014

LMH6672 Dual, High Output Current, High Speed Op Amp

1 Features 2 Applications

1•High Output Drive • ADSL PCI Modem Cards

• xDSL External Modems

– 19.2 VPP Differential Output Voltage,

RL= 50 Ω• Line Drivers

– 9.6 VPP Single-ended Output Voltage, 3 Description

RL= 25 ΩThe LMH6672 is a low cost, dual high speed op amp

•High Output Current capable of driving signals to within 1 V of the power

– ±200 mA @ VO=9VPP, VS= 12 V supply rails. It features the high output drive with low

•Low Distortion distortion required for the demanding application of a

single supply xDSL line driver.

– 105 dB SFDR @ 100 kHz, VO= 8.4 VPP,

RL= 25ΩWhen connected as a differential output driver, the

– 98 dB SFDR @ 1MHz, VO=2VPP,LMH6672 can drive a 50-Ωload to 16.8 VPP swing

RL= 100 Ωwith only −98 dBc distortion, fully supporting the peak

upstream power levels for upstream full-rate ADSL.

•High Speed The LMH6672 is fully specified for operation with 5-V

– 90 MHz 3 dB Bandwidth (G = 2) and 12-V supplies. Ideal for PCI modem cards and

– 135 V/µs Slew Rate xDSL modems.

•Low Noise Device Information(1)

– 3.1 nV/√Hz: Input Noise Voltage PART NUMBER PACKAGE BODY SIZE (NOM)

– 1.8 pA/√Hz: Input Noise Current LMH6672 SOIC (8) 4.89 mm × 3.90 mm

• Low Supply Current: 7.2mA/amp (1) For all available packages, see the orderable addendum at

• Single-supply Operation: 5 V to 12 V the end of the datasheet.

• Stable for Gain of +2V/V or Higher

• Available in 8-pin SOIC and SO PowerPAD (DDA)

Typical Application

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LMH6672

SNOS957H –APRIL 2001–REVISED AUGUST 2014

www.ti.com

Table of Contents

6.6 ±2.5V Electrical Characteristics ................................ 6

1 Features.................................................................. 16.7 Typical Performance Characteristics ........................ 7

2 Applications ........................................................... 17 Detailed Description............................................ 15

3 Description............................................................. 17.1 Functional Block Diagram....................................... 15

4 Revision History..................................................... 28 Power Supply Recommendations...................... 16

5 Pin Configuration and Functions......................... 38.1 Thermal Management............................................. 16

6 Specifications......................................................... 49 Device and Documentation Support.................. 18

6.1 Absolute Maximum Ratings ...................................... 49.1 Trademarks............................................................. 18

6.2 Handling Ratings....................................................... 49.2 Electrostatic Discharge Caution.............................. 18

6.3 Recommended Operating Conditions....................... 49.3 Glossary.................................................................. 18

6.4 Thermal Information.................................................. 410 Mechanical, Packaging, and Orderable

6.5 Electrical Characteristics........................................... 5Information ........................................................... 18

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision G (March 2013) to Revision H Page

• Changed data sheet flow and layout to conform with new TI standards. Added the following sections: Device

Information Table, Application and Implementation; Device and Documentation Support; Mechanical, Packaging,

and Ordering Information ....................................................................................................................................................... 1

• Added "Stable for Gain of +2V/V or Higher" in Features ....................................................................................................... 1

• Changed from "Junction Temperature Range" to "Operating Temperature Range" in Recommended Operating

Conditions............................................................................................................................................................................... 4

• Deleted TJ= 25°C in Electrical Characteristics...................................................................................................................... 5

• Deleted TJ= 25°C and "Slew Rate" in ±2.5V Electrical Characteristics................................................................................. 6

• Added condition "Av = + 2V/V" in Typical Performance Characteristics................................................................................ 7

• Added "Vs= +/-2.5V" and "Vs=+/-6V" as curve labels for Figure 36.................................................................................... 11

• Changed curve label from 31 MHz to 13 MHz. Changed title from +5V to +5V/V in Figure 37........................................... 12

• Changed "10V" to + "10V/V" in caption title for Figure 38.................................................................................................... 12

• Added "Vs = 12V" to Figure 39 caption title......................................................................................................................... 13

• Added "Vs = 5V" to Figure 40 caption title........................................................................................................................... 13

• Changed from "40 = 346 mW" to "40 mW lower or 346 mW" in Thermal Management...................................................... 17

• Changed from 41 mW to 17 mW.......................................................................................................................................... 17

• Added "from ambient"........................................................................................................................................................... 17

• Changed sentence beginning with "Using the same PDRIVER as above..." ........................................................................... 17

• Added caution note............................................................................................................................................................... 17

Changes from Revision F (March 2013) to Revision G Page

• Changed layout of National Data Sheet to TI format ........................................................................................................... 17

Product Folder Links: LMH6672

OUT B

4 5

OUT A

-IN A

+IN A

V-

V+

-IN B

+IN B

LMH6672

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SNOS957H –APRIL 2001–REVISED AUGUST 2014

5 Pin Configuration and Functions

8-Pin

SOIC (D) / SO PowerPAD (DDA)

(Top View)

Pin Functions

PIN I/O DESCRIPTION

NUMBER NAME

1 OUT A O ChA Output

2 -IN A I ChA Inverting Input

3 +IN A I ChA Non-inverting Input

4 V-I Negative Supply

5 +IN B I ChB Non-inverting Input

6 -IN B I ChB Inverting Input

7 OUT B O ChB Output

8 V+I Positive Supply

Product Folder Links: LMH6672

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SNOS957H –APRIL 2001–REVISED AUGUST 2014

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6 Specifications

6.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT

VIN Differential ±1.2 V

Output Short Circuit Duration See(2)

Supply Voltage (V+−V−) 13.2 V

V++0.8

Voltage at Input/Output pins V

V−−0.8

Junction Temperature +150(3) °C

Soldering Information Infrared or Convection (20 sec) 235 °C

Wave Soldering (10 sec) 260 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Shorting the output to either supply or ground will exceed the absolute maximum TJand can result in failure.

(3) The maximum power dissipation is a function of TJ(MAX), RθJA and TA. The maximum allowable power dissipation at any ambient

temperature is PD= (TJ(MAX) −TA)/RθJA. All numbers apply for packages soldered directly onto a PC board.

6.2 Handling Ratings MIN MAX UNIT

Tstg Storage temperature range −65 +150 °C

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all 2 2000

pins(2)

V(ESD) Electrostatic discharge(1) V

Machine Model (MM)l(3) 200

(1) Human body model, 1.5 kΩin series with 100 pF. Machine model, 200 Ωin series with 100 pF.

(2) JEDEC document JEP155 states that 2000-V HBM allows safe manufacturing with a standard ESD control process.

(3) JEDEC document JEP157 states that 200-V MM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT

Supply Voltage (V+- V−) ±2.5 ±6.5 V

Operating Temperature Range −40 150 °C

6.4 Thermal Information SOIC SO PowerPAD

Package D Package DDA

THERMAL METRIC(1) UNIT

8 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 172 58.6 °C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

Product Folder Links: LMH6672

LMH6672

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SNOS957H –APRIL 2001–REVISED AUGUST 2014

6.5 Electrical Characteristics

Unless otherwise specified, all limits are ensured for G = +2, VS= ±2.5 to ±6V, RF= RIN = 470Ω, RL= 100Ω.

PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT

DYNAMIC PERFORMANCE

−3dB Bandwidth 90 MHz

0.1dB Bandwidth VS= ±6V 12 MHz

Slew Rate VS= ±6V, 4V Step, 10-90% 135 V/μs

Rise and Fall Time VS= 6V, 4V Step, 10-90% 23.5 ns

DISTORTION and NOISE RESPONSE

2nd Harmonic Distortion VO= 8.4 VPP, f = 100 kHz, RL= 25Ω −105 dBc

VO= 8.4 VPP, f = 1 MHz, RL= 100Ω −90 dBc

3rd Harmonic Distortion VO= 8.4 VPP, f = 100 kHz, RL= 25Ω −110 dBc

VO= 8.4 VPP, f = 1 MHz, RL= 100Ω −87 dBc

Input Noise Voltage f = 100 kHz 3.1 nV√Hz

Input Noise Current f = 100 kHz 1.8 pA/√Hz

INPUT CHARACTERISTICS

VOS Input Offset Voltage TJ=−40°C to 125°C −5.5 0.1 5.5 mV

−4−0.2 4

IBInput Bias Current TJ=−40°C to 125°C 8 16 µA

IOS Input Offset Current TJ=−40°C to 125°C −2.1 0 2.1 µA

CMVR Common Voltage Range VS= ±6V −6.0 −5.7 to 4.5 4.5 V

CMRR Common-Mode Rejection Ratio VS= ±6V, TJ=−40°C to 125°C 150 7.5 µV/V

TRANSFER CHARACTERISTICS

AVOL Voltage Gain RL= 1k, TJ=−40°C to 125°C 1.0 5 V/mV

RL= 25Ω, TJ=−40°C to 125°C 0.67 3.4 V/mV

VOOutput Swing RL= 25Ω, VS= ±6V −4.5 ±4.8 4.5 V

RL= 25Ω, TJ=−40°C to 125°C, −4.4 ±4.8 4.4

VS= ±6V

VOOutput Swing RL= 1k, VS= ±6V −4.8 ±4.8 4.8 V

RL= 1k, TJ=−40°C to 125°C, −4.7 ±4.8 4.7

VS= ±6V

ISC Output Current(3) VO= 0, VS= ±6V 350 525 mA

VO= 0, VS= ±6V, mA

260 600

TJ=−40°C to 125°C

POWER SUPPLY

ISSupply Current/Amp VS= ±6V 8 mA

VS= ±6V, TJ=−40°C to 125°C 7.2 9

PSRR Power Supply Rejection Ratio VS= ±2.5V to ±6V, dB

72 88.5

TJ=−40°C to 125°C

(1) All limits are specified by testing, characterization or statistical analysis.

(2) Typical values represent the most likely parametric norm.

(3) Shorting the output to either supply or ground will exceed the absolute maximum TJand can result in failure.

Product Folder Links: LMH6672

LMH6672

SNOS957H –APRIL 2001–REVISED AUGUST 2014

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6.6 ±2.5V Electrical Characteristics

Unless otherwise specified, all limits are ensured for G = +2, VS= ±2.5 to ±6V, RF= RIN = 470Ω, RL= 100Ω.

PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT

DYNAMIC PERFORMANCE

−3 dB Bandwidth 80 MHz

0.1 dB Bandwidth 12 MHz

Rise and Fall Time 2V Step, 10-90% 14 ns

DISTORTION and NOISE RESPONSE

2nd Harmonic Distortion VO= 2 VPP, f = 100 kHz, RL= 25Ω −96 dBc

VO= 2 VPP, f = 1 MHz, RL= 100Ω −85 dBc

3rd Harmonic Distortion VO= 2 VPP, f = 100 kHz, RL= 25Ω −98 dBc

VO= 2 VPP, f = 1 MHz, RL= 100Ω −87 dBc

INPUT CHARACTERISTICS

VOS Input Offset Voltage TJ=−40°C to 125°C −5.5 5.5 mV

−4.0 0.02 4.0

IBInput Bias Current TJ=−40°C to 125°C 8.0 16 µA

CMVR Common-Mode Voltage Range −2.5 1.0 V

CMRR Common-Mode Rejection Ratio TJ=−40°C to 125°C 150 8 µV/V

TRANSFER CHARACTERISTICS

AVOL Voltage Gain RL= 25Ω, TJ=−40°C to 125°C 0.67 3 V/mV

RL= 1k, TJ=−40°C to 125°C 1.0 4

OUTPUT CHARACTERISTICS

VOOutput Voltage Swing RL= 25Ω1.20 1.45

RL= 25Ω, TJ=−40°C to 125°C 1.10 1.35 V

RL= 1k 1.30 1.60

RL= 1k, TJ=−40°C to 125°C 1.25 1.50

POWER SUPPLY

ISSupply Current/Amp 8.0 mA

TJ=−40°C to 125°C 6.7 9.0

(1) All limits are specified by testing, characterization or statistical analysis.

(2) Typical values represent the most likely parametric norm.

Product Folder Links: LMH6672

0 50 100 150 200 250

4.5

4.6

4.7

4.8

4.9

5.0

5.1

5.2

5.3

5.4

5.5

+VOUT (V)

ILOAD (mA)

VS = ±6V

85°C

25°C

-40°C

01 2 3 4 5 6 7

±VSUPPLY (V)

0.2

0.4

0.6

0.8

1.0

1.2

1.4

VOUT - VSUPPLY (V)

25°C

85°C

-40°C

01 2 3 4 5 6

±VSUPPLY (V)

0.3

0.4

0.6

0.8

1.0

VOUT - VSUPPLY (V)

-40°C

25°C 85°C

0.1

0.2

0.5

0.7

0.9

01 2 3 4 5 6

±VSUPPLY (V)

0.2

0.6

0.8

1.2

1.4

1.6

VSUPPLY - VOUT (V)

-40°C

85°C

1.0

0.4

25°C

02 4 6 8 10 12 14

VS (V)

SWING (V)

1k:

25:

01 2 3 4 5 6

±VSUPPLY (V)

0.2

0.4

0.6

0.8

1.0

1.2

VSUPPLY - VOUT (V)

-40°C

25°C 85°C

LMH6672

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SNOS957H –APRIL 2001–REVISED AUGUST 2014

6.7 Typical Performance Characteristics

Av = + 2V/V

Figure 2. Positive Output Swing into 1kΩ

Figure 1. Output Swing RL= 25Ω, 1 kΩ@−40°C, 25°C, 85°C

Figure 3. Negative Output Swing into 1 kΩFigure 4. Positive Output Swing into 25Ω

Figure 5. Negative Output Swing into 25ΩFigure 6. +VOUT vs. ILOAD

Product Folder Links: LMH6672

3 4 5 6 7 8 9 10 11 12 13

200

300

400

500

600

700

ISOURCE (mA)

VS (V)

-40°C

25°C

85°C

3 4 5 6 7 8 9 10 11 12 13

200

300

400

500

600

700

ISOURCE (mA)

VS (V)

-40°C

25°C 85°C

0 50 100 150 200 250

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

-VOUT (V)

ILOAD (mA)

VS = ±2.5V

85°C

25°C

-40°C

02 4 6 8 10 12 14 16

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (mA)

-40°C

25°C

85°C

0 50 100 150 200 250

4.5

4.6

4.7

4.8

4.9

5.0

5.1

5.2

5.3

5.4

5.5

-VOUT (V)

ILOAD (mA)

VS = ±6V

85°C

25°C

-40°C

0 50 100 150 200 250

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

+VOUT (V)

ILOAD (mA)

VS = ±2.5V

85°C

25°C

-40°C

LMH6672

SNOS957H –APRIL 2001–REVISED AUGUST 2014

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Typical Performance Characteristics (continued)

Av = + 2V/V

Figure 7. −VOUT vs. ILOAD Figure 8. +VOUT vs. ILOAD

Figure 10. Supply Current vs. Supply Voltage

Figure 9. −VOUT vs. ILOAD

Figure 11. Sourcing Current vs. Supply Voltage Figure 12. Sinking Current vs. Supply Voltage

Product Folder Links: LMH6672

24 6 8 10 12 14

VSUPPLY (V)

0.02

0.04

0.06

0.1

IOFFSET (µA)

0.08

TJ = -40°C to 85°C

-2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5

-3

-2

-1

VIN (mV)

VOUT (V)

-40°C

25°C

85°C

RL = 1k:

-0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5

-3

-2

-1

VOS (mV)

VCM (V)

-40°C

25°C

85°C

24 6 8 10 12 14

SUPPLY VOLTAGE (V)

INPUT BIAS CURRENT (PA)

-40°C

25°

85°C

-0.5 1 2.5 4 5.5 7 8.5 10 11.5 13

-3

-2

-1

VOS (mV)

VCM (V)

-40°C 25°C

85°C

VOS (mV)

357 9 11 12 14 15

VS (V)

-1

-0.5

0.5

-40°C

85°C

25°C

LMH6672

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SNOS957H –APRIL 2001–REVISED AUGUST 2014

Typical Performance Characteristics (continued)

Av = + 2V/V

Figure 13. VOS vs. VSFigure 14. VOS vs. VCM, VS= 12V

Figure 16. Bias Current vs. VSUPPLY

Figure 15. VOS vs. VCM, VS= 5V

Figure 17. Offset Current vs. VSUPPLY Figure 18. VOUT vs. VIN

Product Folder Links: LMH6672

0 1 2 3 4 5 6 7 8 9 10

-105

-95

-85

-75

-65

-55

-45

-35

HARMONIC DISTORTION (dBc)

OUTPUT VOLTAGE PEAK TO PEAK

VS = ±6V

f = 1 MHz

RL = 25:

2ND

3RD

0.0 0.5 1.0 1.5 2.0 2.5 3.0

OUTPUT VOLTAGE PEAK TO PEAK

-115

-105

-95

-85

-75

-65

-55

-45

HARMONIC DISTORTION (dBc)

2ND

3RD

VS = ±2.5V

f = 1 MHz

0 100 200 300 400 500

-115

-105

-95

-85

-75

-65

-55

-45

HARMONIC DISTORTION (dBc)

LOAD RESISTANCE

3RD

2ND

VS = ±2.5V

f = 1 MHz

VOUT = 2 VPP

0 1 2 3 4 5 6 7 8 9 10

-115

-105

-95

-85

-75

-65

-55

-45

HARMONIC DISTORTION (dBc)

OUTPUT VOLTAGE PEAK TO PEAK

2ND

3RD

VS = ±6V

f = 1 MHz

-2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5

-3

-2

-1

VIN (mV)

VOUT (V)

-40°C

25°C

85°C

RL = 25:

0 100 200 300 400 500

-115

-105

-95

-85

-75

-65

-55

-45

HARMONIC DISTORTION (dBc)

LOAD RESISTANCE

3RD

2ND

VS = ±6V

f = 1 MHz

VOUT = 2 VPP

LMH6672

SNOS957H –APRIL 2001–REVISED AUGUST 2014

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Typical Performance Characteristics (continued)

Av = + 2V/V

Figure 20. Harmonic Distortion vs. Load

Figure 19. VOUT vs. VIN

Figure 21. Harmonic Distortion vs. Load Figure 22. Harmonic Distortion vs. Output Voltage

Figure 24. Harmonic Distortion vs. Output Voltage

Figure 23. Harmonic Distortion vs. Output Voltage

Product Folder Links: LMH6672

0.1 1 10 100

FREQUENCY (MHz)

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

HARMONIC DISTORTION (dBc)

2ND

3RD

VS = ±2.5V

VOUT = 2 VPP

0.1 1 10 100

FREQUENCY (MHz)

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

HARMONIC DISTORTION (dBc)

2ND

3RD

VS = ±6V

RL = 25:

VOUT = 2 VPP

0 2 3 7 11

-125

-115

-95

-85

-75

-65

-55

-45

-35

HARMONIC DISTORTION (dBc)

OUTPUT VOLTAGE PEAK TO PEAK

-105

1 4 5 6 8 9 10

VS = ±6V

f = 100 kHz

RL = 25:

2ND 3RD

0.1 1 10 100

FREQUENCY (MHz)

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

HARMONIC DISTORTION (dBc)

2ND

3RD

VS = ±6V

VOUT = 2 VPP

0 1 2 3 4 5 6 7 8 9 10

-125

-115

-105

-95

-85

-75

-65

-55

HARMONIC DISTORTION (dBc)

OUTPUT VOLTAGE PEAK TO PEAK

VS = ±6V

f = 100 kHz

2ND

3RD

0.0 0.5 1.0 1.5 2.0 2.5 3.0

OUTPUT VOLTAGE PEAK TO PEAK

-115

-105

-95

-85

-75

-65

-55

-45

HARMONIC DISTORTION (dBc)

2ND

3RD

VS = ±2.5V

f = 1 MHz

RL = 25:

LMH6672

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SNOS957H –APRIL 2001–REVISED AUGUST 2014

Typical Performance Characteristics (continued)

Av = + 2V/V

Figure 25. Harmonic Distortion vs. Output Voltage Figure 26. Harmonic Distortion vs. Output Voltage

Figure 28. Harmonic Distortion vs. Frequency

Figure 27. Harmonic Distortion vs. Output Voltage

Figure 29. Harmonic Distortion vs. Frequency Figure 30. Harmonic Distortion vs. Frequency

Product Folder Links: LMH6672

0.1 1 10 100

FREQUENCY (MHz)

-3

GAIN (dB)

0.1 dB/div

-2

-1

5.9

6.1

6.2

6.3

6.4

6.5

6.6

6.7

6.8

5.8

Vs = ±2.5 V

Vs = 6 V

Vs = -6 V

40 mV/DIV

20 ns/DIV

40 mV/DIV

1 V/DIV

20 ns/DIV

0.1 1 10 100

FREQUENCY (MHz)

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

HARMONIC DISTORTION (dBc)

2ND

3RD

VS = ±2.5V

RL = 25:

VOUT = 2 VPP

1 V/DIV

20 ns/DIV

LMH6672

SNOS957H –APRIL 2001–REVISED AUGUST 2014

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Typical Performance Characteristics (continued)

Av = + 2V/V

Figure 32. Pulse Response, VS= ±6V

Figure 31. Harmonic Distortion vs. Frequency

Figure 33. Pulse Response, VS= ±2.5V, ±6V Figure 34. Pulse Response, AVCL =−1, VS= ±6V

Figure 35. Pulse Response, AVCL =−1, VS= ±2.5V, ±6V Figure 36. Frequency Response

Product Folder Links: LMH6672

100

PSRR (dB)

100 1k 10k 100k 1M

FREQUENCY (Hz)

10M

100

PSRR (dB)

100 1k 10k 100k 1M

FREQUENCY (Hz)

10M

CMRR (dB)

1k 10k 100k 1M 10M

FREQUENCY (Hz)

100M

120

100

120

CMRR (dB)

1k 10k 100k 1M 10M

FREQUENCY (Hz)

100

100M

100k 1M 10M 100M

FREQUENCY (Hz)

-4

-1

GAIN (dB)

12V

13 MHz

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SNOS957H –APRIL 2001–REVISED AUGUST 2014

Typical Performance Characteristics (continued)

Av = + 2V/V

Figure 37. Frequency Response, AVCL = +5V/V Figure 38. Frequency Response, AVCL = +10V/V

Figure 39. CMRR vs. Frequency, Vs = 12V Figure 40. CMRR vs. Frequency, Vs = 5V

Figure 41. PSRR+ vs. Frequency, VS= 5V and 12V Figure 42. PSRR−vs. Frequency VS= 5V and 12V

Product Folder Links: LMH6672

100 1k 10k 1M 10M

FREQUENCY (Hz)

100

100k

VOLTAGE NOISE (nV/

Hz)

100

CURRENT NOISE (pA/

Hz)

LMH6672

SNOS957H –APRIL 2001–REVISED AUGUST 2014

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Typical Performance Characteristics (continued)

Av = + 2V/V

Figure 43. en& invs. Frequency, VS= 5V and 12V

Product Folder Links: LMH6672

Note: Supply and Bypassing not shown.

1/2

LMH6672

Rf1

VIN

Rf2

1/2

LMH6672

AVVIN

12.5

1:N

(1.2)

12.5

(VPP)Rg VOUT

RL = 100:

LMH6672

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SNOS957H –APRIL 2001–REVISED AUGUST 2014

7 Detailed Description

7.1 Functional Block Diagram

Figure 44. LMH6672 Block Diagram

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SNOS957H –APRIL 2001–REVISED AUGUST 2014

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8 Power Supply Recommendations

8.1 Thermal Management

The LMH6672 is a high-speed, high power, dual operational amplifier with a very high slew rate and very low

distortion. For ease of use, it uses conventional voltage feedback. These characteristics make the LMH6672

ideal for applications where driving low impedances of 25 to 100 Ωsuch as xDSL and active filters.

A class AB output stage allows the LMH6672 to deliver high currents to low impedance loads with low distortion

while consuming low quiescent supply current. For most op-amps, class AB topology means that internal power

dissipation is rarely an issue, even with the trend to smaller surface mount packages. However, the LMH6672

has been designed for applications where high levels of power dissipation may be encountered.

Several factors contribute to power dissipation and consequently higher junction temperatures. These factors

need to be well understood if the LMH6672 is to perform to specifications in all applications. This section will

examine the typical application shown in Figure 44 as an example. Because both amplifiers are in a single

package, the calculations are for the total power dissipated by both amplifiers.

There are two separate contributors to the internal power dissipation:

1. The product of the supply voltage and the quiescent current when no signal is being delivered to the external

load.

2. The additional power dissipated while delivering power to the external load.

The first of these components appears easy to calculate simply by inspecting the data sheet. The typical

quiescent supply current for this part is 7.2 mA per amplifier. Therefore, with a ±6 volt supply, the total power

dissipation is:

PD= VS× 2 × lQ= 12 × (14.4×10-3) = 173 mW

where

• (VS= VCC + VEE) (1)

With a thermal resistance of 172°C/W for the SOIC package, this level of internal power dissipation will result in a

junction temperature (TJ) of 30°C above ambient.

Using the worst-case maximum supply current of 18 mA and an ambient of 85°C, a similar calculation results in a

power dissipation of 216 mW, or a TJof 122°C.

This is approaching the maximum allowed TJof 150°C before a signal is applied. Fortunately, in normal

operation, this term is reduced, for reasons that will soon be explained.

The second contributor to high TJis the power dissipated internally when power is delivered to the external load.

This cause of temperature rise is more difficult to calculate, even when the actual operating conditions are

known.

To maintain low distortion, in a Class AB output stage, an idle current, IQ, is maintained through the output

transistors when there is little or no output signal. In the LMH6672, about 4.8 mA of the total quiescent supply

current of 14.4 mA flows through the output stages.

Under normal large signal conditions, as the output voltage swings positive, one transistor of the output pair will

conduct the load current, while the other transistor shuts off, and dissipates no power. During the negative signal

swing this situation is reversed, with the lower transistor sinking the load current while the upper transistor is cut

off. The current in each transistor will approximate a half wave rectified version of the total load current.

Because the output stage idle current is now routed into the load, 4.8 mA can be subtracted from the quiescent

supply current when calculating the quiescent power when the output is driving a load.

Product Folder Links: LMH6672

2/S x IRMS

(40 mW/50:)

LMH6672

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SNOS957H –APRIL 2001–REVISED AUGUST 2014

Thermal Management (continued)

The power dissipation caused by driving a load in a DSL application, using a 1:2 turns ratio transformer driving

20 mW into the subscriber line and 20 mW into the back termination resistors, can be calculated as follows:

PDRIVER = PTOT – (PTERM + PLINE)

Where

• PDRIVER is the LMH6672 power dissipation

• PTOT is the total power drawn from the power supply

• PTERM is the power dissipated in the back termination resistors

• PLINE is the power sent into the subscriber line

• At full specified power, PTERM = PLINE = 20 mW, PTOT = VS× IS(2)

In this application, VS= 12V.

IS= IQ+ AVG |IOUT| (3)

IQ= the LMH6672 quiescent current minus the output stage idle current. (4)

IQ= 14.4 – 4.8 = 9.6 mA (5)

Average (AVG) |IOUT| for a full-rate ADSL CPE application, using a 1:2 turns ratio transformer, is = 28.28

mA RMS.

For a Gaussian signal, which the DMT ADSL signal approximates, AVG |IOUT| = = 22.6 mA. Therefore,

PTOT = (22.6 mA + 9.6 mA) × 12V = 386 mW and PDRIVER is 40 mW lower or 346 mW.

In the SOIC package, with a θJA of 172°C/W, this causes a temperature rise of 60°C. With an ambient

temperature at the maximum recommended 85°C, the TJis at 145°C, which is below the specified 150°C

maximum.

Even if it is assumed that the absolute maximum ISover temperature of 18 mA, when the IQis scaled up

proportionally to 7 mA, the PDRIVER only goes up by 17 mW causing a 62°C rise from ambient to 147°C.

Although very few CPE applications will ever operate in an environment as hot as 85°C, if a lower TJis desired

or the LMH6672 is to be used in an application where the power dissipation is higher, the SO PowerPAD (DDA)

package provides a much lower RθJA of only 58.6° C/W. Using the same PDRIVER as above, we find that the

temperature rise is only about 21°C, resulting in TJof 106°C with 85°C ambient.

NOTE

Since the exposed PAD (or DAP) of the SO PowerPAD (DDA) package is internally

floating, the footprint for DAP could be connected to ground plane in PCB for better heat

dissipation.

Product Folder Links: LMH6672

LMH6672

SNOS957H –APRIL 2001–REVISED AUGUST 2014

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9 Device and Documentation Support

9.1 Trademarks

All trademarks are the property of their respective owners.

9.2 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

9.3 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Product Folder Links: LMH6672

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LMH6672MA/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMH66

72MA

LMH6672MAX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMH66

72MA

LMH6672MR/NOPB ACTIVE SO PowerPAD DDA 8 95 RoHS & Green SN Level-3-260C-168 HR -40 to 85 LMH66

72MR

LMH6672MRX/NOPB ACTIVE SO PowerPAD DDA 8 2500 RoHS & Green SN Level-3-260C-168 HR -40 to 85 LMH66

72MR

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LMH6672MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

LMH6672MRX/NOPB SO

Power

PAD

DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 31-Jul-2014

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LMH6672MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0

LMH6672MRX/NOPB SO PowerPAD DDA 8 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 31-Jul-2014

Pack Materials-Page 2

www.ti.com

PACKAGE OUTLINE

TYP

6.2

5.8

1.7 MAX

6X 1.27

8X 0.51

0.31

3.81

TYP

0.25

0.10

0 - 8

0.15

0.00

2.34

2.24

2.34

2.24

0.25

GAGE PLANE

1.27

0.40

NOTE 3

5.0

4.8

B4.0

3.8

4218825/A 05/2016

PowerPAD SOIC - 1.7 mm max heightDDA0008A

PLASTIC SMALL OUTLINE

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MS-012.

PowerPAD is a trademark of Texas Instruments.

0.25 C A B

PIN 1 ID

AREA

NOTE 4

SEATING PLANE

0.1 C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 2.400

EXPOSED

THERMAL PAD

www.ti.com

EXAMPLE BOARD LAYOUT

(5.4)

(1.3) TYP

( ) TYP

VIA

0.2

(R ) TYP0.05

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

8X (1.55)

8X (0.6)

6X (1.27)

(2.95)

NOTE 9

(4.9)

NOTE 9

(2.34)

SOLDER MASK

OPENING

(1.3)

TYP

4218825/A 05/2016

PowerPAD SOIC - 1.7 mm max heightDDA0008A

PLASTIC SMALL OUTLINE

SYMM

SEE DETAILS

LAND PATTERN EXAMPLE

SCALE:10X

SOLDER MASK

OPENING

METAL COVERED

BY SOLDER MASK

SOLDER MASK

DEFINED PAD

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

9. Size of metal pad may vary due to creepage requirement.

10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

OPENING

SOLDER MASK METAL UNDER

SOLDER MASK

DEFINED

www.ti.com

EXAMPLE STENCIL DESIGN

(R ) TYP0.05

8X (1.55)

8X (0.6)

6X (1.27)

(5.4)

(2.34)

BASED ON

0.125 THICK

STENCIL

4218825/A 05/2016

PowerPAD SOIC - 1.7 mm max heightDDA0008A

PLASTIC SMALL OUTLINE

1.98 X 1.980.175

2.14 X 2.140.150

2.34 X 2.34 (SHOWN)0.125

2.62 X 2.620.1

SOLDER STENCIL

OPENING

STENCIL

THICKNESS

NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

12. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

EXPOSED PAD

100% PRINTED SOLDER COVERAGE BY AREA

SCALE:10X

SYMM

BASED ON

0.125 THICK

STENCIL

BY SOLDER MASK

METAL COVERED SEE TABLE FOR

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

www.ti.com

PACKAGE OUTLINE

.228-.244 TYP

[5.80-6.19]

.069 MAX

[1.75]

6X .050

[1.27]

8X .012-.020

[0.31-0.51]

.150

[3.81]

.005-.010 TYP

[0.13-0.25]

0 - 8 .004-.010

[0.11-0.25]

.010

[0.25]

.016-.050

[0.41-1.27]

4X (0 -15 )

.189-.197

[4.81-5.00]

NOTE 3

B .150-.157

[3.81-3.98]

NOTE 4

4X (0 -15 )

(.041)

[1.04]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

.010 [0.25] C A B

PIN 1 ID AREA

SEATING PLANE

.004 [0.1] C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 2.800

www.ti.com

EXAMPLE BOARD LAYOUT

.0028 MAX

[0.07]

ALL AROUND

.0028 MIN

[0.07]

ALL AROUND

(.213)

[5.4]

6X (.050 )

[1.27]

8X (.061 )

[1.55]

8X (.024)

[0.6]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

EXPOSED

METAL

OPENING

SOLDER MASK METAL UNDER

SOLDER MASK

DEFINED

EXPOSED

METAL

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SYMM

SEE

DETAILS

SYMM

www.ti.com

EXAMPLE STENCIL DESIGN

8X (.061 )

[1.55]

8X (.024)

[0.6]

6X (.050 )

[1.27] (.213)

[5.4]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

SYMM

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