XCR3032XL-PLCC44 - Xilinx, Inc.

DS012 (v1.3) February 9, 2001 www.xilinx.com 1

Advance Product Specif ication 1-800-255-7778

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

Features

• Fast Zero Power (FZP™) design technique provides

ultra-low power and ver y high speed

• Innovative XP LA 3 architecture comb ines high speed

with extre me fle xibility

• Based on industry's first TotalCMOS™ PLD - both

CMOS design and process technolog ies

• Adv anced 0.35µ fiv e meta l layer E2CMOS process

- 1,0 00 erase/program cycles guaranteed

- 20 years data retention guaranteed

• 3V, In-System Programmable (ISP) using JTAG IEEE

1149.1 interface

- Ful l Boundary Scan Test (IEEE 1149.1)

- Fast programming times

• Ultra-l ow static power of less than 100 µA

• Support for complex asynchronous clocking

- 16 product term clocks and four local control term

clocks per function block

- Four global clocks and one universal control term

clock per de vi ce

• Excellent pin retention during design changes

• 5V tol e ran t I/O p i ns

• I nput register set up time of 1.7 ns

• Single pass logic expandable to 48 product terms

• H i gh-speed pin-to-pin del ays of 5.0 ns

• Slew rate control per output

• 100% routable

• Security bit pre vents unauthorized access

• Supports hot-plugging capability

• Design entry/verification using Xilinx or industry

standard CA E tools

• I nnovative Control Ter m stru cture provides:

- A sy nchronous ma crocell clocking

- A sy nchronous ma crocel l register preset/reset

- Clock enable control per macrocell

• Four output enable controls per function block

• Foldback NAND for synthesis optimization

• Global 3-state which facilitates "bed of nails" testing

• Available in Ch ip-scale BGA, PLCC, and QF P

packages

• C o mm ercial grade and extended voltage industri al

grade available

CoolRunner® XPLA3 CPLD

DS012 (v1.3) February 9, 2001 014

Advance Product Specification

Table 1: CoolRunner XPLA3 Device Family

XCR3032XL XCR3064XL XCR3128XL XCR3256XL XCR3384XL

Macrocells 32 64 128 256 384

Usable Gat es 800 1600 3200 6400 9600

Registers 32 64 128 256 384

TPD (ns) 5667.57.5

TSU (ns)1.72222

TCO (n s) 3.5 4 4 4.5 4.5

Fsystem (MHz) 175 145 145 140 127

Table 2: CoolRun ner XP LA3 Packag es and User I/O Pins

XCR3032XL XCR3064XL XCR3128XL XCR3256XL XCR3384XL

44-pin PLCC 36 36 - - -

44-pin 1mm VQFP 36 36 - - -

48-pin 0.8mm CSP 36 40 - - -

56-pin 0.5mm CSP - 48 - - -

100-pin 1mm VQFP - 68 84 - -

144-pin 0.8mm CSP - - 108 - -

144-pin 1.4mm VQF P - - 1 08 120 -

208-pin PQFP - - - 164 172

256-pin 1.0mm BGA - - - 164 212

280-pin 0.8mm CSP - - - 164 -

CoolRunner® XPLA3 CPLD

2www.xilinx.com DS012 (v1. 3) February 9, 2001

1-800-255-7778 Advance Product Specification

Family Overview

The CoolRunner XPLA3 (eXtended Programmable Logic

Array) family of CPLDs is targeted for low power systems

that include por table, handheld, and power sensitive appli-

cations. Each member of the XPLA3 family includes Fast

Zero Power (FZP) design technology that combines low

power and high speed. With this design technique, the

XPLA3 family offers true pin-to-pin speeds of 5.0 ns, while

simultaneously del ivering p ower that is less than 100 µA at

standby without the need for "turbo bits" or other power

down schemes. By replacing conventional sense amplifier

methods for implementing product terms (a technique that

has been used in PLDs since the bipolar era) with a cas-

caded chain of pure CMOS gates, the dynamic power is

also substantially lower than a ny other CPLD. CoolRunner

devices are the onl y To talCMOS PLDs, as they use both a

CMOS process technology and the patented full CMOS

FZP design techniq ue.

The CoolRunner XPLA3 family emplo ys a full PLA structure

for logic allocation within a function block. The PLA pro-

vides maximum flex ibility and logic density, with superior pin

locking capab ilit y, while maint aining deterministi c timi ng.

XPLA3 CPLDs are supported by WebPACK and WebFIT-

TER from Xilinx and industry standard CAE tools

(Cadence/OrCAD, Exemplar Logic, Mentor, Synopsys,

Viewlogic, andd Synplicity), using text (ABEL, VHDL, Ver-

ilog) and schematic capture design entry. Design verifica-

tion uses industry standard simulators for functional and

timing simulation. Development is supported on personal

computer, Sparc, and HP pl atforms.

The XPLA3 family features also i nclude industry-standard,

I EEE 1149.1, JTAG interface through which boundary-scan

testing and In-System Programming (ISP) and reprogram-

ming of the device can occur. The XPLA3 CPLD is electri-

cally reprogrammable using industry standard device

programmers.

XPLA3 Ar chitecture

Figure 1 shows a high -level block di agram of a 1 28 macro-

cell device implementing the XPLA3 architecture. The

XPLA3 architecture consists of function blocks that are

interconnected by a Zero-power Interconnect Array (ZIA).

The ZIA is a virtual crosspoint switch. Each function block

has 36 inputs from the ZIA and contain s 16 macroce lls.

From this point of view, this architecture looks like many

other CPLD architectures. What makes the XPLA3 family

unique is logic allocation inside each function block and the

design techni que used to implem ent produc t ter ms.

Function Block Architecture

Figure 3 illustrates the function block architecture. Each

function block contains a PLA array that generates control

terms, clock terms, and logic cells. A PLA differs from a PAL

in that the PLA has a fully programmable AND array fol-

lowed by a fully programmable OR array. A PAL arra y has a

fixed OR array, limiting flexibility. Refer to Figure 2 for an

example of a PAL and a PLA arra y. The PLA array receives

its inputs directly from the ZIA. There are 36 pairs of true

and complem ent inputs from the ZIA that feed the 48 prod-

uct terms in the array. Within the 48 P-terms there are eight

local control terms (LCT[0:7]) availab le as control signals to

each macrocell f or use as asynchronous clock s, resets, pre-

sets and output enables. If not needed as control terms,

these P-Terms can join the other 40 P-Terms as additional

l o gic reso ur ces.

In each func tion block there are eight foldback NAND prod-

uct terms that can be used to synthesize increased logic

density in support of wider logic equations. This f eature can

be disabled in software by t he user. As with unused control

P-Te rms, unused foldback NAND P-Terms can be used as

additional logic resources.

Sixteen high-speed P-Terms are available at each macro-

cell for speed critical logic. If wider than a single P-Term

logic is required at a macrocell, 47 additional P-Te rms can

be summed in prior to the VFM (Variable Function Multi-

plexer). The VFM increases logic optimization by imple-

menting some two input logic funtions before entering the

macroc ell (see Figure 4).

Each macrocell can support combinatorial or registered

logic. The macrocell register accommodates asynchronous

presets and resets, and "power on" initial state. A hardware

clock enabl e is also provided for ei ther D or T type registers,

and t he register c lock input i s used as a la tch enable wh en

the macrocel l register is configured as a latch f unct ion.

CoolRunner® XPLA 3 C PLD

DS012 (v1.3) February 9, 2001 www.xilinx.com 3

Advance Product Specif ication 1-800-255-7778

Figure 1: Xilinx XPLA3 CPLD Ar chi t e cture

Figure 2: PLA and PAL Array Examp le

FUNCTION

BLOCK FUNCTION

BLOCK

I/O 36

MC1

MC2

MC16

I/O

MC1

MC2

MC16

FUNCTION

BLOCK FUNCTION

BLOCK

I/O 36

MC1

MC2

MC16

I/O

MC1

MC2

MC16

FUNCTION

BLOCK FUNCTION

BLOCK

I/O 36

MC1

MC2

MC16

I/O

MC1

MC2

MC16

FUNCTION

BLOCK FUNCTION

BLOCK

I/O 36

MC1

MC2

MC16

I/O

MC1

MC2

MC16

DS012_01_112000

ZIA

Inputs

DS012_08_020601

PLA Array

PAL Array

Outputs

CoolRunner® XPLA3 CPLD

4www.xilinx.com DS012 (v1. 3) February 9, 2001

1-800-255-7778 Advance Product Specification

Macrocell Architecture

Figure 5 sho ws the architecture of the macrocell used in the

CoolRunner XPLA3. Any macrocell can be reset or preset

on power-up. Each macroc ell register can be conf igured as

a D-, T-, or Latch-type flip-flop, or bypassed if the macrocell

is required as a combinator ial logic function.

Each of these flip-flops can be clocked from any one of eight

sources or their complements. There are two global syn-

chronous clocks that are selected from the four external

clock pins. There is one universal clock signal. The clock

input signals CT[4:7] (Local Control Terms) can be individu-

ally configured as either a PRODUCT term or SUM term

equation created from the 36 signals available inside the

funct ion block.

There are two muxed paths to the ZIA. One mux selects

from either the output of th e VFM or the output of the regis-

ter. The other mux selects from the output of the register or

from the I/O pad of the macrocell . When the I/O pin is used

as an output, the output buf fer is enabled, and the macrocell

feedback path can be used to feed back the logic imple-

mented in the macrocell. When an I/O pin is used as an

input , the outpu t buffer will be 3-stated and the input signal

will be fed into the ZIA via the I/O feedback path. The logic

Figure 3: Xilinx XPLA3 Function Block Architecture

Figure 4: Variable Functi on Multiplexer

Foldback NAND

(PT[8:15])

(PT[0:47])

(PT0)

(PT7)

(PT[32:47])

(PT16)

(PT[0:47])

(PT31)

To Local Control Term (LCT0)

To Universal Control Term (UCT) Mux

To Local Control Term (LCT7)

P-term Clocks

Product

Term

Array

36 x 48

ZIA

VFM

Macrocell 1

DQI/O1

ZIA

I/O16

VFM

Macrocell 16

DS012_02_101200

From PLA OR Term

To Combinatorial Path

and Register Input

From P-term

DS012_03_121699

CoolRunner® XPLA 3 C PLD

DS012 (v1.3) February 9, 2001 www.xilinx.com 5

Advance Product Specif ication 1-800-255-7778

implemented in the buried macrocell can be fed back to the

ZIA via the macrocell feedback path.

If a macrocell pin is configured as a registered input, there is

a direct path to the register to provide a fast input setup

time. If the macrocell is configured as a latch, the register

clock input functions as the latch enable, with the latch

transparent when this signal is high. The hard-wired clock

enable is non-functional when the macrocell is configured

as a latch.

I/O Cell

The OE (Output Enable) multiplexer has eight possible

modes (Figure 6). When the I/O Cell is configured as an

input, a half latch feature exists. This half latch pulls the

input high (through a weak pullup) if the input should float

and cross the threshold. This protect s the input from st ay-

ing in the linear region and causing an increased amount of

power consumption. This same weak pull up can be

enabled in software such that it is always on when the I/O

Cell is configured as an input. This weak pull up is automat-

ically tur ned on when a pin is unused by the desig n.

The I/O Cell is 5V tolerant when the device is powered.

Each output has independent slew rate c ontrol (f ast or slo w)

which will assist in reducing EMI emissions.

Outputs are 3.3V PCI electrical specification compatib le (no

inter nal clamp diode).

Note that an I/O macrocell used as buried logic that does

not have the I/O pin used for input is considered to be

unused, and the wea k pu ll-up resistors will be turned o n. It

is recommended that any unused I/O pins on the XPLA3

family of CPLDs be left unconne cted. Dedicated input pins

(CLKx/INx) do not have on-chip weak pull-up resistors;

therefore unused dedicated input pins must have external

ter mination. As with all CMOS d evice s, do not allow inputs

to fl oat.

Figure 5: XP LA3 M acrocell Architectu re

Global CLK

Universal CLK

P-term CLK

CT [4:7]

ds012_05_122299

Universal PST

CT [0:5]

Universal RST

CT [0:5]

To ZIA

To I/O

PAD

Note: Global CLK signals come from pins.

To ZIA

VFM

RST

PST

D/T/L

CLKEn

CT4

P-term

PLA OR Term

From PT Array

Figure 6: I/O Cell

GND (Weak P.U.)

VCC

Universal OE

GND

OE [2:0]

To Macrocell / ZIA

From Macrocell I/O Pin

Slew

Control

Decode

I/O Pin

State

3-State

Function CT0

Function CT1

Function CT2

Function CT6

Universal OE

Enable

Weak P.U.

ds012_06_121699

Weak Pull-up

OE = 7

VCC

CoolRunner® XPLA3 CPLD

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1-800-255-7778 Advance Product Specification

Timing Model

The XPLA3 architecture follows a timing model that allows

deter ministic timing i n de si gn and red esign. T he basic tim-

ing model is shown in Figure 7. There is a f ast path (TLOGI1)

into the macrocell which is used if there is a single produc t

term. The TLOGI2 path is used f or m ultiple product term tim-

ing. F or optimization of logic, the XPLA3 CPLD architecture

includes a Fold-back NAND path (TLOGI3). There is a fast

input path to each macrocell if used as an Input Register

(TFIN). XPLA3 also i ncludes universal control ter ms (TUDA)

that can be used for synchronization of the macrocell regis-

ters in different function blocks. There is slew rate control

and outpu t enable control on a per mac roc ell basis.

JTAG Testing Capability

JTAG is the commonly used acronym for the Boundary

Scan Test (BST) feature defined for integrated circuits by

IEEE Standard 1149.1. This standard defines input/output

pins, logic control functions, and commands that facilitate

both boa rd and device level testing with out the use of spe-

cialized test equipment. XPLA3 devices use the JTA G Inter-

face for In-System Programming/Reprogramming. The

JTAG command set is implemented as described in Table 3.

As implemented in XPLA3, the JTAG Port includes four of

the fiv e pi ns (refer to Table 4) described in the JTAG specifi-

cation: TCK, TMS, TDI, and TDO . The fifth signal defined by

the JTAG specification is T RST (Te st Reset). TRST is con-

sidered an optional signal, since it is not actually required to

perf orm BST or ISP. The XPLA3 saves an I/O pin f or general

pur pose use by not im ple men ting t he optional T RS T signal

in the JTAG interface. Instead, the XPLA 3 sup por t s the test

reset functiona lity through t he us e of its power-up res et cir-

cuit.

Port Enable Pin

The Port Enable pin is used to reclaim TMS, TDO, TDI, and

TCK for JTAG ISP programming if the user has defined

these pins as general purpose I/O du ring device program-

ming. For ease of use, XPLA3 dev ices are shipped with the

JTAG por t pins enabled. Please note that the Por t Enable

pin must be low logic level during the power-up sequence

for the device to operate properly.

During device programm ing, the JTAG ISP pin s can be l eft

as is or reco nfigured as user spec ific I/O pins. If the JTAG

ISP pins have been used for I/O pins, sim ply applying high

logic lev el to the Port Enabl e pin conv erts the JTAG ISP pins

back to their respective programming function and the

device can be reprogrammed via ISP. After completing the

desired JTAG ISP programming function, simply return P ort

Enable to Ground. This w ill re- est ablish t he J TAG IS P p ins

to their respective I/O function. Note that reconfiguring the

JTAG port pins as I/Os makes these pins non-JTAG ISP

functional until reclaimed by port enable. If the JTAG pins

are not requi red as I /O, port enable shoul d be perm anently

tied to GND. Pins associated with the JTA G port have inter-

nal weak pull ups enabled to ter minate the pins. However,

in noisy environments, external 10K pull ups are recom-

mended.

The XPLA3 family allows the macrocells associated with

these pins to be used as buried logic when the JTAG/ISP

funct ion is enable d.

Figure 7: XPLA3 Timin g Model

OUT

SLEW

LOGI1,2

DLT Q

S/R

LOGI3

FIN

GCK

UDA

DS017_02_042800

CoolRunner® XPLA 3 C PLD

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Advance Product Specif ication 1-800-255-7778

Table 3: XP LA3 Low-level JTAG Boundary -scan Com m and s

Instruction

(Instru ction Code)

Sample/Preload

(00010)

Boundary-scan Register

The man dato r y Sample/P reload instruct ion allows a snapshot of the nor m al

operation of the component to be taken and exam ined . It also allows data values to

be loaded into the latched parallel outputs of the Boundary-scan Shift Register prior

to selection of the other boundary-scan t est instruct ions.

Extest

(00000)

Boundary-scan Register

The man datory Extest instruction allows testing of off- chip circuitry and board level

interconnections. Data would typically be loaded onto the latched parallel outputs of

Boundary-scan Shift Register using the Sample/Preload instruction prior to selection

of the Extest instr uction.

Bypass

(11111)

Bypass Register

Places the 1-bit bypass register betwe en the TDI and TDO pins, which allows the

BST data to pass synchronously through the selected device to adja cent devices

during norm al device operati on. The Bypass instruc tion can be entered by holding

TDI at a constant hig h v alue and completi ng an Inst ruct ion -scan cycle.

Idcode

(00001)

Boundary-scan Register

Selects the Idcode register and places it between TDI and TDO, allowing the Idcode

to be serially shifted out of TDO . The Idcode instruction permits blind interrogation of

the components assembled onto a printed circuit board. Thus, in circumstances

where the component population may var y, it is possibl e to deter mi ne what

components exist in a product.

High-Z

(00101)

Bypass Register

The High-Z instru ction places the component in a state which all of its system logic

outputs are placed in an inactive drive state (e.g., high impedance). In this state, an

in-circuit test system may drive sig nals onto the connections norma lly driven by a

component output without incurring the risk of damage to the component. The High-Z

instruction also forces the Bypass Register between TDI and TDO

Intest

(00011)

Boundary-scan Register

The Intest instruct ion selects the boundary scan registe r preparator y to applying

tests to the logic core of the dev ice. This permits testing of on-chip system logic while

the comp onent is already on the b oard

Table 4: JTAG Pin Descri ption

Pin Name Description

TCK Test Cloc k Input Clock pin to shift the serial data and instructions in and out of the TDI and TDO pins,

respectively.

TMS Test Mode Select Serial input pin selects the JTAG instruction mode. TMS should be driv en high during

user mode operation.

TDI Test Data Input Serial input pin for instructions and test data. Data is shifted in on the rising edge of

TCK.

TDO Test Data Output Serial output pin for instructions and test data. Data is shifted out on the fal ling edge

of TCK. The signal is 3-stated if data is not being shifted out of the device.

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3V, In-System Programming (ISP)

XPLA3 allows for 3V, in-system programming/reprogram-

ming of its E EPRO M cells via a JTAG inte rface. An on-chip

charge pump eliminates the need for externally provided

super-voltages. This allows programming on the circuit

board using only the 3V supply required by the device for

normal operation. The ISP commands implemented in

XPLA3 are specified in Table 5.

JTAG and ISP Interfacing

A number of industry-established methods exist for

JTAG/ISP interfacing with CPLDs and other integrated cir-

cuits. Th e XPLA 3 family su pports the following methods:

•Xilin x HW 1 30

•PC Parallel Por t

•Workstation or PC Serial Port

•Embedded Processor

•Automated Te st Equipm ent

•Third Party Programmers

•Xilinx ISP Programming Tools

Table 5: Low-l eve l ISP Com m ands

Instruction

(Register Used) Instruction Code Descrip tion

Enable

( ISP Sh ift Register) 01001 Enables the Erase, Program, and Verify commands. Using the Enable

instruction bef ore the Erase, Program, and Verify instructions allows the

user to specify the outputs of the device using the JTAG Boundary-Scan

Sample/Preload command.

Erase

( ISP Sh ift Register) 01010 Erases the entire EEPR OM arra y. User can define the outputs during this

operation by using the JTAG Sample/Preload command.

Program

( ISP Sh ift Register) 01011 Programs the data in the ISP Shift Register into the addressed EEPROM

row. The outputs can be defined by using the JTAG Sample/Preload

command.

Disable

( ISP Sh ift Register) 10000 Disab l e instruction allows the user to leav e ISP mode. It selects the ISP

Verify

( ISP Sh ift Register) 01100 Transfers the data from the addressed row to the ISP Shift Register. The

data can then be shifted out and compared with the JEDEC file. The user

can define the outputs during t his operation.

Table 6: Progra m m i ng Specifi c at io ns

Symbol Parameter Min. Max. Unit

DC Para mete rs

VCCP VCC supply program/verify 3.0 3.6 V

ICCP ICC limit p ro gram/ver ify - 2 0 mA

VIH Input voltage (H igh) 2.0 - V

VIL Input voltage (L ow) - 0.8 V

VOL Output vol tage (Low) - 0.4 V

VOH Output vol tage (High) 2.4 - V

AC Parameters

FMAX TCK maximum frequency - 10 MHz

PWE Pulse width erase 100 - ms

PWP Pulse width program 10 - ms

PWV Pulse width verify 10 - µs

CoolRunner® XPLA 3 C PLD

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Advance Product Specif ication 1-800-255-7778

Absolute Maximu m Ratings(1)

Recommended O peration Co nditions

Quality and Reliability Characteristics

TINIT Initialization time 50 - µs

TMS_SU TMS setup time befo re TCK ↑10 - ns

TDI_SU TDI setup time before TCK ↑10 - ns

TMS_H TMS hold time after TCK ↑20 - ns

TDI_H TDI hold time after TCK ↑20 - ns

TDO_CO TDO valid after TCK ↓-30ns

Table 6: Progra m m i ng Specifi c at io ns (Continued)

Symbol Parameter Min. Max. Unit

VCC Supply voltage(2) relative to GND –0.5 4.6 V

VIInput voltage(3) relativ e to GND –0.5 5.5 V

IOUT Output current, per pin –100 100 mA

TJMaximum junction temperature –40 150 °C

TSTR Storage temperature –65 150 °C

Notes:

1. Stresses above those l isted may cause malfunction or permanent damage to the device. Thi s is a st ress rating only. Func ti onal

operation at these or any other condition above those indicated in the operational and programming specification is not implied.

2. The chip supply voltage mus t rise mo notonical ly.

3. Maxim um DC under shoot belo w GND mus t b e limite d to ei ther 0 .5V or 10 mA, whiche v e r is e asier to achi ev e . Duri ng tr ansit ions , the

device pins may undershoot to –2.0V or overshoot to 7.0V, provided this over - or undershoot lasts less than 10 ns and with the

forcing current being lim ited to 200 mA.

4. External I/O volta ge may not exceed VCC by 4.6V or more, and the I/O voltage may never exceed 5.5V.

Symbol Parameter Test Conditions Min. Max. Unit

VCC Supply voltage Commercial TA = 0°C to 70°C3.03.6V

Indu strial TA = –40°C to +85°C2.73.6V

VIL Low-level inpu t vo ltage 0 0.8 V

VIH High-level input voltage 2.0 5.5 V

VOO utp ut voltage 0 VCC V

TRInput rise time - 20 ns

TFInput fall time - 20 ns

Symbol Parameter Min Max Units

TDR Data retention 20 - Years

NPE Program/erase cycles (Endurance) 1,000 - Cycles

VESD Electrostatic Disch arge (ESD) 2,000 - Volts

CoolRunner® XPLA3 CPLD

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Revision History

The following table shows the revision histor y for this docum ent.

Date Version Revision

02 /20/00 1 .0 Initial X ilin x r ele as e .

03/06 /00 1.1 Minor updates.

11/30 /00 1.2 Updated Mac roc ell numberin g, I/O pins, and avail able packag es.

02/09 /01 1.3 Updated specificat ion.