ASM5P2304A-1H-08-SR - Alliance Semiconductor

August 2004ASMP5P2304A

rev 2.0

Alliance Semiconductor

2575, Augustine Drive Santa Clara, CA Tel: 408.855.4900 Fax: 408.855.4999 www.alsc.com

Notice: The information in this document is subject to change withou

t notice.

3.3 V Zero Delay Buffer

Features

Zero input -output propagation delay,

adjustable by capacitive load on FBK input.

Multiple configurations -Refer

“ASM5P2304A Configurations Table”.

Input frequency range: 10MHz to 133MHz

Multiple low-skew outputs.

Output-output skew less than 200 ps.

Device-device skew less than 500 ps.

Two banks of four outputs.

Less than 200 ps cycle-to-cycle jitter (-1, -1H,

-5H).

Available in space saving, 8-pin 150-mil

SOIC packages and standard TSSOP.

3.3V operation.

Advanced 0.35µ CMOS technology.

Industrial temperature available.

Functional Description

ASM5P2304A is a versatile, 3.3V zero-delay buffer

designed to distribute high-speed clocks in PC,

workstation, datacom, telecom and other high-performance

applications. It is available in a 8-pin package. The part has

an on-chip PLL which locks to an input clock presented on

the REF pin. The PLL feedback is required to be driven to

FBK pin, and can be obtained from one of the outputs. The

input-to-output propagation delay is guaranteed to be less

than 250ps, and the output-to-output skew is guaranteed to

be less than 200ps.

The ASM5P2304A has two banks of two outputs each.

Multiple ASM5P2304A devices can accept the same input

clock and distribute it. In this case the skew between the

outputs of the two devices is guaranteed to be less than

500ps.

The ASM5P2304A is available in two different

configurations (Refer “ASM5P2304A Configurations Table).

The ASM5P2304A-1 is the base part, where the output

frequencies equal the reference if there is no counter in the

feedback path. The ASM5P2304A-1H is the high-drive

version of the -1 and the rise and fall times on this device

are much faster.

The ASM5P2304A-2 allows the user to obtain Ref, 1/2 X

and 2X frequencies on each output bank. The exact

configuration and output frequencies depend on which

output drives the feedback pin.

The ASM5P2304A-5H is a high-drive version with REF/2

on both banks

Block Diagram

FBK

REF PLL

CLKA1

CLKA2

CLKB1

CLKB2

Extra Divider (-2)

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ASM5P2304A Configurations

Device Feedback From Bank A Frequency Bank B Frequency

ASM5P2304A-1 Bank A or Bank BReference Reference

ASM5P2304A-1H Bank A or Bank BReference Reference

ASM5P2304A-2 Bank A Reference Reference /2

ASM5P2304A-2 Bank B2 X Reference Reference

ASM5P2304A-5H Bank A or Bank BReference /2 Reference /2

Zero Delay and Skew Control

For applications requiring zero input-output delay, all outputs must be equally loaded.

To close the feedback loop of the ASM5P2304A, the

FBK pin can be driven from any of the four available

output pins. The output driving the FBK pin will be

driving a total load of 7 pF plus any additional load

that it drives. The relative loading of this output (with

respect to the remaining outputs) can adjust the input

output delay. This is shown in the above graph.

For applications requiring zero input-output delay, all

outputs including the one providing feedback should

be equally loaded. If input-output delay adjustments

are required, use the above graph to calculate

loading differences between the feedback output and

remaining outputs. For zero output-output skew, be

sure to load outputs equally.

-30 -25 -20 -15 -10 -5 0510 15 20 25 30

-500

-1000

-1500

500

1000

1500

Output Load Difference: FBK Load -CLKA/CLKB Load (pF)

REF-Input to CLKA/CLKB Delay (ps)

REF Input to CLKA/CLKB Delay Vs Difference in Loading between FBK pin and CLKA/CLKB pins

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Pin Configuration

Pin Description for ASM5P2304A

Pin #Pin Name Description

1REF1Input reference frequency, 5V tolerant input

2CLKA12Buffered clock output, bank A

3CLKA22Buffered clock output, bank A

4GND Ground

5CLKB12Buffered clock output, bank B

6CLKB2 2Buffered clock output, bank B

7 VDD 3.3V supply

8FBK PLL feedback input

Notes:

1. Weak pull-down.

2. Weak pull-down on all outputs.

REF

CLKA1

CLKA2

CLKB1

CLKB2

VDD

GND

FBK

ASM5P2304A

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Absolute Maximum Ratings

Parameter Min Max Unit

Supply Voltage to Ground Potential -0.5 +7.0 V

DC Input Voltage (Except REF) -0.5 VDD + 0.5 V

DC Input Voltage (REF) -0.5 7 V

Storage Temperature -65 +150 ûC

Max. Soldering Temperature (10 sec) 260 ûC

Junction Temperature 150 ûC

Static Discharge Voltage

(per MIL-STD-883, Method 3015) >2000 V

Note: These are stress ratings only and functional usage is not implied. Exposure to absolute

maximum ratings for prolonged periods can affect device reliability.

Operating Conditions for ASM5P2304A Commercial Temperature Devices

Parameter Description Min Max Unit

VDD Supply Voltage 3.0 3.6 V

TAOperating Temperature (Ambient Temperature) 0 70 ûC

CLLoad Capacitance, below 100 MHz 30 pF

CLLoad Capacitance, from 100 MHz to 133 MHz 15 pF

CIN Input Capacitance37 pF

Note:

3. Applies to both Ref Clock and FBK.

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Electrical Characteristics for ASM5P2304A Commercial Temperature Devices

Parameter Description Test Conditions Min Max Unit

VIL Input LOW Voltage 0.8 V

VIH Input HIGH Voltage 2.0 V

IIL Input LOW Current VIN = 0V 50.0 µA

IIH Input HIGH Current VIN = VDD 100.0 µA

VOL Output LOW Voltage 4IOL = 8mA (-1, -2)

IOH = 12mA (-1H, -5H) 0.4 V

VOH Output HIGH Voltage 4IOL = -8mA (-1, -2)

IOH = -12mA (-1H, -5H) 2.4 V

TBD

Unloaded outputs 100MHz REF,

Select inputs at VDD or GND TBD

Unloaded outputs, 66MHz REF

(-1, -2) TBD

IDD Supply Current

Unloaded outputs, 33MHz REF

(-1, -2) TBD

Note:

4. Parameter is guaranteed by design and characterization. Not 100% tested in production.

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Switching Characteristics for ASM5P2304A Commercial Temperature Devices

Paramete

rDescription Test Conditions Min Typ Max Unit

t1Output Frequency 30-pF load, All devices 10 100 MHz

t1Output Frequency 20-pF load, -1H, -5H devices 10 133.3 MHz

t1Output Frequency 15-pF load, -1, -2 devices 10 133.3 MHz

Duty Cycle 4= (t2 / t1) * 100

(-1, -2, -1H, -5H) Measured at 1.4V, FOUT = 66.66 MHz

30-pF load 40.0 50.0 60.0 %

Duty Cycle 4= (t2 / t1) * 100

(-1, -2,-1H, -5H) Measured at 1.4V, FOUT = <50 MHz

15-pF load 45.0 50.0 55.0 %

t3Output Rise Time 4

(-1, -2) Measured between 0.8V and 2.0V

30-pF load 2.20 ns

t3Output Rise Time 4

(-1, -2) Measured between 0.8V and 2.0V

15-pF load 1.50 ns

t3Output Rise Time 4

(-1H, -5H) Measured between 0.8V and 2.0V

30-pF load 1.50 ns

t4Output Fall Time 4

(-1, -2) Measured between 2.0V and 0.8V

30-pF load 2.20 ns

t4Output Fall Time 4

(-1, -2) Measured between 2.0V and 0.8V

15-pF load 1.50 ns

t4Output Fall Time 4

(-1H, -5H) Measured between 2.0V and 0.8V

30-pF load 1.25 ns

Output-to-output skew on same bank (-1, -2) 4All outputs equally loaded 200

Output-to-output skew

(-1H, -5H) All outputs equally loaded 200

Output bank A -to- output bank B skew (-1, -

5H) All outputs equally loaded 200

Output bank A to output bank b skew (-2) All outputs equally loaded 400

t6Delay, REF Rising Edge to FBK Rising Edge 3Measured at VDD /2 0 ±250 ps

t7Device-to-Device Skew 4Measured at VDD/2 on the FBK pins of the device 0500 ps

t8Output Slew Rate4Measured between 0.8V and 2.0V using

Test Circuit #2 1V/ns

Measured at 66.67 MHz, loaded outputs,

15 pF load 175

Measured at 66.67 MHz, loaded outputs,

30 pF load 200

tJCycle-to-cycle jitter 4

(-1, -1H, -5H)

Measured at 133.3 MHz, loaded outputs,

15 pF load 100

Measured at 66.67 MHz, loaded outputs, 30pF

load 400

tJCycle-to-cycle jitter 4

(-2,) Measured at 66.67 MHz, loaded outputs,

15 pF load 375

tLOCK PLL Lock Time 4Stable power supply, valid clock presented on

REF and FBK pins 1.0 ms

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Operating Conditions for ASM5I2304A Industrial Temperature Devices

Parameter Description Min Max Unit

VDD Supply Voltage 3.0 3.6 V

TAOperating Temperature (Ambient Temperature) -40 85 ûC

CLLoad Capacitance, below 100 MHz 30 pF

CLLoad Capacitance, from 100 MHz to 133 MHz 15 pF

CIN Input Capacitance37 pF

Electrical Characteristics for ASM5I2304A Industrial Temperature Devices

Parameter Description Test Conditions Min Max Unit

VIL Input LOW Voltage 0.8 V

VIH Input HIGH Voltage 2.0 V

IIL Input LOW Current VIN = 0V 50.0 µA

IIH Input HIGH Current VIN = VDD 100.0 µA

VOL Output LOW Voltage 4IOL = 8mA (-1, -2)

IOH = 12mA (-1H, -5H) 0.4 V

VOH Output HIGH Voltage 4IOL = -8mA (-1, -2)

IOH = -12mA (-1H, -5H) 2.4 V

TBD

Unloaded outputs 100MHz REF,

Select inputs at VDD or GND TBD

Unloaded outputs, 66MHz REF

(-1, -2) TBD

IDD Supply Current

Unloaded outputs, 33MHz REF

(-1, -2) TBD

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Notice: The information in this document is subject to change without notice.

Switching Characteristics for ASM5I2304A Industrial Temperature Devices

All parameters are specified with loaded outputs

Parameter Description Test Conditions Min Typ Max Unit

t1Output Frequency 30-pF load, All devices 10 100 MHz

t1Output Frequency 20-pF load, -1H, -5H devices 10 133.3 MHz

t1Output Frequency 15-pF load, -1 and -2 devices 10 133.3 MHz

Duty Cycle 4= (t2 / t1) * 100

(-1, -2, -1H, -5H) Measured at 1.4V, FOUT = <66.66 MHz

30-pF load 40.0 50.0 60.0 %

Duty Cycle 4= (t2 / t1) * 100

(-1, -2, -1H, -5H) Measured at 1.4V, FOUT = <50 MHz

15-pF load 45.0 50.0 55.0 %

t3Output Rise Time 4

(-1, -2) Measured between 0.8V and 2.0V

30-pF load 2.50 ns

t3Output Rise Time 4

(-1, -2) Measured between 0.8V and 2.0V

15-pF load 1.50 ns

t3Output Rise Time 4

(-1H, -5H) Measured between 0.8V and 2.0V

30-pF load 1.50 ns

t4Output Fall Time 4

(-1, -2) Measured between 2.0V and 0.8V

30-pF load 2.50 ns

t4Output Fall Time 4

(-1, -2) Measured between 2.0V and 0.8V

15-pF load 1.50 ns

t4Output Fall Time 4

(-1H, -5H) Measured between 2.0V and 0.8V

30-pF load 1.25 ns

Output-to-output skew on same bank (-1, -2) 4All outputs equally loaded 200

Output-to-output skew

(-1H, -5H) All outputs equally loaded 200

Output bank A -to- output bank B skew (-1, -5H) All outputs equally loaded 200

Output bank A -to- output bank B skew (-2) All outputs equally loaded 400

t6Delay, REF Rising Edge to FBK Rising Edge 4Measured at VDD /2 0 ±250 ps

t7Device-to-Device Skew 4Measured at VDD/2 on the FBK pins of the device 0500 ps

t8Output Slew Rate4Measured between 0.8V and 2.0V using

Test Circuit #2 1V/ns

Measured at 66.67 MHz, loaded outputs,

15 pF load 180

Measured at 66.67 MHz, loaded outputs,

30 pF load 200

tJCycle-to-cycle jitter 4

(-1, -1H, -5H)

Measured at 133.3 MHz, loaded outputs,

15 pF load 100

Measured at 66.67 MHz, loaded outputs, 30pF load 400

tJCycle-to-cycle jitter 4

(-2) Measured at 66.67 MHz, loaded outputs,

15 pF load 380

tLOCK PLL Lock Time 4Stable power supply, valid clock presented on REF

and FBK pins 1.0 ms

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Switching Waveforms

Duty Cycle Timing

All Outputs Rise/Fall Time

Output -Output Skew

Input -Output Propagation Delay

Device -Device Skew

1.4 V1.4 V1.4 V

OUTPUT

2.0 V

0.8 V

3.3 V

0 V

2.0 V

0.8 V

1.4 V

OUTPUT

INPUT

OUTPUT

FBK, Device 1

FBK, Device 2

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Test Circuits



10 pF

GND

OUTPUTS

LOAD

0.1 ÿF



0.1 ÿF

GND

OUTPUTS

Test Circuit #1

Test Circuit #2

For parameter t

(output slew rate) on

1H devices

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Package Information: 8-lead (150 Mil) Molded SOIC

Dimensions in inches Dimensions in

millimeters

Symbo

Min Max Min Max

A0.053 0.069 1.35 1.75

A1 0.004 0.010 0.10 0.25

B0.013 0.022 0.33 0.53

C0.007 0.012 0.18 0.27

D0.188 0.197 4.78 5.00

E0.150 0.158 3.80 4.01

H0.228 0.244 5.80 6.20

e0.050 BSC 1.27 BSC

L0.016 0.035 0.40 0.89

 0ü 8ü 0ü 8ü



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Ordering Code Package Type Operating Range

ASM5P2304A-1-08-SR 8-pin 150-mil SOIC-TAPE & REEL Commercial

ASM5P2304A-1-08-ST 8-pin 150-mil SOIC-TUBE Commercial

ASM5I2304A-1-08-SR 8-pin 150-mil SOIC-TAPE & REEL Industrial

ASM5I2304A-1-08-ST 8-pin 150-mil SOIC-TUBE Industrial

ASM5P2304A-1H-08-SR 8-pin 150-mil SOIC-TAPE & REEL Commercial

ASM5P2304A-1H-08-ST 8-pin 150-mil SOIC-TUBE Commercial

ASM5I2304A-1H-08-SR 8-pin 150-mil SOIC-TAPE & REEL Industrial

ASM5I2304A-1H-08-ST 8-pin 150-mil SOIC-TUBE Industrial

ASM5P2304A-2-08-SR 8-pin 150-mil SOIC-TAPE & REEL Commercial

ASM5P2304A-2-08-ST 8-pin 150-mil SOIC-TUBE Commercial

ASM5I2304A-2-08-SR 8-pin 150-mil SOIC-TAPE & REEL Industrial

ASM5I2304A-2-08-ST 8-pin 150-mil SOIC-TUBE Industrial

ASM5P2304A-5H-08-SR 8-pin 150-mil SOIC-TAPE & REEL Commercial

ASM5P2304A-5H-08-ST 8-pin 150-mil SOIC-TUBE Commercial

ASM5I2304A-5H-08-SR 8-pin 150-mil SOIC-TAPE & REEL Industrial

ASM5I2304A-5H-08-ST 8-pin 150-mil SOIC-TUBE Industrial

Licensed under US patent Nos 5,488,627, 6,646,463 and 5,631,920.

Preliminary datasheet. Specification subject to change without notice.

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DEVICE ORDERING INFORMATION Package Suffix

ASM5P2304A F - 08-OR

* * * NOTE: Industry Standard Part Numbers May Be used

That Differ from this part numbering system...

Alliance Semiconductor

Mixed Signal Product

X= Automotive I= Industrial P or n/c = Commercial

1 = reserved 6 = Power Management * * *

2 = Non PLL based 7 = Power Management * * *

3 = EMI Reduction 8 = Power Management * * *

4 = DDR support products 9 = Hi Performance

5 = STD Zero Delay Buffer 0 = reserved

PART NUMBER

OR = SOT23/ T/R SR = SOIC,T/R

TT = TSSOP, TUBE JT = SSOP, TUBE

TR = TSSOP, T/R JR = SSOP, T/R

VT = TVSOP,TUBE QR = QFN, T/R

VR = TVSOP, T/R QT = QFN, TUBE

ST = SOIC, TUBE BT = BGA, TUBE

BR = BGA, T/R

F = Pb FREE

DEVICE PIN COUNT

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data at any time, without notice. If the product described herein is under development, significant changes to these

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Alliance Semiconductor Corporation

2595, Augustine Drive,

Santa Clara, CA 95054

Tel# 408-855-4900

Fax: 408-855-4999

www.alsc.com

Note: This product utilizes US# 6,646,463

Impedance Emulator Patent issued to Dan Hariton

/ Alliance Semiconductor, dated 11-11-2003

Part Number: ASM5P2304A

Document Version: 2.0 8_30_2004

Use the chart below for device ordering

note Lead Free Option…