TPS2041B-EP SLVSAX8 - SEPTEMBER 2011 www.ti.com CURRENT-LIMITED POWER-DISTRIBUTION SWITCH Check for Samples: TPS2041B-EP FEATURES APPLICATIONS * * * * * * 1 * * * * * * * * * 70-m High-Side MOSFET 500-mA Continuous Current Thermal and Short-Circuit Protection Current Limit: 0.45 A (Min), 1.55 A (Max) Operating Range: 2.7 V to 5.5 V 0.6-ms Typical Rise Time Undervoltage Lockout Deglitched Fault Report (OC) No OC Glitch During Power Up Maximum Standby Supply Current: 1 A Bidirectional Switch ESD Protection Level Per AEC-Q100 Classification UL Recognized, File Number E169910 Heavy Capacitive Loads Short-Circuit Protection SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS * * * * * * * Controlled Baseline One Assembly/Test Site One Fabrication Site Available in Military (-55C/125C) Temperature Range Extended Product Life Cycle Extended Product-Change Notification Product Traceability DBV PACKAGE (TOP VIEW) OUT 1 GND 2 OC 3 5 IN 4 EN DESCRIPTION The TPS2041B power-distribution switch is intended for applications where heavy capacitive loads and short circuits are likely to be encountered. This device incorporates 70-m N-channel MOSFET power switches for power-distribution systems that require multiple power switches in a single package. Each switch is controlled by a logic enable input. Gate drive is provided by an internal charge pump designed to control the power-switch rise times and fall times to minimize current surges during switching. The charge pump requires no external components and allows operation from supplies as low as 2.7 V. When the output load exceeds the current-limit threshold or a short is present, the device limits the output current to a safe level by switching into a constant-current mode, pulling the overcurrent (OC) logic output low. When continuous heavy overloads and short circuits increase the power dissipation in the switch, causing the junction temperature to rise, a thermal protection circuit shuts off the switch to prevent damage. Recovery from a thermal shutdown is automatic once the device has cooled sufficiently. Internal circuitry ensures that the switch remains off until valid input voltage is present. This power-distribution switch is designed to set current limit at 1 A (typ). 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2011, Texas Instruments Incorporated TPS2041B-EP SLVSAX8 - SEPTEMBER 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) TJ ENABLE NO. OF SWITCHES PACKAGE (2) ORDERABLE PART NUMBER TOP-SIDE MARKING VID NUMBER -55C to 125C Active low Single SOT-23 - DBV TPS2041BMDBVTEP PXAM V62/1162001XE (1) (2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 80 m, single Figure 1. TPS2041B Switch at 500 mA ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range unless otherwise noted VI(IN) Input voltage range (IN) (2) -0.3 V to 6 V VO(OUT) Output voltage range (OUT) (2) -0.3 V to 6 V VI(EN) Input voltage range (EN) -0.3 V to 6 V VI(OC) Voltage range (OC) -0.3 V to 6 V IO(OUT) Continuous output current Internally limited Continuous power dissipation at 125C 182 mW JC Thermal resistance, junction-to-case 55C/W TJ Operating virtual-junction temperature range Tstg Storage temperature range -55C to 135C -65C to 150C Lead temperature, soldering Electrostatic discharge (ESD) protection 1,6 mm (1/16 in) from case for 10 s 260C Human-Body Model (HBM) (H2) 2500 V Machine Model (MM) (M0) 50 V Charged-Device Model (CDM) (C5) (1) (2) 1500 V Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. RECOMMENDED OPERATING CONDITIONS MIN MAX 2.7 5.5 UNIT VI(IN) Input voltage (IN) VI(EN) Input voltage (EN) 0 5.5 V IO(OUT) Continuous output current (OUT) 0 500 mA TJ Operating virtual-junction temperature -55 125 C 2 Submit Documentation Feedback V Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): TPS2041B-EP TPS2041B-EP SLVSAX8 - SEPTEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS over recommended operating junction temperature range, VI(IN) = 5.5 V, IO = 0.5 A, VI(EN) = 0 V (unless otherwise noted) TEST CONDITIONS (1) PARAMETER MIN TYP MAX UNIT Power Switch rDS(on) tr tf Static drain-source on-state resistance, 5-V or 3.3-V operation VI(IN) = 5 V or 3.3 V, IO = 0.5 A Static drain-source on-state resistance, 2.7-V operation VI(IN) = 2.7 V, IO = 0.5 A Rise time, output Fall time, output -55C TJ 125C 70 135 m -55C TJ 125C 75 VI(IN) = 5.5 V VI(IN) = 2.7 V VI(IN) = 5.5 V 150 0.6 CL = 1 F, RL = 10 0.4 TJ = 25C ms 0.2 VI(IN) = 2.7 V 0.2 Enable Input (EN) VIH High-level input voltage 2.7 V VI(IN) 5.5 V VIL Low-level input voltage 2.7 V VI(IN) 5.5 V II Input current VI(EN) = 0 V or 5.5 V ton Turn-on time CL = 100 F, RL = 10 3 ms toff Turn-off time CL = 100 F, RL = 10 6 ms 2 V -1 0.8 V 1 A Current Limit VI(IN) = 5 V, OUT connected to GND, device enabled into short-circuit TJ = 25C 0.65 1 1.3 -55C TJ 125C 0.45 1 1.55 Supply current, low-level output No load on OUT, VI(EN) = 5.5 V or VI(EN) = 0 V TJ = 25C 0.5 1 -55C TJ 125C 0.5 5 Supply current, high-level output No load on OUT, VI(EN) = 0 V or VI(EN) = 5.5 V TJ = 25C 43 60 -55C TJ 125C 43 70 Leakage current OUT connected to ground, VI(EN) = 5.5 V or VI(EN) = 0 V -55C TJ 125C 1 A Reverse leakage current VI(OUT) = 5.5 V, IN = ground TJ = 25C 0 A IOS Short-circuit output current A Supply Current A A Undervoltage Lockout Low-level input voltage, IN 2 Hysteresis, IN TJ = 25C 2.5 75 V mV Overcurrent (OC) Output low voltage, VOL(/OC) IO(OC) = 5 mA Off-state current VO(OC) = 5 V or 3.3 V OC deglitch Thermal Shutdown OC assertion or deassertion 3 V 1 A 16 ms (2) Thermal shutdown threshold 135 Recovery from thermal shutdown 125 Hysteresis (1) (2) 8 0.4 C C 10 C Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be accounted for separately. The thermal shutdown only reacts under overcurrent conditions. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): TPS2041B-EP 3 TPS2041B-EP SLVSAX8 - SEPTEMBER 2011 www.ti.com DEVICE INFORMATION Terminal Functions TERMINAL NAME I/O NO. I DESCRIPTION EN 4 GND 2 Enable input, logic low turns on power switch IN 5 I Input voltage OC 3 O Overcurrent, open-drain output, active low OUT 1 O Power-switch output Ground Functional Block Diagram (See Note A) CS IN OUT Charge Pump EN Driver Current Limit OC UVLO GND A. 4 Thermal Sense Deglitch CS = Current sense Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): TPS2041B-EP TPS2041B-EP SLVSAX8 - SEPTEMBER 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION OUT RL tf tr CL VO(OUT) 90% 10% 90% 10% TEST CIRCUIT 50% VI(EN) 50% toff ton VO(OUT) 50% VI(EN) 90% 50% toff ton 90% VO(OUT) 10% 10% VOLTAGE WAVEFORMS Figure 2. Test Circuit and Voltage Waveforms RL = 10 W, CL = 1 mF TA = 255C VI(EN) VI(EN) 5 V/div VI(EN) VI(EN) 5 V/div RL = 10 W, CL = 1 mF TA = 255C VO(OUT) 2 V/div VO(OUT) 2 V/div t - Time - 500 ms/div t - Time - 500 ms/div Figure 3. Turn-On Delay and Rise Time With 1-F Load Figure 4. Turn-Off Delay and Fall Time With 1-F Load Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): TPS2041B-EP 5 TPS2041B-EP SLVSAX8 - SEPTEMBER 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) RL = 10 W, CL = 100 mF TA = 255C VI(EN) VI(EN) 5 V/div VI(EN) VI(EN) 5 V/div RL = 10 W, CL = 100 mF TA = 255C VO(OUT) 2 V/div VO(OUT) 2 V/div t - Time - 500 ms/div t - Time - 500 ms/div Figure 5. Turn-On Delay and Rise Time With 100-F Load Figure 6. Turn-Off Delay and Fall Time With 100-F Load VI = 5 V, RL = 10 W, TA = 255C VI(EN) VI(EN) 5 V/div VI(EN) VI(EN) 5 V/div 220 mF 470 mF IO(OUT) 500 mA/div IO(OUT) 500 mA/div 100 mF t - Time - 500 ms/div t - Time - 500 ms/div Figure 7. Short-Circuit Current, Device Enabled Into Short 6 Figure 8. Inrush Current With Different Load Capacitance Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): TPS2041B-EP TPS2041B-EP SLVSAX8 - SEPTEMBER 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) VO(OC) 2 V/div VO(OC) 2 V/div IO(OUT) 500 mA/div IO(OUT) 500 mA/div t - Time - 2 ms/div Figure 9. 3- Load Connected to Enabled Device t - Time - 2 ms/div Figure 10. 2- Load Connected to Enabled Device Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): TPS2041B-EP 7 TPS2041B-EP SLVSAX8 - SEPTEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS TURN-ON TIME vs INPUT VOLTAGE TURN-OFF TIME vs INPUT VOLTAGE 1.0 3.3 CL = 100 mF, RL = 10 W, TA = 255C 0.9 0.8 CL = 100 mF, RL = 10 W, TA = 255C 3.2 Turnoff Time - ms Turnon Time - ms 0.7 0.6 0.5 0.4 3.1 3 0.3 0.2 2.9 0.1 0 2 3 4 5 VI - Input Voltage - V 2.8 6 3 4 5 6 VI - Input Voltage - V Figure 11. Figure 12. RISE TIME vs INPUT VOLTAGE FALL TIME vs INPUT VOLTAGE 0.25 0.6 CL = 1 mF, RL = 10 W, TA = 255C CL = 1 mF, RL = 10 W, TA = 255C 0.5 0.2 0.4 Fall Time - ms Rise Time - ms 2 0.3 0.15 0.1 0.2 0.05 0.1 0 2 3 4 5 VI - Input Voltage - V 6 0 2 Figure 13. 8 3 4 5 VI - Input Voltage - V 6 Figure 14. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): TPS2041B-EP TPS2041B-EP SLVSAX8 - SEPTEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) SUPPLY CURRENT, OUTPUT ENABLED vs JUNCTION TEMPERATURE SUPPLY CURRENT, OUTPUT DISABLED vs JUNCTION TEMPERATURE 0.5 VI = 5.5 V 60 VI = 5 V 50 40 30 20 VI = 3.3 V 10 0 -55 -25 VI = 2.7 V 50 100 125 25 75 TJ - Junction Temperature - C 0 VI = 5.5 V 0.45 VI = 5 V 0.4 0.35 0.3 VI = 2.7 V VI = 3.3 V 0.25 0.2 0.15 0.1 0.05 0 -55 150 -25 75 25 0 50 100 TJ - Junction Temperature - C 125 Figure 15. Figure 16. STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE SHORT-CIRCUIT OUTPUT CURRENT vs JUNCTION TEMPERATURE 150 1.08 120 IO = 0.5 A 1.06 VI = 2.7 V 100 I OS - Short-Circuit Output Current - A r DS(on) - Static Drain-Source On-State Resistance - m II (IN) - Supply Current, Output Disabled - A I I (IN) - Supply Current, Output Enabled - A 70 80 VI = 3.3 V 60 40 VI = 5 V 20 0 -55 -25 75 0 25 50 100 TJ - Junction Temperature - C 125 150 VI = 2.7 V VI = 3.3 V 1.04 1.02 1.0 0.98 VI = 5 V 0.96 VI = 5.5 V 0.94 0.92 0.9 -55 -25 Figure 17. 75 0 25 50 100 TJ - Junction Temperature - C 125 150 Figure 18. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): TPS2041B-EP 9 TPS2041B-EP SLVSAX8 - SEPTEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) THRESHOLD TRIP CURRENT vs INPUT VOLTAGE UNDERVOLTAGE LOCKOUT vs JUNCTION TEMPERATURE 2.3 2 TA = 255C Load Ramp = 1 A/10 ms UVLO Rising UVLO - Undervoltage Lockout - V Threshold Trip Current - A 1.8 1.6 1.4 1.2 1 2.5 3 3.5 4 4.5 5 5.5 6 2.26 2.22 UVLO Falling 2.18 2.14 2.1 -55 -25 VI - Input Voltage - V 75 0 25 50 100 TJ - Junction Temperature - C Figure 19. 125 150 Figure 20. CURRENT-LIMIT RESPONSE vs PEAK CURRENT 100 Current-Limit Response - s VI = 5 V, TA = 255C 80 60 40 20 0 0 10 2.5 5 7.5 Peak Current - A Figure 21. Submit Documentation Feedback 10 12.5 Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): TPS2041B-EP TPS2041B-EP SLVSAX8 - SEPTEMBER 2011 www.ti.com APPLICATION INFORMATION Power-Supply Considerations TPS2041B 5 Power Supply 2.7 V to 5.5 V IN OUT 0.1 F 1 Load 0.1 F 3 4 22 F OC EN GND 2 Figure 22. Typical Application A 0.01-F to 0.1-F ceramic bypass capacitor between IN and GND, close to the device, is recommended. Placing a high-value electrolytic capacitor on the output pin(s) is recommended when the output load is heavy. This precaution reduces power-supply transients that may cause ringing on the input. Additionally, bypassing the output with a 0.01-F to 0.1-F ceramic capacitor improves the immunity of the device to short-circuit transients. Overcurrent A sense FET is employed to check for overcurrent conditions. Unlike current-sense resistors, sense FETs do not increase the series resistance of the current path. When an overcurrent condition is detected, the device maintains a constant output current and reduces the output voltage accordingly. Complete shutdown occurs only if the fault is present long enough to activate thermal limiting. Three possible overload conditions can occur. In the first condition, the output has been shorted before the device is enabled or before VI(IN) has been applied (see Figure 15). The TPS2041B senses the short and immediately switches into a constant-current output. In the second condition, a short or an overload occurs while the device is enabled. At the instant the overload occurs, high currents may flow for a short period of time before the current-limit circuit can react. After the current-limit circuit has tripped (reached the overcurrent trip threshold), the device switches into constant-current mode. In the third condition, the load has been gradually increased beyond the recommended operating current. The current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is exceeded (see Figure 16). The TPS2041B is capable of delivering current up to the current-limit threshold without damaging the device. Once the threshold has been reached, the device switches into its constant-current mode. OC Response The OC open-drain output is asserted (active low) when an overcurrent or overtemperature shutdown condition is encountered after a 10-ms deglitch timeout. The output remains asserted until the overcurrent or overtemperature condition is removed. Connecting a heavy capacitive load to an enabled device can cause a momentary overcurrent condition; however, no false reporting on OC occurs due to the 10-ms deglitch circuit. The TPS2041B is designed to eliminate false overcurrent reporting. The internal overcurrent deglitch eliminates the need for external components to remove unwanted pulses. OC is not deglitched when the switch is turned off due to an overtemperature shutdown. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): TPS2041B-EP 11 TPS2041B-EP SLVSAX8 - SEPTEMBER 2011 www.ti.com V+ TPS2041B GND IN Rpullup OC OUT EN Figure 23. Typical Circuit for the OC Pin Power Dissipation and Junction Temperature The low on-resistance on the N-channel MOSFET allows the small surface-mount packages to pass large currents. The thermal resistances of these packages are high compared to those of power packages; it is good design practice to check power dissipation and junction temperature. Begin by determining the rDS(on) of the N-channel MOSFET relative to the input voltage and operating temperature. As an initial estimate, use the highest operating ambient temperature of interest and read rDS(on) from Figure 17. Using this value, the power dissipation per switch can be calculated by: PD = rDS(on) x I2 Multiply this number by the number of switches being used. This step renders the total power dissipation from the N-channel MOSFETs. Finally, calculate the junction temperature: TJ = PD x RJA + TA Where: TA = Ambient temperature (C) RJA = Thermal resistance PD = Total power dissipation based on number of switches being used. Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees, repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally sufficient to get a reasonable answer. Thermal Protection Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for extended periods of time. The TPS2041B implements a thermal sensing to monitor the operating junction temperature of the power distribution switch. In an overcurrent or short-circuit condition, the junction temperature rises due to excessive power dissipation. Once the die temperature rises to approximately 140C due to overcurrent conditions, the internal thermal sense circuitry turns the power switch off, thus preventing the power switch from damage. Hysteresis is built into the thermal sense circuit, and after the device has cooled approximately 10C, the switch turns back on. The switch continues to cycle in this manner until the load fault or input power is removed. The OC open-drain output is asserted (active low) when an overtemperature shutdown or overcurrent occurs. Undervoltage Lockout (UVLO) The UVLO ensures that the power switch is in the off state at power up. Whenever the input voltage falls below approximately 2 V, the power switch is quickly turned off. This facilitates the design of hot-insertion systems where it is not possible to turn off the power switch before input power is removed. The UVLO also keeps the switch from being turned on until the power supply has reached at least 2 V, even if the switch is enabled. On reinsertion, the power switch is turned on, with a controlled rise time to reduce EMI and voltage overshoots. 12 Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): TPS2041B-EP TPS2041B-EP SLVSAX8 - SEPTEMBER 2011 www.ti.com Universal Serial Bus (USB) Applications The universal serial bus (USB) interface is a 12-Mb/s, or 1.5-Mb/s, multiplexed serial bus designed for low-to-medium bandwidth PC peripherals (e.g., keyboards, printers, scanners, and mice). The four-wire USB interface is conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for differential data, and two lines are provided for 5-V power distribution. USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power is distributed through more than one hub across long cables. Each function must provide its own regulated 3.3 V from the 5-V input or its own internal power supply. The USB specification defines the following five classes of devices, each differentiated by power-consumption requirements: * Hosts/self-powered hubs (SPHs) * Bus-powered hubs (BPHs) * Low-power bus-powered functions * High-power bus-powered functions * Self-powered functions Self-powered and bus-powered hubs distribute data and power to downstream functions. The TPS2041B can provide power-distribution solutions to many of these classes of devices. Hosts/Self-Powered Hubs and Bus-Powered Hubs Hosts and self-powered hubs have a local power supply that powers the embedded functions and the downstream ports (see Figure 24). This power supply must provide from 5.25 V to 4.75 V to the board side of the downstream connection under full-load and no-load conditions. Hosts and SPHs are required to have current-limit protection and must report overcurrent conditions to the USB controller. Typical SPHs are desktop PCs, monitors, printers, and stand-alone hubs. Power Supply 3.3 V Downstream USB Ports 5V TPS2041B 5 IN D+ D- 1 0.1 F VBUS OUT 0.1 F 3 USB Control 4 120 F GND OC EN GND 2 Figure 24. Typical One-Port USB Host/Self-Powered Hub Bus-powered hubs obtain all power from upstream ports and often contain an embedded function. The hubs are required to power up with less than one unit load. The BPH usually has one embedded function, and power is always available to the controller of the hub. If the embedded function and hub require more than 100 mA on power up, the power to the embedded function may need to be kept off until enumeration is completed. This can be accomplished by removing power or by shutting off the clock to the embedded function. Power switching the embedded function is not necessary if the aggregate power draw for the function and controller is less than one unit load. The total current drawn by the bus-powered device is the sum of the current to the controller, the embedded function, and the downstream ports, and it is limited to 500 mA from an upstream port. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): TPS2041B-EP 13 TPS2041B-EP SLVSAX8 - SEPTEMBER 2011 www.ti.com Low-Power and High-Power Bus-Powered Functions Both low-power and high-power bus-powered functions obtain all power from upstream ports; low-power functions always draw less than 100 mA; high-power functions must draw less than 100 mA at power up and can draw up to 500 mA after enumeration. If the load of the function is more than the parallel combination of 44 and 10 F at power up, the device must implement inrush current limiting (see Figure 25). Power Supply 3.3 V D+ D- VBUS TPS2041B 5 10 F IN 0.1 F OUT GND 1 0.1 F 3 USB Control 4 10 F Internal Function OC EN GND 2 Figure 25. High-Power Bus-Powered Function USB Power-Distribution Requirements USB can be implemented in several ways, and, regardless of the type of USB device being developed, several power-distribution features must be implemented. * Hosts/self-powered hubs must: - Current-limit downstream ports - Report overcurrent conditions on USB VBUS * Bus-powered hubs must: - Enable/disable power to downstream ports - Power up at <100 mA - Limit inrush current (<44 and 10 F) * Functions must: - Limit inrush currents - Power up at <100 mA The feature set of the TPS2041B allows them to meet each of these requirements. The integrated current-limiting and overcurrent reporting is required by hosts and self-powered hubs. The logic-level enable and controlled rise times meet the need of both input and output ports on bus-powered hubs, as well as the input ports for bus-powered functions (see Figure 26). 14 Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): TPS2041B-EP TPS2041B-EP SLVSAX8 - SEPTEMBER 2011 www.ti.com TUSB2046 Hub Controller Upstream Port SN75240 BUSPWR A C B D GANGED D+ D- DP0 DP1 DM0 DM1 Tie to TPS2041B EN Input D+ GND IN 5V DM2 5-V Power Supply EN DM3 D+ A C B D 1 F TPS76333 D- SN75240 Ferrite Beads GND DP4 IN 0.1 F 4.7 F 5V 33 F (see Note A) DP3 OUT 3.3 V 4.7 F DGND SN75240 DP2 OC Ferrite Beads A C B D TPS2041B Downstream Ports DM4 VCC 5V TPS2041B GND GND PWRON1 EN OVRCUR1 OC 33 F (see Note A) IN 0.1 F OUT D+ TPS2041B 48-MHz Crystal XTAL1 PWRON2 EN OVRCUR2 OC D- IN Ferrite Beads 0.1 F GND OUT Tuning Circuit XTAL2 OCSOFF 5V TPS2041B PWRON3 EN OVRCUR3 OC 33 F (see Note A) IN 0.1 F OUT GND D+ TPS2041B PWRON4 EN OVRCUR4 OC Ferrite Beads IN DGND 0.1 F OUT 5V 33 F (see Note A) A. USB rev 1.1 requires 120 F per hub. Figure 26. Hybrid Self-Powered/Bus-Powered Hub Implementation Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): TPS2041B-EP 15 TPS2041B-EP SLVSAX8 - SEPTEMBER 2011 www.ti.com Generic Hot-Plug Applications In many applications, it may be necessary to remove modules or PC boards while the main unit is still operating. These are considered hot-plug applications. Such implementations require the control of current surges seen by the main power supply and the card being inserted. The most effective way to control these surges is to limit and slowly ramp the current and voltage being applied to the card, similar to the way in which a power supply normally turns on. Due to the controlled rise times and fall times of the TPS2041B, these devices can be used to provide a softer startup to devices being hot-plugged into a powered system. The UVLO feature of the TPS2041B also ensures that the switch is off after the card has been removed, and that the switch is off during the next insertion. The UVLO feature ensures a soft start with a controlled rise time for every insertion of the card or module. PC Board Overcurrent Response TPS2041B OC GND Power Supply 2.7 V to 5.5 V 1000 F Optimum 0.1 F IN EN Block of Circuitry OUT Figure 27. Typical Hot-Plug Implementation By placing the TPS2041B between the VCC input and the rest of the circuitry, the input power reaches these devices first after insertion. The typical rise time of the switch is approximately 1 ms, providing a slow voltage ramp at the output of the device. This implementation controls system surge currents and provides a hot-plugging mechanism for any device. DETAILED DESCRIPTION Power Switch The power switch is an N-channel MOSFET with a low on-state resistance. Configured as a high-side switch, the power switch prevents current flow from OUT to IN and IN to OUT when disabled. The power switch supplies a minimum current of 500 mA. Charge Pump An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires little supply current. Driver The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and fall times of the output voltage. Enable (EN) The logic enable pin disables the power switch and the bias for the charge pump, driver, and other circuitry to reduce the supply current. The supply current is reduced to less than 1 A or 2 A when a logic high is present on EN. A logic zero input on EN restores bias to the drive and control circuits and turns the switch on. The enable input is compatible with both TTL and CMOS logic levels. 16 Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): TPS2041B-EP TPS2041B-EP SLVSAX8 - SEPTEMBER 2011 www.ti.com Overcurrent (OC) The OC open-drain output is asserted (active low) when an overcurrent or overtemperature condition is encountered. The output remains asserted until the overcurrent or overtemperature condition is removed. A 10-ms deglitch circuit prevents the OC signal from oscillation or false triggering. If an overtemperature shutdown occurs, the OC is asserted instantaneously. Current Sense A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry sends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power FET into its saturation region, which switches the output into a constant-current mode and holds the current constant while varying the voltage on the load. Thermal Sense The TPS2041B implements a thermal sensing to monitor the operating temperature of the power distribution switch. In an overcurrent or short-circuit condition, the junction temperature rises. When the die temperature rises to approximately 140C due to overcurrent conditions, the internal thermal sense circuitry turns off the switch, thus preventing the device from damage. Hysteresis is built into the thermal sense, and after the device has cooled approximately 10 degrees, the switch turns back on. The switch continues to cycle off and on until the fault is removed. The open-drain false reporting output (OC) is asserted (active low) when an overtemperature shutdown or overcurrent occurs. Undervoltage Lockout (UVLO) A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V, a control signal turns off the power switch. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): TPS2041B-EP 17 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (C) Top-Side Markings (3) (4) TPS2041BMDBVTEP ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 PXAM V62/11620-01XE ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 PXAM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. 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OTHER QUALIFIED VERSIONS OF TPS2041B-EP : Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 * Catalog: TPS2041B * Automotive: TPS2041B-Q1 NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 27-Sep-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS2041BMDBVTEP Package Package Pins Type Drawing SPQ SOT-23 250 DBV 5 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 178.0 9.0 Pack Materials-Page 1 3.23 B0 (mm) K0 (mm) P1 (mm) 3.17 1.37 4.0 W Pin1 (mm) Quadrant 8.0 Q3 PACKAGE MATERIALS INFORMATION www.ti.com 27-Sep-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS2041BMDBVTEP SOT-23 DBV 5 250 180.0 180.0 18.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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