FL1043 - Advanced Micro Devices

FINAL

Publication# 16235 Rev: EAmendment/0

Issue Date: May 2000

Am79C940

Media Access Controller for Ethern et (MACE™)

DISTINCTIVE CHARACTERISTICS

■Integrated Controller w ith Manch ester

encoder/decoder a nd 10BAS E-T tran sceive r

and AUI port

■Supports IEEE 802.3/ANSI 8802-3 and Ethernet

standards

■84-pin PLCC and 100-pin PQFP Packages

■80-pin Thin Quad Flat Pack (TQFP) package

available for space critical applications such as

PCMCIA

■Modular architecture allows easy tuning to

specific applications

■High speed, 16-bit synchronous host system

interface with 2 or 3 cycles/transfer

■Individual transmit (136 byte) and receive (128

byte) FlFOs provide increase of system latency

and support the following features:

— Automatic retransmission with no FIFO

reload

— Automatic receive stripping and transmit

padding (individually programmable)

— Automatic runt packet rejection

— Automatic deletion of collision frames

— Automatic retransmission with no FIFO

reload

■Direct slave access to all on board

configuration/status registers and transmit/

receive FlFOs

■Direct FIFO read/write access for simple

interface to DMA controllers or l/O processors

■Arbitrary byte alignment and little/big endian

memory interface supported

■Internal/external loopback capabilities

■External Address Detection Interface (EADI)

for external hardware address filtering in

bridge/router applications

■JTAG Boundary Scan (IEEE 1149.1) test access

port interface for board level prod uction test

■Integrated Manchester Encoder/Decoder

■Digital Attachment Interface (DAI) allows

by-passing of differential Attachment Unit

Interface (AUI)

■Supports the following types of network

interface:

— AUI to external 10BASE2, 10BASE5 or

10BASE- F MAU

— DAI port to external 10BASE2, 10BASE5,

10BASE-T, 10BASE-F MAU

— General Purpose Serial Interface (GPSI) to

external encoding/decoding scheme

— Internal 10BASE-T transceiver with

automatic selection of 10BASE-T or AUI port

■Sleep mode allows reduced power consump-

tion for critical battery powered applications

■5 MHz-25 MHz system clock speed

■Support for operation in industrial temperature

range (–40°C to +85°C) available in all three

packages

GENERAL DESCRIPTION

The Media Access Controller for Ethernet (MACE) chip

is a CMOS VLSI d evice designed to provide flexibility

in customized LAN design. The MACE device is specif-

ically designed to ad dress a pplication s where multi ple

I/O peripherals are present, and a centralized or sys-

tem specific DMA is required. The high speed, 16-bit

synchronous system interface is optimized for an exter-

nal DMA or I/O processor system, and is similar to

many existing peripheral devices, such as SCSI and

serial link controllers.

The MACE device is a slave register based peripheral.

All transfers to and from the system are performed

using simple memory or I/O read and write commands.

In conjunction with a user defined DMA engine, the

MACE chip provides an IEEE 802.3 interface tailored

to a speci fic ap plicati on. Its s uperi or modul ar arch itec-

ture and versatile system interface allow the MACE

device to be configured as a stand-alone device or

as a connectivity cell incorporated into a larger,

integrated system.

2 Am79C940

The MACE device p rovides a comp lete Et hernet nod e

solution with an integrated 10BASE-T transceiver, and

supports up to 25-MHz system clocks. The MACE

device embodies the Media Access Control (MAC)

and Physical Signaling (PLS) sub-layers of the IEEE

802.3 stan dar d, and pr ovid es an IEE E defi ned A ttach-

ment Unit Interface (AUI) for coupling to an external

Medium A ttachment Unit (MAU) . The MACE device is

compliant with 10BASE2, 10BASE5, 10BASE-T, and

10BASE-F transceivers.

Additional features also enhance over-all system

design. The individual transmit and receive FIFOs

optimize system overhead, providing substantial

latency during pack et trans missio n and rece ption, and

minimizing intervention during normal network error

recovery . The integrated Manchester encoder/decoder

eliminates the need for an external Serial Interface

Adapter (SIA) in the node system. If support for an

external encoding/decoding scheme is desired, the

General Purpose Ser ial Interface ( GPSI) allows direct

access to/from the MAC. In addition, the Digital Attach-

ment Interface (DAI), which is a simplified electrical

attachment specification, allows implementation of

MAUs that do not require DC isolation between the

MAU and DTE. The DAI port can also be used to

indicate transmit, receive, or collision status by

conne cting LEDs to the po rt. The MA CE device also

provides an External Address Detection Interface

(EADI) to allow external hardware address filtering in

internet working applications.

The Am79C940 MACE chip is offered in a Plastic

Leadless Chip Carrier (84-pin PLCC), a Plastic Quad

Flat Package (100-pin PQFP), and a Thin Quad Flat

Pack age (T QFP 80 -p in ). Th er e a re se ve ra l smal l f u nc -

tional and physical differences between the 80-pin

TQFP and the 84-pin PLCC and 100-pin PQFP config-

urations. Because of the smaller number of pins in the

TQFP configuration versus the PLCC configuration,

four pins are not bonded out. Though the die is identical

in all three package configurations, the removal of

these four pins does cause some functionality differ-

ences between the TQFP and the PLCC and PQFP

configurations. Depending on the application, the

removal of these pins will or will not have an effect.

(See section: “Pins Removed for TQFP Package and

Their Effe cts.)

With the rise of embedded networking applications op-

erating in harsh environments where temperatures

may exce ed the normal com mercial temperatu re (0°C

to +70°C) wi ndow, an indus trial tempe rature (-40 °C to

+85°C) version is available in all three packages; 84-

pin PLCC, 100-pin PQFP and 80-pin TQFP. The indus-

trial temperature version of the MACE Ethernet control-

ler is characterized across the industrial temperature

range (-40°C to +85°C) within the published power

supply specificatio n (4.75 V to 5.2 5 V; i.e., ±5% VCC).

Thus, conformance of MACE performance over this

temperature range is guaranteed by the design and

characterization monitor.

Am79C940 3

BLOCK DIAGRAM

C16235D-1

EADI Port

XTAL2

EADI

Port

Control

AUI

Port

10BASE-T

MAU

DAI

Port

GPSI

Port

DXCVR

CLSN

SRDCLK

SRD

SF/BD

EAM/R

DO±

DI±

CI±

TXD±

TXP±

RXD

RXPOL

TXDAT±

TXEN

RXDAT

RXCRS

STDCLK

TXDAT+

TXEN

SRDCLK

RXDAT

RXCRS

CLSN

AUI

10BASE-T

DAI Port

GPSI

R/W

DBUS 15–0

ADD 4–0

Bus

Interface

Unit

EDSEL

SCLK

INTR

BE 1–0

TDTREQ

TCK

RDTREQ

EOF

DTV

FDS

SLEEP

RESET

RCV FIFO

XMT FIFO

JTAG

PORT CNTRL

FIFO

Control

Command

& Status

Registers

802.3

MAC

Core

TDI

TMS

TDO

XTAL1

Notes:

1. Only one of the network ports AUI, 10BASE-T, DAI port or GPSI can be active at any time. Some shared signals are

active regardless of which network port is active, and some are reconfigured.

2. The EADI port is active at all times.

LNKST

4 Am79C940
TABLE OF CONTENTS
AM79C940 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
GENERAL DESCRIPTION  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
BLOCK DIAGRAM  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
TABLE OF CONTENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
CONNECTION DIAGRAMS PL 084 PLCC PACKAGE  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
CONNECTION DIAGRAMS PQR100 PQFP PACKAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
CONNECTION DIAGRAMS PQT080 TQFP PACKAGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Standard Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
PIN/PACKAGE SUMMARY (PLCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
PIN  DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Network Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Attachment Unit Interface (AUI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
CI+/CI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
DI+/DI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
DO+/DO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Digital Attachment Interface (DAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
TXDAT+/TXDAT–. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
TXEN/TXEN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Transmit Enable (Output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
RXDAT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
RXCRS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
DXCVR  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
10BASE-T INTERFACE  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
TXD+, TXD– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
TXP+, TXP–. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
RXD+, RXD– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
LNKST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
RXPOL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
General Purpose Serial Interface (GPSI)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
STDCLK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
CLSN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
External Address Detection Interface  (EADI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
SF/BD  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
SRD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
EAM/R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
SRDCLK  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
HOST SYSTEM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
DBUS15-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
ADD4-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
R/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
RDTREQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
TDTREQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
FDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
DTV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
EOF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
BE1–0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
CS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
INTR  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
RESET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
SCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
EDSEL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
IEEE 1149.1 TEST ACCESS PORT  (TAP)  INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
TCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Am79C940 5
TMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
TDI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
TDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
GENERAL INTERFACE  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
XTAL1  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
XTAL2  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
SLEEP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
DVDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
DVSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
AVDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
PIN FUNCTIONS NOT AVAILABLE WITH THE 80-PIN TQFP PACKAGE. . . . . . . . . . . . . . . . . .28
PINS REMOVED FOR TQFP PACKAGE AND THEIR EFFECTS . . . . . . . . . . . . . . . . . . . . . . . . . . .28
FUNCTIONAL DESCRIPTION  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0
Network Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
System Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
DETAILED FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Block Level Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Bus Interface Unit (BIU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
BIU to FIFO Data Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Byte Alignment For FIFO Read Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
BIU to Control and Status Register Data Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
FIFO Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Media Access Control (MAC)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Manchester Encoder/Decoder (MENDEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Attachment Unit Interface (AUI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Digital Attachment Interface  (DAI)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
10BASE-T Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Twisted Pair Transmit Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Twisted Pair Receive Function  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Link Test Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Polarity Detection and Reversal  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Twisted Pair Interface Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Collision Detect Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Signal Quality Error (SQE) Test (Heartbeat) Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Jabber Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
External Address Detection Interface (EADI)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Internal/External Address Recognition Capabilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
General Purpose Serial Interface (GPSI)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
IEEE 1149.1 Test Access Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
SLAVE ACCESS OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7
Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Reinitialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
TRANSMIT OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Transmit FIFO Write  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Transmit Function Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Automatic Pad Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Transmit FCS Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Transmit Status Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Transmit Exception Conditions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
RECEIVE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Receive FIFO Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Receive Function Programming  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Automatic Pad Stripping  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Receive FCS Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

6 Am79C940
Receive Status Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Receive Exception Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
LOOPBACK OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
USER ACCESSIBLE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
8-Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Programmer’s Register Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Missing Table Title? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
SYSTEM APPLICATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Host System Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
NETWORK INTERFACES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
External Address Detection Interface (EADI)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
MACE Compatible AUI Isolation  Transformers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
MANUFACTURER CONTACT INFORMATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Commercial (C) Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Industrial (I) Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
VCC Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
DC CHARACTERISTICS (UNLESS OTHERWISE NOTED, PARAMETRIC VALUES ARE THE SAME 
BETWEEN COMMERCIAL DEVICES AND INDUSTRIAL DEVICES.)  . . . . . . . . . . . . . . . . . . . . . . .90
AC CHARACTERISTICS (UNLESS OTHERWISE NOTED, PARAMETRIC VALUES ARE THE SAME 
BETWEEN COMMERCIAL DEVICES AND INDUSTRIAL DEVICES.)  . . . . . . . . . . . . . . . . . . . . . . .93
KEY TO SWITCHING WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
SWITCHING TEST CIRCUITS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
PHYSICAL DIMENSIONS* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
PL 084 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
84-Pin Plastic Leaded Chip Carrier (measured in inches). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
PHYSICAL DIMENSIONS* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
PQR100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
100-Pin Plastic Quad Flat Pack; Trimmed and Formed (measured in millimeters) . . . . . . . . . . .118
PHYSICAL DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
PQR100 100-Pin Plastic Quad Flat Pack with Molded Carrier Ring (measured in millimeters)  .119
PHYSICAL DIMENSIONS* PQT080 80-Pin Thin Quad Flat Package (measured in millimeters)120
LOGICAL ADDRESS FILTERING FOR ETHERNET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
BSDL DESCRIPTION OF AM79C940 MACE JTAG STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . .123
AM79C940 MACE REV C0 SILICON ERRATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141

Am79C940 7

CONNECTION DIAGRAMS

PL 084

PLCC PACKAGE

123818283846789458076777879 75

40 47

34 39

3833 48 52

32 53

SRDCLK

EAM/R

SRD

SF/BD

RESET

SLEEP

DVDD

INTR

DBUS0

DVSS

DBUS1

DBUS2

DBUS3

DBUS4

DVSS

DBUS5

DBUS6

DBUS7

DBUS8

DBUS9

XTAL2

AVSS

XTAL1

AVDD

TXD+

TXP+

TXD-

TXP-

AVDD

RXD+

RXD-

DVDD

TDI

DVSS

TCK

TMS

TDO

LNKST

RXPOL

R/W

RXCRS

RXDAT

CLSN

TXEN/ TXEN

STDCLK

DVSS

TXDAT-

TXDAT+

DVSS

EDSEL

DXCVR

DVDD

AVDD

CI+

CI-

DI+

DI-

AVDD

DO+

DO-

AVSS

DBUS10

DBUS11

DBUS12

DBUS13

DVDD

DBUS14

DBUS15

DVSS

EOF

DTV

FDS

BE0

BE1

SCLK

TDTREQ

RDTREQ

ADD0

ADD1

ADD2

ADD3

ADD4

Am79C940JC

MACE

16235D-2

8 Am79C940

CONNECTION DIAGRAMS

PQR100

PQFP PACKAGE

RXCRS

RXDAT

CLSN

TXEN/TXEN

STDCLK

DVSS

TXDAT-

TXDAT+

DVSS

EDSEL

DXCVR

DVDD

AVDD

CI+

CI-

DI+

DI-

AVDD

DO+

DO-

100

TCK

TMS

TDO

LNKST

RXPOL

R/W

AVSS

XTAL2

AVSS

XTAL1

AVDD

TXD+

TXP+

TXD

TXP

AVDD

RXD+

RXD

DVDD

TDI

DVSS

SRDCLK

EAM/R

SRD

SF/BD

RESET

SLEEP

DVDD

INTR

DBUS0

DVSS

DBUS1

DBUS2

DBUS3

DBUS4

DVSS

DBUS5

DBUS6

DBUS7

DBUS8

DBUS9

DBUS10

DBUS11

DBUS12

DBUS13

DVDD

DBUS14

DBUS15

DVSS

EOF

DTV

FDS

BE0

BE1

SCLK

TDTREQ

RDTREQ

ADD0

ADD1

ADD2

ADD3

ADD4

MACE

Am79C940KC

16235D-3

Am79C940 9

CONNECTION DIAGRAMS

PQT080

TQFP PACKAGE

80 79 78 77 76 757473 72 717069 68 676665 64 63 62 61

21 22 23 24 25 262728 29 303132 33 343536 37 38 39 40

SRDCLK

EAM/R

SF/BD

RESET

SLEEP

DVDD

INTR

DBUS0

DVSS

DBUS1

DBUS2

DBUS3

DBUS4

DVSS

DBUS5

DBUS6

DBUS7

DBUS8

DBUS9

XTAL2

AVSS

XTAL1

AVDD

TXD+

TXP+

TXD-

TXP-

AVDD

RXD+

RXD-

DVDD

TDI

DVSS

TCK

TMS

TD0

LNKST

R/W

DBUS10

DBUS11

DBUS12

DBUS13

DVDD

DBUS14

DBUS15

DVSS

EOF

FDS

BE0

BE1

SCLK

TDTREQ

RDTREQ

ADD0

ADD1

ADD2

ADD3

ADD4

RXCRS

RXDAT

CLSN

TXEN/

STDCLK

DVSS

TXDAT+

DVSS

EDSEL

DXCVR

DVDD

AVDD

CI+

CI-

DI+

DI-

AVDD

DO+

DO-

AVSS

MACE

Am79C940VC

Notes: Four pin func tions avai lable on th e PLCC and PQFP p ackag es ar e n ot avail able with the T QFP pa ckag e.

(See full data sheet for description of pins not included with the 80-pin TQFP package. In particular, see section

“Pin Functions not available with the 80-pin TQFP package.”)

16235D-4

10 Am79C940

ORDERING INFORMATION

Standard Products

AMD stand ard products are availab le in several packages and opera ting ranges. The order n umber (V alid Combinat ion) is formed

by a combination of:

Valid Combinations

The Valid Combina tion s tab le lists config urations pl ann ed to

be supported in volume for this device. Consult the local AMD

sales office to confirm availability of specific valid

combinations and to check on newly released combinations.

Note:

Currently the silic on revision level of the MACE Ethernet controll er is revision C0. This is designated by the marking on the pack age

as Am79C940Bxx, where “xx” indi cate package type and temperature range.

AM79C940

OPTIONAL PROCESSING

Blank = Standard Processing

TEMPERATURE RANGE

C=Commercial (0

° to +70°C)

I = Industrial (-40°C to +85°C)

PACKAGE TYPE (per Prod. Nomenclature/16-038)

J = 84-Pin Plastic Leaded Chip Carrier (PL 084)

K = 100-Pin Plastic Quad Flat Pack (PQR100)

V = 80-Pin Thin Quad Flat Package (PQT080)

SPEED

Not Applicable

DEVICE NUMBER/DESCRIPTION (include revision letter)

Am79C940

Media Access Controller for Ethernet

VC ALTERNATE PACKAGING OPTION

\W = Trimmed and Formed in a Tray

Valid Combinations

AM79C940 JC, KC,

KC\W, VC,

VC\W

AM79C940 JI, KI,

KI\W, VI,

VI\W

Am79C940 11

PIN/PACKAGE SUMMAR Y (PLCC)

PLCC Pin # Pin Name Pin Function

1 DXCVR Disable Transceiver

2 EDSEL Edge Select

3DV

SS Digital Ground

4 TXDAT+ Transmit Data +

5TXDAT–Transmit Data –

6DV

SS Digital Ground

7 STDCLK Serial Transmit Data Clock

8 TXEN/TXEN Transmit Enable

9 CLSN Collision

10 RXDAT Receive Data

11 RXCRS Receive Carrier Sense

12 SRDCLK Serial Receive Data Clock

13 EAM/R External Address Match/Reject

14 SRD Serial Receive Data

15 SF/BD Start Frame/Byte Delimiter

16 RESET Reset

17 SLEEP Sleep Mode

18 DVDD Digital Power

19 INTR Interrupt

20 TC Timing Control

21 DBUS0 Data Bus0

22 DVSS Digital Ground

23 DBUS1 Data Bus1

24 DBUS2 Data Bus2

25 DBUS3 Data Bus3

26 DBUS4 Data Bus4

27 DVSS Digital Ground

28 DBUS5 Data Bus5

29 DBUS6 Data Bus6

30 DBUS7 Data Bus7

31 DBUS8 Data Bus8

32 DBUS9 Data Bus9

33 DBUS10 Data Bus10

34 DBUS11 Data Bus11

35 DBUS12 Data Bus12

36 DBUS13 Data Bus13

37 DVDD Digital Power

38 DBUS14 Data Bus14

39 DBUS15 Data Bus15

40 DVSS Digital Ground

41 EOF End Of Frame

42 DTV Data Transfer Valid

43 FDS FIFO Data Strobe

44 BE0 Byte Enable0

12 Am79C940

PIN/PACKAGE SUMMARY (continued)

PLCC Pin # Pin Name Pin Function

45 BE1 Byte Enable 1

46 SCLK System Cloc k

47 TDTREQ Transmit Data Transfer Request

48 RDTREQ Receive Data Transfer Request

49 ADD0 Address0

50 ADD1 Address1

51 ADD2 Address2

52 ADD3 Address3

53 ADD4 Address4

54 R/W Read/Write

55 CS Chip Select

56 RXPOL Receive Polarity

57 LNKST Link Status

58 TDO Test Data Out

59 TMS Test Mode Select

60 TCK Test Clock

61 DVSS Digital Ground

62 TDI Test Data Input

63 DVDD Digital Power

64 RXD–Receive Data–

65 RXD+ Receive Data+

66 AVDD Analog Power

67 TXP–Transmit Pre-distortion

68 TXD–Transmit Data–

69 TXP+ Transmit Pre-distortion+

70 TXD+ Transmit Data+

71 AVDD Analog Power

72 XTAL1 Crystal Output

73 AVSS Analog Ground

74 XTAL2 Crystal Output

75 AVSS Analog Ground

76 DO–Data Out–

77 DO+ Data Out+

78 AVDD Analog Power

79 DI–Data In–

80 DI+ Data In+

81 CI–Control In–

82 CI+ Control In+

83 AVDD Analog Power

84 DVDD Digital Power

Am79C940 13

PIN/PACKAGE SUMMARY (PQFP) (continued)

PQFP Pin # Pin Name Pin Function

1 NC No Connect

2 NC No Connect

3 NC No Connect

4 NC No Connect

5 SHDCLK Serial Receive Data Clock

6 EAM/R External Address Match/Reject

7 SRD Serial Receive Data

8 SF/BD Start Frame/Byte Delimiter

9 RESET Reset

10 SLEEP Sleep Mode

11 DVDD Digital Power

12 INTR Interrupt

13 TC T i mi ng Contro l

14 DBUS0 Data Bus0

15 DVSS Digital Ground

16 DBUS1 Data Bus1

17 DBUS2 Data Bus2

18 DBUS3 Data Bus3

19 DBUS4 Data Bus4

20 DVSS Digital Ground

21 DBUS5 Data Bus5

22 DBUS6 Data Bus6

23 DBUS7 Data Bus7

24 DBUS8 Data Bus8

25 DBUS9 Data Bus9

26 NC No Connect

27 NC No Connect

28 NC No Connect

29 DBUS10 Data Bus10

30 NC No Connect

31 DBUS11 Data Bus11

32 DBUS12 Data Bus12

33 DBUS13 Data Bus13

34 DVDD Digital Power

35 DBUS14 Data Bus14

36 DBUS15 Data Bus15

37 DVSS Digital Ground

38 EOF End of Frame

39 DTV Data Transfer Valid

40 FDS FIFO Data Strobe

41 BE0 Byte Enable0

42 BE1 Byte Enable1

14 Am79C940

PIN/PACKAGE SUMMARY (continued)

PQFP Pin # Pin Name Pin Function

43 SCLK System Clock

44 TDTREQ T ran sm it D ata Transfer Reques t

45 RDTREQ Recei ve Data Transfer Reques t

46 ADD0 Address0

47 ADD1 Address1

48 ADD2 Address2

49 ADD3 Address3

50 ADD4 Address4

51 NC No Connect

52 NC No Connect

53 NC No Connect

54 NC No Connect

55 R/W Read/Write

56 CS Chip Select

57 RXPOL Receive Polarity

58 LNKST Link Status

59 TDO Test Data Out

60 TMS Test Mo de Select

61 TCK Test Clock

62 DVSS Digital Ground

63 TDI Test Data I nput

64 DVDD Digital Power

65 RXD–Receive Data–

66 RXD+ Receive Data+

67 AVDD Analog Power

68 TXP–Tran smit Pre-di stortion –

69 TXD–Transmit Data–

70 TXP+ Transm it Pre-di st orti on+

71 TXD+ T ransmit Data+

72 AVDD Analog Power

73 XTAL1 Crystal Input

74 AVSS Analog Ground

75 XTAL2 Crystal Output

76 NC No Connect

77 NC No Connect

78 NC No Connect

79 AVSS Analog Ground

80 NC No Connect

81 DO–Data Out–

82 DO+ Data Ou t+

83 AVDD Analog Power

84 DI–Data In–

85 DI+ Data In+

Am79C940 15

PIN/PACKAGE SUMMARY (continued)

PQFP Pin # Pin Name Pin Function

86 CI–Control In–

87 CI+ Cont rol In+

88 AVDD Analog Power

89 DVDD Digital Power

90 DXCVR Disable Transceiver

91 EDSEL Edge Select

92 DVSS Digital Ground

93 TXDAT+ Transmit Data +

94 TXDAT–Transmit Data–

95 DVSS Digital Ground

96 STDCLK Serial Tran smit Data Cloc k

97 TXEN/TXEN Tran sm it Enab le

98 CLSN Collision

99 RXDAT Receive Data

100 RXCRS Receive Carrier Sense

16 Am79C940

PIN/PACKAGE SUMMARY (TQFP) (continued)

TQFP # Pin Name Pin Function TQFP

Pin Number Pin Name Pin Function

1 SRDCLK Serial Receive Data Clock 41 R/W Read/Write

2 EAM/R External Address Match/Reject 42 CS Chip/Select

3 SF/BD Start Frame/Byte Delimi ter 43 LNKST Link Status

4 RESET Reset 44 TDO Test Da ta Out

5SLEEP

Sleep Mode 45 TMS Test Mode Select

6 DVDD Digital Power 46 TCK Text Clock

7INTR

Interrupt 47 DVSS Digital Ground

8TC

Timing Control 48 TDI Test Data Inpu t

9 DBUS0 Data Bus0 49 DVDD Digital Power

10 DVSS Digital Gro und 50 RXD–Receive Data–

11 DBUS1 Data Bus1 51 RXD+ Receive Data+

12 DBUS2 Data Bus2 52 AVDD Analog Power

13 DBUS3 Data Bus3 53 TXP–Transmit P re-distortion–

14 DBUS4 Data Bus4 54 TXD–Transmit Data–

15 DVSS Digital Ground 55 TXP+ Transm it Pre-di sto rtio n+

16 DBUS5 Data Bus5 56 TXD+ Transmit Data+

17 DBUS6 Data Bus6 57 AVDD Analog Power

18 DBUS7 Data Bus7 58 XTAL1 Crystal Output

19 DBUS8 Data Bus8 59 AVSS Analog Groun d

20 DBUS9 Data Bus9 60 XTAL2 Crystal Output

21 DBUS10 Data Bus10 61 AVSS Analog Groun d

22 DBUS11 Data Bus11 62 DO–Data Out–

23 DBUS12 Data Bus12 63 DO+ Data Out+

24 DBUS13 Data Bus13 64 AVDD Analog Power

25 DVDD Digital Power 65 DI–Data In–

26 DBUS14 Data Bus14 66 DI+ Data Out+

27 DBUS15 Data Bus15 67 CI–Control In–

28 DVSS Digital Gro und 68 CI+ Control In+

29 EOF End of Frame 69 AVDD Analog Power

30 FDS FIFO Data Strobe 70 DVDD Digital Power

31 BE0 Byte Enable0 71 DXCVR Disable Transceiver

32 BE1 Byte Enable1 72 EDSEL Edge Select

33 SCLK System Clock 73 DVSS Digital Ground

34 TDTREQ Transmit Data Transfer Request 74 TXDAT+ Transmit Data+

35 RDTREQ Receive Data Transfer Request 75 DVSS Digital Ground

36 ADD0 Address0 76 STDCLK Serial Transmit Data Clock

37 ADD1 Address1 77 TXEN/TXEN Transmit Enable

38 ADD2 Address2 78 CLSN Collision

39 ADD3 Address3 79 RXDAT Receive Data

40 ADD4 Addres s4 80 RXCRS Receive Carrier Sense

Am79C940 17

PIN SUMMARY

Pin Name Pin Function Type Active Comment

Attachment Unit Interface (AUI)

DO+/DO–Data Out O Pseudo-ECL

DI+/DI–Data In I Pseudo-ECL

CI+/CI–Cont rol In I Pseud o-ECL

RXCRS Receive Carrier Sense I/O High TTL output. Input in DAI, GPSI port

TXEN Transmit Enable O High TTL. TXEN in DAI port

CLSN Collision I/O High TTL output. Input in GPSI

DXCVR Disable Transceiver O Low TTL low

STDCLK Serial Transmit Data Clock I/O Output. Input in GPSI

SRDCLK Serial Receive Data Clock I/O Output. Input in GPSI

Digital Attachment Interface (DAI)

TXDAT+ Transmit Data + O High TTL. See also GPSI

TXDAT–Transmit Data–OLowTTL

TXEN Transmit Enable O Low TTL. See TXEN in GPSI

RXDAT Receiv e Data I TTL. See als o GPSI

RXCRS Receive Carrier Sense I/O High TTL input. Output in AUI

CLSN Collision I/O High TTL output. Input in GPSI

DXCVR Disable Transceiver O High TTL high

STDCLK Serial Transmit Data Clock I/O Output. Input in GPSI

SRDCLK Serial Receive Data Clock I/O Output. Input in GPSI

10BASE-T Interface

TXD+/TXD–Transmit Data O

TXP+/TXP–Transmit Pre-distortion O

RXD+/RXD–Receive Data I

LNKST Link Status O Low Open Drain

RXPOL Receive Polarity O Low Open Drain

TXEN Transmit Enable O High TTL. TXEN in DAI port

RXCRS Receive Carrier Sense I/O High TTL output. Input in DAI, GPSI port

CLSN Collision I/O High TTL output. Input in GPSI

DXCVR Disable Transceiver O High TTL high

STDCLK Serial Transmit Data Clock I/O Output. Input in GPSI

SRDCLK Serial Receive Data Clock I/O Output. Input in GPSI

General Purpose Serial Interface (GPSI)

STDCLK Serial Transmit Data Clock I/O Input

TXDAT+ Transmit Data + O High TTL. See also DAI port

TXEN Transmit Enable O High TTL. TXEN in DAI port

SRDCLK Serial Receive Data Clock I/O Input. See also EADI port

RXDAT Receive Data I TTL. See also DAI port

RXCRS Receive Carrier Sense I/O High TTL input. Output in AUI

CLSN Collision I/O High TTL input

DXCVR Disable Transceiver O Low TTL low

18 Am79C940

PIN SUMMARY (continued)

Pin Name Pin Function Type Active Comment

External Address Detection Interface (EADI)

SF/BD Start Frame/Byte Delimiter O High

SRD Serial Receive Data O High

EAM/R External Address Match/Reject I Low

SRDCLK Serial Receive Data Clock I/O Output except in GPSI

Host System Interface

DBUS 15–0 Data Bus I/O High

ADD4–0Address I High

R/W Read/Write I High/Low

RDTREQ Receive Data Transfer Request O Low

TDTREQ Transmit Data Transfer Request O Low

DTV Data Transfer Valid O Low Tristate

EOF End Of Frame I/O Low

BE0 Byte Enable 0 I Low

BE1 Byte Enable 1 I Low

CS Chip Sele ct I Low

FDS FIFO Data Strobe I Low

INTR Interrupt O Low Open Drain

EDSEL Edge Select I High

TC Timi ng C ontro l I Low Internal pull-up

SCLK System Clock I High

RESET Reset I Low

IEEE 1149.1 Test Access Port (TAP) Interface

TCK Test Clock I Internal pull-up

TMS Test Mode Select I Internal pull-up

TDI Test Data Input I Internal pull-up

TDO Test Data Out O

General Interface

XTAL1 Crystal Inpu t I CMO S

XTAL2 Crystal Output O CMOS

SLEEP Sleep Mode I Low TTL

DVDD Digital Power (4 pins) P

DVSS Digital Power (6 pins) P

AVDD Analog Power (4 pins) P

AVSS Analog Power (2 pins) P

Am79C940 19

PIN DESCRIPTION

Network Interfaces

The MACE device has five potential network inter-

faces. Only one of the interfaces that provides physical

network attachment can be used (active) at any time.

Selection between the AUI, 10BASE-T, DAI or GPSI

ports is pro vided b y progr ammi ng the PHY Config ura-

tion Control register . The EADI port is effectively active

at all times. Some signals, primarily used for status

reporting, are active for more than one single interface

(the CLSN pin for instance). Under each of the descrip-

tions for the network interfaces, the primary signals

which are unique to that interface are described.

Where signals are active for multiple interfaces, they

are desc ribed on ce u nder the in terfac e mos t appro pri-

ate.

Attachment Unit Interface (AUI)

CI+/CI

Control In (Input)

A differential input pair , signaling the MACE device that

a collision has been detected on the network media, in-

dicated by the CI± inputs being exercised with 10 MHz

pattern of sufficient amplitude and duration. Operates

at pseudo-ECL levels.

DI+/DI

Data In (Input)

A differential input pair to the MACE device for receiv-

ing Manchester encoded data from the network.

Operates at pseudo-ECL levels.

DO+/DO

Data Out (Output)

A differential output pair from the MACE device for

transmitti ng Manc hest er encod ed data to the ne twork.

Operates at pseudo-ECL levels.

Digital Attac h ment Interface (DAI)

TXDAT+/TXDAT–

Transmit Data (Output)

When the DAI port is selected, TXDAT± are configured

as a complementary pair for Manchester encoded data

output from the MACE device, used to transmit data to

a local external network transceiver . During valid trans-

mission (indicated by TXEN low), a logical 1 is indi-

cated by the TXDAT+ pin being in the high state and

TXDAT– in the low state; and a logical 0 is indicated by

the TXDAT+ pi n being in the lo w state a nd TX DAT– in

the high state. During idle (TXEN high), TXDA T+ will be

in the high state, and TXDAT– in the low state. When

the GPSI port is selected, TXDAT+ will provide NRZ

data output from the MAC core, and TXDAT– will be

held in the LOW state. Operates at TTL levels. The

operatio ns of TXDAT+ an d TXDAT– are defi ned in th e

following t ables:

TXDAT + Configuration

TXDAT – Configuration

Notes:

1. PORTSEL [1–0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14).

2. This pin should be externally terminated, if unused, to reduce power consumption.

SLEEP PORTSEL

[1-0] ENDPLSIO Interface Description Pin Function

0 XX X Sleep Mode High Impedance

1 00 1 AUI High Impedance (Note 2)

1 01 1 10BASE–T High Impedance (Note 2)

1101DAI Port TXDAT+ Output

1111GPSI TXDAT+ Output

1 XX 0 Status Disabled High Impedance (Note 2)

SLEEP PORTSEL

[1-0] ENDPLSIO Interface Description Pin Function

0 XX X Sleep Mode High Impedance

1 00 1 AUI High Impedance

1 01 1 10BASE–T High Impedance

1101DAI Port TXDAT– Output

1111GPSI LOW

1 XX 0 Status Disabled High Impedance

20 Am79C940

TXEN/TXEN

Transmit Enable (Output)

When the AUI p ort is sele cted (PO RTSEL [1 -0] = 00) ,

an output indicating that the AUI DO± differential output

has valid Manchester encoded data is presented.

When t he 10BA SE-T port is se lecte d (PO RTSEL [1 -0]

= 01), indicates that Manchester data is being output

on the TXD±/TXP± complemen tary ou tputs. W hen the

DAI por t is s elect ed (PO RTSEL [1–0] = 10), indi cates

that Manchester data is being output on the DAI port

TXDAT± comple men tar y outputs. W hen the GP SI p or t

is selected (PORTSEL [1–0] =11), indicates that NRZ

data is being o utput from the MAC core of the MACE

device, to an external Manchester encoder/decoder, on

the TXDAT+ output. Active low when the DAI port is

selected, active high when the AUI, 10 BASE-T or

GPSI is selected. Operates at TTL levels.

RXDAT

Receive Data (Input)

When the DAI port is selected (PORTSEL [1–0] = 10 ),

the Manchester encoded data input to the integrated

clock rec overy and Manche ster decode r of the MACE

device, from an external network transceiver . When the

GPSI port is selected (PORTSEL [1–0] =11), the NRZ

decoded data input to the MAC core of the MACE

device, from an external Manchester encoder/decoder .

Operates at TTL levels.

RXCRS

Receive Carrier Sense (Input/Output)

When the AUI port is selected (PORTSEL [1–0] = 00),

an output i ndica ting tha t the DI± in put pair is rece ivin g

valid Manchester encoded data from the external

transceiver which meets the signal amplitude and

pulse width requirements. When the 10BASE-T port is

selected (PORTSEL [1–0] = 01), an output indicating

that the RX D± inpu t pair is receiv ing v alid Manch ester

encoded da ta from the twisted pair ca ble which m eets

the signal amplitude and pulse width requirements.

RXCRS wi ll be assert ed high for the en tire du ratio n of

the receive message. When the DAI port is selected

(PORTSEL [1-0] = 10), an input signaling the MACE

device that a receive carrier condition has been

detected on the network, and valid Manchester

encoded d ata is being pres ented to the MA CE device

on the RXDAT line. When the GPSI port is selected

(PORTSEL [1 -0 ] = 11) , a n inp ut sign all in g t he in ter nal

MAC core that valid NRZ data is being presented on

the RXDAT input. Operates at TTL levels.

TXEN/TXEN Configuration

Notes:

1. PORTSEL [1–0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14).

2. When the GPSI port is select ed, TXEN should ha ve an externa l pull-down atta ched (e.g. 3.3 k Ω) to ensure the output is held

inactive before ENPLSIO is set.

3. This pin should be externally terminated, if unused, to reduce power consumption.

SLEEP PORTSEL

[1-0] ENDPLSIO Interface Description Pin Function

0 XX X Sleep Mode High Impedance

1 00 1 AUI TXEN Output

1 01 1 10BASE-T TXEN Output

1 10 1 DAI Port TXEN Output

1 11 1 GPSI TXEN Output

1 XX 0 Status Disabled High Impedance (Note 3)

Am79C940 21

RXDAT Configuration

Notes:

1. PORTSEL [1–0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14).

2. This pin should be externally terminated, if unused, to reduce power consumption.

RXCRS Configuration

Notes:

1. PORTSEL [1–0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14).

2. This pin should be externally terminated, if unused, to reduce power consumption.

DXCVR

Disable Transceiver (Output)

An output from the MACE device to indicate the net-

work port in use, as programmed by the ASEL bit or the

PORTSEL [1–0] bits. The output is provided to allow

power down of an external DC-to-DC converter, typi-

cally used to provide the voltage requirements for an

external 10BASE2 transceiver.

When the Auto Select (ASEL) feature is enabled, the

state of the PORTSEL [1–0] bits is overridden, and the

network interface will be selected by the MACE device,

dependent only on the status of the 10BASE-T link. If

the link is active (LNKST pin driven LOW) the

10BASE-T port will be used as the active network inter-

face. If the link is inactive (LNKST pin pulled HIGH) the

AUI port will be used as the active network interface.

Auto Select will continue to operate even when the

SLEEP pin i s a sser ted if th e RWAKE bit h as been se t.

The AWAKE bit does not allow the Auto Select func-

tion, and only the receive section of 10BASE-T port will

be active (DXCVR = HIGH).

Active (HIGH) when either the 10BASE-T o r DAI port

is selected. Inactive (LOW) when the AUI or GPSI port

is selected.

SLEEP PORTSEL

[1–0] ENPLSIO Interface Desc ri ption Pi n Functio n

0 XX X Sleep Mode High Impedance

1 00 1 AUI High Impedance (Note 2)

1 01 1 10BASE-T High Impedance (Note 2)

1 10 1 DAI Port RXDAT Input

1 11 1 GPSI RXDAT Input

1 XX 0 Status Disabled High Impedance (Note 2)

SLEEP PORTSEL

[1-0] ENDPLSIO Interface Description Pin Function

0 XX X Sleep Mode High Impedance

1001AUI RXCRS Output

1 01 1 10BASE-T RXCRS Output

1 10 1 DAI Port RXCRS Output

1 11 1 GPSI RXCRS Output

1 XX 0 Status Disabled High Impedance (Note 2)

22 Am79C940

DXCVR Configuration—SLEEP Operation

Note:

1. RWAKE and ASEL are located in the PHY Configuration Control register (REG ADDR 15). PORTSEL [1–0] and ENPLSIO

are locate d in the PLS Configurati on Control regi ster (REG ADDR 14). All bits mu st be programm ed prior to the assertion of

the SLEEP pin.

DXCVR Configuration—Normal Operation

Note:

1. RW AKE a nd ASEL are locate d in the PHY Co nfiguration Control reg ister (REG ADDR 15). PORTSEL [1–0] a nd ENPLSIO

are located in the PLS Configuration Control register (REG ADDR 14).

Sleep

Pin RWAKE

Bit AWAKE

Bit ASEL

Bit LNKST

Pin PORTSEL

[1–0] Bits Interface

Description Pin

Function

00 0X High

Impedance XX Sleep

Mode High

Impedance

01 00 High

Impedance 00 AUI with EADI port LOW

01 00 High

Impedance 01 10BASE-T with EADI port HIGH

01 00 High

Impedance 10 Invalid HIGH

01 00 High

Impedance 11 Invalid LOW

01 01 High

Impedance 0X AUI with EADI port LOW

01 01 High

Impedance 0X 10BASE-T with EADI port HIGH

0 1 1 1 HIGH 0X AUI with EADI port LOW

0 1 1 1 LOW 0X 10BASE-T with EADI port HIGH

0 0 1 X X 0X 10BASE-T HIGH

SLEEP

Pin ASEL

Bit LNKST

Pin PORTSEL

[1-0] Bits ENPLSIO

BIT Interface

Description Pin

Function

1 X X XX X SIA Test Mode High

Impedance

10 X 00 X AUI LOW

1 0 X 01 X 10BASE-T HIGH

1 0 X 10 X DAI port HIGH

1 0 X 11 X GPSI LOW

1 1 HIGH 0X X AUI LOW

1 1 LOW 0X X 10BASE-T HIGH

Am79C940 23

10BASE-T INTERF ACE

TXD+, TXD–

Transmit Data (Output)

10BASE–T port differenti al dr iv ers.

TXP+, TXP–

Transmit Pre-Distortion (Output)

T ransmit wave form differential driver for pre-distortion.

RXD+, RXD–

Receive Data (Input)

10BASE–T port differential receiver . These pins should

be externally terminated to reduce power consumption

if the 10BASE–T interface is not used.

LNKST

Link Status (OutputOpen Drain)

This pin is driven LOW if the link is identified as func-

tional. If the link is determined to be nonfunctional, due

to missing idle link pulses or data packets, then this pin

is not driven (requires external pull-up). In the LOW

output state, the pin is capable of sinking a maximum

of 12 mA and can be used to drive an LED.

This feature can be disabled by setting the Disable Link

Test (DLNKTST) bit in the PHY Configuration Control

function is disabled, the LNKST pin will be driven LOW ,

and the Transmit and Receive functions will remain

active regardless of arriving idle link pulses and data.

The interna l 10BA SE-T MAU wil l continu e to gener ate

idle link pulses irrespective of the status of the

DLNKTST bit.

RXPOL

Receive Polarity (Output, Open Drain)

The twisted pair receiver is capable of detecting a

receive signal with reversed polarity (wiring error). The

RXPOL pin is normally in the LOW state, indicating

correct polarity of the received signal. If the receiver

detects a received packet with reversed polarity, then

this pin is not driven (requires external pull-up) and the

polarity of subsequent packets are inverted. In the

LOW output state, this pin is capable of sinking a

maximum of 12mA and can be used to drive an LED.

The polarity correction feature can be disabled by

setting the Disable Auto Polarity Correction (DAPC) bit

in the PHY Configuration Control register. In this case,

the Receive Polarity correction circuit is disabled and

the internal receive signal remains non-inverted,

irrespective of the received signal. Note that RXPOL

will continue to reflect the polarity detected by the

receiver.

General Purpose Serial Interface (GPSI)

STDCLK

Serial Transmit Data Clock (Input/Output)

When either the AUI, 10BASE–T or DAI port is

selected, STDCLK is an output operating at one half the

crystal or XTAL1 frequency. STDCLK is the encoding

clock for Manchester data transferred to the output of

either the AUI DO± pair, the 10BASE-T TXD±/TXP±

pairs, or the DAI port TXDAT± pair. When using the

GPSI p ort, ST DCLK is an in put at t he netw ork data rate,

provided by the external Manchester encode/decoder,

to strobe out the NRZ data presented on the TXDAT+

output. This is also required for internal loopbacks while

in GPSI mo de .

STDCLK Configuration

Notes:

1. PORTSEL [1–0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14).

2. This pin should be externally terminated, if unused, to reduce power consumption.

SLEEP PORTSEL

[1-0] ENDPLSIO Interface Description Pin Function

0 XX X Sleep Mode High Impedance

1001AUI STDCLK Output

1 01 1 10BASE-T STDCLK Output

1 10 1 DAI Port STDCLK Output

1 11 1 GPSI STDCLK Output

1 XX 0 Status Disabled High Impedance (Note 2)

24 Am79C940

CLSN

Collision (Input/Output)

An external indication that a collision condition has

been detected by the (internal or external) Medium

Attachment Unit (MAU), and that signals from two or

more nodes are present on the network. When the AUI

port is selected (PORTSEL [1–0] = 00), CLSN will be

activated when the CI± input pair is receiving a collision

indication from the external transceiver. CLSN will be

asserted high for the entire duration of the collision

detection, but will not be asserted during the SQE Test

message following a transmit message on the AUI.

When the 10BASE-T port is selected (PORTSEL [1–0]

= 01), CL SN will be asserted h igh when sim ultaneous

transmit and receive activity is detected (logically

detected when TXD±/TXP± and RXD± are both active).

When the DAI port is selected (PORTSEL [1–0] = 10 ),

CLSN will b e asserted high when simultane ous trans-

mit and receive activity is detected (logically detected

when RXCRS and TXEN are both active). When the

GPSI po rt is se lecte d (PORTSE L [1 –0] = 11), an i nput

from the external Manchester encoder/decoder signal-

ing the MACE device that a collision condition has

been detec ted on the networ k, and any rece ive frame

in progress should be aborted.

External Address Detection Interface

(EADI)

SF/BD

Start Frame/Byte Delimiter (Output)

The external indication that a start of frame delimiter

has been r eceived. T he seria l bit stream will follow o n

the Serial Receive Data pin (SRD), commencing with

the destination address field. SF/BD will go high for 4

bit times (400 ns) after detecting the second 1 in the

SFD of a received frame. SF/BD will subsequently

toggle every 400 ns (1.25 MHz frequency) with the

rising edge indicating the start (first bit) in each

subsequent byte of the received serial bit stream.

SF/BD will be inactive during frame transmission.

SRD

Serial Receiv e Dat a (Output)

SRD is the decoded NRZ data from the network. It is

available for external address detection. Note that

when the 10BASE-T port is selected, transition on SRD

will only occur during receive activity. When the AUI or

DAI port is selected, transition on SRD will occur

dur ing both transmit and receive activity.

CLSN Configuration

Notes:

1. PORTSEL [1–0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14).

2. This pin should be externally terminated, if unused, to reduce power consumption.

EAM/R

External Ad dres s Matc h/Reje ct (Input)

The incoming frame will be received dependent on the

receive operational mode of the MACE device, and the

polarity of the EAM/R pin. The EAM/R pin function is

programmed by use of the M/R bit in the Receive

Frame Control register . If the bit is set, the pin is config-

ured as EAM. If the bit is reset, the pin is configured as

EAR. E AM/R ca n be asser ted dur ing pa cket rec eptio n

to accept or reject packets based on an external

address comparison.

SRDCLK

Serial Receive Data Clock (Input/Output)

The Seri al Rec eive Data ( SRD ) outp ut i s sync hr on ous

to SRDCLK running at the 10MHz receive data clock

frequency. The pin is configured as an input, only when

the GPSI port is selected. Note that when the

10BASE–T port is selected, transition on SRDCLK will

only occur during receive activity. When the AUI or DAI

port is selected, transition on SRDCLK will occur during

both transmit and receive activity.

SLEEP PORTSEL

[1-0] ENDPLSIO Interface Description Pin Function

0 XX X Sleep Mode High Impedance

1 00 1 AUI CLSN Output

1 01 1 10BASE-T CLSN Output

1101DAI Port CLSN Output

1 11 1 GPSI CLSN Output

1 XX 0 Status Disabled High Impedance (Note 2)

Am79C940 25

SRD Configuration

Note:

1. PORTSEL [1–0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14).

SRDCLK Configuration

Notes:

1. PORTSEL [1–0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14).

2. This pin should be externally terminated, if unused, to reduce power consumption.

SLEEP PORTSEL

[1-0] ENDPLSIO Interface Description Pin Function

0 XX X Sleep Mode High Impedance

1001AUI SRD Output

1 01 1 10BASE-T SRD Output

1 10 1 DAI Port SRD Output

1111GPSI SRD Output

1 XX 0 Status Disabled High Impedance

SLEEP PORTSEL

[1-0] ENDPLSIO Interface Description Pin Function

0 XX X Sleep Mode High Impedance

1 00 1 AUI SRDCLK Output

1 01 1 10BASE-T SRDCLK Output

1 10 1 DAI Port SRDCLK Output

1 11 1 GPSI SRDCLK Ou tpu t

1 XX 0 Status Disabled High Impedance (Note 2)

26 Am79C940

HOST SYSTEM INTERFACE

DBUS15-0

Data Bus (Input/Output/3-state)

DBUS contains read and write data to and from internal

registers and the Transmit and Receive FIFOs.

ADD4-0

Address Bus (Input)

ADD i s used to access th e intern al regist ers and FIF Os

to be read or written.

R/W

Read/Write (Input)

Indicates the direction of data flow during the MACE

device register, Transmit FIFO, or Receive FIFO

accesses.

RDTREQ

Receive Data Transf er Request(Output)

Receive Data Transfer Reques t indicates that there is

data in the Receive FIFO t o be read. When RDT REQ

is asserted there will be a minimum of 16 bytes to be

read except at the completion of the frame, in which

case EOF will be asserted. RDTREQ can be pro-

grammed to request receive data transfer when 16, 32

or 64 by tes a re avai lable in th e Rece ive F IFO, by pr o-

gramming the Receive FIFO Watermark (RCVFW bits)

in the FIFO Configuration Control register. The first

assertion of RDTREQ will not occur until at least 64

bytes have been received, and the frame has been ver-

ified as non runt. Runt packets will normally be deleted

from the Receive FIFO with no external activity on

RDTREQ. W hen Runt Pac k et Accept is e nabl ed ( RPA

bit) in the User Test Register , RDTREQ will be asserted

when the ru nt packet comp letes, and the enti re frame

resides in the Receive FIFO. RDTREQ will be as serted

only when Enable Receive (ENRCV) is set in the MAC

Configuration Control register.

The RCVFW can be overridden by enabling the Low

Latency Receive function (setting LLRCV bit) in the

Receive Frame Control register, which allows

RDTREQ to be asserted after only 12 bytes have been

received. Note that use of this function exposes the

system interface to premature termination of the

receive frame, due to network events such as collisions

or runt packets. It is the responsibility of the system

designer to provide adequate recovery mechanisms for

these condi tio ns .

TDTREQ

Transmit Data Transfer Request (Output)

Transmit Data Transfer Request indicates there is

room in the Transmit FIFO for more data. TDTREQ is

asserted when there are a minimum of 16 empty bytes

in the T ransmit FIFO. TDTREQ can be programmed to

request transmit data transfer when 16, 32 or 64 bytes

are available in the Transmit FIFO, by programming the

Transmit FIFO Watermark (XMTFW bits) in the FIFO

Configuration Control register. TDTREQ will be

asserted only when Enable Transmit (ENXMT) is set in

the MAC Configuration Control register.

FDS

FIFO Data Select (Input)

FIFO Data Select allows direct access to the transmit

or Rec eive FIFO without use of th e A DD add re ss bus .

FDS mus t be activ at ed i n c onj un ction with R/W. Whe n

the MACE device samples R/W as high and FDS l ow,

a read cycle from the Receive FIFO will be initiated.

When the MACE chip samples R/W and FDS low, a

write cycle to the Transmit FIFO will be initiated. The

CS line should be inactive (high) when FIFO access is

requested using the FDS pin. If the MACE device sam-

ples both CS and FDS as active simultaneously, no

cycle will be executed, and DTV will remain inactive.

DTV

Data Transfer Valid (Output/3-state)

When ass erted, indi cates that the read or wr ite opera-

tion has comple ted succes sfully. T he abse nce of DTV

at the termination of a host access cycle on the MACE

device indicates that the data transfer was unsuccess-

ful. DTV nee d not be used if th e system i nterface can

guarantee that the latency to TDTREQ and RDTREQ

asser tion and de -asser tion wi ll not ca use the Transmit

FIFO to be over-written or the Receive FIFO to be

over-re ad. In thi s case , the lat ch ing or strob in g of rea d

or write data can be synchronized to the SCLK input

rather than to the DTV output.

EOF

End Of Frame (Input/Output/3-state)

End Of Frame will be asserted by the MACE device

when the las t byte/ w ord of fr a me da ta is r ead from th e

Receive FIFO, indicating the completion of the frame

data field for the receive message. End Of Frame must

be asserted low to the MACE device when the last

byte/word of the frame is written into the Transmit

FIFO.

BE1–0

Byte Enable (Input)

Used to indic ate the active por tion of the data transf er

to or from the internal FIFOs. For word (16-bit) trans-

fers, both BE0 and BE1 should be activated by the

external host/controller. Single byte transfers are per-

formed by identifying the active data bus byte and acti-

vating onl y one of the two signa ls. The function of the

BE1-0 pins is programmed using the BSWP bit (BIU

Configuration Control register, bit 6). BE1-0 are not

required for accesses to MACE device registers.

Am79C940 27

Chip Select (Input)

Used to access the MACE device FIFOs and internal

registers locations using the ADD address bus. The

FIFOs may alternatively be directly accessed without

supplying the FIFO address, by using the FDS and

R/W pins.

INTR

Interrupt (Output, Open Drain)

An attention signal indicating that one or more of the

following status flags are set: XMTINT, RCVINT,

MPCO, RPCO, RCVCCO, CERR, BABL, or JAB. Each

interrupt source can be individua lly masked. N o inter-

rupt condition can take place in the MACE device

immediately after a hardware or software reset.

RESET

Reset (Input)

Reset clears the internal logic. Reset can be asynchro-

nous to SCLK, but must be asserted for a minimum

duration of 15 SCLK cycles.

SCLK

System Clock (Input)

The system clock input controls the operational fre-

quency o f the slave in terfac e to the MACE d evic e and

the internal processing of frames. SCLK is unrelated to

the 20 MHz clock frequency required for the 802.3/

Ethernet interface. The SCLK frequency range is

1 MHz-25 MHz.

EDSEL

System Clock Edge Select (Input)

EDSEL is a static input that allows System Clock

(SCLK) edg e selectio n. If EDSEL is tie d high, the bus

interface unit will assume falling edge timing. If EDSEL

is tied low, the bus interface unit will assume rising

edge timing, which will effectively invert the SCLK as it

enters the MACE device, i.e., the address, control lines

(CS, R/W, FDS, etc) and data are all latched on the ris-

ing edge of SCLK, and data ou t is driven off the rising

edge of SCLK.

Timing Control (Input)

The T iming Control input conditions the minimum num-

ber of System Clocks (SCLK) cycles taken to read or

write the internal registers and FIFOs. TC can be us ed

as a wait state generator, to allow additional time for

data to be presented by the host during a write cycle,

or allow additional time for the data to be latched during

a read cycle. TC has an internal (SLEEP disabled)

pull up. Timing Control

IEEE 1149.1 TEST ACCESS PORT (TAP)

INTERFACE

TCK

Test Clock (Input)

The clock input for the bound ar y scan te st mod e oper-

ation. T CK can opera te up to 10 MHz. TCK h as an i n-

ternal (not SLE EP disabled) pull up.

TMS

Test Mode Select (Input)

A serial input bit stream used to define the specific

boundary scan tes t to be e xecuted. T MS h as an inter -

nal (not SLEEP disabled) pull up.

TDI

Test Data Input (Input)

The test da ta input path to the MACE devi ce. TDI has

an internal (not SLEE P disabled) pull up.

TDO

Test Data Out (Output)

The test data output path from the MACE device.

GENERAL INTERFACE

XTAL1

Crystal Connection (Input)

The internal clock generator uses a 20 MHz crystal that

is attached to pins XTAL1 and XTAL2. Internally, the

20 MHz crystal frequency is divided by two which

determines the network data rate. Alternatively, an

external 20 MHz CMOS-compatible clock signal can be

used to dr ive this pin. The MACE devi ce supports th e

use of 50 pF cryst als to ge nerat e a 20 MHz fr equen cy

which is compatible with the IEEE 802.3 network

fre quency tolerance and jitter specifications.

XTAL2

Crystal Connection (Output)

The internal clock generator uses a 20 MHz crystal that

is attached to pins XTAL1 and XTAL2. If an external

clock gene ra tor is us ed o n XTAL1, then XTAL2 sh oul d

be left uncon nected.

SLEEP

Sleep Mode (Input)

The optimal power savings made is extracted by

asserting the SLEEP pin with both the Auto Wake

(A W AKE bit) and Remote Wake (RWAKE bit) functions

disable d. In this “deep sle ep” mode, all outputs will be

forced into th eir inactiv e or high impe dance state, and

all inputs will be ignored except for the SLEEP, RESE T,

SCLK, TCK, TMS, and TDI pins. SC LK must run for 5

cycles after the assertion of SLEEP. During the “Deep

Sleep”, the SCLK input can be optionally suspended

for maximum power savings. Upon exiting “Deep

Sleep”, the hardware RESET pin must be asserted and

the SCLK restored. The system must delay the setting

TC Number of

Clocks

28 Am79C940

of the bits in the MAC configuration Control Register of

the internal analog circuits by 1 ns to allow for

stabilization.

If the A W AKE bit is set prior to the activation of SLEEP,

the 10BASE–T receiver and the LNKST output pin

remain operational.

If the RWAKE bit is set prior to SLEEP bein g as se rt e d,

the Manc hester enc oder/decod er, AUI and 10B ASE-T

cells remain operational, as do the SRD, SRDCLK and

SF/BD outputs.

The input on XT AL1 must remain active for the AW AKE

or RW AKE features to operate. After exit from the Auto

Wake or Remote Wake modes, activati on of hardwar e

RESET is not required when SLEEP is reasserted.

On deassertion of SLEEP, the MACE device will go

through an internally generated hardware reset

sequence, requiring re-initialization of MACE registers.

Power Supply

DVDD

Digital Power

There are four Digital VDD pins.

DVSS

Digital Ground

There are six Digital VSS pins.

AVDD

Analog Power

There are four analog VDD pins. Special attention

should be paid to the printed circuit board layout to

avoid ex cessive noise on the suppl y to the PLL i n the

Manchester encoder/decoder (pins 66 and 83 in PLCC,

pins 67 and 88 in PQFP). These supply lines should be

kept separate from the DVDD lines as far back to the

power supply as is practically possible.

AVSS

Analog Ground

There are two analog VSS pins. Special attention

should be paid to the printed circuit board layout to

avoid ex cessive no ise on the P LL supply in Manches-

ter encoder/decoder (pin 73 in PLCC, pin 74 in PQFP).

These supply lines should be kept separate from the

DVSS lines as far back to the power supply as is

practically possible.

PIN FUNCTIONS NOT AVAILABLE WITH

THE 80-PIN TQFP PACKAGE

In the 84-pin PLCC configuration, ALL the pins are

used while in the 100-pin PQFP version, 16 pins are

specifi ed as No Co nnec ts . M oving to th e 80 - pin T QFP

configuration requires the removal of 4 pins. Since

Ethernet controllers with integrated 10BASE-T have

analog portions which are very sensitive to noise,

power and ground pins are not deleted. The MACE

device does have several sets of media interfaces

which typically go unused in most designs, however.

Pins from some of these interfaces are deleted instead.

Removed are the following:

■TXDAT– (previously used for the DAI interface)

■SRD (previously used for the EADI interface)

■DTV (previously used for the host interface)

■RXPOL (previously used as a receive frame polarity

LED driver)

Note that pins from four separate interfaces are

removed rather than removing all the pins from a single

interface. Each of these pins comes from one of the

four si des of t he d ev ice. T his i s do ne to mai ntai n sy m-

metry, thus avoiding bond out problems.

In general, the most critical of the four removed pins

are TXDAT– and SRD. Depending on the application,

either the DAI or the E ADI inter fac e may be imp or tan t.

In most designs, however, this will not be the case.

PINS REMOVED FOR TQFP PACKAGE

AND THEIR EFFECTS

TXDAT–

The re moval of T XDAT– means that the DAI interface is

no longer usable. The DAI interface was designed to be

used with media types that do not require DC isolation

betw een the MAU and t he DTE. Me dia whic h do not re-

quire DC isolation can be implemented more simply

usin g the DAI inte rface, rath er than the AUI int erface. In

most de signs thi s is no t a prob lem be cause most medi a

require s DC isolat ion (10BASE-T, 10BA SE2, 10BASE5 )

and w ill use the A UI port. A bout the on ly media w hich

does no t re qu ire DC isol at ion is 10BASE-F.

SRD

The SRD pin is an output pin used by the MACE device

to transfer a receive data stream to external address

detection logic. It is part of the EADI interface. This pin

is used t o hel p inter fa ce t he MA CE devic e to an ex ter-

nal CAM device. Use of an external CAM is typically

requir ed when a n appli catio n will o perate in p romi scu-

ous mode a nd wil l need per fect filte ring (i .e., the i nter-

nal hash filter will not suffice). Example applications for

this so rt of operatio n are bridges and routers . L ack of

perfect filtering in these applications forces the CPU to

be more involved in filtering an d thus eith er slows th e

forward ing rates achi eved or for ces the use o f a more

powerful CPU.

DTV

The DTV pi n is part of the host interfac e to the MACE

device . It is used t o indic ate tha t a read or wri te cycl e

to the MA CE dev ic e was succ es sf ul. If DTV is n ot a s-

serted at the end of a cycle, the data tran sfer was not

successful. Basically, this will happen on a write to a

full transmit FIFO or a read from an empty receive

Am79C940 29

FIFO. In general, there are ways to ensure that a

transfer is always valid; so this pin is not required in

many designs. For instance, the TDTREQ and

RDTREQ pins can be used to mon itor the stat e of the

FIFOs to ensure that data transfer only occurs at the

correct times.

RXPOL

RXPOL is typically used to drive an LED indicating the

polarity of receive frames. This function is not

necessary for correct operation of the Ethernet and

serves strictly as a status indication to a user . The sta-

tus of the receive polarity is still available through the

PHYCC regis ter.

30 Am79C940

FUNCTIONAL DESCRIPTION

The Media Access Controller for Ethernet (MACE) chip

embodies the Media Access Control (MAC) and Phys-

ical S ignal ing (P LS) sub- laye rs of the 802.3 Standa rd.

The MACE device provides the IEEE defined Attach-

ment Unit Interface (AUI) for coupling to remote Media

Attachment Units (MAUs) or on-board transceivers.

The MACE device also provides a Digital Attachment

Interface (DAI), by-passing the differential

AUI interface.

The system interface provides a fundamental data

conduit to and from an 802.3 network. The MACE de-

vice in conjunction with a user defined DMA engine,

provides an 802.3 interface tailored to a specific

application.

In addition, the MACE device can be combined with

similarly architected peripheral devices and a

multi-channel DMA controller, thereby providing the

system wit h acc es s to m ul tipl e per ip her al de vi ce s wit h

a single master interface to memory.

Network Interfaces

The MA CE device can be con nected to a n 802.3 net-

work using any one of the AUI, 10 BASE-T, DAI and

GPSI network interfaces. The Attachment Unit Inter-

face (AUI) provides an IEEE compliant differential in-

terface to a remote MAU or an on-board transceiver.

An integ rated 10BA SE-T MAU provides a direct i nter-

face for twisted pair Ethernet n etworks. The DA I port

can connect to local transceiver devices for 10BASE2,

10BASE -T or 10BASE-F connections . A Gener al Pur-

pose Serial Interface (GPSI) is supported, which effec-

tively bypasses the integrated Manchester encoder/

decoder, and allows direct access to/from the integral

802.3 Medi a Access Contr oller (MAC) to pr ovide sup-

port for external encoding/decoding schemes. The in-

terface in use is determined by the PORTSEL [1-0] bits

in the PLS Configuration Control register.

The EADI port does not provide network connectivity,

but allows an optional external circuit to assist in

receive packet accept/reject.

System Interface

The MACE device is a slave register based peripheral.

All transfers to and from the device, including data, are

performed us ing simple memory or I/O read and write

commands. Access to all registers, including the Trans-

mit and Receive FIFOs, are performed with identical

read or write timing. All information on the system inter-

face is synchronous to the system clock (SCLK), which

allows simple external logic to be designed to

interrogate the device status and control the network

data flow.

The Recei ve and Transmit FIFOs can be read or writ-

ten by driving the appropriate address lines and assert-

ing CS and R/W. An alternative FIFO access

mechanism allows the use of the FDS and the R/W

lines, ignoring the address lines (ADD4-0). The state of

the R/W line in conjunction with the FDS input deter-

mines whether the Receive FIFO is read (R/W high) or

the Transmit FIFO written (R/W low). The MACE de-

vice syste m interf ace per mits i nterleav ed trans mit an d

receive bus transfers, allowing the Transmit FIFO to be

filled (primed) while a frame is being received from the

network and/or read from the Receive FIFO.

In receive operation, the MACE device asserts Receive

Data T ransfer Request (RDTREQ) when the FIFO con-

tains adequate data. For the first indication of a new

receive frame, 64 bytes must be received, assuming

normal operation. Once the initial 64 byte threshold has

been reac hed , R DT REQ assertion and de-ass erti on is

dependent on the programming of the Receive FIFO

W atermark (RCVFW bits in the BIU Configuration Con-

trol register). The RDTREQ can be programmed to

activate when there are 16, 32 or 64 bytes of data avail-

able in the Receive FIFO. Enable Receive (ENRCV bit

in MAC Configuration Contro l register) must be set to

assert RDTREQ. If the Runt Packet Accept feature is

invo ked (RPA bi t in User Test Register), RDTREQ will

be asserted for receive frames of less than 64 bytes on

the basis of internal and/or external address match

only . When RP A is set, RDTREQ will be assert ed when

the entir e frame has been rec eived or wh en the init ial

64 byte threshold has been exceeded. See the FIFO

Sub-Systems section for further details.

Note that the Receive FIFO may not contain 64 data

bytes at the time RDTREQ is asserted, if the automatic

pad stri pping feature has been enabled (AS TRP RCV

bit in the Receive Frame Control register) and a mini-

mum length packet with pad is received. The MACE

device will check for the minimum received length from

the network, strip the pad characters, and pass only the

data frame through the Receive FIFO.

If the Low Latency Receive feature is enabled (LLRCV

bit set in Receive Frame Control Register), RDTREQ

will be asserted once a low watermark threshold has

been reached (12 bytes plus some additional synchro-

nization time). Note that the system interface will there-

fore be exposed to potential disruption of the receive

frame due to a network condition (see the FIFO

Sub-System description for additional details).

In transmit operation, the MACE device asserts Trans-

mit Data Transfer Request (TDTREQ) dependent on

the programming of the Transmit FIFO Watermark

(XMTFW bits in the BIU Configuration Control register).

TDTREQ will be permanently asserted when the

Transmit FIFO is empty. The TDTREQ can be pro-

gra mme d to ac tiva te w hen th ere are 16, 32 or 6 4 b yte s

of space available in the Transmit FIFO. Enable T rans-

mit (ENXMT bit in MAC Configuration Control register)

must be set to assert TDTREQ. Write cycles to the

Am79C940 31

Transmit FIFO will not return DTV if ENXMT is dis-

abled, and no data will be written. The MACE device

will commence the preamble sequence once the

Transmit Start Point (XMTSP bits in BIU Configuration

Control register) threshold is reached in the Transmit

FIFO.

The Transmit FIF O da ta will n ot be over written u ntil a t

least 512 data bits have been transmitted onto the net-

work. If a collision occurs within the slot time (512 bit

time) window , the MACE device will generate a jam se-

quence (a 32-bit all zeroes pattern) before ceasing the

transmiss ion. Th e Transmit F IFO wil l be reset to poin t

at the st art of the tr ansmi t data fie ld, and th e me ss ag e

will be retried after the random back-off interval has

expired.

DETAILED FUNCTIONS

Block Level Description

The following sections describe the major sub-blocks

of and the external interfaces to the MACE device.

Bus Interface Unit (BIU)

The BIU performs the interface between the host or

system bus and the Transmit and Receive FIFOs, as

well as all chip control and status registers. The BIU

can be configured to accept data presented in either lit-

tle-endian or big indian format, minimizing the external

logic required to access the MACE device internal

FIFOs and registers. In addition, the BIU directly

supports 8-bit transfers and incorporates features to

simplify interfacing to 32-bit systems using

external latches.

Externa lly, the FIFO s appear as two indep endent reg-

isters located at individual addresses. The remainder

of the inte rn al regi ste rs o cc up y 3 0 a dditional c onsec u-

tive addresses, and appear as 8-bits wide.

BIU to FIFO Data Path

The BIU operates assuming that the 16-bit data path

to/from the internal FIFOs is configured as two inde-

pendent byte paths, activated by the Byte Enable

sig nals BE0 and BE1.

BE0 and BE1 are only used during accesses to the

16-bit wide Transmit and Receive FIFOs. After hard-

ware or software reset, the BSWP bit will be cleared.

FIFO accesses to the MACE device will operate

assuming an Intel 80x86 type memory convention

(most significant byte of a word stored in the higher

addressed byte). Word data transfers to/from the

FIFOs over the DBUS15-0 lines will have the least sig-

nificant byte located on DBUS7-0 (activated by BE0)

and the most significant byte located on DBUS15-8

(activated by BE1).

FIFO data can be read or written using either byte and/

or word operations.

If byte operation is required, read/write transfers can be

performed on either the upper or lower data bus by

asserting the appropriate byte enable. For instance

with BSWP = 0, reading from or writing to DBUS15-8 is

accomplished by asserting BE1, and allows the data

stream to be read from or written to the appropriate

FIFO in byte order (byte 0, byte 1,....byte n). It is equally

valid to read or write the data stream using DBUS7–0

and by ass ertin g BE0. For BSWP = 1, readin g from or

writing to DBUS15-8 is accomplished by asserting BE0,

and allows the byte stream to be transferred in byte

order.

When word operations are required, BSWP ensures

that t he by te or de r i ng of t he tar g e t memo r y is c om p ati-

ble with the 802.3 requirement to send/receive the data

stream in byte ascending order. With BSWP = 0, the

data tran sfe rred to/f ro m th e F IFO assu mes th at by te n

will be on DBUS7-0 (activated by BE0) and byte n+1

will be on DBUS15-8 (activated by BE1). With BS WP =

1, the da ta trans ferred to/from the FIFO assumes tha t

byte n will be presented on DBUS15-8 (activated by

BE0), and byte n+1 will be on DBUS7-0 (activated by

BE1).

There are so me additional spe cial cases to the above

generalized rules, which are as follows:

(a) When performing byte read operations, both

halves of the data bus are driven with identical

data, effectivel y allowing the user to arbitrarily read

from either the upper or lower data bus, when only

one of the byte enables is activated.

(b) When byte write operations are performed, the

Transmit FIFO latency is affected. See the FIFO

Sub-System section for additional details.

a receive frame (EOF is asserted), and the mes-

sage contained an odd number of bytes but the

host requested a word operation by asserting both

BE0 and BE1, then th e MACE device will present

one valid and one non -valid byte on th e data bus.

The placement of valid data for the data byte is de-

pendent on the target memory architecture. Re-

gardless of BSWP, the single valid byte will be read

from the BE0 memory bank. If BSWP = 0, BE0 cor-

responds to DBUS7-0; if BSWP = 1, BE0 corre-

sponds to DBUS15-8.

(d) If a byte read is performed when the last data byte

is read for a receive frame (when the MACE device

activate s the EOF signa l), then the same byte wi ll

be presen ted on both the upper and lower byte of

the data bus, regard less of wh ic h by te en abl e was

activated (as is the case for all byte read opera-

tions).

(e) When writing the last byte in a transmit message

to the Transmit FIFO, the portion of the data bus

32 Am79C940

that the last byte is transferred over is irrelevant,

providi ng the appr opri ate by te enabl e is us ed. For

BSWP = 0, data can be presented on DBUS7-0

using B E0 or DBUS15-8 us ing BE1. For BSWP =

1, data can be presented on DBUS7-0 using BE1

or DBUS15-8 using BE0.

(f) When neither BE0 nor BE1 are asserted, no data

transfer will take place. DTV will not be asserted.

Byte Alignment For FIFO Read Operations

Byte Alignment For FIFO Write Ope rations

BIU to Control and Status

Regist er Da t a Path

All registers in the address range 2-31 are 8-bits wide.

When a read cycle is executed on any of these re gis-

ters, the MACE device will drive data on both bytes of

the d ata bus, r ega rdl ess of the prog ra mmi ng of BS WP.

When a write cycle is executed, the MACE device

strobes in data based on the programming of BSWP as

shown in the tables below. All accesses to addresses

2-31 are independent of the BE0 and BE1 pins.

Byte Alignment For Register Read Operations

Byte Alignment For Register Write Operations

FIFO Subsystem

The MACE device has two independent FIFOs, with

128-byt es f or rece ive an d 136-b ytes f or t ransmit oper-

ations. The FIFO sub-system contains both the FIFOs,

and the control logic to handle normal and exception

related co ndi tions.

The Transmit an d Rec ei ve FIF Os in terf ace o n the net-

work side with the serializer/de-serializer in the MAC

engine. The BIU provides access between the FIFOs

and the host system to enable the movement of data to

and from the network.

Internally, the FIFOs appear to the BIU as independent

16-bit wid e registers. By tes or words ca n be written to

the Transmit FIFO (XMTFIFO), or read from the

Receive FIFO (RCVFIFO). Byte and word transfers

can be mixed in any order. The BIU will ensure correct

byte orderi ng dep end ent on the targ et host sy s tem, as

determined by the programming of the BSWP bit in the

BIU Configuration Control register.

The XMTFIFO and RCVFIFO have three different

modes of operation. These are Normal (Default), Burst

and Low Latency Receive. Default operation will be

used after the hardware RESET pin or software

SWRST bit have been activated. The remainder of this

general desc riptio n a pplie s to all mod es e xcept wher e

specific differences are noted.

Transmit FIFO—Gene ral Ope ration

When writing bytes to the XMTFIFO, certain restric-

tions apply. These restrictions have a direct influence

on the latency provided by the FIFO to the host system.

When a by te is writ ten to th e FIFO loc ation, the enti re

word location is used. The unused byte is marked as a

hole in the XMTFIF O. These holes are skipp ed durin g

the serialization process performed by the MAC

engine, when the bytes are unloaded from the

XMTFIFO.

For instance, assume the Transmit FIFO Watermark

(XMTFW) is set for 32 write cycles. If the host writes

byte wide data to the XMTFIFO, after 36 write cycles

there will be space left in the XMTFIFO for only 32

more write cycles. Therefore TDTREQ will de-assert

even though only 36-bytes of data have been loaded

into the XMTFIFO. Transmission will not commence

until 64- by tes o r t he End-of-Frame are ava il abl e in the

XMFIFO, so transmission would not start, and

BE0 BE1 BSWP DBUS7-0 DBUS15-8

00 0 n n+1

01 0 n n

10 0 n n

11 0 X X

00 1 n+1 n

01 1 n n

10 1 n n

11 1 X X

BE0 BE1 BSWP DBUS7-0 DBUS15-8

00 0 n n+1

01 0 n X

10 0 X n

11 0 X X

00 1 n+1 n

01 1 X n

10 1 n X

11 1 X X

BE0 BE1 BSWP DBUS7-0 DBUS15-8

XX 0 Read

Data Read

Data

XX 1 Read

Data Read

Data

BE0 BE1 BSWP DBUS7-0 DBUS15-8

XX 0 Write

Data X

XX 1 XWrite

Data

Am79C940 33

TDTREQ would remain de-asserted. Hence for byte

wide data transfers, the XMTFW should be pro-

grammed to the 8 or 16 write cycle limit, or the host

should ens ure that su fficien t data will be writt en to the

XMTFIFO af ter TDTREQ has been de-asserted (which

is permitted), to guarantee that the transmission will

commence. A third alternative is to program the T rans-

mit Start Point (XMTSP) in the BIU Configuration Con-

trol register to below the 64-byte default; thereby

imposin g a lower latency to the host system requiring

additional data to ensure the XMTFIFO does not

underflow during the transmit process, versus using

the default XMTSP value. Note that if 64 single byte

writes are executed on the XMTFIFO, and the XMTSP

is set to 64-bytes, the transmission will commence, and

all 64-bytes of information will be accepted by

the XMTFIFO.

The num ber of write cycles t hat the host u ses to writ e

the packe t into the Transmit FIFO will also directly in-

fluence the amount of space utilized by the transmit

message . If the number of write cycle s (n) required to

transfer a packet to the Transmit FIFO is even, the

number of bytes used in the Transmit FIFO will be 2*n.

If the number of write cycles required to transfer a

packet to the Transmit FIFO is odd, the number of

bytes used in the Transmit FIFO will be 2*n + 2 be-

cause the En d Of Frame ind ication i n the X MTFIF O is

always placed at the end of a 4-byte boundary. For ex-

ample, a 32-byte message written as bytes (n = 32 cy-

cles) will use 64-bytes of space in the Transmit FIFO

(2*n = 64), whereas a 65-byte message written as 32

words and 1 byte (n = 33 cycles) would use 68-bytes

(2*n + 2 = 68) .

The Transmit FIFO has been sized appropriately to

minimize the system interface overhead. However,

consideration must be given to overall system design if

byte writes are supported. In order to guarantee that

sufficient space is present in the XMTFIFO to accept

the number of write cycles programmed by the XMTFW

(including an End Of Frame delimiter), TDTREQ may

go inactive before the XMTSP threshold is reached

when using the non burst mode (XMTBRST = 0). For

instance, assume that the XMTFW is programmed to

allow 32 write cycles (default), and XMTSP is pro-

grammed to require 64 bytes (default) before starting

transmiss ion. A ssumin g that the h ost bur sts the tr ans-

mit data in a 32 c ycle blo ck, wri ting a s ingle byte any-

where within this block will mean that XMTSP will not

have been reached. This would be a typical scenario if

the transmit data buffer was not aligned to a word

boundary. The MACE device will continue to assert

TDTREQ since an additional 36 write cycles can still be

executed. If the host starts a second burst, the XMTSP

will be reached, and TDTREQ wil l dea ssert w hen less

that 32 write cycle can be performed although the data

written by the host will continue to be accepted.

The host must be aware that additional space exists in

the XMTFIFO although TDTREQ becomes inactive,

and must con tinue to write data to ens ure the XMTSP

threshold is achieved. No transmit activity will com-

mence until the XMTSP threshold is reached.

Once 36 write cycles have been executed.

Note that write cycles can be performed to the XMT-

FIFO even if the TD TREQ is inac tive. Wh en TDTREQ

is asserted, it guarantees that a minimum amount of

space exists, when TDTREQ is deasserted, it does not

necessarily indicate that there is no space in the XMT-

FIFO. The DTV pin will indicat e the succ essful acc ep-

tance of data by the Transmit FIFO.

As another example, assume again that the XMTFW is

programmed for 32 write cycles. If the host writes word

wide data co ntinuo usly to the XMTFIF O, the TDTR EQ

will deassert when 36 writes have executed on the

XMTFIF O, at which poi nt 72- bytes wil l have be en wr it-

ten to the XMTFIFO, the 64-byte XMTSP will have

been exceeded and the transmission of preamble will

have comme nced. T DTREQ will n ot re- as ser t un til th e

transmission of the packet data has commenced and

the possibility of losing data due to a collision within the

slot time is removed (512 bits have been transmitted

without a collision indication). Assuming that the host

actually stopped writing data after the initial 72-bytes,

there will be only 16-bytes of data remaining in the

XMTFIFO (8-bytes of preamble/SFD plus 56-bytes of

data have been transmitted), corresponding to 12.8 µs

of latency before an XMTFIFO underrun occurs. This

latency is considerably less than the maximum possi-

ble 57.6 µs the syste m ma y have a ssume d. If the hos t

had continued with the block transfer until 64 write

cycles had been performed, 128-bytes would have

been written to the XMTFIFO, and 72-bytes of laten cy

would remain (57.6 µs) when TDTREQ was re-as-

serted.

Transmit FIFO—Burst Operation

The XMTFIFO burst mode, programmed by the XMT-

BRST bit in the FIFO Configuration Control register,

modifies TDTREQ behavior . The assertion of TDTREQ

is controlled by the programming of the XMTFW bits,

such that when the specified number of write cycles

can be guaranteed (8, 16 or 32), TDTREQ will be as-

serted. TDTREQ will be de-asserted when the

XMT FIFO can only accept a single write cycle (one

word write including an End Of Frame delimiter) allow-

ing the external device to burst data into the XMTFIFO

when TDTREQ is asserted, and stop when TDTREQ

is deasserted.

Receive FIFO—General Operation

The Receive FIFO contains additional logic to ensure

that suffic ient d ata is presen t in the RCV FIFO to allo w

the specified number of bytes to be read, regardless of

the ordering of byte/word read accesses. This has an

34 Am79C940

impact on the perceived latency that the Receive FIFO

provid es to the hos t syste m. T he desc ripti on and tabl e

below outline the point at which RDTREQ will be

asserted when the first duration of the packet has been

received and when any subsequent transfer of the

packet to the host system is required.

No preamble/SFD bytes are loaded into the Receive

FIFO. All references to bytes pass through the receive

FIFO. These references are received after the pream-

ble/SFD sequence.

The first assertion of RDTREQ for a packet will occur

after the longer of the following two conditions is met:

■64-byte s have b een rece ived ( to assur e runt p ack-

ets and packets experiencing collision within the

slot time will be rejected).

■The RCVFW threshold is reached plus an additional

12 byt es. Th e add itional 12 by tes are neces sary to

ensure that any permutation of byte/word read

access is guaranteed. They are required for all

threshold values, but in the case of the 16 and

32-byte thresholds, the requirement that the slot time

crit eria is met do min ates . Any subseq uent assert ion

of RDTREQ necessary to complete the transfer of

the packet will occur after the RCVFW threshold is

reached plus an additional 12 bytes. The table below

also o utlines the laten cy pro vided by the MA CE de-

vice when the RDTREQ is asserted.

Receive FIFO Watermarks, RDTREQ Assertion and Latency

Receive FIFO—Burst Operation

The RCVFIFO also provides a burst mode capability,

programme d by the RCV BRST bit in the FIFO C onfig-

uration Control register, to modify the operation of

RDTREQ.The as serti on of R DTRE Q will occur accord-

ing to the pr ogramming of th e RCVFW bits. RDTREQ

will be de-asserted when the RCVFIFO can only pro-

vide a single read cycle (one word read). This allows

the external device to burst data from the RCVFIFO

once RDTREQ is asserted, and stop when RDTREQ

is deasserted.

Receive FIFO—Low Latency Receive Operation

The LOW Laten cy Rec eiv e mo de ca n be pr ogram me d

using the Low Latency Receive bit (LLRCV in the

Receive Frame Control register). This effectively

causes the assertion of RDTREQ to be directly coupled

to the low watermark of 12 bytes in the RCVFIFO.

Once the 12-byte threshold is reached (plus some

internal synchronization delay of less than 1 byte),

RDTREQ w ill be assert ed, and will rema in active un til

the RCVFIFO can support only one read cycle

(one word of data), as in the burst operation

describe d ea rli er. The excepti on is the ca se wher e 4-8

bytes of padding is required by the FIFO design, unless

it is the end of the packet.

The intended use for the Low Latency Receive mode is

to allow fast forwarding of a received packet in a bridge

application. In this case, the receiving process is made

aware of the receive packet after only 9.6 µs, instead of

waiting up to 60.8 µs (76-bytes) necessary for the initial

assertion of RDTREQ. An Ethe rnet- to-Ether net b ridg e

employing the MACE device (on all the Ethernet

connections) with the XMTSP of all MACE controller

XMT FIFOs set to the minimum (4-bytes), forwarding of

a receive packet can be achieved within a sub 20 µs

delay including processing overhead.

Note, however, that this mode places significant bur-

den on the host processor . The receiving MACE device

will no longer delete runt packets. A runt packet will

have the Receive Frame Status appended to the re-

ceive data which the host must read as normal. The

MACE device will not attempt to delete runt packets

from the R C VFIF O i n the Low Latency Rec eive mode.

Collision fragments will also be passed to the host if

they are detected after the 12-byte threshold has been

reached . If a collision occ urs, the Receiv e Frame Sta-

tus (RCVFS) will be appended to the data successfully

received in the RCVFIFO up to the point the collision

was detected. No additional receive data will be written

to the RCVFIFO. Note that the RCVFS will not become

available until after the receive activity ceases. The col-

lision indication (CLSN) in the Receive Status

(RCVSTS) wil l be set, and the Recei ve Mess age B yte

Count (RCVCN T) will be the correct count of the total

duration of activity, including the period that collision

was detected. The detection of norm al (slot time) colli-

sions versus late collisions can only be made by

counting the number of bytes that were successfully re-

ceived prior to the termination of the packet data.

In all cases where the reception ends prematurely (runt

or collision), the data that was successfully received

RCVFW

[1-0]

Bytes Required for

First Assertion of

RDTREQ

Bytes of Latency

After First Assertion

of RDTREQ

Bytes Required for

Subsequent Assertion

of RDTREQ

Bytes of Latency After

Subsequent Assertion

of RDTREQ

00 64 64 28 100

01 64 64 44 84

10 76 52 76 52

11 XX XX XX XX

Am79C940 35

prior to the ter mi nati on of rec epti on must be read from

the RCVFIFO before the RCVFS bytes are available.

Media Access Control (MAC)

The Media Access Control engine is the heart of the

MACE device, incorporating the essential protocol

requirements for operation of a compliant Ethernet/

802.3 node, and providing the interface between the

FIFO sub-system and the Manchester Encoder/

Decoder (MENDEC).

The MAC engine is fully compliant to Section 4 of ISO/

IEC 8802-3 (ANSI/IEEE Standard 1990 Second edi-

tion) and ANSI/IEEE 802.3 (1985).

The MAC engine provides enhanced features, pro-

grammed through the Transmit Frame Control and

Receive Frame Control registers, designed to minimize

host super vis io n and pre or post mes sa ge proc es s ing.

These features include the ability to disable retries after

a collision, dynamic FCS generation on a

packet-by-packet basis, and automatic pad field

insertion and deletion to enforce minimum frame

size attributes.

The two primary attributes of the MAC engine are:

■Transmit and receive message data encapsulation

—Framing (frame boundary delimitation, frame

synchronization)

—Addressing (source and destination address

handling)

—Error detection (physical medium transmission

errors)

■Media access management

—Medium allocation (collision avoidance)

—Contention resolution (collision handling)

Transmit and Receive Message Data

Encapsulation

Data passed to the MACE device T ransmit FIFO will be

assumed to be correctly formatted for transmission

over the network as a valid packet. The user is required

to pass the data stream for transmissi on to the MACE

chip in the correct order, according to the byte ordering

convention programmed for the BIU.

The MACE device provides minimum frame size

enforcement for transmit and receive packets. When

APAD XMT = 1 (default), transmit messages will be

padded with sufficient bytes (containing 00h) to ensure

that the receiving station will observe an information

field (destination address, source address, length/type,

data and FCS) of 64-bytes. When ASTRP RCV = 1

(default), the receiver will automatically strip pad and

FCS bytes from the received message if the value in

the length field is below the minimum data size

(46-bytes). Both features can be independently

over-ridden to allow illegally short (less than 64-bytes

of packet data) messages to be transmitted

and/or received.

Framing (Frame Boundary Delimitation,

Frame Synchr onization)

The MACE device will autonomously handle the con-

struction of the transmit frame. When the Transmit

FIFO has been filled to the predetermined threshold

(set by XMTSP), and providing access to the channel

is currently permitted, the MACE device will commence

the 7 byte preamble sequence (10101010b, where first

bit transmitted is a 1). The MACE device will subse-

quently append the Start Frame Delimiter (SFD) byte

(10101011) followed by the serialized data from the

Transmit FIFO. Once the data has been completed, the

MACE device will append the FCS (most significant bit

first) computed on the entire data portion of the

message.

Note that the user is responsibl e for the correct or der-

ing and content in each of the fields in the frame,

including the destination address, source address,

length/type and packet data.

The receiv e sect ion of the MACE dev ice wil l detect a n

incoming preamble sequence and lock to the encoded

clock. T he internal MEN DEC will deco de the serial bi t

stream a nd prese nt this to th e MAC en gine. Th e MAC

will discard the first 8-bits of information before search-

ing for the SF D sequence. Once the SFD is d etected,

all subsequent bits are treated as part of the frame. The

MACE device will inspect the length field to ensure

minimum frame size, strip unnecessary pad characters

(if enable d), and pas s the remai ni ng bytes through the

Receive FIFO to the host. If pad stripping is performed,

the MACE device will also strip the received FCS

bytes, although the normal FCS computation and

checking will occur. Note that apart from pad stripping,

the frame wi ll be passed un modified to the hos t. If the

length field has a value of 46 or greater, the MACE de-

vice will not attempt to validate the length against the

number of bytes contained in the message.

If the frame terminates or suffers a collision before

64-bytes of information (after SFD) have been

received, the MACE device will automatically delete

the frame from the Receive FIFO, without host inter-

vention. Note however , that if the Low Latency Receive

option has been enabled (LLRCV = 1 in the Receive

Frame Control register), the MACE device will not

delete receive frames which experience a collision

once the 12-byte low watermark has been reached

(see the FIFO Sub-System section for additional

details).

Addressing (Source and Destination

Address Handling)

The first 6-bytes of info rmation after SFD will be i nter-

preted as the destination address field. The MACE

device provides facilities for physical, logical and

36 Am79C940

broadcast address reception. In addition, multiple

physical addresses can be constructed (perfect

address filtering) using external logic in conjunction

with the EADI interface.

Error Detection (Physical Medium

Transmission Errors)

The MACE device provides several facilities which

report and recover from errors on the medium. In addi-

tion, the networ k is protected fr om gross errors du e to

inability of the host to keep pace with the MACE

device activ it y.

On completion of transmission, the MACE device will

report the Transmit Frame Status for the frame. The

exact number of transmission retry attempts is reported

(ONE, MORE used with XMTRC, or RTRY), and

whether the MACE device ha d to Defer (DEFER) du e

to channel activity. In addition, Loss of Carrier is

reported, indicating that there was an interruption in the

ability of the MACE device to monitor its own transmis-

sion. Repeated LCAR errors indicate a potentially

faulty transceiver or network connection. Excessive

Defer (EXDEF) will be reported in the Transmit Retry

Count register if the transmit frame had to wait for an

abnormally long period before transmission.

Additional transmit error conditions are reported

through the Interrupt Register.

The Late Collision (LCOL) error indicates that the

transmission suffered a collision after the slot time.

This is indicative of a badly configured network. Late

collisions should not occur in normal operating net-

work.

The Collision Error (CERR) indicates that the trans-

ceiver did not respond with an SQE Test message

within the predetermined time after a transmission

completed. This may be due to a failed transceiver,

disconnected or faulty transceiver drop cable, or the

fact the tr ansceiver d oes not su pport this feature (or it

is disabled).

In addition to the reporting of network errors, the MACE

device will also attempt to prevent the crea tion of any

network err or caus ed b y in abi li ty of the ho st to s er vic e

the MACE device. During transmission, if the host fails

to keep the Transmit FIFO filled sufficiently, causing an

underflow, the MACE device will guarantee the

message is eith er sent a s a runt pa cket (wh ich wil l be

deleted b y the rec ei ving station) or ha s an in va lid FCS

(which w il l al so al low the r ec ei ving station to r ej ec t th e

message).

The stat us of ea ch re ceiv e mess age is pass ed vi a the

Receive Fr ame Sta tus by te s. FC S a nd Fra min g e rror s

(FRAM) are reported, although the received frame is

still passed to the host. The FRAM error will only be

reported if an FCS error is detected and there are a non

integral number of bytes in the message. The MACE

device will ignore up to seven additional bits at the end

of a message (dribbling bits), which can occur under

normal networ k operati ng co nditio ns. T he rece ption o f

eight additional bits will cause the MACE device to

de-serialize the entire byte, and will result in the

received message and FCS being modified.

Received messages which suffer a collision after

64-byte times (after SFD) will be marked to indicate

they have suffered a late collision (CLSN). Additional

counters are provided to report the Receive Collision

Count and Runt Packet Count to be used for network

statistics and utilization calculations.

Note that if the MACE device detects a received packet

which has a 00b pattern in the preamble (a fter the firs t

8-bits which are ignored), the entire packet will be

ignored . The MACE de vice wi ll wait for the network t o

go inactive before attempting to receive additional

frames.

Media Access Management

The basic requirement for all stations on the network

is to pr ovide fair nes s of channel a ll oc ati on. The 8 02.3/

Etherne t protoc ols define a med ia access mech anism

which permits all stations to access the channel with

equality . Any node can attempt to contend for the chan-

nel by waiting for a predetermined time (Inter Packet

Gap interval) after the last activity, before transmitting

on the med ia. The channel is a bus or multidr op com-

municati on s medium ( with vari ous top olo gic al co nfi gu-

rations permitted) which allows a single station to

transmit and all other station s to receive. If two no des

simultaneously contend for the channel, their signals

will interact causing loss of data, defined as a collision.

It is the responsibility of the MAC to attempt to avoid

and recover from a collision, to guarantee data integrity

for the end-to-end transmission to the receiving station.

Medium Allocation (Collision Avoidance)

The IEEE 802.3 Standard (ISO/IEC 8802-3 1990)

requires that the CSMA/CD MAC monitors the medium

for traffic by watching for carrier activity. When carrier

is detected, the media is considered busy, and the

MAC should defer to the existing message.

The IEEE 802.3 Standard also allows optional two part

deferral after a receive message.

See ANSI/IEEE Std 802.3-1990 Edition, 4.2.3.2.1:

Note: “ It is pos sible fo r the PLS car rier sen se ind ica-

tion to fail to be asserted during a collision on the

media. If the deference process simply times the inter-

Frame ga p based on this indi cation it is possi ble for a

short interFrame gap to be generated, leading to a

potential reception failure of a subsequent frame. To

enhance system robustness the following optional

measures, as specified in 4.2.8, are recommended

when interFrameSpacing Part1 is other than zero:”

Am79C940 37

(1) Upon compl eting a transm ission, start timing th e

interpacket gap, as soon as transmitting and carrier

Sense are both false.

(2) When timing an interFrame gap following

reception, reset the interFrame gap timing if

carrierSense becomes true during the first 2/3 of the

interF rame g ap timing inter val. During the final 1/3 o f

the interval the timer shall not be reset to ensure fair

access to the medium. An initial period shorter than 2/

3 of the interval is permissible including zero.“

The MAC en gine implements the optional rec eive two

part deferral algorithm, with a first part in-

ter-frame-spacing time of 6.0 µs. The second part of

the inter-frame-spacing interval is therefore 3.6 µs.

The MACE device will perform the two part deferral

algorithm as specified in Section 4.2.8 (Process Defer-

ence). The Inter Packet Gap (IPG) timer will start timing

the 9.6 µs Inte rFrameS pacing af ter the receiv e carrier

is de-asserted. During the first part deferral

(InterFrameSpacingPart1-IFS1) the MACE device will

defer any pending transmit frame and respond to the

receive message. The IPG counter will be reset to zero

continuo usly un til the c arrier de asserts, a t which p oint

the IPG counter will resume the 9.6 µs count once

again. Once the IFS1 period of 6.0µs has elapsed, the

MACE device will begin timing the second part deferral

(InterFrameSpacingPart2-IFS2) of 3.6 µs. Once IFS1

has comp leted, an d IFS2 has commenc ed, the M ACE

chip will not defer to a receive packet if a transmit

packet is pending. This means that the MACE device

will not attempt to receive an incoming packet, and it

will start to transmit at 9.6 µs regardless of network

activi ty, forcing a coll is io n if an exi sting trans mi ssio n is

in progr ess. The MACE device will g uarantee to co m-

plete the preamble (64-bit) and jam (32-bit) sequence

before c easing transmi ssion and i nvoking the ra ndom

backoff algorithm.

In addition to the deferral after receive process, the

MACE devi ce also allo ws transmit two part deferral to

be implemented as an option. The option can be dis-

abled using the DXMT2PD bit in the MAC Configura-

tion Control register. Two part deferral after

transmission is useful for ensuring that severe IPG

shrinkage cannot occur in specific circumstances,

causing a transmit message to follow a receive mes-

sage so closely, as to make them indistinguishable.

During the time period immediately after a transmission

has been completed, the external transceiver (in the

case of a standard AUI connected device), should gen-

erate the SQ E Test mess ag e (a nom in al 10 MH z burs t

of 5-15 BT duration) on th e CI± pair ( within 0.6 -1.6 µs

after the transmiss ion cease s). During the time p eriod

in which the SQE Test message is expected the MACE

device will not respond to receive carrier sense.

See ANS t42I/IEEE Std 802.3-1990 Edition,

7.2.4.6 (1)):

“At the conclusion of the output function, the DTE

opens a time window during which it expects to see

the signal_quality_error signal asserted on the

Control In circuit. The time window begins when the

CARRIER_STATUS becomes CARRIER_OFF. If

execution of the output function does not cause

CARR IER _ON t o oc cur, no S QE te st oc cur s in t he

DTE. The duration of the window shall be at least

4.0 µs but no more than 8.0 µs. During the time win-

dow the Carrier Sense Function is inhibited.”

The MACE device implements a carrier sense blinding

period within 0 µs-4.0 µs from deassertion of carrier

sense after transmission. This effectively means that

when transmit two par t deferral is enabled (DXMT2PD

in the MAC Configuration Control register is cleared)

the IFS1 time is from 4 µs to 6 µs after a transmission.

However, since IPG shrinkage below 4 µs will not be

encountered on correctly configured networks, and

since the fragment size will be larger than the 4 µs

blindin g window, then the IPG counter wil l be reset by

a worst case IPG shrinkage/fragment scenario and the

MACE device will defer its transmission. The MACE

chip wil l not restart t he carrier sense blinding peri od if

carrier is detected within the 4.0-6.0 µs po rtion of IF S1,

but will restart timing of the entire IFS1 period.

Contention Resolution (Collision Handling)

Collision detection is performed and reported to the

MAC engine either by the integrated Manchester

Encoder/Decoder (MENDEC), or by use of an external

function (e.g. Serial Interface Adaptor, Am7992B)

utilizing the GPSI.

If a collision is detected before the complete preamble/

SFD sequence has been transmitted, the MACE de-

vice will complete the preamble/SFD before appending

the jam sequence. If a collision is detected after the

preamble/SFD has been completed, but prior to 512

bits being transm itted, the MACE device will abort the

transmission, and append the jam sequence immedi-

ately. The jam sequence is a 32-bit all zeroes pattern.

The MACE device will attempt to transmit a frame a

total of 16 times (initi al attempt plu s 15 retries) d ue to

normal collisions (those within the slot time). Detection

of collis ion will cause the tra nsmi ssion to be re-sch ed-

uled, dependent on the backoff time that the MACE de-

vice c omputes . Each coll isio n which oc curs during th e

transmission process will cause the value of XMTRC in

the Transmit Retry Count register to be updated. If a

single retry was required, the ONE bit will be set in the

Transmit Fram e Statu s. If mor e than on e retry wa s re-

quired, the MORE bit will be set, and the exact number

of attempts can be determined (XMTRC+1). If all 16 at-

tempts experienced collisions, the RTRY bit will be set

38 Am79C940

(ONE and MO RE will be clear ), and the transmi t mes-

sage will be flushed from the XMTFIFO, either by reset-

ti ng t he X MTF IFO (i f no End-of-Frame tag exists) or by

moving the XMTFIFO read pointer to the n ext free lo-

cation (If an End-of-Frame tag is present). If retries

have been disabled by setting the DRTRY bit, the

MACE device will abandon transmission of the frame

on dete ction of the f irst co llisio n. In this case, on ly the

RTRY bit wil l be set and the transmit mes sage will be

flushed from the XMTFIFO. The RTRY condition will

cause the de-as sert ion of TD TREQ , and the ass ertio n

of the INTR pin, providing the XMTINTM bit is cleared.

If a co llision is d etected after 512 bit times have been

transmitted, the collision is termed a late collision. The

MACE device will abort the transmission, append the

jam sequence and set the LCOL bit in the Transmit

Frame Status. No retry attempt will be scheduled on

detection of a late collision, and the XMTFIFO will be

flushed. The late collision condition will cause the

de-assertion of TDTREQ, and the assertion of the

INTR pin, providing the XMTINTM bit is cleared.

The IEEE 802.3 Standard requires use of a truncated

binary e xponentia l back off algo rithm which prov ides a

controlled pseudo random mechanism to enforce the

collision backoff interval, before re-transmission is

attempted.

See ANSI/IEEE Std 802.3-1990 Edition, 4.2.3.2.5:

“At the end of e nforcing a col lision (jamm ing),

the CSMA/CD sublayer delays before attempt-

ing to re-transmit the frame. The delay is an in-

teger mul tiple of slot Time. The number of slot

times to delay before the nth re-transmission

attempt is chosen as a uniformly distributed

random integer r in the range:

0 ≤ r ≤ 2k, where k = min (n,10).“

The MACE device implements a random number

generator, configured to ensure that nodes

experiencing a collision, will not have their retry inter-

vals track identically, causing retry errors.

The MACE device provides an alternative algorithm,

which sus pends the counting o f the sl ot time/IPG dur-

ing the time that receive carrier sense is detected. This

aids in networks where large numbers of nodes are

present, and numerous nodes can be in collision. It

effectively ac celer ate s the inc re as e in the bac ko ff time

in busy networks, and allows nodes not involved in the

collision to access the channel whilst the colliding

nodes await a reduction in channel activity . Once chan-

nel activity is reduced, the nodes resolving the collision

time-out their slot time counters as normal.

If a receive message suffers a collision, it will be either

a runt, in which case it will be deleted in the Receive

FIFO, or it will be marked as a receive late collision,

using the CLSN bit in the Receive Frame Status regis-

ter. All frames which suffer a collision within the slot

time will be deleted in the Receive FIFO without

requesting host intervention, providing that the LLRCV

bit (Receive Frame Control) is not set. Runt packets

which suffer a collision will be aborted regardless of the

state of the RPA bit (User Test Register). If the collision

commences after the slot time, the MACE device

receiver will stop sending collided packet data to the

Receive FIFO and the packet data read by the system

will con tain the amount of data r ec eiv ed to t he po int of

collision; the CLSN bit in the Receive Frame Status

the Receive Message Byte Count will report the total

number of bytes during the receive activity, including

the collision.

In all norma l r ece iv e co ll is io n cas es , the MACE d evi c e

eliminates the transfer of packet data across the host

bus. In a receive late collision condition, the MACE chip

minimizes the amount transferred. These functions

preserve bus bandwidth utilization.

Manchester Encoder/Decoder (MENDEC)

The integrated Manchester Encoder/Decoder provides

the PLS (Physical Signaling) functions required for a

fully compliant IEEE 802.3 station. The MENDEC block

contains the AUI, DAI interfaces, and supports the

10BASE-T interface; all of which transfer data to appro-

priate tr ansceive r device s in Manche ster enc oded for-

mat. The M ENDEC prov ides the e ncodi ng functio n for

data to be transmitted on the network using the high

accur acy on-bo ar d os ci llator, driven by eith er the cry s-

tal oscillator or an external CMOS level compatible

clock generator. The MENDEC also provides the

decoding function from data received from the network.

The MENDEC contains a Power On Reset (POR)

circuit, which ensures that all analog portions of the

MACE devi ce are forced into their cor rect state during

power up, and prevents erroneous data transmission

and/or reception during this time.

External Crystal Characteristics

When usi ng a c rystal to drive the oscil lator, the follow-

ing cry stal spec ific ation shoul d be used to ensur e less

than ±0.5 ns jitter at DO±

Am79C940 39

* Requires trimming crystal spec; no trim is 50 ppm total

External Clo ck Driv e Charact er istics

When driving the oscillator from an external clock

source , XTAL 2 must be left f loa tin g (unc onn ec ted) . A n

external clock having the following characteristics must

be used to ensure less than ±0.5 ns jitter at DO±.

MENDEC Transmit Path

The transmit section encodes separate clock and NRZ

data input signals into a standard Manchester encoded

serial bit stream. The transmit outputs (DO±) are

designed to operate into terminated transmission lines.

When operating into a 78 ohm terminated transmission

line, signaling meets the required output levels and

skew for Cheape rnet, Ethernet and IEE E-80 2.3 .

Transmitter Timing and Operation

A 20 MHz fundamental mode crystal oscillator provides

the basic timing reference for the SIA portion of the

MACE device. It is divided by two, to create the internal

transmit clock reference. Both clocks are fed into the

SIA’s Manchester Encoder to generate the transitions

in the encoded data stream. The internal transmit clock

is used by the SIA to internally synchronize the Internal

Transmit Data (ITXD) from the controller and Internal

T ransm it Enabl e (ITENA ). The in ternal transmi t clock i s

also used as a stable bit rate clock by the receive

section of the SIA and controller.

The oscillator requires an external 0.005% crystal, or

an external 0.01% CMOS-level input as a reference.

The accuracy requirements if an external crystal is

used are tighter because allowance for the on-chip

oscillator must be made to deliver a final accuracy of

0.01%.

Transmission is enabled by the controller. As long as

the ITENA request rem ains acti ve, the ser ial output of

the cont roll er will be M anche ster enco ded an d app ear

at DO±. When the internal request is dropped by the

controlle r, the differential tr ansmit ou tputs go to one of

two idle states, dependent on TSEL in the Mode

Receive Path

The principal functions of the Receiver are to signal the

MACE device that there is information on the receive

pair, and separate the incoming Manchester encoded

data stream into clock and NRZ data.

The Receiver section (see Receiver Block Diagram)

consists of two parallel paths. The receive data path is

a zero threshold, wide bandwidth line receiver. The

carrier path is an offset threshold bandpass detecting

line receiver. Both receivers share common bias net-

works to allow operation over a wide input common

mode range.

Parameter Min Nom Max Units

1. Parallel Resonant Frequency 20 MHz

2. Resonant Frequency Error

(CL = 20 pF) –50 +50 PPM

3. Change in Resonant Frequency

With Respect To Temperature (CL = 20

pF)* –40 +40 PPM

4. Crystal Capacitance 20 pF

5. Motional Crystal Capacitance (C1) 0.022 pF

6. Seri es Resistance 35 ohm

7. Shunt Capacitance 7pF

Clock Frequency: 20 MHz ±0.01%

Rise/Fall Time (tR/tF): < 6 ns from 0.5 V

to VDD–0.5

XTAL1 HIGH/LOW Time

(tHIGH/tLOW): 40 – 60%

duty cycle

XTAL1 Falling Edge to

Falling Edge Jitter: < ±0.2 ns at

2.5 V input (VDD/2)

TSEL LOW: The idle state of DO± yields “zero”

differential to operate transformer-

coupled loads.

TSEL HIGH: In this idle state, DO+ is positive with

respect to DO– (logical\HIGH).

40 Am79C940

Input Signal Conditioning

Transient noise pulses at the input data stream

are rejected by the Noise Rejection Fil ter. Pulse widt h

rejection is proportional to transmit data rate. DC

inputs more negative than minus 100 mV are

also suppressed.

The Carrier Detection circuitry detects the presence of

an incoming data packet by discerning and rejecting

noise from expected Manchester data, and controls the

stop and start of the phase-lock loop during clock

acquisition. Clock acquisition requires a valid

Manchester bit pattern of 1010 to lock onto the

incoming message.

When input amplitude and pulse width conditions are

met at DI±, the internal enable signal from the SIA to

controller (RXCRS) is asse rted and a cloc k acquisition

cycle is initiated.

Clock Acquisition

When there is no activity at DI± (receiver is idle), the

receive oscillator is phase locked to TCK. The first neg-

ative clock transition (bit cell center of first valid

Manchester “0") after RXCRS is asserted in terrupts the

receive oscillator. The oscillator is then restarted at the

second Manchester “0" (bit time 4) and is phase locked

to it. As a result, the SIA acquires the clock from the

incoming Manchester bit pattern in 4 bit times with a

“1010" Manchester bit pattern.

SRDCLK and SRD are enabled 1/4 bit time after clock

acquisi tion in bit cell 5 if the ENP LSIO bit is set in th e

PLS configuration control register. SRD is at a HIGH

state when the receiver is idle (no SRDCLK). SRD

however, is undefined when clock is acquired and may

remain HIGH or change to LOW state whenever

SRDCLK is enabled. At 1/4 bi t time through bit cell 5,

the controller portion of the MACE device sees the first

SRDCLK transition. This also strobes in the incoming

fifth bit to the SIA as Manchester “1". SRD may make a

transition after the SRDCLK rising edge bit cell 5, but

its state is still undefined. The Manchester “1" at bit 5 is

clocked to SRD output at 1/4 bit time in bit cell 6.

PLL Tracking

After c lock ac qu is iti on, the ph ase - loc k ed cl oc k i s com-

pared to the incoming transition at the bit cell center

(BCC) and the resulting phase error is applied to a

correction circuit. This circuit ensures that the

phase-locked clock remains locked on the received

signal. Individua l bit cell phase corr ections of the Volt-

age Controlled Oscillator (VCO) are limited to 10%

of the phase differencebetween BCCand phase-

locked clock.

Carrier Tracking and End of Message

The carrier detection circuit monitors the DI± inputs

after RXCRS is asserted for an end of message.

RXCRS de-asserts 1 to 2 bit times after the last positive

transition on the incoming message. This initiates the

end of reception cycle. The time delay from the last ris-

ing edge of the message to RXCRS deassert allows

the last bit to be strobed by SRDCLK and transferred to

the controller section, but prevents any extra bit(s) at

the end of message. When IRENA de-asserts (see

Receive Timing-End of Reception (Last Bit = 0) and

Receive Timing-End of Reception (Last Bit = 1) wave-

form diagrams) an RXCRS hold off timer inhibits

RXCRS asserti on for at least 2 bit times.

Data Decoding

The data receiver is a comparator with clocked output

to minimize noise sensitivity to the DI± inputs. Input

error is less than ± 35 mV to minimize sensitivity to

Data

Receiver Manchester

Decoder

Noise

Reject

Filter

Carrier

Detect

Circuit

DI±SRD

SRDCLK

RXCRS

16235D-5

Receiver Block Diagram

Am79C940 41

input rise and fall time. SRDCLK strobes the data

receiver output at 1/4 bit time to determine the value of

the Manchester bit and clocks the data out on SRD on

the following SRDCLK. The data receiver also gener-

ates the s ignal u sed for phase detecto r co mparis on to

the internal SIA voltage controlled oscillator (VCO).

Differential Input Terminations

The differential input for the Manchester data (DI±) is

externally terminated by two 40.2 ohm ±1% resistors

and one option al common-mode bypass capacitor, as

shown in the Differential Input Termination diagram

below. The different ial input i mpedance , ZIDF, and th e

common-mode input impedance, ZICM, are specified

so that the E thern et spec ific ation for c able term ina tion

impedanc e i s me t us in g standard 1% res ist o r ter mi na-

tors. If SIP devices are used, 39 ohms is also a suitable

value. The CI± differential inputs are terminated in

exactly the same way as the DI± pair.

Collision Detection

A transceiver detects the collision condition on the net-

work and generates a differential signal at the CI±

inputs. This collision signal passes through an input

stage which detects signal levels and pulse duration.

When the signal is detected by the MENDEC, it sets

the CLSN line HIGH. The condition continues for ap-

proximately 1.5 bit times after the last LOW-to-HIGH

transition on CI±.

Jitter Tole rance Definition

The Receiv e Ti ming-Start of Rec eption Clo ck Acquis i-

tion wavefo rm diagram sh ows the internal ti ming rela-

tionships implemented for decoding Manchester data

in the SIA module. The SIA utilizes a clock capture

circuit to ali gn its in ter nal data strobe wi th an inc om in g

bit strea m. The cloc k acq uisi tion ci rcuitr y requi res fo ur

valid bit s with the values 1010. Clock is phase locked

to the negative transition at the bit cell center of the

second “0" in the pattern.

Since data is strobed at 1/4 bit time, Ma nchester tran-

sitions which shift from their nominal placement

through 1/4 bit time will result in improperly decoded

data. With this as the criteria for an error , a definition of

“Jitter Handling” is:

The peak deviation approaching or crossing 1/4 bit cell

position from nominal input transition, for which the SIA

section will prope rly dec od e data.

Atta chme nt Uni t Inte rf ac e (AU I)

The AUI is the PLS (Physical Signaling) to PMA (Phys-

ical Medium Attachment) interface which effectively

connects the DTE to the MAU. The differential interface

provided by the MACE device is fully compliant to

Section 7 of ISO 8802-3 (ANSI/IEEE 802.3).

After the MACE device initiates a transmission it will

expect to see data looped-back on the DI± pair (AUI

port selected). This will internally generate a carrier

sense, indicating that the integrity of the data path to

and from the MAU is in tact, and th at th e MAU is oper-

ating correctly. This carrier sense signal must be

asserted during the transmission when using the AUI

port (DO± transmitting). If carrier sense does not

become active in response to the data transmission, or

becomes inactive before the end of transmission, the

loss of carrier ( LCA R) er ro r bit wil l b e s et in t he Trans-

CURIO

DI+

40.2 Ω40.2 Ω

0.01µF

AUI Isolation

Transformer

16235D-6

Differential Input Te rmination

42 Am79C940

mit Frame Status (bit 7) after the packet has been

transmitted.

Digital Attachment Interface (DAI)

The Digital Attach ment Inte rface is a s impli fied el ectri-

cal attachment specification which allows MAUs which

do not req uire the DC isolation be tween the MA U and

DTE (e.g. devices compatible with the 10BASE-T Stan-

dard and 10BASE-FL Draft document) to be imple-

mented. All data transferred across the DAI port is

Manchester Encoded. Decoding and encoding is

performed by the MEN D EC.

The DAI port will accept receive data on the basis that

the RXC RS input is activ e, and will ta ke the data pre-

sented o n the R XDAT i nput as valid Manc hester data.

Transmit data is sent to the external transceiver by the

MACE devi ce asserti ng TXEN an d presenting compli-

mentary data on the TXDAT± pair. During idle, the

MACE device will assert the TXDAT+ line high, and the

TXDAT line low, while TXEN is maintained inactive

(high). The MACE device implements logical collision

detection and will use the simultaneous assertion of

TXEN and RXC RS to internally detec t a collision con-

dition, take appropriate internal action (such as abort

the current transmit or receive activity), and provide

external indication using the CLSN pin. Any external

transceiver utilized for the DAI interface must not loop

back the transmit data (presented by the MACE de-

vice) on the TXDAT± pins to the RXDAT pin. Neither

should the transceiver assert the RXCRS pin when

transmitting data to the network. Duplication of these

functions by the external transceiver (unless the MACE

device is in the external loop back test configuration)

will cause false collision indications to be detected.

In order to provide an integrity test of the connectivity

between the MACE device and the external transceiver

simila r to the S QE Tes t Mes sage pr ov ide d as a pa rt o f

the AUI functionality, the MACE device can be pro-

grammed to operate the DAI por t in an external loop-

back test. In this case, the external transceiver is

assumed to loopback the TXDAT± data stream to the

RXDAT pin, and assert RXCRS in response to the

TXEN request. When in the external loopback mode of

operation (programmed by LOOP [1-0] = 01), the

MACE device will not internally detect a collision condi-

tion. The external transceiver is assumed to take action

to ensure that this test will not disrupt the network. This

type of test is intended to be operated for a very limited

period (e.g. after power up), since the transceiver is as-

sumed to be located physically close to the MACE

device and with minimal risk of disconnection (e.g. con-

nected via printed circuit board traces).

Note that when the DAI port is selected, LCAR errors

will not occur, since the MACE device will internally loop

back the transmit data path to the receiver. This loop

back function must not be duplicated by a transceiver

which is external ly connecte d via the DAI po rt, since th is

will result in a condition where a collision is generated

during any transmit activity.

The transmit function of the DAI port is protected by a

jabber mechanism which will be invoked if the TXDA T±

and TXEN circuit is active for an excessive period (20 -

150 ms). This prevents a single node from disrupting

the network due to a stuck-on or faulty transmitter. If

this maximum tra ns mit time is exc ee ded , the DAI port

transmitter circuitry is disabled, the CLSN pin is

asserted, the Jabber bit (JAB in the Interrupt Register)

is set and the INTR pin will be asserted providing the

JABM bit (Interrupt Mask Register) is cleared. Once the

internal tran sm it data s tr eam from the ME NDEC stops

(TXEN deasserts), an unjab time of 250 ms-750 ms will

elapse before the MACE device deasserts the CLSN

indication and re-enables the transmit circuitry.

When jabb er is dete cted, the MACE de vice wil l assert

the CLSN pin, de-assert the TXEN pin (regardless of

internal MENDEC activity) and set the TXDAT+ and

TXDAT pins to their inactive state.

10BASE-T Interface

Twisted Pair Transmit Function

Data transmission over the 10BASE-T medium

requires use of the integrated 10BASE-T MAU, and

uses the differential driver circuitry in the TXD± and

TXP± pins. The driver circuitry provides the necessary

electrical driving capability and the pre-distortion con-

trol for transmitting signals over maximum length

Twisted Pair cable, as specified by the 10BASE-T

supplem ent to the IE EE 802.3 Sta ndard. The transmit

function for data o utput meets the propagation delays

and jitter specified by the standard. During normal

transmission, and providing that the 10BASE-T MAU is

not in a Link Fail or jabber state, the TXEN pin will

be driven HIGH and can be used indirectly to drive a

status LED.

Twisted Pair Receive Function

The receiver complies with the receiver specifications

of the IEEE 802.3 10BASE-T Standard, including noise

immunity and received signal rejection criteria (Smart

Squelch). Signals meeting this criteria appearing at the

RXD± differential input pair are routed to the internal

MENDEC. The receiver function meets the propaga-

tion delays and jitter requirements specified by the

10BASE-T Standard. The receiver squelch level drops

to half its threshold value after unsquelch to allow

reception of minimum amplitude signals and to mitigate

carrier fade in t he event of worst case signal atten ua-

tion and crosstalk noise conditions. During receive, the

RXCRS pin is driv en HIG H and ca n be us ed indi rectly

to drive a status LED.

Note that the 10BASE-T Standard defines the receive input

amplitude at the external Media Dependent Interface

Am79C940 43

(MDI). Filter and transformer loss are not specified. The

10BASE-T MAU receiver squelch levels are def ined to ac-

count for a 1dB insertion loss at 10 MHz, which is typical for

the type of receive filt er s/transf ormers recommend ed (s ee

the Appendix f or additiona l details).

Normal 10BASE-T compatible receive thresholds are

employed when the LRT bit is inactive (PHY Configu-

ration Control register). When the LRT bit is set, the

Low Receive Threshold option is invoked, and the sen-

sitivity of the 10BASE-T MAU receiver is increased.

This allows longer line lengths to be employed, ex-

ceeding the 100m target distance of normal 10BASE-T

(assuming typical 24 A WG cable). The additional cable

distance attributes directly to increased signal attenua-

tion and reduced signal amplitude at the 10BASE-T

MAU receiver. However, from a system perspective,

making the receiver more sensitive means that it is also

more susceptible to extraneous noise, primarily caused

by coupling from co-resident services (crosstalk). For

this reason, it is recommended that when using the

Low Recei ve Threshol d option t hat the serv ice shoul d

be installed on 4-pair cable only. Multi-pair cables

within the same outer sheath have lo wer crosst alk at-

tenuation, and may allow noise emitted from adjacen t

pairs to couple into the receive pair , and be of sufficient

amplitude to falsely unsquelch the 10BASE-T

MAU receiver.

Link Test Function

The link test function is implemented as specified by

10BASE-T standard. During periods of transmit pair

inactiv ity, Lin k Test pu ls es wi ll b e p er io dic al ly s entover

the twisted pair medium to constantly monitor

medium integrity.

When the l ink test f unction is e nabled, the absence of

Link Test pulses and receive data on the RXD± pair will

cause the 10BAS E-T MAU to go i nto a Lin k Fail state .

In the Link Fail state, data transmission, data reception,

data loopback and the collision detection functions are

disabled, and remain disabled until valid data or >5

consecutive link pulses appear on the RXD± pair. Dur-

ing Link Fail, the LNKST pin is inactive (externally

pulled HIG H), and the Link F ail bit (L NKFL in the PHY

Configuration Control register) will be set. When the

link i s identi fied as fu nctio nal, t he LNKST pi n is dr iven

LOW (ca pable of di rec tly dri ving a Link OK LED using

an integr ated 12 mA driv er) and the LNK FL bit will b e

cleared. In order to inter-operate with systems which

do not implement link test, this function can be disabled

by setting the the Disable Link Test bit (DLNKTST in the

PHY Configuration Control register). With link test

disabled, the data driver, receiver and loopback func-

tions as well as collision detection remain enabled

irrespec tive of the pres ence o r absenc e of dat a or li nk

pulses on the RXD± pair.

The MACE devices integrated 10BASE-T transceiver

will mimi c the performa nce of an exter nally conne cted

device (such as a 10BASE-T MAU connected using an

AUI). When the 10BASE-T transceiver is in link fail, the

receive da ta path of th e transceiver must be dis abled.

The MACE device will report a Loss of Carrier error

(LCAR bit in the Transmit Frame Status register) due to

the absence of the normal loopback path, for every

packet tran smitted du ring the link fail condition. In ad-

dition, a Collision Error (CERR bit in the Transmit

Frame Status register) will also be reported (see the

section on Signal Quality Error Test Function for

additional details).

If the AWAKE bit is set in the PHY Conf iguratio n Con-

trol register prior to the assertion of the hardware

SLEEP pin, the 10B ASE- T rece iver remain s opera ble,

and is able to detect and indicate (using the LNKST

output) the presence of legitimate Link Test pulses or

receive activity. The transmission of Link Test pulses is

suspended to reduce power consumption.

If the RWAKE bit is set in the PH Y Confi guration Con-

trol register prior to the assertion of the hardware

SLEEP pin, the 10BASE-T receiver and transmitter

functions remain active, the LNKST output is disabled,

and the EADI output pins are enabled. In addition the

AUI port (transmit and receive) remains active. Note

that since the MAC core will be in a sleep mode, no

transmit activity is possible, and the transmission of

Link Test pulses is also suspended to reduce

power consumption.

Polarity Detection and Reversal

The T wisted Pair receive function includes the ability to

invert the polarity of the signals appearing at the RXD±

pair if the polarity of the received signal is reversed

(such as in the case of a wiring erro r). This featur e al-

lows data packets received from a reverse wired RXD±

input pai r to be correc ted in the 10B ASE-T MAU p rior

to transfer to the MENDEC. The polarity detection func-

tion is activated following reset or Link Fail, and will

reverse the r eceiv e pol arity ba sed o n both t he p olarity

of any previous Link Test pulses and the polarity of

subsequent packets with a valid End Transmit

Del imiter (E T D) .

When in the Link Fail state, the internal 10BASE-T

receiver will recognize Lin k Test pulses of either posi-

tive or nega tive po larity. Exi t from the Lin k Fail sta te is

made due to the reception of five to six consecutive

Link Test pulses of identical polarity. On entry to the

Link Pass state, the polarity of the last five Link Test

pulses is used to determine the initial receive polarity

configuration and the receiver is reconfigured to subse-

quently recognize only Link Test pulses of the previ-

ously recognized polarity. This link pulse algorithm is

employed only until ETD polarity determination is made

as described later inthis section.

44 Am79C940

Positive Link Test pulses are defined as received signal

with a positive amplitud e greate r than 5 20 mV (LRT =

LOW) with a pulse width of 60 ns-200 ns. This positive

excursion may be followed by a negative excursion.

This definition is consistent with the expected received

signal at a correctly wired receiver, when a Link Test

pulse which fits the template of Figure 14-12 in the

10BASE -T Standard is gener ated at a tr ansmit ter and

passed through 100 m of twisted pair cable.

Negative Link Test p ulses ar e d efi ned as rec eiv ed si g-

nals with a negative amplitude greater than 520 mV

(LRT = LOW) with a puls e width of 60 ns -200 ns. This

negative excursion may be followed by a positive ex-

cursion. T his definiti on is consist ent with the expecte d

received signal at a reverse wired receiver, when a

Link Test p uls e whi ch fi ts th e t emp lat e o f F i gure 14- 1 2

in the 10BASE–T Standa rd is gen er ate d at a tr ansmi t-

ter and passed through 100 m of twisted pair cable.

The polarity detection/correction algorithm will remain

armed unti l two consecut ive pac kets with v alid ETD of

identical polarity are detected. When armed, the

receiver is capable of changing the initial or previous

polarity configuration based on the most recent ETD

polarity.

On receipt of the first packet with valid ETD following

reset or Link Fail, the MACE device will utilize the

inferred polarity information to configure its RXD±

input, regardless of its previous state. On receipt of a

second packet with a valid ETD with correct polarity,

the detection/correction algorithm will lock-in the

received polarity. If the second (or subsequent) packet

is not detected as confirming the previous polarity

decision, the most recently detected ETD polarity will

be used as the default. Note that packets with invalid

ETD have no effect on updating the previous polarity

decision. Once two consecutive packets with valid ETD

have bee n recei ved, th e MACE devic e will disa ble the

detection/correction algorithm until either a Link Fail

condition occurs or a hardware or software reset

occurs.

During polarity reversal, the RXPOL pin should be

externally pulled HIGH and the Reversed Polarity bit

(REVPOL in the PHY Configuration Control register)

will be set. During normal polarity conditions, the

RXPOL pin is driven LOW (capable of directly driving a

Polarity OK LED using an integrated 12 mA driver) and

the REVPOL bit will be cleared.

If desired, the polarity correction function can be dis-

abled by setting the Disable Auto Polarity Correction bit

(DAPC bit in the PHY Configuration Control register).

However , the polarity detection portion of the algorithm

continues to operate independently, and the RXPOL

pin and the REVPOL bits will reflect the polarity state of

the receiver.

Twisted Pair Interface Status

Three outputs (TXEN, RXCRS and CLSN) indicate

whether th e MACE devic e is trans mitting (ME NDECto

Twist ed Pai r ), rece iv in g ( Twisted Pa ir to ME NDE C), or

in a collision state with both functions active

simultaneously.

The MACE d evice will power up in the Link Fail state .

The normal algorithm will apply to allow i t to enter th e

Link Pass state. On power up, the TXEN, RXCRS and

CLSN) pins will be in a high impedance state until they

are enabled by setting the Enable PLS I/O bit

(ENPLSIO in the PLS Configuration Control register)

and the 10BASE-T port enters the Link Pass state.

In the Link Pass state, transmit or receive activity which

passes the pulse width/amplitud e requirements of the

DO± or RXD± inputs, w ill be indic ated by the TXEN or

RXCRS pin respectively going active. TXEN, RXCRS

and CLSN are all asserted during a collision.

In the Link Fail state, TXEN, RXCRS and CLSN

are inactive.

In jabber detect mode, the MACE device will activate

the CLSN pin, disable TXEN (regar dless of Manche s-

ter data output from the MENDEC), and allow the

RXCRS pin to indicate the current state of the RXD±

pair. If there is no receive activity on RXD±, only CLSN

will be ac t ive dur i ng ja bbe r det ec t . I f ther e is RXD ± ac-

tivity, both CLSN and RXCRS will be active.

If the SLEEP pin is asserted (regardless of the pro-

gramming of the AWAKE or RWAKE bits in the PHY

Configuration Control register), the TXEN, RXCRS and

CLSN outputs will be placed in a high impedance state.

Collision Detect Function

Simultaneous activity (presence of valid data signals)

from both the internal MENDEC transmit function (indi-

cated externally by TXEN active) and the twisted pair

RXD± pins constitutes a collision, thereby causing an

external indication on the CLSN pin, and an internal

indication which is returned to the MAC core. The

TXEN, RXCR S and CLSN pins are driven hig h during

collision.

Signal Quality Error (SQE) Test (Heartbeat)

Function

The SQE Test message (a 10 MHz burst normally

returned on the A UI CI± pai r at the end of eve r y tr an s-

mission) is intended to be a self-test indication to the

DTE that the MAU collision circuitry is functional and

the AUI cable/connection is intact. This has minimal

relevance when the 10BASE-T MAU is embedded in

the LAN controller. A Collision Error (CERR bit in the In-

terrupt Register) will be reported only when the

10BASE-T port is in the link fail state, since the collision

circuit of the MAU will be disabled, causing the

absence of th e SQ E Test m essa ge. I n G PS I mo de th e

Am79C940 45

external encoder/decoder is responsible for asserting

the CLSN pin after each transmission. In DAI mode,

SEQ Test has no relevance.

Jabber Function

The Jabber function inhibits the twisted pair transmit

function of the MACE device if the TXD±/TXP± circuits

are active for an excessive period (20-150 ms). This

prevents any one node from disrupting the network due

to a stuck-on or faulty transmitter. If this maximum

transmit time is exceeded, the data path through the

10BASE-T transmitter circuitry is disabled (although

Link Test pulses will continue to be sent), the CLSN pin

is asser ted, the J abber bi t (JAB in th e Int errupt Re gis-

ter) is set and the INTR pin will be asserted providing

the JABM bit (Interrupt Mask Register) is cl eared.

Once the i nternal transmi t data st ream from the ME N-

DEC stops (TXEN deasserts), an unjab time of

250-750 ms will elapse before the MACE device

deasserts the CLSN indication and re-enables the

transmit circuitry.

When jabb er is dete cted, the MA CE device will assert

the CLSN pin, de-assert the TXEN pin (regardless of

internal MENDEC activity), and allow the RXCRS pin to

indicate the current state of the RXD± pair . If there is no

receive activity on RXD±, only CLSN will be active dur-

ing jabber detect. If the re is RXD± activity, bot h CLSN

and RXCRS will be active.

External Address Detection Interface

(EADI)

This inte rface is provided to all ow external perfect ad-

dress filtering. This feature is typically utilized for termi-

nal server , bridge and/or router type products. The use

of external logic is required, to capture the serial bit

stream fr om the MACE d evice, and comp are this with

a table of stored addresses or identifiers. See the EADI

port diagram in the Systems Applications section,

Network Interfaces sub-section, for details.

The EADI interface operates directly from the NRZ

decoded dat a and clock recov ered by the Manch ester

decoder. This allows the e xternal address detection to

be performed in parallel with frame reception and

address comparison in the MAC Station Address

Detection (SAD) block.

SRDCLK is provided to allow clocking of the receive bit

stream from the MACE device, into the external

address detection logic. Once a re ceived pack et com-

mences and data and clock are available from the

decoder , the EADI interface logic will monitor the alter-

nating (1,0) prea mble patter n until the two ones of the

St art F r am e De l i m it e r (1,0,1,0,1,0,1,1) are d e t ec te d , at

which point the SF/BD output will be driven high.

After SF/BD is asserted the serial data from SRD

should be de-serialized and sent to a Content

Addressable Memory (CAM) or other address

detection device.

To allow simple ser ial to parallel co nversion, SF/BD is

provided as a strobe and/or marker to indicate the

delineat ion of bytes, s ub seq uen t to the S F D. Th is f ea-

ture provides a mechanism to allow not only capture

and/or decoding of the physical or logical (group)

address, but also facilitates the capture of header

information to determine protocol and or inter-network-

ing info rmati on. T he E AM/R pin is driven by the exter-

nal address comparison logic, to either reject or accept

the packet. Two alternative modes are permitted, al-

lowing the external logic to either accept the packet

based on address match, or reject the packet if there is

no match. The two alternate methods are programmed

using the Matc h/Reject ( M/R) bit in the Receiv e Fr am e

Control register.

If the M/R bit is set, the pin is configured as EAM

(External Address Match). The MACE device can be

configured with Physical, Logical or Broadcast Address

comparison operational. If an internal address match is

detected, the packet will be accepted regardless of the

condition of EAM. Additional addresses can be located

in the external address detection logic. If a match is

detected, EAM must go active within 600 ns of the last

bit in the destination address field (end of byte 6) being

presented on the SRD output, to guarantee frame

reception. In addition, EAM must go inactive after a

match has been detected on a previous packet, before

the next match can take place on any subsequent

packet. EAM must be asserted for a minimum pulse

width of 200 ns.

If the M/R bit is clear (default state after either the

RESET pin or SWRST bit have been activated), the pin

is configured as EAR (External Address Reject). The

MACE device can be configured with Physical, Logical

or Broadcast Address comparison operational. If an

internal address match is detected, the packet will be

accepted regardless of the condition of EAR. Incoming

packets which do not pass the internal address com-

parison will continue to be received by the MACE

device. EAR must be externally presented to the

MACE chip prior to the first assertion of RDTREQ, to

guarantee rejection of unwanted packets. This allows

approximately 58 byte times after the last destination

address bit is available to generate the EAR signal, as-

suming the MACE device is not configured to accept

runt packets. EAR will be ignored by the MACE device

from 64 byte times after the SFD, and the packet will be

accepted if EAR has not been asserted before this

time. If the MACE device is configured to accept runt

packets, the EAR signal must be generated prior to the

receive m essage comp letion, which could b e as short

as 12 byte times (assuming six bytes for source

address, two bytes for length, no data, four bytes for

FCS) after the last bit of the destination address is

46 Am79C940

available. EAR must have a pulse width of at least

200 ns.

Note that setting the PROM bit (MAC Configuration

Control) will cause all receive packets to be received,

regardless of the programming of M/R or the state of

the EAM/R input. The following table summarizes the

operation of the EADI features.

Internal/External Address Recognition Capabilities

General Purpose Serial Interface (GPSI)

The GPSI port provides the signals necessary to

present an interface consistent with the non encoded

data fun ctions ob served to/from a LAN co ntroller s uch

as the Am7990 Local Area Network Controller for

Ethernet ( LAN CE) . The actu al GP SI pi ns ar e f unc tio n-

ally identical to some of the pins from the DAI and the

EADI ports, the GPSI replicates this type of interface.

The GPSI allows use of an external Manchester

encoder/decoder, such as the Am7992B Serial Inter-

face Adapter (SIA). In addition, it allows the MACE

device to be used as a MAC sublayer engine in a

repeater bas ed on the Am 79C9 80 Inte gr ate d Mul tip or t

Repeater (IMR) . Si mp le c onn ect ion to the IMR E xpan-

sion Bus al low s th e MA C to v ie w al l pa ck et d ata p ass -

ing through a number of interconnected IMRs, allowing

statistics and network management information to

be collect ed.

The GPSI functional pins are duplicated as follows:

Pin Configuration for GPSI Function

IEEE 1149.1 Test Access Port Interface

An IEEE 1149.1 compatible boundary scan Test

Access Port is provided for board level continuity test

and dia gnostics. All digital input, output and input/out-

put and input/output pins are tested. Analog pins,

including the AUI differential driver (DO±) and receiv-

ers DI±, CI±), and the crystal input (XTAL1/XTAL2)

pins, are not tested.

The following is a brief summary of the IEEE 1149.1

compatible test functions implemented in the MACE

device. For additional details, consult the IEEE Stan-

dard Test Access Port and Boundary-Scan Architec-

ture document (IEEE Std 1149.1–1990).

The boundary scan test circuit requires four pins (TCK,

TMS, TD I and TDO ) , define d as the Test Ac cess P ort

(TAP). It includes a finite state machine (FSM), an

instruction register, a data register array and a power

on reset circuit. Internal pull-up resistors are provided

for the TCK, TDI and TMS pins.

The TAP e ngine is a 16 state FS M, driven b y the Test

Clock (TCK ) an d the Test Mode Select ( TM S) pin s. An

independent power on reset circuit is provided to

ensure t he FSM is in the T EST_LOGIC_ RESET state

at power up.

In addition to the minimum IEEE 1149.1 instruction

requirements (EXTEST, SAMPLE and BYPASS), three

additional instructions (IDCODE, TRI_ST and SET_I/

O) are prov ided to further ea se board lev el testing . All

unused instruction codes are reserved.

IEEE 1149.1 Supported Instruction Summary

PROM M/R EAM/R Required Timing Received Messages

1 X X No timing requirements All Received Frames

0 0 H No timing requirements All Received Frames

00 ↓Low for 200 ns within 512-bits after SFD Physical/Logical/Broadcast Matches

0 1 H No timing requir ements Physical/Logical/Broadcast Matches

01 ↓Low for 200 ns within 8-bits after DA field All Received Frames

Function Type LANCE

Pin MACE

Receive Data I RX RXDAT

Receive Clock I RCLK SRDCL K

Receive Carrier Sense I RENA RXCRS

Collision I CLSN CLSN

Transmit Data O TX TXDAT+

Transmit Clock I TCK STDCLK

Transmit Enable O TENA TXEN

Inst

ame Description Selected

Data Reg Reg

Mode Inst

Code

EXTEST External Test BSR Test 0000

IDCode ID Code Inspection ID Reg Normal 0001

Sample Sample Boundary BSR Normal 0010

TRI_ST Force Tristate Bypass Normal 0011

SET_I/0 Control

Boundar yTo I/0 Bypass Test 0100

Bypass Bypass Scan Bypass Normal 1111

Am79C940 47

After hardwar e or so ftware r es et, the IDCODE in str uc-

tion is always invoked. The decoding logic provides

signals to control the data flow in the DATA registers

accord in g to the current instru cti on.

Each Boundary Scan Register (BSR) cell also has two

stages. A flip-f lop and a latch are used in th e SERIAL

SHIFT STAGE and the PARALLEL OUTPUT STAGE

respectively.

There are fou r poss ible operation al modes in the BS R

cell:

1. CAPTURE

2. SHIFT

3. UPDATE

4. SYSTEM FUNCTION

Other Data Registers

■BYPASS REG (1 bit)

■Device Identification Register (32 bits)

Bits 31-28:Version (4 bits)

Bits 27-12:Part number (16 bits) is 9400H

Bits 11-1:Manufacturer ID (11 bits).

The manufacturer ID code for AMD is

00000000001 in accordance with

JEDEC Publication 106-A.

Bit 0:Always a logic 1

SLAVE ACCESS OPERATION

Internal register accesses are based on a 2 or 3 SCLK

cycle dur ation, depende nt on the state of the TC i nput

pin. TC must be externally pulled low to force the

MACE device to perform a 3-cycle access. TC is inter-

nally pulled high if left unconnected, to configure the

2-cycle access by default.

All re gister ac cesses are byte wide with the exc eption

of the data path to and from the internal FIFOs.

Data exchanges to/from register locations will take

place over the appropriate half of the data bus to suit

the ho st me mory o rgani zation (as prog ramme d by th e

BSWP bit in the BIU Configuration Control register).

The BE0, BE1 and EOF s ignals are provided to allow

control of the data flow to and from the FIFOs. Byte

read operat ions from the Receive FIFO caus e data to

be duplicated on both the upper and lower bytes of the

data bus. Byte write operations to the Transmit FIFO

must use the BE0 and BE1 i nputs to d efine the acti ve

data byte to the MACE device.

Read Access

Details of the read access timing are located in the AC

Waveforms section, Host System Interface, figures:

Two-Cycle Receive FIFO/Register Read Timing and

Three-Cycle Receive FIFO/Register Read Timing.

TC can be dynamically changed on a cycle by cycle

basis to program the slave cycle execution for two (TC

= HIGH) or three (TC = LOW) SCLK cycles. TC must

be stabl e by the fal ling edg e of SCL K ( EDSE L = Hi gh)

in S0 at the start of a cycle, and should only be

changed in S0 in a multiple cycle burst.

A read cycle is initiated when either CS or FD S is sam-

pled low on the falling edge of SCLK at S0. FDS and

CS must be asserted exclusively. If they are active

simultaneously when sampled, the MACE device will

not execute any read or write cycle.

If CS is low, a Register Address read will take place.

The state of the ADD4–0 will be used to commence

decoding of the appropriate internal register/FIFO.

If FDS is low, a FIFO Direct read will take place from

the RCVFIFO. The state of the ADD4-0 bus is irrele-

vant for the FIFO Direct mode.

With either the CS or FDS input active, the state of the

ADD0-4 (for Register Address reads), R/W (high to

indicate a read cycle), BE0 and BE1 will also be latched

on the falling (EDSEL = HIGH) edge of SCLK at S0.

From the falling edge of SCLK in S1 (EDSEL = HIGH),

the MACE device will drive data on DBUS15-0 and

activate the DTV output (providing the read cycle com-

pleted successfully). If the cycle read the last byte/word

of data for a specific frame from the RCVFIFO, the

MACE device will also assert the EOF signal. DBUS15-

0, DTV and EOF will be g uaranteed valid and can be

sampled on the falling (EDSEL = HIGH) edge of SCLK

at S2.

If the Register Address mode is bein g used to access

the RCVFIFO, once EOF is asserted during the last

byte/wor d read for the frame, the Receive Frame S ta-

tus can be r ead in one of two way s. The Register Ad-

dress mode can be continued, by placing the

appropr iate a ddress (00110b) on the a ddress bus an d

executing four r ead cy cles ( CS ac tive) on the Re ceive

Frame Status location. In this case, additional Register

Address read requests from the RCVFIFO will be ig-

nored, and no DTV returne d, until all four byte s of the

Receive Fra me Status regist er have been read. A lter-

natively, a FIFO Direct read can be performed, which

will effectively route the Receive Frame Status through

the RCVFIFO location. This mechanism is explained in

more detail below.

If the FIFO Direct mode is used, the Receive Frame

Status can be read directly from the RCVFIFO by con-

tinuing to execute read cycles (by asserting FDS low

and R/W high) after EOF is asserted indicating the last

byte/word read for the frame. Each of the four bytes of

Receive Frame Status will appear on both halves of the

data bu s, as if the actua l Recei ve Frame Stat us regi s-

ter were being accessed. Alternatively, the status can

be read as normal using the Register Address mode by

48 Am79C940

placing the appropriate address (00110b) on the

address bus and executing four read cycles (CS

active).

Either the FIFO Direct or Register Address modes can

be interl eaved at any time to read the Re ceive Fram e

Status, alt hough this is considered unlikely due to the

additional overhead it requires. In either case, no addi-

tional data will be read from the RCVFIFO until the

Receive Frame Status has been read, as four bytes

appended to the end of the packet when using the

FIFO Direct mode, or as four bytes from the Receive

Frame Status location when using the Register

Address mode.

EOF will only be driven by the MACE device when

reading received packet data from the RCVFIFO. At all

other tim es , i nc lud in g reading th e Re ceive Fr am e S ta-

tus using the FIFO Direc t mode, the MA CE devi ce will

place EOF in a high impedance state.

RDTREQ should be sampled on the falling edge of

SCLK. The assertion of RDTREQ is programmed by

RCVFW, and the de-assertion is modified dependent

on the state of the RCVBRST bit (both in the FIFO Con-

figuration Control register). See the section Receive

FIFO Read for additional details.

Write Access

Details of the write access timing are located in the AC

Waveforms section, Host System Interface, figures:

Two-Cycle Transmit FIFO/Register Write Timing and

Three-Cycle Transmit FIFO/Register Write Timing.

Write cycles are executed in a similar manner as the

read cycle previously described, but with the R/W input

low, and the host responsible to provide the data with

sufficient set up to the falling edge of SCLK after S2.

After a FIFO write, TDTREQ should be sam ple d on or

after the falling (EDSEL = HIGH) edge of SCLK after

S3 of the FIFO write. The state of TDTREQ at this time

will reflect the state of the XMTFIFO.

After going active (low), TDTREQ will remain low for

two or more XMTFIFO writes.

The minimum high (inactive) time of TDTREQ is one

SCLK cycle. When EOF is written to the Transmit

FIFO, TDTREQ will go i nactive after o ne SCLK cycle,

for a minimum of one SCLK cycle.

Initialization

After pow er -up, RE SE T shou ld be ass erted for a m in i-

mum of 15 SCLK cycles to set the MACE device into a

defined state. This will set all MACE registers to their

default va lues. The rec eive and transm it functions wi ll

be turned off. A typical sequence to initialize the MACE

device could look like this:

■Write the BIU Configurat ion Cont rol (BIUCC) re gis-

ter to change the Byte Swap mode to big endian or

to change the Transmit Start Point.

■Write the FIFO Configuration Control (FIFOCC)

enable the FIFO Burst Mode.

■Write the Interrupt Mask Register (IMR) to disable

unwanted interrupt sources.

■Write the PLS Configuration Control (PLSCC)

GPSI interface is used, the register must be written

twice. The first write access should only set

PORTSEL [1–0] = 11. The second access must

write again PORTSEL[1–0] = 1 1 and additionally set

ENPLSIO = 1. This sequence is required to avoid

contention on the clock, dat a and/or carrier indica-

tion signals.

■Write the PHY Configuration Control (PHYCC) reg-

ister to configure any non-default mode if the

10BASE-T interface is used.

■Progr am the Logical Ad dress Filter (LADRF) regis-

ter or the Physical Address Register (PADR). The

Internal Address Configuration (IAC) register must

be accessed first. Set the Address Change

(ADDRCHG) bit to request access to the internal

address RAM. Poll the bit until it is cleared by the

MACE dev ice indicatin g that access to th e internal

address RAM is permitted. In the case of an

address RAM access after hardware or software

reset (ENRCV has not been set), the MACE device

will return ADDRCHG = 0 right away. Set the

LOGADDR bit in the IAC register to select writing to

the Logical Address Filter register. Set the PHY-

ADDR b it in the IA C r eg ister t o sel ec t wri tin g to th e

Physi cal A ddr es s Regi s ter. Either b it c an be set to-

gether with writing the ADDRCHG bit. Initializing the

Logical Address Filter register requires 8 write

cycles. Initializing the Physical Address Register

requires 6 write cycles.

■Write the User Test Register (UTR) to set the MACE

device into any of the user diagnostic modes such

as loopback.

■Write the MAC Configuration Control (MACCC) reg-

ister as the last step in the initialization sequence to

enable the receiver and transmitter. Note that the

system must guarantee a delay of 1 ms after

power-up before enabling the receiver and transmit-

ter to allow the MACE phase lock loop to stabilize.

■The Transmit Frame Control (XMTFC) and the

Receive Frame Control (RCVFC) registers can be

programmed on a per packet basis.

Am79C940 49

Reinitialization

The SWRST bit in the BIU Configuration Control

(BIUCC) reg ist er c an b e s et to rese t the MACE devi c e

into a defined state for reinitialization. The same

seque nce desc ribed in the initi alizati on sec tion can b e

used. The 1 ms delay for the MACE phase lock loop

stabilization need not to be observed as it only applies

to a power-up situation.

TRANSMIT OPERATION

The transmit operation and features of the MACE

device are controlled by programmable options. These

options are programmed through the BIU, FIFO and

MAC Configuration Control registers.

Paramet ers c ontrol le d by the MA C C onfigur at ion Con-

trol register are generally programmed only once,

during initialization, and are therefore static during the

normal operation of the MACE device (see the Media

Acces s Con tro l se ct ion fo r a detail ed de scr ip tio n) . Th e

features controlled by the FIFO Configuration Control

be re-p rogr amm ed if th e M ACE de vi ce is no t trans mi t-

ting.

Transmit FIFO Write

The Transmit FIFO is accessed by performing a host

generated write sequence on the MACE device. See

the Slave Access Operation-Write Access section and

the AC W aveforms section, Host System Interface, fig-

ures: Two-Cycle Transmit FIFO/Register Write Timing

and Three-Cycle Transmit FIFO/Register Write Timing

for details of the write access timin g.

There are two fundamentally different access methods

to write data into the FIFO. Using the Register Address

mode, the FIFO can be addressed using the ADD0-4

lines, (address 00001b), initiating the cycle with the CS

and R/W (low) signals. The FIFO Direct mode allows

write access to the Transmit FIFO without use of the

address lines, and using onl y the FDS and R/W lines.

If the MACE device detects both signals active, it will

not execute a write cycle. The write cycle timing for the

FDS and CS should be mutually exclusive.

The data stream to the Transmit FIFO is writ ten using

multiple byte and/or wor d writes. CS or F DS does not

have to be returned inactive to commence execution of

the next write cycle. If CS/FDS is detected low at the

falling edge of S0, a write cycle will commence. Note

that EOF must be asserted by the host/controller

during the last byte/word transfer.

Transmit Function Programming

The Transmit Frame Control register allows program-

ming of dynamic transmit attributes. Automatic transmit

features such as retry on collision, FCS generation/

transmission and pad field insertion can all be

programmed, to provide flexibility in the

(re-)transmission of message s.

The disable retry on collision (DRTRY bit) and auto-

matic pad field insertion (APAD XMT bit) features

should not be changed while data remains in the T rans-

mit FIFO. Writing to either the DRTRY or APAD XMT

bits in this case may have unpredictable results. These

bits are not in ternally latched or prote cted. When writ-

ing to th e Transmit Fr am e Co ntrol r egister the DRTRY

and APAD XMT bits should be programmed consis-

tently. Once the Transmit FIFO is empty, DRTRY and

APAD XMT can be reprog ra mme d.

This can be ach iev ed with no ris k of transmi t data lo ss

or corru pti on b y cl earin g E N XM T afte r the p ac ket dat a

for the current frame has been completely loaded. The

transmis sion will c omplete nor mally a nd the activa tion

of the INTR pin can be used to determine if the transmit

frame has completed ( XMTINT wi ll be set in the Inter-

rupt Register). Once the Transmit Frame Status has

been read, AP AD XMT and/or DRTRY can be changed

and ENXMT set to restart the transmit process with the

new parameters.

APAD XM T is sampl ed if there ar e less than 60 bytes

in the trans mit pack et when the la st bit of the last byt e

is transmitted. If AP AD XMT is set, a pad field of pattern

00h is add ed un til the min im um fr am e siz e of 6 4 by tes

(excluding preamble and SFD) is achieved. If APAD

XMT is clear, no pad field inse rtion will take place and

runt packet transmission is possible. When AP AD XMT

is enabled, the DXMTFCS feature is over-ridden and

the four byte FCS will be added to the transmitted

packet unconditionally.

The disable FCS generation/transmission feature can

be programmed dynamically on a packet by packet

basis. The current state of the DXMTFCS bit is

internally latched on the last write to the Transmit FIFO,

when the EOF indication is asserted by the

host/controller.

The programming of static transmit attributes are dis-

tributed between the BIU, FIFO and MAC Configura-

tion Control registers.

The point at which transmission begins in relation to

the number of bytes of a frame in the FIFO is controlled

by the XMTSP bits in the BIU Configuration Control

XMTSP can be set to ensure that the Transmit FIFO

does not underflow before more data is written to the

FIFO. When the entire frame is in the FIFO, or the FIFO

becomes full before the threshold is reached, transmis-

sion of preamble will commence regardless of the

value in XMTSP. The default value of XMTSP is 64

bytes after reset.

The point at which TDTREQ is asserted in relation to

the number of empty bytes present in the Transmit

50 Am79C940

FIFO is controlled by the XMTFW bits in the FIFO Con-

figuration Control register. TDTREQ will be asserted

when one of the following conditions is true:

■The num ber o f byte s free in the Transmit FIFO rel-

ative to the current Saved Read Pointer value is

greater than or equal to the threshold set by the

XMTFW (16, 32 or 64 bytes). The Saved Read

Pointer is the first byte of the current transmit frame,

either in progress or awaiting channel availability.

■The num ber o f byte s free in the Transmit FIFO rel-

ative to the current Read Pointer value is greater

than or equal to the threshold set by the XMTFW

(16, 32 or 64 bytes). The Read Pointer becomes

available only after a minimum of 64 byte frame

length has been transmitted on the network (eight

bytes of preamble plus 56 bytes of data), and points

to the current byte of the frame being transmitted.

Depending on the bu s latenc y of the system, XMTFW

can b e set to en sure that t he Transmit FIFO does not

underflow before more data is written into the FIFO.

When the entire frame is in the FIFO, TDTREQ will

remain asserted if sufficient bytes remain empty. The

default v alue of XMTF W is 64 by tes after har dware or

software reset. Note that if the XMTFW is set below the

64 byte limit, the transmit latency for the host to service

the MACE device is effectively increased, since

TDTREQ will occur earlier in the transmit sequence

and more bytes will be present in the Transmit FIFO

when th e TDTR EQ is de-asserted.

The transmit operation of the MACE device can be

halted at any time by c learin g the ENXMT bit (bi t 1) in

the MAC Confi guration Contro l register. Note that any

complete transmit frame that is in the Transmit FIFO

and is currently in progress will complete, prior to the

transmit function halting. Transmit frames in the FIFO

which ha ve n ot c om me nce d will not be s tarted . Trans-

mit frames which have commenced but which have not

been fully transferred into the Transmit FIFO will be

aborted, in one of two ways. If less than 544 bits

(68 bytes) have been transmitted onto the network, the

transmission will be terminated immediately, generat-

ing a runt packet which can be deleted at the receiving

station. If greate r than 544 bi ts have been tr ans mitted,

the mess ages will have t he current CRC in verted and

appended at the next byte boundary, to guarante e an

error is detected at the receiving station. This feature

ensures th at packet s wi ll no t be gene ra ted with pot en-

tial undetected data corruption. An explanation of the

544 bit derivation appears in the “Automatic Pad

Generation” section.

Automatic Pad Generation

Transmit frames can be automatically padded to ex-

tend them t o 64 data bytes (excluding preamble) per-

mitting the minimum frame size of 64 bytes (512 bits)

for 802. 3/Ethernet to b e guarantee d, with no softw are

intervention from the host system.

APAD XMT = 1 enables the automatic padding feature.

The pad is placed between the LLC Data field and FCS

field in the 802.3 frame. The FCS is always added if

APAD XMT = 1, regardl ess of the stat e of DXMTFCS .

The transmit frame will be padded by bytes with the

value of 00h. The default value of APAD XMT will

enable auto pad generation after hardware or software

reset.

It is the responsibility of upper layer software to cor-

rectly define the actual length field contained in the

message to correspond to the total number of LLC

Data bytes encapsulate d in the packet (le ngth field as

define d in the IE EE 8 02.3 s tandar d). The length valu e

contained in the message is not used by the MACE

device to compute the actual number of pad bytes to be

inserted. The MACE chip will append pad bytes depen-

dent on the actual number of bits transmitted onto the

network. Once the last data byte of the frame has com-

pleted, prior to appending the FCS, the MACE device

will che ck to ensure t hat 544 bits ha ve been transm it-

ted. If not, pad bytes are added to extend the frame

size to this value, and the FCS is then added.

The 544 bit count is derived from the following:

Preamble

1010....1010 SFD

10101011 Dest

Addr Srce

Addr Length LLC

Data Pad FCS

Bits 8

Bits 6

Bytes 6

Bytes 2

Bytes 4

Bytes

46—1500

Bytes

IEEE 802.3 Format Data Frame 16235D-7

Am79C940 51

Minimum frame size (excluding preamble,

including FCS) 64 bytes 512 bits

Preamble/SFD size 8 bytes 64 bits

FCS size 4 bytes 32bits

To be classed as a minimum size frame at the receiver ,

the transmitted frame must contain:

Preamble + (Min Frame Size + FCS) bits

At the point that FCS is to be appended, the transmitted

frame should contain:

Preamble + (Min Frame Size –FCS) bits

64 + (512 –32) bits

A minimum length transmit frame from the MACE

device will therefore be 576 bits, after the FCS is

appended.

The Ethernet specification makes no use of the LLC

pad field, and assumes that minimum length messages

will be at least 64 bytes in length.

Tr ansmit FCS Generation

Automatic generation and transmission of FCS for a

transmit frame depends on the value of DXMTFCS

(Disable T ransmit FCS) when the EOF is asserted indi-

cating the la st b yte/wor d o f dat a for th e trans mi t fram e

is being written to the FIFO. The action of writing the

last data byte/word of the transmit frame, latches the

current contents of the Transmit Frame Control regis-

ter, and therefore determines the programming of

DXMTFC S for the tran smit fram e. When DXM TFCS =

0 the transmitte r will generate and append the FCS to

the transmitted frame. If the automatic padding feature

is invoked (APAD XMT in T ransmit Frame Control), the

FCS will be appended regardless of the state of DXMT-

FCS. Note that the calculated FCS is transmitted most

signifi ca nt bit first. The default value of DX MT FC S is 0

after hardware or software reset.

Transmit Status Information

Although multiple transmit frames can be queued in the

T r ansm it FIFO , th e MACE dev ic e wi ll n ot pe rmit lo ss of

Transmit Frame Status information. The Transmit

Frame Status and Transmit Retry Count can only be

buffered internally for a maximum of two frames. The

MACE device will therefore not commence a third

transmit frame, until the status from the first frame is

read. Once the Transmit Retry Count and Transmit

Frame Status for the first transmit packet is read, the

MACE device will auton omously begin the next trans-

mit frame, provided that a transmit frame is pending,

the XMTSP threshold has been exceeded (or the

XMT FIFO is full), the network medium is free, and the

IPG time has elapsed.

Indication of valid Transmit Frame Status can be

obtain ed by servic ing the har dware interrup t and test-

ing the XMTINT bit in the Interrupt Register, or by poll-

ing the XMTSV bit in the Poll register if a continuous

polling mechanism is required. If the Transmit Retry

Count data is required (for loading, diagnostic, or man-

agement information), XMTRC must be read prior to

XMTFS. Reading the XMTFS register when the

XMTSV bit is set will clear both the XMTRC and

XMTFS values.

Transmit Exception Conditions

Exception conditions for frame transmission fall into

two distinct categories; those which are the result of

normal network operation and those which occur due

to abnormal network and/or host related events.

Normal events which may occur and which are handled

autonomously by the MACE device are:

(a) Collisions within the slot time with automatic retry

(b) Deletion of packets due to excessive transmis-

sion attempts.

(a) T he MACE devic e will ensur e that co llisio ns whi ch

occur within 512 bit times from the start of transmission

(including preamble) will be automatically retried with

no host intervention. The Transmit FIFO ensures this

by guaranteeing that data containe d within the Trans-

Preamble

1010....1010 SYNCH

11 Dest

Addr Srce

Addr Type Data FCS

Bits 2

Bits 6

Bytes 6

Bytes 2

Bytes 4

Bytes

46—1500

Bytes

16235D-8

Ethernet Format Data Frame

52 Am79C940

mit FIFO will not be overwritten until at least 64 bytes

(512 bits) of data have been successfully transmitted

onto the network. This criteria will be met, regardless of

whether the transmit frame was the first (or only) frame

in the Transmit FIFO, or if the transmit frame was

queued pending completion of the preceding frame.

(b) If 16 total attempts (initial attempt plus 15 retries)

have been made to transmit the frame, the MACE

device will abandon the transmit process for the partic-

ular frame, de-assert the TDTREQ pin, report a Retry

Error (RTRY) in the T ransmit Frame Status, and set the

XMTINT bit in the Interrupt Register , causing activation

of the external INTR pin providing the interrupt is

unmasked.

Once the XMTINT condition has been externally recog-

nized, the Transmit Frame Counter (XMTFC) can be

read to determine whether the tail end of the frame that

suffers the RTRY error is still in the host memory (i.e .,

when XMTFC = 0). This XMTFC read should be

requested before the Transmit Frame Status read

since reading the XMTFS would cause the XMTFC to

decreme nt. If the tail end of the frame is indeed still in

the host memory, the host is responsible for ensuring

that the tail end of the frame does not get written int o

the FIFO and does not get transmitted as a whole

frame. It is recommended that the host clear the tail

end o f th e fram e from the host m emory befo re re quest -

ing the XMTFS read so that after the XMTFS read,

when MACE devi ce re-ass erts TDT REQ, the tail end of

the frame does not get written into the FIFO. The

T ransmit Frame Status read will indicate that the RTRY

error occurred. The read operation on the Transmit

Frame Status will update the FIFO read and write

pointers. If n o End-of-Frame write (EOF pin ass ertio n)

had occ urred du ring the FIFO wr ite s equence, t he en-

tire transmit path will be reset (which will update the

Transmit FIFO watermark with the current XMTFW

value in the FIFO Configuration Control register). If a

whole fr ame d oes res ide in the FIFO, the r ead p ointer

will be moved to the start of the next frame or free loca-

tion in the FIFO, and the write pointer will be unaf-

fected. TDTREQ will not be re-asserted until the

Transmit Frame Status has been read.

After a RTRY error, all further pa cket tran smission will

be suspended until the Transmit Frame Status is read,

regardless of whether additional packet data exists in

the FIFO to be tr ansm itted. Recei ve FIFO r ead oper a-

tions are not impaired.

Packets experiencing 16 unsuccessful attempt to

transmit wi ll not be re-tr ied. Recovery from t his condi-

tion must be performed by upper layer software.

Abnormal network conditions include:

(a) Loss of carrier.

(b) Late collision.

These should not occur on a correctly configured 802.3

network, but will be reported if the network has been

incorrectly configured or a fault condition exists.

(a) A loss of carrier condition will be reported if the

MACE device cannot observe receive activity while it is

transmitting. After the MACE device initiates a trans-

mission it will expect to see data looped-back on the

receive input path. This will internally generate a carrier

sense, indicating that the integrity of the data path to

and from the external MAU is intact, and that the MAU

is operating correctly.

When the AUI port is selected, if carrier sense does not

become active in response to the data transmission, or

becomes inactive before the end of transmission, the

loss of carrier ( LCA R) er ro r bit wil l b e s et in t he Trans-

mit Frame Status (bit 7) after the packet has been

transmitted. The packet will not be re-tried on the basis

of an LCAR error.

When the 10BASE–T port is selected, LCAR will be

reported for every packet transmitted during the Link

fail condition.

When the GPSI port is selected, LCAR will be reported

if the RXCRS i nput pin fails to bec ome ac tive during a

transmission, or once active, goes inactive before the

end of transmission.

When the DAI port is selected, LCAR errors will not

occur, since the MA CE de vice will internal ly l oop ba ck

the transmit data path to the receiver. The loop back

feature must not be performed by the external trans-

ceiver when the DAI port is used.

During internal loopback, LCAR will not be set, since

the MACE device has direct control of the transmit and

receive path integrity. When in external loopback,

LCAR will operate normally according to the specific

port which has been sel ected.

(b) A late collision will be reported if a collision condition

exists or commences 64 byte times (512 bit times) after

the trans mit pr oc ess was in iti ate d (fir s t bi t o f pream bl e

commenced). The MACE device will abandon the

transmit process for the particular frame, complete

transmission of the jam sequence (32-bit all zeroes

pattern), de-assert the TDTREQ pin, report the Late

Collision (LCOL) and Transmit Status V alid (XMTSV) in

the Transm it Frame Sta tus, and se t the XMTIN T bit in

the Interrupt Register, causing activation of the external

INTR pin providing the interrupt is unmasked.

Once the XMTINT condition has been externally recog-

nized, the Transmit Frame Counter (XMTFC) can be

read to determine whether the tail end of the frame that

suffers the LCOL error is sti ll in the host m emory (i.e .,

when XMTFC = 0). This XMTFC read should be

requested before the Transmit Frame Status read

since rea ding the XM TFS would ca use the XMTFC t o

decrem ent. If the ta il en d of t he frame is indee d sti ll in

Am79C940 53

the host memory, the host is responsible for ensuring

that the tail end of the frame does not get written int o

the FIFO and does not get transmitted as a whole

frame. It is recommended that the host clear the tail

end o f th e fram e from the host m emory befo re re quest -

ing the XMTFS read so that after the XMTFS

read,when the MACE device r e-asserts TDTREQ, th e

tail end of the frame does not get written into the FIFO.

The Transmit Frame Status read will indicate that the

LCOL error occurred. The read operation on the T rans-

mit Frame Status will update the FIFO read an d write

pointers. If n o End-of-Frame write (EOF pin ass ertio n)

had occ urred du ring the FIFO wr ite s equence, t he en-

tire transmit path will be reset (which will update the

Transmit FIFO watermark with the current XMTFW

value in the FIFO Configuration Control register). If a

whole frame resides in the FIFO, the read pointer will

be moved to the start of the next frame or free location

in the FIFO, and the write pointer will be unaffected.

TDTREQ will not be re-asserted until the Transmit

Frame Status has been read.

After an LCOL error , all further packet transmission will

be suspended until the Transmit Frame Status is read,

regardless of whether additional packet data exists in

the FIFO to be transmitted. Receive FIFO operations

are unaffected.

Packets experiencing a late collision will not be re-tried.

Recovery from this condition must be performed by

upper layer software.

pletion of a transmitted message, the AUI CI± pair is

asserted by some transceivers as a self-test. When the

AUI port has been selected, the integral Manchester

Encoder/Decoder will expect the SQE Test Message

(nominal 10 MHz sequence) to be returned via the CI±

pair, with in a 40 netw ork bit time period afte r DI± goes

inactive. If the CI± input is not asserted within the 40

network bit time period following the completion of

transmission, then the MACE device will set the CERR

bit (bit 5) in the Interrupt Register . The INTR pin will be

activated if the corresponding mask bit CERRM = 0.

When th e GPS I po r t is se le cte d, th e MA CE dev ic e wi ll

expect t he CLSN inp ut pin to be a sserted 40 bit times

after the tr ansmi ss io n h as c omp lete d (after TXE N o ut-

put pin has gone inactive). When the DAI port has

been selected, the CERR bit will not be reported. A

transceiver connected via the DAI port is not expected

to support the SQE Test Message feature.

Host related transmit exception conditions include:

(a) Overflow caused by excessive writes to the

T ransmit FIFO (DTV will not be issu ed if the T rans-

mit FIFO is full).

(b) Underflow caused by lack of host writes to the

Transmit FIFO.

(a) The host may continue to write to the Transmit FIFO

after the TDTREQ has been de-asserted, and can

safely do s o on the b asis of kn owledge of the number

of free bytes remaining (set by XMTFW in the FIFO

Configuration Control register). If however the host

system conti nues to write data to the point that no ad-

ditional FIFO space exists, the MACE device will not

return the DTV signal and hence will effectively not

acknowledge acceptance of the data. It is the host’s

responsibility to ensure that the data is re-presented at

a future ti me when space e xists in the Transmit FIFO,

and to track the actual data written into the FIFO.

(b) If the host fails to respond to the TDTREQ from the

MACE device before the Transmit FIFO is emptied, a

FIFO underrun will occur. The MACE device will in this

case ter minate the network transmission in an orderly

sequenc e. If less than 512 b its have b een transm itted

onto the network the transmission will be terminated

immediately, generating a runt packet. If greater than

512 bits have been transmitted, the message will have

the current CRC inverted and appended at the next

byte boun dary, to guarantee an F CS error is d etected

at the receiving station. The MACE device will report

this conditi on to the host by de- asse rt ing the TDTR EQ

pin, setting the UFLO and XMTSV bits (in the Transmit

Frame Status) and the XMTINT bit (in the Interrupt

responding XMTINTM bit (in the Interrupt Mask

Regis ter) is cleared.

Once the XMTINT condition has been externally recog-

nized, the Transmit Frame Counter (XMTFC) can be

read to determine whether the tail end of the frame that

suffers the UFLO erro r is still in the host mem ory (i.e.,

when XM TFC = 0). In the case of FIFO und errun, th is

will definitely be the case and the host is responsible for

ensuring that the tail end of the frame does not get writ-

ten into the FIFO and does not get transmitted as a

whole frame. It is recommended that the host clear the

tail end of the frame from the host memory before

requesting the XMTFS read so that after the XMTFS

read, when the MACE device re-asserts TDTREQ, the

tail end of the frame does not get written into the FIFO.

The Transmit Frame Status read will indicate that the

UFLO error occurred. The read operation on the T rans-

mit Frame Status will update the FIFO read and write

pointers and the entire transmit path will be reset

(which will update the Transmit FIFO watermark with

the current XMTFW value in the FIFO Configuration

Control register). TDTREQ will not be re-asserted until

the Transmit Frame Status has been read.

Frame Stat us for up to two packets . If the host fails to

read the Transmit Frame Status and both internal

entries become occupied, the MACE device will not

commence any subsequent transmit frames to prevent

overwriting of the internally stored values. This will

54 Am79C940

occur regardless of the number of bytes wri tten to th e

Transmit FIFO.

RECEIVE OPERATION

The receive operation and features of the MACE de-

vice are controlled by programmable options. These

options are programmed through the BIU, FIFO and

MAC Configuration Control registers.

Paramet ers c ontrol le d by the MA C C onfigur at ion Con-

trol re gister are g enerall y p rogr am med onl y onc e, dur -

ing initialization, and are therefore static during the

normal operation of the MACE device (see the Media

Acces s Con tro l se ct ion fo r a detail ed de scr ip tio n) . Th e

features controlled by the FIFO Configuration Control

programmed without performing a reset on the part.

The host is responsible for ensuring that no data is

present in the Receive FIFO when re-programming the

receive attributes.

Receive FIFO Read

The Receive FIFO is accessed by performing a host

generated read sequence on the MACE device. See

the Slave Access Operation-Read Access section and

the AC W aveforms section, Host System Interface, fig-

ures: “2 Cycle Receive FIFO/Register Read Timing”

and “3 Cycle Receive FIFO/Register Read Timing” for

details of the read access timing.

Note that EOF will be asserted by the MACE device

during the last data byte/word transfer.

Receive Function Programming

The Receive Frame Control register allows program-

ming of the automatic pad field stripping feature and

the configuration of the Match/Reject (M/R) pin.

ASTRP RCV and M/R must be static when the receive

function i s enable d (ENRC V = 1). T he recei ver shoul d

be disabled before (re-) programming these options.

The EADI port can be used to permit reception of

frames to commence whilst external address decoding

takes place. The M/R bit defines the function of the

EAM/R pin, and hence whether frames will be

accepted or rejected by the external address

comparison logic.

The programming of additional receive attributes are

distributed between the FIFO and MAC Configuration

Control registers, and the User Test Register.

All receive frames can be accepted by setting the

PROM bit (bit 7) in the MAC Configuration Control reg-

ister . When PROM is set, the MACE device will attempt

to receive all messages, subject to minimum frame

enforcement. Setting PROM will override the use of the

EADI port to force the rejection of unwanted messages.

See the sec tions External Address Detection Interface

for more details.

The point at which RDTREQ is asserted in relation to

the number of bytes o f a frame that ar e present in th e

Receive FIFO (RCVFIFO) is co nt roll ed by the RCVFW

bits in the FIFO Configuration Control register, or the

LLRCV bit in the Receive Frame Control register.

RDTREQ will be asserted when one of the following

conditions is true:

(i) There are at least 64 bytes in the RCVFIFO.

(ii) The received packet has passed the 64 byte mini-

mum criteria, and the number of bytes in the

RCVFIFO is greater than or equal to the threshold

set by the RCVFW (16 or 32 bytes).

(iii) A rece ive p acke t has com ple ted, an d part or al l of

it is present in the RCVFIFO.

(iv) The LLRCV bit has been set and greater than

12-bytes of at least 8 bytes have been received.

Note that if the RCV FW is set below the 64-byte li mit,

the M ACE devic e will stil l requi re 64-b ytes of da ta to be

received before th e initial assertio n of RDTREQ . Sub-

sequently, RDTREQ will be asserted at any time the

RCVFW threshold is exceeded. The only times that the

RDTREQ will be asserted when there are not at least

an initial 64-bytes of data in the RCVFIFO are:

(i) When the ASTR P RCV bit has been set in the Re-

ceive Frame Control register, and the pad is auto-

matically stripped from a minimum length packet.

(ii) When the RPA bit has been set in the User Test

been received.

(iii)When the LLRCV bit has been set in the Receive

Frame Control register, and at le ast 12-byte s (after

SFD) has been received.

No preamble/SFD bytes are loaded into the Receive

FIFO. All refer ences to bytes past through the receive

FIFO are received after the preamble/SFD sequence.

Depending on the bus latency of the system, RCVFW

can be set to ensure that the RCVFIFO does not over-

flow before more data is read. When the entire frame is

in the RCVFIFO, RDTREQ will be asserted regardless

of the value in RCVFW . The default value of RCVFW is

64-bytes after hardware or software reset.

The receive operation of the MACE device can be

halted at any time by clearing the ENRCV bit in the

MAC Configuration Control register. Note that any

receive frame currently in progress will be accepted

normally, and the MACE device will disable the receive

process once the message has completed. The Missed

Packet Count (MPC) will be incremented for

Am79C940 55

subsequent packets that would have normally been

passed to the host, and are now ignored due to the

disabled state of the receiver.

Note that clearing the ENRCV bit disables the asser-

tion of RDTREQ. If ENRCV is cleared during receive

activity and remains cleared for a long time and if the

tail end of the receive frame currently in progress is

longer than the amount of space available in the

Receive FIFO, Re ceiv e FIFO o verflow will o ccur. How-

ever, even with RDTREQ deasserted, if there is valid

data in the Receiv e FIFO to be read, succe ssful slave

reads to the Receive FIFO can be executed (indicated

by valid DTV). It is the host’s responsibility to avoid the

overflow situation.

Automatic Pad Stripping

During reception of a frame, the pad field can be

stripped automatically. ASTRP RCV = 1 enables the

automatic pad stripping feature. The pad field will be

stripped before the frame is passed to the FIFO, thus

preserving FIFO space for additional frames. The FCS

field will also be stripped, since it is computed at the

transmitting station based on the data and pad field

charac ters, and will be invali d for a receive frame tha t

has the pad characters stripped.

The numb er of bytes to be stripped is c alculated from

the embedded length field (as defined in the IEEE

802.3 definition) contained in the packet. The length

indicates the actual number of LLC data bytes con-

tained in the message. Any received frame which con-

tains a length field less than 46 bytes will have the pad

field stripped. Receive frames which have a length field

of 46 bytes or greater will be passed to the host

unmodified.

Since any valid Ethernet T ype field value will always be

greater than a normal 802.3 Length field, the MACE

device will not attempt to strip valid Ethernet frames.

Note that for some network protocols, the value passed

in the Ethernet Type and/or 802.3 Length field is not

compliant with either standard and may cause

problems.

The diagram below shows t he byte/bit ordering of the

received length field for an 802.3 compatible frame

format.

Receiv e FC S Checking

Reception and checking of the received FCS is per-

formed auto mat ic all y by the MACE devi ce . Note tha t if

the Automatic Pad Stripping feature is enabled,

the received FCS will be verified against the value

computed for the incoming bit stream including pad

characters, but it will not be passed through the Re-

ceive FIFO to the host. If an FCS error is detected, this

will be reported by the FCS bit (bit 4) in the Receive

Frame Status.

Receive St atus Informa t ion

The EOF indication signals that the last byte/word of

data has been passed from the FIFO for the specific

frame. Th is will be accom panied by a RCVINT indica-

tion in the the Interrupt Register signaling that the

Receive Frame Status has been updated, and must be

Preamble

1010....1010 SYNCH

10101011 Dest.

ADDR. SRCE.

ADDR. Length LLC

DATA Pad FCS

Bits 8

Bits 6

Bytes 6

Bytes 2

Bytes

46–1500

Bytes 4

Bytes

Most

Significant

Byte

Least

Significant

Byte

Bit

0Bit

Start of Packet

at T ime= 0

Increasing T ime

Bit

7Bit

45–0

Bytes

1–1500

Bytes

16235D-9

802.3 Packet and Length Field Transmission Order

56 Am79C940

read. The Receive Frame Status is a single location

which must be read four times to allow the four bytes of

status information associated with each frame to be

read. Further data read operations from the Receive

FIFO using the Register Address mode, will be ignored

by the MACE dev ice (indicated by the MACE ch ip not

returnin g DTV) until all four bytes of the Receive Frame

Status have been read. Alternatively, the FIFO Direct

access mode may be used to read the Receive Frame

Status through the Receive FIFO. In either case, the

4-byte total must be read before additional receive data

can be read from the Receive FIFO. However, the

RDTREQ indic ation will conti nue to reflect the state of

the Receive FIFO as normal, regardless of whether the

Receive F rame S tatu s ha s bee n r ea d. DTV wil l not be

returned when a read operation is performed on the

Receive Frame Status location and no valid status is

present or ready.

Note that the Receive Frame Status can be read using

either the Register Address or FIFO Direct modes. For

additional details, see the section Receive FIFO Read.

Receive Exception Conditions

Exception conditions for frame reception fall into two

distinct categories; those which are the result of normal

network operation, and those which occur due to

abnormal network and/or host related events.

Normal events which may occur and which are handled

autonom ously by the MACE device ar e basic ally colli-

sions within the slot time and automatic runt packet

deletion. The MACE device will ensure that any receive

packet which experiences a collision within 512 bit

times fr om the start of rec eption (exc luding prea mble)

will be automatically deleted from the Receive FIFO

with no host intervention (the state of the RPA bit in the

User Test Register; or the RCVFW bits in the FIFO

Configuration Control register have no effect on this).

This criteria will be met, regardless of whether the

receive frame was the first (or only) frame in the

Receive FIFO, or if the receive frame was queued

behind a previously received message.

Abnormal network conditions include:

■FCS er rors

■Framing err ors

■Dribbling bits

■Late collision

These should not occur on a correctly configured 802.3

network, but may b e reported if the network has been

incorrectly configured or a fault condition exists.

Host related receive exception conditions include:

(a) Underflow caused by excessive reads from the

Receive FIFO (DTV will not be issued if the

Receive FIFO is empty)

(b) Overflow caused by lack of host reads from the

Receive FIFO

the Receive FIFO and/or the Receive Frame

Status

(a) Successive read operations from the Receive FIFO

after the final byte of data/status has been read, will

cause the DTV pin to remain de-asserted during the

read operation, indicating that no valid data is present.

There will be no adverse effect on the Receive FIFO.

(b) Data present in the Receive FIFO from packets

which completed before the overflow condition

occurred, can be read out by accessing the Receive

FIFO normally. Once this data (and the associated

Receive Frame Status) has been read, the EOF indica-

tion will be asserted by the MACE device during the

first read operation takes place from the Receive FIFO,

for the packet which suffered the overflow . If there were

no other packets in the FIFO when the overflow

occurred, the EOF will be asserted on the first read

from the FIFO. In either case, the EOF indication will be

accompanied by assertion of the INTR pin, providing

that the RCVINTM bit in the Inter rup t Mask Regi ster is

not set. If the Register Address mode is being used, the

host is required to access the Receive Frame Status

location using four separate read cycles. Further

access to the Receive FIFO will be ignored by the

MACE device until all four bytes of the Receive Frame

Status have been read. DTV will not be returned if a

Receive FIFO read is attempted. If the FIFO Direct

mode is being used, the host can read the Receive

Frame Status through the Receive FIFO, but the host

must be aware that the subsequent four cycles will

yield the receive status bytes, and not data from the

same or a ne w packet. On ly the OF LO bit will be vali d

in the Receive Frame Status, other error/status and the

RCVCNT fields are invalid.

While th e Receiv e FIFO is in the over flow condi tion, it

is deaf to additional receive data on the network. How-

ever, the MACE device internal address detect logic

continues to operate and counts the number of packets

that would have been passed to the host under normal

(non overflow) conditions. The Missed Packet Count

(MPC) is an 8-bit count (in reg ister 24) that maintains

the num ber of packets w hich pass th e address matc h

criteria, and complete without collision. The MPC

counter will wrap around whe n the maximum count of

255 is reached, setting the MPCO (Missed Packet

Count Overflow) bit in the Interrupt Register, and

asserting the INTR pin providing that MPCOM (Missed

Packet Count Overflow Mask) in the Interrupt Mask

will be unmasked) after hardware or software reset.

However, until the first time that the receiver is enabled,

MPC will not increment, hence no interrupt will occur

due to missed packets after a reset.

Am79C940 57

will eventually cause an overflow condition. The FIFO

will maintain any previously completed packet(s), which

can be read by the host at its convenience. However,

packet data on the network will no longer be received,

regardless of destination address, until the overflow is

cleared by reading the remaining Receive FIFO data

and Receive Status. The MACE device will increment

the M issed Pack et C ount (MP C) regist er to indicat e that

a packet which would have been normally passed to the

host, was dropped due to the error condition.

Note: The moment a packet overflow is detected or

read, an EOF with INT is generated. On status read

(OFLOW), the FIFO pointers are reset to the first

loca tion . Thi s esse ntially flu she s the FI FO .

LOOPBACK OPERATION

During loopback, the FCS logic can be allocated to the

receiv er by setting RCV FCSE = 1 in Us er Test Re gis-

ter. This permits both the transmit and receive FCS op-

erations to be verified during the loopback process.

The state of RCVFCSE is only valid during loopback

opera tion.

If RCVFCSE = 0, the MACE device will calculate and

append the FCS to the transmitted message. The

receive message passed to the host will therefore con-

tain an additional four bytes of FCS. The Receive

Frame Status will indicate the result of the loopback

operation and the RCVCNT.

If RCVFCSE = 1, the last four bytes of the transmit

message must contain the FCS computed for the

transmit data preceding it. The MACE device will trans-

mit the data without addition of an FCS field, and the

FCS will be calculated and verified at the receiver.

The loopback facilities of the MACE device allow full

operatio n to be verified wi thout dis turbanc e to the net-

work. Loo pback oper ation is also a ffected by the s tate

of the Loopb ack Co ntrol bits (LOO P [0–1 ]) in the User

Test Register. This affects whether the internal MEN-

DEC is considered part of the internal or external

loop-back path.

When in the loopback mode(s), the multicast address

detection feature of the MACE device, programmed by

the cont ents of the Logic al Address Fil ter (LADR [63–

0]) can only be tested when RCV FCSE = 1, al loca ting

the CRC generator to the receiver. All other features

operate i dentic ally in l oopback as in no rmal oper ation ,

such as automatic transmit padding and receivepad

stripping.

USER ACCESSIBLE REGISTERS

The following registers are provided for operation of the

MACE device. All registers are 8-bits wide unless

otherwise stated. Note that all reserved register bits

should be written as zero.

Receive FIFO (RCVFIFO) (REG ADDR 0)

This register provides a 16-bit data path from the

Receive FIFO. Reading this register will read one word/

byte from the Receive FIFO. The RCVFIFO should

only be read when Receive Data Transfer Request

(RDTREQ) is asserted. If the RCVFIFO location is read

before 64-bytes are available in the RCVFIFO (or

12-byte s in the cas e that LLR CV is se t in the Re ceive

Frame Control register), DTV will not be returned.

Once the 64-byte threshold has been achieved and

RDTREQ is asserted, the de-assertion of RDTREQ

does not prev ent additiona l data from being read from

the RCVFIFO, but indicates the number of additional

bytes which are present, bef ore the RCV FIFO is emp-

tied, and subsequent reads will not return DTV (see

the FIFO Sub-System section for additional details).

Write operations to this register will be ignored and

DTV will not be returned.

Byte transfers from the RCVFIFO are supported, and

will be fu lly aligned to th e target memor y architecture ,

defined by the BSWP bit in the BIU Configuration Con-

tro l regist er. The By te Enab le input s (BE1-0) wi ll defi ne

which half of the data bus should be used for the trans-

fer. The external host/controller will be informed that

the last byte/word of data in a receive frame is being

read from the RCVFIFO, when the MACE device as-

serts the E O F signal.

Transmit FIFO (XMTFIFO) (REG ADDR 1)

This register provides a 16-bit data path to the Transmit

FIFO. Byte/word data written to this register will be

placed in the Transmit FIFO. The XMTFIFO can be

written at any time the Transmit Data T ransfer Request

(TDTREQ) is asserted. The de-assertion of TDTREQ

does not prevent data being written to the XMTFIFO,

but indicates the number of additional write cycles

which can take place, before the XMTFIFO is filled, and

subsequent writes will not return DTV (see the FIFO

Sub-Sy st em sec tio n for addi tional deta il s). Rea d oper -

ations to this register will be ignored and DTV will not

be returned.

Byte transfers to the XMTFIFO are supported, and

accept data from the source memory architecture to

ensure the correct byte ordering for transmission,

defined by the BSWP bit in the MAC Configuration

Control register. The Byte Enable inputs (BE1-0) will

define which half of the data bus should be used for the

transfer . The use of byte transfers have implications on

the latency time provided by the XMTFIFO (see the

FIFO Sub-System section for additional details). The

external host/controller must indicate the last byte/word

RCVFIFO [15–0]

XMTFIFO [15–0]

58 Am79C940

of data in a transmit frame is being written to the

XMTFIFO, by asserting the EOF signal.

Transmit Frame Control (XMTFC) (REG ADDR 2)

The Transmit Frame Control register is latched inter-

nally on the last write to the T ransmit FIFO for each in-

dividual packet, when EOF is asserted. This permits

automatic transmit padding and FCS generation on a

packet-by-packet basis.

Bit Name Description

Bit 7 DRTRY Disable Retry. When DRTRY is

set, the MACE device will pro-

vide a single transmission at-

tempt for the packet, all further

retrie s will be suspended. In the

case of a collision during the at-

tempt, a Retry Error (RTRY) will

be report ed in the Transm it Sta-

tus. With DRTRY cleared, the

MACE device will attempt up to

15 retries (16 attempts total) be-

fore indicating a Retry Error.

DRTRY is cleared by activation

of the RESET pin or SWRST bit.

DRTRY is sampled during the

transmit process when a

collision occurs. DRTRY should

not be changed whilst data

remains in the Transmit FIFO

since this may cause an unpre-

dic table ret ry r espon se to a col li -

sion. Once the Transmit FIFO is

empty, DRTRY can be repro-

grammed.

Bit 6-4 RES Reserved. Read as zeroes.

Always write as zeroes.

Bit 3 DXMTFCS Disable Transmit FCS. When

DXMTFCS = 0 the transmitter

will generate and append an

FCS to the transmitted frame.

When DXMTFCS = 1, no FCS

will be appended to the transmit-

ted frame, providing that APAD

XMT is als o clea r. If APAD XMT

is set, the calculated FCS will be

appended to the transmitted

message regar dl es s o f the s tat e

of DXMTFCS. The value of

DXMTFCS for each frame is

programmed when EOF is as-

serted to transfer the last byte/

word for the transmit packet to

the FIFO. DXMTFCS is cleared

by activation of the RESET pin

or SWRST bit. DXMTFCS is

sampled only when EOF is

asserted during a Transmit FIFO

write.

Bit Name Description

Bit 2-1 RES Reserved. Read as zeroes.

Always write as zeroes.

Bit 0 APAD XMT Auto Pad Transmit. APAD XMT

enables the automatic padding

feature. Transmit frames will be

padded to extend them to 64

bytes including FCS. The FCS is

calculated for the entire frame

including pad, and appended af-

ter the pad field. APAD XMT will

override the p ro gramm in g of th e

DXMTFCS bit. APAD XMT is set

by activation of the RESET pin

or SWRST bit. APAD XMT is

sampled only when EOF is as-

serted during a Transmit FIFO

write.

Transmit Frame Status (XMTFS) (REG ADDR 3)

The Transmit Frame Status is valid when the XMTSV

bit is se t. The re gister is read only, and is cleare d when

XMTSV is set and a re ad operati on is perform ed. The

XMTINT bit in the Interrupt Register will be set when

any bit is set in this register.

Note that if XMTSV is not set, the values in this register

can change at any time, including during a read opera-

tion. This register should be read after the Transmit

Retry Count (XMTRC). See the description of the

Transmit Retry Count (XMTRC) for additional details.

Bit Name Description

Bit 7 XMTSV Transmit Status Valid. Transmit

Status Valid indicates that this

status is valid for the last frame

transmitted. The value of

XMTSV will no t cha nge dur ing a

read operation.

Bit 6 UFLO Underflow. Indicates that the

Transmit FIFO emptied before

the end of frame was reached.

The transmitted frame is truncat-

ed at that point. If UFLO is set,

TDTREQ will be de-asserted,

and will not be re-asserted until

the XMTFS has been read.

Bit 5 LCOL Late Collision. Indicates that a

collision occurred after the slot

time of the channel elapsed. If

LCOL is set, TDTREQ will be

de-asserted, and will not be

DRTRY RES RES DXMTFCS RES RES APAD XMT

XMTSV UFLO LCOL MORE ONE DEFER LCAR RTRY

Am79C940 59

re-asserted until the XMTFS has

been read. The MACE device

does not retry after a late

collision.

Bit 4 MORE More. Indicates that more than

one retry was needed to transmit

the frame. ONE, MORE and

RTRY are mutually exclusive.

Bit 3 ONE One. Indicates that exactly one

retry was needed to transmit the

frame. ONE, MORE and RTRY

are mutually exclusive.

Bit 2 DEFER Defer. Indicates that MACE

device had to defer transmission

of the frame. This condition

results if the channel is busy

when the MACE device is ready

to transmit.

Bit 1 LCAR Loss of Carrier. Indicates that

the carrier became false during

a transmission. The MACE

device does not retr y upon Lo ss

of Carrier. LCAR will not be set

when the DAI port is selected,

when the 10BASE-T port is se-

lecte d and in the link pas s st ate ,

or during any internal loopback

mode . W he n t he 10 B ASE - T po r t

is selected and in the link fail

state, LCAR will will b e re ported

for any transmission attempt.

Bit 0 RTRY Retry Error. Indicates that all

attempts to transmit the frame

were unsuccessful, and that fur-

ther attempts have been abort-

ed. If Disable Retry (DRTRY in

the Transmit Frame Control reg-

ister) is cleared, RTRY will be

set when a total of 16 unsuc-

cessful attempts were made to

transmit the frame. If DRTRY is

set, RTRY indicates that the first

and only attempt to t ransmit th e

frame was unsuccessful. ONE,

MORE and RTRY are mutually

exclusive. If RTRY is set,

TDTREQ will be de-asserted,

and will not be re-asserted until

the XMTFS has been read.

Transmit Retry Count (XMTRC) (REG ADDR 4)

The Transmit Retry Count should be read only in

response to a hardware interrupt request (INTR

asserted) when XMTINT is set in the Interrupt Register ,

or after XM TSV is set in the Poll R egiste r.The reg ister

should be read before the Transmit Frame Status

XMTSV set will cause the XMTRC value to be reset.

This register is read only.

Bit Name Description

Bit 3-0 EXD EF Excess ive Defer . The EXDEF bit

will be set if a transmit frame

waited for an excessive period

for transmission. An excessive

defer time is defined in accor-

dance with the following (from

page 34, section 5.2.4.1 of IEEE

Std 802.3h-1990 Layer Manage-

ment):maxDeferTime = {2 x

(max frame size x 8)} bits wh er e

maxFrameSize = 1518 bytes

(from page 68, section 4.4.2.1 of

ANSI/IEEE Std 802.3-1990).

So, the maxDeferTime = 24288

bits = 214+ 212 + 211+ 210 + 29

+27 +26 +25

Bit 6-4 RES Reserved. Read as zeroes.

Always write as zeroes.

Bit 3-0 XMTRCTransmit Retry Count.

Contains

[3-0] the count of th e number of r etry

attempts made by the MACE

device to transmit the current

transmit packet. The value of the

counter will be zero if the first

transmission attempt was suc-

cessfu l, and a max imum of 15 i f

all retry attempts were utilized.

RTRY will be set in Transmit

Frame Status if all 16 attempts

were unsuc ce ss ful.

Receive Frame Control (RCVFC) (REG ADDR 5)

Bit Name Description

Bit 7-4 RES Reserved. Read as zeroes.

Always write as zeroes.

Bit 3 LLRCV Low Latency Receive. A

programmable option to allow

access to the Receive FIFO

before the 64-byte threshold has

been reached. When set, data

can be read from the RCVFIFO

once a low threshold (12-bytes

after SFD plus synchronization)

has been exceeded, causing

RDTREQ to be asserted.

RDTREQ will remain asserted

as long as one read cycle can be

performed on the RCVFIFO

(identical to the burst mode).

Indication of a valid read cycle

from the RCVFIFO will return

DTV asserted. Reading the

RCVFIFO before data is avail-

able, or while waiting for addi-

EXDEF RES RES RES XMTRC[3-0]

RES RES RES RES LLRCV M/R RES ASTRPRCV

60 Am79C940

tional data once a packet is in

progress will not cause the

RCVFIFO to underflow, and will

be indicated by DTV being

invalid. The MACE device will no

longer be able to reject runts in

this mode, this responsibility is

transferred to the host system.

In the case of a collided packet

(normal slot time collision or late

collision), the MACE device will

abort the reception, and return

the RCVFS. Note that all colli-

sions in this mode will appear as

late collisions and be reported

by the CLSN bit in the Receive

Status (RCVSTS) byte.

If the host does not keep up with

the incoming receive data, nor-

mal RCVFIFO overfl ow recovery

is provided.

Bit 2 M/R Match/Rejec t. The Match /Reject

option sets the criteria for the

External Address Detection

Interface. If set, the EAM/R pin is

configured as External Address

Match, and is used to signal th e

acceptance of a receive frame to

the MACE device. If cleared, the

pin functions as External

Address Reject and is used to

flush unwanted packets from the

Receive FIFO prior to the first

assertion of RDTREQ. M/R is

cleared by activation of the

RESET pin or SWRST bit. When

the EADI feature is disabled, the

EAM/R pin must be tied active

(low) and all normal receive ad-

dress recognition configurations

are supported (physical, logical

and prom iscuous ). See the sec-

tion “Ext erna l Ad dres s De tecti on

Interface” for additional details.

Bit 1 RES Reserved. Read as zero. Always

write as zero. Bit 0 ASTRP RCV

Auto Strip Receive. ASTRP

RCV enabl es the auto matic pad

stripping feature. The pad and

FCS fields will be stripped from

receive frames and not placed in

the FIFO. ASTRP RCV is set by

activation of the RESET pin or

the SWRST bit.

Receive Frame Status (RCVFS) (REG ADDR 6)

The Receive Frame Status is a single byte location

which must be read by four read cycles to obtain the

four bytes (32-bits) of status associated with each

receive frame. Receive Frame Status can be read

using ei ther the Regi ster Direc t or FIFO D irect acce ss

modes.

In Register Direct mode, access to the Receive FIFO

will be denied until all four status bytes for the com-

pleted fr ame ha ve be en rea d fro m the Re ceiv e Fram e

Status location. In FIFO Direct mode, the Receive

Frame Status is read through the Receive FIFO loca-

tion, by continuing to execute four read cycles after the

completion of packet data (and assertion of EOF). The

Receive Frame Status c an be read usi ng eit her mode ,

or a combi nation of bo th modes, how ever eac h status

byte will be pres ented only once regar dless of access

method. Other register reads and/or writes can be

interleaved at any time, during the Receive Frame

Sta tus sequence.

The Receive Frame Status consists of the following

four bytes of information:

RFS0 Receive Message Byte Count

(RCVCNT) [11–0]

RFS1 Receive Status, (RCVSTS) [15–12]

RFS2 Runt Packet Count (RNTPC) [7–0]

RFS3 Receive Collision Count (RCVCC) [7–0]

RFS0—Receive Message Byte Count (RCVCNT)

Bit Name Description

Bit 7-0 RCVCNT The Receive Message Byte

[7:0] Count indicates the number of

whole bytes in the received mes-

sage. If pad by tes were str ipped

from the received frame,

RCVCNT indicates the number

of bytes received less the num-

ber of pad bytes and less the

number of FCS bytes. RCVCNT

is 12 bits long. If a late collision

is detected (CLSN set in

RCVSTS), the count is an indi-

cation of the length (in byte

times) of the duration of the re-

ceive activity including the colli-

sion. RCVCNT [10:8] corre-

spond to bits 3 -0 i n RFS1 of th e

Receive Frame Status.

RCVCNT [11–0] will be invalid

when OFLO is set.

RFS1—Receive Status (RCVSTS)

Bit Name Description

Bit 7 OFLO Overflow flag. Indicates that the

Receive FIFO over flowed due

RCVFS [31–00]

OFLO CLSN FRAM FCS RCVCNT [10:8]

RCVCNT [7:0]

Am79C940 61

to the inability of the host/con-

troller to read data fast enough

to keep pace with the receive se-

rial bit stream and the latency

provided by the Receive FIFO it-

self. OFLO is indicated on the re-

ceive frame that caused the

overflow condition; complete

frames in the Receive FIFO are

not affected. While the Receive

FIFO is in the overflow condition,

it ignores additional receive data

on the network . The internal a d-

dress detect logic will continue

to operate and the Missed Pack-

et Count (MP C in register 24) will

be incremented for each packet

which passes the address match

criteria, and complete without

collision.

Bit 6 CLSN C ollisi on Flag . Indic ates th at the

receive operation suffered a col-

lision during reception of the

frame. If CLSN is set, it indicates

that the receive frame suffered a

late collision, since a frame ex-

periencing collision within the

slot time will be automatically

deleted from the RCVFIFO (pro-

viding LLRCV in the Receive

Frame Control register is

cleared) . Note that if the LLRCV

bit is enabled, the late collision

threshold is effectively moved

from the normal 64–byte (512–

bit) level to the 12-byte (96–bit)

level. Runt packets suffering a

collis ion will be flush ed from the

RCVFIFO regardless of the

state of the RPA bit (User Test

OFLO is set.

Bit 5 FRAM Framing Error flag. Indicates

that the received frame

containe d a non- i nteg er mu lti ple

of bytes and an FCS error. If

there was no FCS error then

FRAM will not be set. FRAM is

not valid during internal

loopback. FRAM will not be set if

OFLO is set.

Bit 4 FCS FCS Error flag. Indicates that

there is an FCS error in the

frame. The receive FCS is

computed and checked normally

when ASTRP RCV = 1, but is not

passed to the host. FCS will not

be set if OFLO is set.

Bit 3-0 RCVCNT The Receive Message Byte

[11:8] Count indicates the number of

whole bytes in the received

message from the network.

RCVCNT is 12 bits long, and

valid (ac curate) only when th ere

are no errors reported in the

Receive Status (RCVSTS). If a

late collision is detected (CLSN

set in RCVS TS), th e coun t is an

indication of the length (in byte

times) of the duration of the

receive activity including the

collision. RCVCNT [7:0] corre-

spond to bits 7 -0 i n RFS0 of th e

Receive Frame Status.

RCVCNT [11–0} will be invalid

when OFLO is set.

RFS2—Runt Packet Count (RNTPC)

Bit Name Description

Bit 7-0 RNTPC The Runt Packet Count

indicates

[7–0] the number of runt packets

received, addressed to this

node, since the last successfully

received packet. The value does

not roll over after 255 runt

packets have been detected,

and will remain frozen at the

maximum count.

RFS3—Receive Collision Count (RCVCC)

Bit Name Description

Bit 7–0 RCVCC The Receive Collision Count in-

[7–0] dicates the number of collisions

detected on the network since

the last successfully received

packet. The value does not roll

over after 255 collisions have

been detected, and will remain

frozen at the maximum count.

FIFO Frame Count (FIFOFC) (REG ADDR 7)

Bit Name Description

Bit 7–4 RCVFC Receive Frame Count. The

(read

[3–0] only) count of the frames in the

Receive FIFO. A frame is count-

ed when the last byte is put in

the FIFO. The counter is decre-

mented when the last byte of the

frame is read. If the RCVFC

reaches its maximum value of

RNTPC [7–0]

RCVCC [7–0]

RCVFC[3–0] XMTFC[3–0]

62 Am79C940

15, additional receive frames will

be ignored, and the Missed

Packet Count (MPC) re gister wil l

be incremented for frames which

match the internal address(es)

of the MACE device.

Bit 3–0 XMTFC Transmit Frame Count. The

[3–0] (read only) count of the frames in

the Transmit FIFO. A frame is

counted when the last byte is put

in the FIFO. The co unte r is dec -

remented when XMTSV (in the

Transmi t Frame Statu s and Poll

Frame Status read access is

performed.

Interrupt Register (IR) (REG ADDR 8)

All status bits are set upon occurrence of an event and

cleared when read. The resister is read only . In addition

all status bits are cleared by hardware or software

reset. Bit assignments for the register are as follows:

Bit Name Description

Bit 7 JAB Ja bber Err or. JAB indicates that

the MACE device attempted to

transmit for an excessive time

period (20–150 ms), when using

either the DAI port or the

10BASE–T port. If the internal

jabber timer expires during

transmission, the transmit bit

stream will be interrupted, until

the internal transmission ceases

and the unjab timer (0.5 s ±0.25

s) expires. The jabber function

will be disabled, and JAB will not

be set, regardless of transmis-

sion leng th, when eit her the A UI

or GPSI ports have been

selected.

JAB is READ/CLEAR only, and

is set by the MACE device and

reset when read. Writing has no

effect. It is also cleared by acti-

vation of the RESET pin or

SWRST bit.

Bit 6 BABL Babble Error. BABL is the

transmitter time-out error. It in-

dicates that the transmitter has

been on the channel longer

than the time required to send

the maximum packet. It will be

set after 1519 bytes (or great-

er) have been transmitted. The

MACE device will continue to

transmit until the current pack-

et transmission is over. The

INTR pin will be activated if the

corresponding mask bit

BABLM = 0.

BABL is READ/CLEAR only,

and is set by the MACE device

and reset when read. Writing

has no effect. It is also cleared

by activation of the RESET pin

or SWRST bit.

Bit 5 CERR Collision Error. CERR indicates

the absenc e of th e Si gna l Q ual i-

ty Error Test (SQE Test) mes-

sage after a packet transmis-

sion. T he SQE Test m essage is

a transceiver test feature. Detec-

tion depends on th e MACE net-

work interface selected. In all

cases, CERR will be set if the

MACE device failed to observe

the SQE Test message within 20

network bit tim es after the pack-

et transmission ended. When

CERR is set, the INTR pin will be

activated if the corresponding

mask bit CERRM = 0.

When the AUI port is selected,

the SQE Test message is

returned over the CI± pair as a

brief (5-15 bit times) burst of 10

MHz activity. When the

10BASE–T port is selected,

CERR will be reported after a

transmission only when the

internal transceiver is in the link

fail state (LNKST pin = HIGH).

When the GP S I por t is se lec ted ,

the CLSN pin must be asserted

by the external encoder/decoder

to provide the SQE Test func-

tion. When the DAI port is select-

ed, CERR will not be reported at

any time.

CERR is READ/CLEAR only. It

is set by the MACE and reset

when read. Writing has no

effect. It is also cleared by

activation of the RESET pin or

SWRST bit.

Bit 4 RCVCCO Receive Collision Count Over-

flow. Indicates that the Receive

Collision Count register rolled

over at a value of 255 receive

collisions. Receive collisions are

defined as received frames

which suffered a collision. The

INTR pin will be activated if the

corresponding mask bit RCVC-

COM = 0. Note that th e RCVCC

value returned in the Receive

Frame Sta tus (RFS 3) will fre ez e

at a value of 255, whereas this

JAB BABL CERR RDVCCO RNTPCO MPCO RCVINT XMTINT

Am79C940 63

RCVCC (REG ADDR 27) is free

running.

RCVCCO is READ/CLEAR only.

It is set by the MACE device and

reset when read. Writing has no

effect. It is also cleared by

asserting the RESET pin or

SWRST bit.

Bit 3 RNTPCO Runt Packet Count Overflow.

Indicates that the Runt Packet

Count register rolled over at a

value of 255 runt packets. Runt

packets ar e defined as receive d

frames which passed the inter-

nal address match criteria but

did not contain a minimum of

64-byte s of data af ter SFD. The

INTR pin will be activated if

the corresponding mask bit

RNTPCOM = 0. Note that the

RNTPC value returned in the

Receive Frame Status (RFS2)

will freeze at a value of 255,

whereas this register based

version of RNTPC (REG ADDR

26) is free running.

RNTPCO is READ/CLEAR only.

It is set by the MACE device and

reset when read. Writing has no

effect. It is also cleared by

asserting the RESET pin or

SWRST bit.

Bit 2 MPCO Missed Packet Count Overflow.

Indi cat es th at t he Miss ed Pack et

Count register rolled over at a

value of 255 missed frames.

Missed frames are defined as

received frames which passed

the internal address match

criteria but were missed due to a

Receive FIFO overflow, the

receiver being disabled (ENRCV

= 0) or an excessive receive

frame c oun t (RCVF C > 15) . Th e

INTR pin will be activated if the

corresponding mask bit MPCOM

= 0.

MPCO is READ/CLEAR only. It

is set by the MACE device and

reset when read. Writing has no

effect. It is also cleared by

asserting the RESET pin or

SWRST bit.

Bit 1 RCVINT Receive Interrupt. Indica tes that

the host read the last byte/word

of a packet from the Receive

FIFO. The Receive Frame Sta-

tus is available immediately on

the next host read operation.

The INTR pin will be ac tivated i f

the corresponding mask bit

RCVINTM = 0.

RCVINT is READ/CLEAR only.

It is set by the MACE device and

reset when read. Writing has no

effect. It is also cleared by acti-

vation of the RESET pin or

SWRST bit.

Bit 0 XMTINT Transmit Interrupt. Indicates that

the MACE device has completed

the transmission of a packet and

updated the Transmit Frame

Status. The INTR pin will be

activated if the corresponding

mask bit XMTINTM = 0.

XMTINT is READ/CLEAR only.

It is set by the MACE device and

reset when read. Writing has no

effect. It is also cleared by acti-

vation of the RESET pin or

SWRST bit.

Interrupt Mask Register (IMR) (REG ADDR 9)

This register cont ains the mask bits for the interrupts.

Read/write operations are permitted. Writing a one into

a bit will mask the corresponding interrupt. Writing a

zero to any previously set bit will unmask the corre-

sponding interrupt. Bit assignments for the register are

as follows:

Bit Name Description

Bit 7 JABM Jabber Error Ma sk. JABM is th e

mask fo r JAB. The I NTR pin wi ll

not be asserted by the MACE

device reg ar dless of the s tate of

the JAB bit, if JABM is set. It is

cleared by activation of the

RESET pin or SWRST bit.

Bit 6 BABLM Babble Error Mask. BABLM is

the mask for BABL. The INTR

pin will not be asserted by the

MACE device regardless of the

state of the BABL bit, if BABLM

is set. It is cleared by activation

of the RESET pin or SWRST bit.

Bit 5 CERRM Col lision Error Mask. CERRM is

the mask for CERR. The INTR

pin will not be asserted by the

MACE device regardless of the

state of the CERR bit, if CERRM

is set. It is cleared by activation

of the RESET pin or SWRST bit.

Bit 4 RCVCCOM Receive Collision Count Over-

flow Mask. RCVCCOM is the

mask for RCVCCO(Receive

Collision Count Overflow). The

INTR pin wil l not be a sserted by

RES BABLM CERRM RCVCCOM RNTPCOM MPCOM RCVINTM XMTINTM

64 Am79C940

the MACE device regardless of

the state of the RCVCCO bit, if

RCVCCOM is set. It is cleared

by activation of the RESET pin

or SWRST bit.

Bit 3 RNTPCOM Runt Packet Count Overflow

Mask. RNTPCOM is the mask

for RNTPCO (Runt Packet

Count Overflow). The INTR pin

will not be asserted by the

MACE device regardless of the

state of the RNTPCO bit, if

RNTPCOM is set. It is cleared by

activation of the RESET pin or

SWRST bit.

Bit 2 MPCOM Missed Packet Count Overflow

Mask. MPCOM is the mask for

MPCO (Missed Packet Count

Overflow). The INT R pin will no t

be asserted by the MACE device

regardless of the state of the

MPCO bit, if MPCOM is set. It is

cleared by activation of the

RESET pin or SWRST bit.

Bit 1 RCVINTM Receive Interrupt Mask.

RCVINTM is the mask for

RCVINT. The INTR pin will not

be asserted by the MACE device

regardless of the state of the

RCVINT bit, if RCVINTM is set. It

is cleared by activation of the

RESET pin or SWRST bit.

Bit 0 XMTINTM Transmit Interrupt Mask.

XMTINTM is the mask for

XMTINT. The INTR pin will not

be asserted by the MACE device

regardless of the state of the

XMTINT bit, if XMTINT is set. It

is cleared by activation of the

RESET pin or SWRST bit

Poll Register (PR) (REG ADDR 10)

This register contains copies of internal status bits to

simplify a host implementation which is non-interrupt

driven. The register is read only, and its status is unaf-

fected by read o peration s. All register bits are cleared

by hardw ar e or s oft war e res et. Bi t as si gn men ts a re as

follows:

Bit Name Description

Bit 7 XMTSV Transmit Status Valid. Transmit

Status Valid indicates that the

Transmit Frame Stat us is valid.

Bit 6 TDTREQ Transmit Data Transfer

Request. An internal indication

of the current request status of

the Transmit FIFO. TDTREQ is

set when the external TDTREQ

signal is asse rt ed.

Bit 5 RDTREQ Receive Data Transfer Request.

An inte rnal in dication of th e cur-

rent request status of the

Receive FIFO. RDTREQ is set

when the external RDTREQ

signal is asse rt ed.

Bit 4-0 RES Reserved. Read as zeroes.

Always write as zeroes.

BIUConfigurationControl(BIUCC) (REGADDR11)

All bits within the BIU Configuration Control register will

be set to their default state upon a hardware or soft-

ware reset. Bit assignments are as follows:

Bit Name Description

Bit 7 RES Reserved. Read as zero. Always

write as zero.

Bit 6 BSW P Byte Swap. The BSWP function

allows data to and from the

FIFOs to be orientated accord-

ing to little endian or big endian

byte ordering conventions.

BSWP is cleared by by activa-

tion of the RESET pin or SWRST

bit, defaulting to Intel byte

ordering.

Bit 5-4 XMTSP Transmit Start Point. XMTSP

[1-0] controls the point preamble

transmission commences in

relation to the number of bytes

written to the XMTFIFO. When

the entire frame is in the XMT-

FIFO (or the XMTFIFO becomes

full before the threshold is

achieved), transmission of pre-

amble will start regardless of the

value in XMTSP (once the IPG

time has expired). XMTSP is

given a value of 10 (64 bytes)

after hardware or software reset.

Regardless of XMTSP, the FIFO

will not internally over write its

data until at least 64 bytes, or the

entire fr ame, h as bee n transm it-

ted onto the network. This

ensure s that for collisi ons within

the slot time window, transmit

data need not be re-written to

the XMTFIFO, and re-tries will

be handled autonomously by the

MACE device.

XMTSV TDTREQ RDTREQ RES RES RES RES RES

RES BSWP XMTSP [1-0] RES RES RES SWRST

Am79C940 65

Transmit Start Point

Bit 3-1 RES Reserved. Read as zeroes. Al-

ways write as zeroes.

Bit 0 SWRST Software Reset. When set, pro-

vides an equivalent of the hard-

ware RESET pin function. All

default values. The MACE de-

vice will require re-initialization

after SWRST has been activat-

ed. The MACE device will clear

SWRST during its internal rese t

sequence.

FIFO Configuration Control (REG ADDR 12)

(FIFOCC)

All bits within the FIFO Configuration Control register

will be set to their default state upon a hardware or soft-

ware reset. Bit assignments are as follows:

Bit Name Description

Bit 7-6 XMTFW Transmit

FIFO Watermark.

[1-0] XMTFW controls the point

TDTREQ is asserted in relation

to the number of write cycles to

the Transmit FIFO. TDTREQ will

be ass erted at a ny time that th e

number o f write cycles speci fied

by XMTFW can be executed.

XMTFW is set to a value of 00 (8

cycles) after hardware or

software reset.

Transmit FIFO Watermarks

The XMTFW value will only be

updated when the XMTFWU bit

is set.

To ensure that sufficient space

is present in the XMTFIFO to

accept the specified number of

write cycles (including an

End-Of-Frame delimiter),

TDTREQ may go inactive before

the XMTSP threshold is reached

when using the non burst mode

(XMTBRST = 0). The host must

be aware that despite TDTREQ

going inactive, additional space

exists in the XMTFIFO, and the

data write must continue to

ensure the XMTSP threshold is

achieved. No transmit activity

will commence until the XMTSP

threshold is reached. When

using the burst mode, TDTREQ

will not be de - ass erted until on ly

a single write cycle can be per-

formed. See the FIFO Sub-sys-

tem section for additional de-

tails.

Bit 5-4 RCVFW Receive FIFO Watermark.

[1-0] RCVFW controls the point

RDTREQ is asserted in relation

to the number of bytes available

in the RCVFIFO. RCVFW speci-

fies the number of bytes which

must be present (once the pack-

et has been verified as a

non-runt), before the RDTREQ

is asserted. Note however that in

order for RDTREQ to be activat-

ed for a new frame, at least

64-bytes must have been

received . This effe ctively avoids

reacting to receive frames which

are runts or suffer a collision dur-

ing the slot time (512 bit times).

If the Runt Packet Accept fea-

ture (RPA in Receive Frame

Control) is enabled, the

RDTREQ pin will be activated as

soon as either 64-bytes are

received, or a complete valid

receive frame is detected

(regardless of length). RCVFW

is set to a v al ue o f 10 (6 4 byte s)

after hardware or software reset.

Receive FIFO Watermarks

The RCVFW value will only be

updated when the RCVFWU bit

is set.

Bit 3 XMTFWU Transmit FIFO Watermark

Update. Allows update of the

XMTSP [1-0] Bytes

00 4

01 16

10 64

11 112

XMTFW[1-0] RCVFW [1-0] XMTFWU RCVFWU XMTBRST RCVBRST

XMTSP [1–0] Bytes

00 8

01 16

10 32

11 XX

XMTSP [1–0] Bytes

00 16

01 32

10 64

11 XX

66 Am79C940

Transmit FIFO Watermark bits.

The XMTFW can be written at

any point, and will b e read back

as written. However, the new

valu e in the XMT FW bits wi ll be

ignored unti l XM T FWU i s set ( or

the transm it path is reset due to

a r etr y f a il ur e) . T h e re co mm end -

ed procedure to change the

XMTFW is to write the new value

with XMTFWU set, in a single

write cycle. The XMTFIFO

should be empty and all transmit

activity complete before attempt-

ing a watermark update, since

the XMTFIFO will be reset to

allow the new pointer values to

be loaded. It is recommended

that the transmitter be disabled

by clearing the ENXMT bit.

XMTFWU will be cleared by the

MACE device after the new

XMTFW value has been loaded,

or by activation of the RESET

pin or SWRST bit.

Bit 2 RCVFWU Receive FIFO Watermark

Update. Allows update of the

Receive FIFO Watermark bits.

The RCVFW bits can be written

at any point, and will read back

as written. However, the new

value in the RCVFW bits will be

ignored until RCVFWU is set.

The recommended procedure to

change the RCVFW is to write

the new value with RCVFWU

set, in a single write cycle. The

RCVFIFO should be empty

before attempting a watermark

update, since the RCVFIFO will

be reset to allow the new pointer

valu es to be lo aded. It is re co m-

mended that the receiver be dis-

abled by clearing the ENRCV

bit. RCVFWU will be cleared by

the MACE device after the new

RCVFW value has been loaded,

or by activation of the RESET

pin or SWRST bit.

Bit 1 XMTBRST Transmit Burst. When set, the

transmit b urst mode i s selected.

The behavior of the Transmit

FIFO high watermark, and

hence the de-assertion of

TDTREQ, will be modified.

TDTREQ will be deasserted if

there are only two bytes of space

available in the XMTFIFO (so

that a full word write can still

occur) or if four bytes of space

exist and the EOF pin is assert -

ed by the host.TDTREQ will be

asserted identically in both

normal and burst modes, when

there is sufficient space in the

XMTFIFO to allow the specified

number of write cycles to occur

(programmed by the XMTFW

bits).

Cleared by activation of the

RESET pin or SWRST bit.

Bit 0 RCVBRST Receive Burst. When set, the

receive burst mode is selected.

The behavior of the Receive

FIFO low w ater ma rk, a nd he nc e

the de-assertion of RDTREQ,

will be modified. RDTREQ will

de-assert when there are only

2-bytes of data available in the

RCVFIFO (so that a full word

read can still occur).

RDTREQ will be asserted identi-

cally in both normal and burst

modes, when a minimum of

64-bytes have been received for

a new frame (or a runt packet

has been received and RPA is

set). Once the 64-byte limit has

been exceeded, RDTREQ will

be asserted providing there is

sufficient data in the RCVFIFO

to exceed the threshold, as pr o-

grammed by the RCVFW bits.

Cleared by activation of the

RESET pin or SWRST bit.

MAC Configuration

Control (MACCC) (REG ADDR 13)

This register programs the transmit and receive opera-

tion and behavior of the internal MAC engine. All bits

within the MAC Configuration Control register are

cleared upon hardware or software reset. Bit

assignments are as follows:

Bit Name Description

Bit 7 PROM Promiscuous. When PROM is

set all incoming frames are

receiv ed re gardl es s o f the d e st i-

nation address. PROM is

cleared by activation of the

RESET pin or SWRST bit.

Bit 6 DXMT2PD Disable Transmit Two Part

Deferral. W hen set, di sa ble s th e

transmit two part deferral option.

DXMT2PD is cleared by

activation of the RESET pin or

SWRST bit.

Bit 5 EMBA Enable Modified Back-off Algo-

rithm. When set, enables the

PROM DXMT2PD EMBA RES DRCVPA DRCVBC ENXMT ENRCV

Am79C940 67

modified backoff algorithm.

EMBA is cleared by activation of

the RESET pin or SWRST bit.

Bit 4 RES Reserved. Read as zeroes.

Always write as zeroes.

Bit 3 DRCVPA Disable Receive Physical

Address. When set, the physical

address detection (Station or

node ID) of the MACE device will

be disabl ed. Packets ad dresse d

to the nodes individual physical

address will not be recognized

(although the packet may be

accepted by the EADI mecha-

nism). DRCVPA is cleared by

activation of the RESET pin or

SWRST bit.

Bit 2 DRCVBC Disable Receive Broadcast.

When set, disables the MACE

device from responding to

broadcast messages. Used for

protocols that do not support

broadcast addressing, except as

a function of multicast. DRCVBC

is cleared by activation of the

RESET pin or SWRST bit

(broadcast messages will be

received).

Bit 1 ENXMT Enable Transmit. Setting

ENXMT = 1 enables transmis-

sion. With ENXMT = 0, no trans-

mission will occur. If ENXMT is

written as 0 during frame trans-

mission, a packet transmission

which is incomplete will have a

guaranteed CRC violation

appended before the internal

Transmit FIFO is cleared. No

subsequ ent a ttem pts to lo ad th e

FIFO should be made until

ENXMT is set and TDTREQ is

asserted. ENXMT is cleared by

activation of the RESET pin or

SWRST bit.

Bit 0 ENRCV Enable Receive. Setting ENRCV

= 1 enables reception of frames.

With ENRCV = 0, no frame s will

be received from the network

into the internal FIFO. When

ENRCV is written as 0, any

receive frame currently in

progre ss will be co mpleted ( and

valid data contained in the

RCVFIFO can be read by the

host) and the MACE device will

enter the monitoring state for

missed packets. Note that

clearing th e ENRCV bit d isabl es

the assertion of RDTREQ. If

ENRCV is cleared during re-

ceive activity and remains

cleared for a long time and if the

tail end of the receive frame cur-

rently in progress is longer than

the amount of space available in

the Receive FIFO, Receive

FIFO overflow will occur. How-

ever, even with RDTREQ deas-

serted, if there is valid data in the

Receive FIFO to be read, suc-

cessful slave reads to the

Receive FIFO can be executed

(indicated by valid DTV). It is the

host’s respons ibility to avoid th e

overflow situation. ENRCV is

cleared by activation of the

RESET pin or SWRST bit.

PLS Configuration

Control (PLSCC) (REG ADDR 14)

All bits within the PLS Configuration Control register

are cleared upon a hardware or software reset. Bit

assignments are as follows:

Bit Name Description

Bit 7-4 RES Reserved. Read as zeroes.

Always write as zeroes.

Bit 3 XMTSEL Transmit Mode Select. XMTSEL

provides control over the AUI

DO+ and DO– operation while

the MACE device is not transmit-

ting. With XMTSEL = 0, DO+

and DO will be equal during

transmit idle state, providing

zero differential to operate trans-

former coupled loads. The turn

off and r etu rn to z er o d elay s are

controlled internally. With

XMTSEL = 1, DO+ is positive

with respect to DO during the

transmit idle state .

Bit 2-1 PORTSEL Port Select. PORTSEL is used

[1-0] to select between the AUI,

10BASE–T, DAI or GPSI ports

of the MA CE device . PORTSEL

is cleared by hardware or soft-

ware reset. PORTSEL will deter-

mine which of the interfaces is

used during normal operation, or

tested when utilizing the loop-

back options (LOOP [1-0]) in the

User Test Register. Note that

the PORTSEL [1–0] program-

ming will be overridden if the

ASEL bit in the PHY Configura-

tion Control register is set.

RES RES RES RES XMTSEL PORTSEL [1-0] ENPLSIO

68 Am79C940

PORTSEL Interface Definition

Bit 0 ENPLSIO Enable PLS I/O. ENPLSIO is

used to enable the optional I/O

functions fr om the PLS fun ction.

The following pins are affected

by the ENPLSIO bit: RXCRS,

RXDAT, TXEN, TXDAT+,

TXDAT-, CLSN, STDCLK,

RDCLK and SRD. Note that if an

externa l SIA is being uti lized via

the GPSI , PORTSEL [1–0] = 11

must be programmed before

ENPLSIO is set, to avoid con-

tention of clock, data and/or

carrier indicator signals.

PHY Configuration

Control (PHYCC) (REG ADDR 15)

All bits within the PHY Configuration Control register

with the exc eption of LNKFL, are cleared by hardwar e

or software reset. Bit assignments are as follows:

Bit Name Description

Bit 7 LNKFL Link Fail. Reports the link integ-

rity of the 10BASE–T receiver.

When the link test function is

enabled (DLNKTST = 0), the

absence of link beat pulses on

the RXD± pair will cause the

integrated 10BASE–T transceiv-

er to go into the link fail state . In

the link fail sta te, data transmis -

sion, data reception, data loop-

back and the collision detection

functions are disabled, and

remain disabled until valid data

or >5 consecutive link pulses

appear on the RXD± pair. During

link fail, the LNKFL bit will be set

and the LNKST pin should be

externally pulled HIGH. When

the link is identified as function-

al, the LN KFL bit wil l be clear ed

and the LNKST pin is driven

LOW, which is capable of direct-

ly driving a Link OK LED. In

order to inter-operate with sys-

tems which do not implement

Link Test, this function can be

disabled by setting the

DLNKTST bit. With Link Test

disabled (DLNKTST = 1), the

data driver, receiver and loop-

back functions as well as colli-

sion detection remain enabled

irrespective of the presence or

absence of data or link pulses on

the RXD± pair. The transmitter

will continue to generate link

beat pulses during periods of

transmit data inactivity. Set by

hardware or software reset.

Bit 6 DLNKTST Disable Link Test. When set, the

integrated 10BASE–T transceiv-

er will be forced into the link pass

state, regardless of receive link

test pulses or receive packet

activity.

Bit 5 REVPOL Reversed Polarity. Indicates the

receive po larity of the RD± pair.

When normal polarity is detect-

ed, the REVPOL bit will be

cleared, and the RXPOL pin

(capable of driving a Polarity O K

LED) will be dr iven LOW . When

reverse polarity is detected, the

REVPOL bit will be set, and the

RXPOL pin sho uld be ext ernally

pulled HIGH.

Bit 4 DAPC Disable Auto Polarity Correction.

When set, the automatic polarity

correction will be disabled.

Pola rity det ection and i ndication

will still be possible via the

RXPOL pin.

Bit 3 LRT Low Receive Threshold. When

set, the threshold of the twisted

pair receiver will be reduced by

4.5 dB, to allow extended dis-

tance operation.

Bit 2 ASEL Auto Select. When set, the

PORTSEL [1-0] bits are overrid-

den, and the MACE device will

automatically select the operat-

ing media interface port. When

the 10BASE–T transceiver is in

the link pass state (due to receiv-

ing valid packet data and/or Link

Test pulse s or the DLNKTST bit

is set), the 10BASE-T port will be

used. Whe n the 10B AS E–T port

is in the link fail state, the AUI

port will be used. Switching

between th e ports will not occur

during transmission in order to

avoid any type of fragment

generation.

Bit 1 RWAKE Remote Wake. When set prior to

the SLEEP pin being activated,

the AUI and 10BASE–T receiver

sections and the EADI port will

PORTSEL

[1–0] Active

Interface DXCVR Pin

00 AUI LOW

01 10BASE–THIGH

10 DAI Port HIGH

11 GPSI LOW

LNKFL DLNKTST REVPOL DAPC LRT ASEL RWAKE AWAKE

Am79C940 69

continue to operate e ven during

SLEEP. Inco ming pack et activi ty

will be passed to the EADI port

pins permi tting d etecti on of sp e-

cific frame contents used to ini-

tiate a wake-up sequence.

RWAKE must be programmed

prior to SLEEP being asserted

for this function to operate.

RWAKE is not cleared by

SLEEP, only by activ ation of the

SWRST bit or RESET pin.

Bit 0 AWAKE Auto Wake. When set prior to

the SLEEP pin being activated,

the 10BASE-T receiver section

will continue to operate even

during SLEEP, and will activate

the LNKST pin if Link Pass is

detected. AWAKE must be pro-

grammed prior to SLEEP being

asserted for this function to

operate. AWAKE is not cleared

by SLEEP, only by activation of

the SWRST bit or RESET pin.

Chip Identification Register

(CHIPID [15-00]) (REG ADDR 16 &17)

This 16-bit value corresponds to the specific version of

the MACE device being used. The value will be

programme d to X940 h, where X is a value depen dent

on version. [For the current version of the MACE de-

vice, X = 3 to denote Rev C0 silicon.]

Internal Address

Configuration (IAC) (REG ADDR 18)

This register allows access to and from the mu lti-byte

Physical Address and Logical Address Filter locations,

using only a single byte location.

The MACE d evi ce will r ese t th e IAC re gist er P HYADDR

and LOGADDR bits after the appropriate number of

read or write cycles have been executed on the Physical

Address Register or the Logical Address Filter. Once the

LOGADDR bi t is set, t he MA CE de vic e wil l res et the bit

after 8 read or write operations have been performed.

Once the PHYADDR bit is set, the MACE device will

reset the bi t after 6 read or wr ite ope ratio ns have been

perfor med. T he MACE de vice makes no distinc tion be-

tween read or write operations, advancing the internal

address RAM pointer with each access. If both PHY-

ADDR and LOGADDR bits are set, the MACE device

will accep t only the LOGADD R bit. If the PHYADDR bit

is set and the Logical Address Filter location is ac-

cessed, a DTV will not be returned. Similarly, if the

LOGADDR bit is set and the Physical Address Register

location is accessed, DTV will not be returned. PHY-

ADDR or LOGADDR can be set in the same cycle as

ADDRCHG.

Bit Name Description

Bit 7 ADDRCHG Address Change. When set,

allows the physical and/or logi-

cal address to be read or pro-

grammed. When ADDRCHG is

set, ENRCV will be cleared, the

MPC will be stopped, and the

last or current in progress

recei ve fram e will be r eceived a s

normal. After the frame com-

pletes, access to the internal

address RAM will be permitted,

indicated by the MACE device

clearing the ADDRCHG bit.

Please refer to the register

description of the ENRCV bit in

the MAC Configuration Control

effect of clearing the ENRCV bit.

Normal reception can be

resumed once the physical/logi-

cal address has been changed,

by setting ENRCV.

Bit 6-3 RES Reserved. Read as zeroes.

Always write as zeroes.

Bit 2 PHYADDR Physical Address Reset. When

set, successive reads or writes

to the Physical Address Register

will occur in the order PADR

[07–00], PADR [15–08],....,

PADR [47–40]. Each read or

write operation on the PADR

location will auto-increment the

internal pointer to access the

next most significant byte.

Bit 1 LOGADDR Logical Address Reset. When

set, successive reads or writes

to the Logica l Address F ilter will

occur in the order LADRF [07–

00], LADRF [15-08],....,LADRF

[63–56]. Each read or write

operation on the LADRF location

will auto-increment the internal

pointer to access the next most

significant byte.

Bit 0 RES Reserved. Read as zero. Always

write as zero.

Logical Address Filter

(LADRF [63–00]) (REG ADDR 20)

This 64-bit mask is used to accept incoming Logical

Addresses. The Logical Address Filter is expected to

be programmed at initialization (after hardware or

CHIPID [07–00]

CHIPID [15–08]

ADDRCHG RES RES RES RES PHYADDR LOGADDR RES

LADRF [63–00]

70 Am79C940

software reset). After a hardware or software reset and

before the ENRCV bit in the MAC Configuration Con-

trol r egister h as been set, the Logical Address can b e

accessed by settin g the LOG ADDR bit in the Internal

Address Configuration register (REG ADDR 18) and

then by performing 8 reads or writes to the Logical

Address Filter. Once ENRCV has been se t, the ADDR

CHG bit in th e Internal Addre ss Config uration register

must be set and be polled until it is cleared by the

MACE device before setting the LOGADDR bit and

before accessing of the Logical Address Filter is

allowed.

If the least significant address bit of a received

message is set (Destination Address bit 00 = 1), then

the address is deemed logical, and passed through the

FCS genera tor. After processing the 48-bi t destinatio n

address, a 32-bit resultant FCS is produced and

strobed into an internal register. Th e high order 6-bits

of this resultant FCS are used to select one of the 64-bit

positions in the Logical Address Filter (see diagram). If

the selected filter bit is a 1, the address is accepted and

the packet will be placed in memory.

The first bi t of the incoming ad dress must be a 1 for a

logical address. If the first bit is a 0, it is a physical

address and is compared against the value stored in

the Physical Address Register at initialization.

The Logical Address Filter is used in multicast address-

ing schemes. The acceptance of the incoming frame

based on the filter value indicates that the message

may be intended for the node. It is the user’s resp onsi-

bility to determine if the message is actually intended

for the node by comparing the destination address of

the stored message with a list of acceptable logical

addresses.

The Broadcast address, which is all ones, does not go

through the Logical Address Filter and is always

enabled provided the Disable Receive Broadcast bit

(DRCVBC in the MAC Configuration Control register) is

cleared. If the Logical A ddress Filter i s loaded with all

zeroes (and PROM = 0), all incoming logical addresses

except broadcast will be rejected.

Multicast addressing can only be performed when

using external loopback (LOOP [1–0] = 0) by pro-

gramming RCVFCSE = 1 in the User Test Register.

The FCS logic is internally allocated to the receiver

section, allowing the FCS to be computed on the in-

coming logic al add res s.

47 1 0

Received Message

Destination Address

1CRC

GEN

SEL

31 26 0

MUX MATCH*

MATCH = 1:

MATCH = 0:

P acket Accepted

Packet Rejected

63 0

Logical

Address

Filter

(LADRF)

32-Bit Resultant CRC

16235D-10

Logical Address Match Logic

Physical Address

(PADR [47-00]) (REG ADDR 21)

This 48-bit value represents the unique node value

assigned by the IEEE and used for internal address

comparison. After a hardware or software reset and

before the ENRCV bit in the MAC Configuration Con-

trol register has been set, the Physical Address can be

accessed by setting the PHYADDR bit in the Internal

Address Configuration register (REG ADDR 18) and

then by performing 6 reads or writes to the Physical

Address. Once ENRCV has been set, the ADDRCHG

bit in the Internal A ddress Configur ation register must

be set and be polled until it is cleared by the MACE

device before setting the PHYADDR bit and before

accessing of the Physical Address is allowed. The first

bit of the in comin g address m ust be a 0 for a physic al

address. The incoming address is compared against

the va lu e stored i n t h e Ph ys ica l Ad dr es s r e gister at i ni -

tialization provided that the DRCVPA bit in the MAC

Configuration Control register is cleared.

Missed Packet Count (MPC) (REG ADDR 24)

The Missed Packet Count (MPC) is a read only 8-bit

counter. The MPC is incremented when the receiver is

unable to respond to a packet which would have nor-

mally b een passed to the host . The MP C will be re set

to zero when read. The MACE device will be deaf to

receive traffic due to any of the following conditions:

■The host disabled the receive function by clearing

the ENRCV bit in the MAC Configuration Control

■A Receive FIFO overflow condition exists, and must

be cleared by reading the Receive FIFO and the

Receive Frame Stat us.

■The Receive Frame Count (RCVFC) in the FIFO

Frame Co unt register ex ceeds its maxi mum value,

indicating that greater than 15 frames are in the

Receive FIFO.

If the number of received frames that have been

missed exceeds 255, the MPC will roll over and con-

tinue counting from zero, the MPCO (Missed Packet

Count Overfl ow) bit in the Interr upt Reg ister wil l be set

(at the value 255), and the INTR pin will be asserted

providing that MPCOM (Missed Packet Count Overflow

Mask) in the I nter rupt Mas k Reg ister i s cl ear. MPCOM

will be c leared (the interrupt w ill be unm asked) afte r a

hardware or software reset.

Note that the following conditions apply to the MPC:

■After hardware or software reset, the MPC will not

increment until the first time the receiver is enabled

(ENRCV = 1). Once the receiver has been enabled,

the MPC will count all missed packet events,

regardless of the programming of ENRCV.

■The packet must pass the internal address match to

be counted. Any of the following address match

conditi ons will i ncreme nt MPC wh ile the rece iver is

deaf:

Physical Address match;

Logical Address match;

Broadcast reception;

Any receive in promiscuous mode (PROM = 1 in the

MAC Configuration Control register);

EADI feature match mode and EAM is as serted;

EADI feature reject mode and EAR is not asserted.

■Any packet which suffers a collision within the slot

time will not be counted.

■Runt packets will not be counted unless RPA in the

User Test Register is enabled.

■Packets which pass the a ddress match c riteria but

experienc e FCS or Frami ng errors will be counted,

since they are normally passed to the host.

Runt Packet Count (RNTPC) (REG ADDR 26)

The Runt Packet Count (RNTPC) is a read only 8-bit

counter, incremen ted when th e rece iver det ects a runt

packet that is addressed to this node. Runt packets are

defined as received frames which passed the internal

address match criteria but did not contain a minimum

of 64-bytes of data after SFD. Note that the RNTPC

value returned in the Receive Frame Status (RFS2) will

freeze at a value of 255, whereas this register based

version of RNTPC is free running. The value will roll

over after 255 runt packets have been detected, setting

the RNTPC O bit (in th e Interrupt Re gister and a ssert-

ing the INTR pin if the co rres po ndi ng ma sk bit (R NTP-

COM in the Interrupt Mask Register) is cleared.

RNTPC will be reset to zero when read.

Receive Collision Count (RCVCC)(REG ADDR 27)

The Receive Collision Count (RCVCC) is a read only

8-bit counter, incremented when the receiver detects a

collision on the network. Note that the RCVCC value

returned in the Receive Frame Status (RFS3) will

freeze at a value of 255, whereas this register based

version of RCVCC is free running. The value will roll

over after 255 receive collisions have been detected,

setting the RCVCCO bit (in the Inte rrupt Register an d

asserting the INTR pin if the corresponding mask bit

(RCVCCOM in the Interrupt Mask Register) is cleared.

RCVCC will be reset to zero when read.

User Test Register (UTR) (REG ADDR 29)

The User Test Register is used to put the chip into test

configurations. All bits within the Test Register are

cleared upon a hardware or software reset. Bit

assignments are as follows:

PADR [47–00]

MPC [7–0]

RTRE RTRD RPA FCOLL RCVFCSE LOOP [1-0] FD_TEST

RNTPC [7–0]

RCVCC [7–0]

Bit Name Description

Bit 7 RTRE Reserved Test Register Ena ble.

Access to the Reserved Test

Registers should not be attempt-

ed by the user. Note that

access to the Reserved Test

to the MACE device if config-

ured in a system board appli-

cation. Access t o the Re served

Test Register is prevented,

regardless of the state of RTRE,

once RTRD has been set. RTRE

is cleared by activation of the

RESET pin or SWRST bit.

Bit 6 RTRD Reserved Test Register Disable.

When set, access to the

Reserved Test Registers is

inhibited, and further writes to

the RTRD bit are ignored.

Access to the Reserved Test

less of the state of RTRE, once

RTRD has been set. RTRD can

only be cleared by hardware or

software reset.

Bit 5 RPA Runt Packet Accept. Allows

receive packets which are less

than th e le gal m ini mum as sp ec-

ified by IEEE 802.3/Ethernet, to

be passed to the host interface

via the Receive FIFO. The

receive packets must be at least

8 bytes (after SFD) in length to

be accepted. RPA is cleared by

activation of the RESET pin or

SWRST bit.

Bit 4 FC OLL Force Collision . Allows the coll i-

sion logic to be tested. The

MACE device should be in an

internal loopback test for the

FCOLL test. When FCOLL = 1, a

collision will be forced during the

next transmission attempt. This

will result in 16 total transmis-

sion attempts (if DRTRY = 0)

with the Retry Error reported in

the Transmit Frame Status reg-

ister. FCOLL is cleared by the

activation of the RESET pin or

SWRST bit.

Bit3 RCVFCSE Receive FCS Enable. Allows the

hardware associated with the

FCS generation to be allocated

to the transmitter or receiver dur-

ing loopback diagnostics. When

clear, th e FC S wi ll be gen erate d

and appended to the transmit

message (providing that DX MT-

FCS in the Transmit Frame Con-

trol is clear), and received after

the loopback process through

the Receive FIFO. When set, the

hardware associated with the

FCS generation is allocated to

the receiver. A transmit packet

will be assumed to contain the

FCS in the last f our byte s of the

frame passed through the

Transmit FIFO. The received

frame will have the FCS calcu-

lated on t he data field and com-

pared with the last four bytes

contained in the received mes-

sage. An FCS error will be

flagged in the Received Status

(RFS1) if the received and cal-

culated values do not match.

RCVFCSE is only valid when in

any one of the loopback modes

as defi ned b y LO O P [0–1]. Not e

that if the receive frame is

expected to be recognized on

the basis of a multicast add ress

match, the FCS logic must be

allocated to the receiver

(RCVFCSE = 1). RCVFCSE is

cleared by activation of the

RESET pin or SWRST bit.

Bit 2-1 LOOP [1-0] Loopback Control. The loopback

functions allow the MACE

device to receive its own trans-

mitted frames. Three levels of

loopback are provided as shown

in the following table. During

loopback operation a multicast

addres s can onl y be reco gnized

if RCVFCSE = 1. LOOP [0-1] are

cleared by activation of the

RESET pin or SWRST bit

Loopback Functions

External loopback allow the

MACE device to transmit to the

physical medium, using either

the AUI, 10BASE–T, DAI or

GPSI port, dependent on the

PORTSEL [1–0] bits in the PLS

Configuration Control register.

Using the internal loopback test

will ensure that transmission

Loop [1–0] Function

00 No Loo pba ck

01 Extern al Loo pback

10 Internal Loopba ck , exc lud es

MENDEC

11 Internal Loopba ck , incl ude s

MENDEC

does not disturb the physical

medium and will prohibit frame

reception from the network. One

Internal loopback function in-

cludes the MENDEC in the loop.

Bit 0 FD_TEST Full Duplex Test. When set, will

allow the MACE device to

transmit back to back packets

with 9.6 µs IPG regardless of

receive ac ti vitie s. The sett ing of

this bit should also be in

conjunction with the setting of

Bit 0 of the T ransmi t Frame Con-

trol (XMTFC) (REG ADDR 2).

The setting of Bit 0 of the

XMTFC register will cause dis-

abling of transmit FCS.

To activate Full Duplex Test mode, program the MACE

device into external loopback mode (EXLOOP=1,

INLOOP=0) and set FD_TEST=1. The code sequence

would be as follows:

write 2 08 ;register XMTFC, transmit FCS disable

write 29 0b ;register UTR, receive FCS enable external

loop enable, full duplex enable

Reserved Test Register 1 (RTR1) (REG ADDR 30)

Reserved for AMD internal use only .

Reserved Test Register 2 (RTR2) (REG ADDR 31)

Reserved for AMD internal use only .

Address Mnemonic Contents Comments

0 RCVFIFO Receive FIFO [15–00] Read only

1 XMTFIFO Transmit FIFO [15–00] Write only

2 XMTFC Transmit Frame Control Read/Write

3 XMTFS Transmit Frame Status Read only

4 XMTRC Transmit Retry Count Read only

5 RCVFC Receive Frame Control Read/Write

6 RCVFS Receive Frame Status (4-bytes) Read only

7 FIFOFC FIFO Frame Count Read only

8 IR Interrupt Regist er Read onl y

9 IMR Interrupt Mask Register Read/Write

10 P R Poll R egister Read only

11 BIUCC BIU Configuration Control Read/Write

12 FIFOCC FIFO Configuration Control Read/Write

13 MACCC MAC Configuration Control Read/Write

14 PLSCC PLS Configuration Control Read/Write

15 PHYCC PHY Configuration Control Read/Write

16 CHIPID Chip Identification Register [07–00] Read only

17 CHIPID Chip Identification Register [15–08] Read only

18 IAC Internal Addre ss Config uration Read/Writ e

19 Reserved Read/Write as 0

20 LADRF Logical Address Filter (8-bytes) Read/Write

21 PADR Physical Addre ss (6-byt es) Read/Writ e

22 Reserved Read/Write as 0

23 Reserved Read/Write as 0

24 MPC Missed Packet Count Read only

25 Reserved Read/Write as 0

26 RNTPC Runt Packet Count Read only

27 RCVCC Rece iv e Collision Count Read only

28 Reserved Read/Write as 0

29 UTR User Test Register Read/ Write

30 RTR1 Reserved Test Register 1 Read/Write as 0

31 RTR2 Reserved Test Register 2 Read/Write as 0

16-Bit Registers

8-Bit Registers

Receive Frame Status

0 RCVFIFO [15–0]

1 XMTFIFO [15–0]

Address Mnemonic

2 DRTRY RES RES RES DXMTFCS RES RES APADXMT

3 XMTSV UFLO LCOL MORE ONE DEFER LCAR

4 EXDEF RES RES RES XMTRC [3–0]

5 RES RES RES RES LLRCV M/R RES ASTRPRCV

6 RCVFS [31–00]

7 RCVFC [3–0] XMTFC [ 3–0]

8 JAB BABL CERR RCVCCO RNTPCO MPCO RCVINT XMTINT

9 JABM BABLM CERRM RCVCCOM RNTPCOM MPCOM RCVINTM XMTINTM

10 XMTSV TDTREQ RDTREQ RES RES RES RES RES

11 RES BSWP XMTSP [1–0] RES RES RES SWRST

12 XMTFW [1–0] RCVFW [1–0] XMTFWU RCVFWU XMTBRST RCVBRST

13 PROM DXMT2PD EMBA RES DRCVPA DRCVBC ENXMT ENRCV

14 RES RES RES RES XMTSEL PORTSEL [1–0] ENPLSIO

15 LNKFL DLNKTST REVPOL DAPC LRT ASEL RWAKE AWAKE

16 CHIPID [07–00]

17 CHIPID [15–08]

18 ADDRCHG RES RES RES RES PHYADDR LOGADDR RES

19 RESERVED

20 LADRF [63–00]

21 PADR [47–00]

22 RESERVED

23 RESERVED

24 MPC [7–0]

25 RESERVED

26 RNTPC [7–0]

27 RCVCC [7–0]

28 RESERVED

29 RTRE RTRD RPA FCOLL RCVFCSE LOOP [1–0] RES

30 RESERVED

31 RESERVED

Address Mnemonic

RFS0 RCVCNT [7:0]

RFS1 OFLO CLSN FRAM FCS RCVCNT [10:8]

RFS2 RNTPC [7–0]

RFS3 RCVCC [7–0]

Programmer’s Register Model

Addr Mnemonic Contents R/W

0 RCVFIFO Receive FIFO–16 bits RO

1 XMTFIFO Tran s mit FIFO–16 bits WO

2 XMTFC Transmit Frame Control

80 DRTRY Disable Retry

08 DXMTFC Disable Transmit FCS

01 APADXMT Auto Pad Transmit

R/W

3 XMTFS Transmit Frame Status

80 XMTSV Transmit Status Valid

40 UFLO Underflow

20 LCOL Late Collision

10 MORE MORE than one retry was needed

08 ONE Exactly ONE retry occurred

04 DEFER Transmission was deferred

02 LCAR Loss of Carrier

01 RTRY Transmit aborted after 16 attempts

R/W

4 XMTRC 80 EXDEF Excessive Defer

40 –

20 –

10 –

0F XMTRC [3:0] 4-bit Transmit Retry Count

5 RCVFC Receive Frame Control

08 LLRCV Low Latency Receive

04 M/R Match/Reject for external address detection

01 ASTRPRCV Auto Strip Receive–Strips pad and FCS from

received frames

R/W

6 RCVFS Receive Frame Status–4 bytes–r ead in 4 read cycles

RFS0 RCVCNT [7:0] Receive Message Byte Count

RFS1 RCVSTS, RCVCNT [11:8]–Receive Status & Receive Msg Byte Count MSBs

80 OFLO Receive FIFO Overflow

40 CLSN Collision during reception

20 FRAM Framing Error

10 FCS FCS (CRC) error

0F RCVCNT [11:8] 4 MSBs of Receive Msg. Byte Count

RFS2 RNTPC [7:0] Runt Packet Count (since last successful reception)

RFS3 RCVCC [7:0] Receive Collision Count (since last successful

reception)

7 FIFOFC FIFO Frame Count

F0 RCVFC Receive Frame Count–# of RCV fram es in FIFO

0F XMTFC Transmit Frame Count–# of XMT frames in FIFO

8 IR Interrupt Register

80 JAB Jabber Error–Excessive transmit during (20–150ms)

40 BABL Babble Error➔ 1518 bytes transmitted

20 CERR Collision Error–No SQE Test Message

10 RCVCCO Receive Collision Count Overflow–Red Add 27 overflow

08 RNTPCO Runt Packet Count Overflow–Reg Addr 26 overflow

04 MPCO Missed Packet Count Overflow–Reg Addr 24 overflow

02 RCVINT Receive Interrupt–Host has read last byte of packet

01 XMTINT Transmit Interrupt–Transmission is complete

9 IMR Interrupt Mask Register

80 JABM Jabber Error Mask

40 BABLM Babble Error Mask

20 CERRM Collision Error Mask

10 RCVCCOM Receive Collision Count Overflow Mask

08 RNTPCOM Runt Packet Count Overflow Mask

04 MPCOM Missed Packet Count Overflow Mask

02 RCVINTM Receive Interrupt Mask

01 XMTINTM Transmit Interrupt Mask

R/W

10 PR Poll Register

80 XMTSV Transmit Status Valid

40 TDTREQ Transmit Data Transfer Request

20 RDTREQ Receive Data Transfer Request

11 BIUCC Bus Interfac e Unit Confi guration Co ntro l

80 –

40 BSWP Byte Swap

30 XMTSP–Transmit Start Point (2 bits)

00 Transmit after 4 bytes have been loaded

01 Transmit after 16 bytes have been loaded

10 Transmit after 64 bytes have been loaded

11 Transmit after 112 bytes have been loaded

01 SWRST Software Reset

R/W

Addr Mnemonic Contents R/W

Programmer’s Register Model (continued)

Addr Mnemonic Contents R/W

12 FIFOCC FIFO Conf iguration Control

C0 XMTFW Transmit FIFO Watermark (2 bits)

00 Assert TDTREQ after 8 write cycles can be made

01 Assert TDTREQ after 16 write cycles can be made

10 Assert TDTREQ after 32 write cycles can be made

11 XX

30 RCVFW Receive FIFO Watermark (2 bits)

00 Assert RDTREQ after 16 bytes are present

01 Assert RDTREQ after 32 bytes are present

10 Assert RDTREQ after 64 bytes are present

11 XX

08 XMTFWU Transmit FIFO Watermark Update–loads XMTFW bits

04 RCVFWU Receive FIFO Watermark Update–loads

RCVFW bits

02 XMBRST Select Transmit Burst mode

01 RCVBRST Select Receive Burst mode

R/W

13 MACCC Media Ac cess Control (MAC) Confi guration C ontrol

80 PROM Promiscuous mode

40 DXMT2PD Disable Transmit Two Part Deferral

20 EMBA Enable Modified Back-off Algorithm

10 –

08 DRCVPA Disable Receive Physical Address

04 DRCVBC Disable Receive Broadcast

02 ENXMT Enable Transmit

01 ENRCV Enable Receive

R/W

14 PLSCC Physical Layer Signalling (PLS) Configuration Control

08 XMTSEL Transmit Mode Select: 1➔ DO± =1 during IDLE

06 PORTSEL [1:0]–Port Select (2 bits)

00 AUI selected

01 10BASE-T selected

10 DAI port selected

11 GPSI selected

01 ENPLSIO Enable Status

R/W

Programmer’s Register Model (continued)

Addr Mnemonic Contents R/W

15 PHYCC

Physical Layer (PHY) Configuration Control

80 LNKFL Link Fail–Reports 10BASE-T receive inactivity

40 DLNKTST Disable Link Te st–Force 10BASE–T port into Link Pass

20 REVPOL Reversed Polarity–Reports 10BASE-T receiver wiring error

10 DAPC Disable Auto Polarity Correction–Detection r emains active

08 LRT Low Receive Threshold–Extended distance capability

04 ASEL Auto Select–Select 10BASE-T port when active, otherwise

AUI

02 RW AKE Remote W a ke–10BASE-T, AUI and EADI features active du ring

sleep

01 A WAKE Auto Wake–10BASE-T rece ive and LNKST active during sleep

R/W

16 CHIPID Chip Identification Register LSB–CHIPID [7:0] RO

17 CHIPID Chip Identification Register MSB–CHIPID [15:8] RO

18 IAC Internal Address Configuration

80 ADDRCHG Address Change–Write to PHYADDR or LOGADDR after ENRCV

40 –

20 –

10 –

08 –

04 –

04 PHYADDR Reset Physical Address pointer

02 LOGADDR Reset Logical Address pointer

01 –

R/W

19 –Reserved R/W as 0

20 LADRF Logic al Addre ss Filte r–8 byt e s–8 reads or writes–LS Byte first R/W as 0

21 PADR Physical 6 bytes–6 reads or writes–LS Byte

first R/W as 0

22 –Reserved R/W as 0

23 –Reserved R/W as 0

24 MPC Missed Pac ket Cou nter–Number of receive packets missed R/W as 0

25 –Reserved R/W as 0

26 RNTPC Runt Packet Count–Number of runt packets addressed to this node R/W as 0

27 RCVCC Re ceive Collision Count–Number of receive collision frames on network R/W as 0

28 –Reserved R/W as 0

Missing Table Title?

SYSTEM APPLICATIONS

Host System Examples

Motherboard DMA Controller

The block diagram shows the MACE device interfacing

to a 8237 type DMA controller. T wo external latches are

used to provide a 24 bit address capability. The first

latch st ores the address bits A [1 5:8], which the 8237

will output on the data line DB [7:0], while the signal

ADSTB is active. T he second latc h is used as a page

8237 from 16–bit to 24–bit. This latch must be pro-

grammed by the system using an I/0 command to gen-

erate the signal LATCHHIGHADR.

The MACE device uses two of the four DMA channels.

One is dedicated to fill the T ransmit FIFO and the other

to empty the Receive FIFO. Both DMA channels

should be programmed in the following mode:

—Command Register:

Memory to memory disabled

DREQ sense acti ve hig h

DACK sense active low

Normal timing

Late Write

Note:

This is the same configuration as used in the IBM PC.

The 8237 and the MACE device run synchronous to

the same S CLK. The 8237 is programme d to execute

a transfe r in three clock cy cles This r equires an ex tra

wait state in the MACE dev ice during FIF O accesses .

A system not using the same configuration as in the

IBM PC can minimize the bus bandwidth required by

the MACE device by programming the DMA controller

in the compressed timing mode.

Care must be taken with respect to the number of

transfers within a burst. The 8237 will drive the signal

EOP low every time the internal counter reaches the

zero. The MACE device however only expects EOF as-

serted on the last byte/word of a packet. This means,

that the word counter of the 8237 should be initially

loaded with the number of bytes/words in the whole

packet. If the application requires that the packet will be

constructed from several buffers at transmit time, some

extra logic is required to suppress the assertion of EOF

at the end of all but the last buffer transferred by the

DMA con troller. Also n ote that th e DMA co ntroller ca n

only handle either bytes or words at any time. It re-

quires sp ecial han dl ing if a packe t is tr an sfe rred to th e

MACE device Transmit FIFO in word qu antities and it

ends in an odd byt e.

The 8237 requires an extra clock cycle to update the

external address latch every 256 transfer cycles. This

example assumes that an update of the external

address latch occurs only at the beginning of the

block transfer.

Addr Mnemonic Contents R/W

29 UTR User Test Register

80 RTRE

40 RTRD

20 RPA

10 FCOLL

08 RCVFCSE

06 LOOP

Reserved Test Register Enable–must be 0

Reserved Test Register Disable

Runt Packet Accept

Force Collision

Receive FCS Enable

Loopback control (2 bits)

No loopback

External loopback

Internal loopback, excludes MENDEC

Internal loopback, includes MENDEC

–

R/W

30 –Reserved R/W as 0

31 –Reserved R/W as 0

D[7:0]

Q[7:0]

SCLK

DREQ0

DREQ1

EOP

DACK0

DACK1

ADSTB

DB[7:0]

A[7:0]

8237

D[7:0]

Q[7:0]

’373

D[7:0]

’373

SCLK

RDTREQ

TDTREQ

EOF

FDSAm79C940

CLK

IOW

CSMACE

LATCHHIGHADR

D[15:0]

A[23:0]

DBUS[15:0]

ADD[4:0]

VDD

16235D-11

R/W

System Interface - Motherboard DMA Example

PC/AT Ethernet Adapter Card

SD7-SD0

SD15-SD8

AUI

Am79C940

TP RJ45

IEEE

Address

PROM

GPSI/DAI

Header

Remote

Boot

PROM

CAM

D7-D0

D15-D8

DB15

SA19-SA0

16235D-12

System Interface - Simple PC/AT Ethernet Adapter Card Example

NETWORK INTERFACES

External Address Detection Interface

(EADI)

The External Address Detection Int erface can be used

to impleme nt alter native add ress reco gnitio n sche mes

outside the MACE device, to complement the physical,

logical and promiscuous detection supported internally .

The address matching, and the support logic neces-

sary to capture and present the relevant data to the ex-

ternal table of address is application specific. Note that

since the en tire 8 02.3 pac ket a fter SFD is made av ail-

able, recognition is not limited to the destination ad-

dress and/or type fields (Ethernet only).

Inter-networking protocol recognition can be performed

on specific header or LLC information fields.

QH’

74LS595

74LS245

SER

SRCK

RCK

QH’

QH-A

A8-A1

B8-B1

EADI

Pins

SER

SRCK

RCK

A8-A1

B8-B1

SRD

SRDCLK

SF/BD

Logic

Block

EAM/R

Am99C10

D15-D0

MTCH

CAM

Programming

Interface

Databus

16235D-13

QH-A

EADI Feature - Simple External CAM Interface

Attachment Unit Interface (AUI)

The AUI can drive up to 50 m of standard drop cable to

allow the transceiver to be remotely located, as is typi-

cally t he case in IE EE 803.3 10B ASE5 or thick Ether-

net® installations. For a locally mounted transceiver,

such as 802.3 10BASE2 or Cheape rnet interface, the

isolati on transformer requirements between the trans-

ceiver and the MACE device can be reduced.

When used with the Am79C98 TPEX (Twisted Pair

Ethernet T ransceiver), the isolation requirements of the

AUI are completely removed providing that the trans-

ceiver is mounted locally. For remote location of the

TPEX via an AUI dro p cab le , the is ola tio n re qui rement

is necessary to meet IEEE 802.3 specifications for fault

toleranc e and reco ve ry.

CPU Memory

Power

Supply

Loc al Bus

10BASE5/Ethernet DTE AUI

Cable MAU

Tap

Am7996

Transceiver

Ethernet

Coax

16235D-14

Am79C940

AUI-10BASE5/Ethernet Example

RG58

BNC “T”

System

CPU Local

Memory

10BASE2/Cheapernet

Cheapernet

Coax

Power

Supply

Am7996

Transceiver

Am79C940

DMA

Engine I/O Bus

16235D-15

AUI-10BASE2/Cheapernet Example

System

CPU

Other Slave

I/O Device(s)

i.e . SCSI Am79C9416

MACE

10BASE-T/Twisted-Pair Ethernet

Am79C940

I/O

Processor Slave Peripheral Bus

RJ45

Unshielded

Twisted-Pair

16235D-16

10BASE-T/Unshielded Twisted-Pair Interface

XMT

Filter

RCV

Filter

ANLG GND

ANLG +5 V

AVSSAVDD

0.1 µF

Filter &

Transformer

Module

Note 1

Note 2

Am79C940

TXP+

TXD-

TXP-

TXD+

RXD+

RXD-

0.1 µF

LNKST LINK OK DGTL +5 V

RXPOL RX POL OK

1.21KΩ

100Ω

61.9 Ω

422 Ω

61.9 Ω

422 Ω

DO-

DI+

DI-

CI+

CI-

DO+

Pulse

Transformer

Note 3

40.2Ω

Optional ANLG GND

0.1 µF0.1 µF

DXCVR Optional Disable

10BASE2 DC/DC

Convertor

10BASE2 MAU

COAX

TAP

(BNC)

See Am7996 Data Sheet

for component and

implementation details

Active High

Active Low

RJ45

Connector

40.2 Ω

40.2 Ω40.2 Ω

TD+

TD-

RD+

RD-

16235D-17

Am7996

Notes:

1. Compatible filter modules, with a brief description of package type and features are included in the following section.

2. The resistor values are recommended for general purpose use and should allow compliance to the 10BASE-T specification for template

fit and jitter performance. However, the overall performance of the transmitter is also affected by the transmit filter configuration. All

resistors are ± 1%.

3. Compatible AUI transformer modules, with a brief description of package type and features are included in the following section.

4. Active High indicates the external convertor should be turned off. The Disable Transceiver (DXCVR) output is used to indicate the active

network port. A high level indicates the 10BASE-T port is selected and the AUI port is disabled. A low level indicates the AUI port is

selected and the Twisted Pair interface is disabled.

Active Low: indicates the external converter should be turned off. The LNKST output can be used to indicate the active network

port. A high level indicates the 10BASE-T port is in the Link Fai l state, and the external convertor should be on. A low level indicates the

10BASE-T port is in the Link Pass state, and the external convertor should be off.

1:1

Note 4

10BASE–T and 10BASE2 Configuration of Am79C940

XMT

Filter

RCV

Filter

ANLG GND

ANLG +5 V

AVSSAVDD

0.1µF

Filter &

Transformer

Module

Note 1

Note 2

Am79C940

TXP+

TXD-

TXP-

TXD+

RXD+

RXD-

DGTL GND

0.1µF

LNKST LINK OK DGTL +5 V

RXPOL RX POL OK

1.21KΩ

100Ω

61.9Ω

422Ω

61.9Ω

422Ω

DI+

DI-

CI+

CI-

DO+

Pulse

Transformer

Note 3

40.2Ω

Optional ANLG GND

0.1µF0.1µF

AUI

Connector

RJ45

Connector

40.2Ω

40.2Ω40.2Ω

TD+

TD-

RD+

RD-

16235D-18

Notes:

1. Compatible filter mod ules, w ith a brief d escription o f packag e type and features a re incl uded in th e following sec-

tion.

2. The resistor values are recommended for general purpose use and should allow compliance to the 10BASE-T

specification for template fit and jitter performance. However, the overall performance of the transmitter is also

affected by the transmit filter configuration. All resistors are ± 1%.

3. Compatible AUI transformer modules, with a brief description of package type and features are included in the

following section.

1:1

10BASE-T and AUI Implementation of Am79C940

DO–

MACE Compatible 10BASE-T Filters

and Transformers

The table be low provides a sample list of MA CE com-

patible 10BASE-T filter and transformer modules

available from various vendors. Contact the respective

manufacturer for a complete and updated listing of

components.

MACE Compatible AUI Isolation

Transformers

The table be low provides a sample list of MA CE com-

patible AUI isolation transformers available from

vendors. Contact the respective manufacturer for a

complete and updated listing of components .

Manufacturer Part # Package

Filters

and

Transformers

Filters

Transformers

and Choke

Filters

Transformers

Dual Chokes

Filters

Transformers

Resistors

Dual Chokes

Bel Fuse A556-2006-DE 16–pin 0.3 DIL ✓

Bel Fuse 0556-2006-00 14–pin SIP ✓

Bel Fuse 0556-2006-01 14–pin SIP ✓

Bel Fuse 0556-6392-00 16–pin 0.5 DIL ✓

Halo Electronics FD02-101G 16–pin 0.3 DIL ✓

Halo Electronics FD12-101G 16–pin 0.3 DIL ✓

Halo Electronics FD22-101G 16–pin 0.3 DIL ✓

PCA Electronics EPA1990A 16–pin 0.3 DIL ✓

PCA Electronics EPA2013D 16–pin 0.3 DIL ✓

PCA Electronics EPA2162 16–pin 0.3 SIP ✓

Pulse Engineering PE-65421 16–pin 0.3 DIL ✓

Pulse Engineering PE-65434 16–pin 0.3 SIL ✓

Pulse Engineering PE-65445 16–pin 0.3 DIL ✓

Pulse Engineering PE-65467 12–pin 0.5 SMT ✓

Valor Electronics PT3877 16–pin 0.3 DIL ✓

Valor Electronics FL1043 16–pin 0.3 DIL ✓

Manufacturer Part # Package Description

Bel Fuse A553-0506-AB 16–pin 0.3 DIL 50 µH

Bel Fuse S553-0756-AE 16–pin 0.3 SMD 75 µH

Halo Electronics TD01-0756K 16–pin 0.3 DIL 75 µH

Halo Elec tro nic s TG 01 - 075 6W 16–pin 0.3 SMD 75 µH

PCA Electronic s EP9531-4 16–pin 0.3 DIL 50 µH

Pulse Engineering PE64106 16–pin 0.3 DIL 50 µH

Pulse Engineering PE65723 16–pin 0.3 S MT 75 µH

Val o r Electronics LT6032 16–pin 0.3 DIL 75 µH

Valor Electronics ST7 032 16 –pin 0.3 SMD 75 µH

MACE Compatible DC/DC Converters

The table be low provides a sample list of MA CE com-

patible DC/DC converters available from various ven-

dors. Contact the respective manufacturer for a

complete and updated listing of components.

MANUFACTURER CONTACT

INFORMATION

Contact the following companies for further information

on their products .

Manufacturer Part # Package Voltage Remote On/Off

Halo Electronics DCU0-0509D 24–pin DIP 5/-9 No

Halo Electronics DCU0-0509E 24–pin DIP 5/-9 Yes

PCA Electronics EPC1007P 24–pin DIP 5/-9 No

PCA Electronics EPC1054P 24–pin DIP 5/-9 Yes

PCA Electronics EPC1078 24–pin DIP 5/-9 Yes

Valor Electronics PM7202 24–pin DIP 5/-9 N o

Valor Electronics PM7222 24–pin DIP 5/-9 Yes

Company US. and Domestic Asia Europe

Bel Fuse Phone:

FAX: (201) 432-0463

(201) 432-9542 852-328-5515

852-352-3706 33-1-69410402

33-1-69413320

Halo Elec tron ic s Phone:

FAX: (415) 969-7313

(415) 367-7158 65-285-1566

65-284-9466

PCA Electronic s

(HPC in Hong Kong) Phone:

FAX: (818) 892-0761

(818) 894-5791 852-553-0165

852-873-1550 33-1-44894800

33-1-42051579

Pulse Engineering Phone:

FAX: (619) 674-8100

(619) 675-8262 852-425-1651

852-480-5974 353-093-24107

353-093-24459

Valor Electronics Phone:

FAX: (619) 537-2500

(619) 537-2525 852-513-8210

852-513-8214 49-89-6923122

49-89-6926542

ABSOLUTE MAXIMUM RATINGS

Storage Temperature . . . . . . . . . . . . -65°C to +150°C

Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . .

Under Bias . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

Supply Voltage to AVSS

or DVss (AVDD, DVDD). . . . . . . . . . .-0.3 V to +6.0 V

Stresses above those listed under Absolute Maximum Rat-

ings may cause permanent device failure. Functionality at or

above these limits is not implied. Exposure to Absolute Max-

imum Rati ngs for extende d periods may affect device reli abil-

ity. Programming conditions may differ.

OPERATING RANGES

Commercial (C) Devices

Ambient Tempera t ure (TA) . . . . . . . . . . .0°C to +70°C

Industrial (I) Devices

Ambient Tempera t ure (TA) . . . . . . . . .–40°C to +85°C

VCC Supply Voltages

. . . . . . . . . . . . . . . . . . . . . . (AVDD, DVDD) 5 V ±5%

All inputs within the range: . . AVDD – 0.5 V ≤ Vin ≤

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .AVSS + 0.5 V, or

. . . . . . . . . . . . . . . . . . . . . . . . . DVDD – 0.5 V ≤ Vin ≤

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DVSS + 0.5 V

Operati ng ranges defin e those limits bet ween which the func-

tionality of the device is guaranteed.

DC CHARACTERISTICS (Unless otherwise note d , parametric values are the same

between Commercial devices and Industrial devices.)

Parameter

Symbol Parameter Description Test Conditions Min Max Unit

VIL Input LOW Voltage 0.8 V

VIH Input HIGH Voltage 2.0 V

VILX XTAL1 Input LOW Voltage

(External C lock Signal) VSS = 0.0 V –0.5 0.8 V

VIHX XTAL1 Input HIGH Voltage

(External C lock Signal) VSS = 0.0 V VDD–

0.8 VDD+

0.5 V

VOL Output LOW Voltage IOL = 3.2 mA 0.45 V

VOH Output HIGH Voltage IOH = -0.4 mA (Note 1) 2.4 V

IIL1 Input Leakage Current VDD = 5 V, VIN = 0 V

(Note 2) –10 10 µA

IIL2 Input Leakage Current VDD = 5 V, VIN = 0 V

(Note 2) –200 200 µA

IIH Input Leakage Current VDD = 5 V, VIN = 2.7 V

(Note 3) –100 µA

IIAXD Input Current at DI+

and DI––1 V < VIN < AVDD + 0.5 V –500 +500 µA

IIAXC Input Current at CI+

and CI––1 V < VIN < AVDD + 0.5 V –500 +500 µA

IILXN XTAL1 Input LOW Current

during norma l operation VIN = 0 V

SLEEP = HIGH –92

(Note 9) µA

IIHXN XTAL1 Input HIGH Current

during norma l operation VIN = 5.5 V

SLEEP = HIGH 92

(Note 10) µA

IILXS XTAL1 Input LOW Current

during Sleep VIN = 0 V

SLEEP = LOW <10 µA

IIHXS XTAL1 Input HIGH Current

during Sleep VIN = 5.5 V

SLEEP = LOW 410 µA

IOZ Output Leakage Current 0.4 V < VOUT < VDD

(Note 4) –10 10 µA

VAOD Differential Output Voltage

|(DO+)–(DO–)| RL = 78 Ω630 1200 mV

VAODOFF Transmit Differential Output

Idle Voltage RL = 78 Ω (Note 5) –40 +40 mV

DC CHARACTERISTICS (Continued)

Parameter

Symbol Parameter Description Test Conditions Min Max Unit

IAODOFF Transmit Differential

Output Idle Current RL = 78 Ω–1+1mA

VAOCM DO± Common Mode

Output Voltage RL = 78 Ω2.5 AVDD V

VODIDO± Differential Output

Voltage Imbalance RL = 78 Ω (Note 6) –25 25 mV

VATH Receive Data Differential

Input Threshold RL = 78 Ω (Note 6) –35 35 mV

VASQ DI± and CI± Differential

Input Threshold Squelch RL = 78 Ω (Note 6) –160 –275 mV

VIRDVD DI± and CI± Differential

Mode Input Voltage Range 1.5 V

VICM DI± and CI± Input Bias

Voltage IIN= 0 mA AVDD –3.0 AVDD –0.8 V

VOPD DI± Undershoot Voltage at Zero

Differ ential on Tra nsmit Return

to Zero (ETD)

(Note 5) –100 mV

IDD Power Supply Current SCLK = 25 MHz

XTAL1 = 20 MHz 75 mA

IDDSLEEP Power Supply Current SLEEP Asserted, AWAKE = 0

RWAKE = 1 (Note 7) 100 µA

IDDSLEEP Power Supply Current SLEEP Asserted, AWAKE = 1

RWAKE = 0 (Note 7) 10 mA

IDDSLEEP Power Supply Current SLEEP Asserted, AWAKE = 0

RWAKE = 1 (Note 7) 20 mA

Twisted Pair Interfac e

IIRXD Input Current at RXD±AVSS< VIN < AVDD –500 500 µA

RRXD RXD± Differential Input

Resistance (Note 8) 10 KΩ

VTIVB RXD±, RXD– Open Circuit

Input Voltage (Bias) IIN= 0 mA AVDD –3.0 AVDD –1.5 V

VTIDV Differential Mode Input

Voltage Range (RXD±)AVDD= +5 V –3.1 +3.1 V

VTSQ+ RXD Positive Squelch

Threshold (Peak) Sinusoid

5 MHz ≤ f ≤10 MHz 300 520 mV

VTSQ–RXD Negative Squelch

Threshold (Peak) Sinusoid

5 MHz ≤ f ≤10 MHz –520 –300 mV

VTHS+ RXD Post-Squelch

Positive Threshold (Peak) Sinusoid

5 MHz ≤ f ≤10 MHz 150 293 mV

VTHS–RXD Post-Squelch

Negative Threshold) (Peak) Sinusoid

5 MHz ≤ f ≤10 MHz –293 –150 mV

VLTSQ+ RXD Positive Squelch

Threshold (Peak) LRT = LOW 180 312 mV

VLTSQ–RXD Negative Squelch

Threshold (Peak) LRT = LOW –312 –180 mV

VLTHS+ RXD Post-Squelch Positive

Threshold (Peak) LRT = LOW 90 156 mV

DC CHARACTERISTICS (Continued)

Notes:

1. VOH does not apply to open-drain ou tput pins.

2. IIL1 and IIL2 applies to all input only pins except DI±, CI±, and XTAL1.

IIL1 = ADD4–0, BE1–0, CS, EAM/R, FDS, RESET, RXDAT, R/W, SCLK.

IIL2 =TC, TDI, TCK, TMS.

3. Specified for input only pins with internal pull-ups: TC, TDI, TCK, TMS.

4. IOZ applies to all three-state output pins and bi-directional pins.

5. Test not implemented to data sheet specification.

6. Tested, but to values in excess of limits. Test accuracy not sufficient to allow screening guard bands.

7. During the activation of SLEEP:

–The following pins are placed in a high impedance state: SRD, SF/BD, TXDAT, DXCVR, DTV, TDTREQ, RDTREQ, NTR

and TDO.

–The following I/O pins are placed in a high impedance mode and have their internal TTL level translators disabled:

DBUS15–0, EOF, SRDCLK, RXCRS, RXDAT, CLSN, TXEN, STDCLK and TXDAT+.

–The following input pin has its internal pull-up and TTL level translator disabled: TC.

–The following input pins have their internal TTL level translators disabled and do not have internal pull-ups: CS, FDS,

R/W, ADD4-0, SCLK, BE0, BE1 and EAM/R.

–The following pins are pulled low: XTAL1 (XTAL2 feedback is cut off from XTAL1), TXD+, TXD–, TXP+, T XP–, D O+

and DO.

–The following pins have their input voltage bias disabled: DI+, DI, CI+ and CI.

–AWAKE and RWAKE are reset to zero. IDDSLEEP, with either AWAKE set or RWAKE set, will be much higher and its

value remains to be determined.

8. Parameter not tested.

9. For indust rial temperature version, Max value is –150 µA.

10. For industrial temperature versio n, Max value is +150 µA.

Parameter

Symbol Parameter Description Test Conditions Min Max Unit

VLTHS–RXD Post-Squelch

Negative Threshold (Peak) LRT = LOW –156 –90 mV

VRXDTH RXD Switching Threshold (Note 4) –35 35 mV

VTXH TXD± and TXD± Output

HIGH Voltage DVSS = 0V DVDD –0.6 DVDD V

VTXL TXD± and TXD± Output

LOW Voltage DVDD = +5V DVSS DVSS + 0. 6 V

VTXI TXD± and TXD± Differential

Output Voltage Imbalance –40 +40 mV

VTXOFF TXD± and TXD± Idle Output

Voltage DVDD = +5V 40 mV

RTX TXD± Differential Driver Output

Impedance (Note 8) 40 Ω

TXD± Differential Driver Output

Impedance (Note 8) 80 Ω

AC CHARACTERISTICS (Unless otherwise note d , parametric values are the same

between Commercial devices and Industrial devices.)

Notes:

1. The following BIU timing assumes that EDSEL = 1. Therefo re, these parameters are specified with respect to the falling edge

of SCLK (SCLK↓). If EDSEL = 0, the same parameters apply but should be referenced to the rising edge of SCLK ↑).

2. T ested with CL set at 100 pF an d derated to support th e Indicated di stributed capa citive Load. See the BIU out put valid dela y

vs. Load Chart.

3. Guaranteed by design–not tested.

4. tDATD is defined as the time required for outputs to turn high impedence and is not referred to as output voltage lead.

No. Parameter

Symbol Parameter Description Test Conditions Min (ns) Max (ns)

Clock and Reset Timing

SCLK SCLK period 40 1000

SCLKL SCLK LOW pulse width 0.4*tSCLK 0.6*tSCLK

SCLKH SCLK HIGH pulse width 0.4*tSCLK 0.6*tSCLK

SCLKR SCLK rise time 5

SCLKF SCLK fall time 5

RST RESET pulse width 15*tSCLK

BT Network Bit Time (BT)=2*tX1 or tSTDC 99 101

Internal MENDEC Clock Timing

X1 XTAL1 period 49.995 50.005

11 tX1H XTAL1 HIGH pulse width 20

12 tX1L XTAL1 LOW pulse width 20

13 tX1R XTAL1 rise time 5

14 tX1F XTAL1 fall time 5

BIU TIMING (Note 1)

31 tADDS Address valid setup to SCLK↓9

32 tADDH Address valid hold after SCLK↓2

1. 33 tSLVS CS or FDS and TC, BE1–0,

R/W setup to SCLK↓9

34 tSLVH CS or FDS and TC, BE1–0,

R/W hold after SCLK↓2

35 tDATD Data out valid delay from SCLK↓CL = 100 pF (Note 2) 32

36 tDATH Data out valid hold from SCLK↓6

37 tDTVD DTV valid delay from SCLK↓CL = 100 pF (Note 2) 32

38 tDTVH DTV valid hold after SCLK↓6

39 tEOFD EOF valid delay from SCLK↓CL = 100 pF (Note 2) 32

40 tEOFH EOF output valid hold after SCLK↓6

41 tCSIS CS inactive prior to SCLK↓9

42 tEOFS EOF input valid setup to SCLK↓9

43 tEOFH EOF input valid hold after SCLK↓2

44 tRDTD RDTREQ valid delay from SCLK↓CL = 100 pF (Note 2) 32

45 tRDTH RDTREQ input valid hold after SCLK↓6

46 tTDTD TDTREQ valid delay from SCLK↓CL = 100 pF (Note 2) 32

47 tTDTH TDTREQ input valid hold after SCLK↓6

48 tDATS Data in valid setup to SCLK↓9

49 tDATIH Data in valid setup after SCLK↓2

50 tDATE Data output enable delay from SCLK↓ (Note

3) 0

51 tDATD Data output disable delay from SCLK↓ (Note

3, 4) 25

AC CHARACTERISTICS (continued)

No. Parameter

Symbol Parameter Description Test Conditions Min (ns) Max (ns)

AUI Timing

53 tDOTD XTAL1 (externall y driv en) to DO± ουτπυτ 100

54 tDOTR DO± rise time (10% to 90%) 2.5 5.0

55 tDOTF DO± fall time (10% to 90%) 2.5 5.0

56 tDOETM DO± rise and fall mismatch 1

57 tDOETD DO± End of Transmit Delimiter 200 375

58 tPWRDI DI± pulse width to reject |input| > |VASQ|15

59 tPWODI DI± pulse width to turn on internal DI carrier

sense |input| > |VASQ|45

60 tPWMDI DI± pulse width to main tain intern al DI carrier

sense on |input| > |VASQ| 45 136

61 tPWKDI DI± pulse width to turn internal DI carrier

sense off |input| > |VASQ|200

62 tPWRCI CI± pulse width to reject |input| > |VASQ|10

63 tPWOCI CI± pulse width to turn on in ternal SQE se nse |input| > |VASQ|26

64 tPWMCI CI± pulse width to maintain internal SQE

sense on |input| > |VASQ|2690

65 tPWKCI CI± pulse width to turn inte rnal SQE sense of f |inp ut| > |VASQ|160

66 tSQED CI± SQE Test delay from O± inactive |input| > |VASQ|

67 tSQEL CI± SQE Test length |input| > |VASQ|

79 tCLSHI CLSN high time tSTDC + 30

80 tTXH TXEN or DO± hold time from CLSN↑|input| > |VASQ| 32*tSTDC 96*tSTDC

DAI Port Timing

70 tTXEND STDCLK↑ delay to TXEN ↓CL = 50 pF 70

72 tTXDD STDCLK↑ delay to TXDAT± change CL = 50 pF 70

80 tTXH TXEN or TXD AT± hold time from CLSN↑32*tSTDC 96*tSTDC

95 tDOTF Mi smatc h in STDCLK ≠ to TXEN↓ and

TXDAT± change 15

96 tTXDTR TXDAT± rise time See Note 1 5

97 tTXDTF TXDAT± fall time See Note 1 5

98 tTXDTM TXDAT± rise and fall mismatch See Not e 1 1

99 tTXENETD TXEN End of Transmit Delimiter 250 350

100 tFRXDD First RXDAT↓ delay to RXCRS↑100

101 tLRXDD Last RXDAT ≠ delay to RXCRS↓120

102 tCRSCLSD RXCRS↑ delay to CLSN↑ (TXEN = 0) 100

AC CHARACTERISTICS (continued)

Note:

1. Not tested but data available upon request.

No. Parameter

Symbol Parameter Description Test Conditions Min (ns) Max (ns)

GPSI Clock Timing

17 tSTDC STDCLK period 99 101

18 tSTDCL STDCLK low pulse width See Note 1 45

19 tSTDCH STDCLK high pulse width 45

20 tSTDCR STDCLK rise time See Note 1 5

21 tSTDCF STDCLK fall time See Note 1 5

22 tSRDC SRDCLK period 85 115

23 tSRDCH SRDCLK HIGH pulse width 38

24 tSRDCL SRDCLK LOW pulse width 38

25 tSRDCR SRDCLK rise time See Note 1 5

26 tSRDCF SRDCLK fall time See Note 1 5

GPSI Timing

70 tTXEND STDCLK↑ delay to TXEN↑(CL = 50 pF) 70

71 tTXENH TXEN hold time from STDCLK↑(CL = 50 pF) 5

72 tTXDD STDCLK↑ delay to TXDAT+ change (CL = 50 pF) 70

73 tTXDH TXDAT+ hold time from STDCLK↑(CL = 50 pF) 5

74 tRXDR RXDAT rise time See Note 1 8

75 tRXDF RXDAT fall time See Note 1 8

76 tRXDH RXDAT hold time (SRDCLK↑ to

RXDAT change) 25

77 tRXDS RXDAT setup time (RXDAT stable

to SRDCLK↑)0

78 tCRSL RXCRS low time tSTDC + 20

79 tCLSHI CLSN high time tSTDC + 30

80 tTXH TXEN or TXDAT± hold time from

CLSN↑32*tSTDC 96*tSTDC

81 tCRSH RXCRS hold time from SRDCLK↑0

EADI Feature Timing

85 tDSFBDR SRDCLK↓ delay to SF/BD↑20

86 tDSFBDF SRDCLK↓ delay to SF/BD↑20

87 tEAMRIS EAM/R invalid setup prior to

SRDCLK↓ after SFD –150

88 tEAMS

EAM setup to SRDCLK↓ at bit 6 of

Source Address byte 1 (match

packet) 0

89 tEAMRL EAM/R low time 200

90 tSFBDHIH SF/BD high hold from last

SRDCLK↓100

91 tEARS

EAR setup SRDCLK↓ at bit 6 of

message byte 64

(reject normal packet) 0

AC CHARACTERISTICS (continued)

Note:

1. Not tested but data available upon request.

No. Parameter

Symbol Parameter Description Test Conditions Min Max

IEEE 1149.1 Timing

109 tTCLK TCK Period, 50% duty cycle (+5%) 100

110 tsu1 TMS setup to TCK↑8

111 tsu2 TDI setup to TCK↑5

112 thd1 TMS hold time from TCK↑5

113 thd2 TDI hold time from TCK↑10

114 td1 TCK↓ delay to TDO 30

115 td2 TCK↓ delay to SYSTEM OUTPUT 35

10BASE–T Transmit Timing Min Max

125 tTETD Transmit Start of Idle 250 350

126 tTR Transmitter Rise Time (10% to 90%) 5.5

127 tTF Transmitter Fall Time (90% to 10%) 5.5

128 tTM Transmitter Rise and Fall Time Mi smatch 1

129 tXMTON XMT# Asserted Delay 100

130 tXMTOFF XMT# De-asserted Delay TBD TBD

131 tPERLP Idle Signal Period 8 24

132 tPWLP Idle Link Puls e Wid th (Note 1) 75 120

133 tPWPLP Predistortion Idle Link Pulse Width (Note 1) 45 55

134 tJA Transmit Jabber Activation Time 20 150

135 tJR Transmit Jabber Reset Time 250 750

136 tJREC Transmit Jabber Recovery Time (Minimum

Time Gap Between Transmitted Packets to

Prevent Jabber Activation)

1.0

10BASE–T Receive Timing

140 tPWNRD RXD Pulse Width Not to Turn Off Internal

Carrier S ense VIN > VTHS

(min) 136 –

141 tPWROFF RXD Pulse Width to Turn Off VIN> VTHS

(min) 200

142 tRETD Receive Start of Idle 200

143 tRCVON RCV# Asserted Delay tRON – 50 tRON – 100

144 tRCVOFF RCV# De-asserted Delay TBD TBD

BIU Output Valid Delay vs. Load Chart

KEY TO SWITCHING WAVEFORMS

nom+4

nom

nom-4

nom-8

50 75 100 125 150

BIU Output Valid Delay

from SCLK↓

(ns)

CL (pF) 16235D-19

Must be

Steady

May

Change

from H to L

May

Change

from L to H

Does Not

Apply

Don’t Care,

Any Chan ge

Permitted

Will be

Steady

Will be

Changing

from H to L

Will be

Changing

from L to H

Changing,

State

Unknown

Center

Line is High-

Impedance

“Off” State

WAVEFORM INPUTS OUTPUTS

KS000010

SWITCHING TEST CIRCUITS

VTHRESHOLD

IOL

IOH

Normal and Three-State Outputs

16235D-20

Sense Point

AVDD

DO+

154 Ω

100 pF

DO-

AVSS

52.3 Ω

Test Point

16235D-21

AUI DO Switching Test Circuit

DVDD

TXD+

294 Ω

100 pF

TXD-

DVSS

294 Ω

Test Point

Includes Test

Jig Capacitance

16235D-22

TXD Switching Test Circuit

DVDD

TXP+

715 Ω

100 pF

TXP-

DVSS

715 Ω

Test Point

Includes Test

Jig Capa ci tanc e

16235D-23

TXP Outputs Test Circuit

SCLK

4 5

13 14

RESET

XTAL1

Clock and Reset Timing

AC WAVEFORMS

16235D-24

100

SCLK

(EDSEL = 1) S3S2S1S0THTL

DBUS[15:0]

S0 S2S1 S3

ADD[4:0]

R/W

S2S1 S3S0

DTV

EOF

Word N Word N+1 Last Byte

or Word

33 34

36 38

CS or FDS

TC = 1

BE0-1

SCLK

(EDSEL = 0) S3S2S1S0THTL S0 S2S1 S3 S2S1 S3S0 S0

AC WAVEFORMS

Hos t System Interface—2-Cycle Rece ive FIFO/ Reg ister Read Timing

16235D-25

101

DBUS[15:0]

ADD[4:0]

R/W

DTV

EOF

Word N Word N+1 Last Byte

or Word

SCLK

(EDSEL = 1) S3S2S1S0THTL S0 W0S1 S3 S2S1 S3S0 S0W0 W1 W1 S2 W0 W1

BE0-1

TC = 0

CS or FDS

37 40

SCLK

(EDSEL = 0) S3S2S1S0THTL S0 W0S1 S3 S2S1 S3S0 S0W0 W1 W1 S2 W0 W1

AC WAVEFORMS

Host System Interface—3-Cycle Receive FIFO/Register Read Timing

16235D-26

102

SCLK

(EDSEL = 1)

R/W

DTV

EOF

Word N Word N+1 Last Byte

or Word

S3S2S1S0THTL S0 S2S1 S3 S2S1 S3S0 S0

CS or FDS

DBUS15–0

ADD4–0

BE0-1

TC = 1

S3S2S1S0THTL S0 S2S1 S3 S2S1 S3S0 S0

SCLK

(EDSEL = 0)

AC WAVEFORMS

Hos t System Interface—2-Cycle Transmit FIFO/Register Write Timing

16235D-27

103

Word N Word N+1 Last Byte

or Word

S3S2S1S0THTL S0 S2S1 S3 S1S0W1W0 W1W0 S2 S3 S0W1W0SCLK

(EDSEL = 1)

R/W

DTV

EOF

DBUS[15:0]

ADD[4:0]

BE0-1

TC = 0

S3S2S1S0THTL S0 S2S1 S3 S1S0W1W0 W1W0 S2 S3 S0W1W0SCLK

(EDSEL = 0)

AC WAVEFORMS

Host System Interface—3-Cycle Transmit FIFO/Register Write Timing

16235D-28

EOF

RDTREQ

SCLK

(EDSEL = 1) S0 S2S1 S3

S2S1S0 S2S1 S3S0 S0S3S2

Note 1

SCLK

(EDSEL = 0) S0 S2S1 S3

S2S1S0 S2S1 S3S0 S0

S3S2

Note: Onc e t he h os t de tec ts the EOF o utp ut a cti ve from the MAC E d ev ic e (S2 /S3 ed ge ), if n o o ther rec eiv e p ack et exi st s

in the RCVFIFO which meets the assert conditions for RDTREQ, the MACE device will deassert RDTREQ within 4 SCLK

cycles (S0/S1 edge). This is consistent for both 2 or 3 cycle read operations.

16235D-29

Host System Interface–RDTREQ Read Timing

104

SCLK

(EDSEL = 1)

EOF

TDTREQ

Note 1

Note 3Note 2

S3S2S1 S0 S2S1 S3 S2S1 S3S0 S0 S2S1 S3 S0

SCLK

(EDSEL = 0)

AC WAVEFORMS

Notes:

1. TDTREQ will be asserted for two write cycles (4 SCLK cycles) minimum.

2. TDTREQ will deassert 1 SCLK cycle after EOF is detected (S2/S3 edge) .

3. When EOF is written, TDTREQ will go inactive for 1 SCLK cycle minimum.

Host System Interface–TDTREQ Write Timing

16235D-30

XTAL1

STDCLK

TXDAT+

DO+

DO–

DO±

TXEN

(Note 1)

54 55

16235D-31

AUI Transmit Timing–Start of Packet

Note: TXDAT+ is the internal version of the signal, and is shown for clarification only.

105

010

bit (n–2) bit (n–1) bit (n)

XTAL1

STDCLK

TXDAT+

DO+

DO–

DO±

TXEN

(Note 1)

> 200 ns

16235D-32

Note: TXDAT+ is the internal version of the signal, and is shown for clarification only.

AUI Transmit Timing–End of Packet (Last Bit = 0)

bit (n–2) bit (n–1) bit (n)

XTAL1

SRDCLK

TXDAT+

DO+

DO–

DO±

TXEN

(Note 1)

> 250 ns

16235D-33

Note: TXDAT+ is the internal version of the signal, and is shown for clarification only.

AUI Transmit Timing–End of Packet (Last Bit = 1)

106

0 V

100 mV Max

40 mV

DO±

80 Bit Times Max

AUI Transmit Timing—End Transmit Delimiter (ETD) 16235D-34

DI±

RXCRS

IVCO

SRDCLK

SRD

IVCO_ENABLE

(Note 1)

BCC BCB BCC BCB BCC BCC BCB BCC BCB

5 Bit Times Max

(Note 2) (Note 3)

10 10 10

Bit Cell 5Bit Cell 4Bit Cell 3Bit Cell 2Bit Cell 1

VASQ

59 60

16235D-35

Notes:

1. Minimum pulse width>45 ns with amplitude >–1 60 mV.

2. SRD first decoded bit might not be defined until bit time 5.

3. First valid data bit.

4. IVCO and VCO ENABLE are internal signals shown for clarification only.

AUI Receive Timing–Start of Packet

107

DI±

RXCRS

IVCO

SRDCLK

(Note 1)

BCC BCB

Bit Cell (n–1)

BCC BCB

Bit Cell (n)

bit (n–1) bit (n)

(Note 2)

SRD

VASQ

16235D-36

Notes:

1. RXCRS deasserts in less than 3 bit times after last DI± risi ng edge.

2. Start of next packet reception (2 bit times).

3. IVCO is an internal signal shown for clarification only.

AUI Receive Timing–End of Packet (Last Bit = 0)

DI±

RXCRS

IVCO

RDCLK

SRD

(Note 1)

BCC BCB

Bit Cell (n–1)

BCC

Bit Cell (n)

bit (n–1) bit (n)

Notes:

1. RXCRS deassets in less than 3 bit times after last DI± rising edge.

2. IVCO is an internal sign al sh own f or clar ific at ion only.

16235D-37

AUI Receive Timing–End of Packet (Last Bit = 1)

108

DO±

CLSN

CI+

CI-

TXEN

AUI Collision Timing 16235D-38

CLSN = 0

DO±

CI+

CI-

AUI SQE Test Timing 16235D-39

109

TXDAT±

TXDAT-

TXDAT+

TXEN

STDCLK

72 BCB BCB BCB BCB BCB BCB BCB BCB

96 97 99

DAI Port Transmit Timing 16235D-40

100

RXDAT

RXCRS

101

DAI Port Receive Timing 16235D-41

110

TXDAT+

102

CLSN

RXDAT

RXCRS

TXEN

TXDAT-

DAI Port Collision Timing 16235D-42

SRDCLK

SRD SFD BIT

0BIT

1BIT

2BIT

3BIT

4BIT

5BIT

6BIT

7BIT

Destination Address

Byte 1 Destination Address

Byte 2

EAM/R

SF/BD

85 Note 1

16235D-43

EADI Feature Timing–Start of Address

Note: First assertion of EAM/R must occur after bit 2/3 boundary of preamble.

111

SRDCLK

SRD

SF/BD

86 90

Last Byte of Message

EADI Feature–End of Packet Ti ming 16235D-44

SRDCLK

SRD

SF/BD

Source Address

Byte 2

EAM

BIT

0BIT

1BIT

2BIT

3BIT

4BIT

5BIT

6BIT

7BIT

BIT

5BIT

6BIT

Destination Address

Byte 6 Source Address

Byte 1

EADI Feature-Match Timing 16235D-45

112

RDCLK

SRD

SF/BD

Byte 66

(Data Byte 53)

EAR

Byte 64

(Data Byte 51) Byte 65

(Data Byte 52)

BIT

0BIT

1BIT

2BIT

3BIT

4BIT

5BIT

6BIT

7BIT

BIT

5BIT

6BIT

BIT

4BIT

EADI Feature Reject Timing 16235D-46

STDCLK

TXDAT+

TXEN

RXCRS

72 73 20 21

19 18

Note 1

GPSI Transmit Timing

16235D-47

Note: During transmit, the RXCRS input must be asserted (high) and remain active-high after TXEN goes active (high). If

RXCRS is deasserted before TXEN is deasserted, LCAR will be reported (Transmit Frame Status) after the transmission is

completed by the MACE device.

113

77 75

7881

7476

SRDCLK

RXDAT

RXCRS

2324

16235D-48

GPSI Receive Timing

STDCLK

TXDAT+

TXEN

CLSN

16235D-49

GPSI Collision Timing

114

tsu1 thd1 td1

TCK

TMS

TDO

System Output

TDI

tsu2

thd2

td2

16235D-50

IEEE 1149.1 TAP T iming

16235D-51

tXMTOFF

tTF

tTETD

Note:

1. Parameter is internal to the device.

tTF

10BASE-T Transmit Timing

115

RXCRS

RXD±

tRCVOFF

tRCVON

VTSQ+

VTSQ-

16235D-52

10BASE-T Receive Timing

TXD±

CLSN

tCOLOFF

RXD±

tCOLON

16235D-53

10BASE-T Collision Timing

116

TXD+

tPERLP

tPWLP

tPWPLP

TXP+

TXD-

TXP-

16235D-54

10BASE-T Idle Link Test Pulse

RXD±

VTSQ+

VTSQ-

VTHS-

VTHS+

16235D-55

10BASE-T Receive Thresholds (LRT = 0)

RXD±

VLTSQ+

VLTSQ-

VLTHS-

VLTHS+

16235D-56

10BASE-T Receive Thresholds (LRT = 1)

117

PHYSICAL DIMENSIONS*

PL 084

84-Pin Plastic Leaded Chip Carrier (measured in inches)

TOP VIEW

SEATING PLANE

1.185

1.195 1.150

1.156

Pin 1 I.D.

.026

.032 .050 REF

.042

.056

.062

.083

.013

.021

1.000

REF

.007

.013

.165

.180

.090

.130

SIDE VIEW

1.185

1.195

1.150

1.156

1.090

1.130

118

PHYSICAL DIMENSIONS*

PQR100

100-Pin Plastic Quad Flat Pack; Trimmed and Formed (measured in millimeters)

0.22

0.38

13.90

14.10

17.10

17.30

18.85

REF

19.90

20.1023.00

23.40

0.65

BASIC

Pin 1 I.D.

12.35

REF

2.70

2.90 3.35

MAX

0.70

0.90

0.25

MIN

TOP VIEW

SIDE VIEW 17198A

CG 47

7/14/92 SG

80 100

119

PHYSICAL DIMENSIONS

PQR100

100-Pin Plastic Quad Flat Pack with Molded Carrier Ring (measured in millimeters)

Pin 1 I.D.

19.80

20.10

27.87

28.13

31.37

31.63

35.87

36.13

13.80

14.10

25.20

BSC

27.87

28.13

31.37

31.63

35.50

35.90

35.87

36.13

.65 NOM

.65 Typ

.65 Pitch .45 Typ

2.00 4.80

1.80

SIDE VIEW

17198A

CB 48

6/25/92 SG

0.22

0.38

25.15

25.25 22.15

22.25

35.50

35.90

25.15

25.25

22.15

22.25

80 100

TOP VIEW

120

PHYSICAL DIMENSIONS*

PQT080

80-Pin Thin Quad Flat Package (measured in millimeters)

13.80

14.20

11.80

12.20

13.80

14.20

11.80

12.20

1.00 REF.

1.20 MAX

11ϒ

– 13ϒ

11ϒ

– 13ϒ

0.50 BSC

.95

1.05

APPENDIX A

Am79C940 121

Logical Address Filtering

For Ethernet

The purpose of logical (or group or multicast)

ad dresses is to allow a group of nodes in a network to

receive the same message. Each node can maintain a

list of multicast addresses that it will respond to. The

logical address filter mechanism in AMD Ethernet con-

trollers is a hardware aide that reduces the average

amount of host computer time required to determine

whether or not an incoming packet with a multicast

des tination address should be accepted.

The logical address filter hardware is an implementa-

tion of a hash code searching technique commonly

used by software programmers. If the multicast bit in

the destination address of an incoming packet is set,

the hardware maps this address into one of 64 catego-

ries then accepts or rejects the packet depending on

whether or not the bit in the logical address filter regis-

ter corresponding the selected category is set. For

ex ample, if the address maps into category 24, and bit

24 of the logical address filter register is set, the packet

is accepted.

Since there are more than 1014 possible multicast

ad dresses and only 64 categories, this scheme is far

from unambiguous. This means that the software will

still have to c ompare the add re ss of a re ce iv ed p ac ke t

with its li st of ac ceptable multicas t address es to make

the final decision whether to accept or discard the

packet. However, the hardware prevents the software

from having to deal with the vast majority of the

unac ceptable packets.

The efficiency of this sch eme depends on the numb er

of multicast groups that are used on a particular net-

work and the number of groups to which a node

be lon gs. A t one extreme if a no de hap pens to bel ong

to 64 groups that map into 64 different c ategories, th e

hardware will accept all multicast addresses, and all fil-

tering must be don e by softwa re. At the othe r extrem e

(which is closer to a practical network), if multicast

ad dresses are assigned by the local administrator , and

fewer than 65 groups are set up, the addresses can be

assigned so that each address maps into a different

category, and no software filtering will be needed at all.

In the latter case described above, a node can be made

a member of several groups by setting the appropriate

bits in the logical address filter register . The administra-

tor can use the table Mapping of Logical Address to

Fil ter Mask to find a multicast address that maps into a

particu la r add re ss fi lte r bit . F or e xam pl e a ddr es s 000 0

0000 00BB maps i nto bit 15. Ther efore, any node tha t

has bit 15 set in its logical address filter register will

re ceive all packets addressed to 0000 0000 00BB.

(Address es in thi s table are not shown in the st andar d

Ethernet format. In the table the rightmost byte is the

first byte to appear on the network with the least

signif icant bit appearing first).

Driver software that manages a list of multicast

ad dresses can work as follows. First the multicast

ad dress list and the logical address filter must be

ini tialized. Some sort of management function such as

the driver initialization routine passes to the driver a list

of addresses. For each address in the list the driver

uses a subroutine similar to the one listed in the

Am7990 LANCE data sheet to set the appropriate bit in

a software copy of the logical address filter register.

When the complete list of addresses has been

pro cessed, the register is loaded.

Later, when a packet is received, the driver first looks

at the Individual/Group bit of the destination address of

the pack et t o fi nd out whet her or not this i s a m ultic as t

address. If it is, the driver must search the multicast

ad dress list to see if this address is in the list. If it is not

in the list, the packet is discarded.

The bro adcas t ad dr es s, w hic h c on sist s o f all on es is a

special multicast address. Packets addressed to the

broadcast address must be received by all nodes.

Since broadcast packets are usually more common

than other multicast packets, the broadcast address

should be the first address in the multicast address list.

122 Am79C940

MAPPING OF LOGICAL ADDRESS TO FILTER MASK

Byte # Bit # LADRF

Bit Destination

Address Accepted Byte # Bit # LADRF

Bit Destination

Address Accepted

0 0 0 85 00 00 00 00 00 4 0 32 21 00 00 00 00 00

0 1 1 A5 00 00 00 00 00 4 1 33 01 00 00 00 00 00

0 2 2 E5 00 00 00 00 00 4 2 34 41 00 00 00 00 00

0 3 3 C5 00 00 00 00 00 4 3 35 71 00 00 00 00 00

0 4 4 45 00 00 00 00 00 4 4 36 E1 00 00 00 00 00

0 5 5 65 00 00 00 00 00 4 5 37 C1 00 00 00 00 00

0 6 6 25 00 00 00 00 00 4 6 38 81 00 00 00 00 00

0 7 7 05 00 00 00 00 00 4 7 39 A1 00 00 00 00 00

1 0 8 2B 00 00 00 00 00 5 0 40 8F 00 00 00 00 00

1 1 9 0B 00 00 00 00 00 5 1 41 BF 00 00 00 00 00

1 2 10 4B 00 00 00 00 00 5 2 42 EF 00 00 00 00 00

1 3 11 6B 00 00 00 00 00 5 3 43 CF 00 00 00 00 00

1 4 12 EB 00 00 00 00 00 5 4 44 4F 00 00 00 00 00

1 5 13 CB 00 00 00 00 00 5 5 45 6F 00 00 00 00 00

1 6 14 8B 00 00 00 00 00 5 6 46 2F 00 00 00 00 00

1 7 15 BB 00 00 00 00 00 5 7 47 0F 00 00 00 00 00

2 0 16 C7 00 00 00 00 00 6 0 48 63 00 00 00 00 00

2 1 17 E7 00 00 00 00 00 6 1 49 43 00 00 00 00 00

2 2 18 A7 00 00 00 00 00 6 2 50 03 00 00 00 00 00

2 3 19 87 00 00 00 00 00 6 3 51 23 00 00 00 00 00

2 4 20 07 00 00 00 00 00 6 4 52 A3 00 00 00 00 00

2 5 21 27 00 00 00 00 00 6 5 53 83 00 00 00 00 00

2 6 22 67 00 00 00 00 00 6 6 54 C3 00 00 00 00 00

2 7 23 47 00 00 00 00 00 6 7 55 E3 00 00 00 00 00

3 0 24 69 00 00 00 00 00 7 0 56 CD 00 00 00 00 00

3 1 25 49 00 00 00 00 00 7 1 57 ED 00 00 00 00 00

3 2 26 09 00 00 00 00 00 7 2 58 AD 00 00 00 00 00

3 3 27 29 00 00 00 00 00 7 3 5 9 8D 00 00 00 00 00

3 4 28 A9 00 00 00 00 00 7 4 60 0D 00 00 00 00 00

3 5 29 89 00 00 00 00 00 7 5 6 1 2D 00 00 00 00 00

3 6 30 C9 00 00 00 00 00 7 6 62 6D 00 00 00 00 00

3 7 31 E9 00 00 00 00 00 7 7 63 4D 00 00 00 00 00

APPENDIX B

Am79C940 123

BSDL DESCRIPTION OF

Am79C940 MACE JTAG

STRUCTURE

-- -------- 04 November 1996 -----------

-- JWB 13-AUG-1996 changed "TQFP_PACKAGE" to "TQFP"

-- 31-OCT-1996 corrected reversed bit subscripts for ADD, DBUS !

-- and bumped chip rev version from 2 to 3

-- A separate file for TQFP only, had to be created due to the missing

-- four pins/functions on the TQFP version.

-- The compiler does not know how to handle the missing four pins/functions

-- in the TQFP version while at the same time, available for the PQFP

-- and PLCC versions. We have no further plans for going back to

-- combining both files into a single BSDL file.

-- Network Products Division Product Marketing Group

-- -------------------------------------

-- BSDL File created/edited by AT&T BSD Editor

-- BSDE:Revision: Silicon Rev. C0; File REV A3

-- BSDE:Description: BSDL File for the AM79C940 MACE Rev C0 Product

-- BSDE:Comments: /* BSDL file for the TQFP Definition only.

-- * BSDL file checked by AT&T’s BCAD2 BSD Editor on 04/03/96

-- */

entity AM79C940 is

generic (PHYSICAL_PIN_MAP : string := "TQFP" );

port (

ADD: in bit_vector (4 downto 0);

AVDD1: linkage bit;

AVDD2: linkage bit;

AVDD3: linkage bit;

AVDD4: linkage bit;

124 Am79C940

AVSS1: linkage bit;

AVSS2: linkage bit;

BE0_L: in bit;

BE1_L: in bit;

CI0: linkage bit;

CI1: in bit;

CLSN: inout bit;

CS_L: in bit;

DBUS: inout bit_vector (15 downto 0);

DI0: linkage bit;

DI1: in bit;

DO0: linkage bit;

DO1: out bit;

DVDD1: linkage bit;

DVDD2: linkage bit;

DVDDN: linkage bit;

DVDDP: linkage bit;

DVSS1: linkage bit;

DVSS2: linkage bit;

DVSSN1: linkage bit;

DVSSN2: linkage bit;

DVSSN3: linkage bit;

DVSSP: linkage bit;

DXRCV_L: out bit;

EAM_R_L: in bit;

EDSEL: in bit;

EOF_L: inout bit;

FDS_L: in bit;

INTR_L: out bit;

LNKST_L: out bit;

RDTREQ_L: out bit;

RESET_L: in bit;

RXCRS: inout bit;

RXD0: linkage bit;

RXD1: in bit;

RXDAT: inout bit;

R_W_L: in bit;

SCLK: in bit;

SF_BD: out bit;

Am79C940 125

SLEEP_L: in bit;

SRDCLK: inout bit;

STDCLK: inout bit;

TCK: in bit;

TC_L: in bit;

TDI: in bit;

TDO: out bit;

TDTREQ_L: out bit;

TMS: in bit;

TXD0: linkage bit;

TXD1: out bit;

TXDAT1: inout bit;

TXEN_L: inout bit;

TXP0: linkage bit;

TXP1: out bit;

XTAL1: in bit;

XTAL2: linkage bit

);

use STD_1149_1_1990.all;

attribute PIN_MAP of AM79C940 : entity is PHYSICAL_PIN_MAP;

constant TQFP: PIN_MAP_STRING:=

"ADD:(40,39,38,37,36)," &

"AVDD1:52," &

"AVDD2:57," &

"AVDD3:64," &

"AVDD4:69," &

"AVSS1:59," &

"AVSS2:61," &

"BE0_L:31," &

"BE1_L:32," &

"CI0:67," &

"CI1:68," &

"CLSN:78," &

"CS_L:42," &

"DBUS:(27,26,24,23,22,21,20,19,18,17," &

"16,14,13,12,11,9)," &

126 Am79C940

"DI0:65," &

"DI1:66," &

"DO0:62," &

"DO1:63," &

"DVDD1:49," &

"DVDD2:70," &

"DVDDN:25," &

"DVDDP:6," &

"DVSS1:47," &

"DVSS2:73," &

"DVSSN1:10," &

"DVSSN2:15," &

"DVSSN3:28," &

"DVSSP:75," &

"DXRCV_L:71," &

"EAM_R_L:2," &

"EDSEL:72," &

"EOF_L:29," &

"FDS_L:30," &

"INTR_L:7," &

"LNKST_L:43," &

"RDTREQ_L:35," &

"RESET_L:4," &

"RXCRS:80," &

"RXD0:50," &

"RXD1:51," &

"RXDAT:79," &

"R_W_L:41," &

"SCLK:33," &

"SF_BD:3," &

"SLEEP_L:5," &

"SRDCLK:1," &

"STDCLK:76," &

"TCK:46," &

"TC_L:8," &

"TDI:48," &

"TDO:44," &

"TDTREQ_L:34," &

"TMS:45," &

Am79C940 127

"TXD0:54," &

"TXD1:56," &

"TXDAT1:74," &

"TXEN_L:77," &

"TXP0:53," &

"TXP1:55," &

"XTAL1:58," &

"XTAL2:60";

attribute TAP_SCAN_IN of TDI : signal is true;

attribute TAP_SCAN_OUT of TDO : signal is true;

attribute TAP_SCAN_MODE of TMS : signal is true;

attribute TAP_SCAN_CLOCK of TCK : signal is (1.00e+07, BOTH);

attribute INSTRUCTION_LENGTH of AM79C940 : entity is 4;

attribute INSTRUCTION_OPCODE of AM79C940 : entity is

"BYPASS ( 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110," &

" 1111)," &

"EXTEST ( 0000)," &

"IDCODE ( 0001)," &

"SAMPLE ( 0010)," &

"SELFTST ( 0101)," &

"SETBYP ( 0100)," &

"TRIBYP ( 0011)" ;

attribute INSTRUCTION_CAPTURE of AM79C940 : entity is "0001";

attribute INSTRUCTION_DISABLE of AM79C940 : entity is "TRIBYP";

attribute INSTRUCTION_PRIVATE of AM79C940 : entity is

" SELFTST";

attribute IDCODE_REGISTER of AM79C940 : entity is

"0011" &---- version 31-OCT-1996 bumped version from 2 to 3 !

"1001010000000000" &--- part number

"00000000001" &---- manufacturer’s id

"1";----- required by standard

attribute REGISTER_ACCESS of AM79C940 : entity is

128 Am79C940

"BYPASS ( BYPASS, SETBYP, TRIBYP)," &

"BOUNDARY ( EXTEST, SAMPLE, SELFTST)," &

"IDCODE ( IDCODE)";

attribute BOUNDARY_CELLS of AM79C940 : entity is

" BC_1, BC_4";

attribute BOUNDARY_LENGTH of AM79C940 : entity is 99;

attribute BOUNDARY_REGISTER of AM79C940 : entity is

" 0 (BC_1, *, control, 0)," &

" 1 (BC_1, LNKST_L, output3, X, 0, 0, Weak1)," &

" 2 (BC_1, *, internal, 0)," &

" 3 (BC_1, CS_L, input, 1)," &

" 4 (BC_1, R_W_L, input, 1)," &

" 5 (BC_1, ADD(4), input, 0)," &

" 6 (BC_1, ADD(3), input, 0)," &

" 7 (BC_1, ADD(2), input, 0)," &

" 8 (BC_1, ADD(1), input, 0)," &

" 9 (BC_1, ADD(0), input, 0)," &

" 10 (BC_1, *, control, 0)," &

" 11 (BC_1, RDTREQ_L, output3, X, 10, 0, Z)," &

" 12 (BC_1, TDTREQ_L, output3, X, 10, 0, Z)," &

" 13 (BC_4, SCLK, clock, 1)," &

" 14 (BC_1, BE1_L, input, 1)," &

" 15 (BC_1, BE0_L, input, 1)," &

" 16 (BC_1, FDS_L, input, 1)," &

" 17 (BC_1, *, internal, 0)," &

" 18 (BC_1, *, internal, 0)," &

" 19 (BC_1, *, control, 0)," &

" 20 (BC_1, EOF_L, output3, X, 19, 0, Z)," &

" 21 (BC_1, EOF_L, input, 1)," &

" 22 (BC_1, *, control, 0)," &

" 23 (BC_1, DBUS(15), output3, X, 22, 0, Z)," &

" 24 (BC_1, DBUS(15), input, 0)," &

" 25 (BC_1, DBUS(14), output3, X, 22, 0, Z)," &

" 26 (BC_1, DBUS(14), input, 0)," &

" 27 (BC_1, DBUS(13), output3, X, 22, 0, Z)," &

" 28 (BC_1, DBUS(13), input, 0)," &

Am79C940 129

" 29 (BC_1, DBUS(12), output3, X, 22, 0, Z)," &

" 30 (BC_1, DBUS(12), input, 0)," &

" 31 (BC_1, DBUS(11), output3, X, 22, 0, Z)," &

" 32 (BC_1, DBUS(11), input, 0)," &

" 33 (BC_1, DBUS(10), output3, X, 22, 0, Z)," &

" 34 (BC_1, DBUS(10), input, 0)," &

" 35 (BC_1, *, control, 0)," &

" 36 (BC_1, DBUS(9), output3, X, 35, 0, Z)," &

" 37 (BC_1, DBUS(9), input, 0)," &

" 38 (BC_1, DBUS(8), output3, X, 35, 0, Z)," &

" 39 (BC_1, DBUS(8), input, 0)," &

" 40 (BC_1, DBUS(7), output3, X, 35, 0, Z)," &

" 41 (BC_1, DBUS(7), input, 0)," &

" 42 (BC_1, DBUS(6), output3, X, 35, 0, Z)," &

" 43 (BC_1, DBUS(6), input, 0)," &

" 44 (BC_1, DBUS(5), output3, X, 35, 0, Z)," &

" 45 (BC_1, DBUS(5), input, 0)," &

" 46 (BC_1, DBUS(4), output3, X, 35, 0, Z)," &

" 47 (BC_1, DBUS(4), input, 0)," &

" 48 (BC_1, DBUS(3), output3, X, 35, 0, Z)," &

" 49 (BC_1, DBUS(3), input, 0)," &

" 50 (BC_1, DBUS(2), output3, X, 35, 0, Z)," &

" 51 (BC_1, DBUS(2), input, 0)," &

" 52 (BC_1, DBUS(1), output3, X, 35, 0, Z)," &

" 53 (BC_1, DBUS(1), input, 0)," &

" 54 (BC_1, DBUS(0), output3, X, 35, 0, Z)," &

" 55 (BC_1, DBUS(0), input, 0)," &

" 56 (BC_1, TC_L, input, 1)," &

" 57 (BC_1, *, control, 0)," &

" 58 (BC_1, INTR_L, output3, 1, 57, 0, Weak1)," &

" 59 (BC_1, SLEEP_L, input, 1)," &

" 60 (BC_1, RESET_L, input, 1)," &

" 61 (BC_1, *, control, 0)," &

" 62 (BC_1, SF_BD, output3, X, 61, 0, Z)," &

" 63 (BC_1, *, internal, 0)," &

" 64 (BC_1, EAM_R_L, input, 0)," &

" 65 (BC_1, *, control, 0)," &

" 66 (BC_1, SRDCLK, output3, X, 65, 0, Z)," &

" 67 (BC_1, SRDCLK, input, 0)," &

130 Am79C940

" 68 (BC_1, *, control, 0)," &

" 69 (BC_1, RXCRS, output3, X, 68, 0, Z)," &

" 70 (BC_1, RXCRS, input, 0)," &

" 71 (BC_1, *, control, 0)," &

" 72 (BC_1, RXDAT, output3, X, 71, 0, Z)," &

" 73 (BC_1, RXDAT, input, 0)," &

" 74 (BC_1, *, control, 0)," &

" 75 (BC_1, CLSN, output3, X, 74, 0, Z)," &

" 76 (BC_1, CLSN, input, 0)," &

" 77 (BC_1, *, control, 0)," &

" 78 (BC_1, TXEN_L, output3, X, 77, 0, Z)," &

" 79 (BC_1, TXEN_L, input, 0)," &

" 80 (BC_1, *, control, 0)," &

" 81 (BC_1, STDCLK, output3, X, 80, 0, Z)," &

" 82 (BC_1, STDCLK, input, 0)," &

" 83 (BC_1, *, control, 0)," &

" 84 (BC_1, *, internal, 0)," &

" 85 (BC_1, TXDAT1, output3, X, 83, 0, Z)," &

" 86 (BC_1, TXDAT1, input, 1)," &

" 87 (BC_1, EDSEL, input, 1)," &

" 88 (BC_1, *, control, 0)," &

" 89 (BC_1, DXRCV_L, output3, X, 88, 0, Z)," &

" 90 (BC_4, XTAL1, clock, 0)," &

" 91 (BC_1, RXD1, input, 1)," &

" 92 (BC_1, *, control, 0)," &

" 93 (BC_1, TXP1, output3, X, 92, 0, Z)," &

" 94 (BC_1, TXD1, output3, X, 92, 0, Z)," &

" 95 (BC_1, *, control, 0)," &

" 96 (BC_1, DO1, output3, X, 95, 0, Z)," &

" 97 (BC_4, DI1, input, 1)," &

" 98 (BC_4, CI1, input, 1)";

end AM79C940;

=============================================================================

Am79C940 131

-- BSDL File created/edited by AT&T BSD Editor

-- BSDE:Revision: Silicon Rev. C0; File REV A3

-- BSDE:Description: BSDL File for the AM79C940 MACE Product;

-- 84-Pin PLCC and 100-Pin PQFP packages.

-- Separate file for 80-Pin TQFP package.

-- BSDE:Comments: /* TQFP Definition has been deleted.

-- * BSDL file checked by AT&T’s BCAD2 BSD Editor on 9/7/95

-- */

entity AM79C940 is

generic (PHYSICAL_PIN_MAP : string := "PLCC_PACKAGE" );

port (

ADD: in bit_vector (0 to 4);

AVDD1: linkage bit;

AVDD2: linkage bit;

AVDD3: linkage bit;

AVDD4: linkage bit;

AVSS1: linkage bit;

AVSS2: linkage bit;

BE0_L: in bit;

BE1_L: in bit;

CI0: linkage bit;

CI1: in bit;

CLSN: inout bit;

CS_L: in bit;

DBUS: inout bit_vector (0 to 15);

DI0: linkage bit;

DI1: in bit;

DO0: linkage bit;

DO1: out bit;

DTV_L: out bit;

DVDD1: linkage bit;

DVDD2: linkage bit;

DVDDN: linkage bit;

DVDDP: linkage bit;

132 Am79C940

DVSS1: linkage bit;

DVSS2: linkage bit;

DVSSN1: linkage bit;

DVSSN2: linkage bit;

DVSSN3: linkage bit;

DVSSP: linkage bit;

DXRCV_L: out bit;

EAM_R_L: in bit;

EDSEL: in bit;

EOF_L: inout bit;

FDS_L: in bit;

INTR_L: out bit;

LNKST_L: out bit;

RDTREQ_L: out bit;

RESET_L: in bit;

RXCRS: inout bit;

RXD0: linkage bit;

RXD1: in bit;

RXDAT: inout bit;

RXPOL_L: out bit;

R_W_L: in bit;

SCLK: in bit;

SF_BD: out bit;

SLEEP_L: in bit;

SRD: out bit;

SRDCLK: inout bit;

STDCLK: inout bit;

TCK: in bit;

TC_L: in bit;

TDI: in bit;

TDO: out bit;

TDTREQ_L: out bit;

TMS: in bit;

TXD0: linkage bit;

TXD1: out bit;

TXDAT0: out bit;

TXDAT1: inout bit;

TXEN_L: inout bit;

TXP0: linkage bit;

Am79C940 133

TXP1: out bit;

XTAL1: in bit;

XTAL2: linkage bit

);

use STD_1149_1_1990.all;

attribute PIN_MAP of AM79C940 : entity is PHYSICAL_PIN_MAP;

constant PLCC_PACKAGE: PIN_MAP_STRING:=

"ADD:(49,50,51,52,53)," &

"AVDD1:66," &

"AVDD2:71," &

"AVDD3:78," &

"AVDD4:83," &

"AVSS1:73," &

"AVSS2:75," &

"BE0_L:44," &

"BE1_L:45," &

"CI0:81," &

"CI1:82," &

"CLSN:9," &

"CS_L:55," &

"DBUS:(21,23,24,25,26,28,29,30,31,32," &

"33,34,35,36,38,39)," &

"DI0:79," &

"DI1:80," &

"DO0:76," &

"DO1:77," &

"DTV_L:42," &

"DVDD1:63," &

"DVDD2:84," &

"DVDDN:37," &

"DVDDP:18," &

"DVSS1:61," &

"DVSS2:3," &

"DVSSN1:22," &

"DVSSN2:27," &

"DVSSN3:40," &

134 Am79C940

"DVSSP:6," &

"DXRCV_L:1," &

"EAM_R_L:13," &

"EDSEL:2," &

"EOF_L:41," &

"FDS_L:43," &

"INTR_L:19," &

"LNKST_L:57," &

"RDTREQ_L:48," &

"RESET_L:16," &

"RXCRS:11," &

"RXD0:64," &

"RXD1:65," &

"RXDAT:10," &

"RXPOL_L:56," &

"R_W_L:54," &

"SCLK:46," &

"SF_BD:15," &

"SLEEP_L:17," &

"SRD:14," &

"SRDCLK:12," &

"STDCLK:7," &

"TCK:60," &

"TC_L:20," &

"TDI:62," &

"TDO:58," &

"TDTREQ_L:47," &

"TMS:59," &

"TXD0:68," &

"TXD1:70," &

"TXDAT0:5," &

"TXDAT1:4," &

"TXEN_L:8," &

"TXP0:67," &

"TXP1:69," &

"XTAL1:72," &

"XTAL2:74";

constant PQFP_PACKAGE: PIN_MAP_STRING:=

Am79C940 135

"ADD:(46,47,48,49,50)," &

"AVDD1:67," &

"AVDD2:72," &

"AVDD3:83," &

"AVDD4:88," &

"AVSS1:74," &

"AVSS2:79," &

"BE0_L:41," &

"BE1_L:42," &

"CI0:86," &

"CI1:87," &

"CLSN:98," &

"CS_L:56," &

"DBUS:(14,16,17,18,19,21,22,23,24,25," &

"29,31,32,33,35,36)," &

"DI0:84," &

"DI1:85," &

"DO0:81," &

"DO1:82," &

"DTV_L:39," &

"DVDD1:64," &

"DVDD2:89," &

"DVDDN:34," &

"DVDDP:11," &

"DVSS1:62," &

"DVSS2:92," &

"DVSSN1:15," &

"DVSSN2:20," &

"DVSSN3:37," &

"DVSSP:95," &

"DXRCV_L:90," &

"EAM_R_L:6," &

"EDSEL:91," &

"EOF_L:38," &

"FDS_L:40," &

"INTR_L:12," &

"LNKST_L:58," &

"RDTREQ_L:45," &

"RESET_L:9," &

136 Am79C940

"RXCRS:100," &

"RXD0:65," &

"RXD1:66," &

"RXDAT:99," &

"RXPOL_L:57," &

"R_W_L:55," &

"SCLK:43," &

"SF_BD:8," &

"SLEEP_L:10," &

"SRD:7," &

"SRDCLK:5," &

"STDCLK:96," &

"TCK:61," &

"TC_L:13," &

"TDI:63," &

"TDO:59," &

"TDTREQ_L:44," &

"TMS:60," &

"TXD0:69," &

"TXD1:71," &

"TXDAT0:94," &

"TXDAT1:93," &

"TXEN_L:97," &

"TXP0:68," &

"TXP1:70," &

"XTAL1:73," &

"XTAL2:75";

attribute TAP_SCAN_IN of TDI : signal is true;

attribute TAP_SCAN_OUT of TDO : signal is true;

attribute TAP_SCAN_MODE of TMS : signal is true;

attribute TAP_SCAN_CLOCK of TCK : signal is (1.00e+07, BOTH);

attribute INSTRUCTION_LENGTH of AM79C940 : entity is 4;

attribute INSTRUCTION_OPCODE of AM79C940 : entity is

"BYPASS ( 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110," &

" 1111)," &

"EXTEST ( 0000)," &

"IDCODE ( 0001)," &

Am79C940 137

"SAMPLE ( 0010)," &

"SELFTST ( 0101)," &

"SETBYP ( 0100)," &

"TRIBYP ( 0011)" ;

attribute INSTRUCTION_CAPTURE of AM79C940 : entity is "0001";

attribute INSTRUCTION_DISABLE of AM79C940 : entity is "TRIBYP";

attribute INSTRUCTION_PRIVATE of AM79C940 : entity is

" SELFTST";

attribute IDCODE_REGISTER of AM79C940 : entity is

"0011" &-- version

"1001010000000000" &-- part number

"00000000001" &-- manufacturer’s id

"1";-- required by standard

attribute REGISTER_ACCESS of AM79C940 : entity is

"BYPASS ( BYPASS, SETBYP, TRIBYP)," &

"BOUNDARY ( EXTEST, SAMPLE, SELFTST)," &

"IDCODE ( IDCODE)";

attribute BOUNDARY_CELLS of AM79C940 : entity is

" BC_1, BC_4";

attribute BOUNDARY_LENGTH of AM79C940 : entity is 99;

attribute BOUNDARY_REGISTER of AM79C940 : entity is

" 0 (BC_1, *, control, 0)," &

" 1 (BC_1, LNKST_L, output3, X, 0, 0, Weak1)," &

" 2 (BC_1, RXPOL_L, output3, X, 0, 0, Weak1)," &

" 3 (BC_1, CS_L, input, 1)," &

" 4 (BC_1, R_W_L, input, 1)," &

" 5 (BC_1, ADD(4), input, 0)," &

" 6 (BC_1, ADD(3), input, 0)," &

" 7 (BC_1, ADD(2), input, 0)," &

" 8 (BC_1, ADD(1), input, 0)," &

" 9 (BC_1, ADD(0), input, 0)," &

138 Am79C940

" 10 (BC_1, *, control, 0)," &

" 11 (BC_1, RDTREQ_L, output3, X, 10, 0, Z)," &

" 12 (BC_1, TDTREQ_L, output3, X, 10, 0, Z)," &

" 13 (BC_4, SCLK, clock, 1)," &

" 14 (BC_1, BE1_L, input, 1)," &

" 15 (BC_1, BE0_L, input, 1)," &

" 16 (BC_1, FDS_L, input, 1)," &

" 17 (BC_1, *, control, 0)," &

" 18 (BC_1, DTV_L, output3, X, 17, 0, Z)," &

" 19 (BC_1, *, control, 0)," &

" 20 (BC_1, EOF_L, output3, X, 19, 0, Z)," &

" 21 (BC_1, EOF_L, input, 1)," &

" 22 (BC_1, *, control, 0)," &

" 23 (BC_1, DBUS(15), output3, X, 22, 0, Z)," &

" 24 (BC_1, DBUS(15), input, 0)," &

" 25 (BC_1, DBUS(14), output3, X, 22, 0, Z)," &

" 26 (BC_1, DBUS(14), input, 0)," &

" 27 (BC_1, DBUS(13), output3, X, 22, 0, Z)," &

" 28 (BC_1, DBUS(13), input, 0)," &

" 29 (BC_1, DBUS(12), output3, X, 22, 0, Z)," &

" 30 (BC_1, DBUS(12), input, 0)," &

" 31 (BC_1, DBUS(11), output3, X, 22, 0, Z)," &

" 32 (BC_1, DBUS(11), input, 0)," &

" 33 (BC_1, DBUS(10), output3, X, 22, 0, Z)," &

" 34 (BC_1, DBUS(10), input, 0)," &

" 35 (BC_1, *, control, 0)," &

" 36 (BC_1, DBUS(9), output3, X, 35, 0, Z)," &

" 37 (BC_1, DBUS(9), input, 0)," &

" 38 (BC_1, DBUS(8), output3, X, 35, 0, Z)," &

" 39 (BC_1, DBUS(8), input, 0)," &

" 40 (BC_1, DBUS(7), output3, X, 35, 0, Z)," &

" 41 (BC_1, DBUS(7), input, 0)," &

" 42 (BC_1, DBUS(6), output3, X, 35, 0, Z)," &

" 43 (BC_1, DBUS(6), input, 0)," &

" 44 (BC_1, DBUS(5), output3, X, 35, 0, Z)," &

" 45 (BC_1, DBUS(5), input, 0)," &

" 46 (BC_1, DBUS(4), output3, X, 35, 0, Z)," &

" 47 (BC_1, DBUS(4), input, 0)," &

" 48 (BC_1, DBUS(3), output3, X, 35, 0, Z)," &

Am79C940 139

" 49 (BC_1, DBUS(3), input, 0)," &

" 50 (BC_1, DBUS(2), output3, X, 35, 0, Z)," &

" 51 (BC_1, DBUS(2), input, 0)," &

" 52 (BC_1, DBUS(1), output3, X, 35, 0, Z)," &

" 53 (BC_1, DBUS(1), input, 0)," &

" 54 (BC_1, DBUS(0), output3, X, 35, 0, Z)," &

" 55 (BC_1, DBUS(0), input, 0)," &

" 56 (BC_1, TC_L, input, 1)," &

" 57 (BC_1, *, control, 0)," &

" 58 (BC_1, INTR_L, output3, 1, 57, 0, Weak1)," &

" 59 (BC_1, SLEEP_L, input, 1)," &

" 60 (BC_1, RESET_L, input, 1)," &

" 61 (BC_1, *, control, 0)," &

" 62 (BC_1, SF_BD, output3, X, 61, 0, Z)," &

" 63 (BC_1, SRD, output3, X, 61, 0, Z)," &

" 64 (BC_1, EAM_R_L, input, 0)," &

" 65 (BC_1, *, control, 0)," &

" 66 (BC_1, SRDCLK, output3, X, 65, 0, Z)," &

" 67 (BC_1, SRDCLK, input, 0)," &

" 68 (BC_1, *, control, 0)," &

" 69 (BC_1, RXCRS, output3, X, 68, 0, Z)," &

" 70 (BC_1, RXCRS, input, 0)," &

" 71 (BC_1, *, control, 0)," &

" 72 (BC_1, RXDAT, output3, X, 71, 0, Z)," &

" 73 (BC_1, RXDAT, input, 0)," &

" 74 (BC_1, *, control, 0)," &

" 75 (BC_1, CLSN, output3, X, 74, 0, Z)," &

" 76 (BC_1, CLSN, input, 0)," &

" 77 (BC_1, *, control, 0)," &

" 78 (BC_1, TXEN_L, output3, X, 77, 0, Z)," &

" 79 (BC_1, TXEN_L, input, 0)," &

" 80 (BC_1, *, control, 0)," &

" 81 (BC_1, STDCLK, output3, X, 80, 0, Z)," &

" 82 (BC_1, STDCLK, input, 0)," &

" 83 (BC_1, *, control, 0)," &

" 84 (BC_1, TXDAT0, output3, X, 83, 0, Z)," &

" 85 (BC_1, TXDAT1, output3, X, 83, 0, Z)," &

" 86 (BC_1, TXDAT1, input, 1)," &

" 87 (BC_1, EDSEL, input, 1)," &

140 Am79C940

" 88 (BC_1, *, control, 0)," &

" 89 (BC_1, DXRCV_L, output3, X, 88, 0, Z)," &

" 90 (BC_4, XTAL1, clock, 0)," &

" 91 (BC_1, RXD1, input, 1)," &

" 92 (BC_1, *, control, 0)," &

" 93 (BC_1, TXP1, output3, X, 92, 0, Z)," &

" 94 (BC_1, TXD1, output3, X, 92, 0, Z)," &

" 95 (BC_1, *, control, 0)," &

" 96 (BC_1, DO1, output3, X, 95, 0, Z)," &

" 97 (BC_4, DI1, input, 1)," &

" 98 (BC_4, CI1, input, 1)";

end AM79C940;

APPENDIX C

Am79C940 141

Am79C940 MACE Rev C0 Silicon

Errata

The items below are the known errata for Rev C0 silicon. Rev C0 is the production silicon.

The enclos ed is a list of kn own errata’s encounte re d with the MA CE Rev C0 dev ice. Eac h of the se errat a ’s is pro-

vided with de sc ript ion , impli cat ion , and wor kar oun d (if po ssi bl e). Wher e the err ata was pub li sh ed in a prev io us er-

rata list, is so noted. Other than those listed exceptions below that have not been fixed, the MACE Rev C0

production device is fully functional.

The "Description" secti on of th e errata give s a br ief des cripti on of th e proble m. The "Implication" secti on of the

errata d es crib es the e ffects of the p ro ble m i n a s yst em co nfi guration. T he "Workaround" section of the er rata de-

scribes methods to minimize the system effects. The “Status” section of the e rrata d escri bes w hen a nd how th e

problem will be corrected.

Current package marking for this revision: Line 1: <Logo>

Line 2: Am79C940BKC (Assuming package is PQFP)

Line 3: <Date Code>

Value of CHIPID register for this revision: CHIPID[15:00] = 3940h

1) Receive Fragment Frame Treated as a New Packet Even After Receive FIFO Overflows:

Description: The MACE device continues to receive the remains of a long packet even after the receive FIFO

overflo ws. If this da ta stream has t he ’Start of Frame ’ (SFD) bi t pattern "10101 011" ( and no "00" bit pattern

before th e "SFD" patter n) and the de stination ad dress field o f the packet m atches the s tation addr ess after

the SFD b it p atter n , or if the MACE de vi ce is i n prom is cu ous mo de, the r em ai nin g po rt ion of th e l ong pac ke t

will be recei ved a nd treate d by the MACE d evic e as a ne w packet even thoug h t he rece ive status wil l sho w

an FCS error.

Implication: There is no impact of any kind if the receive FIFO overflow is not permitted by the system design.

The likelihood of such an occurrence of the above conditions is extremely remote. Should this condition occur ,

this will impact performance only in products using the “cut-through” method. This is because the "cut-

through" method will not look at the FCS field, which would indicate an error in the packet received.

Workaround: Check for FCS error after the packet is received.

Status: No current plan to fix this item.

2) In Low Latency Receive Mode, Loses Synchronization When Connected to a Coaxial Tr ansceiver via the

AUI Port:

Description: In low latency receive mode, the MACE device loses synchronization when connected to a co-

axial (10BASE2) transceiver . The problem occurs when connecting the MACE to a coaxial transceiver via the

AUI inter fac e, an d a t th e s am e ti me the MA CE de vi ce i s progr am med i nto lo w l aten cy r ecei ve m ode. W he n

a collision occurs in the media and if MACE device continues to receive data, after the collision is ended, the

MACE device loses synchronization.

Implication: No performance impact to the MACE device if the 10BASE-T port is used instead of a 10BASE2

coaxial transceiver connected to the AUI port of the MACE device.

Workaround: This condition is being validated at this time. In the meantime, it is recommended that if the

product is to be used in a network topology where a 10BASE2 coaxial transceive r is connected to the AUI

port, care must be exercised to avoid using the MACE device in low latency receiver mode.

142 Am79C940

Status: No current plan to fix this item.

3) Flashing LED for Link Status:

Description: When TMAU receiver is receiving negative polarity link pulse, and the automatic polarity correc-

tion alg orithm (DA PC bit in PHY Con figur ation Con trol Reg ister) is disable d, link test state machin e will loop

between ’link fail’ and ’link pass’ state causing the Link Status LED to flash.

Implication: The re is no impact to system perf ormance. Howev er, the L ink Status LED flashing may cause

an erroneous interpretation by the user.

Workaround: There is no workaround.

Status: No current plan to fix this item.

4) Incorrect Runt Packet Count in Low Latency Receive Mode:

Description: In Low Latency Receive mode, the MACE Runt Packet count is incremented when the receive

packet is less than 12 bytes. The correct runt packet count should always be incremented when the receive

packet is less than 64 bytes.

Implication: T here is no impact on system perfor mance if th e runt p acket c ount is not being utilized by the

system.

Workaround: This co ndition is bein g validated a t this time. Theref ore, a workaro und for this is to be d eter-

mined.

5) Device Failure at 1.25 MHz System Clock:

Description: MACE devi ce does not function reli ability at system cl ock spee d of less than 5MHz due to ar-

chitecture constraints.

Implication: There is no performance impact since the serial clock is still running at the IEEE specified

10MHz.

Workarounds:

1. Avoid operating the MACE device at speeds of less than 5MHz.

2. Send one packet at a time. Essentially, write one packet to the transmit FIFO, let the Mace device

transmit that packet, wait for the transmit complete interrupt, before writing another packet to the

transmit FIFO.

Status: No current plan to fix this item.

6) False BABL errors generated:

Description: The MACE device will intermittenly give BABL error indications when the network traffic has

frames equal to or greater than 1518 bytes.

Implication: False BABL errors on the receiving station can be passed up to the upper layer software if MACE

device is just coming out of deferral and the multi-purpose counter used to count the number of bytes recevied

reaches 1518 at t he same ti me. I f the network is h eav il y loaded wit h full- size frames, t hen th e p ro bab il ity o f

a false BABL error is high.

Workaround: There are two possible workarounds.

1. If the user has no intention to transmit frames larger than 1518 bytes, then the BABL bit may be

masked to ignore babble errors. In this case the false babble error will not cause an interrupt, nor will

it be passed to the higher level software.

2. Check to se e if the dev ice is tran smitt ing in IS R (Interr upt Ser vice Rout ine), which i s induced by the

BABL error. The BCRs which control the LED settings can be programmed to indicate a transmit ac-

tivity, assuming the interrupt latency is not longer than one mininum IFG (inter-frame gap) time.

Am79C940 143

If (ISR_LATENCY < 9.6 us)

True_bable_err = BABL * ( TINT + XMT_LED)

{ i.e. False_bable_err = ~ (BABL * ( TINT + XMT_LED))}

else

Cannot tell if the BABL error is true or false just by reading BABL, TINT,

XMT_LED bits in ISR.

Status: No current plan to fix this item.

144 Am79C940