1
5045A–SEEPR–04/04
Features
•Low-voltage and Standard-voltage Operation, VCC = 2.7V–5.5V
•Internally Organized 131,072x 8
•Two-wire Serial Interface
•Schmitt Triggers, Filtered Inputs for Noise Suppression
•Bidirectional Data Transfer Protocol
•1 MHz (5V) and 400 kHz (2.7V) Compatibility
•256-byte Page Write Mode (Partial Page Writes Allowed)
•Self-timed Write Cycle (5 ms Typical)
•High Reliabil ity
– Endurance: 100,000 Write Cycles
– Data Retention: 40 Years
– 5.5V ESD Protection: >4000V
Description
The AT24C1024SC provides 1,048,576 bits of se rial electrically erasable and pro-
gramma ble read only memo ry (EEPROM) organized as 131,072 wo rds of 8 bit s each.
This device is optim ized for use in smar t card applications where low-power and low-
volta ge opera t ion may b e ess en t ial. Th is devi ce i s availa ble in a standar d IS O 7816
smart card module (see O rd er i ng I nfor mat ion, page 11). All devices are functionally
equivalent to At mel ser ial EEPROM products offered in standard I C packages (P DIP,
SOIC, dBGA, LAP), with the exception of the slave address and write protect func-
tions, which are not required for sm art card applications.
Table 1. Pin Configurations
Figure 1. C ard Module Contact
Pad Name Description ISO M odule Contact
VCC Power Supply Vol tage C1
GND Ground C5
SCL Serial Clock Input C3
SDA Serial Da ta Input /Output C7
NC No Connect C2, C4, C6, C8
SCL = C3
NC = C4
VCC = C1
NC = C2 C5 = GND
C6 = NC
C7 = SDA
C8 = NC
Two-wire Serial
EE PR O M Sm art
Card Module
1K (131,072 x 8)
AT24C1024SC
2AT24C1024SC 5045A–SEEPR–04/04
Fi gure 2. Block Diagram
Pin Description SERIAL CLOCK (S CL): Th e SC L inp ut is u sed to po sitive edg e clock data into each
EEPROM device and negative edge clock data out of eac h device.
SER IAL DA TA (SDA ): The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open
collector devices.
Memory Organization AT24C1024SC, 1024K SERIAL EEPROM: The 1024K is internally organized as 512
pages of 256 bytes e ach. Random word addressing req uires a 17-bit data word
address.
Absolute Ma ximu m Ratings*
Operating Temperature......................................−55°C to +125°CNOTICE:* Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the
device. This is a stress rating only; functional opera-
tion of the device at these or any other conditions
beyond those indicated in the operational sections of
this specificat ion is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
Storage Temperature.........................................−65°C to +150°C
Voltage on Any Pin
with Respect to Ground........................................ −1.0V to +7.0 V
Maximum Operating Voltage .......................................... 6.25V
DC O ut pu t C urrent ........... ............ .................... ............ . 5.0 m A
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AT24C1024SC
5045A–SEEPR–04/04
Pin Capacita nce
Note: 1. This parameter is characterized and is not 100% tested.
DC Characteristics
Note: 1. Applicable over recom mended operating range from TAC = 0°C to +70°C, VCC = +2.7V to +5.5V (unless otherwise noted)
2. VIL min and VIH max are reference only and are not tested.
AC Characteristics
Table 2. Pin Capacitance(1)
Applicable o ve r recommended operating range from TA = 25 °C, f = 1.0 MHz, VCC = +2.7V
Symbol Test Condition Max Units Conditions
CI/O Input/Output Capacitance (SDA) 8pF VI/O = 0V
CIN Input Capacitance (SCL) 6pF VIN = 0V
Table 3. DC Characteristics(1)
Symbol P arameter Test Conditi on Min Typ Max Un it s
VCC Supply Voltage 2.7 5.5 V
ICC1 Supply Current VCC = 5.0V Read at 400 kHz 2.0 mA
ICC2 Supply Current VCC = 5.0V Write at 400 kHz 5.0 mA
ISB Standby Current VCC = 2.7V VIN = VCC or GND 3.0 µA
VCC = 5.5V 6.0
ILI Input Leakage Current VIN = VCC or GND 0.10 3.0 µA
ILO Out put Leakag e
Current VOUT = VCC or GND 0.05 3.0 µA
VIL Input Low Level(2) −0.6 VCC x 0.3 V
VIH Input High Level(2) VCC x 0.7 VCC + 0.5 V
VOL Output Low Le vel VCC = 3.0V IOL = 2.1 mA 0.4 V
Table 4. AC Characteristics(1)
Symbol Parameter
2.7-volt 5.0-volt
UnitsMin Max Min Max
fSCL Clock Frequency, SCL 400 1000 kHz
tLOW Clock Pulse Width Low 1.3 0.4 µs
tHIGH Clock Pulse W idth High 0.6 0.4 µs
tAA Clock Low to Dat a Out Va lid 0.05 0.9 0.05 0.55 µs
tBUF Time the bus must be free before a new
transmission can star t(2) 1.3 0.5 µs
tHD.STA Start Hold Time 0.6 0.25 µs
tSU.STA Start Set-up Time 0.6 0.25 µs
tHD.DAT Data In H old Time 0 0 µs
tSU.DAT Data In Se t-up Tim e 100 100 ns
tRInputs Rise Time(2) 0.3 0.3 µs
4AT24C1024SC 5045A–SEEPR–04/04
Note: 1. Applicable over recommended operating range from TA = 0°C to +70°C, VCC = +2.7V to +5.5V, CL = 100 pF (unless other-
wise noted). Test conditions are listed in Note 2.
2. This parameter is characterized and is not 100% tested.
3. AC measur ement conditions:
RL (connects to VCC): 1.3 kΩ (2.7V, 5V)
Input pulse voltages: 0.3VCC to 0.7VCC
Input r i se and fall times: ≤ 50ns
Input and output ti m ing ref erence vo ltag e s: 0.5VCC
tFInputs Fall Time(2) 300 100 ns
tSU.STO Stop Set -up Time 0.6 0.25 µs
tDH Data Ou t Hol d T im e 50 50 ns
tWR Write Cycle Time 10 10 ms
Endurance(2) 5.0V, 25°C , Page Mode 100K 100K Write Cycl es
Table 4. AC Characteristics(1) (Continued)
Symbol Parameter
2.7-volt 5.0-volt
UnitsMin Max Min Max
5
AT24C1024SC
5045A–SEEPR–04/04
Device Operation C LOCK AND DATA T RANSITIONS: The SDA pin is normally pulled high with an exter-
nal device. Data on the SDA pin may change only during SCL-low time periods (see
Figure 5 on pag e 6 ). Data changes during SCL-hig h periods will indicate a start or s top
condition as defined below.
START CONDITIO N: A h igh -to-l ow t rans iti on of SDA wit h SC L hig h is a sta rt conditi on
that m u st prec ede an y other com m and (see F igure 6 on page 7).
STOP CONDITION: A low-to- high t rans itio n of SDA with S CL h igh i s a sto p co nditio n.
Af ter a r ea d seq uen c e, th e stop c omm an d will pl ac e the EEPROM in a standby power
mode (Figure 6 on page 7).
ACKNOWLEDGE: All addre sses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to
acknowl edge that it has received each word .
STANDBY M ODE: The AT 24C1024SC features a low-power standb y mode that is
enabled upon power-up and after the receipt of the stop bit and the completion of an y
internal operations.
MEMORY RESET: After an interruption in protocol, power loss, or system reset, any
two-wire part can be reset by fol lowing these steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a sta rt condition a s SDA is high.
6AT24C1024SC 5045A–SEEPR–04/04
Ti ming D i agra m s
Bus Timing Fi gure 3. Bus Timing(1)
Note: 1. SCL: Serial Clock; SDA: Serial Data I/O
2. The write cycle time tWR is the time from a valid stop condition of a write sequence to
the end of the internal clear/write cycle.
Write Cycle Tim ing Fi gure 4. Write Cycle Tim ing
Note: 1. SCL: Serial Clock; SDA: Serial Data I/O
Data Validity Figu re 5 . Data Validity
tWR(1)
SDA
SCL
DATA STABLE
DATA
CHANGE
DATA STABLE
7
AT24C1024SC
5045A–SEEPR–04/04
Start and Stop Definition Fi gure 6. Sta rt and Stop Definition
Outp ut Ac knowledge Fi gure 7. Output Acknowledge
SDA
SCL
START STOP
SCL
DATA IN
DATA OUT
START ACKNOWLEDGE
8AT24C1024SC 5045A–SEEPR–04/04
Device Add r ess in g The 1024K EEPROM requires an 8-bit device address word fol lowing a start condition to
enable the chip for a read or write operation (see Figure 8). The device address word
consists of a mandatory “one, zero” sequence for the first four most significant bits as
shown. T his is common to all two-wire EEPROM devices.
Th e nex t th ree bi ts of t he devi ce addr ess w or d a re unused. These three unused bits
should be set to “0”.
The sev enth bit (P0) of the device address is a memory page address bit. The memory
page address bit is the most significant bit of the d at a word ad d r e ss t ha t f ol lo w s .
The eighth bit of the device address is the read/write operation select bit. A read opera-
tion is initiat ed if this bit is high and a wri te operatio n is i nitiated i f this bit is low.
U pon a com pare of the devi ce address, t he EEPROM will output a “0”. If a compare is
not made, the device will retu rn to a standby state.
Fi gure 8. Device Address
Wr ite Op er at io ns BYTE WRITE: To select a data word in the 1024K memory requ ires a 17-bit word
address. The word address field co nsists of the P0 bit o f the d e vi ce addr es s, then t he
most significant word address followed by the least significant word address (s ee Figure
9).
A write oper ation requir es the P0 bit and two 8-bit word addres ses followin g th e device
address word and acknowledgment. Upon receipt of this address, the EEPROM will
again respond wi th a “0” and then clock in the first 8-b it dat a word. Following receip t of
the 8-bit data word, the EEPROM will output a “0”. T he ad dre ssi ng device, s uch as a
m icr oco n tro ller, t hen mu s t term inate the wri te sequence with a stop condition. At this
time the EEPROM enters an internally-timed write cycle, tWR, to the nonvolat ile mem ory.
All inputs are disabled durin g this write cycle and the EEPROM will not r e spond until the
write is complete (see Figure 9 ).
Fi gure 9. Byte Write
PAGE WRITE: The 1024K EEPROM is capable of 256-byte page writes.
A page wri te is initiated t he same way as a byte write , bu t the m icrocont roller does not
send a sto p condition after the first data wo rd is clocked in. Instea d, after the EEPROM
ac knowle dges receip t of the first dat a word, the micro contro ller ca n tr ansmit up to 255
more data words. The EEPROM will respond with a “0” after each data word received.
The m icrocontroller must termina te the page write sequence with a stop condition (see
Figure 10).
MSB LSB
101000P
0R/W
MOST SIGNIFICANT LEAST
SIGNIFICANT
P0
9
AT24C1024SC
5045A–SEEPR–04/04
Figure 10. Page Write
The lowe r eight data word add ress bi ts a re internal ly increment ed fo llowing the rec eipt
of each data word. The higher data word address bits are not incremented, retaining the
me mory pa ge row location . When the word ad dre ss, inte rnally g enerate d, reaches the
page boun dary, the following by te is placed at the beginning of the sam e page. If more
tha n 256 data w ords are tran smitted to the EEPRO M, the data word address will “roll
over” and previ ous data will be overwritten. The addre ss “ro ll over” during write is fro m
the last byte o f the current page to the first byte of the same page.
ACKNOWLE DGE POLLING: Once the int ernally-timed write cycle has star ted and the
EEPROM inputs are disa bled, acknowledg e polling can be initiat ed. This involves send-
ing a start condition followed by the device address word. The read/write bit is
representative of the operation desired. Only if the internal write cycle has completed
will the EEPROM respond with a “0”, allo wing the read or write sequenc e to continue.
P0
MOST SIGNIFICANT LEAST
SIGNIFICANT
L
S
B
10 AT24C1024SC 5045A–SEEPR–04/04
Rea d Oper ati on s Read op eratio ns are initiated the sa me way as write op erations with t he exception t hat
the rea d/write selec t bit in t he d evice addres s wo rd i s s et to one. There are three read
operations: current addre ss read, random address read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the
last address accessed during the last read or write operation, incremented by one. This
add re ss s tays val id b et ween oper ati ons a s l ong as the ch ip power i s maint ained. The
addres s “rol l over” du ring read is from the last byte of the last memory page to the first
byte of the first page.
Once the device address with the rea d/write select bit set to one is clocked in and
acknowled ged by the EEPR OM, th e current address dat a word is serially clocked out.
The microcontroller does not respond with an input “0” but does generate a following
stop condition (see Figure 11).
Fi gure 11 . Current Addres s Read
RANDOM RE AD: A random read requires a “dummy” byte write seque nce to load in the
dat a word address . On ce the devi ce address word and data wo rd add ress are clo cked
in and ack nowledged by the E EPROM , the microcontroller must gen erate another start
con dition. The m icrocontroller now i nitiates a current address read by sendin g a d evice
address with the read/write select bit high. The EEPROM acknowledges the device
address and serially clocks out the data word . The microcontroller does not respond
with a “0” but does generate a follo wing stop condition (see Figure 12).
Figure 12. Random Read
S
T
A
R
T
SDA LINE
M
S
B
L
S
B
R
/
W
A
C
K
DATA N
O
A
C
K
DEVICE
ADDRESS
R
E
A
D
S
T
O
P
DEVICE
ADDRESS
DUMMY WRITE
SDA LINE
M
S
B
S
T
A
R
T
P0R
/
W
A
C
K
1st, 2nd WORD
ADDRESS n
A
C
K
S
T
A
R
T
A
C
K
DEVICE
ADDRESS
R
E
A
D
DATA n
S
T
O
P
N
O
A
C
K
W
R
I
T
E
L
S
B
0
11
AT24C1024SC
5045A–SEEPR–04/04
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or
a random address re ad. After the m icroc ontroller receives a data word, it r esponds with
an ac knowled ge. As long as the E EPRO M receives an acknowledge, it will conti nue to
incremen t the data word address and serially clock out sequential data words. When the
mem ory addres s li mi t is reac hed, the data word address will “roll over” and the sequen-
tial read will continue. The sequential read operation is terminated when the
microcont roller does not res pond with a “0” but does generate a following stop condition
(see Figure 13)
Figure 13. Sequential Read.
DEVICE
ADDRESS
DUMMY WRITE
SDA LINE
M
S
B
S
T
A
R
T
P0R
/
W
A
C
K
1st, 2nd WORD
ADDRESS n
A
C
K
S
T
A
R
T
A
C
K
DEVICE
ADDRESS
R
E
A
D
DATA n
S
T
O
P
N
O
A
C
K
W
R
I
T
E
L
S
B
0
12 AT24C1024SC 5045A–SEEPR–04/04
AT24C32SC Ordering Information
Note: 1. Formal drawings may be obta ined from an Atmel sa les office.
Order ing Code Package(1) Vol tage R an g e Temperature Range
AT24C1024SC-09AT M2 – A Module 2.7V–5.5V Commer cial (0°C–70°C)
AT24C1024SC-09BT M2 – B Module 2.7V–5.5V Comm ercial ( 0°C–70°C)
AT24C1024SC-10WI 7 mil Wafer 2. 7V–5.5V Industrial (−40°C–85°C)
Package Type(1) Description
M2 – A Module M2 ISO 7816 Smar t Card Module
M2 – B Module M2 ISO 7816 Smar t Card Module with Atmel Logo
13
AT24C1024SC
5045A–SEEPR–04/04
Smart C ard Module
Note: * 1
The module dimensions listed refer to the dimensions of the exposed metal contact
area. The actual dimensions of the module after excise or punching from the carrier tape
are generally 0.4 mm greater in both directions (i.e., a punched M2 module will yield
13.0 x 11.8 mm).
Module Size: M2
Dimension*: 12.6 x 11.4 [mm]
Glob Top: Square - 8.6 x 8.6 [mm]
Thickness: 0.58 [mm] max.
Pitch: 14.25 mm
Ordering Code: 09AT
Module Size: M2
Dimension*: 12.6 x 11.4 [mm]
Glob Top: Square - 8.6 x 8.6 [mm]
Thickness: 0.58 [mm] max.
Pitch: 14.25 mm
Ordering Code: 09BT
Pr inted o n rec ycled pa per.
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5045A–SEEPR–04/04
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