INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC * The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4093B gates Quadruple 2-input NAND Schmitt trigger Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification HEF4093B gates Quadruple 2-input NAND Schmitt trigger DESCRIPTION The HEF4093B consists of four Schmitt-trigger circuits. Each circuit functions as a two-input NAND gate with Schmitt-trigger action on both inputs. The gate switches at different points for positive and negative-going signals. The difference between the positive voltage (VP) and the negative voltage (VN) is defined as hysteresis voltage (VH). Fig.2 Pinning diagram. HEF4093BP(N): 14-lead DIL; plastic (SOT27-1) HEF4093BD(F): 14-lead DIL; ceramic (cerdip) HEF4093BT(D): 14-lead SO; plastic (SOT73) (SOT108-1) ( ): Package Designator North America Fig.3 Logic diagram (one gate). FAMILY DATA, IDD LIMITS category GATES See Family Specifications Fig.1 Functional diagram. January 1995 2 Philips Semiconductors Product specification HEF4093B gates Quadruple 2-input NAND Schmitt trigger DC CHARACTERISTICS VSS = 0 V; Tamb = 25 C VDD V Hysteresis SYMBOL 5 MIN. TYP. MAX. 0,4 0,7 - V 0,6 1,0 - V 15 0,7 1,3 - V Switching levels 5 1,9 2,9 3,5 V positive-going 10 3,6 5,2 7 V input voltage 15 4,7 7,3 11 V 5 1,5 2,2 3 4 voltage 10 negative-going input voltage VH VP 10 VN 15 Fig.5 Fig.4 Transfer characteristic. January 1995 3 3,1 V 4,2 6,4 V 6,0 10,3 V Waveforms showing definition of VP, VN and VH; where VN and VP are between limits of 30% and 70%. Philips Semiconductors Product specification HEF4093B gates Quadruple 2-input NAND Schmitt trigger AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Propagation delays In On HIGH to LOW LOW to HIGH Output transition times HIGH to LOW LOW to HIGH 5 package (P) TYPICAL EXTRAPOLATION FORMULA MAX. 90 185 ns 63 ns + (0,55 ns/pF) CL 40 80 ns 29 ns + (0,23 ns/pF) CL 30 60 ns 22 ns + (0,16 ns/pF) CL 5 85 170 ns 58 ns + (0,55 ns/pF) CL tPHL 40 80 ns 29 ns + (0,23 ns/pF) CL 15 30 60 ns 22 ns + (0,16 ns/pF) CL 5 60 120 ns 10 ns + (1,0 ns/pF) CL 10 tPLH 30 60 ns 9 ns + (0,42 ns/pF) CL 15 20 40 ns 6 ns + (0,28 ns/pF) CL 5 60 120 ns 10 tTHL 10 tTLH VDD V dissipation per TYP. 15 10 15 Dynamic power SYMBOL 10 ns + (1,0 ns/pF) CL 30 60 ns 9 ns + (0,42 ns/pF) CL 20 40 ns 6 ns + (0,28 ns/pF) CL TYPICAL FORMULA FOR P (W) 5 1300 fi + (foCL) x VDD2 where 10 6400 fi + (foCL) x VDD 2 fi = input freq. (MHz) 15 18 700 fi + (foCL) x VDD 2 fo = output freq. (MHz) CL = load capacitance (pF) (foCL) = sum of outputs VDD = supply voltage (V) January 1995 4 Philips Semiconductors Product specification HEF4093B gates Quadruple 2-input NAND Schmitt trigger Fig.6 Typical drain current as a function of input voltage; VDD = 5 V; Tamb = 25 C. Fig.8 Typical drain current as a function of input voltage; VDD = 15 V; Tamb = 25 C. January 1995 Fig.7 5 Typical drain current as a function of input voltage; VDD =10 V; Tamb = 25 C. Philips Semiconductors Product specification HEF4093B gates Quadruple 2-input NAND Schmitt trigger Fig.9 Typical switching levels as a function of supply voltage VDD; Tamb = 25 C. APPLICATION INFORMATION Some examples of applications for the HEF4093B are: * Wave and pulse shapers * Astable multivibrators * Monostable multivibrators. Fig.11 Schmitt trigger driven via a high impedance (R > 1 k). Fig.10 The HEF4093B used as a astable multivibrator. If a Schmitt trigger is driven via a high impedance (R > 1 k) then it is necessary to incorporate a capacitor C of such value that: C V DD - V SS ------- > -------------------------- , otherwise oscillation can occur on the edges of a pulse. VH Cp Cp is the external parasitic capacitance between inputs and output; the value depends on the circuit board layout. Note The two inputs may be connected together, but this will result in a larger through-current at the moment of switching. January 1995 6