COLUMBIA 16x12 PRELIMINARY Product Brief Part Number S19219PBI, Revision 1.4, August 2002 16xOC-12/OC-3 Mixed Rate SONET/SDH Framer and POS/ATM Mapper The Columbia 16x12 (S19219) is an integrated framer and mapper solution, optimized for dense OC-12c and OC-3c port-card applications in switches and routers. It supports sixteen dual mode OC-3c/OC-12c SONET/SDH line interfaces and sixteen data engines capable of processing independently Packet Over SONET (POS) or ATM traffic that is transferred to and from external packet processors through a OIF SPI-4 Phase 2 compliant-system interface. The Columbia 16x12 integrates SONET/SDH compliant multiplexing, de-multiplexing, and Clock and Data Recovery (CDR) functionality, and supports direct connection to OC-12 or OC-3 optics with no external components required. With Columbia's mixed OC-3c/OC-12c line operation on a per-port basis, dual-rate line cards can now replace multiple dedicated OC-3 and OC-12 line cards, resulting in better inventory management and significantly reduced Capital and Operating expenses for Carriers and Service providers. Combined with AMCC nP7570 10Gb/s full-duplex network processor, the Columbia 16x12 enables the design of low power, high-density port cards in Metro and edge switches and routers. * Supports Packet Over SONET (HDLC), ATM or Direct Map Mode on a per-line interface basis, allowing for termination of mixed traffic. FEATURES * Integrates sixteen SONET/SDH compliant line interfaces that support direct connection to optic modules at OC-3c or OC-12c rates. * POS/HDLC processing is compliant with IETF RFC2615 and RFC1662. * Support OC-3c or OC-12c operation on a per-line interface basis, allowing mixed 155Mb/s and 622MHz operation. * HDLC processors enable Ethernet over SDH (EoS) using LAPS (Link Access Procedure - SDH) framing per ITU-T draft X.86 as well as IP over SDH using LAPS (ITU X.85) * Integrated OC-12/OC-3 CSU/CDR functionality is fully compliant with the bit-error rate requirements of the Telcordia and ITU-T standards. * ATM processing is compliant with ITU-T I.432.1 and I.432.2, and ATM Forum UNI 3.1. * Supports independent line timing or common system reference timing in both OC-12c and OC-3c modes. * A dedicated low-power 4x2.488 Gb/s inter-chip interface with built-in clock and data recovery is provided to support 1:1 and 1+1 protection configurations. * Processes SONET (SDH) section (Regenerator Section), line (Multiplex Section) and path overhead in compliance with Telcordia GR-253, ANSI T1.105 and T1.416, and ITU-T G.707 and G.783. * Provides a 16-bit 800 MHz system interface compliant with the OIF SPI-4 Phase 2 recommendation. * 16-bit synchronous microprocessor interface for configuration, control, and status monitoring. X43+1 Descramb. SEL SPEGEN POHINS x16 TOHINSERT PROT_DATA_OUT[1:4] PROTFRMR TX_TOH_EN_IN TX_TOH_ID_OUT TX_TOH_CTRL_OUT STS-12c/3c HDLC/ATM RxProcessor x16 x4 X43+1 Scramb. STS-12c/3c HDLC/ATM TxProcessor x16 JTAG TDO TCK TMS TDI TRSTB TS_EN SYS_REFCLK_IN CSU POH MON x16 HDLC/ATMMON STS-12/3 TXFRMR x16 TX_TOH_CLK_OUT TX__DATA_OUT[1:16] GPIO [15:0] MICROPROCESSORI/F SEL PTR INT x16 TOHMON TX_TOH_DATA_IN[1:4] DR RX__DATA_IN[1:16] C x16 LINE INTERFACE RX_ALM_OUT[1:16] RSTB INTB D[15:0] ADDR[13:0] CSN WRB(RW B) RDYB(DTACKB) BUSMO DE APS_INTB UPCLK PROTFRMR x4 TOHEXTRACT STS-12/3 RXFRMR x16 * 0.13 micron CMOS, 1.2V/2.5V/3.3V technology. PROT_DATA_IN[1:4] RX_TOH_DATA_OUT[1:4] RX_TOH_ID_OUT RX_TOH_CTRL_OUT SYS_REFCLK_OUT RX_TOH_CLK_OUT * Supports full-duplex mapping of packets or cells into sixteen SONET/SDH tributaries at STS-12c/AU-4-4c or STS-3c/AU-4 rates. Figure 1: Block Diagram PRELIMINARY Information - The information contained in this document is about a product in its sample release stage and is subject to change without notice at any time. All features described herein are design goals. Contact AMCC for updates to this document and the latest product status. Empowering Intelligent Optical Networks RXSYSTEM INTERFACE FIFOx16 RDCLK RDAT[15:0] RCTL RSCLK RSTAT[1:0] SPI-4MON TXSYSTEM INTERFACE FIFOx16 TSTAT[1:0] TSCLK TDCLK TDAT[15:0] TCTL COLUMBIA 16x12 PRELIMINARY Product Brief 16xOC-12/OC-3 Mixed Rate SONET/SDH Framer and POS/ATM Mapper OVERVIEW AND APPLICATIONS POS HDLC Processing Line Interface The POS/HDLC framer of the Columbia 16x12 can process any mix of up to sixteen STS-12c/VC-4-4c or STS-3c/VC-4 channels. It is standards compliant with IETF RFC 1662 and RFC 2615. The Columbia 16x12 can operate either in OC-12c or in OC-3c SONET/SDH line configuration on a per-line basis. The line interfaces connect directly to OC-12 or OC-3 optics without the need for an external serializer/deserializer chip. The Columbia includes a high-frequency PLL to generate a highspeed transmit clock from a lower speed reference. In the receive direction, the Columbia 16x12 integrates sixteen independent Clock and Data Recovery (CDR) circuits that perform clock recovery on the incoming 622.08MHz (OC-12) or 155.52MHz (OC-3) signals. Independent line timing is supported in both OC-3 or OC-12 modes. By allowing each line interface to independently use its recovered clock in the transmit direction, the Columbia removes the need for expensive SONET/SDH compliant reference clocks in the system. The Columbia 16x12 is fully compliant with the Telcordia and ITUT bit-error rate requirements. It meets or exceeds the SONET/ SDH input jitter tolerance, jitter transfer, and jitter generation requirements specified in these standards. APS Interface The Columbia 16x12 provides a 10 Gb/s input/output port, consisting of four 2.488 Gb/s CML signals in each direction to support 1:1 and 1+1 protection configurations. The 2.488 Gb/s interface integrates the clock and data recovery function, removing the need for external components. The APS interface signal format follows the STS-48 SONET/SDH frame structure and supports protection for both STS-12c and STS-13c tributaries. Prior to transmission on the APS interface, the Columbia 16x12 provides frame alignment of the sixteen STS12c or STS-3c signals so that they can be multiplexed on the four 2.488 Gb/s physical interfaces. SONET/SDH Processing The Columbia 16x12 implements SONET/SDH processing functions for sixteen STS-12c/STM-4 or STS-3c/STM-1 data streams or a mix of both rates. It performs full section (Regenerator Section), line (Multiplex Section) and path overhead processing of all defined TOH/POH bytes, including framing, scrambling/descrambling, alarm signal (AIS) insertion/detection, remote failure insertion/detection (REI/RDI), section/path trace insertion/capture (J0/ J1), and bit interleaved parity (B1/B2/B3) processing. The Columbia 16x12 also provides programmable Signal Fail (SF) and Signal Degrade (SD) thresholds for B2 monitoring. The Columbia 16x12 is SONET and SDH standards compliant with Telcordia GR-253, GR-499, and GR-1377, and ANSI T1. 105-1995, and ITU G.707 and G.783. 2 Part Number S19219PBI, Revision 1.4, August 2002 Transmit HDLC processor (POS mode) In Packet Over SONET mode, the transmit HDLC processor encapsulates packets into HDLC frames that are subsequently mapped into the Synchronous Payload Envelope or Virtual Container. The HDLC processor optionally inserts provisioned address and control fields to the packets received from the system interface. The 32-bit Frame Check Sequence (FCS) is then generated unless the device is provisioned for external FCS insertion. The HDLC performs transparency processing and inter-frame time fill by adding flag sequences when no data is available for transmission. The HDLC-framed data stream can optionally be scrambled (X4 3+1) before being mapped in the SONET (SDH) SPE (VC). Receive HDLC processor (POS mode) In the receive direction, the data received from the SONET/SDH) SPE/VC is optionally de-scrambled (X 4 3+1). The receive HDLC processor provides for the delineation of HDLC frames by identifying the flag sequence that begins and ends each frame. It performs transparency removal, FCS error checking and can be provisioned to either drop the FCS or pass it through the system interface. The HDLC address and control fields are optionally checked and dropped or can be passed through the system interface. The Columbia 16x12 also provides a robust set of counters and status/control registers for performance monitoring via the microprocessor. LAPS (ITU X.85/X.86) Processing The HDLC processor of the Columbia 16x12 includes extensions to support IP over SDH using LAPS (ITU X.85) as well as Ethernet over SDH using LAPS (ITU X.86) applications. Link Access Procedure - SDH is a byte-stuffed HDLC framing protocol as defined in ISO-IEC3309. The LAPS HDLC framer of the Columbia 16x12 can process sixteen STS-12c/VC-4-4c or STS-3c/VC-4 channels. It is standards compliant with the ITU Study Group 7 Draft X.86 on Ethernet over LAPS as well as with ITU X.85. Transmit LAPS HDLC processor The transmit LAPS HDLC processor encapsulates packets into HDLC frames that are subsequently mapped into the Synchronous Payload Envelope or Virtual Container. Empowering Intelligent Optical Networks COLUMBIA 16x12 PRELIMINARY Product Brief Part Number S19219PBI, Revision 1.4, August 2002 16xOC-12/OC-3 Mixed Rate SONET/SDH Framer and POS/ATM Mapper It optionally inserts provisioned address and control fields and generates a 32-bit Frame Check Sequence (FCS). It also performs transparency processing and inter-frame time fill by adding flag sequences when no data is available for transmission. The LAPS processing additionally provides an intra-packet rate-adaptation method. A two-byte rate-adaptation sequence (0x7d,0xdd) is sent if no data is available and a frame transmission has not been completed. This sequence is provisionable. The LAPS HDLC framed data stream can optionally be scrambled (X43 +1) before being mapped in the SONET (SDH) SPE (VC). Receive LAPS HDLC processor The data received from the SONET/SDH) SPE/VC is optionally descrambled (X43 +1). The receive LAPS HDLC processor provides for the delineation of HDLC frames by identifying the flag sequence that begins and ends each frame. It performs transparency removal as well as optional FCS error checking and drop. The HDLC address and control fields are optionally checked and dropped or can be passed through the system interface. The receive LAPS processor provides the ability to detect and delete the intra-frame two-byte rate adaptation sequence defined by the Ethernet over LAPS standard. The Columbia 16x12 also provides a robust set of counters and status/control registers for performance monitoring via the microprocessor. System Packet Interface The Columbia 16x12 provides a Flexbus TM 4 Phase 2 system interface to allow the transfer of packets or ATM cells between the Columbia 16x12 and a link layer device. This 16-bit wide LVDS bus can operate at speeds of up to 800MHz and is compliant with the OIF SPI4 Phase 2 specification. It provides in-band port addresses, start/endof-packet indications and error control codes and supports multi-PHY operation for up to 16 tributaries. For each tributary, transmit and receive FIFOs are 1KByte deep. This interface supports both static and dynamic phase alignment and includes both low-speed TTL as well as high-speed LVDS FIFO status channels. Transmit-to-receive and receive-to-transmit loopback functionality is available for diagnostic and test purposes. Microprocessor Interface The Columbia 16x12 supports a 16-bit synchronous microprocessor interface for device control and monitoring. The interface supports both Intel and Motorola type microprocessors, and is capable of operating in either interrupt-driven or polled-mode configurations. Maximum operating frequency is 66MHz. AMCC Companion Devices * AMCC nP7570 full-duplex 10Gb/s network. ATM Processing The Columbia 16x12 can be configured for ATM processing on a perline basis. It can process sixteen STS-12c/VC4-4c or STS-3c/VC-4 tributaries carrying ATM traffic. The transmit ATM processor performs all necessary cell processing including optional HEC generation, idle cell insertion to adapt the cell rate to the SPE/VC rate and cell level scrambling (X4 3+1). When receiving data from the line side, the receive ATM processor performs cell payload de-scrambling (X43 +1), cell delineation, optional Idle cell deletion, HEC check and optional drop. Applications * Dense, low-power and dual rate OC-12/3 POS/ATM Port Cards in switches and routers. * Dense OC-3 connectivity in equipment architected for 10Gb/s using SPI-4 Phase 2 based chipsets. * Ethernet over SONET/SDH over LAPS applications. The columbia 16x12 is ATM standards compliant with ATM Forum UNI 3.1, ITU-T I.432.1 and I.432.2. Direct Map Mode Direct Map Mode permits the user to have full control over SONET/ SDH Synchronous Payload Envelope/Virtual Container and therefore map any protocol into SONET/SDH. In this mode, the user is responsible for providing data at the SPE/VC rate. For additional flexibility, the Columbia 16x12 can optionally be provisioned to add FIFO underflow stuff bytes and a subset of the HDLC processor is used to perform transparency processing of underflow bytes and Control Escape characters. The Columbia 16x12 can also be provisioned to perform X 4 3+1 payload scrambling and descrambling in direct map mode. Empowering Intelligent Optical Networks 3 COLUMBIA 16x12 PRELIMINARY Product Brief Part Number S19219PBI, Revision 1.4, August 2002 16xOC-12/OC-3 Mixed Rate SONET/SDH Framer and POS/ATM Mapper 16-bit 800MHz 155 / 622.08MHz OC-12/3 Optics 16 ports Mixed OC-12c/OC-3c POS/ATM Port Card x16 OC-12/3 Optics OC-12c/3c Framer L I N E POH Proc HDLC ATM S P I 4 x16 I F OC-12c/3c Framer POH Proc nP7570 10Gb/s Network Processor nPX5700 Traffic Manager Backplane HDLC ATM COLUMBIA 16x12 Packet/Cell Switch Fabric 4x2.488GHz OC-48 Optics 4xOC-48 POS/ATM Port Card OC-48 Optics OC-48 Framer OC-48 Framer OC-48 Framer OC-48 Framer L I N E OC-48 Optics OC-48 Optics I F POH Proc POH Proc HDLC ATM POH Proc POH Proc HDLC ATM HDLC ATM HDLC ATM S P I 4 nP7570 10Gb/s Network Processor nPX5700 Traffic Manager Backplane S P I 4 nP7570 10Gb/s Network Processor nPX5700 Traffic Manager Backplane COLUMBIA 4x48 SFI-4 Phase 2 - 4x2.566Gb/s SFI-4 - 16x622MHz XSBI - 16-bit, 644.53MHz LVDS 10 GE LAN/WAN OC-192c POS Port Card AMCC text S19215 OC-192/10GbE LAN/WAN pluggable XENPAK or 300 pin MSA L I N E I F OC-192 Framer WIS POH Proc PCS 64B/66B HDLC 10GbE MAC COLUMBIA 192 Figure 2: Typical Configurations for Columbia 16x12 AMCC reserves the right to make changes to its products, or to discontinue any product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied upon is cu rrent. AMCC is a registered trademark of Applied Micro Circuits Corporation. Copyright (c) 2002 Applied Micro Circuits Corporation. All Rights Reserved. 200 Minuteman Road * Andover, MA 01810 * Tel: 978-247-8000 * Fax: 978-623-0024 * http:// 4 Empowering Intelligent Optical Networks AMCC Cyclone or nPX5800