PRELIMINARY Information - The information contained in this document is
about a product in its sample release stage and is subject to change without
notice at any time. All features described herein are design goals. Contact AMCC
for updates to this document and the latest product status.
Empowering Intelligent Optical Networks
PRELIMINARY Product Brief
COLUMBIA 16x12
16xOC-12/OC-3 Mixed Rate SONET/SDH Framer and POS/ATM Mapper Part Number S19219PBI, Revision 1.4, August 2002
FEATURES
•Integrates sixteen SONET/SDH compliant line interfaces that
support direct connection to optic modules at OC-3c or OC-12c
rates.
•Support OC-3c or OC-12c operation on a per-line interface
basis, allowing mixed 155Mb/s and 622MHz operation.
•Integrated OC-12/OC-3 CSU/CDR functionality is fully compli-
ant with the bit-error rate requirements of the Telcordia and
ITU-T standards.
•Supports independent line timing or common system reference
timing in both OC-12c and OC-3c modes.
•Processes SONET (SDH) section (Regenerator Section), line
(Multiplex Section) and path overhead in compliance with Tel-
cordia GR-253, ANSI T1.105 and T1.416, and ITU-T G.707
and G.783.
•Supports full-duplex mapping of packets or cells into sixteen
SONET/SDH tributaries at STS-12c/AU-4-4c or STS-3c/AU-4
rates.
•Supports Packet Over SONET (HDLC), ATM or Direct Map
Mode on a per-line interface basis, allowing for termination of
mixed traffic.
•POS/HDLC processing is compliant with IETF RFC2615 and
RFC1662.
•HDLC processors enable Ethernet over SDH (EoS) using
LAPS (Link Access Procedure - SDH) framing per ITU-T draft
X.86 as well as IP over SDH using LAPS (ITU X.85)
•ATM processing is compliant with ITU-T I.432.1 and I.432.2,
and ATM Forum UNI 3.1.
•A dedicated low-power 4x2.488 Gb/s inter-chip interface with
built-in clock and data recovery is provided to support 1:1 and
1+1 protection configurations.
•Provides a 16-bit 800 MHz system interface compliant with the
OIF SPI-4 Phase 2 recommendation.
•16-bit synchronous microprocessor interface for configuration,
control, and status monitoring.
•0.13 micron CMOS, 1.2V/2.5V/3.3V technology.
The Columbia 16x12 (S19219) is an integrated framer and mapper solution, optimized for dense OC-12c and OC-3c port-card applica-
tions in switches and routers. It supports sixteen dual mode OC-3c/OC-12c SONET/SDH line interfaces and sixteen data engines capa-
ble of processing independently Packet Over SONET (POS) or ATM traffic that is transferred to and from external packet processors
through a OIF SPI-4 Phase 2 compliant-system interface. The Columbia 16x12 integrates SONET/SDH compliant multiplexing, de-multi-
plexing, and Clock and Data Recovery (CDR) functionality, and supports direct connection to OC-12 or OC-3 optics with no external
components required. With Columbia’s mixed OC-3c/OC-12c line operation on a per-port basis, dual-rate line cards can now replace
multiple dedicated OC-3 and OC-12 line cards, resulting in better inventory management and significantly reduced Capital and Operating
expenses for Carriers and Service providers. Combined with AMCC nP7570 10Gb/s full-duplex network processor, the Columbia 16x12
enables the design of low power, high-density port cards in Metro and edge switches and routers.
Figure 1: Block Diagram
LINE INTERFACE
TDAT[15:0]
POH INS
TX_TOH_CLK_OUT
TX_TOH_ID_OUT
TX_TOH_DATA_IN[1:4]
TSCLK
D[15:0]
ADDR[13:0]
CSN
WRB(RWB)
RDYB(DTACKB)
BUSMODE
INTB
MICROPROCESSOR I/F
RSTB
APS_INTB
PROT_DATA_OUT[1:4]PROT_DATA_IN[1:4]
RX_TOH_CLK_OUT
RX_TOH_ID_OUT
RX_TOH_DATA_OUT[1:4]
TOH INSERT
FIFO x16
INTERFACE
SYS_REFCLK_INSYS_REFCLK_OUT
RX_ALM_OUT[1:16]
UPCLK
GPIO[15:0]
TCK
TDO
TMS
TDI
TRSTB
TS_EN
SPE GEN STS-12c/3c
Tx Processor
SEL
TCTL
TDCLK
TSTAT[1:0]
x16
PROT FRMR
x4
TX__DATA_OUT[1:16]
x16
HDLC/ATM
TOH EXTRACT
RDAT[15:0]
TOH MON
RSCLK
PROT FRMR
RX SYSTEM
FIFO x16
INTERFACE
JTAG
RDCLK
RCTL
RSTAT[1:0]
x4
RX__DATA_IN[1:16] CDR
x16
STS-12c/3c
Rx Processor
x16
HDLC/ATM
TX SYSTEM
STS-12/3
x16
RX FRMR
STS-12/3
x16
TX FRMR
X
43
+1
Descramb.
X
43
+1
Scramb.
HDLC/ATM MON SPI-4 MON
CSU
TX_TOH_CTRL_OUT
TX_TOH_EN_IN RX_TOH_CTRL_OUT
PTRx16
INT
SEL POH
MON
x16
2Empowering Intelligent Optical Networks
PRELIMINARY Product Brief
COLUMBIA 16x12
16xOC-12/OC-3 Mixed Rate SONET/SDH Framer and POS/ATM Mapper Part Number S19219PBI, Revision 1.4, August 2002
OVERVIEW AND APPLICATIONS
Line Interface
The Columbia 16x12 can operate either in OC-12c or in OC-3c
SONET/SDH line configuration on a per-line basis.
The line interfaces connect directly to OC-12 or OC-3 optics with-
out the need for an external serializer/deserializer chip. The
Columbia includes a high-frequency PLL to generate a high-
speed transmit clock from a lower speed reference. In the receive
direction, the Columbia 16x12 integrates sixteen independent
Clock and Data Recovery (CDR) circuits that perform clock recov-
ery on the incoming 622.08MHz (OC-12) or 155.52MHz (OC-3)
signals.
Independent line timing is supported in both OC-3 or OC-12
modes. By allowing each line interface to independently use its
recovered clock in the transmit direction, the Columbia removes
the need for expensive SONET/SDH compliant reference clocks
in the system.
The Columbia 16x12 is fully compliant with the Telcordia and ITU-
T bit-error rate requirements. It meets or exceeds the SONET/
SDH input jitter tolerance, jitter transfer, and jitter generation
requirements specified in these standards.
APS Interface
The Columbia 16x12 provides a 10 Gb/s input/output port,
consisting of four 2.488 Gb/s CML signals in each direction to
support 1:1 and 1+1 protection configurations. The 2.488 Gb/s
interface integrates the clock and data recovery function,
removing the need for external components.
The APS interface signal format follows the STS-48 SONET/SDH
frame structure and supports protection for both STS-12c and
STS-13c tributaries. Prior to transmission on the APS interface,
the Columbia 16x12 provides frame alignment of the sixteen STS-
12c or STS-3c signals so that they can be multiplexed on the four
2.488 Gb/s physical interfaces.
SONET/SDH Processing
The Columbia 16x12 implements SONET/SDH processing func-
tions for sixteen STS-12c/STM-4 or STS-3c/STM-1 data streams
or a mix of both rates. It performs full section (Regenerator Sec-
tion), line (Multiplex Section) and path overhead processing of all
defined TOH/POH bytes, including framing, scrambling/descram-
bling, alarm signal (AIS) insertion/detection, remote failure inser-
tion/detection (REI/RDI), section/path trace insertion/capture (J0/
J1), and bit interleaved parity (B1/B2/B3) processing. The Colum-
bia 16x12 also provides programmable Signal Fail (SF) and Sig-
nal Degrade (SD) thresholds for B2 monitoring.
The Columbia 16x12 is SONET and SDH standards compliant
with Telcordia GR-253, GR-499, and GR-1377, and ANSI T1.
105-1995, and ITU G.707 and G.783.
POS HDLC Processing
The POS/HDLC framer of the Columbia 16x12 can process any
mix of up to sixteen STS-12c/VC-4-4c or STS-3c/VC-4 channels.
It is standards compliant with IETF RFC 1662 and RFC 2615.
Transmit HDLC processor (POS mode)
In Packet Over SONET mode, the transmit HDLC processor
encapsulates packets into HDLC frames that are subsequently
mapped into the Synchronous Payload Envelope or Virtual Con-
tainer.
The HDLC processor optionally inserts provisioned address and
control fields to the packets received from the system interface.
The 32-bit Frame Check Sequence (FCS) is then generated
unless the device is provisioned for external FCS insertion.
The HDLC performs transparency processing and inter-frame
time fill by adding flag sequences when no data is available for
transmission.
The HDLC-framed data stream can optionally be scrambled
(X43
+1) before being mapped in the SONET (SDH) SPE (VC).
Receive HDLC processor (POS mode)
In the receive direction, the data received from the SONET/SDH)
SPE/VC is optionally de-scrambled (X43
+1). The receive HDLC
processor provides for the delineation of HDLC frames by identify-
ing the flag sequence that begins and ends each frame. It per-
forms transparency removal, FCS error checking and can be
provisioned to either drop the FCS or pass it through the system
interface. The HDLC address and control fields are optionally
checked and dropped or can be passed through the system inter-
face.
The Columbia 16x12 also provides a robust set of counters and
status/control registers for performance monitoring via the micro-
processor.
LAPS (ITU X.85/X.86) Processing
The HDLC processor of the Columbia 16x12 includes extensions
to support IP over SDH using LAPS (ITU X.85) as well as Ether-
net over SDH using LAPS (ITU X.86) applications. Link Access
Procedure - SDH is a byte-stuffed HDLC framing protocol as
defined in ISO-IEC3309.
The LAPS HDLC framer of the Columbia 16x12 can process six-
teen STS-12c/VC-4-4c or STS-3c/VC-4 channels. It is standards
compliant with the ITU Study Group 7 Draft X.86 on Ethernet over
LAPS as well as with ITU X.85.
Transmit LAPS HDLC processor
The transmit LAPS HDLC processor encapsulates packets into
HDLC frames that are subsequently mapped into the Synchro-
nous Payload Envelope or Virtual Container.
Empowering Intelligent Optical Networks 3
PRELIMINARY Product Brief
COLUMBIA 16x12
16xOC-12/OC-3 Mixed Rate SONET/SDH Framer and POS/ATM Mapper Part Number S19219PBI, Revision 1.4, August 2002
It optionally inserts provisioned address and control fields and gener-
ates a 32-bit Frame Check Sequence (FCS). It also performs trans-
parency processing and inter-frame time fill by adding flag sequences
when no data is available for transmission.
The LAPS processing additionally provides an intra-packet rate-adap-
tation method. A two-byte rate-adaptation sequence (0x7d,0xdd) is
sent if no data is available and a frame transmission has not been
completed. This sequence is provisionable.
The LAPS HDLC framed data stream can optionally be scrambled
(X43+1) before being mapped in the SONET (SDH) SPE (VC).
Receive LAPS HDLC processor
The data received from the SONET/SDH) SPE/VC is optionally
descrambled (X43+1). The receive LAPS HDLC processor provides for
the delineation of HDLC frames by identifying the flag sequence that
begins and ends each frame. It performs transparency removal as well
as optional FCS error checking and drop. The HDLC address and con-
trol fields are optionally checked and dropped or can be passed
through the system interface.
The receive LAPS processor provides the ability to detect and delete
the intra-frame two-byte rate adaptation sequence defined by the
Ethernet over LAPS standard.
The Columbia 16x12 also provides a robust set of counters and sta-
tus/control registers for performance monitoring via the microproces-
sor.
ATM Processing
The Columbia 16x12 can be configured for ATM processing on a per-
line basis. It can process sixteen STS-12c/VC4-4c or STS-3c/VC-4
tributaries carrying ATM traffic.
The transmit ATM processor performs all necessary cell processing
including optional HEC generation, idle cell insertion to adapt the cell
rate to the SPE/VC rate and cell level scrambling (X43+1).
When receiving data from the line side, the receive ATM processor
performs cell payload de-scrambling (X43+1), cell delineation, optional
Idle cell deletion, HEC check and optional drop.
The columbia 16x12 is ATM standards compliant with ATM Forum
UNI 3.1, ITU-T I.432.1 and I.432.2.
Direct Map Mode
Direct Map Mode permits the user to have full control over SONET/
SDH Synchronous Payload Envelope/Virtual Container and therefore
map any protocol into SONET/SDH. In this mode, the user is
responsible for providing data at the SPE/VC rate. For additional flexi-
bility, the Columbia 16x12 can optionally be provisioned to add FIFO
underflow stuff bytes and a subset of the HDLC processor is used to
perform transparency processing of underflow bytes and Control
Escape characters. The Columbia 16x12 can also be provisioned to
perform X43
+1 payload scrambling and descrambling in direct map
mode.
System Packet Interface
The Columbia 16x12 provides a FlexbusTM 4 Phase 2 system inter-
face to allow the transfer of packets or ATM cells between the Colum-
bia 16x12 and a link layer device. This 16-bit wide LVDS bus can
operate at speeds of up to 800MHz and is compliant with the OIF SPI-
4 Phase 2 specification. It provides in-band port addresses, start/end-
of-packet indications and error control codes and supports multi-PHY
operation for up to 16 tributaries. For each tributary, transmit and
receive FIFOs are 1KByte deep.
This interface supports both static and dynamic phase alignment and
includes both low-speed TTL as well as high-speed LVDS FIFO status
channels.
Transmit-to-receive and receive-to-transmit loopback functionality is
available for diagnostic and test purposes.
Microprocessor Interface
The Columbia 16x12 supports a 16-bit synchronous microprocessor
interface for device control and monitoring. The interface supports
both Intel and Motorola type microprocessors, and is capable of oper-
ating in either interrupt-driven or polled-mode configurations. Maxi-
mum operating frequency is 66MHz.
AMCC Companion Devices
•AMCC nP7570 full-duplex 10Gb/s network.
Applications
•Dense, low-power and dual rate OC-12/3 POS/ATM
Port Cards in switches and routers.
•Dense OC-3 connectivity in equipment architected for
10Gb/s using SPI-4 Phase 2 based chipsets.
•Ethernet over SONET/SDH over LAPS applications.
AMCC reserves the right to make changes to its products, or to discontinue any product or service without notice, and advises its customers to
obtain the latest version of relevant information to verify, before placing orders, that the information being relied upon is current.
AMCC is a registered trademark of Applied Micro Circuits Corporation. Copyright © 2002 Applied Micro Circuits Corporation. All Rights Reserved.
200 Minuteman Road • Andover, MA 01810 • Tel: 978-247-8000 • Fax: 978-623-0024 • http://
4Empowering Intelligent Optical Networks
PRELIMINARY Product Brief
COLUMBIA 16x12
16xOC-12/OC-3 Mixed Rate SONET/SDH Framer and POS/ATM Mapper Part Number S19219PBI, Revision 1.4, August 2002
Figure 2: Typical Configurations for Columbia 16x12
16-bit
800MHz
HDLC
ATM
POH
Proc
L
I
N
E
I
F
OC-12c/3c
Framer S
P
I
4
16 ports Mixed
OC-12c/OC-3c
POS/ATM
Port Card POH
Proc
OC-12/3 Optics
COLUMBIA 16x12
155 / 622.08MHz
nP7570
10Gb/s
Network
Processor
nPX5700
Traffic
Manager
HDLC
ATM
x16 x16
Packet/Cell
Switch
Fabric
AMCC
Cyclone
or
nPX5800
Backplane
POH
Proc
L
I
N
E
I
F
OC-48
Framer S
P
I
4
4xOC-48
POS/ATM
Port Card POH
Proc
OC-48
Framer POH
Proc
OC-48
Framer POH
Proc
OC-48
Framer
OC-48 Optics
OC-48 Optics
OC-48 Optics
OC-48 Optics
COLUMBIA 4x48
4x2.488GHz
nPX5700
Traffic
Manager
Backplane
text
AMCC
S19215
SFI-4 Phase 2 - 4x2.566Gb/s
SFI-4 - 16x622MHz
XSBI - 16-bit, 644.53MHz
LVDS
10GbE
MAC
OC-192/10GbE
LAN/WAN
pluggable XENPAK
or 300 pin MSA COLUMBIA 192
PCS
64B/66B
OC-192
Framer
WIS
S
P
I
4
10 GE LAN/WAN
OC-192c POS
Port Card
nPX5700
Traffic
Manager
Backplane
HDLC
POH
Proc
L
I
N
E
I
F
nP7570
10Gb/s
Network
Processor
nP7570
10Gb/s
Network
Processor
HDLC
ATM
HDLC
ATM
HDLC
ATM
HDLC
ATM
OC-12c/3c
Framer
OC-12/3 Optics
