Features
• Bluetooth radio
– Fully embedded Bluetooth® v3.0 with SPP and HID profiles
– Class 2 module
– Enhanced data rate (EDR) support
– Complete RF-ready module
– Embedded support for MFi iAP2 profile
– 128-bit encryption security
– Integrated antenna
• ST Cortex-M4 microprocessor
– Up to 100 MHz
– 512 kB Flash
– 128 kB RAM
• Supports transmission speed with SPP up to 1.5 Mbit/s
• 8 general-purpose I/Os
• User interface
– AT command data package (DP)
– Firmware upgrade over UART
• EU, FCC, IC and Bluetooth qualified
• Single voltage supply: 3.3 V typical
• Micro-sized form factor: 11.6 x 13.5 x 2.9 mm
• Operating temperature range: -40 °C to 85 °C
• RoHS compliance
Maturity status link
SPBT3.0DP2
Device summary
Order code SPBT3.0DP2
Description Class 2 OEM
Bluetooth antenna
module
Packing JEDEC tray
MOQ 2448 pcs
Bluetooth® Classic module
SPBT3.0DP2
Datasheet
DS11599 - Rev 6 - February 2018
For further information contact your local STMicroelectronics sales office.
www.st.com
1Description
The SPBT3.0DP2 is an easy-to-use Bluetooth module that is compliant with Bluetooth v3.0.
The module has among the smallest form factors available in a complete Class 2 RF platform. The SPBT3.0DP2
enables electronic devices with wireless connectivity, requiring no RF experience or expertise to integrate into the
final product. As a certified solution, the SPBT3.0DP2 module optimizes time-to-market for end-applications.
The module is designed for maximum performance in a minimal space including high speed UART and 8 general
purpose I/O lines, and up to 1.5 Mbps transmission speed with SPP service active and 1 Mbps with iAP2 service
active.
Its optimized design allows the integration of a complete working Bluetooth modem, including antenna, in the
smallest possible size.
Deep Sleep mode reduces power consumption when a Bluetooth connection is not established.
The SPBT3.0DP2 is a surface-mount PCB module that provides fully embedded, ready-to-use Bluetooth wireless
technology. The reprogrammable Flash memory contains embedded firmware for serial cable replacement using
the Bluetooth SPP profile. Embedded Bluetooth data package (DP) firmware provides a user-friendly interface,
offering simple control for cable replacement and enabling communication with most Bluetooth-enabled devices
that support the SPP profile. The SPBT3.0DP2 supports the iAP2 profile, allowing communication with the newest
Apple® iOS Bluetooth-enabled devices.
An Apple authentication IC is required to exchange data with an Apple device or access an Apple device
application. The DP FW includes a Bluetooth iAP2 profile capable of recognizing the Apple authentication chip.
Customers using the Apple authentication IC must register as developers to become an Apple certified MFi
member. License fees may apply. For additional information, please visit the Apple developer website.
Certified MFi developers developing electronic accessories that connect to the iPod®, iPhone® and iPad®, gain
access to technical documentation, hardware components, technical support and certification logos.
Customized firmware for peripheral device interaction, power optimization, security, and other proprietary features
may be supported and can be ordered pre-loaded and configured.
SPBT3.0DP2
Description
DS11599 - Rev 6 page 2/31
3Software architecture
Figure 2. Software architecture overview
3.1 BT stack layers
• Bluetooth v3.0
• Device power modes: active, deep sleep
• Connection modes: active, sniff
• Wake on Bluetooth feature optimizes power consumption of host CPU
SPBT3.0DP2
Software architecture
DS11599 - Rev 6 page 4/31
• Authentication and encryption
• Encryption key length from 8 bits to 128 bits
• Secure simple pairing support
• Persistent Flash memory for BD address and user parameter storage
• All ACL (asynchronous connection-less) packet types
• Master/slave switch supported during connection and post connection
• Dedicated inquiry access code for improved inquiry scan performance
• Dynamic packet selection channel quality-driven data rate to optimize link performance
• Dynamic power control
• Bluetooth radio natively supports 802.11b co-existence AFH
• RFCOMM, SDP, and L2CAP protocols supported
3.2 Supported profile
• Serial port profile (SPP)
• Human interface device (HID)
• iPhone accessory profile 2 (iAP2)
• Device identification profile (DID)
3.3 AT command set: Data Package
The complete command list is available in user manual UM2077 SPBT3.0DPx data package, which you can
download from www.st.com.
SPBT3.0DP2
Supported profile
DS11599 - Rev 6 page 5/31
4Module block diagram
Figure 3. SPBT3.0DP2 block diagram
SPBT3.0DP2
Module block diagram
DS11599 - Rev 6 page 6/31
5Hardware specifications
General conditions (VIN = 3.3 V and 25 °C).
5.1 Recommended operating conditions
Table 1. Recommended operating conditions
Rating Min. Typical Max. Unit
Operating temperature range - 40 - +8 5 °C
Supply voltage VIN 2.1 3.3 3.6 V
Signal pin voltage - 1.8 - V
5.2 Radio features
Table 2. Radio features
Feature Min. Typical Max. Unit
Bluetooth version - 3.0 -
Bluetooth class - 2 -
Radiated transmit power - - +2.6 dBm
Receiver sensitivity - -88 - dBm
RF frequency 2402 - 2480 MHz
5.3 Absolute maximum ratings
Table 3. Absolute maximum ratings
Rating Min. Typical Max. Unit
Storage temperature range -40 - +85 °C
Supply voltage, VIN -0.3 - +5.5 V
I/O pin voltage, VIO -0.3 +1.8 +2.1(1) V
1. for pins not 5 V tolerant
5.4 Current consumption
Test conditions:
• Temperature: 25 °C
• Configuration variables:
– CpuMHz:
◦ 84 MHz (default)
◦ 13 MHz (minimum)
– UseExtLPO:
◦ Internal LPO: FALSE (default)
SPBT3.0DP2
Hardware specifications
DS11599 - Rev 6 page 7/31
◦ External LPO: TRUE
– HostDeepSleepEnable:
◦ Active mode: FALSE (default)
◦ Deep Sleep mode: TRUE
– PageScan:
◦ with Page Scan: TRUE (default)
◦ No Page Scan: FALSE
◦ duration: 11.25 msec (default)
◦ interval: 1.25 sec (default)
– InquiryScan:
◦ With Inquiry scan: TRUE (default)
◦ No Inquiry scan: FALSE
◦ duration: 11.25 msec (default)
◦ interval: 1.25 sec (default)
– AllowSniff:
◦ Active Mode: FALSE (default)
◦ Sniff Mode: TRUE
• Sniff mode tested vs. phone powered by Android OS version 5.1.1
Table 4. Power consumption in standby (no connection)
Mode
Typical
Unit
84 MHz 13 MHz
Deep sleep, no page/inquiry scan, external LPO 130 130 μA
Deep sleep, with page/inquiry scan, external LPO 690 690 μA
Deep sleep, no page/inquiry scan, internal LPO 4.9 1.7 mA
Deep sleep, with page/inquiry scan, internal LPO 5.4 2.2 mA
Active, with page/inquiry scan, deep sleep enabled 6.6 2.4 mA
Active, with page/inquiry scan, deep sleep disabled 8.3 4.2 mA
Table 5. Power consumption during connection
Mode
Typical
Unit
84 MHz 13 MHz
Active, master role, no data traffic 9.0 4.9 mA
Active, slave role, no data traffic 11.2 7.0 mA
Active, master role, 90 kbps data transmission 16 13.5 mA
Active, slave role, 90 kbps data transmission 18 14 mA
Active, slave role, 450 kbps data transmission 26 (1) N.A. mA
Sniff, deep sleep enabled 6.8 1.9 (2) mA
Sniff, deep sleep disabled 8.7 3.7 (2) mA
1. Peak current during transmission: 80 mA.
2. External LPO required for sniff mode @ 13 MHz CPU frequency.
SPBT3.0DP2
Current consumption
DS11599 - Rev 6 page 8/31
5.5 I/O operating characteristics
Table 6. I/O operating characteristics
Symbol Parameter Min. Max. Unit Conditions
VIL Low-level input voltage - 0.5 V VIN, 3.3 V
VIH High-level input voltage 1.3 - V VIN, 3.3 V
VOL Low-level output voltage - 0.5 V VIN, 3.3 V
VOH High-level output voltage 1.4 - V VIN, 3.3 V
IOL Low-level output current - 4 (1) mA VOL = 0.4 V
IOH High-level output current - 4 (1) mA VOH = 1.8 V
RPU Pull-up resistor 30 50 kΩ Resistor turned on (2)
RPD Pull-down resistor 30 50 kΩ Resistor turned on (2)
1. GPIO14 max sunk or sourced current is limited to 3mA. The speed should not exceed 2 MHz with a maximum load of 30 pF.
This I/O must not be used as a current source (e.g. to drive an LED).
2. Normally not used. Firmware dependent.
5.6 Pin assignment
Figure 4. Pin assignment
SPBT3.0DP2
I/O operating characteristics
DS11599 - Rev 6 page 9/31
Table 7. Pin assignment
Pin Name Description I/O Note
1 GPIO1 GPIO indicating BT connection status
- 1: BT connection is active
- 0: BT connection is not active
O 5 V tolerant
2 GPIO2 General purpose I/O I/O
3 GPIO3 General purpose I/O I/O 5 V tolerant
4 GPIO4 GPIO indicating module power status
- 1: active mode
- 0: Deep Sleep Mode
O
5 GPIO5 I2C_SDA line for MFi chip or general purpose I/O I/O 5 V tolerant
6 GPIO6 I2C_SCL line for MFi chip or general purpose I/O I/O 5 V tolerant
7 GND Reference ground NA
8 Vin Main power supply input NA
9 Boot 0 Boot 0 pin I
10 RESETn Reset input (active low for 5 ms) I
11 CTS Clear to send (active low) I 5 V tolerant
12 RTS Request to send (active low) O 5 V tolerant
13 RXD Receive data I 5 V tolerant
14 TXD Transmit data O 5 V tolerant
15 LPO Low power 32 KHz oscillator I/O See Section 7.5 External LPO input circuit
16 GPIO8 General purpose I/O I/O 5 V tolerant
17 GPIO7 General purpose I/O I/O 5 V tolerant
18 +1.8V OUT +1.8 V out (max 10 mA) NA
Note: Some GPIOs can be configured with alternate functions. For details refer to the AT Command Data Package
user manual.
SPBT3.0DP2
Pin assignment
DS11599 - Rev 6 page 10/31
6Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK®
packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions
and product status are available at: www.st.com. ECOPACK® is an ST trademark.
6.1 RF module package information
Figure 5. RF module package outline
SPBT3.0DP2
Package information
DS11599 - Rev 6 page 11/31
Figure 6. Recommended land pattern (top view)
SPBT3.0DP2
RF module package information
DS11599 - Rev 6 page 12/31
7Hardware design
The SPBT3.0DP2 module with Data Package embedded firmware supports UART, I²C and GPIO hardware
interfaces.
Note:
• All unused pins (including the additional 6 pads on bottom side) should be left floating; do not ground.
• All GND pins must be well grounded.
• The area around the module should be free of any ground planes, power planes, trace routings, or metal for
6 mm from the module antenna position, in all directions.
• Traces should not be routed under the module.
7.1 Reflow soldering
The SPBT3.0DP2 is a high temperature-strength surface-mount Bluetooth module supplied on a PCB with the
following characteristics: 18-pin, 6-layer. The recommended final assembly reflow profiles are indicated below.
The soldering phase must be executed with care. To prevent undesired melting, particular attention must be paid
to the setup of the peak temperature.
The following soldering indications are based on temperature profile recommendations.
Table 8. Soldering
Profile feature PB-free assembly
Average ramp-up rate (TSMAX to TP) 3 °C/sec max
Preheat:
– Temperature min. (TS min.)
– Temperature max. (TS max.)
– Time (ts min. to ts max.)(ts)
150 °C
200 °C
60-100 sec
Time maintained above:
– Temperature TL
– Temperature TL
217 °C
60-70 sec
Peak temperature (TP) 240 + 0 °C
Time within 5 °C of actual peak temperature (TP) 10-20 sec
Ramp-down rate 6 °C/sec
Time from 25 °C to peak temperature 8 minutes max.
SPBT3.0DP2
Hardware design
DS11599 - Rev 6 page 13/31
Figure 7. Soldering profile
7.2 UART interface
The UART is compatible with the 16550 industry standard. Four signals are provided with the UART interface.
The TXD and RXD pins are used for data, while the CTS and RTS pins are used for flow control.
Figure 8. Connection to host device
SPBT3.0DP2
UART interface
DS11599 - Rev 6 page 14/31
Figure 9. Typical RS232 circuit
7.3 GPIO interface
Module GPIO configuration depends on the Data Package embedded firmware.
By default the GPIO1, GPIO4, GPIO5 and GPIO6 have specific functions.The remaining GPIOs are available to
the HOST processor that can configure them as GPIO or as alternate function ( HostMode_Sel, HostMode_Ind,
Host_WakeUp, Factory_Reset).
GPIO1: Bluetooth Connection Status
• 0: BT connection not present
• 1: BT connection is present
GPIO4: Module Power Status
• 1: module is in Active Mode
• Blinking: module is in Deep Sleep Mode
GPIO5: I2C SDA pin to be connected to MFi co-processor. External pull-up resistor is needed. It can be used as
GPIO if MFi chip is not used.
GPIO6: I2C SCL pin to be connected to MFi co-processor. External pull-up resistor is needed. It can be used as
GPIO if MFi chip is not used.
Pins used as generic GPIO can be handled by the HOST processor using the following commands:
• AT+AB GPIOConfig [GPIO pin] [I/O]
• AT+AB GPIORead [GPIO pin]
• AT+AB GPIOWrite [GPIO pin] [1/0]
For more details about GPIOs alternate functions refer to the AT Command Data Package user manual.
All GPIOs are capable of sinking and sourcing 4 mA of I/O current.
7.4 Reset circuit
Two types of system reset circuits are detailed below.
The maximum voltage that can be supplied to the RESET pin is 3.6V, but it is suggested to use 1.8V VDD voltage,
as there is an internal pull-up resistor to VDD. As shown in Figure 10. Simple external reset circuit and Figure
11. Host controlled reset circuit the RESET is active low, in the absence of a reset circuit the pin is internally
pulled up and therefore inactive.
SPBT3.0DP2
GPIO interface
DS11599 - Rev 6 page 15/31
7.4.1 Simple external reset circuit
The figure below shows a simple push-button reset circuit.
Figure 10. Simple external reset circuit
Note: RPU ranges from 30 kΩ to 50 kΩ internally provided.
7.4.2 Host controlled reset circuit
The figure below shows a typical host controlled reset circuit.
Figure 11. Host controlled reset circuit
Note:
• RPU ranges from 30 kΩ to 50 kΩ internally.
• The host reset resistor should be from 1 kΩ to 10 kΩ
7.5 External LPO input circuit
An optional external LPO may be connected to the PIN 15 of the module to allow lower power consumption in
Deep sleep and Sniff modes.
SPBT3.0DP2
External LPO input circuit
DS11599 - Rev 6 page 16/31
LPO parameters:
• Frequency: 32.768 KHz
• Tolerance: +/- 150 ppm typical, +/- 250 maximum
• Absolute maximum supplied voltage at LPO pin: +1.8 V
• VIL min/max = 0 V/+0.5 V
• VIH min/max = +1.47 V/+1.8 V
• Input capacitance: 2.5 pF maximum
By default the 32 KHz is internally generated and is output on the LPO pin of the module. In order to enable the
use of external low power oscillator, the UseExtLPO variable has to be set to TRUE (refer to the Data Package
user manual for details), possibly at first power on of the board to avoid conflict in case external LPO output has
no enabling control. STM small footprint device M41T62LC6F can be used. Its LPO output can be disabled
through I2C interface.
7.6 MFi co-processor interface
A specific MFi co-processor is needed to enable iAP2 profile for connection with Apple devices. The MFi co-
processor component details are available for licensed MFi developers from the MFi program.
The MFi co-processor can be connected to the module through the I2C pins. External pull-up resistors are
needed on both lines.
The Data Package firmware handles the communication with the MFi co-processor.
SPBT3.0DP2
MFi co-processor interface
DS11599 - Rev 6 page 17/31
Figure 12. SPBT3.0DP2 to MFi coprocessor interconnections
TBD TBD
Note: R1 and R2 are used to select the I2CBus address:
power supply
Circuit with 1.8V coprocessor
TBD TBD
with only R1 mounted--> RST signal is at high logic level and are selected the 0x22 Write Address and 0x23 Read Address
with only R2 mounted--> RST signal is at low logic level and are selected the 0x20 Write Address and 0x21 Read Address
Note: R7 and R8 are used to select the I2CBus address:
3.3V
power supply
Circuit with 3.3V coprocessor
3.3V
3.3V
with only R7 mounted--> RST signal is at high logic level and are selected the 0x22 Write Address and 0x23 Read Address
with only R8 mounted--> RST signal is at low logic level and are selected the 0x20 Write Address and 0x21 Read Address
C3
100n
R1
10 kOhm
R3
2.2 kOhm
ANTENNA
BT2
CTS 11
SPBT3.0DP2
9
BOOT
7GND
10
RESET
RTS 12
RXD 13
TXD 14
5GPIO05
VIN 8
6GPIO06
4GPIO04
3GPIO03
2GPIO02
1GPIO01
LPO 15
16
GPIO08
17
GPIO07
18
LDOUT
R8
10 kOhm
R6
2.2 kOhm
BT1
ANTENNA
CTS
SPBT3.0DP2
11
9
BOOT
7GND
10
RESET
RTS 12
RXD 13
TXD 14
5GPIO05
VIN 8
6GPIO06
4GPIO04
3GPIO03
2GPIO02
1GPIO01
LPO 15
16
GPIO08
17
GPIO07
18
LDOUT
C1
100n
U2
1GND
2SDA
APPLE MFI COPROCESSOR
NC
3
NC
4NC 5
SCL 6
RST 7
8
VCC
C4
100n
U1
GND
1
2SDA
APPLE MFI COPROCESSOR
NC
3
NC
4NC 5
6
SCL
RST 7
8
VCC
R2
10 kOhm
R7
10 kOhm
R4
2.2 kOhm
C2
100n
R5
2.2 kOhm
SPBT_SCL
SPBT_SDA
LDOUT=1.8V
SPBT_SCL
SPBT_SDA
7.7 PCB layout guidelines
The SPBT3.0DP2 module require proper placement on PCB to ensure optimal performance. The antenna on the
PCB has an omnidirectional radiation pattern. To maximize antenna efficiency, an adequate grounding plane must
be provided under the module, respecting the distance for the antenna clearance.
The position of the module on the host board and overall design of the product enclosure contributes to the
antenna performance. Poor design can limit the antenna radiation patterns and can result in reflection, diffraction,
and/or scattering of the transmitted signal thus limiting the useful operating range.
Basic guidelines:
• Never place the ground plane or route copper traces directly underneath the antenna portion of the module
• Keep a 6 mm clear zone surrounding the antenna (no ground planes, no traces)
SPBT3.0DP2
PCB layout guidelines
DS11599 - Rev 6 page 18/31
• Never place the antenna close to metallic objects
• Keep wiring, components and objects away from antenna
• Do not place the antenna in a metallic or metalized plastic enclosure
• Enclosure walls should be 20 mm or more away from the antenna in all directions
• If possible, mount antenna overhanging the edge of the host board
• Place power supply capacitors very close to VIN pin, with minimum values shown in following figure
Figure 13. Power supply capacitors
SPBT3.0DP2
PCB layout guidelines
DS11599 - Rev 6 page 19/31
8Firmware upgrade
Bluetooth is a consolidated and well known standard, anyhow interoperability issues may arise whenever a new
version of an operating system (Android, Windows, Linux, iOS, etc.) appear on the market. Bug fixes and new
features may also become available.
The SPBT3.0DP2 Data Package firmware has been designed to be upgradable via UART interface.
It is recommended to support the firmware update procedure in order to always get the benefit of latest firmware
versions.
ST may update the FW provided with the modules at any time. ST recommends that users regularly check for
documentation.
The SPBT3.0DP2 module leverages the STM32 built-in bootloader to load the new firmware. It is a three-step
procedure:
1. Enter bootloader mode
2. Transfer the new firmware
3. Exit bootloader mode
8.1 Enter bootloader mode
To enter the Bootloader mode:
1. Set the BOOT pin to HIGH level
2. Reset the module:
a. Set the RESET pin to HIGH
b. Pause
c. Set the RESET pin to LOW
8.2 Transfer the new firmware
The specification of the protocol used in the STM32 bootloader to download the new firmware is described in the
document:
http://www.st.com/web/en/resource/technical/document/application_note/CD00264342.pdf
A reference implementation of the STM32 bootloader protocol can be found at the following link:
http://sourceforge.net/projects/stm32flash/
The STM32 Flash loader demonstrator, a Windows GUI that implement that protocol can be downloaded at the
following link:
http://www.st.com/web/en/catalog/tools/PF257525
8.3 Exit bootloader mode
To exit Bootloader mode:
1. Set the BOOT pin to LOW
2. Reset the module:
a. Set the RESET pin to HIGH
b. Pause
c. Set the RESET pin to LOW
SPBT3.0DP2
Firmware upgrade
DS11599 - Rev 6 page 20/31
9Regulatory compliance
9.1 FCC certification
This module has been tested and found to comply with FCC part 15 rules. These limits are designed to provide
reasonable protection against harmful interference in approved installations. This equipment generates, uses, and
can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause
harmful interference to radio communications.
However, there is no guarantee that interference may not occur in any particular installation.
Operation is subject to the following two conditions:
1. This device may not cause harmful interference
2. this device must accept any interference received, including interference that may cause undesired
operation. Modifications or changes to this equipment not expressly approved by STMicroelectronics may
render void the user's authority to operate this equipment.
The safe user distance for RF exposure is ≥ 5 mm (in compliance with 447498 D01 General RF Exposure
Guidance v06).
Modular approval
FCC ID: S9NSPBT30DP2
In accordance with FCC part 15, the SPBT3.0DP2 is listed as a modular transmitter device.
This module is evaluated for stand-alone use only. Finished products incorporating multiple transmitters must
comply with collocation and RF exposure requirements in accordance with FCC multi-transmitter product
procedures. Collocated transmitters operating in portable RF exposure conditions (e.g. < 20 cm from persons
including but not limited to body-worn and handheld devices) may require separate approval.
9.1.1 FCC labeling instructions
When integrating the SPBT3.0DP2 into the final product, the OEM must ensure that the FCC labeling
requirements are satisfied. A statement must be included on the exterior of the final product which indicates that
the product includes a certified module. The label should state the following (or similar wording that conveys the
same meaning):
Contains FCC ID: S9NSPBT30DP2
OR
This product contains FCC ID: S9NSPBT30DP2
The OEM must include the following statements on the exterior of the final product unless the product is too small
(e.g. less than 4 x 4 inches)This device complies with Part 15 of the FCC Rules. Operation is subject to the
following two conditions:
1. this device may not cause harmful interference
2. this device must accept any interference received, including any interference that may cause undesired
operation.
9.1.2 Product manual instructions for FCC compliance
This section applies to OEM final products containing the SPBT3.0DP2 module, subject to FCC compliance. The
final product manual must contain the following statement (or a similar statement that conveys the same
meaning):
Warning: Changes or modifications not expressly approved by the party responsible for compliance
could void the user's authority to operate the equipment. (Part. 15.21)
In the case where an OEM seeks Class B (residential) limits for the final product, the following statement must be
included in the final product manual:
Note: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to
part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference
in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not
SPBT3.0DP2
Regulatory compliance
DS11599 - Rev 6 page 21/31
installed and used in accordance with the instructions, may cause harmful interference to radio communications.
However, there is no guarantee that interference will not occur in a particular installation. If this equipment does
cause harmful interference to radio or television reception, which can be determined by turning the equipment off
and on, the user is encouraged to try to correct the interference by one or more of the following measures:
•Reorient or relocate the receiving antenna.
•Increase the separation between the equipment and receiver.
•Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
•Consult the dealer or an experienced radio/TV technician for help.
In cases where an OEM seeks the lesser category of a Class A digital device for the final product, the following
statement must be included in the final product manual:
Note: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to
part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference
when the equipment is operated in a commercial environment. This equipment generates, uses, and can radiate
radio frequency energy and, if not installed and used in accordance with the instruction manual, may cause
harmful interference to radio communications. Operation of this equipment in a residential area is likely to cause
harmful interference in which case the user will be required to correct the interference at his expense.
9.2 IC certification
The SPBT3.0DP2 module has been tested and found compliant with the IC RSS-210 rules. These limits are
designed to provide reasonable protection against harmful interference in approved installations. This equipment
generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the
instructions, may cause harmful interference to radio communications.
However, there is no guarantee that interference may not occur in any particular installation.
This device complies with RSS-210 of the IC rules. Operation is subject to the following two conditions:
1. this device may not cause harmful interference
2. this device must accept any interference received, including interference that may cause undesired
operation.
Modifications or changes to this equipment not expressly approved by STMicroelectronics may render void the
user's authority to operate this equipment.
The safe user distance for RF exposure is ≥ 15 mm (in compliance with RSS-102 Issue 5).
Modular approval
IC: 8976C-SPBT302
In accordance with IC RSS-210, the SPBT3.0DP2 is listed as a modular transmitter device.
This module is evaluated for stand-alone use only. Finished products incorporating multiple transmitters must
comply with collocation and RF exposure requirements in accordance with IC multi-transmitter product
procedures. Collocated transmitters operating in portable RF exposure conditions (e.g. <20 cm from persons
including but not limited to body-worn and handheld devices) may require separate approval.
9.2.1 IC labeling instructions
When integrating the SPBT3.0DP2 into the final product, the OEM must ensure that the IC labeling requirements
are satisfied. A statement must be included on the exterior of the final product which indicates that the product
includes a certified module. The label should state the following (or similar wording that conveys the same
meaning):
Contains IC: 8976C-SPBT302
OR
This product contains IC: : 8976C-SPBT302
The OEM must include the following statements on the exterior of the final product unless the product is too small
(e.g. less than 4 x 4 inches):
This device complies with RSS-210 of the IC Rules. Operation is subject to the following two conditions:
1. this device may not cause harmful interference
SPBT3.0DP2
IC certification
DS11599 - Rev 6 page 22/31
2. this device must accept any interference received, including any interference that may cause undesired
operation.
9.2.2 Product manual instructions for IC compliance
This section applies to OEM final products containing the SPBT3.0DP2 module, subject to IC compliance. The
final product manual must contain the following statement (or a similar statement that conveys the same
meaning):
Warning: Changes or modifications not expressly approved by the party responsible for compliance
could void the user's authority to operate the equipment. (RSS-210)
In cases where an OEM seeks Class B (residential) limits for the final product, the following statement must be
included in the final product manual:
Note: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to
RSS-210 of the IC Rules. These limits are designed to provide reasonable protection against harmful interference
in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not
installed and used in accordance with the instructions, may cause harmful interference to radio communications.
However, there is no guarantee that interference will not occur in a particular installation. If this equipment does
cause harmful interference to radio or television reception, which can be determined by turning the equipment off
and on, the user is encouraged to try to correct the interference by one or more of the following measures:
•Reorient or relocate the receiving antenna.
•Increase the separation between the equipment and receiver.
•Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
•Consult the dealer or an experienced radio/TV technician for help.
In cases where an OEM seeks the lesser category of a Class A digital device for the final product, the following
statement must be included in the final product manual:
Note: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to
RSS-210 of the IC Rules. These limits are designed to provide reasonable protection against harmful interference
when the equipment is operated in a commercial environment. This equipment generates, uses, and can radiate
radio frequency energy and, if not installed and used in accordance with the instruction manual, may cause
harmful interference to radio communications. Operation of this equipment in a residential area is likely to cause
harmful interference in which case the user will be required to correct the interference at his expense.
9.3 Bluetooth certification
Module with embedded stack and profile has been qualified according to SIG qualification rules:
• Bluetooth SIG Declaration ID: D031101 (subset QDID 84049)
• Qualified Design ID (QDID): 81857
• Product type: End Product
• Core spec version: 3.0
• Product descriptions: Bluetooth module, spec V3.0
9.4 CE certification
The module has been certified according to the following certification rules:
• EN 300 328 V 2.1.1 (2016 11) (a)
• ETSI EN 301 489-17 V3.1.1 (2017-02) (b)
• ETSI EN 301 489-1 V2.1.1 (2017-02) (c)
• EN 60950-1:2006 + A11:2009 + A1:2010 + A12:2011 + A2:2013 (d)
• EN 62479:2010
a) EN 300 328 V 2.1.1 (2016 11): “electromagnetic compatibility and radio spectrum Matters (ERM); Wideband
transmission systems; data transmission equipment operating in the 2.4 GHZ ISM band and using wideband
modulation techniques; harmonized EN covering essential requirements under article 3.2 of the R&TTE directive”.
SPBT3.0DP2
Bluetooth certification
DS11599 - Rev 6 page 23/31
b) EN 301 489-17 V 3.1.1 (2017 02): “electromagnetic compatibility and radio spectrum Matters (ERM);
electromagnetic compatibility (EMC) standard for radio equipment and services; part 17: specific condition for 2.4
GHz wideband transmission systems and 5 GHz high performance RLAN equipment”.
c) ETSI EN 301 489-1 V2.1.1 (2017 02) : “electromagnetic compatibility and radio spectrum Matters (ERM);
electromagnetic compatibility (EMC) standard for radio equipment and services; part 1: Common technical
requirements”.
d) EN60950-1:2006 +A11:2009+A1:2010 +A12:2011+A2:2013: “Information technology equipment - safety”.
The module is provided by CE marking:
Figure 14. CE marking
The module has obtained the RED certificate is: No. 0051-RED-0027 REV. 0”
The certified module production firmware release is:
1.X
For additional information please refer to:
STMicroelectronics Via C. Olivetti 2, Agrate Brianza 20864 (ITALY)
SPBT3.0DP2
CE certification
DS11599 - Rev 6 page 24/31
10 Traceability
Each module is univocally identified by a serial number stored in a 2D data matrix laser marked on the bottom of
the module.
The serial number has the following format: WW YY D FF NNN
Table 9. Traceability information
Letter Meaning
WW Week
YY Year
D Product ID number
FF Production panel coordinate identification
NN Progressive serial number
Each module bulk package is identified by a bulk ID.
The Bulk ID and module 2D data matrix are linked by a reciprocal traceability link.
The module 2D data matrix traces the lot number of any raw material used.
SPBT3.0DP2
Traceability
DS11599 - Rev 6 page 25/31
Revision history
Table 10. Document revision history
Date Version Changes
09-Jun-2016 1 Initial release.
28-Jun-2016 2 Updated cover page image
Minor text edits
01-Jul-2016 3 In Table 6 "Pin assignment"
- updated pin 6 description
23-Feb-2017 4 In Table 6 "Pin assignment"
- updated pins 11 and 12 description
14-Sep-2017 5 Updated features and descriprtion in
cover page.
Updated Section " Cover image" in cover
page.
Updated Table 3: "Absolute maximum
ratings".
Updated Figure 3: "Pin assignment".
Updated Section 8.3: "GPIO interface".
Added Figure 11: "SPBT3.0DP2 to MFi
coprocessor interconnections".
Updated Figure 12: "Power supply
capacitors".
Updated Section 10.4: "CE certification".
Minor text changes.
26-Feb-2018 6 Updated: Section 5.4 Current
consumption.
SPBT3.0DP2
DS11599 - Rev 6 page 26/31
Contents
1Description ........................................................................2
2Applications .......................................................................3
3Software architecture ..............................................................4
3.1 BT stack layers................................................................4
3.2 Supported profile ..............................................................5
3.3 AT command set: Data Package .................................................5
4Module block diagram .............................................................6
5Hardware specifications ...........................................................7
5.1 Recommended operating conditions ..............................................7
5.2 Radio features ................................................................7
5.3 Absolute maximum ratings ......................................................7
5.4 Current consumption ...........................................................7
5.5 I/O operating characteristics .....................................................8
5.6 Pin assignment................................................................9
6Package information ..............................................................11
6.1 RF module package information ................................................11
7Hardware design..................................................................13
7.1 Reflow soldering..............................................................13
7.2 UART interface...............................................................14
7.3 GPIO interface ...............................................................15
7.4 Reset circuit .................................................................15
7.4.1 Simple external reset circuit ...............................................15
7.4.2 Host controlled reset circuit ...............................................16
7.5 External LPO input circuit ......................................................16
7.6 MFi co-processor interface .....................................................17
7.7 PCB layout guidelines .........................................................18
8Firmware upgrade ................................................................20
8.1 Enter bootloader mode ........................................................20
8.2 Transfer the new firmware .....................................................20
SPBT3.0DP2
Contents
DS11599 - Rev 6 page 27/31
8.3 Exit bootloader mode..........................................................20
9Regulatory compliance ...........................................................21
9.1 FCC certification..............................................................21
9.1.1 FCC labeling instructions .................................................21
9.1.2 Product manual instructions for FCC compliance ...............................21
9.2 IC certification................................................................22
9.2.1 IC labeling instructions ...................................................22
9.2.2 Product manual instructions for IC compliance.................................23
9.3 Bluetooth certification .........................................................23
9.4 CE certification ...............................................................23
10 Traceability ......................................................................25
Revision history .......................................................................26
Contents ..............................................................................27
List of tables ..........................................................................29
List of figures..........................................................................30
Disclaimer .............................................................................31
SPBT3.0DP2
Contents
DS11599 - Rev 6 page 28/31
List of tables
Table 1. Recommended operating conditions.......................................................7
Table 2. Radio features ......................................................................7
Table 3. Absolute maximum ratings .............................................................7
Table 4. Power consumption in standby (no connection) ...............................................8
Table 5. Power consumption during connection .....................................................8
Table 6. I/O operating characteristics ............................................................9
Table 7. Pin assignment .................................................................... 10
Table 8. Soldering ........................................................................ 13
Table 9. Traceability information............................................................... 25
Table 10. Document revision history ............................................................. 26
SPBT3.0DP2
List of tables
DS11599 - Rev 6 page 29/31
List of figures
Figure 2. Software architecture overview .........................................................4
Figure 3. SPBT3.0DP2 block diagram ...........................................................6
Figure 4. Pin assignment....................................................................9
Figure 5. RF module package outline .......................................................... 11
Figure 6. Recommended land pattern (top view)................................................... 12
Figure 7. Soldering profile .................................................................. 14
Figure 8. Connection to host device ........................................................... 14
Figure 9. Typical RS232 circuit............................................................... 15
Figure 10. Simple external reset circuit .......................................................... 16
Figure 11. Host controlled reset circuit .......................................................... 16
Figure 12. SPBT3.0DP2 to MFi coprocessor interconnections .......................................... 18
Figure 13. Power supply capacitors ............................................................ 19
Figure 14. CE marking ..................................................................... 24
SPBT3.0DP2
List of figures
DS11599 - Rev 6 page 30/31
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST
products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST
products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2018 STMicroelectronics – All rights reserved
SPBT3.0DP2
DS11599 - Rev 6 page 31/31
