ASYNCHRONOUS
SRAM 128K x 8 SRAM
+3.3V SUPPLY, SINGLE CHIP ENABLE
REVOLUTIONARY PINOUT
GVT73128A8
REVOLUTIONARY PINOUT 128K X 8
GALVANTECH, INC.
Galvantech, Inc. reserves the right to change
products or specifications without notice.
Rev. 1/00
Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051
Tel (408) 566-0688 Fax (408) 566-0699Web Site http://www.galvantech.com
FEATURES
•Fast access times: 10, 12, 15and 20ns
•Fast OE# access times: 5, 6, 7 and 8ns
•Single +3.3V+0.3V power supply
•Fully static -- no clock or timing strobes necessary
•All inputs and outputs are TTL-compatible
•Three state outputs
•Center power and ground pins for greater noise immunity
•JEDEC standard for functionality and revolutionary pinout
•Easy memory expansion with CE# and OE# options
•Automatic CE# power down
•High-performance, low-power consumption, CMOS
double-poly, double-metal process
OPTIONSMARKING
•Timing
10ns access -10
12ns access -12
15ns access -15
20ns access -20
•Packages
32-pin SOJ (400 mil) J
32-pin SOJ (300 mil) SJ
32-pin TSOP II (400 mil) TS
•Power consumption
Standard None
Low L
•
•Temperature
Commercial None (0°C to 70°C)
Industrial I (-40°C to 85°C)
•
GENERAL DESCRIPTION
The GVT73128A8 is organized as a 131,072 x 8 SRAM
using a four-transistor memory cell with a high performance,
silicon gate, low-power CMOS process. Galvantech SRAMs
are fabricated using double-layer polysilicon, double-layer
metal technology.
This device offers center power and ground pins for
improved performance and noise immunity. Static design
eliminates the need for external clocks or timing strobes. For
increased system flexibility and eliminating bus contention
problems, this device offers chip enable (CE#) and output
enable (OE#) with this organization.
Writing to these devices is accomplished when write
enable (WE#) and chip enable (CE#) inputs are both LOW.
Reading is accomplished when (CE#) and (OE#) go LOW
with (WE#) remaining HIGH. The device offers a low power
standby mode when chip is not selected. This allows system
designers to meet low standby power requirements.
1
2
3
4
5
6
7
8
9
10
32
31
30
29
28
27
26
25
24
23
22
21
20
11
12
13
14
15
16
19
18
17
A5
A6
DQ6
DQ5
A8
A9
A10
A11
A12
A7
OE#
DQ8
DQ7
VSS
VCC
A2
A1
DQ3
DQ4
WE#
A16
A15
A14
A13
A0
CE#
DQ1
DQ2
VCC
VSS
A4A3
PIN ASSIGNMENT
32-Pin SOJ
32-Pin TSOP II
November 20, 19992Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 1/00
GVT73128A8
REVOLUTIONARY PINOUT 128K X 8
GALVANTECH,
FUNCTIONAL BLOCK DIAGRAM
TRUTH TABLE
PIN DESCRIPTIONS
MODECE#WE#OE#DQPOWER
READLHLQACTIVE
WRITEL L XDACTIVE
OUTPUT DISABLELH H HIGH-ZACTIVE
STANDBYHX X HIGH-ZSTANDBY
SOJ/TSOP Pin
NumbersSYMBOLTYPEDESCRIPTION
4, 3, 2, 1, 32, 31, 30,
29, 21, 20, 19, 18,
17, 16, 15, 14, 13
A0-A16InputAddresses Inputs: These inputs determine which cell is addressed.
12 WE#InputWrite Enable: This input determines if the cycle is a READ or WRITE cycle. WE# is LOW
for a WRITE cycle and HIGH for a READ cycle.
5CE#InputChip Enable: This active LOW input is used to enable the device. When CE# is LOW, the
chip is selected. When CE# is HIGH, the chip is disabled and automatically goes into
standby power mode.
28 OE#InputOutput Enable: This active LOW input enables the output drivers.
6, 7,10, 11,
22, 23, 26, 27DQ1-DQ8Input/OutputSRAM Data I/O: Data inputs and data outputs
8, 24VCCSupplyPower Supply: 3.3V +0.3V
9, 25VSS SupplyGround
CE#
ADDRESS BUFFER
ROW DECODER
COLUMN DECODER
MEMORY ARRAY
512 ROWS X 256 X 8
COLUMNS
I/O CONTROL
WE#
OE#
DQ8
DQ1
POWER
DOWN
A16
A0
VCC
VSS
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Supply Relative to VSS........-0.5V to +4.6V
VIN ..........................................................-0.5V to VCC+0.5V
Storage Temperature (plastic) ..........................-55oC to +125o
Junction Temperature .....................................................+125o
Power Dissipation ...........................................................1.0W
Short Circuit Output Current .......................................50mA
*Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.This is a stress
rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
November 20, 19993Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 1/00
GVT73128A8
REVOLUTIONARY PINOUT 128K X 8
GALVANTECH,
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(All Temperature Ranges; VCC = 3.3V +0.3V unless otherwise noted)
CAPACITANCE
DESCRIPTIONCONDITIONSSYMBOLMINMAXUNITSNOTES
Input High (Logic 1) voltageVIH2.2VCC+0.5V1, 2
Input Low (Logic 0) VoltageVIl-0.50.8V1, 2
Input Leakage Current0V < VIN < VCCILI-5 5 uA
Output Leakage CurrentOutput(s) disabled,
0V < VOUT < VCCILO-5 5 uA
Output High VoltageIOH = -4.0mA VOH2.4V1
Output Low VoltageIOL = 8.0mA VOL0.4V1
Supply VoltageVCC3.03.6V1
DESCRIPTIONCONDITIONS SYMTYPPOWER-10-12-15-20UNITSNOTES
Power Supply
Current: OperatingDevice selected; CE# < VIL; VCC =MAX;
f=fMAX; outputs openIcc60 standard140 120 100 80 mA3, 14
low130 110 90 70
TTL StandbyCE# >VIH; VCC = MAX; f=fMAXISB112 standard30 25 20 17 mA14
low25 20 17 15
CMOS StandbyCE1# >VCC -0.2; VCC = MAX;
all other inputs < VSS +0.2 or >VCC -0.2;
all inputs static; f= 0
ISB20.02standard10 10 10 10 mA14
low0.750.750.750.75
DESCRIPTIONCONDITIONSSYMBOLMAXUNITSNOTES
Input CapacitanceTA = 25oC; f = 1 MHz
VCC = 3.3VCI6 pF4
Input/Output Capacitance (DQ)CI/O8 pF4
November 20, 19994Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 1/00
GVT73128A8
REVOLUTIONARY PINOUT 128K X 8
GALVANTECH,
AC ELECTRICAL CHARACTERISTICS
(Note 5) (All Temperature Ranges; VCC = 3.3V+0.3V)
DESCRIPTION- 10- 12- 15- 20
SYMMINMAXMINMAXMINMAXMINMANUNITSNOTES
READ Cycle
READ cycle timetRC 10 12 15 20 ns
Address access timetAA 10 12 15 20 ns
Chip Enable access timetACE10 12 15 20 ns
Output hold from address changetOH3 4 4 4 ns
Chip Enable to output in Low-ZtLZCE3 4 4 4 ns4, 7
Chip disable to output in High-ZtHZCE5 6 7 8 ns4, 6, 7
Output Enable access timetAOE5 6 7 8 ns
Output Enable to output in Low-ZtLZOE0 0 0 0 ns
Output Enable to output in High-ZtHZOE5 6 7 8 ns4, 6
Chip Enable to power-up timetPU0 0 0 0 ns4
Chip disable to power-down timetPD10 12 15 20 ns4
WRITE Cycle
WRITE cycle timetWC10 12 15 20 ns
Chip Enable to end of writetCW8 8 9 10 ns
Address valid to end of write, with OE#
HIGHtAW8 8 9 10 ns
Address setup timetAS 0 0 0 0 ns
Address hold from end of writetAH0 0 0 0 ns
WRITE pulse widthtWP2 10 10 11 12 ns
WRITE pulse width, with OE# HIGHtWP1 8 8 9 10 ns
Data setup timetDS5 5 6 7 ns
Data hold timetDH 0 0 0 0 ns
Write disable to output in Low-ZtLZWE3 4 5 5 ns4, 7
Write Enable to output in High-ZtHZWE5 6 7 8 ns4, 6, 7
AC TEST CONDITIONS
Input pulse levels0V to 3.0V
Input rise and fall times1.5ns
Input timing reference levels1.5V
Output reference levels1.5V
Output loadSee Figures 1 and 2
OUTPUT LOADS
Vt = 1.5V
30 pF
Q
Z
0
= 50
Ω
Fig. 1 OUTPUT LOAD EQUIVALENT
50
Ω
Q
+5V
480
Ω
255
Ω
Fig. 2 OUTPUT LOAD EQUIVALENT
5 pF
Vt = 1.5V
30 pF
DQ
Z
0
= 50
Ω
Fig. 1 OUTPUT LOAD EQUIVALENT
50
Ω
DQ
3.3v
317
Ω
351
Ω
Fig. 2 OUTPUT LOAD EQUIVALENT
5 pF
November 20, 19995Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 1/00
GVT73128A8
REVOLUTIONARY PINOUT 128K X 8
GALVANTECH,
NOTES
1. All voltages referenced to VSS (GND).
2. Overshoot: VIH ≤ +6.0V for t ≤ tRC /2.
Undershoot: VIL ≤ -2.0V for t ≤ tRC /2
3. Icc is given with no output current. Icc increases with greater
output loading and faster cycle times.
4. This parameter is sampled.
5. Test conditions as specified with the output loading as shown in
Fig. 1 unless otherwise noted.
6. Output loading is specified with CL=5pF as in Fig. 2. Transition
is measured +500mV from steady state voltage.
7. At any given temperature and voltage condition, tHZCE is less
than tLZCE and tHZWE is less than tLZWE.
8. WE# is HIGH for READ cycle.
9. Device is continuously selected. Chip enable and output enables
are held in their active state.
10. Address valid prior to, or coincident with, latest occurring chip
enable.
11. tRC = Read Cycle Time.
12. Chip Enable and Write Enable can initiate and terminate a
WRITE cycle.
13. Capacitance derating applies to capacitance different from the
load capacitance shown in Fig. 1.
14. Typical values are measured at 3.3V, 25oC and 20ns cycle time.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTIONCONDITIONSSYMBOLMINTYPMAXUNITSNOTES
Vcc for Retention DataVDR2V
Data Retention CurrentCE# >VCC -0.2;
all other inputs < VSS +0.2
or >VCC -0.2;
all inputs static; f= 0
Vcc = 2VICCDR2 400 uA13
Vcc = 3VICCDR3 600 uA13
Chip Deselect to
Data Retention TimetCDR0 ns4
Operation Recovery TimetRtRC ns4, 11
November 20, 19996Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 1/00
GVT73128A8
REVOLUTIONARY PINOUT 128K X 8
GALVANTECH,
LOW VCC DATA RETENTION WAVEFORM
READ CYCLE NO. 1(8, 9)
READ CYCLE NO. 2(7, 8, 10, 12)
VCC
CE#
DATA RETENTION MODE
VDR
4.5V 4.5V
VIH
VIL
tRC
tCDR
VCC
CE#
DATA RETENTION MODE
VDR
3.0V 3.0V
VIH
VIL
tRC
tCDR
ADDR VALID
tRC
DATA VALID
tOH
tAA
PREVIOUS DATA VALID
Q
CE#
tRC
DATA VALID
tLZCE
tACE
OE#
HIGH Z
tAOE
tLZOE
tHZCE
tHZOE
Q
UNDEFINED
DON'T CARE
November 20, 19997Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 1/00
GVT73128A8
REVOLUTIONARY PINOUT 128K X 8
GALVANTECH,
WRITE CYCLE NO. 1(7, 12, 13)
(Write Enable Controlled with Output Enable OE# active LOW))
WRITE CYCLE NO. 2(12, 13)
(Write Enable Controlled with Output Enable OE# inactive HIGH)
ADDR
t
WC
t
AH
t
DS
DATA VALID
CE#
WE#
D
Q
t
DH
t
WP2
t
AS
t
AW
t
CW
HIGH Z
t
HZWE
t
LZWE
ADDR
t
WC
t
AH
t
DS
DATA VALID
HIGH Z
CE#
WE#
D
Q
t
DH
t
WP1
t
AS
t
AW
t
CW
UNDEFINED
DON'T CARE
November 20, 19998Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 1/00
GVT73128A8
REVOLUTIONARY PINOUT 128K X 8
GALVANTECH,
WRITE CYCLE NO. 3(12, 13)
(Chip Enable Controlled)
ADDR
tWC
tAH
tDS
DON'T CARE
DATA VALID
CE#
WE#
D
Q
tDH
tWP1
tAS
tAW tCW
HIGH Z
November 20, 19999Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 1/00
GVT73128A8
REVOLUTIONARY PINOUT 128K X 8
GALVANTECH,
Package Dimensions
Note: All dimensions in inches (millimeters)
.830 (21.08)
.820 (20.83)
.405 (10.29)
.395 (10.03)
PIN #1 INDEX .050 (1.27) TYP
.020 (0.51)
.015 (0.38)
MAX
MIN or typical, min where noted.
SEATING PLANE
.380 (9.65)
.360 (9.14)
.095 (2.41)
.080 (2.03)
.145 (3.68)
.131 (3.33)
.030 (0.76)
MIN
.445 (11.30)
.435 (11.05)
32-pin 400 Mil Plastic SOJ (J)
Note: All dimensions in inches (millimeters)
.825 (20.96)
.810 (20.57)
.305 (7.75)
.292 (7.42)
PIN #1 INDEX .050 (1.27) TYP
.020 (0.51)
.015 (0.38)
MAX
MIN or typical, min where noted.
SEATING PLANE
.274 (6.95)
.254 (6.44)
.095 (2.41)
.080 (2.03)
.140 (3.55)
.120 (3.04)
.025 (0.63)
MIN
32-pin 300 Mil Plastic SOJ (SJ)
.340 (8.64)
.330 (8.38)
November 20, 199910 Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 1/00
GVT73128A8
REVOLUTIONARY PINOUT 128K X 8
GALVANTECH,
Package Dimensions
Note: All dimensions in inches (millimeters)
.730 (18.54)
.720 (18.28)
.405 (10.29)
.395 (10.03)
PIN #1 INDEX .05 (1.27) TYP
.018 (0.45)
.012 (0.30)
MAX
MIN or typical, max where noted.
SEATING
PLANE
.0006 (0.15)
.0004 (0.01)
.007 (0.18)
.005 (0.12)
.471 (11.96)
.455 (11.56)
32-pin 400 Mil Plastic TSOP (TS)
.005 (1.27)
MAX
.031 (0.80) .026 (0.65)
.014 (0.35)
November 20, 199911 Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 1/00
GVT73128A8
REVOLUTIONARY PINOUT 128K X 8
GALVANTECH,
Ordering Information
GVT 73128A8 X XX - XX X X
Galvantech Prefix
Part Number
15 = 15ns, 20 = 20ns)
Speed (10 = 10ns, 12= 12ns
Temperature (Blank = Commercial
I = Industrial)
Power (Blank= Standard,
L= Low Power)
Package (J = 400 mil SOJ,
Revision Differentiator
(Blank for original revision)
SJ = 300 mil SOJ
TS = 400 mil TSOP II)
