5555 N.E. Moore Ct. Hillsboro, Oregon 97124-6421 Phone (503) 268-8000 FAX (503) 268-8347
Internet: http://www.latticesemi.com
ispPAC®-POWR1208 Device Datasheet
September 2010
All Devices Discontinued!
Product Change Notification (PCN) #13-10 has been issued to discontinue all devices in
this data sheet.
The original datasheet pages have not been modified and do not reflect those changes.
Please refer to the table below for reference PCN and current product status.
Product Line
Ordering Part Number
Product Status
Reference PCN
ispPAC-
POWR1208
ispPAC-POWR1208-01T44I
Discontinued
PCN#13-10
ispPAC-POWR1208-01T44E
ispPAC-POWR1208-01TN44I
ispPAC-POWR1208-01TN44E
www.latticesemi.com
1-1
DS1031_04.1
August 2004 Data Sheet DS1031
© 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other
brand or product names are trademarks or registered trademarks of their respective holders . The specifications and information herein are subject to change without
notice.
Features
■
Monitor and Control Multiple Power
Supplies
• Simultaneously monitors up to 12 po w er supplies
• Sequence controller for power-up conditions
• Provides eight output control signals
• Programmable digital and analog circuitry
■
Embedded PLD for Sequence Control
• Implements state machine and input conditional
events
• In-System Programmable (ISP™) through JTAG
and on-chip E
2
CMOS
®
■
Embedded Programmable Timers
• 4 Programmable 8-bit timers (32µs to 524ms)
• Programmable time delay between multiple
power supply ramp-up and wait statements
■
Analog Comparators for Monitoring
• 12 analog comparators for monitoring
• 192 precise programmable threshold levels
spanning 1.03V to 5.72V
• Each comparator can be independently config-
ured around standard logic supply voltages of
1.2V, 1.5V, 1.8V, 2.5V, 3.3V, 5V
• Other user-defined voltages possible
• Eight direct comparator outputs
■
Embedded Oscillator
• Built-in clock generator, 250kHz
• Programmable clock frequency
• Programmable timer pre-scaler
• External clock support
■
Programmable Output Configurations
• Four digital outputs for logic and power supply
control
• Four fully programmable gate driver outputs for
FET control, or programmable as four additional
digital outputs
• Expandable with ispMACH™ 4000 CPLD
■
2.25V to 5.5V Supply Range
• In-system programmable at 3.0V to 5.5V
• Industrial temperature range: -40°C to +85°C
• Automotive temperature range: -40°C to +125°C
• 44-pin TQFP package
• Lead-free package option
Application Block Diagram
Description
The Lattice ispPAC-POWR1208 incorporates both in-
system programmable logic and in-system programma-
ble analog circuits to perform special functions for
power supply sequencing and monitoring. The ispPAC-
POWR1208 device has the capability to be configured
through software to control up to eight outputs for power
supply sequencing and 12 comparators monitoring sup-
ply voltage limits, along with four digital inputs for inter-
facing to other control circuits or digital logic. Once
configured, the design is downloaded into the device
through a standard JTAG interface. The circuit configu-
ration and routing are stored in non-volatile E
2
CMOS.
PAC-Designer,
®
an easy-to-use Windows-compatible
software package gives users the ability to design the
logic and sequences that control the power supplies or
FET driver circuits. The user has control over timing
functions, programmable logic functions and compara-
tor threshold values as well as I/O configurations.
-48V
Primary +
Gnd
+
-
+5V
+3.3V
+2.5V
+1.8V +1.8V
ispPAC-POWR1208
Power Sequence
Controller
HVOUT1
0.1uF10uF
HVOUT2
HVOUT3
HVOUT4
OUT5
OUT6
OUT7
OUT8
DC/DC Supply
or Regulator
OE/EN
Digital
Logic
EN
Circuits
RESET
Comp2
Comp4
VMON12
12 Analog Inputs
IN1
IN2
VDD
IN3
IN4
VMON1
VMON2
VMON3
VMON4
VMON5
VMON6
VMON7
VMON8
VMON9
VMON10
VMON11
CLK
Comp3
Comp1
Comp6
Comp8
Comp7
Comp5
+2.5V
Circuits
+3.3V
Circuits
+5V
Circuits
OE/EN
Digital
Logic
EN
-48V
Primary +
Gnd
+
-
-48V
Primary +
Gnd
+
-
DC/DC
Supply
-48V
Primary +
Gnd
+
-
DC/DC Supply
or Regulator
POR
DC/DC
Supply
DC/DC
Supply
DC/DC
RG
Supply
VDD VDDINP
0.1uF
CREF
3.3V
3.3V
RG
RG
RG
ispPAC-POWR1208
In-System Programmable Power Supply
Sequencing Controller and Monitor
®
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Lattice Semiconductor ispPAC-POWR1208 Data Sheet
1-2
Power Supply Sequence Controller and Monitor
The ispPAC-POWR1208 device is specifically designed as a fully-progr ammable power supply sequencing control-
ler and monitor for managing up to eight separate power supplies, as well as monitoring up to 12 analog inputs or
supplies. The ispPAC-POWR1208 device contains an internal PLD that is programmable by the user to implement
digital logic functions and control state machines. The internal PLD connects to four programmable timers, special
purpose I/O and the programmable monitoring circuit blocks. The internal PLD and timers can be clocked by either
an internal programmable clock oscillator or an external clock source.
The voltage monitors are arranged as 12 independent comparators each with 192 programmable trip point set-
tings. Monitoring levels are set around the following standard voltages: 1.2V, 1.5V, 1.8V, 2.5V, 3.3V or 5.0V.
All 12 voltages can be monitored simultaneously (i.e., continuous-time operation). Other non-standard voltage lev-
els can be accounted for using various scale factors.
For added robustness, the comparators feature a variable hysteresis that scales with the voltage they monitor.
Generally, a larger hysteresis is better. However, as power supply voltages get smaller, that hysteresis increasingly
aff ects trip-point accuracy. Therefore , the hysteresis is +/-16mV for 5V supplies and scales do wn to +/-3mV for 1.2V
supplies, or about 0.3% of the trip point.
The programmable logic functions consist of a block of 36 inputs with 81 product terms and 16 macrocells. The
architecture supports the sharing of product terms to enhance the overall usability.
Output pins are configurable in two different modes. There are eight outputs for controlling eight different power
supplies. OUT5-OUT8 are open-drain outputs for interfacing to other circuits. The HVOUT1-HVOUT4 pins can be
programmed individually as open-drain outputs or as high voltage FET gate drivers. As high voltage FET gate
driver outputs, they can be used to drive an external N-Channel MOSFET as a switch to control the voltage ramp-
up of the target board. The four HVOUT drivers have programmable current and voltage levels. Of the eight out-
puts, four can be configured in the FET gate driver mode or open-drain digital mode.
Figure 1-1. ispPAC-POWR1208 Block Diagram
Sequence
Controller
CPLD
36 I/P & 16
Macrocell
GLB
Comparator
Outputs
High V oltage
Outputs
Analog
Inputs
CLKIO
Digital
Inputs
250kHz
Internal
OSC
4 Timers Logic
Outputs
12
8
4
4
5
COMP1
COMP2
COMP3
COMP4
COMP5
COMP6
COMP7
COMP8
OUT5
OUT6
OUT7
OUT8
HVOUT1
HVOUT2
HVOUT3
HVOUT4
VDD
ispPAC-POWR1208
VMON1
VMON2
VMON3
VMON4
VMON5
VMON6
VMON7
VMON8
VMON9
VMON10
VMON11
VMON12
IN1
RESET
IN2
IN3
IN4
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Lattice Semiconductor ispPAC-POWR1208 Data Sheet
1-3
Pin Descriptions
Number Name Pin Type V oltage Range Description
1 HVOUT4 O/D Output 2.25V-5.5V
2
Open-drain Output 4
Current Source 8V-12V
3
FET Gate Driver 4
2 HVOUT3 O/D Output 2.25V-5.5V
2
Open-drain Output 3
Current Source 8V-12V
3
FET Gate Driver 3
3 HVOUT2 O/D Output 2.25V-5.5V
2
Open-drain Output 2
Current Source 8V-12V
3
FET Gate Driver 2
4 HVOUT1 O/D Output 2.25V-5.5V
2
Open-drain Output 1
Current Source 8V-12V
3
FET Gate Driver 1
5 VDD Power 2.25V-5.5V Main Power Supply
6 IN1 CMOS Input VDDINP
1
Input 1
7 IN2 CMOS Input VDDINP
1
Input 2
8 IN3 CMOS Input VDDINP
1
Input 3
9 IN4 CMOS Input VDDINP
1
Input 4
10 RESET
CMOS input VDD
7
PLD Reset Input, Active Low
11 VDDINP Power 2.25V-5.5V
4
Digital Inputs Power Supply
12 OUT5 O/D Output 2.25V-5.5V
2
Open-Drain Output
13 OUT6 O/D Output 2.25V-5.5V
2
Open-Drain Output
14 OUT7 O/D Output 2.25V-5.5V
2
Open-Drain Output
15 OUT8 O/D Output 2.25V-5.5V
2
Open-Drain Output
16 COMP8 O/D Output 2.25V-5.5V
2
VMON8 Comparator Output (Open-Drain)
17 COMP7 O/D Output 2.25V-5.5V
2
VMON7 Comparator Output (Open-Drain)
18 COMP6 O/D Output 2.25V-5.5V
2
VMON6 Comparator Output (Open-Drain)
19 COMP5 O/D Output 2.25V-5.5V
2
VMON5 Comparator Output (Open-Drain)
20 COMP4 O/D Output 2.25V-5.5V
2
VMON4 Comparator Output (Open-Drain)
21 COMP3 O/D Output 2.25V-5.5V
2
VMON3 Comparator Output (Open-Drain)
22 COMP2 O/D Output 2.25V-5.5V
2
VMON2 Comparator Output (Open-Drain)
23 COMP1 O/D Output 2.25V-5.5V
2
VMON1 Comparator Output (Open-Drain)
24 TCK TTL/LVCMOS Input VDD
6
Test Clock (JTAG Pin)
25 POR
O/D Output 2.25V-5.5V Power-On-Reset Output
26 CLK Bi-directional I/O VDD Clock Output (Open-Drain) or Clock Input
27 GND Ground Ground
28 TDO TTL/LVCMOS Output VDD Test Data Out (JTAG Pin)
29 TRST
TTL/LVCMOS Input VDD Test Reset, Active Low, 50k Ohm Internal Pull-up
(JTAG Pin, Optional Use)
30 TDI TTL/LVCMOS Input VDD Test Data In, 50k Ohm Internal Pull-up (JTAG Pin)
31 TMS TTL/LVCMOS Input VDD Test Mode Select, 50k Ohm Internal pull-up (JTAG
Pin)
32 VMON1 Analog Input 0V-5.72V
5
Voltage Monitor Input 1
33 VMON2 Analog Input 0V-5.72V
5
Voltage Monitor Input 2
34 VMON3 Analog Input 0V-5.72V
5
Voltage Monitor Input 3
35 VMON4 Analog Input 0V-5.72V
5
Voltage Monitor Input 4
36 VMON5 Analog Input 0V-5.72V
5
Voltage Monitor Input 5
37 VMON6 Analog Input 0V-5.72V
5
Voltage Monitor Input 6
38 VMON7 Analog Input 0V-5.72V
5
Voltage Monitor Input 7
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Lattice Semiconductor ispPAC-POWR1208 Data Sheet
1-4
Absolute Maximum Ratings
Absolute maximum ratings are sho wn in the table below. Stresses above those listed values may cause permanent
damage to the device. Functional operation of the device at these or any other conditions above those indicated in
the operating sections of this specification is not implied.
39 CREF Reference 1.17V
8
Reference for Internal Use, Decoupling Capacitor
(.1uf Required, CREF to GND)
40 VMON8 Analog Input 0V-5.72V
5
Voltage Monitor Input 8
41 VMON9 Analog Input 0V-5.72V
5
Voltage Monitor Input 9
42 VMON10 Analog Input 0V-5.72V
5
Voltage Monitor Input 10
43 VMON11 Analog Input 0V-5.72V
5
Voltage Monitor Input 11
44 VMON12 Analog Input 0V-5.72V
5
Voltage Monitor Input 12
1. IN1...IN4 are digital inputs to the PLD. The thresholds for these pins are referenced by the voltage on V
DDINP
.
2. The 18 open-drain outputs can be pow ered independently of V
DD,
the open-drain outputs can be pulled up as high as +6.0V (referenced to
ground). Exception, CLK pin 26 can only be pulled as high as V
DD
.
3. The four FET driv er outputs (when this mode is activated, the corresponding 4 open-drain outputs are disabled) are internally powered and
can source up to 7.5V above V
DD
.
4. V
DDINP
can be chosen independent of V
DD.
It applies only to the four logic inputs IN1-IN4.
5. The 12 VMON inputs can be biased independently of V
DD
. The 12 VMON inputs can be as high as 7.0V Max (referenced to ground).
6. CLK is the PLD clock output in master mode . It is re-routed as an input in slav e mode . The clock mode is set in software during design time.
In output mode it is an open-drain type pin and requires an external pull-up resistor (pull-up voltage must be
≤
V
DD
). Multiple ispPAC-
POWR1208 devices can be tied together with one acting as the master , the master can use the internal clock and the sla ve can be clocked
by the master. The slave needs to be set up using the clock as an input.
7. RESET is an active lo w INPUT pin, e xternal pull-up resistor to V
DD
is required. When driv en low it resets all internal PLD flip-flops to zero or
one, and may turn “ON” or “OFF” the output pins, including the HVOUT pins depending on the polarity configuration of the outputs in the
PLD. If a reset function is needed for the other devices on the board, the PLD inputs and outputs can be used to generate these signals.
The RESET connected to the POR pin can be used if multiple ispPAC-POWR1208 devices are cascaded together in expansion mode or if
a manual reset button is needed to reset the PLD logic to the initial state. While using the ispPAC-POWR1208 in hot-swap applications it is
recommended that either the RESET pin be connected to the POR pin, or connect a capacitor to ground (such that the time constant is 10
ms with the pull-up resistor) from the RESET pin.
8. The CREF pin requires a 0.1µF capacitor to ground, near the de vice pin. This reference is used internally by the de vice . No additional e xter-
nal circuitry should be connected to this pin.
Symbol Parameter Conditions Min. Max. Units
V
DD
Core supply voltage at pin — -0.5 6.0 V
V
DDINP
1
Digital input supply voltage for IN1-IN4 — -0.5 6.0 V
HVOUTmax HVOUT pin voltage, max = V
DD
+ 9V — -0.5 15 V
V
IN
2
Input voltage applied, digital inputs — -0.5 6.0 V
VMON Input voltage applied, V
MON
voltage monitor inputs — -0.5 7.0 V
V
TRI
Tristated or open drain output, external voltage applied (CLK
pin 26 pullup
≤
V
DD
). — -0.5 6.0 V
T
S
Storage temperature — -65 150 °C
T
A
Ambient temperature with power applied — -55 125 °C
T
SOL
Maximum soldering temperature (10 sec. at 1/16 in.) — — 260 °C
1. V
DDINP
is the supply pin that controls logic inputs IN1-IN4 only. Place 0.1µF capacitor to ground and supply the V
DDINP
pin with appropriate
supply voltage for the given input logic range.
2. Digital inputs are tolerant up to 5.5V, independent of the V
DDINP
voltage.
Pin Descriptions (Continued)
Number Name Pin Type V oltage Range Description
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Lattice Semiconductor ispPAC-POWR1208 Data Sheet
1-5
Recommended Operating Conditions
Analog Specifications
Over Recommended Operating Conditions
Reference
Voltage Monitors
Symbol Parameter Conditions Min. Max. Units
V
DD
Core supply voltage at pin 2.25 5.5 V
V
DDPROG
1
Core supply voltage at pin During E
2
cell programming 3.0 5.5 V
V
DDINP
2
Digital input supply voltage for IN1-IN4 2.25 5.5 V
V
IN
3
Input voltage digital inputs 0 5.5 V
V
MON
Voltage monitor inputs V
MON1
- V
MON12
0 6.0 V
Erase/Program
Cycles EEPROM, programmed at
V
DD
= 3.0V to 5.5V
-40°C to +85°C 1000 — Cycles
T
APROG
Ambient temperature during
programming -40 +85 °C
T
A
Ambient temperature Power applied - Industrial -40 +85 °C
Power applied - Automotive -40 +125 °C
1. The ispPAC-POWR1208 device must be powered from 3.0V to 5.5V during programming of the E
2
CMOS memory.
2. V
DDINP
is the supply pin that controls logic inputs IN1-IN4 only. Place 0.1µF capacitor to ground and supply the V
DDINP
pin with appropriate
supply voltage for the given input logic range.
3. Digital inputs are tolerant up to 5.5V, independent of the V
DDINP
voltage.
Symbol Parameter Conditions Min. Typ. Max. Units
I
DD
Supply Current Internal Clock = 250kHz — 7 15 mA
Symbol Parameter Conditions Min. Typ. Max. Units
V
REF
1
Reference voltage at CREF pin T = 25°C — 1.17 — V
1. CREF pin requires a 0.1µF capacitor to ground.
Symbol Parameter Conditions Min. Typ. Max. Units
R
IN
Input impedance 70 100 130 kΩ
VMON Range Programmable voltage monitor trip
point (192 steps) 1.03 5.72 V
VMON Accuracy Absolute accuracy of any trip point T = 25 °C,
VDD = 3.3V -0.9 +0.9 %
VMON Tempco1Temperature drift of any trip point -40°C to +85°C 50 ppm/ °C
-40°C to +125°C 76 ppm/ °C
HYST Hysteresis of VMON input,
VHYST = HYST*VMON (+/-3 to +/-13mV) VDD = 3.3V +/- 0.3% of
trip point
setting %
PSR Trip point sensitivity to VDD VDD = 3.3V 0.06 %/V
1. See typical performance curves.
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Lattice Semiconductor ispPAC-POWR1208 Data Sheet
1-6
High Voltage FET Drivers
Power-On-Reset
Symbol Parameter Conditions Min. Typ. Max. Units
VPP Range Programmable gate driver voltage
(eight steps) (Note 1) 8 — 12 V
VPP Accuracy Absolute accuracy of VPP output
voltage 25°C -10 — 10 %
VPP Step Gate driver voltage step (Note 2) — 0.5 — V
ISOURCE Range
Programmable ISOURCE current
(32 steps) FET Driver mode
-40°C to +85°C 0.5 — 50 µA
Programmable ISOURCE current
(16 steps) FET Driver mode
+85°C to +125°C (Note 3) 5.45 — 50 µA
ISOURCE Accuracy Absolute accuracy of ISOURCE
current -40°C to +125°C
ISOURCE > 0.5µA —10—%
ISTEP Relative current value, from any
ISOURCE setting to the next —15—%
RSINK Gate driver sink/discharge resistor
when setting FET driver to a LOW
state
FET Driver in OFF state
VDD = 2.25V — 8 — kΩ
1. Maximum voltage of VPP is not to exceed 7.5V over VDD.
2. The high voltage driv er outputs are set in softw are , HVOUT voltage range is betw een 8V and 12V. VDD values determine the maximum VPP.
3. For high temper ature operation from +85°C to +125°C , the lo wer HVOUT source current selections (0.5µA to 4.62µA) should not be used to
drive MOSFETs due to increased leakage current to GND. Select gate currents from 5.45µA to 50µA for high temperature use.
Symbol Parameter Conditions Min. Typ. Max. Units
VLPOR VDD supply threshold beyond which POR
output is guaranteed to be driven low VDD ramping up1— — 1.15 V
VHPOR VDD supply threshold above which POR
output is guaranteed driven high, and device
initializes VDD ramping up1— — 2.1 V
1. POR tests run with 10kΩ resistor pulled up to VDD.
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Lattice Semiconductor ispPAC-POWR1208 Data Sheet
1-7
AC/Transient Characteristics
Over Recommended Operating Conditions
Digital Specifications Over Recommended Operating Conditions
DC Input Levels: IN1-IN4
Symbol Parameter Conditions Min. Typ. Max. Units.
Voltage Monitors
tPD5 Propagation Delay. Output
transitions after a step input. Glitch filter set to 5µs.1
Input VTRIP + 100mV to VTRIP - 100mV —5—µs
tPD20 Propagation Delay. Output
transitions after a step input. Glitch filter set to 20us.1
Input VTRIP + 100mV to VTRIP - 100mV —20—µs
Oscillators
fCLK Internal Master Clock
frequency (Note 2) 230 — 330 kHz
PLDCLK
Range Programmable frequency range
of PLD clock (8 binary steps) Internal Osc 250kHz 1.95 — 250 kHz
PLDCLKext Max frequency of applied
external clock source External clock applied — — 1 MHz
Timers
Timeout
Range Range of programmable
time-out duration (15 steps) Internal Osc 250kHz 0.03 — 524 ms
1. See Typical Performance Graphs.
2. fCLK frequency sensitivity with respect to VDD, 0.4%/Volt, typical.
Symbol Parameter Conditions Min. Typ. Max. Units
IIL, IIH Input or I/O leakage current, no pull-up 0V ≤ VIN ≤ VDDINP or VDD
25 °C +/-10 µA
IPU Input pull-up current (TMS, TDI, TRST) 25 °C 70 µA
VOL [OUT5-OUT8]
[COMP1-COMP8]
[HVOUT1-HVOUT4]
ISINKOUT = 4mA 0.4 V
ISINKHVOUT Maxim um sink current for HV OUT pins in
open-drain mode [HVOUT1-HVOUT4] (Note 1) 4mA
ISINKOUT Maximum sink current for logic outputs
[OUT5-OUT8], [COMP1-COMP8] (Note 1) 20 mA
ISINKTOTAL Total combined sink currents from all
outputs [OUT, HVOUT, COMP] (Note 1) 80 mA
1. [OUT5-OUT8] and [COMP1-COMP8] can sink up to 20mA max. per pin for LEDs, etc. However, output voltage levels may exceed VOL.
Total combined sink currents from all outputs (OUT, HVOUT, COMP) should not exceed ISINKTOTAL.
Standard VIL (V) VIH (V)
Min. Max. Min. Max.
CMOS, LVCMOS3.3, LVTTL, TTL -0.3 0.8 2.0 5.5
LVCMOS2.5 -0.3 0.7 1.7 5.5
Note: VDDINP is the input supply pin for IN1-IN4 digital logic input pins. The logic threshold trip point of IN1-IN4 is dependent on the voltage at
VDDINP.
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Lattice Semiconductor ispPAC-POWR1208 Data Sheet
1-8
Transient Characteristics
Over Recommended Operating Conditions
Symbol Parameter Conditions Min. Typ. Max. Units
PLD Timing
Digital Glitch
Filter Minimum pulse width to transition through
glitch filter. Applied to IN1-IN4 20 µs
tCO Clock to Out Dela y. Rising edge of clock to
output transition. Stable input before
clock edge (Note 1) 300 ns
tSU Time that input needs to be present when
using a registered function with the clock. Data valid bef ore cloc k
(Note 1) 20 µs
tHTime that input needs to be held valid after
the clock edge when using a registered
function with the clock.
Hold data after clock 0 µs
tPD Propagation delay internal to the
embedded PLD 90 ns
tRST RESET pulse width 25 µs
1. External clock 1MHz. Open drain outputs with 2k pull-up resistor to VDD.
Note: All the above parameters apply to signal paths from the digital inputs [IN1-IN4].
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Lattice Semiconductor ispPAC-POWR1208 Data Sheet
1-9
Timing for JTAG Operations
Symbol Parameter Conditions Min Typ. Max Units
tCKMIN Minimum clock period 1 µs
tCKH TCK high time 200 ns
tCKL TCK low time 200 ns
tMSS TMS setup time 15 ns
tMSH TMS hold time 50 ns
tDIS TDI setup time 15 ns
tDIH TDI hold time 50 ns
tDOZX TDO float to valid delay 200 ns
tDOV TDO valid delay 200 ns
tDOXZ TDO valid to float delay 200 ns
tRSTMIN Minimum reset pulse width 40 ns
tPWP Time for a programming operation140 100 ms
tPWE Time for an erase operation 40 100 ms
1. tPWP represents programming pulse width for a single row of E2CMOS cells.
tCK
tMSS tMSS tMSStMSH
tDIS tDIH
tCKH tCKMIN
tCKL
tMS
tCK
tMS
tDI
tDO
tDOZH tDOXZ
tDOV
tPWP, tPWE
Program and Erase cycles
executed in Run-Test/Idle
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Lattice Semiconductor ispPAC-POWR1208 Data Sheet
1-10
Typical Performance Graphs
0
25
10-1 -0.8 -0.6 -0.4 -0.2 0 10.2 0.4 0.6 0.8 20 50 100 200
50
75
100
125
Propagation Delay (μs)
Count
Input Overdrive (mV)Trip Point Error %
Propagation Delay vs. OverdriveVMON Trip Point Error 25°C
Glitch Filter = 20μs
Glitch Filter = 5μs
Note: Typical propagation delay of VMON inputs to outputs
as a function of overdrive beyond selected trip point.
% Error
Temperature (°C)
Typical VMON Comparator Trip Point
Accuracy vs. Temperature
-50 0 50 100 150
0
1000
2000
3000
4000
5000
6000
7000
-0.5
0
0.5
1
1.5
2
2.5
3
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Lattice Semiconductor ispPAC-POWR1208 Data Sheet
1-11
Table1-1. VMON Trip Point Table1
Table 1-1 shows all possible comparator trip point voltage settings. The inter nal resistive divider allows ranges for
1.2V, 1.8V, 2.5V, 3.3V and 5.0V. There are 192 available v oltages, ranging from 1.036V to 5.723V. In addition to the
192 voltage monitor trip points, the user can add additional resistors outside the device to divide down the voltage
and achie ve virtually any voltage trip point. This allows the capability to monitor higher voltages such and 12V, 15V,
24V, etc. Voltage monitor trip points are set in the graphical user interface of PAC-Designer software by simple pull-
down menus. The user simply selects the given range and corresponding trip point value. Attenuation and refer-
ence values are set internally using E2CMOS configuration bits internal to the device.
Figure 1-2 shows a single comparator, the attenuation network and reference used to program the monitor trip
points. Each of the twelve comparators are independently set in the same way.
Theory Of Operation
The ispPAC-POWR1208 incorporates programmable voltage monitors along with digital inputs and outputs as well
as high voltage FET gate drivers to control MOSFETs for ramping up power supply rails. The 16 macrocell PLD
inputs are from the 12 v oltage monitors and four digital inputs. There are four embedded programmable timers that
interface with the PLD, along with an internal programmable oscillator.
The 12 independently programmable voltage monitors each have 192 programmable trip points.
Figure 1-2 shows a simplified schematic representation of one of these monitors.
1.2 low 1.2 high 1.5 low 1.5 high 1.8 low 1.8 high 2.5 low 2.5 high 3.3 low 3.3 high 5.0 low 5.0 high
1.036 1.202 1.291 1.502 1.549 1.801 2.153 2.500 2.842 3.297 4.299 4.991
1.046 1.213 1.303 1.516 1.564 1.818 2.173 2.524 2.869 3.328 4.340 5.038
1.056 1.225 1.316 1.531 1.579 1.836 2.195 2.549 2.897 3.361 4.383 5.088
1.066 1.237 1.329 1.546 1.595 1.854 2.216 2.574 2.926 3.394 4.426 5.138
1.076 1.249 1.341 1.560 1.609 1.871 2.237 2.597 2.952 3.425 4.466 5.185
1.087 1.261 1.354 1.575 1.625 1.889 2.258 2.622 2.981 3.458 4.509 5.235
1.096 1.272 1.366 1.590 1.639 1.906 2.279 2.646 3.008 3.489 4.550 5.282
1.107 1.284 1.379 1.605 1.655 1.924 2.300 2.671 3.036 3.522 4.593 5.332
1.117 1.295 1.391 1.619 1.669 1.941 2.320 2.694 3.063 3.553 4.633 5.379
1.127 1.307 1.404 1.634 1.685 1.959 2.342 2.719 3.091 3.586 4.676 5.429
1.137 1.319 1.417 1.649 1.700 1.977 2.363 2.744 3.120 3.619 4.719 5.479
1.147 1.331 1.429 1.663 1.715 1.994 2.384 2.768 3.147 3.650 4.760 5.526
1.157 1.343 1.442 1.678 1.730 2.012 2.405 2.793 3.175 3.683 4.803 5.576
1.168 1.355 1.455 1.693 1.746 2.030 2.427 2.818 3.203 3.716 4.846 5.626
1.178 1.366 1.467 1.707 1.761 2.047 2.447 2.841 3.230 3.747 4.886 5.673
1.188 1.378 1.480 1.722 1.776 2.065 2.469 2.866 3.259 3.780 4.929 5.723
1.All possible comparator trip voltages using internal attenuation settings.
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Lattice Semiconductor ispPAC-POWR1208 Data Sheet
1-12
Figure 1-2. Voltage Monitors
Each monitor consists of three major subsystems. The core of the monitor is a voltage comparator. This compara-
tor outputs a HIGH signal to the PLD array if the voltage at its positive terminal is greater than that at its negative
terminal, otherwise it outputs a LOW signal. A small amount of hysteresis is provided by the comparator to reduce
the effects of input noise.
The input signal is attenuated by a programmable resistive divider before it is fed into the comparator. This feature
is used to determine the coarse range in which the comparator should trip (e.g. 1.8V, 3.3V, 5V). Twelve possible
ranges are available from the input divider network. The comparator’s negative terminal is obtained from a pro-
grammable reference source (Reference), which may be set to one of 16 possible values scaled in approximately
1% increments from each other, allowing for fine tuning of the voltage monitor’s trip points. This combination of
coarse and fine adjustment supports 192 possible trip-point voltages for a given monitor circuit. Because each
monitor’s reference and input divider settings are completely independent of those of the other monitor circuits’, the
user can set any input monitor to any of the 192 available settings.
Comparator Hysteresis
PLD Architecture
The ispPAC-POWR1208 digital logic is composed of an inter nal PLD that is programmed to perform the sequenc-
ing functions. The PLD architecture allows flexibility in designing various state machines and control logic used for
monitoring. The macrocell shown in Figure 1-3 is the heart of the PLD. There are 16 macrocells that can be used to
control the functional states of the sequencer state machine or other control or monitoring logic. The PLD AND
array shown in Figure 1-4 has 36 inputs, and 81 product terms (PTs). The resources from the AND array feed the
16 macrocells. The resources within the macrocells share routing and contain a product-term allocation array. The
VMON
Range Setting1T ypical Hysteresis on
Over V oltage Range Typical Hysteresis on
Under V oltage Range Units
5.0V +/- 16.2 +/- 14.0 mV
3.3V +/- 10.7 +/- 9.2 mV
2.5V +/- 8.1 +/- 7.0 mV
1.8V +/- 5.8 +/- 5.0 mV
1.5V +/- 4.9 +/- 4.2 mV
1.2V +/- 3.9 +/- 3.4 mV
1. The hysteresis scales depending on the voltage monitor range that is selected. The values shown are typical
and are centered around the nominal voltage trip point for a given range selection.
To PLD Array
Reference
Monitor Voltage
VMON1..VMON12
3mV
Hysteresis
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Lattice Semiconductor ispPAC-POWR1208 Data Sheet
1-13
product ter m allocation array greatly expands the PLD’s ability to implement complex logical functions by allowing
logic to be shared between adjacent blocks and distributing the product terms to allow for wider decode functions.
The basic macrocell has five product terms that f eed the OR gate and the flip-flop. The flip-flop in each macrocell is
independently configured. It can be programmed to function as a D-Type or T-Type flip-flop . The combinatorial func-
tions are achie v ed through the b ypass MUX function sho wn. By having the polarity control XOR, the logic reduction
can be best fit to minimize the number of product terms. The flip-flop’s clock is driv en from a common cloc k that can
be generated from a pre-scaled, on-board clock source or from an external clock. The macrocell also supports
asynchronous reset and preset functions, derived from either product terms, the global reset input or the power-on
reset signal.
Figure 1-3. ispPAC-POWR1208 Macrocell Block Diagram
PT0
PT1
PT2
PT3
PT4
D/T Q
RPTo ORP
CLK
Clock
Polarity
Macrocell flip-flop provides
D, T, or combinatorial
output with polarity
Product T erm Allocation
Global Reset Power On Reset
Global Polarity Fuse for
Init Product Term
Block Init Product Term
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Lattice Semiconductor ispPAC-POWR1208 Data Sheet
1-14
Figure 1-4. PLD and Timer Functional Block Diagram
MC0
Timer1
MC1
MC2
MC3
MC4
MC5
MC6
MC7
MC8
MC9
MC10
MC11
MC12
MC13
MC14
MC15
Clock Generation
Routing
Pool
4
16
IN[1:4]
VMON[1:12]
Comparators
4
12
Output
Routing
Pool
HVOUT1
HVOUT2
HVOUT3
HVOUT4
OUT5
OUT6
OUT7
OUT8
36 Inputs
81 PTs
16 Outputs
POR/RESET
BLK-INIT PT
AND
Array
Timer2
Timer3
Timer4
16
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Lattice Semiconductor ispPAC-POWR1208 Data Sheet
1-15
Clock and Timer Systems
Figure 1-5 shows a bloc k diagr am of the ispPAC-PO WR1208’s internal clock and timer systems. The PLD cloc k can
be programmed with eight different frequencies based on the internal oscillator frequency of 250kHz.
Figure 1-5. Clock and Timer Block
Table 1-2. PLD Clock Prescaler1
The inter nal oscillator runs at a fixed frequency of 250kHz. This main signal is then fed to the PLD clock pre-scaler
and also the Timer Clock pre-scaler (Figure 1-5). For the PLD Clock, the main 250kHz oscillator is divided down to
eight selectable frequencies shown in the Table 1-2. The architecture of the clock networ k allows the PLD clock to
be driven to the CLK pin. This enables the user access to the PLD clock as an output for expansion mode or other
uses of the (CLK) clock pin.
Schematically, when the switch is in the upper position, the internal oscillator drives the PLD clock pre-scaler and
the timer pre-scaler. In this mode, the CLK pin is an open-drain output and represents the same frequency as the
PLD clock. This is used when operating other devices (such as “slave” sequencing devices) in a synchronized
mode. When the switch is in the lower position, the CLK pin is an input and must be driven with an exter nal clock
source. When driven from an external source, the same PLD clock pre-scaler is availab le to this external clock. The
frequencies available for the PLD clock will be the external clock frequency divided by 1, 2, 4, 8, 16, 32, 64 or 128,
depending on the programmable value chosen.
The Timer Cloc k Pre-Scaler divides the internal 250kHz oscillator (or external clock, if selected) do wn bef ore it gen-
erates the clock for the four programmable timers. The pre-scaler has eight different divider ratios: Divide by 4, 8,
PLD Clock Frequency (kHz) PLD Prescaler Divider
250 1
125 2
62.5 4
31.3 8
15.6 16
7.8 32
3.9 64
2 128
1. Values based on 250kHz clock.
Internal
OSC
250kHz Timer Prescaler
(Time Out Range)
PLD Clock
Prescaler
CLK
Timer1
Timer2
Timer3
Timer4
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Lattice Semiconductor ispPAC-POWR1208 Data Sheet
1-16
16, 32, 64, 128, 256 and 512 (Table 1-3). After the clock for the timers is divided down, it is used to drive the pro-
grammable timers. The four timers share the same timer clock frequency but may have different end count values.
The timers can cover a range from 32us to 524ms for the internal oscillator. Longer delays can be achieved by
using the external clock as an input.
Table 1-3. Timer Values1
For design entry, the user can select the source for the clock and the PAC-Designer software will calculate the
appropriate delays in an easy-to-select menu format.
The control inputs f or Timer1-Timer4 can be driven b y any of the 16 PLD macrocell outputs . The reset f or the timers
is a function of the Global Reset pin (RESET), a pow er-on reset or when the timer gate goes lo w. The waveforms in
Figure 1-6 show the basic timer star t and reset functions. Timer and clock divider values are entered in during the
design phase using PAC-Designer software, simple pull-down menus allow the user to select the clocking mode
and the values for the timers and the PLD clock.
Figure 1-6. Timer Waveforms
÷÷
÷÷ 4
62 kHz ÷÷
÷÷ 8
31.2 kHz ÷÷
÷÷ 16
15.6 kHz ÷÷
÷÷ 32
7.8 kHz ÷÷
÷÷ 64
3.9 kHz ÷÷
÷÷ 128
2 kHz ÷÷
÷÷ 256
1 kHz ÷÷
÷÷ 512
0.5 kHz
0.032 ms
0.064 ms 0.064 ms
0.128 ms 0.128 ms 0.128 ms
0.256 ms 0.256 ms 0.256 ms 0.256 ms
0.512 ms 0.512 ms 0.512 ms 0.512 ms 0.512 ms
1.024 ms 1.024 ms 1.024 ms 1.024 ms 1.024 ms 1.024 ms
2.048 ms 2.048ms 2.048ms 2.048ms 2.048ms 2.048ms 2.048ms
4.096 ms 4.096 ms 4.096 ms 4.096 ms 4.096 ms 4.096 ms 4.096 ms 4.096 ms
8.192 ms 8.192 ms 8.192 ms 8.192 ms 8.192 ms 8.192 ms 8.192 ms
16.384 ms 16.384 ms 16.384 ms 16.384 ms 16.384 ms 16.384 ms
32.768 ms 32.768 ms 32.768 ms 32.768 ms 32.768 ms
65.536 ms 65.536 ms 65.536 ms 65.536 ms
131.072 ms 131.072 ms 131.072 ms
262.144 ms 262.144 ms
524.288 ms
1. Timer values based on 250kHz clock.
Timer Period
Timer Gate
Timer Output
Timer Period
(From PLD)
(To PLD)
Start
Timer Timer
Expired Reset
Timer
ProgrammableTimer
Delay
Start
Timer Timer
Expired
ProgrammableTimer
Delay
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Lattice Semiconductor ispPAC-POWR1208 Data Sheet
1-17
Note that if the clock module is configured as “slave” (i.e. the CLK is an input), the actual time-out of the four timers
is determined by the external clock frequency.
Output Configuration Modes
The output pins for the ispPAC-POWR1208 device are programmable for different functional modes. The four out-
puts HVOUT1-HVOUT4, can be used as FET gate drivers or be programmed as open-drain digital outputs.
Figure 1-7 explains the details of the gate driver mode.
Figure 1-7. Basic Function Diagram for an Output in Gate Driver Mode
Figure 1-7 shows an output programmed for gate driver mode. In this mode the output is a current source that is
programmable between 0.5µA to 50µA. The maximum voltage that the output level at the pin will rise is also pro-
grammable. The levels required depend on the gate-to-source threshold of the FET and the supply voltage. The
maximum level needs to be sufficient to turn the gate-to-source threshold on and accommodate for the voltage of
the board also, since the source pin of the FET is tied to the supply of the target board. When the HVOUT pin is
sourcing current, charging a FET gate, the current is programmable between 0.5µA and 50µA. When the driver is
turned to the off state, the driver will sink current. through the 8kΩ resistor.
Predicting MOSFET T urn-on Time
Because the ispPAC-POWR1208’s MOSFET output drivers source a precise and well-defined output current, it
becomes possible to predict MOSFET gate rise times if one knows the value of the load capacitance presented by
the MOSFET being driven. The other method is by relating the total gate charge to the gate-to-source voltage.
ISource
(0.5-50uA)
≈ 8kΩ
VPP
(8-12V)
Digital In
From Sequence
Controller
Output to
IC Pin
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Lattice Semiconductor ispPAC-POWR1208 Data Sheet
1-18
Figure 1-8. MOSFET Gate Charge vs. Gate-Source Voltage
Using this method, it becomes straightforward to estimate the gate rise time for a given charging current. As an
example a MOSFET’s source voltage (VS) will be 3.3V when the device is fully switched on, while the gate voltage
(VG) will be 10V in this condition. The device’s gate-to-source voltage (VGS) will therefore be 6.7V. Reading across
and down the plot of Figure 1-8, a VGS of 6.7V corresponds to ~40 nC of gate charge (QG). Because charge is
equal to the product of current (I) and time (tCHARGE-TIME) when current is constant, gate charging time can be
expressed as:
(1)
(2)
For this example, let us assume a charging current of 10.9µA. Gate charging time is given by:
(3)
Validation of this result can be seen in the scope plot shown in Figure 1-9. The top set of traces shows gate rise
times for various (5.5µA to 50.3µA) gate dr ive currents. The trace labeled 10.9µA shows a 0-10V rise time of just
over 3 milliseconds, which agrees to within 25% of our predicted value, well within the limits of device-to-device
variation.
VGS, Gate-to-source Voltage (V)
QG, Total Gate Charge (nC)
0204060
0
3
6
9
=
idQ
dt
=
tCHARGE-TIME QG
I
= = 3.7 x 1
tCHARGE-TIME 40 x 10-9C
10.9 x 10-6A
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Lattice Semiconductor ispPAC-POWR1208 Data Sheet
1-19
Figure 1-9. Gate and Source Voltage Responses for a 3.3V Supply
MOSFET gate capacitance ranges from hundreds to thousands of picoFarads. Refer to the MOSFET manufac-
turer’s data sheet for values of Cgs (Capacitance gate-to-source). If slower r amps are required, an additional exter-
nal low leakage capacitor (e .g. a polycarbonate or other poly type capacitor) can be added from the gate to ground.
As a good design practice, it is recommended that a series resistor of 10-100Ω be placed in the gate drive signal
near the FET gate pin.
Charge Pump
F our internal charge pumps are provided to fully support e xternal N-channel FET devices . No external components
are required f or the charge pumps. The output voltage is programmab le from 8 to 12V in 0.5V steps . The user m ust
select a high voltage limit no greater than 7.5V above VDD (the software assists this process). This voltage is con-
trolled with an on-chip feedback loop, and is independent of the actual supply voltage.
Programmable Output Voltage Levels for HVOUT1- HVOUT4
There are eight selectable steps for the output voltage of the FET driv ers when in FET driver mode . The output pins
HVOUT1-4 are current source outputs, each with a programmable current. The current is programmable in 32 dif-
ferent steps ranging from .5µA to 50µA. The voltage that the pin is capable of driving to is listed in Table 1-4. For
each supply range, the charge-pump range will be set by the software.
Table 1-4. HVOUT Gate Driver Voltage Range
VDD = 2.5V VDD = 3.3V VDD = 5V
888
8.5 8.5 8.5
999
9.5 9.5 9.5
10 10
10.5
11
12
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Lattice Semiconductor ispPAC-POWR1208 Data Sheet
1-20
IEEE Standard 1149.1 Interface
Communication with the ispPAC-POWR1208 is facilitated via an IEEE 1149.1 test access port (TAP). It is used by
the ispPAC-POWR1208 as a ser ial programming interface, and not for boundary scan test purposes. There are no
boundary scan logic registers in the ispPAC-POWR1208 architecture. This does not prevent the ispPAC-
PO WR1208 from functioning correctly, howe ver, when placed in a valid serial chain with other IEEE 1149.1 compli-
ant devices. Since the ispPAC-POWR1208 is used to powerup other devices, it should be programmed in a sepa-
rate chain from PLDs, FPGAs or other JTAG devices.
A brief descr iption of the ispPAC-POWR1208 ser ial interface follows. For complete details of the reference specifi-
cation, ref er to the pub lication, Standard Test Access Port and Boundary-Scan Architecture, IEEE Std 1149.1-1990
(which now includes IEEE Std 1149.1a-1993).
Overview
An IEEE 1149.1 test access port (TAP) provides the control interface for serially accessing the digital I/O of the isp-
PAC-POWR1208. The TAP controller is a state machine driven with mode and clock inputs. Under the correct pro-
tocol, instructions are shifted into an instruction register, which then determines subsequent data input, data
output, and related operations. Device programming is perfor med by addressing var ious registers, shifting data in,
and then executing the respective program instruction. The programming instructions transfer the data into internal
E2CMOS memory. It is these non-volatile memory cells that determine the configuration of the ispPAC-POWR1208.
By cycling the TAP controller through the necessary states, data can also be shifted out of the various registers to
verify the current ispPAC-POWR1208 configuration. Instructions exist to access all data registers and perform
internal control operations.
For compatibility between compliant devices, two data registers are mandated by the IEEE 1149.1 specification.
Other registers are functionally specified, but inclusion is strictly optional. Finally, there are provisions for optional
user data registers that are defined by the manufacturer. The two required registers are the bypass and boundary-
scan registers. For ispPAC-POWR1208, the bypass register is a 1-bit shift register that provides a short path
through the device when boundar y testing or other operations are not being perfor med. The ispPAC-POWR1208,
as mentioned earlier has no boundary-scan logic and therefore no boundary scan register. All instr uctions relating
to boundar y scan operations place the ispPAC-POWR1208 in the BYPASS mode to maintain compliance with the
specification.
The optional identification (IDCODE) register described in IEEE 1149.1 is also included in the ispPA C-POWR1208.
Six additional user data registers are included in the TAP of the ispPAC-POWR1208 as shown in Figure 1-10. Most
of these additional registers are used to program and ver ify the analog configuration (CFG) and PLD bits. A status
register is also provided to read the status of the twelve analog comparators.
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Lattice Semiconductor ispPAC-POWR1208 Data Sheet
1-21
Figure 1-10. TAP Registers
TAP Controller Specifics
The TAP is controlled b y the Test Clock (TCK) and Test Mode Select (TMS) inputs. These inputs determine whether
an Instruction Register or Data Register operation is performed. Driven by the TCK input, the TAP consists of a
small 16-state controller. In a given state, the controller responds according to the lev el on the TMS input as shown
in Figure 1-11. Test Data In (TDI) and TMS are latched on the rising edge of TCK, with Test Data Out (TDO) becom-
ing valid on the falling edge of TCK. There are six steady states within the controller : Test-Logic-Reset, Run-Test/
Idle, Shift-Data-Register, Pause-Data-Register, Shift-Instruction-Register, and Pause-Instruction-Register. But
there is only one steady state for the condition when TMS is set high: the Test-Logic-Reset state. This allows a
reset of the test logic within five TCKs or less by keeping the TMS input high. Test-Logic-Reset is the power-on
default state.
When the correct logic sequence is applied to the TMS and TCK inputs, the TAP will e xit the Test-Logic-Reset state
and move to the desired state. The next state after Test-Logic-Reset is Run-Test/Idle. Until a data or instruction
scan is performed, no action will occur in Run-Test/Idle (steady state = idle). After Run-Test/Idle, either a data or
instruction scan is performed. The states of the Data and Instruction Register blocks are identical to each other dif-
fering only in their entr y points. When either block is entered, the first action is a capture operation. For the Data
Registers, the Capture-DR state is ver y simple; it captures (parallel loads) data onto the selected serial data path
(previously chosen with the appropriate instruction). For the Instr uction Register, the Capture-IR state will always
load the IDCODE instruction. It will always enable the ID Register for readout if no other instruction is loaded pr ior
to a Shift-DR operation. This, in conjunction with mandated bit codes, allows a “blind” interrogation of any device in
a compliant IEEE 1149.1 serial chain.
STATUS REGISTER (12 bits)
IDCODE REGISTER (32 bits)
UES REGISTER (16 bits)
CFG REGISTER (41 bits)
CFG ADDRESS REGISTER (4 bits)
PLD DATA REGISTER (81 bits)
PLD ADDRESS REGISTER (75 bits)
BYPASS REGISTER (1 bit)
TEST ACCESS PORT
(TAP) LOGIC OUTPUT
LATCH
MULTIPLEXER
ANALOG
CONFIGURATION
E2 NON-VOLATILE
MEMORY
(164 bits)
PLD
AND / ARCH
E2 NON-VOLATILE
MEMORY
(6075 bits)
INSTRUCTION REGISTER (6 bits)
ANALOG COMPARATOR ARRAY (12 bits)
TDI TCK TMS TDO
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Lattice Semiconductor ispPAC-POWR1208 Data Sheet
1-22
Figure 1-11. TAP States
From the Capture state, the TAP transitions to either the Shift or Exit1 state. Normally the Shift state follows the
Capture state so that test data or status information can be shifted out or new data shifted in. Following the Shift
state, the TAP either returns to the Run-Test/Idle state via the Exit1 and Update states or enters the P ause state via
Exit1. The Pause state is used to temporarily suspend the shifting of data through either the Data or Instruction
Register while an external operation is performed. From the Pause state, shifting can resume by re-entering the
Shift state via the Exit2 state or be terminated by entering the Run-Test/Idle state via the Exit2 and Update states.
If the proper instruction is shifted in during a Shift-IR operation, the next entr y into Run-Test/Idle initiates the test
mode (steady state = test). This is when the device is actually prog rammed, er ased or v erified. All other instructions
are executed in the Update state.
Test Instructions
Like data registers, the IEEE 1149.1 standard also mandates the inclusion of certain instructions. It outlines the
function of three required and six optional instructions. Any additional instructions are left exclusively for the manu-
f acturer to determine. The instruction word length is not mandated other than to be a minimum of two bits , with only
the BYPASS and EXTEST instr uction code patterns being specifically called out (all ones and all zeroes respec-
tively). The ispPAC-POWR1208 contains the required minimum instruction set as well as one from the optional
instruction set. In addition, there are several proprietary instructions that allow the device to be configured, verified,
and monitored. For ispPAC-POWR1208, the instruction word length is 6-bits. All ispPAC-POWR1208 instructions
available to users are shown in Table 1-5.
1
0
0
1
1
0
0
1
0
0
0
0
1
0
1
1
0101
1
1
0
1
0
0
111
0
0
1
Update-IR
Exit2-IR
Pause-IR
Exit1-IR
Shift-IR
Capture-IR
Select-IR-Scan
Update-DR
Exit2-DR
Pause-DR
Exit1-DR
Shift-DR
Capture-DR
Select-DR-Scan
Run-Test/Idle
Test-Logic-Reset
Note: The value shown adjacent to each state transition represents the signal present
at TMS at the time of a rising edge at TCK.
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Lattice Semiconductor ispPAC-POWR1208 Data Sheet
1-23
Table 1-5. ispPAC-POWR1208 TAP Instruction Table
BYPASS is one of the three required instructions. It selects the Bypass Register to be connected between TDI and
TDO and allows serial data to be transferred through the device without affecting the operation of the ispPAC-
POWR1208. The IEEE 1149.1 standard defines the bit code of this instruction to be all ones (111111).
The required SAMPLE/PRELOAD instruction dictates the Boundary-Scan Register be connected between TDI
and TDO. The ispPAC-POWR1208 has no boundar y scan register, so for compatibility it defaults to the BYPASS
mode whenever this instruction is received. The bit code for this instruction is defined by Lattice as shown in
Table 1-5.
The EXTEST (external test) instr uction is required and would normally place the device into an exter nal boundary
test mode while also enabling the boundary scan register to be connected between TDI and TDO. Again, since the
ispPAC-POWR1208 has no boundary scan logic, the device is put in the BYPASS mode to ensure specification
compatibility. The bit code of this instruction is defined by the 1149.1 standard to be all zeros (000000).
The optional IDCODE (identification code) instruction is incorporated in the ispPAC-POWR1208 and leaves it in its
functional mode when executed. It selects the Device Identification Register to be connected between TDI and
TDO. The Identification Register is a 32-bit shift register containing information regarding the IC manufacturer,
Instruction Code Description
EXTEST 000000 External Test. Defaults to BYPASS.
ADDPLD1000001 Address PLD address register (75 bits).
DATAPLD1000010 Address PLD column data register (81 bits).
ERASEAND1, 2 000011 Bulk Erase AND array.
ERASEARCH1, 2 000100 Bulk Erase Architect array.
PROGPLD1, 2 000101 Program PLD column data register into E2.
PROGESF1, 2 000110 Program the Electronic Security Fuse bit.
BYPASS 000111 Bypass (connect TDI to TDO).
READPLD1001000 Reads PLD column data from E2 to the register (81 bits).
DISCHARGE1001001 F ast VPP discharge.
ADDCFG1001010 Address CFG array address (4 bits).
DATACFG1001011 Address CFG data (41 bits).
ERASECFG1, 2 001100 Bulk Erase CFG data.
PROGCFG1, 2 001101 Program CFG data register into E2.
READCFG1001110 Read CFG column data from E2 to the register (41 bits).
CFGBE1, 2 010110 Bulk Erase all E2 memory (CFG, PLD, USE, and ESF).
SAFESTATE1010111 Digital outputs hiZ (FET pulled L)
PROGRAMEN1011000 Enable program mode (SAFESTATE IO)
IDCODE 011001 Address Identification Code data register (32 bits).
PROGRAMDIS 011010 Disable Program mode (normal IO)
ADDSTATUS 011011 Address STATUS register (12 bits).
SAMPLE 011100 Sample/Preload. Default to Bypass.
ERASEUES1, 2 011101 Bulk Erase UES.
SHIFTUES 011110 Reads UES data from E2 and selects the UES register (16 bits).
PROGUES1, 2 011111 Program UES data register into E2.
BYPASS 1xxxxx Bypass (connect TDI to TDO).
1. When these instructions are executed, the outputs are placed in the same mode as the instruction SAFESTATE (as
described later) to prevent invalid and potentially destructive power supply sequencing.
2. Instructions that erase or program the E2CMOS memory must be executed only when the supply to the device is
maintained at 3.0V to 5.5V.
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Lattice Semiconductor ispPAC-POWR1208 Data Sheet
1-24
device type and version code (Figure 1-12). Access to the Identification Register is immediately available, via a
TAP data scan operation, after power-up of the device, or by issuing a Test-Logic-Reset instruction. The bit code f or
this instruction is defined by Lattice as shown in Table 1-5.
Figure 1-12. ID Code
ispPAC-POWR1208 Specific Instructions
There are 21 unique instructions specified by Lattice for the ispPAC-POWR1208. These instr uctions are primarily
used to interface to the various user registers and the E2CMOS non-volatile memory. Additional instructions are
used to control or monitor other features of the device. A brief descr iption of each unique instr uction is provided in
detail below, and the bit codes are found in Table 1-5.
ADDPLD – This instruction is used to set the address of the PLD AND/ARCH arrays for subsequent program or
read operations. This instruction also forces the outputs into the SAFESTATE.
DATAPLD – This instruction is used to shift PLD data into the register prior to programming or reading. This
instruction also forces the outputs into the SAFESTATE.
ERASEAND – This instruction will bulk erase the PLD AND array. The action occurs at the second r ising edge of
TCK in Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAMEN instruction).
This instruction also forces the outputs into the SAFESTATE.
ERASEARCH – This instruction will bulk erase the PLD ARCH array. The action occurs at the second r ising edge
of TCK in Run-Test-Idle JTAG state . The de vice must already be in prog ramming mode (PR OGRAMEN instruction).
This instruction also forces the outputs into the SAFESTATE.
PROGPLD – This instruction programs the selected PLD AND/ARCH array column. The specific column is prese-
lected by using ADDPLD instruction. The programming occurs at the second rising edge of the TCK in Run-Test-
Idle JTAG state. The device must already be in programming mode (PROGRAMEN instruction). This instruction
also forces the outputs into the SAFESTATE.
PROGESF – This instruction is used to program the electronic security fuse (ESF) bit. Programming the ESF bit
protects proprietary designs from being read out. The programming occurs at the second rising edge of the TCK in
Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAMEN instruction). This
instruction also forces the outputs into the SAFESTATE.
READPLD – This instruction is used to read the content of the selected PLD AND/ARCH array column. This spe-
cific column is preselected by using ADDPLD instruction. This instruction also forces the outputs into the SAF-
ESTATE.
DISCHARGE – This instruction is used to discharge the internal programming supply v oltage after an erase or pro-
gramming cycle and prepares ispPAC-POWR1208 for a read cycle. This instruction also forces the outputs into the
SAFESTATE.
XXXX / 0000 0001 0100 0000 / 0000 0100 001 / 1
MSB LSB
Version
(4 bits)
E2 Configured
Part Number
(16 bits)
0140h = ispPAC-POWR1208 JEDEC Manufacturer
Identity Code for
Lattice Semiconductor
(11 bits) Constant 1
(1 bit)
per 1149.1-1990
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Lattice Semiconductor ispPAC-POWR1208 Data Sheet
1-25
ADDCFG – This instruction is used to set the address of the CFG arra y for subsequent program or read operations .
This instruction also forces the outputs into the SAFESTATE.
DATACFG – This instruction is used to shift data into the CFG register prior to programming or reading. This
instruction also forces the outputs into the SAFESTATE.
ERASECFG – This instruction will bulk erase the CFG array. The action occurs at the second rising edge of TCK in
Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAMEN instruction). This
instruction also forces the outputs into the SAFESTATE.
PROGCFG – This instruction programs the selected CFG array column. This specific column is preselected by
using ADDCFG instruction. The programming occurs at the second rising edge of the TCK in Run-Test-Idle JTAG
state. The device must already be in programming mode (PROGRAMEN instruction). This instruction also forces
the outputs into the SAFESTATE.
READCFG – This instruction is used to read the content of the selected CFG array column. This specific column is
preselected by using ADDCFG instruction. This instruction also forces the outputs into the SAFESTATE.
CFGBE – This instruction will bulk erase all E2CMOS bits (CFG, PLD, UES, and ESF) in the ispPAC-POWR1208.
The de vice must already be in programming mode (PROGRAMEN instruction). This instruction also forces the out-
puts into the SAFESTATE.
SAFESTATE – This instruction tur ns off all of the open-drain output transistors. Pins that are programmed as FET
drivers will be placed in the active low state. This instruction is effective after Update-Instruction-Register JTAG
state.
PROGRAMEN – This instruction enables the programming mode of the ispPAC-POWR1208. This instr uction also
forces the outputs into the SAFESTATE.
IDCODE – This instruction connects the output of the Identification Code Data Shift (IDCODE) Register to TDO
(Figure 1-13), to support reading out the identification code.
Figure 1-13. IDCODE Register
PROGRAMDIS – This instruction disables the programming mode of the ispPAC-POWR1208. The Test-Logic-
Reset JTAG state can also be used to cancel the programming mode of the ispPAC-POWR1208.
ADDSTATUS – This instruction is used to both connect the status register to TDO (Figure 1-14) and latch the 12
voltage monitor (comparator outputs) into the status register. Latching of the 12 comparator outputs into the status
register occurs during Capture-Data-Register JTAG state.
Figure 1-14. Status Register
ERASEUES – This instruction will bulk erase the content of the UES E2CMOS memory. The device must already
be in programming mode (PR OGRAMEN instruction). This instruction also forces the outputs into the SAFESTATE.
SHIFTUES – This instruction both reads the E2CMOS bits into the UES register and places the UES register
between the TDI and TDO pins (as shown in Figure U), to suppor t programming or reading of the user electronic
signature bits.
TDO
Bit
0
Bit
1
Bit
2
Bit
3
Bit
4
Bit
27
Bit
28
Bit
29
Bit
30
Bit
31
TDO
VMON
12
VMON
11
VMON
10
VMON
9
VMON
8
VMON
7
VMON
6
VMON
5
VMON
4
VMON
3
VMON
2
VMON
1
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Lattice Semiconductor ispPAC-POWR1208 Data Sheet
1-26
Figure 1-15. UES Register
PROGUES – This instruction will program the content of the UES Register into the UES E2CMOS memory. The
device must already be in programming mode (PROGRAMEN instruction). This instruction also forces the outputs
into the SAFESTATE.
Notes:
In all of the descriptions above, SAFESTATE refers both to the instruction and the state of the digital output pins, in
which the open-drains are tri-stated and the FET drivers are pulled low.
Before any of the above programming instructions are executed, the respective E2CMOS bits need to be erased
using the corresponding erase instruction.
Application Example
The ispPAC-PO WR1208 device has 12 comparators to monitor v arious power supply levels . The comparators each
have a programmable trip point that is programmed by the user at design time. The output of the comparators feed
into the PLD logic array to drive the state machine logic or monitor logic. The outputs of comparators
COMP1...COMP8 are also routed to e xternal pins to be monitored directly or can be used to drive additional control
logic if expansion is required. The comparator outputs are open-drain type output buffers and require a pull up
resistor to drive a logic high. All 12 comparators have hysteresis, the hysteresis is dependent on the voltage trip
point scale that is set, it ranges from 3.4mV for the 1.2V monitor supply range to 16.2mV for the 5.0V monitor sup-
ply range. The comparators can be set with a trip point from 1.03V to 5.72V, with 192 different values. The applica-
tion diagram shows a set-up that can monitor and control multiple power supplies. The ispPAC-POWR1208 device
controls FET switches to ramp the supplies at different slew rates and time delays. The digital outputs and inputs
are also used to interface with the board that is being powered up.
To reduce the possibility of RF oscillation, a gate resistor (RG) is often inserted in series with the gate of the MOS-
FET power switch. This resistor should be placed physically close to the MOSFET gate terminal, and connected by
as shor t a PCB trace as is feasible. An appropriate value for these gate resistors is highly dependent on both the
characteristics of the MOSFET being used and the circumstances of the application, but will often be in the range
of 10Ω to 100Ω.
TDO
Bit
0
Bit
1
Bit
2
Bit
3
Bit
4
Bit
5
Bit
6
Bit
7
Bit
8
Bit
9
Bit
10
Bit
11
Bit
12
Bit
13
Bit
14
Bit
15
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Lattice Semiconductor ispPAC-POWR1208 Data Sheet
1-27
Figure 1-16. Typical Application Example: ispPAC-POWR1208 Driving [4] FET Switches [4] Digital OE/EN
Lines
-48V
Primary +
Gnd
+
-
+5V
+3.3V
+2.5V
+1.8V +1.8V
ispPAC-POWR1208
Power Sequence
Controller
HVOUT1
0.1uF10uF
HVOUT2
HVOUT3
HVOUT4
OUT5
OUT6
OUT7
OUT8
DC/DC Supply
or Regulator
OE/EN
Digital
Logic
EN
Circuits
RESET
Comp2
Comp4
VMON12
12 Analog Inputs
IN1
IN2
VDD
IN3
IN4
VMON1
VMON2
VMON3
VMON4
VMON5
VMON6
VMON7
VMON8
VMON9
VMON10
VMON11
CLK
Comp3
Comp1
Comp6
Comp8
Comp7
Comp5
+2.5V
Circuits
+3.3V
Circuits
+5V
Circuits
OE/EN
Digital
Logic
EN
-48V
Primary +
Gnd
+
-
-48V
Primary +
Gnd
+
-
DC/DC
Supply
-48V
Primary +
Gnd
+
-
DC/DC Supply
or Regulator
POR
DC/DC
Supply
DC/DC
Supply
DC/DC
RG
Supply
VDD VDDINP
0.1uF
CREF
3.3V
3.3V
RG
RG
RG
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Lattice Semiconductor ispPAC-POWR1208 Data Sheet
1-28
Software-Based Design Environment
Design Entry Software
All functions within the ispPAC-POWR1208 are controlled through a Windows-based software development tool
called PAC-Designer. PAC-Designer is an easy-to-use graphical user interface (Figure 1-17) that allows the user to
set up the ispPAC-POWR1208 to perform given functions, such as timed sequences for power supply and monitor
trip points for the voltage monitor inputs. The software tool gives the user control over how the device drives the
outputs and the functional configurations for all I/O pins. User-friendly dialog boxes are provided to set and edit all
of the analog features of the ispPAC-POWR1208. An extension to the schematic screen is the LogiBuilder design
environment (Figure 1-18) that is used to enter and edit control sequences. Again, user-friendly dialog boxes are
provided in this window to help the designer to quickly implement sequences that take advantage of the powerful
built-in PLD. Once the configurations are chosen and the sequence has been described by the utilities, the device
is ready to program. A standard JTAG interface is used to program the E2CMOS memory. PAC-Designer software
supports downloading the device through the PC’s parallel port. The ispPAC-POWR1208 can be reprogrammed
using the software and ispDOWNLOAD® Cable assembly, to adjust for variations in supply timing, sequencing or
scaling of voltage monitor inputs.
Figure 1-17. PAC-Designer Schematic Screen
The user interface (Figure 1-17) provides access to various inter nal function blocks within the ispPAC-POWR1208
device.
Analog Inputs: Accesses the programmable threshold trip-points for the comparators and pin naming conven-
tions.
Digital Inputs: Digital input naming configurations and digital inputs feed into the internal PLD for the sequence
controller.
Sequence Controller: Incorporates a PLD architecture for designing the state machine to control the order and
functions associated with the user-defined power-up sequence/monitor and control.
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Lattice Semiconductor ispPAC-POWR1208 Data Sheet
1-29
FET Drivers: Allows the user to define r amp r ates b y controlling the current driven to the gate of the external FETs.
Maximum voltage levels and pin names are also set using this functional block. The four FET driver outputs
HVOUT1-4 can also be configured as open-drain digital logic outputs.
Logic Outputs: These pins are configured and assigned in the Logic Output Functional Block. The four digital out-
puts are open-drain and require a pull-up resistor.
Internal Clock: The internal clock configuration and clock prescaler values are user-programmable, as well as the
four internal programmable timers used for sequence delay.
User Electronic Signature (UES): Stores 16 bits of ID or board information in non-volatile E2CMOS.
Figure 1-18. PAC-Designer LogiBuilder Screen
Programming of the ispPAC-POWR1208 is accomplished using the Lattice ispDOWNLOAD Cable. This cable con-
nects to the parallel port of a PC and is driven through the PAC-Designer software. The software controls the JTAG
TAP interface and shifts in the JEDEC data bits that set the configuration of all the analog and digital circuitry that
the user has defined during the design process.
Power to the de vice m ust be set at 3.0V to 5.5V during programming, once the prog ramming steps ha v e been com-
pleted, the power supply to the ispPAC-POWR1208 can be set from 2.5V to 5V. Once programmed, the on-chip
non-volatile E2CMOS bits hold the entire design configuration for the digital circuits, analog circuits and trip points
f or comparators etc. Upon powering the device up, the non-volatile E 2CMOS bits control the device configuration. If
design changes need to be made such as adjusting comparator trip points or changes to the digital logic functions,
the device is simply re-programmed using the ispDOWNLOAD Cable.
Design Simulation Capability
Support for functional simulation of the control sequence is provided using the software tools Waveform Editor and
Waveform Viewer. Both applications are spawned from the LogiBuilder environment of PAC-Designer. The simula-
tion engine combines the design file with a stimulus file (edited by the user with Wavefor m Editor) to produce an
output file that can be observed with the Waveform Viewer (Figure 1-19).
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Lattice Semiconductor ispPAC-POWR1208 Data Sheet
1-30
Figure 1-19. PAC-Designer Functional Simulation Screen
In-System Programming
The ispPAC-POWR1208 is an in-system programmable device. This is accomplished by integrating all E2CMOS
configuration memory and control logic on-chip. Programming is performed through a 4-wire, IEEE 1149.1 compli-
ant serial JTAG interface. Once a device is programmed, all configuration infor mation is stored on-chip, in non-vol-
atile E2CMOS memory cells. The specifics of the IEEE 1149.1 serial interface and all ispPAC-POWR1208
instructions are described in the JTAG interface section of this data sheet.
User Electronic Signature
The User Electronic Signature (UES), allows the designer to include identification bits or serial numbers inside the
device, stored in E2CMOS memory. The ispPAC-POWR1208 contains 16 UES bits that can be configured by the
user to store unique data such as ID codes, revision numbers or inventory control codes.
Electronic Security
An Electronic Security Fuse (ESF) bit is provided to pre v ent unauthorized readout of the E 2CMOS bit pattern. Once
programmed, this cell prevents further access to the functional user bits in the device. This cell can only be erased
by reprogramming the device; this way the original configuration cannot be examined or copied once programmed.
Usage of this feature is optional.
Production Programming Support
Once a final configuration is determined, an ASCII format JEDEC file can be created using the PAC-Designer soft-
ware . Devices can then be ordered through the usual supply channels with the user’s specific configuration already
preloaded into the devices. By virtue of its standard interface, compatibility is maintained with existing production
programming equipment, giving customers a wide degree of freedom and flexibility in production planning.
Evaluation Fixture
The ispPAC-POWR1208 Design Kit includes an engineer ing prototype board that can be connected to the parallel
port of a PC using a Lattice ispDOWNLOAD cable. It demonstrates proper layout techniques for the ispPAC-
POWR1208 and can be used in real time to check circuit operation as par t of the design process. LEDs are sup-
plied to debug designs without involving test equipment. Input and output connections as well as a “breadboard”
circuit area are provided to speed deb ugging of the circuit. The board includes an area for prototyping other circuits
Part Number Description
PAC-SYSTEM POWR1208 Complete system kit, evaluation board, ispDOWNLOAD Cable and software
ispPAC-POWR1208-EV Evaluation board only, with components, fully assembled
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Lattice Semiconductor ispPAC-POWR1208 Data Sheet
1-31
and interconnect areas with pads for pins or cables. The user can check out designs on the hardware and make
necessary changes to the design for the function required.
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Lattice Semiconductor ispPAC-POWR1208 Data Sheet
1-32
Package Diagrams
44-Pin TQFP (Dimensions in Millimeters)
0.10 C
BASE METAL
5. THE TOP OF PACKAGE MAY BE SMALLER THAN THE BOTTOM
4. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION.
DATUMS A, B AND D TO BE DETERMINED AT DATUM PLANE H.
ALLOWABLE MOLD PROTRUSION IS 0.254 MM ON D1 AND E1
2. ALL DIMENSIONS ARE IN MILLIMETERS.
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5 - 1982.
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.10 AND 0.25 MM FROM THE LEAD TIP.
7. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE
TO THE LOWEST POINT ON THE PACKAGE BODY.
EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8.
DIMENSIONS.
OF THE PACKAGE BY 0.15 MM.
6. SECTION B-B:
3.
SECTION B-B
b1
c 1
c
0.45
0.40
0.16
0.20
c1 0.09 0.13
c
b1
0.09
0.30
b
e
0.30
0.35
0.15
0.37
0.80 BSC
MAX.
1.60
0.15
1.45
0.75
E 12.00 BSC
0.45L
N
E1
0.60
44
10.00 BSC
D
D1
A2 1.35
12.00 BSC
10.00 BSC
1.40
DETAIL 'A'
A1
A1
A
0.05
-
SYMBOL MIN.
-
-
NOM.
1.00 REF.
0.20 MIN.
B
L
0-7∞
SEATING PLANE
LEAD FINISH
0.20
b
b
A-BC
MD
SIDE VIEW
e
TOP VIEW
8D3
A
3
D
GAUGE PLANE
DH A-B4X 0.20 BOTTOM VIEW
A2
C
A
SEE DETAIL 'A'
H
B
3
E
B
E1
D1
0.25
A-B0.20 C44XD
NOTES:
PIN 1 INDICATOR
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Lattice Semiconductor ispPAC-POWR1208 Data Sheet
1-33
Part Number Description
ispPAC-POWR1208 Ordering Information
Conventional Packaging Industrial
Automotive
Lead-Free Packaging Lead-Free Industrial
Lead-Free Automotive
Part Number Package Pins
ispPAC-POWR1208-01T44I TQFP 44
Part Number Package Pins
ispPAC-POWR1208-01T44E TQFP 44
Part Number Package Pins
ispPAC-POWR1208-01TN44I TQFP 44
Part Number Package Pins
ispPAC-POWR1208-01TN44E TQFP 44
Device Number
ispPAC-POWR1208 - 01XX44X
Operating Temperature Range
I = Industrial (-40°C to +85°C)
E = Automotive (-40°C to +125°C)
Package
T = 44-pin TQFP
TN = Lead-Free 44-pin TQFP
Performance Grade
01 = Standard
Device Family
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Lattice Semiconductor ispPAC-POWR1208 Data Sheet
1-34
Package Options
Revision History
Date Version Change Summary
— — Previous Lattice releases.
September 2003 03.1 Added 125°C Automotive Range -40°C to +125°C to Features bullets.
Added VMON tempco for 125°C 76PPM to Voltage Monitors table.
IsinkHVout f or open dr ain mode 4mA max to Digital Specifications tab le .
Isinkout max added for logic outputs OUT5-8 and comparators COMP1-
8 20mA Max (Digital Specifications table).
Spec added for Isinktotal Total combined sink current from all
OUT,HVOUT,COMP 80mA (Digital Specifications table).
Automotive range added to Part Number Description section.
TN suffix added for lead free packaging, Part Number Description sec-
tion.
Automotive part number added in the Ordering Information section.
January 2004 04.0 Ordering part number added for "Lead Free" packaging, Ordering Infor-
mation section.
August 2004 04.1 Add R/C network to RESET pin in Application Block Diagram to acco-
modate hot-swapping.
Edited note 7 in Pin Descriptions table to support hot-swapping.
OUT5
OUT6
OUT7
OUT8
VMON1
VMON2
VMON3
VMON4
VMON5
VMON6
VMON7
VMON8
VMON9
COMP1
COMP2
COMP4
COMP5
COMP6
COMP7
COMP8
ispPAC-POWR1208
44-pin TQFP
1
44
43
42
41
40
39
38
37
35
34
33
2
3
4
5
6
7
8
9
10
11 12 13 14 15 16 17 18 19 20 21 22
23
24
25
26
27
28
29
30
31
32
36
COMP3
POR
VMON10
VMON11
VMON12
TDI
TDO
TCK
TMS
TRST
CLK
CREF
GND
HVOUT1
HVOUT2
HVOUT3
VDD
IN1
IN2
IN3
IN4
VDDINP
HVOUT4
RESET
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