TMS320C6424 Evaluation Module Technical Reference 2007 DSP Development Systems TMS320C6424 Evaluation Module Technical Reference 509125-0001 Rev. A February 2007 SPECTRUM DIGITAL, INC. 12502 Exchange Drive, Suite 440 Stafford, TX. 77477 Tel: 281.494.4505 Fax: 281.494.5310 sales@spectrumdigital.com www.spectrumdigital.com IMPORTANT NOTICE Spectrum Digital, Inc. reserves the right to make changes to its products or to discontinue any product or service without notice. Customers are advised to obtain the latest version of relevant information to verify that the data being relied on is current before placing orders. Spectrum Digital, Inc. warrants performance of its products and related software to current specifications in accordance with Spectrum Digital's standard warranty. Testing and other quality control techniques are utilized to the extent deemed necessary to support this warranty. Please be aware that the products described herein are not intended for use in life-support appliances, devices, or systems. Spectrum Digital does not warrant nor is Spectrum Digital liable for the product described herein to be used in other than a development environment. Spectrum Digital, Inc. assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does Spectrum Digital warrant or represent any license, either express or implied, is granted under any patent right, copyright, or other intellectual property right of Spectrum Digital, Inc. covering or relating to any combination, machine, or process in which such Digital Signal Processing development products or services might be or are used. WARNING This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures necessary to correct this interference. Copyright (c) 2007 Spectrum Digital, Inc. Contents 1 Introduction to the C6424 Evaluation Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Provides you with a description of the C6424 Evaluation Module, key features, and block diagram. 1.1 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.3 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.5 Configuration Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.6 Power Supply ......................................................... 1-5 1.7 Power Measurement ................................................... 1-5 2 Board Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Describes the operation of the major board components on the C6424 Evaluation Module. 2.1 EMIF Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.1 DDR2 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.2 Flash, NAND Flash, SRAM Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Peripheral Interfaces ................................................. 2-2 2.2.1 VLYNQ Interface .................................................. 2-2 2.2.2 UART Interface .................................................. 2-2 2.3 AIC33 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.4 Ethernet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.5 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.5.1 I/O Expanders ........................................................ 2-5 ........................................................ 2-7 2.5.2 I2C EEPROM 2.6 S/PDIF Analog, and Optical Interfaces .................................... 2-7 2.7 Daughter Card Interface ................................................. 2-8 2.8 C6424 Core CPU Clock ................................................ 2-8 2.9 C6424 Core Voltage Select .............................................. 2-8 3 Physical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Describes the physical layout of the C6424 Evaluation Module and its connectors. 3.1 Board Layout ........................................................ 3.2 Connectors ........................................................ 3.2.1 J10, S/PDIF Out ..................................................... 3.2.2 J16, +5V Input ....................................................... 3.2.3 J20, Mini PCI Interface ................................................ 3.2.4 J501, Embedded Mini USB Emulation Interface ............................ 3.2.5 P3, Ethernet Interface ................................................. 3.2.6 P4, PCI Interface ..................................................... 3.2.7 P8, RS-232 UART .................................................. 3.2.8 P10, Audio Line In Connector ......................................... 3.2.9 P11, Microphone In Connector ......................................... 3.2.10 P12, Headphone Out Connector ..................................... 3.2.11 P13, Audio Line Out Connector ........................................ 3.2.12 P14, S/PDIF Out (Optical) ........................................... 3.2.13 DC_P1, Memory/Video Expansion ..................................... 3.2.14 DC_P2, Peripheral Expansion ........................................ 3.2.15 DC_P3, VLYNQ Connector .......................................... 3.3 Jumpers ............................................................ 3.3.1 JP1 Jumper ......................................................... 3.3.2 JP2 Jumper ......................................................... 3.3.3 JP3 Jumper ......................................................... 3.3.4 JP4 Jumper ........................................................ 3.4 LEDs ................................................................ 3.5 Switches ............................................................. 3.5.1 SW1, Bootload Mode Selections ....................................... 3.5.2 SW2, Bootload Configuration Select .................................... 3.5.3 SW3, EMDATA Select ................................................ 3.5.4 SW4, 4 Position User Readable ........................................ 3.5.5 SW5, Power On Reset Switch .......................................... 3.5.6 SW6, Reset Switch .................................................. 3.5.7 SW7, Slide Switch .................................................. 3.6 Test Points ........................................................ A Schematics .............................................................. Contains the schematics for the C6424 Evaluation Module B Mechanical Information .................................................. Contains the mechanical information about the C6424 Evaluation Module 3-1 3-3 3-4 3-5 3-5 3-6 3-7 3-7 3-8 3-10 3-11 3-11 3-11 3-12 3-12 3-13 3-14 3-15 3-15 3-16 3-16 3-16 3-16 3-17 3-17 3-18 3-19 3-19 3-19 3-19 3-19 3-20 3-21 A-1 B-1 About This Manual This document describes the board level operations of the C6424 Evaluation Module (EVM). The EVM is based on the Texas Instruments TMS320C6424 Processor. The C6424 Evaluation Module is a table top card that allows engineers and software developers to evaluate certain characteristics of the C6424 processor to determine if the processor meets the designers application requirements. Evaluators can create software to execute on board or expand the system in a variety of ways. Notational Conventions This document uses the following conventions. The C6424 Evaluation Module will sometimes be referred to as the C6424 EVM or EVM. Program listings, program examples, and interactive displays are shown in a special italic typeface. Here is a sample program listing. equations !rd = !strobe&rw; Information About Cautions This book may contain cautions. This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software, or hardware, or other equipment. The information in a caution is provided for your protection. Please read each caution carefully. Related Documents, Application Notes and User Guides Information regarding this device can be found at the following Texas Instruments website: http://www.ti.com Table 1: Manual History Revision A History Alpha Release Table 2: Board History Revision A History Alpha Release Chapter 1 Introduction to the C6424 EVM Chapter One provides a description of the C6424 EVM along with the key features and a block diagram of the circuit board. Topic 1.1 1.2 1.3 1.4 1.5 1.6 1.7 Page Key Features Functional Overview Basic Operation Memory Map Configuration Switch Settings Power Supply Power Measurement 1-2 1-3 1-4 1-4 1-5 1-5 1-5 1-1 Spectrum Digital, Inc 1.1 Key Features The C6424 EVM is a PCI based or standalone development platform that enables users to evaluate and develop applications for the TI C64xx processor family. Schematics, list of materials, and application notes are available to ease hardware development and reduce time to market. The EVM comes with a full complement of on board devices that suit a wide variety of application environments. Key features include: * A Texas Instruments C6424 processor operating up to 600 Mhz. * 128 Mbytes of DDR2 DRAM * UART I/O Interface * 16 Mbytes of non-volatile Flash memory, 64 Mbytes NAND Flash, 2 Mbytes SRAM * AIC33 stereo codec * I2C Interface with onboard eeprom and expanders * 10/100 MBS Ethernet Interface * Configurable boot load options * Embedded JTAG emulation interface * 4 user LEDs and 4 position user switch * Single voltage power supply (+5V) * Expansion connectors for daughter card use * VLYNQ Interface * S/PDIF Interface, analog, and optical 1-2 C6424 EVM Technical Reference Spectrum Digital, Inc 1.2 Functional Overview of the C6424 EVM DIP ENET RJ45 RST POR ENET PHY DDR2 MIC IN Embedded JTAG Emulator UARTs DC_P2 DDR2 DC_P1 32 RMII MII AIC33 Codec LINE OUT HP Out JTAG McBSP0 C6424 LINE IN SPI ROM McBSP1 or McASP0 1.8V Supply S/PDIF (optical) 2 I C Bus PCI VLNQ Mini PCI 1.2V Core Supply S/PDIF 3.3V I/O Supply PCI Connector PWR SRAM NAND Flash BM0 BM1 BM2 BM3 FASTB ENDIAN 8/16 1234567 1234 AEM2 AEM1 AEM0 NOR Flash Ext JTAG UART Switches LEDs EMIF RS-232 USB EMU 1 2 3 4 Figure 1-1, Block Diagram C6424 EVM The C6424 on the EVM interfaces to on-board peripherals through integrated device interfaces and a 16-bit wide EMIF bus. The DDR2 memory is connected to its own dedicated 32 bit wide bus. The EMIF bus is jumper selectable to be connected to the Flash, SRAM, NAND, and daughter card expansion connectors which are used for add-on boards. An on-board AIC33 codec allows the DSP to transmit and receive analog audio signals. The I2C bus is used for the codec control interface, while the McBSP controls the audio stream. Signal interfacing is done through 3.5mm audio jacks that correspond to microphone input, line input, line output, and headphone outputs. The EVM includes 4 user LEDs, and 4 position user DIP switch which can be used to provide the user with interactive feedback. These interfaces are implemented via I2C expanders. VLYNQ, and ethernet MAC interfaces are integrated peripherals on the C6424 processor exploiting its system on a chip architecture. VLYNQ is available when the PCI is not used. An included 5V external power supply is used to power the board. On-board switching voltage regulators provide the +1.2V CPU core voltage and +3.3V for peripherals and +1.8V DDR2 memory. The board is held in reset until these supplies are within operating specifications. Code Composer communicates with the EVM through an embedded emulator or via the 14 pin external JTAG connector. 1-3 Spectrum Digital, Inc 1.3 Basic Operation The EVM is designed to work with TI's Code Composer Studio development. Code Composer communicates with the board through the embedded emulator or an external JTAG emulator. To start, follow the instructions in the Quick Start Guide to install Code Composer. This process will install all of the necessary development tools, documentation and drivers. Detailed information about the EVM including examples and reference material is available on the EVM's CD-ROM. 1.4 Memory Map The C64xx family of processors have a large byte addressable address space, some limitations to byte addressing are determined by peripheral interconnection to the C6424 device. Program code and data can be placed anywhere in the unified address space. Addresses are multiple sizes depending on hardware implementation. Refer to the appropriate device data sheets for more details. The memory map shows the address space of a C6424 processor on the left with specific details of how each region is used on the right. By default, the internal memory sits at the beginning of the address space. Portions of memory can be remapped in software as L2 cache rather than fixed RAM. The part incorporates a dual EMIF interface. One dedicated EMIF directly interfaces to the DDR2 memory. The Flash, NAND Flash, or SRAM are mapped into CS2 space and selectable via JP2. When CS2 is used for daughter card interfacing JP2 must be set appropriately. Address 0x10800000 C6424 EVM Cache/RAM 0x42000000 CS2 0x44000000 CS3 0x46000000 CS4 0x48000000 CS5 0x4C000000 VLNQ 0x80000000 DDR Figure 1-2, Memory Map, C6424 EVM 1-4 C6424 EVM Technical Reference Spectrum Digital, Inc 1.5 Configuration Switch Settings The EVM has a two configuration switches that allow users to control the operational state of the processor when it is released from reset. The configuration switches are labeled SW1 and SW2 on the EVM board. Switch SW1 configures the boot mode that will be used when the DSP starts executing. By default the switches are configured to EMIF boot (out of 16-bit Flash). Refer to section 3.5.1 for the boot load options using switch SW1. 1.6 Power Supply The EVM operates from a single +5V external power supply connected to the main power input (J16), a 2.5 MM. barrel-type plug. Internally, the +5V input is converted into +1.2V, +1.8V and +3.3V using Texas Instruments swift voltage regulators. The +1.2V supply is used for the DSP core while the +3.3V supply is used for the DSP's I/O buffers and other chips on the board. The +1.8 volt supply is used for C6424 DDR2 interface, and DDR2 memory. There are three power test points on the EVM; TP23, TP34, and TP38. These test points provide a convenient mechanism to check the EVM's multiple power supplies. The table below shows the voltages for each test point and what the supply is used for. Table 1: Power Test Points Test Point Voltage Voltage Use TP23 +1.2 V C6424 Core TP34 +3.3V DSP I/O and logic TP38 +1.8 V DDR2 Memory, DSP I/O, and logic 1.7 Power Measurement The EVM supports power test points to allow measurement of the various power rails on the C6424 device. Series resistors are used in the device's power domains thereby measuring the voltage across these resistors. The current can be calculated via V = I * R. Refer to the test point section in chapter 3 for detailed information on measuring current on the C6424 device. 1-5 Spectrum Digital, Inc 1-6 C6424 EVM Technical Reference Chapter 2 Board Components This chapter describes the operation of the major board components on the C6424 EVM. Topic 2.1 2.1.1 2.1.2 2.2 2.2.1 2.2.2 2.3 2.4 2.5 2.5.1 2.5.2 2.6 2.7 2.8 2.9 Page EMIF Interfaces DDR2 Memory Interface Flash, NAND Flash, SRAM Memory Interface Peripheral Interfaces VLYNQ Interface UART Interface AIC33 Interface Ethernet Interface I2C Interface I/O Expanders I2C EEPROM S/PDIF Analog, and Optical Interfaces Daughter Card Interface C6424 Core CPU Clock C6424 Core Voltage Select 2-2 2-2 2-2 2-2 2-2 2-2 2-3 2-4 2-4 2-5 2-7 2-7 2-8 2-8 2-8 2-1 Spectrum Digital, Inc 2.1 EMIF Interfaces A separate 16 bit EMIF with multiple chip selects divide up the address space and allow for asynchronous accesses on the EVM. On board the CS2 is used for Flash, NAND Flash, or SRAM. 2.1.1 DDR2 Memory Interface The C6424 device incorporates a dedicated 32 bit wide DDR2 memory bus. The EVM uses two 512 megabit 16 bit wide memories on this bus, for a total of 128 megabytes of memory for program, data, and video storage. The internal DDR controller uses a PLL to control the DDR memory timing. The interface supports rates up to 166 Mhz., and is clocked on differential edges for optimal performance. Memory refresh for DDR2 is handled automatically by the C6424 internal DDR controller. 2.1.2 Flash, NAND Flash, SRAM Memory Interface The C6424 has 16 megabytes of NOR Flash, or 64 megabytes of NAND Flash, or 2 megabyte of SRAM memory mapped into the CS2 space. This NOR Flash memory, and NAND Flash memory are used primarily for boot loading. SRAM is used for debugging application code. The CS2 space is configured as 16 bits wide on the C6424 EVM for NOR Flash, SRAM. The NAND flash is always configured as an 8 bit device. 2.2 Peripheral Interfaces The C6424 has several peripheral interfaces which allow the user to interface to external devices. These interfaces are outlined in the following sections. 2.2.1 VLYNQ Interface The C6424 brings its internal VLYNQ interface out to a mini PCI connector J20 and small 20 pin connector DC_P3. The VLYNQ interface is multiplexed on the PCI/EM bus and this bus must be reconfigured after boot up to support VLYNQ. A multiplexer is used to minimize board layout stubs and allow as direct as possible interface for the VLYNQ signals. VLYNQ is not operational if the board is used in a PCI slot. 2.2.2 UART Interface The internal UART0 on the C6424 device is driven to connector P8. The UART's interface is routed to a Texas Instruments MAX3221 RS-232 line driver prior to being brought out to a male DB-9 connector, P8. The on board UART signals can be disabled by pulling the RS232_ENABLEn signal high via the daughter card connectors. 2-2 C6424 EVM Technical Reference Spectrum Digital, Inc 2.3 AIC33 Interface The EVM uses a Texas Instruments TLV320AIC33 stereo codec for input and output of audio signals. The codec samples analog signals on the microphone or line inputs and converts them into digital data so it can be processed by the DSP. When the DSP is finished with the data it uses the codec to convert the samples back into analog signals on the line output so the user can hear the output. The codec communicates using two serial channels, one to control the codec's internal configuration registers and one to send and receive digital audio samples. The I2C bus is used as the unidirectional control channel. The control channel is generally only used when configuring the codec, it is typically idle when audio data is being transmitted, The default configuration is to use the McBSP is used as the bi-directional data channel. However, optionally the McASP can be used to drive the data channel. Data channel selection is controller via an on board I2C expander. All audio data flows through the data channel. Many data formats are supported based on the three variables of sample width, clock signal source and serial data format. The EVM examples generally use a 16-bit sample width with the codec in master mode so it generates the frame sync and bit clocks at the correct sample rate without effort on the DSP side. The codec has a fixed clock from a 12 Mhz. source. The internal sample rate generate subdivides the 12 MHz clock to generate common frequencies such as 48KHz and 8KHz. The sample rate is set by a codec register. The figure below shows the codec interface on the C6424 EVM. AIC33 Codec MIC IN I2C Control SCL SDA I2C Format SCL SDA LINE IN Control Registers Analog Digital LINE OUT McASP or McBSP AXR[0] AXR[1] ACLKR ACLKX AFSR AFSX DX DR CLKR CLKX FSR FSX I2S Format DOUT DIN BCLK WCLK MIC IN ADC LINE IN DAC LINE OUT HP OUT HP OUT Figure 2-2, C6424 EVM CODEC INTERFACE 2-3 Spectrum Digital, Inc 2.4 Ethernet Interface The C6424 integrates an ethernet MAC on chip. The EVM supports RMII and MII protocols. The mode of operation is switch selectable via SW3. This interface is routed to the PHY via CBT switches. The EVM uses an Micrel KS8001L PHY. The 10/100 Mbit interface is isolated and brought out to a RJ-45 standard ethernet connector, P3. The PHY directly interfaces to the C6424. The ethernet address is stored in the I2C serial ROM during manufacturing. The RJ-45 has 2 LEDs integrated into its connector. The LEDs are green and yellow and indicate the status of the ethernet link. The green LED, when on, indicates link and when blinking indicates link activity. The yellow LED, when illuminated, indicates full duplex mode. 2.5 I2C Interface The I2C bus on the C6424 is ideal for interfacing to the control registers of many devices. On the C6424 EVM the I2C bus is used to configure the stereo Codec, I/O expanders. An I2C ROM is also interfaced via the serial bus. The format of the bus is shown in the figure below. Start Slave Address W ACK Sub Address ACK-S Data ACK-S Stop Write Sequence Start Slave Address R Data STOP Read Sequence Figure 2-4, I2C Bus Format The addresses of the on board peripherals are shown in the table below. Table 1: I2C Memory Map 2-4 Device Address R/W Device Function PCF 8574A 0x38 R/W U10 User Input PCF 8574A 0x39 R/W U11 User LEDs PCF 8574A 0x3A R/W U13 PLL, User I/O PCF8574A 0x3B R/W U64 User I/O TLV320AIC33 0x1B R/W U43 CODEC 24WC256 0x50 R/W U25 I2C EEPROM C6424 EVM Technical Reference Spectrum Digital, Inc 2.5.1 I/O Expanders The C6424 EVM uses four I2C expanders to handle various bit I/O functions. Each of these is an 8 bit I/O expander, a PCF8574A. At Power Up Reset the expanders are initialized to 0xFF, all ones. The functions for each of the I/O expanders are shown in the tables below. Table 2: U10 I/O Expander Pin Number Function Description P0 Jumper JP1 Read only user jumper P1 SW7 Slide Switch Read only slide switch P2 Reserved None P3 Reserved None P4 SW4-1 Read only user switch P5 SW4-2 Read only user switch P6 SW4-3 Read only user switch P7 SW4-4 Read only user switch Table 3: U11 I/O Expander Pin Number Function Description P0 User LED DS1 0=Turns LED on, 1=Turns LED off P1 User LED DS2 0=Turns LED on, 1=Turns LED off P2 User LED DS3 0=Turns LED on, 1=Turns LED off P3 User LED DS4 0=Turns LED on, 1=Turns LED off P4 VLYNQ Reset 0=Removes Reset, 1=Applies Reset P5 Reserved None P6 User I/O DC_P2 To daughter card, DC_P2 Pin 81 P7 User I/O DC_P2 To daughter card, DC_P2 Pin 82 2-5 Spectrum Digital, Inc Table 4: U13 I/O Expander Pin Number Function Description P0 User I/O Daughter Card, DC_P2 Pin 87 P1 User I/O Daughter Card, DC_P2 Pin 88 P2 User I/O Daughter Card, DC_P2 Pin 85 P3 User I/O Daughter Card, DC_P2 Pin 84 P4 Reserved P5 Reserved P6 Reserved P7 Reserved Table 5: U64 I/O Expander Pin Number Function Description P0 McBSP_Enable to AIC23 * 1=Enable, 0=Disable P1 McASP_Enable to AIC23 * 0=Enable, 1=Disable P2 SPDIF Enable * 0=Enable, 1=Disable P3 Reserved None P4 Reserved None P5 Reserved None P6 Reserved None P7 Core Voltage Select 0 = 1.05 Volt, 1 = 1.2 Volt * only one should be enabled at a time 2-6 C6424 EVM Technical Reference Spectrum Digital, Inc 2.5.2 I2C EEPROM The C6424 EVM incorporates an I2C eeprom that can be used for booting or general purpose storage. This eeprom is also used to store the ethernet MAC address and the board's revision. The MAC address is also labeled on the board. Care should be taken not to erase these items when user information is stored in the eeprom. Spectrum Digital uses addresses 0x7F00 to 0x7FFF for manufacturing information. This information is shown in the table below. Table 6: C6424 MAC Addresses Address Contents 0x7F00 EMAC Address 0 (most significant) 0x7F01 EMAC Address 1 0x7F02 EMAC Address 2 0x7F03 EMAC Address 3 0x7F04 EMAC Address 4 0x7F05 EMAC Address 5 0x7F06 Reserved 0x7F07 Board Revision 2.6 S/PDIF Analog, and Optical Interfaces The McBSP's FSR pin on the C6424 can be configured to operate as a S/PDIF transmitter. The C6424 EVM supports both analog and optical interfaces. The analog S/PDIF output pin is routed to a driver and filter circuit before being output on J10. I2C Expander U64 output P2 is used to enable the S/PDIF interface. When S/PDIF is selected on the expander (P2=0), the McASP enable should be disabled and the McBSP enable should be disabled.Another driver is used to interface the optical transmitter P14. When the S/PDIF interface is enabled the TLV320AIC33 codec is disabled, the WCLK should be disabled prior to enabling the S/PDIF output. The McBSP interface can be disabled for daughter card use by pulling the AIC_ENABLEn signal high from the daughter card connector. 2-7 Spectrum Digital, Inc 2.7 Daughter Card Interfaces The EVM provides expansion connectors that can be used to accept plug-in daughter cards. The daughter card allows users to build on their EVM platform to extend its capabilities and provide customer and application specific I/O. The expansion connectors are for all major interfaces including memory, peripherals, and video expansion. The pin outs for this interface are documented in Section 3. The connectors provide access to the DSP's EMIF signals to interface with memories and memory mapped devices. The video capture port is brought out to the daughter card interface. Several signals are used to disable the on board video peripherals so that they can be used by the expansion connector. The table below indicates the operation of these signals. Table 7: Daughter Card Interface Signal Function AIC33_ENABLEn Disconnects CPU from on board codec EMADD_ENABLEn Disables upper on board EMIF address lines MEM_EMD7-0_ENABLEn Disables CPU from on board data bus D0-D7 MEM_EMD15-8_ENABLEn Disables CPU from on board data bus D15-D8 ENET_ENABLEn Disconnects CPU from on board ethernet PHY RS232_ENABLEn Disconnects CPU from on board UART Other than the buffering, most daughter card signals are not modified on the board. 2.8 C6424 Core CPU Clock The C6424 EVM uses a 27 Megahertz crystal to generate the input clock. The C6424 has an internal PLL which can multiply the input clock to generate the internal clock. The PLL multiplier is set via software on the C6424 device. 2.9 C6424 Core Voltage Select The C6424 EVM has the ability to adjust the core voltage between 1.2 volts and 1.05 volts. an I/O expander is used to control this I2C feature. 2-8 C6424 EVM Technical Reference Chapter 3 Physical Description This chapter describes the physical layout of the C6424 EVM and its interfaces. Topic 3.1 3.2 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.2.7 3.2.8 3.2.9 3.2.10 3.2.11 3.2.12 3.2.13 3.2.14 3.2.15 Page Board Layout Connectors J10, S/PDIF Out J16, +5V Input J20, Mini PCI Interface J501, Embedded Mini USB Emulation Interface P3, Ethernet Interface P4, PCI Connector P8, RS-232 UART P10, Audio Line In Connector P11, Microphone In Connector P12, Headphone Out Connector P13, Audio Line Out Connector P14, S/PDIF Out (Optical) DC_P1, Memory/Video Expansion DC_P2, Peripheral Expansion DC_P3, VLYNQ Connector 3-3 3-4 3-5 3-5 3-6 3-7 3-7 3-8 3-10 3-11 3-11 3-11 3-12 3-12 3-13 3-14 3-15 3-1 Spectrum Digital, Inc Topic 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.4 3.5 3.5.1 3.5.2 3.5.3 3.5.4 3.5.5 3.5.6 3.5.7 3.6 3-2 Jumpers JP1 Jumper JP2 Jumper JP3 Jumper JP4 Jumper LEDs Switches SW1, Bootload Mode Selections SW2, Bootload Configuration Select SW3, EMIF Data Select SW4, 4 Position User Readable SW5, Power On Reset Switch SW6, Reset Switch SW7, Slide Switch Test Points Page 3-15 3-16 3-16 3-16 3-16 3-17 3-17 3-18 3-19 3-19 3-19 3-19 3-19 3-20 3-21 C6424 EVM Technical Reference Spectrum Digital, Inc 3.1 Board Layout The C6424 EVM is a 8.75 x 4.5 inch (210 x 115 mm.) ten (10) layer printed circuit board which is powered by an external +5 volt only power supply. Figure 3-1 shows the layout of the C6424 EVM. P10 J10 P11 P14 P12 P13 J16 DS5 P8 DC_P3 DS501 J20 J501 DS501 J6 P3 SW3 SW7 DC_P2 JP4 SW5 SW6 DC_P1 JP3 JP2 P4 JP1 SW1 SW4 DS1-DS4 SW2 Figure 3-1, C6424 EVM, Interfaces Top Side 3-3 Spectrum Digital, Inc 3.2 Connectors The EVM has twenty three (23) connectors providing interfaces to various peripherals. These connectors are described in the following sections. Table 1: Connectors Connector Size Function J6 14 External Emulation Header J10 RCA S/PDIF Out J16 2.5 mm +5V In J20 2 x 62 Mini PCI Interface J501 Mini USB Embedded USB Emulation Interface P3 RJ-45 Ethernet P4 PCI PCI P8 9 Pin D-sub RS-232 UART P10 3.5 mm Stereo Line In P11 3.5 mm Microphone In P12 3.5 mm Headphone Out P13 3.5 mm Stereo Line Out P14 Optical S/PDIF Out DC_P1 2x50 Expansion DC_P2 2x45 Expansion DC_P3 2x10 Expansion * Not populated 3-4 C6424 EVM Technical Reference Spectrum Digital, Inc 3.2.1 J10, S/PDIF Out J10 is an RCA jack used as an analog output from the McBSP FSR signal on the DSP. This connector brings out the S/PDIF signal. Do NOT plug into this connector with the power on. The figure below shows this connector as viewed from the card edge. Pin 2, Shield (ground) Pin 1, Signal Output Figure 3-2, J10, S/PDIF Out, RCA Jack Table 2: J10, S/PDIF, RCA Jack Pin # Signal Name 1 S/PDIF Analog output 2 GND 3.2.2 J16, +5V Input Connector J16 is the input power connector. This connector bring in +5 volts to the EVM. This is a 2.5 mm. jack. The figure below shows this connector as viewed from the card edge. +5V J14 Ground PC Board Front View Figure 3-3, J16, +5 Volt Input Connector 3-5 Spectrum Digital, Inc 3.2.3 J20, Mini PCI Interface Connector J20 provides a mini-PCI on the C6424 EVM. Do NOT plug into this connector with the power on. The table below shows the signals on this connector. Table 3: J16, VLYNQ Card Interface Pin # 2,3,4,5,6,7,8,10,11, 12,13,15,17,18,29, 30,38,39,47,49,51, 53,55,57,71,73,75, 77,80,82,84,86,93, 98,100,104,105, 106,107,108,109, 113,115,116,117, 118,120,122,123, 124 9,14,20,23,25,27 32,33,34,35,37,41, 42,44,45,46,48,50, 52,54,56,58,60,62, 64,66,68,69,72,74, 76,78,79,81,83,85, 87,90,91,92,94,95, 96,99,101,102, 110,114,119 3-6 Signal NC GND 111 VCC_1.8V 1,19,28,31,40,63, 70,88,89 VCC_3.3V 97,103 VCC_5V 16 VLYNQ_CLK 21 VLYNQ_RXD0 22 VLYNQ_RXD1 24 VLYNQ_SCRUN 26 VLYNQ_RESET 59 VLYNQ_RXD2 61 VLYNQ_RXD3 36 VLYNQ_TXD0 65 VLYNQ_TXD2 67 VLYNQ_TXD3 43 VLYNQ_TXD1 C6424 EVM Technical Reference Spectrum Digital, Inc 3.2.4 J501, Embedded Mini USB Emulation Interface This connector allows the user to run software development tools and emulation without an external emulator. The signals on this connector are shown in the table below. Table 4: J501, Embedded Mini USB Emulation Interface Pin # Signal Name 1 VBUS 2 D- 3 D+ 4 ID (not used) 5 Ground 3.2.5 P3, Ethernet Interface The P3 connector is used to provide an 10/100 Mbps Ethernet interface. This is a standard RJ-45 connector. The pinout for the P3 connector is shown in the table below. Table 5: P3, Ethernet Interface Pin # Signal Pin # Signal 1 LXT_TDP 2 LXT_TDM 3 LXT_RDP 4 LXT_TDCT 5 NC 6 LXT_RDM 7 NC 8 GND Two LEDs are embedded into the connector to report link status. Table 6: Ethernet LEDs LED # Color LED1 Green LED2 Yellow 3-7 Spectrum Digital, Inc 3.2.6 P4, PCI Connector The P4 connector is a card edge PCI interface. This connector has an "A" and "B" side. Because of the card seating notches the pin numbers are not contiguous. The "B" side is the top component side. The I/O direction field is referenced from the PCI slot. Table 7: P4, PCI Connector, "A" Side 3-8 Pin Signal 1 TRST- 3 TMS 5 +5 Volts 7 INTC- I/O O Description Pin Signal I/O Description Not Used 2 +12 Volts Not Used 4 TDI I/O Tied to TDO +5 Volts Power Interrupt Out 6 INTA- O 8 +5 Volts +5 Volts Power Not Used Interrupt Out 9 Rsvd.0 Not Used 10 +V I/O Not Used 11 Rsvd.1 Not Used 12 Key.1 Key 13 Key.2 Key 14 +3.3 Vaux 15 RST- I PCI_Resetn 16 +V I/O 17 GNT- O Grant- 19 PME- 21 +3.3 Volts 23 AD26 I/O/Z 25 AD24 I/O/Z 27 +3.3 Volts 29 AD20 31 AD18 33 35 Not Used O Not Used 18 GND 20 AD30 I/O/Z Address/Data 30 Ground Not Used 22 AD28 I/O/Z Address/Data 28 Address/Data 26 24 GND Address/Data 24 26 IDSEL I Initialization Device Select Not Used 28 AD22 I/O/Z Address/Data 22 I/O/Z Address/Data 20 30 GND I/O/Z Address/Data 18 32 AD16 I/O/Z Address/Data 16 +3.3 Volts Not Used 34 FRAME- I Frame GND Ground 36 TRDY- I/O/Z Target Ready Stop Direction Ground 37 GND Ground 38 STOP- I/O/Z 39 +3.3 Volts Not Used 40 SDONE O 41 SBO- 42 GND 43 PAR 44 AD15 I/O/Z Address/Data 15 45 +3.3 Volts I/O/Z Address/Data 13 47 Done Ground I/O/Z Parity Not Used 46 AD13 AD11 I/O/Z Address/Data 11 48 GND 49 AD9 I/O/Z Address/Data 9 50 Key.3 Key 51 Key.4 Key 52 C/BE0 Command/Byte Enable0 53 +3.3 Volts Not Used 54 AD6 55 AD4 I/O/Z Address/Data 4 56 GND 57 AD2 I/O/Z Address/Data 2 58 AD0 59 +V I/O Not Used 60 REQ64- Not Used 61 +5 Volts +5 Volts Power 62 +5 Volts +5 Volts Power Ground I/O/Z Address/Data 6 I/O/Z Address/Data 0 Ground C6424 EVM Technical Reference Spectrum Digital, Inc The signals on the "B" side of the connector are shown in the table below. Table 8: P4, PCI Connector, "B" Side Pin Signal 1 3 I/O Description Pin Signal I/O -12 Volts Not Used GND Ground 5 +5 Volts 7 INTB- 9 PRSNT1- 11 PRSNT2- 13 Key.6 15 GND 17 GND 19 +V I/O 21 AD29 23 AD27 25 +3.3 Volts 27 Description 2 TCK I Not Used 4 TDO I Tied to TDO +5 Volt Power 6 +5 Volts I +5 Volt Power Interrupt OUT 8 INTD- O Power Requirement 10 Rsvd.2 O Power Requirement 12 Key.5 Key 14 Rsvd.3 Ground 16 CLK Ground 18 REQ- Not Used 20 AD31 I/O/Z Address/Data 29 22 GND I/O/Z Address/Data 27 24 Not Used AD23 I/O/Z Address/Data 23 29 AD21 I/O/Z Address/Data 21 30 AD19 I/O/Z Address/Data 19 31 +3.3 Volts Not Used 32 AD17 I/O/Z Address/Data 17 33 C/BE2- I/O/Z Command/Byte Enable 2 34 GND Ground 35 IRDY- I Initiator Ready 36 +3.3 Volts Not Used 37 DEVSEL- I/O/Z Device Select 38 GND 39 LOCK- I Resource Locked 40 PERR- Interrupt Out Key System Clock I/O/Z Address/Data 31 AD25 I/O/Z Address/Data 25 26 C/BE3 I/O/Z Command/Byte Enable 3 28 GND Ground Ground Ground I/O/Z Parity Error 41 +3.3 Volts Not Used 42 SERR- O System Error 43 +3.3 Volts Not Used 44 C/BE1- I/O/Z Command/Byte Enable 1 45 AD14 I/O/Z Address/Data 14 46 GND 47 AD12 I/O/Z Address/Data 12 48 AD10 I/O/Z Address/Data 10 49 M66EN O 66 Mhz Enable 50 Key.7 51 Key.8 Key 52 AD8 I/O/Z Address/Data 8 53 AD7 I/O/Z Address/Data 7 54 +3.3 Volts 55 AD5 I/O/Z Address/Data 5 56 AD3 I/O/Z Address/Data 3 I/O/Z Address/Data 1 Ground Key Not Used 57 GND Ground 58 AD1 59 +V I/O Not Used 60 ACK64- Not Used 61 +5 Volts +5 Volt Power 62 +5 Volts +5 Volt Power 3-9 Spectrum Digital, Inc 3.2.7 P8, RS-232 UART Connector The C6424 EVM has an RS-232 connector which brings out the SCI transmit and receive signals to be used as UART. This UART uses the MAX3221 RS-232 line driver and is routed to a male 9 pin D-connector, P8. The pin positions for the P8 connector as viewed from the edge of the printed circuit board are shown below. 4 5 9 3 8 2 7 1 6 Figure 3-4, P8, DB9 Male Connector The pin numbers and their corresponding signals are shown in the table below. This corresponds to a standard dual row to DB-9 connector interface used on personal computers. Table 9: P8, RS-232 UART Pinout 3-10 Pin # Signal Name 1 No Connect 2 RXD 3 TXD 4 No Connect 5 GND 6 No Connect 7 No Connect 8 No Connect 9 No Connect C6424 EVM Technical Reference Spectrum Digital, Inc 3.2.8 P10, Audio Line In Connector The audio line in is a stereo input. The input connector is a 3.5 mm stereo jack. The signals on the mating plug are shown in the figure below. Ground Right Line In Left Line In Figure 3-5, Audio Line In Stereo Jack 3.2.9 P11, Microphone Connector The input is a 3.5 mm. stereo jack. Both inputs are connected to the microphone so it is monaural. The signals on the plug are shown in the figure below. Ground Microphone In Microphone Bias Figure 3-6, Microphone Stereo Jack 3.2.10 P12, Headphone Connector Connector P12 is a headphone/speaker jack. It can drive standard headphones or a high impedance speaker directly. The standard 3.5 mm jack is shown in the figure below. Ground Right Headphone Left Headphone Figure 3-7, Headphone Jack 3-11 Spectrum Digital, Inc 3.2.11 P13, Audio Line Out Connector The audio line out is a stereo output. The output connector is a 3.5 mm stereo jack. The signals on the mating plug are shown in the figure below. Ground Right Line Out Left Line Out Figure 3-8, Audio Line Out Stereo Jack 3.2.12 P14, S/PDIF Out (Optical) P14 is an optical transmitter connector used as an output from the McBSP FSR signal on the C6424 DSP. This connector brings out an optical S/PDIF signal. Do NOT plug into this connector with the power on. The figure below shows this connector as viewed from the card edge. 3-12 C6424 EVM Technical Reference Spectrum Digital, Inc 3.2.13 DC_P1, Memory/Video ExpansionTable 10: DC_P1, Memory/Video Expansion Pin Signal Pin Signal 1 GROUND Conn 2 GROUND 3 PCLK_GP[54] 4 MEM_D15-8_ENABLE 5 RESERVED 6 GROUND 7 EM_D[12]_GP39] 8 EM_D[11]_GP40] 9 EM_D[13]_GP[38] 10 EM_D[10]_GP[41] 11 EM_D[14]_GP[37] 12 EM_D[9]_GP[42] 13 EM_D[15]_GP[36] 14 EM_D[8]_GP[43] 15 GROUND 16 GROUND 17 RNW_GP[35] 18 EM_A[21]_GP[34] 19 VD_GP[53] 20 HD_GP[52] 21 EM_A[17]_GP[47] 22 EM_A[16]_GP[48] 23 EM_A[18]_GP[46] 24 EM_A[15]_GP[49] 25 EM_A[19]_GP[45] 26 EM_A[14]_GP[50] 27 EM_A[20]_GP[44] 28 EM_A[13]_GP[51] 29 GROUND 30 GROUND 31 VCLK_GP[31] 32 EM_CS4n_GP[32] 33 GROUND 34 GROUND 35 VPBECLK_GP[30] 36 EM_CS5n_GP[33] 37 GROUND 38 GROUND 39 GP[25]_BOOTMODE3 40 GP[26]_FASTBOOT 41 GP[24]_BOOTMODE2 42 GP[27] 43 GP[23]_BOOTMODE1 44 GP[28] 45 GP[22]_BOOTMODE0 46 GP[29] 47 GROUND 48 GROUND 49 EM_D[3]_GP[17] 50 EM_D[4]_GP[18] 51 EM_D[2]_GP[16] 52 EM_D[5]_GP[19] 53 EM_D[1]_GP[15] 54 EM_D[6]_GP[20] 55 EM_D[0]_GP[14] 56 EM_D[7]_GP[21] 57 GROUND 58 GROUND 59 EM_A[3]_GP[11] 60 EM_A[4]_GP[10]_(AEAW2) 61 EM_A[1]_(ALE)_GP[9]_(AEAW1) 62 EMA[2]_(CLE)_GP[8]_(AEAW0) 63 EM_BA[0]_GP[6]_(AEM1) 64 EM_A[0]_GP[7]_(AEM2) 65 EM_BA[1]_GP[6]_(AEM0) 66 EM_CS2n__GP[12] 67 EM_WAIT_(RDY/BSTn) 68 EM_CS3n_GP[13] 69 GROUND 70 GROUND 71 EM_A[5]_GP[96] 72 EM_A[9]_GP[92] EM_A[10]_GP[91] 73 EM_A[6]_GP[95] 74 75 EM_A[7]_GP[94] 76 EM_A[11]_GP[90] 77 EM_A[8]_GP[93] 78 EM_A[12]_GP[89] 79 EM_WEn 80 EM_OEn 81 GROUND 82 GROUND 83 MEM_D7-0_ENABLE 84 CLKOUT0_PWM2_GP[84] 85 EMADD_ENABLE 86 GROUND 87 RESETn 88 GP[4]_PWM1 89 SYS_RESETn 90 I2C_INT_ENABLEn 91 VCC_1V8 92 VCC_1V8 93 GROUND 94 GROUND 95 VCC_3V3 96 VCC_3V3 97 GROUND 98 GROUND 99 VCC_5V 100 VCC_5V Conn 3-13 Spectrum Digital, Inc 3.2.14 DC_P2, Peripheral Expansion Table 11: DC_P2, Peripheral Expansion Pin Signal Pin Signal 1 GROUND 2 GROUND 3 VCC_5V 4 VCC_5V 5 VCC_3V3 6 VCC_3V3 8 GROUND CLKS1_TINPOL_GP[98] 10 CLKS0_TINPOL_GP[97] 7 9 3-14 Conn 11 GP[00] 12 GP[01] 13 GP[02] 14 GP[03] 15 RS232_ENABLEn 16 GROUND 17 URXD0_GP[85] 18 URTS0_PWM0_GP[88] 19 UTXD0_GP[86] 20 UCTS0_GP[87] 21 GROUND 22 GROUND 23 TINP1L_URXD1_GP[56] 24 TOUT1L_UTXD1_GP[55] 25 GROUND 26 CAN_ENABLEn 27 AUDIO_CLK 28 GROUND 29 AXR0[3]_FSR0_GP[102] 30 AXR0[2]_FSX0_GP[103] 31 AFSR0_DR0_GP[100] 32 AXR0[1]_DX0_GP[104] 33 AHCLKR0_CLKR0_GP[101] 34 ACLKR0_CLKX0_GP[99] 35 GROUND 36 GROUND 37 I2C_CLK 38 I2C_DATA 39 AIC33_ENABLEn 40 GROUND 41 AXR0_FSR1_GP[106] 42 AMUTEIN0_FSX1_GP[109] 43 AMUTE0_DR1_GP[110] 44 ACHLKX0_CLKR1_GP[108] 45 ACLKX0_CLKX1_GP[106] 46 AFSX0_DX1_GP[107] 47 GROUND 48 GROUND 49 RESET_OUTn 50 SPARE 51 SPARE 52 HCNTL0_MRXER_GP[76] 53 HDS1n_RXD1_GP[79] 54 HDS2n_RXD0_GP[78] 55 HINTn_RXD3_GP[82] 56 HRDYn_RXD2_GP[80] HD09_COL_GP[67] 57 GROUND 58 59 HHWIL_RXDV_GP[74] 60 GROUND 61 HD10_CRS_GP[68] 62 HRNW_RXCLK_GP[77] 63 GROUND 64 GROUND 65 HCSnMDC_GP[81] 66 HASn_MDIO_GP[83] 67 GROUND 68 GROUND 69 HD11_TXD3_GP[69] 70 HD12_TXD2_GP[70] 71 HD13_TXD1_GP[71] 72 HD14_TXD0_GP[72] 73 HCNTL1_TXEN_GP[75] 74 ENET_ENABLEn 75 GROUND 76 GROUND 77 SPARE 78 HD15_TXCLK_GP[73] 79 GROUND 80 GROUND 81 USER_I2C_IO.A0P6 82 USER_I2C_IO.A0P7 83 SPARE 84 SPARE 85 USER_I2C_IO.A1P2 86 USER_I2C_IO.A1P3 87 USER_I2C_IO.A1P0 88 USER_I2C_IO.A1P1 89 GROUND 90 GROUND Conn C6424 EVM Technical Reference Spectrum Digital, Inc 3.2.15 DC_P3, VLYNQ Connector The DC_P3 connector allows the user to connect the VLYNQ interface to other logic. The pinout for the DC_P3 connector is shown in the table below. Table 12: DC_P3, VLYNQ Header Pin # Signal 1 Conn Pin # Signal HD00_VLYNQ_SCRUN_GP[58] 2 VLYNQ_CLOCK_GP[57] 3 GROUND 4 GROUND 5 HD01_VLYNQ_RXD0_GP[59] 6 HD05_VLYNQ_TXD0_GP[63] 7 HD02_VLYNQ_RXD1_GP[60] 8 HD06_VLYNQ_TXD1_GP[64] 9 GROUND 10 GROUND 11 VCC_3V3 12 DC_P3_VLYNQ_RESETn 13 HD03_VLYNQ_RXD2_GP[61] 14 HD07_VLYNQ_TXD2_GP[65] 15 HD04_VLYNQ_RXD3_GP[62] 16 HD08_VLYNQ_TXD3_GP[66] 17 GROUND 18 GROUND 19 VCC_5V 20 VCC_5V Conn 3.3 Jumpers The C6424 EVM has four (4) jumpers which are used to make certain logic or feature determinations on the board. The function of each jumper is described in the table below. Table 13: Jumpers Jumper # Function Size JP1 User Jumper 1x2 JP2 CS2 Select 2x4 JP3 * Reset 1x2 JP4 * Power Up Reset 1x2 * Not populated 3-15 Spectrum Digital, Inc 3.3.1 JP1 Jumper Jumper JP1 is a read only user accessible input. It can be read by the I2C expander U10, bit 0. When the jumper is in the 1-2 position a logic "1" is read. When the jumper is in the 2-3 position a logic "0" is read. 3.3.2 JP2 Jumper 2 1 Jumper JP2 is a jumper bank used to select the routing of the CS2 signal. It can be routed to Flash ROM, SRAM, NAND Flash, and daughter card connector. Only one of these 1-2 selections should be made. The positions are shown in the figure below. CS2-SEL FLASH SRAM NAND DC JP2 Figure 3-9, JP2 Jumper 3.3.3 JP3 Jumper Jumper JP3 is a jumper used to allow external switches to interface to the C6424 power up reset signal. 3.3.3 JP4 Jumper Jumper JP4 is a jumper used to allow external switches to interface to the C6424 reset signal. 3-16 C6424 EVM Technical Reference Spectrum Digital, Inc 3.4 LEDs The C6424 EVM has eight (8) LEDs. Four of these LEDs (DS1-4) are under user control and addressed over the I2C bus. LED DS5 indicates the presence of +5 volts on the board. The remaining LEDs, DS501 and DS502 indicate embedded USB status. DS502 is on when embedded USB emulation is selected and off when the external JTAG emulator is plugged into connector J6. DS501 blinks as packets are sent to and from the embedded USB emulator. The LED functions are summarized in the table below. Table 14: LEDs LED # Use Color DS1 User Defined Green DS2 User Defined Green DS3 User Defined Green DS4 User Defined Green DS5 +5V present Red DS501 Embedded Emulation Status Green DS502 Embedded/external EMU Green 3.5 Switches The C6424 EVM has seven (7) switches. These switches are used to create certain actions on the board or to select certain functions on the board. The switch functions are summarized in the table below. Table 15: Switches LED # Function SW1 Bootload Mode Select SW2 C6424 Muxing Configuration SW3 Ethernet Phy Mode Select SW4 4 Position User Readable SW5 Power On Reset SW6 Reset SW7 Slide Switch 3-17 Spectrum Digital, Inc 3.5.1 SW1, Bootload Mode Select Switch SW1 is an 8 position switch used to select the source of the bootload. Seven (7) of the eight (8) positions are used. The selections are shown in the tables below. Table 16: SW1, Bootload Mode Select SW1[4:1] SW1[5] Auto Detected Boot Description 0000 x x 0001 1* 0 HPI Boot C6424 is slave 0x0010 0000 0001 1* 1 PCI Boot without autoinitialization C6424 is slave 0x0010 0000 0010 1* 0 PCI Boot with autoinitialization C6424 is slave 0x0010 0000 0010 1* 1 HPI Boot C6424 is slave 0x0010 0000 0100 0 x EMIFA ROM Direct Boot C6424 is master 0x4200 0000 0100 1 x EMIFA ROM Fast Boot C6424 is master 0x0010 0000 0101 x x I2C Boot C6424 is master 0x0010 0000 0110 1* x SPI Boot (McBSP peripheral) C6424 is master 0x0010 0000 Emulation Boot In this mode, FASTBOOT setting is don't care (not used by bootloader code) Notes DSPBOOTADDR default C6424 is master 0x0010 0000 0111 1* x NAND Flash C6424 is master 0x0010 0000 1000 x x UART C6424 is master 0x0010 0000 1011 x x EMAC Boot through secondary bootloader C6424 is slave 0x0010 0000 x = don't care, * these boot modes must be accompanied with FASTBOOT = 1. Position 6 of switch SW1 is used to select the endianess mode of the memory. The selections are shown in the table below. Table 17: SW1, Position 6, Endianess Select Position Description Position Endianess Select 0 Big Endian Endianess Select 1 Little Endian Endianess Position 7 of switch SW1 is used to select the width of the memory. The selections are shown in the table below. Table 18: SW1, Position 7, Memory Width Select 3-18 Position Description Position Memory Width Memory Width Select 0 8 Bits Memory Width Select 1 16 Bits C6424 EVM Technical Reference Spectrum Digital, Inc 3.5.2 SW2, Bootload Configuration Select Switch SW2 is an 4 position switch used to select the C6424 multiplexing options at reset. Three (3) of the four (4) positions are used. The selection are shown in the table below. Table 19: SW2, Bootload Configuration Select SW2[2:0] AEM2:0 Description 000 No EMIF 010 16 bit EMIF 101 8 bit EMIF - NAND flash 3.5.3 SW3, EMIF Data Select Switch SW3 is used to select between data bus pins for the asynchronous EMIF controller. The functions of this switch are shown in the table below. Table 20: SW3, EMDATA Select Position Function Description 1 RMII/MII Select Selects mode of Ethernet Phy 0=RMII, 1=MII 2 Reserved 3.5.4 SW4, 4 Position User Readable Switch SW4 is a 4 position bank of user readable switches via the I2C expander. The individual switches can be placed in any position and read by the user software from the expander. See the section on I2C expanders for more information. 3.5.5 SW5, Power On Reset Switch Switch SW5 is a momentary switch that asserts power on reset to the C6424 device. 3.5.6 SW6, Reset Switch Switch SW6 is a momentary switch that asserts a reset to the C6424 processor. 3-19 Spectrum Digital, Inc 3.5.7 SW7, Slide Switch Switch SW7 is a 2 position slide switch used by demonstration software. The switch is read via a I2C expander. Refer to the I2C section for more information. 3-20 C6424 EVM Technical Reference Spectrum Digital, Inc 3.6 Test Points The EVM has 42 test points. All test points appear on the top of the board. The following figure identifies the position of each test point. the next table list each test point and the signal appearing on that test point. TP36 TP18 TP31 TP17 TP27 TP15 TP25 TP16 TP26 TP21 TP28 TP38 TP32 TP29 TP34 TP37 TP33 TP23 TP22 TP12 TP7 TP30 TP47 TP41 TP46 TP1 TP8 TP40 TP64 TP42 TP10 TP43 TP48,TP49 TP4,TP5 TP6,TP2 TP9 Figure 3-10, C6424 EVM, Test Points 3-21 Spectrum Digital, Inc Table 21: C6424 EVM Test Points Test Point # Signal Test Point # TP1 RESETOUTn TP26 GND TP2 RSV4 TP27 GND TP6 RSV5 TP28 GND TP7 GND TP29 GND TP8 GND TP30 GND TP9 GND TP31 VCC_5V TP10 GND TP32 3V3_PWR_OK TP12 Ethernet PHY Interrupt Pin TP36 1V8_PWR_OK TP15 Codec MFP2 Pin TP40 C6424 I2CCLK TP16 Codec MPF3 Pin TP41 C6424 I2CDATA TP17 Codec GPIO1 Pin TP61 TOUT1L TP18 Codec GPIO2 Pin TP64 TINP1L TP21 CORE_PWR_OK TP69 C6424 PWM1 TP25 GND Signal Table 22: Power Pair Test Points Power Pairs Input1 Input2 Power Domain Resistance Between Inputs TP5 DDR_VDDL 0.1 ohms TP22 TP23 DSP_CORE_VDD 0.025 ohms TP33 TP34 VCC_3V3 0.025 ohms TP37 TP38 VCC_1V8 0.025 ohms TP42 TP43 DVD_3V3 0.025 ohms TP47 TP46 DVDD_1V8 0.025 ohms TP48 TP49 PLLPWR18 0.1 ohms TP52 TP53 VDDA_1P1V 0.1 ohms TP4 3-22 C6424 EVM Technical Reference Appendix A Schematics This appendix contains the schematics for the C6424 EVM. A-1 A-2 A B C D A A 1 REV SH 2 A 12 A 11 22 SH 21 SH A 4 A A 3 14 A 24 A 13 A 23 A 5 5 A 6 7 A 16 A A 17 A A 15 27 A 26 A 25 A REVISION STATUS OF SHEETS REV A REV SH REV 5 8 A 18 A 28 A 9 A 19 A 29 A 10 A 20 A 30 A APPLICATION NEXT ASSY - SHEET20 SHEET21 SHEET22 SHEET23 SHEET24 SHEET25 SHEET26 SHEET27 SHEET28 SHEET29 SHEET30 4 RLSE MFG QA ENGR-MGR ENGR CHK R.R.P. R.R.P. C.M.D. R.R.P. R.R.P. T.W.K. R.R.P. - SHEET10 SHEET11 SHEET12 SHEET13 SHEET14 SHEET15 SHEET16 SHEET17 SHEET18 SHEET19 DWN - SHEET01 SHEET02 SHEET03 SHEET04 SHEET05 SHEET06 SHEET07 SHEET08 SHEET09 3 DATE 06/01/2006 DATE 06/01/2006 DATE 06/01/2006 DATE 06/01/2006 DATE 06/01/2006 DATE 06/01/2006 DATE 06/01/2006 3 PCI-Mux PCI-Mux II PCI-Connector mPCI VLYNQ Connector AIC33 SPDIF EMIF DC Connector EMAC/MCBSP DC Conn. VLYNQ/EMIF DC Conn. RESET SUPERVISOR POWER Boot DIP Switches I2C Expanders I2C Expanders 2 DDR2 Memories EMIF Muxing NAND-Flash/SRAM NOR-Flash/EEPROM ENET Muxing ENET RS232 TITLE BLOCK DIAGRAM DSP CLKS/RST/EMU EMULATION DSP Serial/I2C DSP EMIF/PCI/ENET DSP DDR Interface DSP GND-pins DSP Power Pins SCHEMATIC CONTENTS USED ON 4 0x1B 00011011B 2 AIC33 CAT24C256 01010000B 0x50 00111010B 0x3A PCF8574 PCF8574 00111001B 0x39 00111011B PCF8574 00111000B 0x38 0x3B PCF8574 BINARY DEVICE FUNCTION 1 Date: Size:B DWG NO TITLE SHEET 1 509122-0001 Sheet TMS320C6424 Evaluation Module SPECTRUM DIGITAL INCORPORATED Thursday, February 01, 2007 Page Contents: Title: AUDIO CODEC - 00110(MFP1)(MFP0) EEPROM - 1010(A2)(A1)(A0) IO Expander - 0111(A2)(A1)(A0) IO Expander - 0111(A2)(A1)(A0) LED Expander - 0111(A2)(A1)(A0) USER INPUT Expander - 0111(A2)(A1)(A0) I2C Address Table HEX ADDRESS 2 1 of 30 Revision: A A B C D Spectrum Digital, Inc C6424 EVM Technical Reference A B C D 5 5 PCI Edge Conn PCI Switches/Mux ENET XCVR NAND/NOR/SRAM 4 VLYNQ DC Connector EMAC DC Connector ENET Switches DC Connector Boot DIP Switches EMIF Switch DC Connector I2C EEPROM I2C Expanders 4 VLYNQ mPCI Connector UHPI/PCI/EMAC EMIF/RMII EMIF-Addr/PCI EMIF-Ctrl EMIF/ McASP1/PCI I2C GIO/PCI 3 PCI AD DSP 3 Reset Logic Power Supplies VLYNQ/PCI/ UHPI Emulator PLL DDR2 IF UART0/PWM0 PWM1 Timer1/UART1 Timer0 2 MISC DC Connector McBSP1/MCASP0 McBSP0/McASP0 SPI EEPROM Socket 2 Date: Size: B DWG NO 1 509122-0001 BLOCK DIAGRAM Sheet TMS320C6424 Evaluation Module SPECTRUM DIGITAL INCORPORATED Embedded EMU EMU Header RS-232 XCVR Stereo Codec Thursday, February 01, 2007 Page Contents: Title: EMU Muxes Crystal/Osc DDR2 SDRAM UART Switches DC Connector S/PDIF Out Audio Switch McBSP/McASP DC Connector 1 2 of 30 Revision: A A B C D Spectrum Digital, Inc A-3 A B C D 1 2 5 A AA HEADER 2 NO-POP JP3 B BB 33 R2 GND EN U2 OUT VCC 3 4 ASFL3-27.000MHZ-EK-T 102229-0027 NO-POP 2 1 L1 1uF C1 R1 10K C3 .1uF NO-POP 4 VCC_1V8 2 1 BLM21PG221SN1D CRYSTAL AND CAPS REMOVED WHEN OSCILLATOR IS USED OPTIONAL OSCILLATOR POPULATION SILKSCREEN: RESETn PUSHBUTTON SW SW6 VCC_3V3 4 R4 R19 R5 C4 C2 no-pop 0 18 pF Y1 27MHz 18 pF 21 NO-POP R3 PCIEN 16,18,24,26,29 SYS_RESETn 4,20,26 RESETn 3 K18 K19 J19 T3 N4 M4 3 MXVSS MXI/CLKIN MXO PCIEN nPOR RESETn TMS320C6424 RSV2 RSV3 RSV4 RESETOUTn U1A K5 L5 L15 N3 2 2 TP2 TP30 R188 10K VCC_3V3 2 1 4 RESET_OUTn 20,27 RESET_OUT 17 DWG NO Thursday, February 01, 2007 1 509122-0001 DSP CLKS/RST/EMU Sheet TMS320C6424 Evaluation Module Size:B Date: 1 SPECTRUM DIGITAL INCORPORATED TP1 TP30 SN74AHC1G14DCKRG4 C195 .1uF Page Contents: Title: U69 VCC_3V3 5 A-4 3 5 3 of 30 Revision: A A B C D Spectrum Digital, Inc C6424 EVM Technical Reference A B C D TMS TRST TDI GND PD nc TDO GND TCKRET GND TCK GND EMU0 EMU1 J6 SILKSCREEN: EMULATION HEADER 5 2 4 6 8 10 12 14 24 ALT_AIC33_CLK 3,20,26 RESETn 10K R151 VCC_3V3 XDS_EMU1 XDS_TRST# 29 EMU_SYS_RESETn TSW-107-14-G-D-006 XDS_EMU0 13 1 3 XDS_TVD 5 XDS_TDO 7 XDS_TCK_RTN 9 XDS_TCK 11 XDS_TMS XDS_TDI VCC_3V3 VCC_3V3 R6 1K 4 Embedded_USB CLK_24MHZ CLK_12MHZ USB_DSP_RSTn PONRSn 3.3V XDS_TDO 4 C164 0.1uF T_TRSTn T_TCK T_TMS T_TDI T_TDO T_EMU0 T_EMU1 5V GND Green DS502 VCC_5V XDS_TCK_RTN XDS_TRST# XDS_EMU1 XDS_EMU0 XDS_TMS XDS_TCK XDS_TDI T_TCK_RET SN74AHC1G14DCKRG4 Embedded_USB 0.1uF C165 2 U38 VCC_3V3 5 3 VCC_3V3 4 3 R150 10K GND 4A 3A 2A 1A 8 12 9 7 4 16 S OE 1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2 U539 GND 4A 3A 2A 1A VCC 8 12 9 7 4 16 SN74CBTLV3257PWR 1 15 2 3 5 6 11 10 14 13 T_TCK_RET T_TRSTn T_TCK T_TMS T_TDI T_TDO T_EMU0 T_EMU1 10K R152 S OE 1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2 VCC SN74CBTLV3257PWR 1 15 2 3 5 6 11 10 14 13 U41 VCC_3V3 R10 R12 DSP_TRST# DSP_EMU1 DSP_EMU0 VCC_3V3 DSP_TMS DSP_TDI DSP_TDO JTAG MULTIPLEXERS USB EMBEDDED EMU ON VCC_3V3 EMU_STS T_TCK_RET T_TRSTn T_EMU1 T_EMU0 T_TMS T_TCK T_TDI T_TDO R149 150 VCC_3V3 3 0.1uF C167 2 NO-POP NO-POP 0.1uF C166 2 DSP_TCK DSP_EMU0 DSP_EMU1 DSP_TDO 4 Date: Size:B 1K 1K DSP_TCK VCC_3V3 U1F 33 33 C169 NO POP 1 1 509122-0001 Thursday, February 01, 2007 DWG NO DSP CLKS/RST/EMU Sheet TMS320C6424 Evaluation Module SPECTRUM DIGITAL INCORPORATED TCK EMU0 EMU1 TDO TMS TDI TRSTn Page Contents: Title: C168 0.1uF C163 0.1uF TMS320C6424 R11 R13 N1 P2 N2 P3 R3 P4 R2 R9 R8 SN74LVC1G32 U37 VCC_3V3 DSP_TMS DSP_TDI 4 NO POP SN74LVC1G32 U35 DSP_TRST# 2 1 2 1 VCC_3V3 R148 5 3 5 3 5 4 of 30 Revision: A A B C D Spectrum Digital, Inc A-5 A B C D 5 TINP0L TOUT0L CLKR0 DX0 FSX0 FSR0 CLKX0 DR0 27 16,24,27 16,27 27 16,24,27 16,24,27 27 27 CLKX1 DX1 CLKR1 DR1 FSX1 FSR1 24,27 24,27 24,27 24,27 24,27 24,27 26 I2C_INT_ENABLEn 33 33 33 33 R434 R435 R436 0 R432 R433 0 0 0 R429 R430 R431 10K R251 NO-POP R18 VCC_3V3 K2 J4 J2 J3 H3 G4 H1 H4 F1 G2 G1 G3 F2 H2 11 2 U3 74LVC1G125DCKRG4 4 CLKS1/TINP0L/GP[98] CLKS0/TOUT0L/GP[97] AHCLKR0/CLKR0/GP[101] AXR0[1]/DX0/GP[104] AXR0[2]/FSX0/GP[103] AXR0[3]/FSR0/GP[102] ACLKR0/CLKX0/GP[99] AFSR0/DR0/GP[100] ACLKX0/CLKX1/GP[106] AFSX0/DX1/GP[107] AHCLKX0/CLKR1/GP[108] AMUTE0/DR1/GP[110] AMUTEIN0/FSX1/GP[109] AXR0[0]/FSR1/GP[105] TMS320C6424 I2C_INT .1uF C7 4 VCC_3V3 5 4 U1E AD[0]/GP[0] AD[1]/GP[1] AD[2]/GP[2] AD[4]/GP[3] SCL SDA URTS0/PWM0/GP[88] UCTS0/GP[87] UTXD0/GP[86] URXD0/GP[85] GP[4]/PWM1 CLK_OUT/PWM2/GP[84] TOUT1L/UTXD1/GP[55] TINP1L/URXD1/GP[56] 1 A-6 3 5 E1 E2 E3 E4 M2 M3 L3 L1 K3 L2 F3 M1 K4 L4 R14 PWM1_I2C_INT 33 3 3 27 27 19,27 19,27 AD0_GP[0] 21 AD1_GP[1] 21 AD2_GP[2] 21 AD4_GP[3] 21 URTS0 UCTS0 UTXD0 URXD0 PWM1 26 CLK_OUT 26 TP41 TP-30 TP40 TP-30 TP61 TP-60 TP64 TP-60 2 2 TINP1L TOUT1L I2C_CLK 11,12,16,24,27 I2C_DATA 11,12,16,24,27 Thursday, February 01, 2007 1 509122-0001 DWG NO Date: DSP Serial/CAN/I2C Sheet TMS320C6424 Evaluation Module SPECTRUM DIGITAL INCORPORATED 2.2K R16 Size:B 2.2K R15 VCC_3V3 Page Contents: Title: 19,27 19,27 1 5 of 30 Revision: A A B C D Spectrum Digital, Inc C6424 EVM Technical Reference A B C D EM_D[0] EM_D[1] EM_D[2] EM_D[3] EM_D[4] EM_D[5] EM_D[6] EM_D[7] 5 R28 C135 0.1uF VCC_3V3 4 U29 3 EN GND 50MHz OUT VCC 1 2 4 RMII_SELECT D4 A4 TXD0 TXCLK 21 21 G19 D19 A15 A14 A13 H15 H16 H17 G17 G16 G15 F15 F18 A12 B13 C13 D14 B14 C14 B15 C15 D16 D18 D17 E16 E18 E17 F16 F17 C6 B5 C5 D5 B4 0 RPACK8-22 RPACK8-10 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 8 RPACK8-22 7 6 5 4 3 2 1 COL CRS TXD3 TXD2 TXD1 0 22 0 0 0 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 9 RPACK8-22 11 RPACK8-22 D15 10 RPACK8-22 E14 E15 4 21 21 21 21 21 RN6 RN4 RN1 A B A B A B A7 C8 D7 A8 B7 C7 A6 D6 B6 A5 R184 R27 R311 R312 R313 EM_D[8] EM_D[9] EM_D[10] EM_D[11] EM_D[12] EM_D[13] EM_D[14] EM_D[15] EM_D[0] EM_D[1] EM_D[2] EM_D[3] EM_D[4] EM_D[5] EM_D[6] EM_D[7] WAIT_BSYn PULL UP ON PAGE 16 RN14F 6 RN14G 7 RN14H 8 20 PCICLK 20 AD18 20 AD16 20 AD17 20 PCBE2n 20 PFRAMEn 20 PIDRDYn 21 PTRDYn 21 PDEVSELn 21 PPERn 26 RMCRSVD 26 RMREFCLK 26 RMRXER 26 GP[54] 26 GP[53] 26 RMTXEN 10,26 RMTXD0_8_16 10,26 RMTXD1_LENDIAN 10,26 GP[26]_FASTBOOT 10,26 GP[25]_BOOTMODE3 10,26 GP[24]_BOOTMODE2 10,26 GP[23]_BOOTMODE1 10,26 GP[22]_BOOTMODE0 14,26 EM_D[8] 14,26 EM_D[9] 14,26 EM_D[10] 14,26 EM_D[11] 14,26 EM_D[12] 14,26 EM_D[13] 14,26 EM_D[14] 14,26 EM_D[15] 14,26 14,26 14,26 14,26 14,26 14,26 14,26 14,26 15,16,26 EM_OEn 15,16,26 EM_WEn 15,26 EM_WAIT_BSYn 5 TMS320C6424 RMII_SELECT 12,17,18 HD14/MTXD0/AD15/GP[72] HD15/MTXCLK/AD12/GP[73] HD9/MCOL/PSTOPn/GP[7] HD10/MCRS/PSERRn/GP[68] HD11/MTXD3/PCBE1/GP[69] HD12/MTXD2/PPAR/GP[70] HD13/MTXD1/AD14/GP[71] VLYNQ_CLOCK/PCICLK/GP[57] HD0/VLYNQ_SCRUN/AD18/GP[58] HD1/VLYNQ_RXD0/AD16/GP[59] HD2/VLYNQ_RXD1/AD17/GP[60] HD3/VLYNQ_RXD2/PCBE2n/GP[61] HD4/VLYNQ_RXD3/PFRAMEn/GP[62] HD5/VLYNQ_TXD0/PIRDYn/GP[63] HD6/VLYNQ_TXD1/PTRDYn/GP[64] HD7/VLYNQ_TXD2/PDEVSELn/GP[65] HD8/VLYNQ_TXD3/PPERRn/GP[66] RMCRSVD/GP[30] RMREFCLK/GP[31] RMRXER/GP[52] GP[54] GP[53] RMTXEN/GP[29] RMTXD0/GP[28]/(8_16) RMTXD1/GP[27]/(ENDIAN) GP[26]/(FASTBOOT) GP[25]/(BOOTMODE3) GP[24]/(BOOTMODE2) GP[23]/(BOOTMODE1) GP[22]/(BOOTMODE0) EM_D[8]/GP[43] EM_D[9]/GP[42] EM_D[10]/GP[41] EM_D[11]/GP[40] EM_D[12]/GP[39] EM_D[13]/GP[38] EM_D[14]/GP[37] EM_D[15]/GP[36] EM_D[0]/GP[14] EM_D[1]/GP[15] EM_D[2]/GP[16] EM_D[3]/GP[17] EM_D[4]/GP[18] EM_D[5]/GP[19] EM_D[6]/GP[20] EM_D[7]/GP[21] EM_OEn EM_WEn EM_WAIT/(RDY/BSYn) 3 3 HCSn/MDCLK/AD5/GP[81] HASn/MDIO/AD3/GP[83] HHWIL/MRXDV/AD13/GP[74] HCNTL0/MRXER/AD10/GP[76] HCNTL1/MTXEN/AD11/GP[75] HRNW/MRXCLK/AD8/GP[77] HINTn/MRXD3/AD6/GP[82] HRDYn/MRXD2/PCBE0/GP[80] HDS1n/MRXD1/AD7/GP[79] HDS2n/MRXD0/AD9/GP[78] AD26 AD28 AD30 EM_RNW/GP[35] EM_CS2n/GP[12] EM_CS3n/GP[13] RMRXD0/EM_CS4n/GP[32] RMRXD1/EM_CS5n/GP[33] EM_A[13]/AD25/GP[51] EM_A[14]/AD27/GP[50] EM_A[15]/AD29/GP[49] EM_A[16]/PGNTn/GP[48] EM_A[17]/AD31/GP[47] EM_A[18]/PRSTn/GP[46] EM_A[19]/PREQn/GP[45] EM_A[20]/PINTAn/GP[44] EM_A[5]/AD19/GP[96] EM_A[6]/AD20/GP[95] EM_A[7]/AD22/GP[94] EM_A[8]/AD21/GP[93] EM_A[9]/PIDSEL/GP[92] EM_A[10]/AD23/GP[91] EM_A[11]/AD24/GP[90] EM_A[12]/PCBE3/GP[89] EM_BA[0]/GP[6]/(AEM1) EM_BA[1]/GP[5]/(AEM0) EM_A[0]/GP[7]/(AEM2) EM_A[1]/(ALE)/GP[9] EM_A[2]/(CLE)/GP[8] EM_A[3]/GP[11] EM_A[4]/GP[10] EM_A[21]/GP[34] U1G C1 D1 C4 B3 D3 A3 C2 D2 B2 C3 E10 E11 E12 D13 C19 C18 E19 F19 B10 A10 B11 C11 A11 D11 B12 C12 B8 D8 C9 B9 D9 A9 C10 D10 C17 C16 B17 A16 B16 B18 A17 D12 RPACK8-22 RPACK8-22 RPACK8-22 RPACK8-22 RPACK8-22 9 10 11 12 13 14 15 16 RN2 2 15 16 14 13 12 R165 R168 A A A A A 2 1 3 4 5 RN14B RN14A RN14C RN14D RN14E RPACK8-22 8 7 6 5 4 3 2 1 B B B B B VCC_3V3 2 Date: Size: B MDC MDIO RXDV RXER TXEN RXCLK RXD3 RXD2 RXD1 RXD0 AD26 AD28 AD30 21 21 21 21 21 21 21 21 21 21 20 20 20 EM_RNW 26 EM_CS2 14 EM_CS3 26 RMRXD0_EM_CS4 26 RMRXD1_EM_CS5 26 EM_A13_AD25 20 EM_A14_AD27 20 EM_A15_AD29 20 EM_A16_PGNTn 20 EM_A17_AD31 20 EM_A18_PRSTn 20 EM_A19_PREQn 20 EM_A20_PINTAn 20 EM_A05_AD19 20 EM_A06_AD20 20 EM_A07_AD22 20 EM_A08_AD21 20 EM_A09_PIDSEL 20 EM_A10_AD23 20 EM_A11_AD24 20 EM_A12_PCBE3 20 EM_BA0 10,15,16,26 EM_BA1 10,15,16,26 EM_A00 10,15,16,26 EM_A01_ALE 15,16,26 EM_A02_CLE 15,16,26 EM_A03 15,16,26 EM_A04 10,15,16,26 EM_A21 14,26 20K 20K 1 509122-0001 Thursday, February 01, 2007 DWG NO DSP VP/EMIF/PCI/ENET Sheet TMS320C6424 Evaluation Module SPECTRUM DIGITAL INCORPORATED R166 R167 Page Contents: Title: NO-POP NO-POP 1 6 of 30 Revision: A A B C D Spectrum Digital, Inc A-7 A-8 A B C D 13 VREF_STL 0.1uF C5 0.1uF C111 R77 1K 1% R76 1K 1% VCC_1V8 5 13 13 13 13 DDR_DQS0 DDR_DQS1 DDR_DQS2 DDR_DQS3 13 DDR_D[0:31] Follow the DDR PCB Layout App Note 5 DDR _D0 DDR _D1 DDR _D2 DDR _D3 DDR _D4 DDR _D5 DDR _D6 DDR _D7 DDR _D8 DDR _D9 D DR_D10 D DR_D11 D DR_D12 D DR_D13 D DR_D14 D DR_D15 D DR_D16 D DR_D17 D DR_D18 D DR_D19 D DR_D20 D DR_D21 D DR_D22 D DR_D23 D DR_D24 D DR_D25 D DR_D26 D DR_D27 D DR_D28 D DR_D29 D DR_D30 D DR_D31 4 C9 0.1uF VREF_STL DDR_DQS0 DDR_DQS1 DDR_DQS2 DDR_DQS3 4 T15 U4 U6 U14 U16 T1 T2 U1 U2 V2 U3 V3 W3 V4 W4 U5 V5 W5 V6 W6 V7 W14 V14 W15 V15 U15 W16 V16 T17 V17 U17 T18 W17 U18 V18 U19 T19 TP10 TP-60 TP9 TP-60 TP8 TP-60 TP7 TP-60 DDR_VREF DDR_DQS[0] DDR_DQS[1] DDR_DQS[2] DDR_DQS[3] DDR_D[0] DDR_D[1] DDR_D[2] DDR_D[3] DDR_D[4] DDR_D[5] DDR_D[6] DDR_D[7] DDR_D[8] DDR_D[9] DDR_D[10] DDR_D[11] DDR_D[12] DDR_D[13] DDR_D[14] DDR_D[15] DDR_D[16] DDR_D[17] DDR_D[18] DDR_D[19] DDR_D[20] DDR_D[21] DDR_D[22] DDR_D[23] DDR_D[24] DDR_D[25] DDR_D[26] DDR_D[27] DDR_D[28] DDR_D[29] DDR_D[30] DDR_D[31] TMS320C6424 BDDR_DQM0 BDDR_DQM1 BDDR_DQM2 BDDR_DQM3 T4 T6 T14 T16 R13 T12 T13 T10 T11 R34 TP6 TP-30 0 DDR_PADREFN R32 D DR_PADREFP R33 BDDR_CLK_N BDDR_C LK BD DR_CS T9 W8 W7 BDDR_CAS BDDR_RAS BDDR_WE BDDR_CKE BDDR_BS00 BDDR_BS01 BDDR_BS02 U8 V9 U9 T7 U7 T8 V8 BDDR_A0 BDDR_A1 BDDR_A2 BDDR_A3 BDDR_A4 BDDR_A5 BDDR_A6 BDDR_A7 BDDR_A8 BDDR_A9 BDDR_A10 BDDR_A11 BDDR_A12 W13 U13 V13 U12 V12 W12 W11 V11 V10 U11 U10 W10 W9 3 SURFACE MOUNT TEST POINT PADS USED FOR VERIFYING DDR TIMINGS RSV5 DDR_VDDDLL DDR_VSSDLL DDR_ZN DDR_ZP DDR_CLK0n DDR_CLK0 DDR_DQM[0] DDR_DQM[1] DDR_DQM[2] DDR_DQM[3] DDR_CSn DDR_CASn DDR_RASn DDR_WEn DDR_CKE DDR_BS[0] DDR_BS[1] DDR_BS[2] DDR_A[0] DDR_A[1] DDR_A[2] DDR_A[3] DDR_A[4] DDR_A[5] DDR_A[6] DDR_A[7] DDR_A[8] DDR_A[9] DDR_A[10] DDR_A[11] DDR_A[12] U1C 3 200 200 4 3 2 1 4 3 2 1 4 3 2 1 R30 R31 R86 R84 R87 R85 R29 RN11 5 6 7 8 RN10 4 3 2 1 RN9 RN8 RN7 C8 0.1uF DDR_A0 DDR_A1 DDR_A2 DDR_A3 C10 1uF R35 2 0.1 TP5 TP-30 DDR_CLK_N DDR_CLK DDR_DQM0 DDR_DQM1 DDR_DQM2 DDR_DQM3 DDR_ CS RPACK4-22 DD R_CAS DD R_RAS DDR_WE DD R_CKE TP4 TP-30 10 10 22 22 22 22 22 4 3 2 1 RPACK4-22 5 DDR_A12 DDR_BS00 6 DDR_BS01 7 DDR_BS02 8 RPACK4-22 5 DDR_A4 6 DDR_A5 7 DDR_A6 8 DDR_A7 RPACK4-22 5 DDR_A8 6 DDR_A9 7 DDR_A10 8 DDR_A11 5 6 7 8 RPACK4-22 2 1 Thursday, February 01, 2007 1 509122-0001 DWG NO Date: DSP DDR Interface Size: B Sheet TMS320C6424 Evaluation Module SPECTRUM DIGITAL INCORPORATED VCC_1V8 Page Contents: Title: 2 BLM21PG221SN1D L3 DDR_CLK_N 13 DDR_CLK 13 13 13 13 13 13 13 13 13 13 DDR_DQM0 DDR_DQM1 DDR_DQM2 DDR_DQM3 DDR_ CS DDR_CAS DDR_RAS DDR_WE DDR_CKE DDR_BS00 13 DDR_BS01 13 DDR_BS02 13 DDR_A[0:12] 13 1 7 of 30 Revision: A A B C D Spectrum Digital, Inc C6424 EVM Technical Reference A B C D 5 5 4 4 3 3 A19 B1 B19 E7 E9 E13 F4 F6 F8 F10 F12 F14 G5 G7 G9 G11 G13 G18 H6 H8 H10 H12 H14 H19 J5 J7 J9 J11 J13 J15 J17 J18 K1 K6 K8 K10 K12 K14 K16 P17 N15 N16 N19 TMS320C6424 Vss.1 Vss.2 Vss.3 Vss.4 Vss.5 Vss.6 Vss.7 Vss.8 Vss.9 Vss.10 Vss.11 Vss.12 Vss.13 Vss.14 Vss.15 Vss.16 Vss.17 Vss.18 Vss.19 Vss.20 Vss.21 Vss.22 Vss.23 Vss.24 Vss.25 Vss.26 Vss.27 Vss.28 Vss.29 Vss.30 Vss.31 Vss.32 Vss.33 Vss.34 Vss.35 Vss.36 Vss.37 Vss.38 Vss.39 TMS320C6424 RSV14(VSS) RSV13(VSS) RSV15(VSS) RSV6(VSS) U1D P16 P15 N17 N18 P18 P19 Vss.40 Vss.41 Vss.42 Vss.43 Vss.44 Vss.45 Vss.46 Vss.47 Vss.48 Vss.49 Vss.50 Vss.51 Vss.52 Vss.53 Vss.54 Vss.55 Vss.56 Vss.57 Vss.58 Vss.59 Vss.60 Vss.61 Vss.62 Vss.63 Vss.64 Vss.65 Vss.66 Vss.67 Vss.68 Vss.69 Vss.70 Vss.71 Vss.72 Vss.73 Vss.74 Vss.75 Vss.76 Vss.77 U1H RSV11(VSS) RSV12(VSS) RSV10(OPEN) RSV9(OPEN) RSV8(OPEN) RSV7(OPEN) L7 L9 L11 L13 L17 L19 M6 M8 M10 M12 M14 M16 M17 M18 M19 N5 N7 N9 N11 N13 N14 P6 P8 P10 P12 P14 R1 R5 R7 R9 R11 R15 R17 R18 R19 V19 W1 W2 2 2 Thursday, February 01, 2007 1 509122-0001 DWG NO Date: DSP DACS/GND-pins Size: B Sheet TMS320C6424 Evaluation Module SPECTRUM DIGITAL INCORPORATED Page Contents: Title: 1 8 of 30 Revision: A A B C D Spectrum Digital, Inc A-9 A-10 A B C D TP42 TP-60 5 0.025 TP43 TP-60 R317 TP47 TP-60 0.025 3 2 1 MH3 MH2 MH1 TMS320C6424 MH6 MH5 MH4 5 U1L 6 5 4 THESE PINS ARE FOR LAYOUT SYMBOL FOR SOCKET MOUNTING PINS & SOCKET MOUNTING HOLES VCC_1V8 TP46 TP-60 R319 DVDD_1V8 POWER TEST POINT AT THE REGULATOR FOR 1.2 V DSP_CORE_VDD VCC_3V3 L18 L14 P5 P7 P9 P11 P13 R4 R6 H7 H9 H11 H13 J8 J10 J12 K7 K9 K11 A1 A2 A18 E6 E8 F5 F7 F9 F11 F13 G6 G8 G10 G12 G14 H5 H18 DVdd33.18 DVdd33.19 DVdd33.20 DVdd33.21 DVdd33.22 DVdd33.23 DVdd33.24 DVdd33.25 DVdd33.26 DVdd33.27 DVdd33.28 TMS320C6424 4 U1B CVdd.11 CVdd.12 CVdd.13 CVdd.14 CVdd.15 CVdd.16 CVdd.17 CVdd.18 CVdd.19 CVdd.20 CVdd.21 U1I PLLPWR18 RSV1 U1K DVDDR2.9 DVDDR2.10 DVDDR2.11 DVDDR2.12 DVDDR2.13 DVDDR2.14 DVDDR2.15 DVDDR2.16 DVDDR2.17 TMS320C6424 MXVDD DVDDR2.1 DVDDR2.2 DVDDR2.3 DVDDR2.4 DVDDR2.5 DVDDR2.6 DVDDR2.7 DVDDR2.8 TMS320C6424 CVdd.1 CVdd.2 CVdd.3 CVdd.4 CVdd.5 CVdd.6 CVdd.7 CVdd.8 CVdd.9 CVdd.10 U1J C VDD_CORE DVdd33.1 DVdd33.2 DVdd33.3 DVdd33.4 DVdd33.5 DVdd33.6 DVdd33.7 DVdd33.8 DVdd33.9 DVdd33.10 DVdd33.11 DVdd33.12 DVdd33.13 DVdd33.14 DVdd33.15 DVdd33.16 DVdd33.17 TMS320C6424 DVDD_3V3 4 L16 E5 R8 R10 R12 R14 R16 T5 V1 W18 W19 K13 L8 L10 L12 M7 M9 M11 M13 N8 N10 N12 J1 J6 J14 J16 K15 K17 L6 M5 M15 N6 P1 C VDD_CORE DVDD_1V8 C VDD_CORE C VDD_CORE DVDD_3V3 DVDD_3V3 + + C57 33uF 3 C71 1000pF + C55 33uF C27 33uF 3 + + + + + 0.1uF C49 0.1uF C42 0.1uF C29 0.1uF C19 C72 0.1uF C69 33uF C56 33uF C41 33uF C39 33uF C28 33uF 0.1uF C51 0.1uF C44 0.1uF C31 0.1uF C21 0.1uF C52 0.1uF C45 0.1uF C32 0.1uF C22 0.1uF C53 0.1uF C46 0.1uF C33 0.1uF C23 C73 1uF 0.1uF C58 0.1uF C60 TP48 TP-30 R320 0.1uF C59 2 C26 L6 0.1uF C64 0.1uF 0.1uF C70 DWG NO 1 509122-0001 Thursday, February 01, 2007 DSP Power Pins Size: B Date: 0.1uF C188 Sheet TMS320C6424 Evaluation Module Page Contents: Title: 0.1uF C67 1 SPECTRUM DIGITAL INCORPORATED 0.1uF C66 VCC_1V8 0.1uF C65 0.1uF C37 C190 0.1uF C36 0.1uF 2 1 BLM21PG221SN1D 0.1uF C63 0.1uF C189 0.1uF C48 0.1uF C35 0.1uF C25 0.1uF TP49 TP-30 0.1 0.1uF C61 C62 0.1uF C54 0.1uF C47 0.1uF C34 0.1uF C24 Place near DDR side of package 0.1uF C50 0.1uF C43 0.1uF C30 0.1uF C20 2 9 of 30 Revision: A A B C D Spectrum Digital, Inc C6424 EVM Technical Reference A B C 5 6,26 GP[22]_BOOTMODE0 6,26 GP[23]_BOOTMODE1 6,26 GP[24]_BOOTMODE2 6,26 GP[25]_BOOTMODE3 6,26 GP[26]_FASTBOOT 6,26 RMTXD1_LENDIAN 6,26 RMTXD0_8_16 4 VCC_3V3 4 R173 R44 R45 R174 1.5K 1.5K 1.5K 1.5K 1 2 3 4 4 3 2 1 ON SW2 8 7 6 5 DIP_SWITCH-4 RN12 RPACK8-20K 9 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1 D 5 3 3 R42 20K R43 20K R364 20K R258 20K VCC_3V3 R175 20K ON 8 6 7 5 4 3 2 1 1 2 3 4 5 6 7 8 R176 20K DIP_SWITCH-8 16 15 14 13 12 11 10 9 SW1 2 EM_A00 EM_BA0 EM_BA1 EM_A04 2 6,15,16,26 6,15,16,26 6,15,16,26 6,15,16,26 R357 1.5K 16 15 14 13 12 11 10 9 RN13 Date: Size:B BM0 BM1 BM2 BM3 FASTB LENDIAN 8_16 DWG NO 1 509122-0001 Boot DIP Switches Sheet TMS320C6424 Evaluation Module Thursday, February 01, 2007 Page Contents: Title: 1 2 3 4 5 6 7 8 SPECTRUM DIGITAL INCORPORATED VCC_3V3 RPACK8-1.5K 1 10 o f 30 Revision: A A B C D Spectrum Digital, Inc A-11 A B C D 5 4 5 2 1 R74 10K 27 USER_I2C_IO.A0P7 27 USER_I2C_IO.A0P6 23,28 VLYNQ_RESET U66 SN74AHC1G14DCKRG4 I2C_INT C187 .1uF VCC_3V3 5,12,16,24,27 I2C_DATA 5,12,16,24,27 I2C_CLK 5 3 C90 .1uF 4 5 4 2 1 20 19 17 16 18 13 VCC_3V3 U10 6 7 9 10 11 12 14 15 3 8 VCC_3V3 RN20 RPACK4-10K VDD A0 SDA A1 SCL A2 INT P0 P7 P1 P6 P2 P5 P3 P4 GND NC.4 NC.1 NC.3 NC.2 PCF8574APWRG4 VCC_3V3 8 7 6 5 1 2 3 4 16 15 14 13 12 11 10 9 3 JP1 3 PIN JUMPER 1 PADDLE DIP-4 C91 .1uF 5 4 2 1 20 19 17 16 18 13 VCC_3V3 SILKSCREEN: USER SWITCHES SW4 RPACK8-10K RN37 3 A0 A1 A2 P0 P1 P2 P3 GND NC.1 NC.2 U11 R17 PCF8574APWRG4 VDD SDA SCL INT P7 P6 P5 P4 NC.4 NC.3 2 4 3 A-12 1 2 3 4 5 6 7 8 5 6 7 9 10 11 12 14 15 3 8 1K VCC_3V3 2 4 1 2 DS1 LED_GRN R64 330 VCC_3V3 2 4 3 2 1 RPACK4-1K 1K 3 1 509122-0001 Thursday, February 01, 2007 DWG NO Date: I2C Expanders Sheet TMS320C6424 Evaluation Module SPECTRUM DIGITAL INCORPORATED LED_RED DS4 R67 330 Size:B DS3 LED_GRN R66 330 Page Contents: Title: DS2 LED_GRN R65 330 USER CONTROLLED LEDS 5 6 7 8 RN38 R7 SW7 GS01MSAKE 5 1 11 o f 30 Revision: A A B C D Spectrum Digital, Inc C6424 EVM Technical Reference A B C D 5 5,11,16,24,27 I2C_DATA 5,11,16,24,27 I2C_CLK VCC_3V3 5,11,16,24,27 I2C_DATA 5,11,16,24,27 I2C_CLK C92 0.1uF R162 R161 C185 0.1uF VCC_3V3 5 4 2 1 20 19 17 16 18 13 1K 1K 5 4 2 1 20 19 17 16 18 13 U13 A0 A1 A2 P0 P1 P2 P3 GND NC.1 NC.2 A0 A1 A2 P0 P1 P2 P3 GND NC.1 NC.2 U64 4 PCF8574APWRG4 VDD SDA SCL INT P7 P6 P5 P4 NC.4 NC.3 2 1 1 2 SW3 DIP_SWITCH-2 4 3 6 7 9 10 11 12 14 15 3 8 PCF8574APWRG4 VDD SDA SCL INT P7 P6 P5 P4 NC.4 NC.3 RPACK4-10K RN22 VCC_3V3 1 2 3 4 8 7 6 5 6 7 9 10 11 12 14 15 3 8 VCC_3V3 VCC_3V3 RN34 RPACK4-10K R253 10K VCC_3V3 R252 NO-POP 1 2 3 4 8 7 6 5 VCC_3V3 3 USER_I2C_IO.A1P0 27 USER_I2C_IO.A1P1 27 USER_I2C_IO.A1P2 27 USER_I2C_IO.A1P3 27 3 VCC_3V3 27 AIC33_ENABLEn RMII_SELECT 6,17,18 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 RN15 RPACK8-10k R185 10K 2 1 2 1 2 4 2 1 C205 0.1uF DWG NO 1 509122-0001 Thursday, February 01, 2007 I2C Expanders Sheet TMS320C6424 Evaluation Module Size: B Date: McASP_ONn 24 McBSP_ONn 24 1 SPECTRUM DIGITAL INCORPORATED C206 0.1uF Page Contents: Title: 4 SN74LVC1G32 U74 VCC_3V3 U42 SN74AHC1G14DCKRG4 4 SN74LVC1G32 U73 VCC_3V3 VCC_3V3 I2C.IOP4 I2C.IOP5 I2C.IOP6 CORE_VDD_SELECT 29 SPDIF_ONn 24 I2C.IOP3 C170 0.1uF 2 5 3 5 3 4 5 3 5 12 o f 30 Revision: A A B C D Spectrum Digital, Inc A-13 A-14 A B C D 7 DDR_DQM1 7 DDR_DQM0 7 DDR_DQS0 7 DDR_DQS1 7 DDR_CLK 7 DDR_CLK_N 7 DDR_CS 7 DDR_CAS 7 DDR_RAS 7 DDR_WE 7 DDR_CKE 7 DDR_BS02 7 DDR_BS01 7 DDR_BS00 7 DDR_A[0:12] 5 7 DDR_ D[0:31] E3 J3 D8 22 BDDR_DQS1 E7 H8 22 BDDR_DQS0 J7 DDR_DQM1 DDR_DQM0 DDR_DQS0 R82 DDR_DQS1 R80 M8 N8 DDR_CLK DDR_CLK_N 22 V3 V7 N9 P8 P7 N7 N3 N2 R78 T8 T2 R7 R3 R8 P1 P3 P2 DDR_A4 DDR_A3 DDR_A2 DDR_A1 DDR_A0 AA9 AA8 AA2 AA1 D2 V8 A9 A8 A2 A1 H2 V2 U7 R2 U3 U8 U2 T7 T3 DDR_A12 DDR_A11 DDR_A10 DDR_A9 DDR_A8 DDR_A7 DDR_A6 DDR_A5 DDR_CS DDR_CAS DDR_RAS DDR_WE DDR_CKE DDR_BS02 DDR_BS01 DDR_BS00 5 U16 VSS.1 VSS.2 VSS.3 VSS.4 VSS.5 VSSQ.1 VSSQ.2 VSSQ.3 VSSQ.4 VSSQ.5 VSSQ.6 VSSQ.7 VSSQ.8 VSSQ.9 VSSQ.10 VSSDL DQ3 DQ2 DQ1 DQ0 DQ7 DQ6 DQ5 DQ4 DQ11 DQ10 DQ9 DQ8 DQ15 DQ14 DQ13 DQ12 VREF VDDL VDD.1 VDD.2 VDD.3 VDD.4 VDD.5 VDDQ.1 VDDQ.2 VDDQ.3 VDDQ.4 VDDQ.5 VDDQ.6 VDDQ.7 VDDQ.8 VDDQ.9 VDDQ.10 BDDR_D7 BDDR_D6 BDDR_D5 BDDR_D4 BDDR_D3 BDDR_D2 BDDR_D1 BDDR_D0 G3 G7 F2 F8 J9 J1 L9 L1 L3 L7 K2 K8 U9 T1 H3 D3 M3 G8 J8 D7 J2 E2 L8 L2 E8 H7 G2 M7 BDDR_D11 BDDR_D10 BDDR_D9 BDDR_D8 E9 E1 G9 G1 VREF_STL VCC_1V8 BDDR_D15 BDDR_D14 BDDR_D13 BDDR_D12 M2 M1 M9 H1 R9 D1 V1 F3 F7 K1 K3 K7 K9 D9 F1 F9 H9 0.1uF 7 DDR_DQM3 7 DDR_DQM2 7 DDR_DQS2 7 DDR_DQS3 BDDR_D12 4 BDDR_D14 3 BDDR_D11 2 BDDR_D9 1 RN27 BDDR_D4 1 BDDR_D6 2 BDDR_D3 3 BDDR_D1 4 RN29 RN23 BDDR_D13 1 BDDR_D15 2 BDDR_D8 3 BDDR_D10 4 RN25 BDDR_D5 4 BDDR_D7 3 BDDR_D2 2 BDDR_D0 1 BDDR_D[0:15] 0.1uF C93 C105 C104 0.1uF 0.1uF C95 0.1uF C94 0.1uF C97 DDR_DQS2 22 DDR_DQS3 22 5D DR_D12 6D DR_D14 7D DR_D11 8DDR _D9 RPACK4-22 8DDR _D4 7DDR _D6 6DDR _D3 5DDR _D1 RPACK4-22 RPACK4-22 8D DR_D13 7D DR_D15 6DDR _D8 5D DR_D10 RPACK4-22 5DDR _D5 6DDR _D7 7DDR _D2 8DDR _D0 C112 0.1uF VREF_STL 0.1uF C106 0.1uF C96 DDR_DQM3 DDR_DQM2 R83 R81 R79 DDR_A4 DDR_A3 DDR_A2 DDR_A1 DDR_A0 BDDR_DQS2 BDDR_DQS3 DDR_CLK DDR_CLK_N 4 3 22 DDR_A12 DDR_A11 DDR_A10 DDR_A9 DDR_A8 DDR_A7 DDR_A6 DDR_A5 DDR_CS DDR_CAS DDR_RAS DDR_WE DDR_CKE DDR_BS02 DDR_BS01 DDR_BS00 22uF + C102 3 Layout for the 92-ball DDR Package but populate the 84-ball EDE5116AFSE. Ball assignments are incorrect for 84-ball package. Use -5C-E (533MHz) or -4A-E (400MHz) speed grade? 64 MEGABYTES 92-ball DDR Package UDM LDM UDQS#/NU UDQS LDQS#/NU LDQS CK CK# CS# CAS# RAS# WE# CKE RFU.1 RFU.2 ODT NC.1 NC.2 NC.3 NC.4 NC.5 NC.6 NC.7 NC.8 NC.9 NC.10 NC.11 A4 A3 A2 A1 A0 BA2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 4 U17 VSS.1 VSS.2 VSS.3 VSS.4 VSS.5 VSSQ.1 VSSQ.2 VSSQ.3 VSSQ.4 VSSQ.5 VSSQ.6 VSSQ.7 VSSQ.8 VSSQ.9 VSSQ.10 VSSDL DQ3 DQ2 DQ1 DQ0 DQ7 DQ6 DQ5 DQ4 DQ11 DQ10 DQ9 DQ8 DQ15 DQ14 DQ13 DQ12 VREF VDDL VDD.1 VDD.2 VDD.3 VDD.4 VDD.5 VDDQ.1 VDDQ.2 VDDQ.3 VDDQ.4 VDDQ.5 VDDQ.6 VDDQ.7 VDDQ.8 VDDQ.9 VDDQ.10 92-ball DDR Package UDM LDM UDQS#/NU UDQS LDQS#/NU LDQS CK CK# CS# CAS# RAS# WE# CKE RFU.1 RFU.2 ODT NC.1 NC.2 NC.3 NC.4 NC.5 NC.6 NC.7 NC.8 NC.9 NC.10 NC.11 A4 A3 A2 A1 A0 BA2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 U9 T1 H3 D3 M3 G8 J8 D7 J2 E2 L8 L2 E8 H7 G2 M7 L3 L7 K2 K8 J9 J1 L9 L1 G3 G7 F2 F8 E9 E1 G9 G1 M2 M1 M9 H1 R9 D1 V1 F3 F7 K1 K3 K7 K9 D9 F1 F9 H9 VCC_1V8 2 BDDR_ D19 BDDR_ D18 BDDR_ D17 BDDR_ D16 BDDR_ D23 BDDR_ D22 BDDR_ D21 BDDR_ D20 BDDR_ D27 BDDR_ D26 BDDR_ D25 BDDR_ D24 BDDR_ D31 BDDR_ D30 BDDR_ D29 BDDR_ D28 64 MEGABYTES E3 J3 D8 E7 H8 J7 M8 N8 P8 P7 N7 N3 N2 V3 V7 N9 AA9 AA8 AA2 AA1 D2 V8 A9 A8 A2 A1 H2 T8 T2 R7 R3 R8 P1 P3 P2 V2 U7 R2 U3 U8 U2 T7 T3 2 C108 0.1uF C99 0.1uF C109 0.1uF C100 0.1uF 1 509122-0001 Thursday, February 01, 2007 DWG NO Date: DDR2 Memories Size: B Sheet TMS320C6424 Evaluation Module SPECTRUM DIGITAL INCORPORATED Page Contents: Title: 4 3 2 1 RN30 BDDR_D19 BDDR_D17 BDDR_D22 BDDR_D20 RPACK4-22 5 DDR_D19 6 DDR_D17 7 DDR_D22 8 DDR_D20 RPACK4-22 8 DDR_D23 7 DDR_D16 6 DDR_D18 5 DDR_D21 1 2 3 4 DDR_D26 DDR_D29 DDR_D24 DDR_D31 C103 22uF RN28 BDDR_D23 BDDR_D16 BDDR_D18 BDDR_D21 5 6 7 8 RPACK4-22 + RPACK4-22 5 DDR_D28 6 DDR_D30 7 DDR_D25 8 DDR_D27 4 3 2 1 C110 0.1uF C101 0.1uF RN26 BDDR_D28 4 BDDR_D30 3 BDDR_D25 2 BDDR_D27 1 BDDR_D26 BDDR_D29 BDDR_D24 BDDR_D31 RN24 0.1uF C113 BDDR_D[16:31] VREF_STL C107 0.1uF C98 0.1uF 1 13 o f 30 Revision: A VREF_STL 7 A B C D Spectrum Digital, Inc C6424 EVM Technical Reference A B C D 26 EMA21-13_ENABLEn 5 6 EM_CS2 R88 NO-POP VCC_3V3 R247 10K 5 B.EM_A17 B.EM_A18 B.EM_A19 B.EM_A20 20,26 20,26 20,26 20,26 47K 1 2 3 4 5 6 7 8 R89 16 15 14 13 12 11 10 9 RN31 B.EM_A17 B.EM_A18 B.EM_A19 B.EM_A20 B.EM_A13 B.EM_A14 B.EM_A15 B.EM_A16 TO TO TO TO JP2 1 5 3 7 2 6 4 8 2 4 6 8 FLASH SRAM NAND FLASH DAUGHTERCARD CONN 4x2 1 3 5 7 PIN PIN PIN PIN EM_CS2 SELECT SILKSCREEN: B.EM_A13 B.EM_A14 B.EM_A15 B.EM_A16 20,26 20,26 20,26 20,26 6,26 EM_A21 4 1OE 2OE 1A1 1A2 1A3 1A4 1A5 2A1 2A2 2A3 2A4 2A5 U18 GND 1B1 1B2 1B3 1B4 1B5 2B1 2B2 2B3 2B4 2B5 VCC 12 2 5 6 9 10 15 16 19 20 23 24 FLASH_CEn 16 SRAM_CEn 15 NAND_CEn 15 DC_EM_CS2n 26 MEM.EM_A20 MEM.EM_A19 MEM.EM_A18 MEM.EM_A17 MEM.EM_A13 MEM.EM_A14 MEM.EM_A15 MEM.EM_A16 MEM.EM_A21 SN74CBTLV3384PW 1 13 3 4 7 8 11 14 17 18 21 22 RPACK8-47K 4 MEM.EM_A17 MEM.EM_A18 MEM.EM_A19 MEM.EM_A20 MEM.EM_A21 MEM.EM_A13 MEM.EM_A14 MEM.EM_A15 MEM.EM_A16 C114 0.1uF 3 3 26 MEM_D15-8_ENABLEn VCC_3V3 R190 10K R92 NO-POP R248 10K R90 NO-POP VCC_3V3 26 MEM_EMD7-0_ENABLEn MEM.EM_A[20:13] 15,16 MEM.EM_A21 16 VCC_3V3 EM_D[7] EM_D[6] EM_D[1] EM_D[0] EM_D[5] EM_D[4] EM_D[3] EM_D[2] 6,26 EM_D[12] 6,26 EM_D[13] 6,26 EM_D[14] 6,26 EM_D[15] 6,26 EM_D[8] 6,26 EM_D[9] 6,26 EM_D[10] 6,26 EM_D[11] 6,26 6,26 6,26 6,26 6,26 6,26 6,26 6,26 2 EM_D[12] EM_D[13] EM_D[14] EM_D[15] EM_D[8] EM_D[9] EM_D[10] EM_D[11] EM_D7 EM_D6 EM_D1 EM_D0 EM_D5 EM_D4 EM_D3 EM_D2 2 1OE 2OE 1A1 1A2 1A3 1A4 1A5 2A1 2A2 2A3 2A4 2A5 GND 1B1 1B2 1B3 1B4 1B5 2B1 2B2 2B3 2B4 2B5 VCC 12 2 5 6 9 10 15 16 19 20 23 24 1OE 2OE 1A1 1A2 1A3 1A4 1A5 2A1 2A2 2A3 2A4 2A5 GND 1B1 1B2 1B3 1B4 1B5 2B1 2B2 2B3 2B4 2B5 VCC 12 2 5 6 9 10 15 16 19 20 23 24 C117 0.1uF DWG NO 1 509122-0001 Thursday, February 01, 2007 EMIF Muxing Sheet TMS320C6424 Evaluation Module 14 o f 30 Revision: A MEM.EM_D[15:8] 15,16 MEM.EM_D[7:0] 15,16 SPECTRUM DIGITAL INCORPORATED MEM.EM_D12 MEM.EM_D13 MEM.EM_D14 MEM.EM_D15 MEM.EM_D8 MEM.EM_D9 MEM.EM_D10 MEM.EM_D11 VCC_3V3 Size:B Date: C115 0.1uF MEM.EM_D7 MEM.EM_D6 MEM.EM_D1 MEM.EM_D0 MEM.EM_D5 MEM.EM_D4 MEM.EM_D3 MEM.EM_D2 Page Contents: Title: SN74CBTLV3384PW 1 13 3 4 7 8 11 14 17 18 21 22 U21 SN74CBTLV3384PW 1 13 3 4 7 8 11 14 17 18 21 22 U19 VCC_3V3 1 A B C D Spectrum Digital, Inc A-15 A B C 5 R101 NO-POP R100 10K VCC_3V3 6,26 EM_WAIT_BSYn 6,16,26 EM_OEn 14 NAND_CEn 14 SRAM_CEn R93 10K B.EM_A12 B.EM_A11 B.EM_A10 B.EM_A09 B.EM_A08 B.EM_A07 B.EM_A06 B.EM_A05 6,16,26 EM_WEn 6,16,26 EM_OEn 6,10,16,26 EM_A04 6,16,26 EM_A03 6,16,26 EM_A02_CLE 6,16,26 EM_A01_ALE 6,10,16,26 EM_A00 6,10,16,26 EM_BA1 16,20,26 16,20,26 16,20,26 16,20,26 16,20,26 16,20,26 16,20,26 16,20,26 4 R94 R75 R98 VCC_3V3 0 MEM.EM_A17 MEM.EM_A16 MEM.EM_A15 MEM.EM_A14 MEM.EM_A13 6,16,26 EM_A02_CLE 6,16,26 EM_A01_ALE 6,16,26 EM_WEn R97 10K VCC_3V3 C122 .1uF VCC_3V3 R96 10K VCC_3V3 VCC_3V3 0 NO-POP MEM.EM_A18 R95 0 D3 D6 D7 D8 E3 C5 C8 D4 C6 E4 E5 H8 K3 E6 E7 D5 C4 C7 C3 E8 F3 F4 F5 F6 G5 A2 B5 A6 H6 G2 H1 D3 E4 F4 F3 G4 G3 H5 H4 H3 H2 D4 C4 C3 B4 B3 A5 A4 A3 NC.D3 NC.D6 NC.D7 NC.D8 NC.E3 GND1 R/#B #RE #CE NC.E4 NC.E5 VCC1 GND2 NC.E6 NC.E7 CLE ALE #WE #WP NC.E8 NC.F3 NC.F4 NC.F5 NC.F6 U23 WE OE CE CE2 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 NC.11 NC.1 NC.6 NC.2 NC.3 NC.7 NC.8 NC.9 NC.10 NC.4 NC.5 E3 NC.G3 NC.F8 NC.F7 3 G3 F8 F7 NAND512W3A2BZA6E NC.J5 J5 NC.J3 J3 NC.H7 H7 NC.H6 H6 I/O7 J8 I/O6 K7 I/O5 J7 I/O4 K6 NC.H5 H5 NC.H3 H3 NC.G7 G7 VCC2 J6 GND3 K8 NC.G6 G6 NC.G5 G5 NC.G4 G4 I/O3 K5 I/O2 K4 I/O1 J4 I/O0 H4 PRE G8 R70 0 R99 MEM.EM_D8 MEM.EM_D9 MEM.EM_D10 MEM.EM_D11 MEM.EM_D12 MEM.EM_D13 MEM.EM_D14 MEM.EM_D15 B1 C1 C2 D2 E2 F2 F1 G1 A1 B2 MEM.EM_D0 MEM.EM_D1 MEM.EM_D2 MEM.EM_D3 MEM.EM_D4 MEM.EM_D5 MEM.EM_D6 MEM.EM_D7 B6 C5 C6 D5 E5 F5 F6 G6 IS62WV102416BLL-10MLI LB/UB DATA16 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 0.1uF 0.1uF A1 A2 B1 14,16 MEM.EM_A[18:13] U22 C119 C118 VCC_3V3 NC.A1 NC.A2 NC.B1 6,10,16,26 EM_BA0 3 NC.A9 NC.A10 NC.B9 NC.B10 A9 A10 B9 B10 4 D6 E1 VDD.1 VDD.2 GND.1 GND.2 NC.L1 NC.L2 NC.M1 NC.M2 L1 L2 M1 M2 D1 E6 NC.L9 NC.L10 NC.M9 NC.M10 A-16 L9 L10 M9 M10 D 5 VCC_3V3 NO-POP MEM.EM_D3 MEM.EM_D2 MEM.EM_D1 MEM.EM_D0 NO-POP MEM.EM_D7 MEM.EM_D6 MEM.EM_D5 MEM.EM_D4 2 .1uF C123 VCC_3V3 CE DON'T CARE DEVICE R69 0 R107 MEM.EM_D[15:8] 14,16 MEM.EM_D[7:0] 14,16 2 Date: Size:B DWG NO 1 509122-0001 NAND-Flash/SRAM Sheet TMS320C6424 Evaluation Module 15 o f 30 Revision: B 8 BIT INTERFACE IS61WV20488BLL-25MI IS61WV20488BLL-25MLI SPECTRUM DIGITAL INCORPORATED Thursday, February 01, 2007 Page Contents: Title: 16 BIT INTERFACE IS61WV102416BLL-10MI IS61WV102416BLL-10MLI Set this up to run 8 or 16 bit 1 A B C D Spectrum Digital, Inc C6424 EVM Technical Reference A B C D 5 14 FLASH_CEn R103 10K 14,15 MEM.EM_A[20:13] 5 R71 NO-POP R105 10K VCC_3V3 R153 R154 4 R310 VCC_3V3 5,27 FSX0 5,24,27 DR0 R106 NO-POP R104 10K VCC_3V3 3,18,24,26,29 SYS_RESETn 6,15,26 EM_OEn 6,15,26 EM_WEn 14 MEM.EM_A21 6,10,15,26 EM_BA0 6,10,15,26 EM_BA1 6,10,15,26 EM_A00 6,15,26 EM_A01_ALE 6,15,26 EM_A02_CLE 6,15,26 EM_A03 6,10,15,26 EM_A04 15,20,26 B.EM_A05 15,20,26 B.EM_A06 15,20,26 B.EM_A07 15,20,26 B.EM_A08 15,20,26 B.EM_A09 15,20,26 B.EM_A10 15,20,26 B.EM_A11 15,20,26 B.EM_A12 4 FSX0 D R0 0.1uF C126 VCC_3V3 R21 10K VCC_3V3 B4 B5 F2 G2 A5 F7 5,11,12,24,27 I2C_CLK 5,11,12,24,27 I2C_DATA 10K 0 NO-POP MEM.EM_A13 MEM.EM_A14 MEM.EM_A15 MEM.EM_A16 MEM.EM_A17 MEM.EM_A18 MEM.EM_A19 MEM.EM_A20 E2 D2 C2 A2 B2 D3 C3 A3 B6 A6 C6 D6 B7 A7 C7 D7 E7 B3 C4 D5 D4 C5 B8 C8 F8 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 VSS.1 VSS.2 VSS.3 VIO.1 VIO.2 VCC RY/BY DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15/A-1 CS SO WP GND U65 VCC HOLD SCK SI 8 7 6 5 6 5 8 A0 A1 A2 WP VSS 3 CAT24C256 SCL SDA VCC U25 SOCKETED_SPI_EEPROM 1 2 3 4 3 S29GL256N11FFI010 WP/ACC RESET CE OE WE BYTE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 NC/A24 U24 1 2 3 7 4 A1 B1 C1 D1 E1 G1 H1 A8 G8 H8 H2 H7 E8 F1 D8 G5 A4 E3 H3 E4 H4 H5 E5 H6 E6 F3 G3 F4 G4 F5 G6 F6 G7 CLKX0 DX0 0.1uF C366 Internal pull-downs CLKX0 DX0 10K R309 VCC_3V3 5,24,27 5,24,27 C183 0.1uF C125 0.1uF VCC_3V3 MEM.EM_D0 MEM.EM_D1 MEM.EM_D2 MEM.EM_D3 MEM.EM_D4 MEM.EM_D5 MEM.EM_D6 MEM.EM_D7 MEM.EM_D8 MEM.EM_D9 MEM.EM_D10 MEM.EM_D11 MEM.EM_D12 MEM.EM_D13 MEM.EM_D14 R72 0 MEM.EM_D15 R73 NO-POP EM_BA0 2 0.1uF C124 VCC_3V3 6,10,15,26 2 Date: Size: B 1 DWG NO 1 509122-0001 NOR-Flash/EEPROM Sheet TMS320C6424 Evaluation Module SPECTRUM DIGITAL INCORPORATED Thursday, February 01, 2007 Page Contents: Title: R102 10K VCC_3V3 MEM.EM_D[15:8] 14,15 MEM.EM_D[7:0] 14,15 16 o f 30 Revision: A A B C D Spectrum Digital, Inc A-17 A B C D VCC_3V3 27 ENET_ENABLEn 5 R246 10K R326 NO-POP 3 RESET_OUT 6,12,18 RMII_SELECT R22 2 1 4 NO-POP SN74LVC1G32 U71 C196 0.1uF VCC_3V3 5 4 4 4 SN74LVC1G32 U14 26 B_RMRXD0 26 B_RMRXD1 26 B_RMCRSDV 26 B_RMRXER 26 B_RMREFCLK 26 B_RMTXD0 26 B_RMTXD1 26 B_RMTXEN 2 1 VCC_3V3 5 3 A-18 3 5 C175 0.1uF 3 B.TXCLK B.TXD0 B.TXD1 B.TXEN 21,27 21,27 21,27 21,27 21,27 B.TXD2 21,27 B.TXD3 21,27 B.RXCLK 21,27 B.COL 21,27 B.C RS 21,27 B.RXD2 21,27 B.RXD3 21,27 B.MDC 21,27 B.MDIO 21,27 21,27 21,27 21,27 3 B.RXD0 B.RXD1 B.RXDV B.RXER 1OE 2OE 1A1 1A2 1A3 1A4 1A5 2A1 2A2 2A3 2A4 2A5 GND 1B1 1B2 1B3 1B4 1B5 2B1 2B2 2B3 2B4 2B5 VCC 12 2 5 6 9 10 15 16 19 20 23 24 15 1 3 6 10 13 2 5 11 14 15 1 3 6 10 13 2 5 11 14 GND 1A 2A 3A 4A VCC 8 4 7 9 12 16 1A 2A 3A 4A VCC 4 7 9 12 16 OE S GND 8 74CBTLV3257PWR 1B2 2B2 3B2 4B2 1B1 2B1 3B1 4B1 U28 74CBTLV3257PWR OE S 1B2 2B2 3B2 4B2 1B1 2B1 3B1 4B1 U26 SN74CBTLV3384PW 1 13 3 4 7 8 11 14 17 18 21 22 U27 2 VCC_3V3 VCC_3V3 VCC_3V3 2 R24 NO-POP 1 509122-0001 Thursday, February 01, 2007 DWG NO Date: ENET Muxing Size: B Sheet TMS320C6424 Evaluation Module SPECTRUM DIGITAL INCORPORATED Page Contents: Title: EPHY.RXD0 18 EPHY.RXD1 18 EPHY.RX_DV 18 EPHY.RX_ER 18 C129 0.1uF EPHY.TXCLK 18 EPHY.TXD0 18 EPHY.TXD1 18 EPHY.TX_EN 18 C127 0.1uF EPHY.TXD2 18 EPHY.TXD3 18 EPHY.RX_CLK 18 EPHY.COL 18 EPHY.CRS 18 EPHY.RXD2 18 EPHY.RXD3 18 EPHY.MDC 18 EPHY.MDIO 18 C128 0.1uF 1 17 o f 30 Revision: A A B C D Spectrum Digital, Inc C6424 EVM Technical Reference A B C EPHY.TXCLK EPHY.TXD0 EPHY.TXD1 EPHY.TXD2 EPHY.TXD3 6,12,17 RMII_SELECT 5 1 2 3 4 5 6 7 8 R191 NO-POP VCC_3V3 RMII_SELECT 3,16,24,26,29 SYS_RESETn RN32 U70 SN74LVC1G126DCKR 4 .1uF RPACK8-10 16 15 14 13 12 11 10 9 10K 10K NO-POP R123 R233 R126 2 1 4 C193 .1uF 17 EPHY.MDC U68 SN74AHC1G14DCKRG4 VCC_3V3 1.5K R133 R192 10K 4 VCC_3V3 R23 10K TP12 TP-30 R132 R122 R234 R120 R118 22 10 16 14 15 17 18 19 20 R136 NO-POP 30 48 25 1 2 10 21 22 6 5 4 3 9 11 4.7uF + C133 LED0/TEST REXT NC1 NC2 FXSD/FXEN RX- RX+ TX- TX+ PD# RESET# INT#/PHYAD0 MDIO MDC RX_CLK 3 KS8001L XO XI 45 46 29 28 R128 330 R127 330 27 R124 26 VCC L11 L9 GND OUT 25MHz EN U72 R131 C137 4.7uF C132 4.7uF PHY_1V8 2 1 6.65K C141 4.7uF C136 0.1uF C131 0.1uF 37 42 43 34 32 33 40 41 C140 0.1uF VDD_1V8PLL VDD_3V3A VDD_1V8RX 3 COL/RMII CRS/RMII_BTB LED1/SPD100 RXD0/PHYAD4 RXD1/PHYAD3 LED2/DUPLEX RXD2/PHYAD2 RXD3/PHYAD1 LED3/NWAYEN RX_DV/CRSDV/PCS_LPBK RX_ER/ISO TX_EN TX_ER TX_CLK/REF_CLK TXD0 TXD1 TXD2 TXD3 U30 C130 0.1uF VCC_3V3 PH YAD4 PH YAD3 PH YAD2 PH YAD1 10K NO-POP NO-POP NO-POP NO-POP C139 4.7uF R111 R116 C138 0.1uF VCC_3V3 R135 NO-POP 10K 10K R121 R119 PH YAD4 PH YAD3 PH YAD2 PH YAD1 VCC_3V3 17 EPHY.RX_CLK R112 NO-POP R113 NO-POP 10K R157 10K 10K R156 R159 10K VCC_3V3 PHY_1V8 7 24 VDDIO1 VDDIO2 4 13 VDDC1 R155 C194 17 EPHY.MDIO 17 EPHY.COL 17 EPHY.CRS 17 EPHY.RXD0 17 EPHY.RXD1 17 EPHY.RXD2 17 EPHY.RXD3 17 EPHY.RX_DV 17 EPHY.RX_ER RMII_SELECT 2 VCC_3V3 17 EPHY.TX_EN 17 17 17 17 17 5 3 1 47 VDDPLL D 5 3 31 38 VDDRX VDDRCV GND1 GND2 GND3 GND4 GND5 GND6 GND7 8 12 23 35 36 39 44 L55 BLM21PG221SN1D 2 GND_E_ENET 22 BLM21PG221SN1D BLM21PG221SN1D L56 BLM21PG221SN1D 3 R249 4 .1uF C199 VCC_3V3 10K R115 49.9 R110 49.9 VCC_3V3 EPHY.LED2 EPHY.LED0 NO_POP R114 R109 49.9 2 VDD_1V8RX VDD_1V8PLL R117 49.9 EPHY.LED2 EPHY.LED0 Date: Size:B P3 L8 VCC_3V3 NO-POP R134 NO-POP R230 1 509122-0001 Thursday, February 01, 2007 DWG NO ENET Sheet TMS320C6424 Evaluation Module 18 o f 30 Revision: A BLM21PG221SN1D R129 NO-POP R229 NO-POP 0.1uF C143 VDD_3V3A GND_E_ENET VDD_3V3A RJ45 HALO HFJ11-2450E-L21 VCC_3V3 RXD+ RXD-CT RXD- TXD+ TXD-CT TXD- NC1 GND LED2LED2+ LED1LED1+ VCC_3V3 3 5 6 1 4 2 7 8 12 11 10 9 SILKSCREEN: ETHERNET SPECTRUM DIGITAL INCORPORATED NO-POP R130 NO-POP R231 Page Contents: Title: NO-POP R137 NO-POP R232 VCC_3V3 GND_E_ENET 1000pF 2kV C142 VCC_3V3 0.1uF C134 VDD_3V3A 1 S1 S0 13 14 5 A B C D Spectrum Digital, Inc A-19 A B C 5 27 RS232_ENABLEn R187 10K R144 NO-POP VCC_3V3 VCC_3V3 R147 10K R146 NO-POP 4 3 6 10 13 5,27 TOUT1L 5,27 TINP1L 15 1 2 5 11 14 UTXD0 URXD0 5,27 5,27 4 GND 1A 2A 3A 4A VCC 8 4 7 9 12 16 74CBTLV3257PWR OE S 1B2 2B2 3B2 4B2 1B1 2B1 3B1 4B1 U33 C152 .1uF C159 1uF + 3 R145 R257 VCC_3V3 C153 1uF UART_TXD UART_RXD VCC_3V3 3 0 33 C154 47uF 14 4 2 1 9 11 15 U34 V- V+ C2- C2+ INVALID R_IN T_OUT FORCEON FORCEOFF MAX3221CPWRG4 GND C1- C1+ EN R_OUT T_IN VCC 16 7 3 6 5 10 8 13 12 C161 1uF C160 1uF 2 GND_E_RS232 C157 10pF C162 1uF L13 1uH L12 1uH R143 10K VCC_3V3 GND_E_RS232 C155 10pF R142 10K VCC_3V3 2 C156 10pF L57 DWG NO 1 509122-0001 Thursday, February 01, 2007 RS232 Sheet TMS320C6424 Evaluation Module Size: B Date: GND_E_CAN P8 DB9-MALE GND_E_RS232 GND_E_RS232 5 9 4 8 3 7 2 6 1 SPECTRUM DIGITAL INCORPORATED GND_E_RS232 Page Contents: Title: BLM21PG221SN1D L58 BLM21PG221SN1D GND_E_RS232 C158 10pF GND_E_RS232 1 SILKSCREEN: UART B A-20 A D 5 19 o f 30 Revision: A A B C D Spectrum Digital, Inc C6424 EVM Technical Reference A B C D 3,27 RESET_OUTn C361 5.6pF 0 RN5 R337 2 1 5 1 2 3 4 5 6 7 8 22 4 0.1uF R172 C144 NO-POP 0 1B2 2B2 3B2 4B2 5B2 6B2 7B2 8B2 9B2 10B2 11B2 12B2 1B1 2B1 3B1 4B1 5B1 6B1 7B1 8B1 9B1 10B1 11B1 12B1 U51 PCI4.1V SINGLE GATE 53 51 48 46 44 42 40 37 35 33 31 29 54 52 50 47 45 43 41 39 36 34 32 30 R171 PCI_P_PINTAn RPACK8-33 16 15 14 13 12 11 10 9 R333 PCI_P_AD31 PCI_P_AD30 PCI_P_AD29 PCI_P_AD28 PCI_P_AD27 PCI_P_AD26 PCI_P_AD25 PCI_P_AD24 PCI4.1V SN74LVC1G08 U40 VCC_3V3 R181 14,26 B.EM_A20 22 PCI_P_PINTAn 14,26 B.EM_A18 B.EM_A16 B.EM_A19 B.EM_A17 B.EM_A15 B.EM_A14 B.EM_A13 B.EM_A11 B.EM_A12 22 PCI_P_RSTn 14,26 14,26 14,26 14,26 14,26 14,26 15,16,26 15,16,26 23,28 VLYNQ_CLOCK 22 PCI_P_C/BEn3 21,22 PCI_P_AD[31:0] 22 PCI_P_CLK 22 PCI_P_GNTn 22 PCI_P_REQn 5 3 4 17 VCC.1 GND.4 GND.3 GND.2 GND.1 0 4 S 3 5 7 10 12 14 16 20 22 24 26 28 55 56 2 4 6 9 11 13 15 18 21 23 25 27 1 R158 VCC_3V3 S OE 1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2 U12 GND 4A 3A 2A 1A VCC SN74CBT3257PW 1 15 2 3 5 6 11 10 14 13 21 PCI4.1V 16 8 12 9 7 4 PCICLK 6 EM_A16_PGNTn 6 EM_A19_PREQn 6 EM_A17_AD31 6 AD30 6 EM_A15_AD29 6 AD28 6 EM_A14_AD27 6 AD26 6 EM_A13_AD25 6 EM_A11_AD24 6 EM_A12_PCBE3 6 21,22 PCI_P_AD[31:0] 3 0.1uF C178 PCI4.1V 3 R170 10K VCC_3V3 PCI_S_RSTn PCI_S_PINTAn C364 5.6pF 23,28 VLYNQ_TXD0 23,28 VLYNQ_RXD3 23,28 VLYNQ_RXD2 23,28 VLYNQ_RXD0 23,28 VLYNQ_RXD1 23,28 VLYNQ_SCRUN 15,16,26 B.EM_A05 15,16,26 B.EM_A06 15,16,26 B.EM_A08 15,16,26 B.EM_A07 15,16,26 B.EM_A10 15,16,26 B.EM_A09 0 PCI_S_CLKOUT0 PCI_S_GNTn PCI_S_REQn0 PCI_S_AD31 PCI_S_AD30 PCI_S_AD29 PCI_S_AD28 PCI_S_AD27 PCI_S_AD26 PCI_S_AD25 PCI_S_AD24 PCI_S_C/BEn3 PCI_DETECTn 0.1uF C184 SN74CBT16292DGGR NC.1 NC.2 NC.3 NC.4 NC.5 NC.6 NC.7 NC.8 NC.9 NC.10 NC.11 NC.12 NC.13 NC.14 1A 2A 3A 4A 5A 6A 7A 8A 9A 10A 11A 12A PCI_DETECTn 49 38 19 8 21 2 1 NO-POP C363 B B B B B B 16 15 14 13 12 11 R177 C120 EM_A18_PRSTn 6 U36 SN74LVC1G07 4 0.1uF VCC_3V3 C362 NO-POP A A A A A A NO-POP R339 1 2 3 4 5 6 0.1uF C186 0 7 8 RN3H 1B2 2B2 3B2 4B2 5B2 6B2 7B2 8B2 9B2 10B2 11B2 12B2 1B1 2B1 3B1 4B1 5B1 6B1 7B1 8B1 9B1 10B1 11B1 12B1 U52 RN3G 53 51 48 46 44 42 40 37 35 33 31 29 54 52 50 47 45 43 41 39 36 34 32 30 2 2 RESETn 3,4,26 R307 R308 R329 R347 R331 R332 RPACK8-22 RPACK8-22 RPACK8-22 RPACK8-22 RPACK8-22 RPACK8-22 EM_A20_PINTAn 6 RN3A RN3B RN3C RN3D RN3E RN3F 22 0 0 0 0 0 22 PCI_P_IDSEL PCI_P_AD16 PCI_P_AD17 PCI_P_AD18 PCI_P_AD19 PCI_P_AD20 PCI_P_AD21 PCI_P_AD22 PCI_P_AD23 22 PCI_P_IRDYn 22 PCI_P_FRAMEn 22 PCI_P_C/BEn2 R338 NO-POP 5 3 17 VCC.1 GND.4 GND.3 GND.2 GND.1 A B A B S 1 3 5 7 10 12 14 16 20 22 24 26 28 55 56 2 4 6 9 11 13 15 18 21 23 25 27 PCI_S_AD16 PCI_S_AD17 PCI_S_AD18 PCI_S_AD19 PCI_S_AD20 PCI_S_AD21 PCI_S_AD22 PCI_S_AD23 1 509122-0001 Thursday, February 01, 2007 DWG NO Date: PCI-Switches Size: B Sheet TMS320C6424 Evaluation Module Page Contents: Title: 9 RPACK8-22 20 o f PIDRDYn 6 PFRAMEn 6 PCBE2n 6 AD16 6 AD17 6 AD18 6 EM_A05_AD19 6 EM_A06_AD20 6 EM_A08_AD21 6 EM_A07_AD22 6 EM_A10_AD23 6 EM_A09_PIDSEL 6 PCI_DETECTn 21 PCI_DETECTn 1 SPECTRUM DIGITAL INCORPORATED SN74CBT16292DGGR NC.1 NC.2 NC.3 NC.4 NC.5 NC.6 NC.7 NC.8 NC.9 NC.10 NC.11 NC.12 NC.13 NC.14 1A 2A 3A 4A 5A 6A 7A 8A 9A 10A 11A 12A 10 RPACK8-22 49 38 19 8 5 30 Revision: A A B C D Spectrum Digital, Inc A-21 A B C D 5 22 PCI_PLUGn 17,27 B.TXEN 17,27 B.TXCLK 17,27 B.RXDV 17,27 B.TXD1 17,27 B.TXD0 17,27 B.TXD3 17,27 B.TXD2 17,27 B.CRS 17,27 B.COL 23,28 VLYNQ_TXD3 23,28 VLYNQ_TXD2 23,28 VLYNQ_TXD1 22 PCI_P_C/BEn1 22 PCI_P_PAR 22 PCI_P_SERRn 22 PCI_P_STOPn 22 PCI_P_PERRn 22 PCI_P_DEVSELn 22 PCI_P_TRDYn 5 0 0 22 PCI_P_AD11 PCI_P_AD12 PCI_P_AD13 PCI_P_AD14 PCI_P_AD15 VCC_5V R68 0 R315 C365 5.6pF 2 1 1.5K 1 PCI4.1V 4 C121 0.1uF 1B2 2B2 3B2 4B2 5B2 6B2 7B2 8B2 9B2 10B2 11B2 12B2 1B1 2B1 3B1 4B1 5B1 6B1 7B1 8B1 9B1 10B1 11B1 12B1 4 0.1uF C174 4 1A 2A 3A 4A 5A 6A 7A 8A 9A 10A 11A 12A S 3 5 7 10 12 14 16 20 22 24 26 28 55 56 2 4 6 9 11 13 15 18 21 23 25 27 1 20 3 TXEN TXCLK RXDV TXD1 TXD0 TXD3 TXD2 CRS COL PPERn PDEVSELn PTRDYn 6 6 6 6 6 6 6 6 6 6 6 6 3 3 The PCLK signal trace length must be 2.5" +/- 0.1". The PCI 33 Mhz Signals must be shorter than 1.5" PCI4.1V PCIEN PCI_S_AD11 PCI_S_AD12 PCI_S_AD13 PCI_S_AD14 PCI_S_AD15 PCI_S_C/BEn1 PCI_S_PAR PCI_S_SERRn PCI_S_STOPn PCI_DETECTn PCI4.1V SN74CBT16292DGGR NC.1 NC.2 NC.3 NC.4 NC.5 NC.6 NC.7 NC.8 NC.9 NC.10 NC.11 NC.12 NC.13 NC.14 PCI_DETECTn 20 U39 SN74AHC1G14DCKRG4 VCC_3V3 PCI_DETECTn 53 51 48 46 44 42 40 37 35 33 31 29 54 52 50 47 45 43 41 39 36 34 32 30 U53 LM4040DCIM3-4.1 D5 R334 R335 R336 2 5 3 17 VCC.1 GND.4 GND.3 GND.2 GND.1 49 38 19 8 2 PCI4.1V 22 PCI_P_C/BEn0 17,27 B.RXER 17,27 B.RXD0 17,27 B.RXCLK 17,27 B.RXD2 17,27 B.RXD1 17,27 B.RXD3 17,27 B.MDC 27 B_GP[3] 17,27 B.MDIO 27 B_GP[2] 27 B_GP[1] 27 B_GP[0] PCI_P_AD7 PCI_P_AD6 PCI_P_AD5 PCI_P_AD4 PCI_P_AD3 PCI_P_AD2 PCI_P_AD1 PCI_P_AD0 PCI_P_AD10 PCI_P_AD9 PCI_P_AD8 0.1uF C176 2 53 51 48 46 44 42 40 37 35 33 31 29 54 52 50 47 45 43 41 39 36 34 32 30 1B2 2B2 3B2 4B2 5B2 6B2 7B2 8B2 9B2 10B2 11B2 12B2 1B1 2B1 3B1 4B1 5B1 6B1 7B1 8B1 9B1 10B1 11B1 12B1 U54 17 VCC.1 GND.4 GND.3 GND.2 GND.1 A-22 PCI_S_AD10 PCI_S_AD9 PCI_S_AD8 PCI_S_C/BEn0 PCI_S_AD7 PCI_S_AD6 PCI_S_AD5 PCI_S_AD4 PCI_S_AD3 PCI_S_AD2 PCI_S_AD1 PCI_S_AD0 2 4 6 9 11 13 15 18 21 23 25 27 3 5 7 10 12 14 16 20 22 24 26 28 55 56 DWG NO 1 509122-0001 Thursday, February 01, 2007 PCI-Muxing Sheet TMS320C6424 Evaluation Module 21 o f RXER 6 RXD0 6 RXCLK 6 RXD2 6 RXD1 6 RXD3 6 MDC 6 AD4_GP[3] 5 MDIO 6 AD2_GP[2] 5 AD1_GP[1] 5 AD0_GP[0] 5 SPECTRUM DIGITAL INCORPORATED Size: B Date: 1 20 PCI_DETECTn PCI_DETECTn 1 SN74CBT16292DGGR NC.1 NC.2 NC.3 NC.4 NC.5 NC.6 NC.7 NC.8 NC.9 NC.10 NC.11 NC.12 NC.13 NC.14 1A 2A 3A 4A 5A 6A 7A 8A 9A 10A 11A 12A S Page Contents: Title: 49 38 19 8 20,22 PCI_P_AD[31:0] 30 Revision: A A B C D Spectrum Digital, Inc C6424 EVM Technical Reference A B C D 0 R180 20 PCI_P_IRDYn 20 PCI_P_C/BEn2 PCI_P_AD17 PCI_P_AD21 PCI_P_AD19 PCI_P_AD23 20 PCI_P_C/BEn3 PCI_P_AD27 PCI_P_AD25 PCI_P_AD31 PCI_P_AD29 20 PCI_P_REQn 20 PCI_P_CLK 0 R179 PCIVCC_3V3 10K 5 5 PCI_P_AD1 PCI_P_AD5 PCI_P_AD3 PCI_P_AD8 PCI_P_AD7 PCI_P_AD12 PCI_P_AD10 PCI_P_AD14 21 PCI_P_C/BEn1 21 PCI_P_PERRn 21 PCI_P_SERRn 21 PCI_P_DEVSELn R163 VCC_3V3 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 P4 TRST +12V TMS TDI +5V INTA INTC +5V Rsvd.0 +V I/O Rsvd.1 Key.1 Key.2 3.3Vaux RST +V I/O GNT GND PME AD30 +3.3V AD28 AD26 GND AD24 IDSEL +3.3V AD22 AD20 GND AD18 AD16 +3.3V FRAME GND TRDY GND STOP +3.3V SDONE SBO GND PAR AD15 +3.3V AD13 AD11 GND AD9 Key.3 Key.4 C/BE0 +3.3V AD6 AD4 GND AD2 AD0 +V I/O REQ64 +5V +5V 0 PCI Connector R178 -12V TCK GND TDO +5V +5V INTB INTD PRSNT1 Rsvd.2 PRSNT2 Key.5 Key.6 Rsvd.3 GND CLK GND REQ +V I/O AD31 AD29 GND AD27 AD25 +3.3V C/BE3 AD23 GND AD21 AD19 +3.3V AD17 C/BE2 GND IRDY +3.3V DEVSEL GND LOCK PERR +3.3V SERR +3.3V C/BE1 AD14 GND AD12 AD10 M66EN Key.7 Key.8 AD8 AD7 +3.3V AD5 AD3 GND AD1 +V I/O ACK64 +5V +5V NO-POP PCI_VIO VCC_5V R164 4 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 4 PCI_VIO PCI_PLUGn 21 PCIVCC_3V3 PCI_P_AD2 PCI_P_AD0 PCI_P_AD6 PCI_P_AD4 PCI_P_C/BEn0 21 PCI_P_AD9 PCI_P_AD13 PCI_P_AD11 PCI_P_AD15 PCI_P_PAR 21 PCI_P_STOPn 21 PCI_P_TRDYn 21 PCI_P_FRAMEn 20 PCI_P_AD18 PCI_P_AD16 PCI_P_AD22 PCI_P_AD20 PCI_P_IDSEL 20 PCI_P_AD24 PCI_P_AD28 PCI_P_AD26 PCI_P_AD30 PCI_P_GNTn 20 PCI_P_RSTn 20 PCI_P_PINTAn 20 VCC_5V 3 PCI_P_AD[31:0] 20,21 3 + C204 33uF VCC_5V A21,A27,B25,B31 C180 0.1uF PCIVCC_3V3 A10,A16,B19 C172 0.1uF PCI_VIO 0.1uF C203 C181 0.1uF A33,A39,B41,B43 C179 0.1uF A59,B59 2 2 C182 0.1uF Date: 1 509122-0001 Thursday, February 01, 2007 PCI-Connector DWG NO Size: B Sheet TMS320C6424 Evaluation Module SPECTRUM DIGITAL INCORPORATED Page Contents: Title: 1 22 o f 30 Revision: A A B C D Spectrum Digital, Inc A-23 A B C D 125 126 127 128 9 14 20 23 25 27 32 33 34 35 37 41 45 42 44 46 48 50 52 54 56 58 60 62 64 66 68 69 72 74 76 78 79 81 83 85 87 90 91 92 94 95 96 99 101 102 110 114 119 17 39 123 15 55 57 107 106 108 105 13 12 10 11 8 122 120 118 117 VLYNQ 5 mPCI_VLYNQ_CONNECTOR HOLE1 HOLE2 GND_PAD1 GND_PAD2 GND_9 GND_14 GND_20 GND_23 GND_25 GND_27 GND_32 GND_33 GND_34 GND_35 GND_37 GND_41 GND_45 GND_42 GND_44 GND_46 GND_48 GND_50 GND_52 GND_54 GND_56 GND_58 GND_60 GND_62 GND_64 GND_66 GND_68 GND_69 GND_72 GND_74 GND_76 GND_78 GND_79 GND_81 GND_83 GND_85 GND_87 GND_90 GND_91 GND_92 GND_94 GND_95 GND_96 GND_99 GND_101 GND_102 GND_110 GND_114 GND_119 PIN17 PIN39 PIN123 PIN15 PIN55 PIN57 PIN107 PIN106 PIN108 PIN105 PIN13 PIN12 PIN10 PIN11 PIN8 PIN122 PIN120 PIN118 PIN117 VBAT 5V_97 5V_103 PIN2 VLYNQ_TARGET_TXD2 VLYNQ_TARGET_TXD3 VLYNQ_TARGET_RXD2 VLYNQ_TARGET_RXD3 PIN80 PIN82 PIN84 PIN85 PIN47 PIN49 PIN51 PIN53 PIN112 PIN121 PIN98 PIN100 PIN93 PIN124 VLYNQ_TARGET_RXD0 VLYNQ_TARGET_RXD1 VLYNQ_TARGET_TXD0 VLYNQ_TARGET_TXD1 VLYNQ_CLK VLYNQ_SCRUN PIN71 PIN73 PIN75 PIN77 PIN113 PIN116 PIN104 PIN109 PIN29 PIN38 PIN30 PIN3 PIN5 VLYNQ_RESETn PIN4 PIN6 PIN7 PIN18 PIN115 D1_8V D3_3V_19 D3_3V_28 D3_3V_31 D3_3V_40 D3_3V_63 D3_3V_70 D3_3V_88 D3_3V_89 mPCI_VLYNQ_CONNECTOR Power Supplies J20 59 61 65 67 80 82 84 86 47 49 51 53 112 121 98 100 93 124 36 43 21 22 16 24 71 73 75 77 113 116 104 109 29 38 30 3 5 26 4 6 7 18 115 111 0.33uF 470pF 22uF C378 22uF C372 470pF C394 470pF C380 VLYNQ_RXD2 VLYNQ_RXD3 VLYNQ_TXD2 VLYNQ_TXD3 20,28 20,28 21,28 21,28 VLYNQ_TXD0 20,28 VLYNQ_TXD1 21,28 VLYNQ_RXD0 20,28 VLYNQ_RXD1 20,28 VLYNQ_CLOCK 20,28 VLYNQ_SCRUN 20,28 mPCI_VLYNQ_RSTn C385 C393 0.33uF 470pF 19 28 31 40 63 70 88 89 C392 C379 97 103 4 C377 C376 0.33uF 0.33uF 470pF 470pF C371 C405 VCC_5V 1 2 4 0 .33uF C386 0 .33uF C381 3 3 22uF C375 0.33uF C383 R419 NO-POP R394 1K VCC_3V3 4.7uF C384 VCC_1V8 0.33uF C374 VCC_1V8 470pF C382 470pF C373 VCC_3V3 4 2 U67 SN74LVC1G06DBVRG4 C171 0.1uF 2 VCC_3V3 5 A-24 3 5 2 1 Date: Size: B DWG NO 1 509122-0001 mPCI VLYNQ CONNECTOR Sheet TMS320C6424 Evaluation Module SPECTRUM DIGITAL INCORPORATED Thursday, February 01, 2007 Page Contents: Title: VLYNQ_RESET 11,28 1 23 o f 30 Revision: A A B C D Spectrum Digital, Inc C6424 EVM Technical Reference A B C D CLKX1 CLKR1 FSX1 DX1 DR1 <--> <--> <--> <--> <--> <--> FSR1 12 McBSP_ONn 12 McASP_ONn 12 SPDIF_ONn 5,27 5 1OE 2OE 1A1 1A2 1A3 1A4 1A5 2A1 2A2 2A3 2A4 2A5 U75 GND 1B1 1B2 1B3 1B4 1B5 2B1 2B2 2B3 2B4 2B5 VCC 24 12 2 5 6 9 10 15 16 19 20 23 1OE 2OE 3OE 4OE 1A 2A 3A 4A GND 1B 2B 3B 4B VCC SN74CBTLV3125PWRG4 1 4 10 13 2 5 9 12 U76 SN74CBTLV3384PW 1 13 3 4 7 8 11 14 17 18 21 22 7 3 6 8 11 14 VCC_3V3 0.1uF C207 0.1uF C246 VCC_3V3 5.6K R205 R206 R207 R208 GND_AIC 4 12 SPDIF_ONn B_FSR1_AFSR0 C236 C224 220pF 0.1uF R20 10K 10 10 10 10 10 10 R209 R182 VCC_3V3 R216 R213 R214 R215 R218 R219 0.1uF C235 10K NO-POP NO-POP 10K 0.1uF C244 C241 0.1uF 0.1uF C237 27 AUDIO_CLK ALT_AIC33_CLK R202 330 0.1uF C238 C234 220pF GND_AIC R194 5.6K GND_AIC R196 5.6K 5.6K R193 B_CLKX1_ACLKX0 B_CLKR1_ACLKR0 B_FSX1_AFSX0 B_DX1_AXR0[0] B_DR1_AXR0[1] R201 10K R198 330 GND_AIC 0.1uF C242 GND_AIC L20 R195 BLM21PG221SN1D GND_AIC VCC_3V3 R197 47K GND_AIC 4 2 1 3 4 2 1 3 3,16,18,26,29 SYS_RESETn AFSR0 AXR0[1] ACLKR0 ACLKX0 AXR0[0] AFSX0 12 McBSP_ONn 12 McASP_ONn 5,16,27 DR0 5,16,27 DX0 5,16,27 CLKX0 5,27 5,27 5,27 5,27 5,27 DR0 DX0 CLKX0 CLKX1 FSR1 DX1 220pF P11 Line In Mic In C239 SILKSCREEN: MIC SILKSCREEN: LINE IN P10 4 2 1 3 L18 R221 10K R200 R199 4 U43 33 3 PLACE THIS GATE NEAR DC_P2 C191 0.1uF + SCL SDA GPIO1 GPIO2 LEFT_LO+ LEFT_LORIGHT_LO+ RIGHT_LO- MONO_LO+ MONO_LO- HPLOUT HPLCOM DRVSS.1 DRVSS.2 HPRCOM HPROUT DRVDD.1 DRVDD.2 AVDD_ADC AVSS_ADC.1 AVSS_ADC.2 AVDD_DAC AVSS_DAC.1 AVSS_DAC.2 10uF C221 SPIF_OUT 25 TVL320AIC33IZQE BCLK WCLK DIN DOUT SELECT MCLK MFP0 MFP1 MPF2 MFP3 RESET MICBIAS MIC3R MIC3L MICDET LINE2L+ LINE2LLINE2R+ LINE2R- LINE1L+ LINE1LLINE1R+ LINE1R- R356 SN74LVC1G32 U62 R222 10K G9 F9 E9 F8 E8 G8 B8 B9 A8 A9 H8 A2 A1 B3 B2 A4 B5 B4 A3 A6 A5 B7 B6 0.1uF 0.1uF DVDD IOVDD DVSS C220 C219 H9 C9 D9 BLM21PG221SN1D VCC_3V3 VCC_3V3 TP15 TP-30 TP16 TP-30 NO-POP 10 0 0 C225 0.1uF 5 3 C8 D8 J9 J8 J4 J5 J6 J7 J2 J3 D1 E1 E2 F2 F1 G1 C1 H1 B1 C2 D2 J1 G2 H2 0.1uF C222 0.1uF 0.1uF L16 2 GND_AIC BLM41P750SPT C247 TP18 TP-30 Date: Size: B 0.1uF R211 20K GND_AIC GND_AIC R210 20K GND_AIC L19 1 509122-0001 Thursday, February 01, 2007 DWG NO AIC33 SILKSCREEN: HP OUT P13 24 o f 30 Revision: A SILKSCREEN: LINE OUT Line Out 3 1 2 4 Sheet TMS320C6424 Evaluation Module P12 0.1uF C231 VCC_3V3 Headphone Out 3 1 2 4 SPECTRUM DIGITAL INCORPORATED I2C_CLK 5,11,12,16,27 I2C_DATA 5,11,12,16,27 TP17 TP-30 BLM21PG221SN1D BLM21PG221SN1D R212 20K L24 L23 R204 20K GND_AIC GND_AIC R203 20K BLM21PG221SN1D GND_AIC C229 BLM21PG221SN1D 1 BLM21PG221SN1D 10uF C230 + GND_AIC 0.1uF C228 Page Contents: Title: 10UF,6.3V 10UF,6.3V L22 33uF,6.3V C245 C243 C240 L21 0.1uF 0.1uF 33uF,6.3V C227 C226 GND_AIC GND_AIC Isolate analog and digital GNDs at single location in the ground plane R217 20K GND_AIC C233 C232 VCC_1V8 0.1uF C223 2 + + + + 5 A B C D Spectrum Digital, Inc A-25 A B C 5 24 SPIF_OUT 4 74LVC1G125DCKRG4 2 U49 74LVC1G125DCKRG4 2 1 5 3 4 R228 4 R226 VCC_3V3 5 3 U46 VCC_3V3 1 4 0 0 0.1uF C252 0.1uF C249 R224 3 0.1uF C253 VCC_3V3 0.1uF C250 3 3 1 2 IN GND VCC P14 100 R225 TOTX141P 220 J10 1 SILKSCREEN: SPDIF OUT RCA JACK SILKSCREEN: SPDIF OUT MP1 2 MP2 4 A-26 5 D 5 2 2 Thursday, February 01, 2007 1 509122-0001 DWG NO Date: SPDIF/TVP5146-Switch Size: B Sheet TMS320C6424 Evaluation Module SPECTRUM DIGITAL INCORPORATED Page Contents: Title: 1 25 o f 30 Revision: A A B C D Spectrum Digital, Inc C6424 EVM Technical Reference A B C D 5 EM_D[3] EM_D[2] EM_D[1] EM_D[0] 15,16,20 15,16,20 15,16,20 15,16,20 6,15,16 B.EM_A05 B.EM_A06 B.EM_A07 B.EM_A08 EM_WEn 6,15,16 EM_A03 6,15,16 EM_A01_ALE 6,10,15,16 EM_BA0 6,10,15,16 EM_BA1 6,15 EM_WAIT_BSYn 6,14 6,14 6,14 6,14 GP[25]_BOOTMODE3 GP[24]_BOOTMODE2 GP[23]_BOOTMODE1 GP[22]_BOOTMODE0 6 RMCRSVD 14 MEM_EMD7-0_ENABLEn 14 EMA21-13_ENABLEn 3,4,20 RESETn 3,16,18,24,29 SYS_RESETn 6,10 6,10 6,10 6,10 EM_RNW GP[53] B.EM_A17 B.EM_A18 B.EM_A19 B.EM_A20 EM_D[12] EM_D[13] EM_D[14] EM_D[15] GP[54] 6 RMREFCLK 6 6 14,20 14,20 14,20 14,20 6,14 6,14 6,14 6,14 6 6 RMRXER 6 RMREFCLK 6 RMRXD1_EM_CS5 6 RMRXD0_EM_CS4 6 RMCRSVD 6,10 RMTXD1_LENDIAN 6,10 RMTXD0_8_16 6 RMTXEN 5 9 10 11 12 13 14 15 16 RN39 8 7 6 5 4 3 2 1 4 RPACK8-10 VCC_5V VCC_3V3 VCC_1V8 EM_A05_GP[96] EM_A06_GP[95] EM_A07_GP[94] EM_A08_GP[93] EM_WEn EM_A03_GP[11] EM_A01_ALE_GP[9] EM_BA0_GP[6]_(AEM1) EM_BA1_GP[5]_(AEM0) EM_D[3]_GP[17] EM_D[2]_GP[16] EM_D[1]_GP[15] EM_D[0]_GP[14] GP[25]_BOOTMODE3 GP[24]_BOOTMODE2 GP[23]_BOOTMODE1 GP[22]_BOOTMODE0 RMC RSDV_GP[30] RMREFCLK_GP[31] EM_RNW_GP[35] GP[53] EM_A17_GP[47] EM_A18_GP[46] EM_A19_GP[45] EM_A20_GP[44] EM_D[12]_GP[39] EM_D[13]_GP[38] EM_D[14]_GP[37] EM_D[15]_GP[36] GP[54] 4 B_RMRXER 17 B_RMREFCLK 17 B_RMRXD1 17 B_RMRXD0 17 B_RMCRSDV 17 B_RMTXD1 17 B_RMTXD0 17 B_RMTXEN 17 RESERVED_PIN5 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 DC_P1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 CONNECTOR 50 X 2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 SILKSCREEN: DC_P1 3 3 VCC_5V VCC_3V3 VCC_1V8 PWM1/AXR0_4/GIO004 CLK_OUT/PWM2/GIO084 EM_A9_GP[92] EM_A10_GP[91] EM_A11_GP[90] EM_A12_GP[89] EM_OEn EM_A04_GP[10] EM_A02_CLE_GP[8] EM_A00_GP[7]_(AEM2) EM_CS2_GP[12] EM_CS3_GP[13] EM_D[4]_GP[18] EM_D[5]_GP[19] EM_D[6]_GP[20] EM_D[7]_GP[21] GP[26]_FASTBOOT RMTXD1_GP[27] RMTXD0_GP[28] RMTXEN_GP[29] RMRXD1_EM_CS5_GP[33] RMRXD0_EM_CS4_GP[32] EM_A21_GP[34] RMRXER_GP[52] EM_A16_GP[48] EM_A15_GP[49] EM_A14_GP[50] EM_A13_GP[51] EM_D[11]_GP[40] EM_D[10]_GP[41] EM_D[9]_GP[42] EM_D[8]_GP[43] 6,14 6 14,20 14,20 14,20 14,20 6,14 6,14 6,14 6,14 6,14 6,14 6,14 6,14 15,16,20 15,16,20 15,16,20 15,16,20 6,15,16 2 PWM1 5 I2C_INT_ENABLEn 5 CLK_OUT 5 B.EM_A09 B.EM_A10 B.EM_A11 B.EM_A12 EM_OEn EM_A04 6,10,15,16 EM_A02_CLE 6,15,16 EM_A00 6,10,15,16 DC_EM_CS2n 14 EM_CS3 6 EM_D[4] EM_D[5] EM_D[6] EM_D[7] GP[26]_FASTBOOT 6,10 RMTXD1_LENDIAN 6,10 RMTXD0_8_16 6,10 RMTXEN 6 RMRXD1_EM_CS5 6 RMRXD0_EM_CS4 6 EM_A21 RMRXER B.EM_A16 B.EM_A15 B.EM_A14 B.EM_A13 EM_D[11] EM_D[10] EM_D[9] EM_D[8] DWG NO Thursday, February 01, 2007 1 509122-0001 VIDEO DC Conn. Sheet TMS320C6424 Evaluation Module Size:B Date: 1 SPECTRUM DIGITAL INCORPORATED Page Contents: Title: MEM_D15-8_ENABLEn 14 2 26 o f 30 Revision: A A B C D Spectrum Digital, Inc A-27 A-28 A B C D 5 5 DX1 CLKR1 FSX1 UCTS0 URTS0 21 B_GP[3] 21 B_GP[1] 5 TOUT0L 5 5 5,19 TOUT1L 5,16,24 CLKX0 5,16,24 DX0 5,16 FSX0 5,11,12,16,24 I2C_DATA 5,24 5,24 5,24 17,21 B.COL 17,21 B.RXD2 17,21 B.RXD0 17,21 B.RXER 17,21 B.RXCLK 17,21 B.MDIO 17 ENET_ENABLEn 17,21 B.TXD0 17,21 B.TXD2 17,21 B.TXCLK 11 USER_I2C_IO.A0P7 12 USER_I2C_IO.A1P1 12 USER_I2C_IO.A1P3 4 VCC_5V VCC_3V3 B_GP[3] B_GP[1] CLKS0_TOUT0L_GP[97] UCTS0_GP[87] URTS0_PWM0_GP[88] TOUT1L_UTXD1_GP[55] ACLKR0_CLKX0_GP[99] AXR0[1]_DX0_GP[104] AXR0[2]_FSX0_GP[103] I2C_DATA AFSX0_DX1_GP[107] AHCLKX0_CLKR1_GP[108] AMUTEIN0_FSX1_GP[109] HD09_MCOL_GP[67] HRDYn_MRXD2_GP[80] HDS2n_MRXD0_GP[78] HCNTL0_MRXER_GP[74] HRNW_MRXCLK_GP[77] HASn_MDIO_GP[83] HD14_MTXD0_GP[72] HD12_MTXD2_GP[70] HD15_MTXCLK_GP[73] USER_I2C_IO.A0P7 USER_I2C_IO.A1P1 USER_I2C_IO.A1P3 4 90 88 86 84 82 80 78 76 74 72 70 68 66 64 62 60 58 56 54 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 90 88 86 84 82 80 78 76 74 72 70 68 66 64 62 60 58 56 54 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 DC_P2 89 87 85 83 81 79 77 75 73 71 69 67 65 63 61 59 57 55 53 51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 CONNECTOR 45 X 2 89 87 85 83 81 79 77 75 73 71 69 67 65 63 61 59 57 55 53 51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 3 AUDIO_CLK 3 VCC_5V VCC_3V3 B_GP[2] B_GP[0] CLKS1_TINP0L_GP[98] UTXD0_GP[86] URXD0_GP[85] AHCLKR0_CLKR0_GP[101] AFSR0_DR0_GP[100] AXR0[3]_FSR0_GP[102] NO-POP R270 AUDIO_CLK TINP1L_URXD1_GP[56] I2C_CLK ACLKX0_CLKX1_GP[106] AMUTE0_DR1_GP[110] AXR0[0]_FSR1_GP[105] RESET_OUTn HINTn_MRXD3_GP[82] HDS1n_MRXD1_GP[79] HD1 0_CRS_GP[68] HHWIL_MRXDV_GP[74] MDC/HCSn/AD05/GIO081 HCNTL1_MTXEN_GP[75] HD13_MTXD1_GP[71] HD11_TXD3_GP[69] USER_I2C_IO.A0P6 USER_I2C_IO.A1P0 USER_I2C_IO.A1P2 17,21 17,21 17,21 17,21 17,21 17,21 17,21 17,21 5 5,16,24 5 2 UTXD0 5,19 URXD0 5,19 RS232_ENABLEn 19 B_GP[2] 21 B_GP[0] 21 TINP0L 5 AUDIO_CLK 24 TINP1L 5,19 CLKR0 DR0 FSR0 CLKX1 5,24 DR1 5,24 FSR1 5,24 AIC33_ENABLEn 12 I2C_CLK 5,11,12,16,24 RESET_OUTn 3,20 B.RXD3 B.RXD1 B.CRS B.RXDV B.MDC B.TXEN B.TXD1 B.TXD3 USER_I2C_IO.A0P6 11 USER_I2C_IO.A1P0 12 USER_I2C_IO.A1P2 12 2 Date: Thursday, February 01, 2007 1 509122-0001 EMAC/MCBSP DC Conn. DWG NO Size:B Sheet TMS320C6424 Evaluation Module SPECTRUM DIGITAL INCORPORATED Page Contents: Title: 1 27 o f 30 Revision: A A B C D Spectrum Digital, Inc C6424 EVM Technical Reference A B C 5 11,23 VLYNQ_RESET 20,23 VLYNQ_RXD2 20,23 VLYNQ_RXD3 20,23 VLYNQ_RXD0 20,23 VLYNQ_RXD1 20,23 VLYNQ_SCRUN 4 3 2 1 4 C177 0.1uF 4 U15 SN74LVC1G06DBVRG4 VCC_3V3 VCC_5V HD03_VLYNQ_RXD2_GP[61] HD04_VLYNQ_RXD3_GP[62] HD01_VLYNQ_RXD0_GP[59] HD02_VLYNQ_RXD1_GP[60] HD00_VLYNQ_SCRUN_GP[58] R266 1K DC_P3 2 4 6 8 10 12 14 16 18 20 R267 NO-POP VCC_1V8 HEADER 10X2 1 3 5 7 9 11 13 15 17 19 SILKSCREEN: DC_P3 - VLYNQ VCC_3V3 VCC_3V3 3 VCC_5V HD07_VLYNQ_TXD2_GP[65] HD08_VLYNQ_TXD3_GP[66] HD05_VLYNQ_TXD0_GP[63] HD06_VLYNQ_TXD1_GP[64] VLYNQ_CLOCK_GP[57] Note: Place ontop of traces going between the bus-exchange switches and the mPCI connector to improve signal integrity. 5 3 D 5 2 2 Thursday, February 01, 2007 1 509122-0001 DWG NO Date: VLYNQ/EMIF DC Conn. Size:B Sheet TMS320C6424 Evaluation Module SPECTRUM DIGITAL INCORPORATED Page Contents: Title: VLYNQ_TXD2 21,23 VLYNQ_TXD3 21,23 VLYNQ_TXD0 20,23 VLYNQ_TXD1 21,23 VLYNQ_CLOCK 20,23 1 28 o f 30 Revision: A A B C D Spectrum Digital, Inc A-29 A-30 A A AA L49 0.039uF 0.1uF 0.1uF 1 2 SILKSCREEN: nPOR 5 PUSHBUTTON SW SW5 B BB SILKSCREEN: EXT nPOR 33 R346 R345 10K VCC_3V3 1uF C368 C322 + TPS54310PWP 101338-0001 PGND3 PGND2 PGND1 VIN3 VIN2 VIN1 POWERPAD RT SYNC SS/ENA VBIAS U55 VCC_3V3 4 0 R285 R282 VCC_1V8 13 12 11 16 15 14 21 20 19 18 17 AGND R289 Q4 0.047uF R290 10K 1% R287 10K 1% R283 10K 1% 6 7 8 9 10 1 2 3 4 5 20K 1% 9.09K 1% PH1 PH2 PH3 PH4 PH5 AGND VSENSE COMP PWRGD BOOT 3.3 sq in AGND, min thermal pad DSP_CORE_VDD 71.5K 1% R275 10uF LESR C321 C315 C314 EMI SUPPRESION. LOCATE NEAR EACH REGULATOR. 6 VIAS FROM PAD TO PLANE OR DIRECT TIE. HEADER 2 NO-POP JP4 0 D BLM41P750SPT C320 0.1uF R349 Connect at pin 1 BSS123 S B VCC_5V NO-POP R344 3V3_PWR_OK 1V8_PWR_OK 4 G C D 30 3V3_PWR_OK 30 1V8_PWR_OK 5 R276 1.65K 1% NO-POP C331 NO-POP C329 NO-POP C327 C318 C316 560pF R273 56.0K 1% 2.7 uH C313 0.01uF R274 56.0K 1% L50 3300pF C317 3 + 3 4 5 3 4 5 3 4 5 3 GND RESET VDD 1000pF 2 1 6 GND RESET VDD 1 6 2 1 GND RESET VDD 2 1 6 TPS3808G09DBVRG4 MR CT SENSE1 U58 TPS3808G09DBVRG4 MR CT SENSE1 U57 BAS16-7-F D10 TPS3808G09DBVRG4 MR CT NO-POP C312 0 107 1% R277 C324 SENSE1 U56 100uF 4V C323 10K 0.1% R279 3 VCC_3V3 VCC_3V3 VCC_3V3 TP22 TP-60 R272 2 R281 1K VCC_3V3 TP23 TP-60 R280 2 NO-POP 10K TP27 TP-60 TP28 TP-60 GND Test Points TP26 TP-60 EMU_SYS_RESETn TP29 TP-60 TP30 TP-60 Thursday, February 01, 2007 1 509122-0001 DWG NO Date: RESET SUPERVISOR Size:B Sheet TMS320C6424 Evaluation Module SPECTRUM DIGITAL INCORPORATED 29 o f 30 Revision: A CORE_PWR_OK 30 Need box mounting holes and case shielding tabs. TP25 TP-60 1 CORE_PWR_OK TP21 TP-30 Page Contents: Title: NO-POP R314 SYS_RESETn 3,16,18,24,26 1 00 uF C325 R284 10K + R288 10K Reset Threhold 0.84 Volts 0.1uF C330 VCC_3V3 Reset Threhold 0.84 Volts 0.1uF C328 VCC_3V3 Reset Threhold 0.84 Volts 0.1uF C326 0.025 C319 R278 VCC_5V CORE_VDD_SELECT function: 0: 1.05V 1: 1.2V The FET and resistor in series with it can be removed if voltage scaling is not desired. DSP_CORE_VDD CORE_VDD_SELECT 12 A B C D Spectrum Digital, Inc C6424 EVM Technical Reference A B C D CENTER SHUNT SLEEVE VCC_5V 5 L53 C340 47uF 0 R439 BLM41P750SPT C354 0.1uF NO-POP R438 + VCC_5V GREEN DS5 R299 220 TP31 TP-30 NO-POP R292 1V8_PWR_OK EMI SUPPRESION. LOCATE NEAR EACH REGULATOR. 6 VIAS FROM PAD TO PLANE OR DIRECT TIE. 29 CORE_PWR_OK 2.5 MM JACK RASM712 J16 SILKSCREEN: 5V IN 29 1V8_PWR_OK 29 CORE_PWR_OK 0.1uF C333 C342 4 71.5K 1% R301 0.1uF C356 0.039uF 0.1uF C355 10uF LESR C349 + 0.1uF C339 71.5K 1% R294 13 12 11 16 15 14 21 20 19 18 17 TPS54310PWP 101338-0001 PGND3 PGND2 PGND1 VIN3 VIN2 VIN1 PH1 PH2 PH3 PH4 PH5 AGND VSENSE COMP PWRGD BOOT AGND 3.3 sq in AGND, min thermal pad POWERPAD RT SYNC SS/ENA VBIAS U59 Connect at pin 1 13 12 11 16 15 14 21 20 19 18 17 AGND 3.3 sq in AGND, min thermal pad TPS54310PWP 101338-0001 POWERPAD RT AGND SYNC VSENSE SS/ENA COMP VBIAS PWRGD BOOT VIN3 VIN2 VIN1 PH1 PH2 PGND3 PH3 PGND2 PH4 PGND1 PH5 U60 Connect at pin 1 6 7 8 9 10 1 2 3 4 5 EMI SUPPRESION. LOCATE NEAR EACH REGULATOR. 6 VIAS FROM PAD TO PLANE OR DIRECT TIE. 10uF LESR + 0.039uF C334 C348 3V3_PWR_OK BLM41P750SPT C341 0.1uF L51 NO-POP R393 4 3 C352 C350 470pF C335 470pF 2.7 uH L52 L54 + + 100uF 4V R296 R297 10K 1% R303 1000pF C344 1000pF C358 3300pF 100uF 4V C343 R305 C357 C351 Sets Voltage C347 8200pF R300 10.2K 1% 3.3 uH 3300pF 10K 1% C336 Sets Voltage C332 8200pF R291 3.74K 1% R293 2K 1% C337 R302 2K 1% 0.047uF 0.047uF 6 7 8 9 10 1 2 3 4 5 3 + 2 TP37 TP-60 0.025 107 1% TP33 TP-60 107 1% 100 uF 4V C345 2 1 5 TP34 TP-60 R298 TP38 TP-60 R306 DWG NO 1 509122-0001 Thursday, February 01, 2007 POWER Sheet TMS320C6424 Evaluation Module Size:B Date: 1V8_PWR_OK 10K SPECTRUM DIGITAL INCORPORATED 100 uF C359 C353 30 o f TP32 TP-30 3V3_PWR_OK R304 VCC_5V NO-POP Page Contents: Title: + 100 uF C346 NO-POP C338 3V3_PWR_OK 29 + VCC_3V3 VCC_1V8 3V3_PWR_OK 3.3V @1.5Amp Max 0.025 10K R295 VCC_5V 1 30 Revision: A TP36 TP-30 A B C D Spectrum Digital, Inc A-31 Spectrum Digital, Inc A-32 C6424 EVM Technical Reference Appendix B Mechanical Information This appendix contains the mechanical information about the C6424 EVM produced by Spectrum Digital. B-1 THIS DRAWING IS NOT TO SCALE Spectrum Digital, Inc B-2 C6424 EVM Technical Reference Spectrum Digital, Inc B-3 Spectrum Digital, Inc B-4 C6424 EVM Technical Reference Printed in U.S.A., February 2007 509125-0001 Rev A Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Spectrum Digital: 702070