CMOS 4-BIT SINGLE CHIP MICROCONTROLLER S1C60N16 Technical Manual Rev.1.3 NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. 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Configuration of product number Devices S1 C 60N01 F 0A01 00 Packing specifications 00 : Besides tape & reel 0A : TCP BL 2 directions 0B : Tape & reel BACK 0C : TCP BR 2 directions 0D : TCP BT 2 directions 0E : TCP BD 2 directions 0F : Tape & reel FRONT 0G : TCP BT 4 directions 0H : TCP BD 4 directions 0J : TCP SL 2 directions 0K : TCP SR 2 directions 0L : Tape & reel LEFT 0M: TCP ST 2 directions 0N : TCP SD 2 directions 0P : TCP ST 4 directions 0Q : TCP SD 4 directions 0R : Tape & reel RIGHT 99 : Specs not fixed Specification Package D: die form; F: QFP Model number Model name C: microcomputer, digital products Product classification S1: semiconductor Development tools S5U1 C 60R08 D1 1 00 Packing specifications 00: standard packing Version 1: Version 1 Tool type Hx : ICE Ex : EVA board Px : Peripheral board Wx : Flash ROM writer for the microcomputer Xx : ROM writer peripheral board Cx Ax Dx Qx : C compiler package : Assembler package : Utility tool by the model : Soft simulator Corresponding model number 60R08: for S1C60R08 Tool classification C: microcomputer use Product classification S5U1: development tool for semiconductor products CONTENTS CONTENTS CHAPTER 1 OVERVIEW _______________________________________________ 1 1.1 1.2 1.3 1.4 1.5 1.6 CHAPTER Configuration ................................................................................................ 1 Features ......................................................................................................... 1 Block Diagram .............................................................................................. 2 Pin Layout Diagram ..................................................................................... 3 Pin Description ............................................................................................. 4 Option List .................................................................................................... 5 2 POWER SUPPLY AND INITIAL RESET ____________________________ 8 2.1 2.2 Power Supply ................................................................................................ 8 Initial Reset ................................................................................................... 9 2.2.1 Power-on reset circuit ................................................................................ 9 2.2.2 RESET terminal .......................................................................................... 9 2.2.3 Simultaneous high input to input ports (K00-K03) .................................. 9 2.2.4 Watchdog timer .......................................................................................... 10 2.2.5 Internal register at initial reset ................................................................. 10 2.3 CHAPTER 3 CPU, ROM, RAM ________________________________________ 11 3.1 3.2 3.3 CHAPTER Test Terminal (TEST) ................................................................................... 10 CPU .............................................................................................................. 11 ROM ............................................................................................................. 11 RAM ............................................................................................................. 11 4 PERIPHERAL CIRCUITS AND OPERATION __________________________ 12 4.1 4.2 Memory Map ................................................................................................ 12 Resetting Watchdog Timer ........................................................................... 16 4.2.1 Configuration of watchdog timer .............................................................. 16 4.2.2 Mask option ............................................................................................... 16 4.2.3 Control of watchdog timer ........................................................................ 16 4.2.4 Programming note ..................................................................................... 16 4.3 Oscillation Circuit ....................................................................................... 17 4.3.1 Configuration of oscillation circuit .......................................................... 17 4.3.2 OSC1 oscillation circuit ............................................................................ 17 4.3.3 OSC3 oscillation circuit (S1C60A16) ....................................................... 18 4.3.4 Switching the system clock (S1C60A16) ................................................... 18 4.3.5 Control of oscillation circuit (S1C60A16) ................................................ 19 4.3.6 Programming notes (S1C60A16) .............................................................. 19 4.4 Input Ports (K00-K03, K10) ........................................................................ 20 4.4.1 Configuration of input ports ..................................................................... 20 4.4.2 Input comparison registers and interrupt function .................................. 20 4.4.3 Mask option ............................................................................................... 21 4.4.4 Control of input ports ................................................................................ 22 4.4.5 Programming notes ................................................................................... 23 4.5 Output Ports (R00-R03, R10-R13) ............................................................. 25 4.5.1 Configuration of output ports ................................................................... 25 4.5.2 Mask option ............................................................................................... 25 4.5.3 Control of output ports .............................................................................. 27 4.5.4 Programming note ..................................................................................... 28 S1C60N16 TECHNICAL MANUAL EPSON i CONTENTS 4.6 I/O Ports (P00-P03, P10-P13) ................................................................... 29 4.6.1 Configuration of I/O ports ........................................................................ 29 4.6.2 Mask option ............................................................................................... 29 4.6.3 I/O control register and I/O mode ............................................................ 29 4.6.4 Control of I/O ports ................................................................................... 30 4.6.5 Programming notes ................................................................................... 31 4.7 Serial Interface ............................................................................................ 32 4.7.1 Configuration of serial interface .............................................................. 32 4.7.2 Mask option ............................................................................................... 32 4.7.3 Master mode and slave mode of serial interface ...................................... 33 4.7.4 Data input/output and interrupt function ................................................. 34 4.7.5 Control of serial interface ......................................................................... 36 4.7.6 Programming notes ................................................................................... 38 4.8 LCD Driver (COM0-COM3, SEG0-SEG37) ............................................. 39 4.8.1 Configuration of LCD driver .................................................................... 39 4.8.2 Cadence adjustment of oscillation frequency ........................................... 44 4.8.3 Mask option (segment allocation) ............................................................. 45 4.8.4 Control of LCD driver ............................................................................... 46 4.8.5 Programming notes ................................................................................... 47 4.9 Clock Timer .................................................................................................. 48 4.9.1 Configuration of clock timer ..................................................................... 48 4.9.2 Interrupt function ...................................................................................... 48 4.9.3 Control of clock timer ............................................................................... 49 4.9.4 Programming notes ................................................................................... 50 4.10 Stopwatch Timer ........................................................................................... 51 4.10.1 Configuration of stopwatch timer ........................................................... 51 4.10.2 Count-up pattern ..................................................................................... 51 4.10.3 Interrupt function .................................................................................... 52 4.10.4 Control of stopwatch timer ..................................................................... 53 4.10.5 Programming notes ................................................................................. 54 4.11 Sound Generator .......................................................................................... 55 4.11.1 Configuration of sound generator .......................................................... 55 4.11.2 Frequency setting .................................................................................... 56 4.11.3 Digital envelope ...................................................................................... 56 4.11.4 Mask option ............................................................................................. 57 4.11.5 Control of sound generator ..................................................................... 58 4.11.6 Programming note ................................................................................... 59 4.12 Event Counter .............................................................................................. 60 4.12.1 Configuration of event counter ............................................................... 60 4.12.2 Switching count mode ............................................................................. 60 4.12.3 Mask option ............................................................................................. 61 4.12.4 Control of event counter .......................................................................... 62 4.12.5 Programming notes ................................................................................. 63 4.13 Analog Comparator ..................................................................................... 64 4.13.1 Configuration of analog comparator ...................................................... 64 4.13.2 Operation of analog comparator ............................................................ 64 4.13.3 Control of analog comparator ................................................................ 65 4.13.4 Programming notes ................................................................................. 65 4.14 Supply Voltage Detection (SVD) Circuit ...................................................... 66 4.14.1 Configuration of SVD circuit .................................................................. 66 4.14.2 Detection timing of SVD circuit .............................................................. 66 4.14.3 Control of SVD circuit ............................................................................. 67 4.14.4 Programming notes ................................................................................. 67 ii EPSON S1C60N16 TECHNICAL MANUAL CONTENTS 4.15 Heavy Load Protection Function (S1C60A16) ............................................ 68 4.15.1 Outline of heavy load protection function .............................................. 68 4.15.2 Control of heavy load protection function .............................................. 68 4.15.3 Programming notes ................................................................................. 68 4.16 Interrupt and HALT ..................................................................................... 69 4.16.1 Interrupt factors ...................................................................................... 71 4.16.2 Specific masks and factor flags for interrupt ......................................... 71 4.16.3 Interrupt vectors ...................................................................................... 72 4.16.4 Control of interrupt and HALT ............................................................... 73 4.16.5 Programming notes ................................................................................. 74 CHAPTER 5 SUMMARY OF NOTES _______________________________________ 75 5.1 5.2 5.3 Notes for Low Current Consumption ........................................................... 75 Summary of Notes by Function .................................................................... 76 Precautions on Mounting ............................................................................ 80 CHAPTER 6 BASIC EXTERNAL WIRING DIAGRAM ____________________________ 82 CHAPTER 7 ELECTRICAL CHARACTERISTICS ________________________________ 84 7.1 7.2 7.3 7.4 7.5 7.6 CHAPTER 8 PACKAGE ________________________________________________ 90 8.1 8.2 CHAPTER Absolute Maximum Rating ........................................................................... 84 Recommended Operating Conditions .......................................................... 84 DC Characteristics ...................................................................................... 85 Analog Circuit Characteristics and Current Consumption ........................ 86 Oscillation Characteristics .......................................................................... 88 Serial Interface AC Characteristics ............................................................ 89 Plastic Package ............................................................................................ 90 Ceramic Package for Test Samples .............................................................. 91 9 PAD LAYOUT _____________________________________________ 92 9.1 9.2 Diagram of Pad Layout ................................................................................ 92 Pad Coordinates ........................................................................................... 93 REVISION HISTORY S1C60N16 TECHNICAL MANUAL EPSON iii CHAPTER 1: OVERVIEW CHAPTER 1 OVERVIEW The S1C60N16 Series is a single-chip microcomputer made up of the 4-bit core CPU S1C6200C, ROM (4,096 words x 12 bits), RAM (256 words x 4 bits), LCD driver, analog comparator, event counter, watchdog timer, and two types of time base counter. Because of its low-voltage operation and low power consumption, this series is ideal for a wide range of battery-driven applications. It is especially suitable for various controller applications such as a clock, game and pager. 1.1 Configuration The S1C60N16 Series is configured as follows, depending on supply voltage and oscillation circuits. Table 1.1.1 Model configuration Model Supply voltage Oscillation circuit LCD power supply S1C60N16 S1C60L16 S1C60A16 3.0 V 1.5 V 3.0 V OSC1 only OSC1 and OSC3 (Single clock) (Twin clock) Supports 3.0 V LCD panels 1.2 Features Table 1.2.1 Features Model OSC1 oscillation circuit OSC3 oscillation circuit Instruction set Instruction execution time (differs depending on instruction) (CLK: CPU operation frequency) ROM capacity RAM capacity Input ports Output ports I/O ports Serial interface LCD driver Time base counter Watchdog timer Event counter Sound generator Analog comparator Supply voltage detection (SVD) Heavy load protection function External interrupt Internal interrupt Supply voltage Current CLK= 32.768 kHz consumption (when halted) (Typ. value) CLK= 32.768 kHz (when executed) CLK= 1 MHz (ceramic) (when executed) CLK= 1 MHz (CR) (when executed) Form when shipped S1C60N16 TECHNICAL MANUAL S1C60N16 S1C60L16 S1C60A16 Crystal oscillation circuit 32.768 kHz (Typ.) - CR or ceramic oscillation circuit (selected by mask option) 1 MHz (Typ.) 108 types 153 sec, 214 sec, 366 sec (CLK = 32.768 kHz) - 5 sec, 7 sec, 12 sec (CLK = 1 MHz) 4,096 words x 12 bits 256 words x 4 bits 5 bits (pull-down resistor can be added by mask option) 8 bits (BZ, BZ, FOUT and SIOF outputs are available by mask option) 8 bits (pull-down resistor is added during input data read-out) (3 bits can be configured as serial I/O ports by mask option) 1 port (8-bit clock synchronous system) 38 segments x 4, 3, or 2 commons (selected by mask option) V-3 V 1/4, 1/3 or 1/2 duty (voltage regulator and booster circuits built-in) Two types (timer and stopwatch) Built-in (can be disabled by mask option) Two 8-bit inputs (dial input evaluation or independent) Programmable in 8 sounds (8 frequencies) Digital envelope built-in (can be disabled by mask option) Inverted input x 1, non-inverted input x 1 2.2 V 1.2 V 2.2 V Not implemented Implemented Input interrupt: 2 systems Time base counter interrupt: 2 systems Serial interface interrupt: 1 system 3.0 V (2.2-3.6 V) 1.5 V (1.2-1.8 V) 3.0 V (2.2-3.6 V) 0.7 A 0.7 A 1.5 A (Normal operation mode) 1.4 A 1.4 A 2.4 A (Normal operation mode) - - 50 A (Normal operation mode) - - 85 A (Normal operation mode) QFP14-80pin or chip EPSON 1 CHAPTER 1: OVERVIEW 1.3 Block Diagram ROM System Reset Control 4,096 words x 12 bits RESET Core CPU S1C6200C OSC1 OSC2 OSC3 OSC4 OSC Interrupt Generator RAM Input Port K00-K03 K10 TEST I/O Port P00-P03 P10-P13 256 words x 4 bits COM0-3 SEG0-37 VDD VD1 VC1 VC2 VC3 CA CB VSS AMPP AMPM LCD Driver 38 SEG x 4 COM Serial I/F Power Controller Output Port SVD Sound Generator Event Counter Timer Comparator Stopwatch R00-R03 R10-R13 Fig. 1.3.1 Block diagram 2 EPSON S1C60N16 TECHNICAL MANUAL CHAPTER 1: OVERVIEW 1.4 Pin Layout Diagram QFP14-80pin 60 41 40 61 INDEX 21 80 1 20 No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name P13 P12 P11 P10 P03 P02 P01 P00 R13 R12 R11 R10 R03 R02 R01 R00 K00 K01 K02 K03 No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Name K10 VSS AMPM AMPP OSC1 OSC2 VD1 OSC3 OSC4 VDD VC3 VC2 VC1 CB N.C. CA COM3 COM2 COM1 COM0 No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Name No. Name SEG37 61 SEG17 SEG36 62 SEG16 SEG35 63 SEG15 SEG34 64 SEG14 SEG33 65 SEG13 SEG32 66 SEG12 SEG31 67 SEG11 SEG30 68 SEG10 SEG29 69 SEG9 SEG28 70 SEG8 SEG27 71 SEG7 SEG26 72 SEG6 SEG25 73 SEG5 SEG24 74 SEG4 SEG23 75 SEG3 SEG22 76 SEG2 SEG21 77 SEG1 SEG20 78 SEG0 SEG19 79 RESET SEG18 80 TEST N.C. : No Connection Fig. 1.4.1 Pin layout S1C60N16 TECHNICAL MANUAL EPSON 3 CHAPTER 1: OVERVIEW 1.5 Pin Description Table 1.5.1 Pin description Pin name VDD VSS VD1 VC1 VC2 VC3 CA, CB OSC1 OSC2 OSC3 OSC4 K00-K03 K10 P00-P03 P10 P11 P12 P13 R00-R03 R10 R13 R11 R12 AMPP AMPM SEG0-37 COM0-3 RESET TEST Pin No. 30 22 27 33 32 31 36, 34 25 26 28 29 17-20 21 8-5 4 I/O (I) (I) - - - - - I O I O I I I/O I/O 3 2 1 16-13 12 11 10 9 24 23 78-41 40-37 79 80 I/O I/O I/O O O O O O I I O O I I Function Power supply pin (+) Power supply pin (-) Oscillation and internal logic system voltage output pin LCD drive voltage output pin (approx. 0.98 V) LCD drive voltage output pin (2*VC1) LCD drive voltage output pin (3*VC1) Boost capacitor connecting pin Crystal oscillation input pin Crystal oscillation output pin CR or ceramic oscillation input pin * (N.C. for S1C60N16 and S1C60L16) CR or ceramic oscillation output pin * (N.C. for S1C60N16 and S1C60L16) Input port pin Input port pin I/O port pin I/O port pin or serial interface data input pin * I/O port pin or serial interface data output pin * I/O port pin or serial interface clock input/output pin * I/O port pin Output port pin Output port pin or BZ output pin * Output port pin or BZ output pin * Output port pin or SIOF output pin * Output port pin or FOUT output pin * Analog comparator non-inverted input pin Analog comparator inverted input pin LCD segment output pin or DC output pin * LCD common output pin (1/2, 1/3 or 1/4 duty are selectable *) Initial reset input pin Test input pin Can be selected by mask option 4 EPSON S1C60N16 TECHNICAL MANUAL CHAPTER 1: OVERVIEW 1.6 Option List The following function and segment options are provided for the S1C60N16 Series. Multiple specifications are available in each option item as indicated in the Option List. Select the specifications that meet the target system using the function option generator winfog and the segment option generator winsog. Be sure to record the specifications for unused ports too, according to the instructions provided. Refer to the "S1C60/62 Family Development Tool Manual" for winfog and winsog. <FUNCTION OPTION> 1. DEVICE TYPE * DEVICE TYPE ...................................... 1. S1C60N16 (Normal Type) 2. S1C60L16 (Low Power Type) 3. S1C60A16 (Twin Clock Type) 2. OSC3 SYSTEM CLOCK (only for S1C60A16) 1. Ceramic 2. CR 3. MULTIPLE KEY ENTRY RESET * COMBINATION .................................. * TIME AUTHORIZE ............................. 1. Not Use 2. Use K00, K01 3. Use K00, K01, K02 4. Use K00, K01, K02, K03 1. Not Use 2. Use 4. WATCHDOG TIMER 1. Use 2. Not Use 5. I/P INTERRUPT NOISE REJECTOR * K00-K03 ................................................ 1. Use * K10 ......................................................... 1. Use 2. Not Use 2. Not Use 6. SIO FUNCTION * SIO FUNCTION ................................... 1. Not Use * SIO SCLK LOGIC ................................ 1. Positive * SIO DATA PERMUTATION .............. 1. MSB First 2. Use 2. Negative 2. LSB First 7. I/P PULL DOWN RESISTOR * K00 * K01 * K02 * K03 * K10 ......................................................... ......................................................... ......................................................... ......................................................... ......................................................... 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Pch-OpenDrain 2. Pch-OpenDrain 2. Pch-OpenDrain 2. Pch-OpenDrain 8. O/P OUTPUT SPECIFICATION (R00-R03) * R00 .......................................................... * R01 .......................................................... * R02 .......................................................... * R03 .......................................................... 1. Complementary 1. Complementary 1. Complementary 1. Complementary 9. R10 TERMINAL SPECIFICATION * OUTPUT SPECIFICATION ............... 1. Complementary * OUTPUT TYPE .................................... 1. DC Output S1C60N16 TECHNICAL MANUAL EPSON 2. Pch-OpenDrain 2. Buzzer Output 5 CHAPTER 1: OVERVIEW 10. R11 TERMINAL SPECIFICATION * OUTPUT SPECIFICATION ............... 1. Complementary * OUTPUT TYPE .................................... 1. DC Output 2. Pch-OpenDrain 2. SIO Flag 11. R12 TERMINAL SPECIFICATION * OUTPUT SPECIFICATION ............... 1. Complementary * OUTPUT TYPE .................................... 1. DC Output 2. FOUT 32768 [Hz] 3. FOUT 16384 [Hz] 4. FOUT 8192 [Hz] 5. FOUT 4096 [Hz] 6. FOUT 2048 [Hz] 7. FOUT 1024 [Hz] 8. FOUT 512 [Hz] 9. FOUT 256 [Hz] 2. Pch-OpenDrain 12. R13 TERMINAL SPECIFICATION * OUTPUT SPECIFICATION ............... 1. Complementary 2. Pch-OpenDrain * OUTPUT TYPE .................................... 1. DC Output 2. Buzzer Inverted Output (R13 Control) 3. Buzzer Inverted Output (R10 Control) 13. I/O PORT SPECIFICATION (P00-P03) * P00 .......................................................... * P01 .......................................................... * P02 .......................................................... * P03 .......................................................... 1. Complementary 1. Complementary 1. Complementary 1. Complementary 2. Pch-OpenDrain 2. Pch-OpenDrain 2. Pch-OpenDrain 2. Pch-OpenDrain 2. Pch-OpenDrain 2. Pch-OpenDrain 2. Pch-OpenDrain 2. Pch-OpenDrain 14. I/O PORT SPECIFICATION (P10-P13) * P10 .......................................................... * P11 .......................................................... * P12 .......................................................... * P13 .......................................................... 1. Complementary 1. Complementary 1. Complementary 1. Complementary 15. EVENT COUNTER NOISE REJECTOR 1. 2048 [Hz] 2. 256 [Hz] 16. LCD DRIVER DUTY * DUTY SELECTION ............................. 1. 1/4 Duty 2. 1/3 Duty 3. 1/2 Duty 17. LCD BIAS & POWER SOURCE * BIAS & POWER SOURCE SELECTION S1C60N16 .............................................. 1. 1/3 Bias, Regulator Used, LCD 3 V S1C60L16 .............................................. 1. 1/3 Bias, Regulator Used, LCD 3 V S1C60A16 .............................................. 1. 1/3 Bias, Regulator Used, LCD 3 V 2. 1/3 Bias, Regulator Not Used, LCD 3 V 3. 1/2 Bias, Regulator Not Used, LCD 3 V 18. SEGMENT MEMORY ADDRESS 1. 2 Page (240-265) 6 EPSON 2. 0 Page (040-065) S1C60N16 TECHNICAL MANUAL CHAPTER 1: OVERVIEW <SEGMENT OPTION> TERMINAL NAME SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 Legend: COM0 H L D ADDRESS COM1 COM2 H L D H L D H COM3 L D OUTPUT SPECIFICATION SEG output DC output C P SEG output DC output C P SEG output DC output C P SEG output DC output C P SEG output DC output C P SEG output DC output C P SEG output DC output C P SEG output DC output C P SEG output DC output C P SEG output DC output C P SEG output DC output C P SEG output DC output C P SEG output DC output C P SEG output DC output C P SEG output DC output C P SEG output DC output C P SEG output DC output C P SEG output DC output C P SEG output DC output C P <OUTPUT SPECIFICATION> C: Complementary output P: Pch open drain output <ADDRESS> H: High order address (4-6) L: Low order address (0-F) D: Data bit (0-3) Note: When setting H (high order address) to 6, L (low order address) must be within 0 to 5. S1C60N16 TECHNICAL MANUAL EPSON 7 CHAPTER 2: POWER SUPPLY AND INITIAL RESET CHAPTER 2 POWER SUPPLY AND INITIAL RESET 2.1 Power Supply With a single external power supply (1) supplied to VDD through VSS, the S1C60N16 Series generates the necessary internal voltage with the voltage regulator circuit (<VD1> for oscillators, <VC1> for LCD) and the voltage booster circuit (<VC2 and VC3> for LCD). 1 Supply voltage: S1C60N16/60A16 .. 3 V, S1C60L16 .. 1.5 V Figure 2.1.1 shows the power supply configuration. The voltage <VD1> for the internal circuit is generated by the internal system voltage regulator. The S1C60N16 Series generates <VC1> with the voltage regulator and <VC2, VC3> with the voltage booster. Notes: * External loads cannot be driven by the output voltage of the voltage regulator and voltage booster. * See Chapter 7, "Electrical Characteristics", for voltage values. External power supply Internal circuit VDD VD1 Internal system voltage regulator VD1 VC1 LCD system voltage regulator VC1 OSC1, 2 OSC3, 4 (S1C60A16) Oscillation circuit VC1 VC2 VC3 LCD system voltage booster CA CB VC2 VC3 COM0-3 SEG0-37 LCD driver VSS Fig. 2.1.1 Power supply configuration The LCD system voltage regulator in the S1C60A16 can be disabled by mask option. In this case, external elements can be minimized because the external capacitors for the LCD system voltage regulator are not necessary. However when the LCD system voltage regulator is not used, the display quality of the LCD panel, when the supply voltage fluctuates (drops), is inferior to when the LCD system voltage regulator is used. Figure 2.1.2 shows the external element configuration when the LCD system voltage regulator is not used. 3 V LCD panel 1/4, 1/3 or 1/2 duty, 1/3 bias VDD 3 V LCD panel 1/4, 1/3 or 1/2 duty, 1/2 bias VDD 3.0 V VD1 VC1 VC2 VC3 CA CB VSS 3 V LCD panel 1/4, 1/3 or 1/2 duty, 1/2 bias VDD 3.0 V VD1 VC1 VC2 VC3 CA CB VSS Note: VC3 is shorted to VDD inside the IC 1.5 V VD1 VC1 VC2 VC3 CA CB VSS Note: VC1 is shorted to VDD inside the IC Fig. 2.1.2 External elements when LCD system voltage regulator is not used (S1C60A16) 8 EPSON S1C60N16 TECHNICAL MANUAL CHAPTER 2: POWER SUPPLY AND INITIAL RESET 2.2 Initial Reset To initialize the S1C60N16 Series circuits, initial reset must be executed. There are four ways of doing this. (1) Initial reset by the power on reset circuit (2) External initial reset by the RESET terminal (3) External initial reset by simultaneous high input to terminals K00-K03 (4) Initial reset by the watchdog timer Figure 2.2.1 shows the configuration of the initial reset circuit. OSC1 OSC2 OSC1 oscillation circuit Watchdog timer Mask option Power-on reset circuit K00 K01 VSS Time authorize circuit K02 K03 Noise rejector Initial reset Mask option RESET VSS Fig. 2.2.1 Configuration of initial reset circuit 2.2.1 Power-on reset circuit The power-on reset circuit outputs the initial reset signal at power-on until the oscillation circuit starts oscillating. Note: The power-on reset circuit may not work properly due to unstable or lower voltage input. The following two initial reset method are recommended to generate the initial reset signal. 2.2.2 RESET terminal Initial reset can be executed externally by setting the reset terminal to the high level. This high level must be maintained for at least 5 msec (when oscillating frequency is fOSC1 = 32 kHz), because the initial reset circuit contains a noise rejector. When the reset terminal goes low the CPU begins to operate. 2.2.3 Simultaneous high input to input ports (K00-K03) Another way of executing initial reset externally is to input a high signal simultaneously to the input ports (K00-K03) selected with the mask option. The specified input port terminals must be kept high for at least 5 msec (when oscillating frequency is fOSC1 = 32 kHz), because the initial reset circuit contains a noise rejector. Table 2.2.3.1 shows the combinations of input ports (K00-K03) that can be selected with the mask option. Table 2.2.3.1 Input port combination Selection Combination A Not used B C D K00K01 K00K01K02 K00K01K02K03 When, for instance, mask option D (K00*K01*K02*K03) is selected, initial reset is executed when the signals input to the four ports K00-K03 are all high at the same time. S1C60N16 TECHNICAL MANUAL EPSON 9 CHAPTER 2: POWER SUPPLY AND INITIAL RESET Further, the time authorize circuit can be selected with the mask option. The time authorize circuit performs initial reset, when the input time of the simultaneous high input is authorized and found to be the same or more than the defined time (1 to 3 sec). If you use this function, make sure that the specified ports do not go high at the same time during ordinary operation. 2.2.4 Watchdog timer If the CPU runs away for some reason, the watchdog timer will detect this situation and output an initial reset signal. See Section 4.2, "Resetting Watchdog Timer", for details. 2.2.5 Internal register at initial reset Initial reset initializes the CPU as shown in the table below. Table 2.2.5.1 Initial values CPU Core Name Symbol Bit size Program counter step PCS 8 Program counter page PCP 4 New page pointer NPP 4 Stack pointer SP 8 Index register X X 10 Index register Y Y 10 Register pointer RP 4 General-purpose register A A 4 General-purpose register B B 4 Interrupt flag I 1 Decimal flag D 1 Zero flag Z 1 Carry flag C 1 Initial value 00H 1H 1H Undefined Undefined Undefined Undefined Undefined Undefined 0 0 Undefined Undefined Peripheral Circuits Bit size Initial value RAM 4 Undefined Display memory 4 Undefined Other peripheral circuits 4 See Section 4.1, "Memory Map". Name 2.3 Test Terminal (TEST) This terminal is used when the IC load is being detected. During ordinary operation be certain to connect this terminal to VSS. 10 EPSON S1C60N16 TECHNICAL MANUAL CHAPTER 3: CPU, ROM, RAM CHAPTER 3 CPU, ROM, RAM 3.1 CPU The S1C60N16 Series employs the core CPU S1C6200C for the CPU, so that register configuration, instructions and so forth are virtually identical to those in other family processors using the S1C6200/ 6200A/6200B/6200C. Refer to the "S1C6200/6200A Core CPU Manual" for details about the core CPU. Note the following points with regard to the S1C60N16 Series: (1) The SLEEP operation is not assumed, so the SLP instruction cannot be used. (2) Because the ROM capacity is 4,096 words, bank bits are unnecessary and PCB and NBP are not used. (3) Data memory is set up to two pages, so only the two low-order bits are valid for the page portion (XP, YP) of the index register that specifies addresses. (The two high-order bits are ignored.) 3.2 ROM The built-in ROM, a mask ROM for loading the program, has a capacity of 4,096 steps, 12 bits each. The program area is 16 pages (0-15), each of 256 steps (00H-FFH). After initial reset, the program start address is page 1, step 00H. The interrupt vector is allocated to page 1, steps 01H-0FH. Bank 0 Step 00H Page 0 Step 01H Program start address Page 1 Interrupt vector area Page 2 Page 3 Step 0FH Step 10H Program area Page 15 Step FFH 12 bits Fig. 3.2.1 ROM configuration 3.3 RAM The RAM, a data memory for storing a variety of data, has a capacity of 256 words, 4-bit words. When programming, keep the following points in mind: (1) Part of the data memory is used as stack area when saving subroutine return addresses and registers, so be careful not to overlap the data area and stack area. (2) Subroutine calls and interrupts take up three words on the stack. (3) Data memory 000H-00FH is the memory area pointed by the register pointer (RP). S1C60N16 TECHNICAL MANUAL EPSON 11 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Peripheral circuits (timer, I/O, and so on) of the S1C60N16 Series are memory mapped. Thus, all the peripheral circuits can be controlled by using memory operations to access the I/O memory. The following sections describe how the peripheral circuits operate. 4.1 Memory Map The data memory of the S1C60N16 Series has an address space of 287 words (325 words when display memory is laid out in Page 2), of which 38 words are allocated to display memory and 31 words, to I/O memory. Figure 4.1.1 shows the overall memory map for the S1C60N16 Series, and Tables 4.1.1(a)-(c), the memory maps for the peripheral circuits (I/O space). Address Low 0 1 2 3 4 5 6 7 8 9 A B C D E F Page High 0 M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF 1 2 3 4 5 6 7 RAM (256 words x 4 bits) 0 8 R/W 9 A B C D E F 0 1 2 3 4 5 6 Unused area 7 2 8 9 A B C D E I/O memory F (see Table 4.1.1) Fig. 4.1.1 Memory map Address Low 0 Page High 4 0 or 2 5 6 1 2 3 4 5 6 7 8 9 A B C D E F Display memory (38 words x 4 bits) Page 0: R/W, Page 2: W only Unused area Fig. 4.1.2 Display memory map Notes: * The display memory area can be selected from between Page 0 (040H-065H) and Page 2 (240H-265H) by mask option. When Page 0 (040H-065H) is selected, the display memory is assigned in the RAM area. So read/write operation is allowed. When Page 2 (240H-265H) is selected, the display memory is assigned as a write-only memory. * Memory is not mounted in unused area within the memory map and in memory area not indicated in this chapter. For this reason, normal operation cannot be assured for programs that have been prepared with access to these areas. 12 EPSON S1C60N16 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Table 4.1.1(a) I/O memory map (2D0H, 2E0H-2ECH) Address Register Comment Name Init 1 1 0 Unused 0 3 - 2 - - 0 0 0 CSDC2 0 3 - 2 Unused - - 2D0H 0 3 - 2 Unused - - R R/W CSDC2 1 Normal All off LCD all off control Clock timer data (2 Hz) TM3 0 TM3 TM2 TM1 TM0 Clock timer data (4 Hz) TM2 0 2E0H Clock timer data (8 Hz) TM1 0 R Clock timer data (16 Hz) TM0 0 MSB SWL3 0 SWL3 SWL2 SWL1 SWL0 SWL2 0 2E1H Stopwatch timer 1/100 sec data (BCD) SWL1 0 R LSB SWL0 0 MSB SWH3 0 SWH3 SWH2 SWH1 SWH0 SWH2 0 2E2H Stopwatch timer 1/10 sec data (BCD) SWH1 0 R LSB SWH0 0 K03 - 2 High Low K03 K02 K01 K00 - 2 High K02 Low 2E3H Input port data (K00-K03) - 2 High K01 Low R - 2 High K00 Low KCP03 0 KCP03 KCP02 KCP01 KCP00 KCP02 0 2E4H Input comparison register (K00-K03) KCP01 0 R/W KCP00 0 EIK03 0 Enable Mask EIK03 EIK02 EIK01 EIK00 EIK02 0 Enable Mask 2E5H Interrupt mask register (K00-K03) EIK01 0 Enable Mask R/W EIK00 0 Enable Mask HLMOD Heavy load Normal Heavy load protection mode register (S1C60A16) 0 HLMOD 0 EISWIT1 EISWIT0 - 0 3 Unused - 2 - 2E6H EISWIT1 0 Enable Mask Interrupt mask register (stopwatch 1 Hz) R/W R R/W EISWIT0 0 Enable Mask Interrupt mask register (stopwatch 10 Hz) SCTRG3 Trigger - Serial I/F clock trigger - SCTRG EIK10 KCP10 K10 EIK10 Enable Mask Interrupt mask register (K10) 0 2E7H KCP10 Input comparison register (K10) 0 W R/W R Low Input port data (K10) K10 - 2 High CSDC1 0 Static Dynamic LCD drive switch CSDC1 ETI2 ETI8 ETI32 ETI2 0 Enable Mask Interrupt mask register (clock timer 2 Hz) 2E8H ETI8 0 Enable Mask Interrupt mask register (clock timer 8 Hz) R/W ETI32 0 Enable Mask Interrupt mask register (clock timer 32 Hz) 0 3 - 2 Unused - - 0 TI2 TI8 TI32 TI2 4 0 Interrupt factor flag (clock timer 2 Hz) Yes No 2E9H TI8 4 0 Interrupt factor flag (clock timer 8 Hz) Yes No R TI32 4 0 Interrupt factor flag (clock timer 32 Hz) Yes No IK1 4 0 Interrupt factor flag (K10) Yes No IK1 IK0 SWIT1 SWIT0 IK0 4 0 Interrupt factor flag (K00-K03) Yes No 2EAH SWIT1 4 0 Interrupt factor flag (stopwatch 1 Hz) Yes No R SWIT0 4 0 Interrupt factor flag (stopwatch 10 Hz) Yes No R03 0 High Low Output port (R03) R03 R02 R01 R00 R02 0 High Low Output port (R02) 2EBH R01 0 High Low Output port (R01) R/W R00 0 High Low Output port (R00) R13 0 High/On Low/Off Output port (R13)/BZ output control R11 R13 R12 R10 R12 0 High/On Low/Off Output port (R12)/FOUT output control SIOF 2ECH R11 0 High Low Output port (R11) R/W SIOF 0 Run Stop Output port (SIOF) R/W R/W R R10 0 High/On Low/Off Output port (R10)/BZ output control 1 Initial value at initial reset 3 Always "0" being read 5 Undefined 2 Not set in the circuit 4 Reset (0) immediately after being read D3 D2 D1 S1C60N16 TECHNICAL MANUAL D0 EPSON 13 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Table 4.1.1(b) I/O memory map (2EDH-2F3H, 2F6H-2FCH) Address Register Comment 1 0 Name Init 1 P03 - 2 High Low P03 P02 P01 P00 - 2 High I/O port data (P00-P03) P02 Low 2EDH - 2 High Output latch is reset at initial reset P01 Low R/W - 2 High P00 Low TMRST3 Reset Reset Clock timer reset - TMRST SWRUN SWRST IOC0 SWRUN 0 Run Stop Stopwatch timer Run/Stop 2EEH SWRST3 Reset Reset Stopwatch timer reset - W R/W W R/W IOC0 0 Output Input I/O control register 0 (P00-P03) WDRST3 Reset Reset Watchdog timer reset - WDRST WD2 WD1 WD0 WD2 Timer data (watchdog timer) 1/4 Hz 0 2EFH WD1 Timer data (watchdog timer) 1/2 Hz 0 W R WD0 Timer data (watchdog timer) 1 Hz 0 SD3 x 5 SD3 SD2 SD1 SD0 x 5 SD2 2F0H Serial I/F data register (low-order 4 bits) x 5 SD1 R/W x 5 SD0 SD7 x 5 SD7 SD6 SD5 SD4 x 5 SD6 2F1H Serial I/F data register (high-order 4 bits) x 5 SD5 R/W x 5 SD4 [SCS1, 0] 0 1 2 3 SCS1 Serial I/F clock 1 SCS1 SCS0 SE2 EISIO Clock CLK CLK/2 CLK/4 Slave SCS0 mode selection 1 2F2H SE2 Serial I/F clock edge selection 0 R/W EISIO 0 Enable Mask Interrupt mask register (serial I/F) 0 3 - 2 Unused - - 0 0 0 ISIO 0 3 - 2 Unused - - 2F3H 0 3 - 2 Unused - - R ISIO 4 0 Interrupt factor flag (serial I/F) Yes No 1 2 3 [BZFQ2-0] 0 BZFQ2 0 Buzzer BZFQ2 BZFQ1 BZFQ0 ENVRST Frequency fOSC1/8 fOSC1/10 fOSC1/12 fOSC1/14 BZFQ1 0 frequency 5 6 7 [BZFQ2-0] 4 2F6H BZFQ0 0 selection Frequency fOSC1/16 fOSC1/20 fOSC1/24 fOSC1/28 R/W W ENVRST3 Reset Reset - Envelope reset ENVON Envelope On/Off 0 On Off ENVON ENVRT AMPDT AMPON ENVRT 0 1.0 sec 0.5 sec Envelope cycle selection register 2F7H AMPDT 1 +>+ < - Analog comparator data R/W R R/W AMPON Analog comparator On/Off 0 On Off EV03 0 EV03 EV02 EV01 EV00 EV02 0 2F8H Event counter 0 (low-order 4 bits) EV01 0 R EV00 0 EV07 0 EV07 EV06 EV05 EV04 EV06 0 2F9H Event counter 0 (high-order 4 bits) EV05 0 R EV04 0 EV13 0 EV13 EV12 EV11 EV10 EV12 0 2FAH Event counter 1 (low-order 4 bits) EV11 0 R EV10 0 EV17 0 EV17 EV16 EV15 EV14 EV16 0 2FBH Event counter 1 (high-order 4 bits) EV15 0 R EV14 0 EVSEL 0 Separate Phase Event counter mode selection EVSEL ENRUN EV1RST EV0RST EVRUN 0 Run Stop Event counter Run/Stop 2FCH EV1RST3 Reset Reset Event counter 1 reset - R/W W EV0RST3 Reset Reset Event counter 0 reset - 1 Initial value at initial reset 3 Always "0" being read 5 Undefined 2 Not set in the circuit 4 Reset (0) immediately after being read 14 D3 D2 D1 D0 EPSON S1C60N16 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Table 4.1.1(c) I/O memory map (2FDH-2FFH) Address Register D3 D2 D1 P13 P12 P11 2FDH R/W 0 CLKCHG OSCC 2FEH R SVDDT 2FFH R/W 0 0 SVDON R R W 1 Initial value at initial reset 2 Not set in the circuit S1C60N16 TECHNICAL MANUAL Comment Name Init 1 1 0 P13 - 2 High Low P10 - 2 High I/O port data (P10-P13) P12 Low - 2 High Output latch is reset at initial reset P11 Low - 2 High P10 Low 0 3 Unused - 2 - - IOC1 CLKCHG 0 OSC3 OSC1 CPU clock switch OSCC 0 OSC3 oscillation On/Off On Off IOC1 0 Output Input I/O control register (P10-P13) SVDDT 0 Low Normal SVD evaluation data 0 SVDON 0 On SVD On/Off Off 0 3 - 2 - Unused - 0 3 - 2 - Unused - 0 3 - 2 - Unused - 3 Always "0" being read 5 Undefined 4 Reset (0) immediately after being read D0 EPSON 15 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Resetting Watchdog Timer) 4.2 Resetting Watchdog Timer 4.2.1 Configuration of watchdog timer The S1C60N16 Series incorporates a watchdog timer as the source oscillator for OSC1 (clock timer 2 Hz signal). The watchdog timer must be reset cyclically by the software. If reset is not executed in at least 3 or 4 seconds, the initial reset signal is output automatically for the CPU. Figure 4.2.1.1 is the block diagram of the watchdog timer. Clock timer TM0-TM3 OSC1 demultiplier (256 Hz) 2 Hz Watchdog timer WD0-WD2 Initial reset signal Watchdog timer reset signal Fig. 4.2.1.1 Watchdog timer block diagram The watchdog timer, configured of a three-bit binary counter (WD0-WD2), generates the initial reset signal internally by overflow of the MSB. Watchdog timer reset processing in the program's main routine enables detection of program overrun, such as when the main routine's watchdog timer processing is bypassed. Ordinarily this routine is incorporated where periodic processing takes place, just as for the timer interrupt routine. The watchdog timer operates in the halt mode. If the halt status continues for 3 or 4 seconds, the initial reset signal restarts operation. 4.2.2 Mask option You can select whether or not to use the watchdog timer with the mask option. When "Not use" is chosen, there is no need to reset the watchdog timer. 4.2.3 Control of watchdog timer Table 4.2.3.1 lists the watchdog timer's control bits and their addresses. Table 4.2.3.1 Control bits of watchdog timer Address Register D3 D2 D1 WDRST WD2 WD1 2EFH W 1 Initial value at initial reset 2 Not set in the circuit R Comment 1 0 Name Init 1 3 WDRST Watchdog timer reset Reset Reset - WD0 WD2 Timer data (watchdog timer) 1/4 Hz 0 WD1 Timer data (watchdog timer) 1/2 Hz 0 WD0 Timer data (watchdog timer) 1 Hz 0 3 Always "0" being read 5 Undefined 4 Reset (0) immediately after being read D0 WDRST: Watchdog timer reset (2EFH*D3) This is the bit for resetting the watchdog timer. When "1" is written : Watchdog timer is reset When "0" is written : No operation Read-out : Always "0" When "1" is written to WDRST, the watchdog timer is reset, and the operation restarts immediately after this. When "0" is written to WDRST, no operation results. This bit is dedicated for writing, and is always "0" for read-out. 4.2.4 Programming note When the watchdog timer is being used, the software must reset it within 3-second cycles, and timer data (WD0-WD2) cannot be used for timer applications. 16 EPSON S1C60N16 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) 4.3 Oscillation Circuit 4.3.1 Configuration of oscillation circuit The S1C60N16 and S1C60L16 have one oscillation circuit (OSC1), and the S1C60A16 has two oscillation circuits (OSC1 and OSC3). OSC1 is a crystal oscillation circuit that supplies the operating clock to the CPU and peripheral circuits. OSC3 is either a CR or ceramic oscillation circuit. When processing with the S1C60A16 requires high-speed operation, the CPU operating clock can be switched from OSC1 to OSC3. Figure 4.3.1.1 is the block diagram of this oscillation system. OSC1 oscillation circuit Divider To peripheral circuits Clock switch OSC3 oscillation circuit To CPU (and serial interface) CPU clock selection signal Oscillation circuit control signal S1C60A16 Fig. 4.3.1.1 Oscillation system 4.3.2 OSC1 oscillation circuit The OSC1 oscillation circuit generates the main clock for the CPU and the peripheral circuits. The oscillator type is a crystal oscillation circuit and the oscillation frequency is 32.768 kHz (Typ.). Figure 4.3.2.1 is the block diagram of the OSC1 oscillation circuit. CGX VSS To CPU (and peripheral circuits) RDX RFX X'tal1 OSC1 CDX OSC2 VSS Fig. 4.3.2.1 OSC1 oscillation circuit As shown in Figure 4.3.2.1, the crystal oscillation circuit can be configured simply by connecting the crystal oscillator (X'tal1) of 32.768 kHz (Typ.) between the OSC1 and OSC2 terminals and the trimmer capacitor (CGX) between the OSC1 and VSS terminals. S1C60N16 TECHNICAL MANUAL EPSON 17 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) 4.3.3 OSC3 oscillation circuit (S1C60A16) The S1C60A16 has built-in the OSC3 oscillation circuit that generates the CPU's sub-clock (Typ. 1 MHz) for high speed operation and the source clock for the serial interface. The mask option enables selection of CR or ceramic oscillation circuit. Figure 4.3.3.1 is the block diagram of the OSC3 oscillation circuit. C CR OSC3 RCR To CPU (and serial interface) Oscillation circuit control signal OSC4 S1C60A16 (a) CR oscillation circuit C GC To CPU (and serial interface) RFC Ceramic CDC OSC3 Oscillation circuit control signal RDC S1C60A16 OSC4 VSS (b) Ceramic oscillation circuit Fig. 4.3.3.1 OSC3 oscillation circuit As shown in Figure 4.3.3.1, the CR oscillation circuit can be configured simply by connecting the resistor RCR between the OSC3 and OSC4 terminals when CR oscillation is selected. See Chapter 7, "Electrical Characteristics", for resistance value of RCR. When ceramic oscillation is selected, the ceramic oscillation circuit can be configured by connecting the ceramic oscillator (Typ. 1 MHz) between the OSC3 and OSC4 terminals, capacitor CGC between the OSC3 and OSC4 terminals, and capacitor CDC between the OSC4 and VSS terminals. See Chapter 7, "Electrical Characteristics", for capacitor values of CGC and CDC. To reduce current consumption of the OSC3 oscillation circuit, oscillation can be stopped by the software (OSCC register). For the S1C60N16 and S1C60L16 (single clock model), do not connect anything to terminals OSC3 and OSC4. 4.3.4 Switching the system clock (S1C60A16) In the S1C60A16, the CPU system clock is switched to OSC1 or OSC3 by the software (CLKCHG register). When OSC3 is to be used as the CPU clock, it should be done as the following procedure using the software: turn the OSC3 oscillation ON and wait at least 5 msec for oscillation stabilization, then switch the CPU clock after waiting 5 msec or more. When switching from OSC3 to OSC1, switch the CPU clock, then turn the OSC3 oscillation circuit off. OSC1 OSC3 1. Set OSCC to "1" (OSC3 oscillation ON). 2. Maintain 5 msec or more. 3. Set CLKCHG to "1" (OSC1 OSC3). 18 OSC3 OSC1 1. Set CLKCHG to "0" (OSC3 OSC1). 2. Set OSCC to "0" (OSC3 oscillation OFF). EPSON S1C60N16 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) 4.3.5 Control of oscillation circuit (S1C60A16) Table 4.3.5.1 lists the control bits and their addresses for the oscillation circuit. Table 4.3.5.1 Control bits of oscillation circuit Address Register D3 0 D2 D1 CLKCHG OSCC 2FEH R R/W 1 Initial value at initial reset 2 Not set in the circuit Comment 1 0 Name Init 1 0 3 Unused - 2 - - IOC1 CLKCHG 0 OSC3 OSC1 CPU clock switch OSCC 0 OSC3 oscillation On/Off On Off IOC1 0 Output Input I/O control register (P10-P13) 3 Always "0" being read 5 Undefined 4 Reset (0) immediately after being read D0 OSCC: OSC3 oscillation control (2FEH*D1) Controls oscillation ON/OFF for the OSC3 oscillation circuit. (S1C60A16 only.) When "1" is written : The OSC3 oscillation ON When "0" is written : The OSC3 oscillation OFF Read-out : Valid When it is necessary to operate the CPU of the S1C60A16 at high speed, set OSCC to "1". At other times, set it to "0" to reduce current consumption. For S1C60N16 and S1C60L16, keep OSCC set to "0". At initial reset, OSCC is set to "0". CLKCHG: CPU clock switch (2FEH*D2) The CPU's operation clock is selected with this register. (S1C60A16 only.) When "1" is written : OSC3 clock is selected When "0" is written : OSC1 clock is selected Read-out : Valid When the S1C60A16's CPU clock is to be OSC3, set CLKCHG to "1"; for OSC1, set CLKCHG to "0". This register cannot be controlled for S1C60N16 and S1C60L16, so that OSC1 is selected no matter what the set value. At initial reset, CLKCHG is set to "0". 4.3.6 Programming notes (S1C60A16) (1) It takes at least 5 msec from the time the OSC3 oscillation circuit goes ON until the oscillation stabilizes. Consequently, when switching the CPU operation clock from OSC1 to OSC3, do this after a minimum of 5 msec have elapsed since the OSC3 oscillation went ON. Further, the oscillation stabilization time varies depending on the external oscillator characteristics and conditions of use, so allow ample margin when setting the wait time. (2) When switching the clock form OSC3 to OSC1, use a separate instruction for switching the OSC3 oscillation OFF. An error in the CPU operation can result if this processing is performed at the same time by the one instruction. S1C60N16 TECHNICAL MANUAL EPSON 19 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) 4.4 Input Ports (K00-K03, K10) 4.4.1 Configuration of input ports The S1C60N16 Series has five bits (4 bits + 1 bit) of general-purpose input ports. Each of the input port terminals (K00-K03, K10) provides internal pull-down resistor. Pull-down resistor can be selected for each bit with the mask option. Figure 4.4.1.1 shows the configuration of input port. VDD Data bus Interrupt request K Mask option Address VSS Fig. 4.4.1.1 Configuration of input port Selection of "With pull-down resistor" with the mask option suits input from the push switch, key matrix, and so forth. When "Gate direct" is selected, the port can be used for slide switch input and interfacing with other LSIs. Further, The input port terminal K02 and K03 are used as the input terminals for the event counter. (See Section 4.12, "Event Counter", for details.) 4.4.2 Input comparison registers and interrupt function All five bits of the input ports (K00-K03, K10) provide the interrupt function. The conditions for issuing an interrupt can be set by the software. Further, whether to mask the interrupt function can be selected individually for all five bits by the software. Figure 4.4.2.1 shows the configuration of the input interrupt circuit. K One for each terminal series Data bus Address Noise rejector Input comparison register (KCP) Address Interrupt factor flag (IK) Mask option Interrupt request Address Interrupt mask register (EIK) Address Fig. 4.4.2.1 Input interrupt circuit configuration 20 EPSON S1C60N16 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) The input interrupt timing for K00-K03 and K10 depends on the value set for the input comparison registers (KCP00-KCP03 and KCP10). Interrupt can be selected to occur at the rising or falling edge of the input. The interrupt mask registers (EIK00-EIK03, EIK10) enables the interrupt mask to be selected individually for K00-K03 and K10. However, whereas the interrupt function is enabled inside K00-K03, the interrupt occurs when the contents change from matching those of the input comparison register to non-matching contents. Interrupt for K10 can be generated by setting the same conditions individually. When the interrupt is generated, the interrupt factor flag (IK0 and IK1) is set to "1". Figure 4.4.2.2 shows an example of an interrupt for K00-K03. Interrupt mask register EIK03 1 EIK02 1 EIK01 1 EIK00 0 Input comparison register KCP03 KCP02 KCP01 KCP00 1 0 1 0 With the above setting, the interrupt of K00-K03 is generated under the following condition: Input port (1) K03 1 K02 0 K01 1 K00 0 (2) K03 1 K02 0 K01 1 K00 1 (3) K03 0 K02 0 K01 1 K00 1 (4) K03 0 K02 1 K01 1 K00 1 (Initial value) Interrupt generation Because K00 interrupt is masked, interrupt will be generated when no matching occurs between the contents of the 3 bits K01-K03 and the 3 bits input comparison register KCP01-KCP03. Fig. 4.4.2.2 Example of interrupt of K00-K03 K00 is masked by the interrupt mask register (EIK00), so that an interrupt does not occur at (2). At (3), K03 changes to "0"; the data of the terminal that is interrupt enabled no longer matches the data of the input comparison register, so that interrupt occurs. As already explained, the condition for the interrupt to occur is the change in the port data and contents of the input comparison register from matching to nonmatching. Hence, in (4), when the nonmatching status changes to another nonmatching status, an interrupt does not occur. Further, terminals that have been masked for interrupt do not affect the conditions for interrupt generation. 4.4.3 Mask option The contents that can be selected with the input port mask option are as follows: (1) Internal pull-down resistor can be selected for each of the five bits of the input ports (K00-K03, K10). When you have selected "Gate direct", take care that the floating status does not occur for the input. Select "With pull-down resistor" for input ports that are not being used. (2) The input interrupt circuit contains a noise rejector for preventing interrupt occurring through noise. The mask option enables selection of whether to use the noise rejector for each separate terminal series. When "Use" is selected, a maximum delay of 1 msec occurs from the time interrupt condition is established until the interrupt factor flag (IK) is set to "1". S1C60N16 TECHNICAL MANUAL EPSON 21 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) 4.4.4 Control of input ports Table 4.4.4.1 lists the input ports control bits and their addresses. Table 4.4.4.1 Input port control bits Address Register Comment 1 0 Name Init 1 K03 - 2 High Low K03 K02 K01 K00 - 2 High K02 Low 2E3H Input port data (K00-K03) - 2 High K01 Low R 2 - K00 High Low KCP03 0 KCP03 KCP02 KCP01 KCP00 KCP02 0 2E4H Input comparison register (K00-K03) KCP01 0 R/W KCP00 0 EIK03 0 Enable Mask EIK03 EIK02 EIK01 EIK00 EIK02 0 Enable Mask 2E5H Interrupt mask register (K00-K03) EIK01 0 Enable Mask R/W EIK00 0 Enable Mask SCTRG3 Trigger - Serial I/F clock trigger - SCTRG EIK10 KCP10 K10 EIK10 Enable Mask Interrupt mask register (K10) 0 2E7H KCP10 Input comparison register (K10) 0 W R/W R Low Input port data (K10) K10 - 2 High IK1 4 0 Interrupt factor flag (K10) Yes No IK1 IK0 SWIT1 SWIT0 IK0 4 0 Interrupt factor flag (K00-K03) Yes No 2EAH SWIT1 4 0 Interrupt factor flag (stopwatch 1 Hz) Yes No R SWIT0 4 0 Interrupt factor flag (stopwatch 10 Hz) Yes No 1 Initial value at initial reset 3 Always "0" being read 5 Undefined 2 Not set in the circuit 4 Reset (0) immediately after being read D3 D2 D1 D0 K00-K03, K10: Input port data (2E3H, 2E7H*D0) Input data of the input port terminals can be read out with these registers. When "1" is read out : High level When "0" is read out : Low level Writing : Invalid The read-out is "1" when the terminal voltage of the five bits of the input ports (K00-K03, K10) goes high (VDD), and "0" when the voltage goes low (VSS). These bits are dedicated for read-out, so writing cannot be done. KCP00-KCP03, KCP10: Input comparison registers (2E4H, 2E7H*D1) Interrupt conditions for terminals K00-K03 and K10 can be set with these registers. When "1" is written : Falling edge When "0" is written : Rising edge Read-out : Valid The interrupt conditions can be set for the rising or falling edge of input for each of the five bits (K00-K03 and K10), through the input comparison registers (KCP00-KCP03 and KCP10). At initial reset, these registers are set to "0". EIK00-EIK03, EIK10: Interrupt mask registers (2E5H, 2E7H*D2) Masking the interrupt of the input port terminals can be selected with these registers. When "1" is written : Enable When "0" is written : Mask Read-out : Valid With these registers, masking of the input port bits can be selected for each of the five bits. Writing to the interrupt mask registers can be done only in the DI status (interrupt flag = "0"). At initial reset, these registers are all set to "0". 22 EPSON S1C60N16 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) IK0, IK1: Interrupt factor flags (2EAH*D2 and D3) These flags indicate the occurrence of input interrupt. When "1" is read out : Interrupt has occurred When "0" is read out : Interrupt has not occurred Writing : Invalid The interrupt factor flags IK0 and IK1 are associated with K00-K03 and K10, respectively. From the status of these flags, the software can decide whether an input interrupt has occurred. These flags are reset when the software reads them. Read-out can be done only in the DI status (interrupt flag = "0"). At initial reset, these flags are set to "0". 4.4.5 Programming notes (1) When input ports are changed from high to low by pull-down resistance, the fall of the waveform is delayed on account of the time constant of the pull-down resistance and input gate capacitance. Hence, when fetching input ports, set an appropriate wait time. Particular care needs to be taken of the key scan during key matrix configuration. Aim for a wait time of about 1 msec. (2) When "Use" is selected with the noise rejector mask option, a maximum delay of 1 msec occurs from time the interrupt conditions are established until the interrupt factor flag (IK) is set to "1" (until the interrupt is actually generated). Hence, pay attention to the timing when reading out (resetting) the interrupt factor flag. For example, when performing a key scan with the key matrix, the key scan changes the input status to set the interrupt factor flag, so it has to be read out to reset it. However, if the interrupt factor flag is read out immediately after key scanning, the delay will cause the flag to be set after read-out, so that it will not be reset. (3) Input interrupt programming related precautions Port K input Active status Active status Input comparison register Falling edge interrupt Rising edge interrupt Mask register Factor flag set Not set Factor flag set When the content of the mask register is rewritten while the port K input is in the active status, the input interrupt factor flags are set at and , being the interrupt due to the falling edge and the interrupt due to the rising edge. Fig. 4.4.5.1 Input interrupt timing When using an input interrupt, if you rewrite the content of the mask register, when the value of the input terminal which becomes the interrupt input is in the active status, the factor flag for input interrupt may be set. Therefore, when using the input interrupt, the active status of the input terminal implies input terminal = low status, when the falling edge interrupt is effected and input terminal = high status, when the rising edge interrupt is effected. When an interrupt is triggered at the falling edge of an input terminal, a factor flag is set with the timing of shown in Figure 4.4.5.1. However, when clearing the content of the mask register with the input terminal kept in the low status and then setting it, the factor flag of the input interrupt is again set at the timing that has been set. S1C60N16 TECHNICAL MANUAL EPSON 23 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) Consequently, when the input terminal is in the active status (low status), do not rewrite the mask register (clearing, then setting the mask register), so that a factor flag will only set at the falling edge in this case. When clearing, then setting the mask register, set the mask register, when the input terminal is not in the active status (high status). When an interrupt is triggered at the rising edge of the input terminal, a factor flag will be set at the timing of shown in Figure 4.4.5.1. In this case, when the mask registers cleared, then set, you should set the mask register, when the input terminal is in the low status. In addition, when the mask register = "1" and the content of the input comparison register is rewritten in the input terminal active status, an input interrupt factor flag may be set. Thus, you should rewrite the content of the input comparison register in the mask register = "0" status. (4) Read out the interrupt factor flag (IK) only in the DI status (interrupt flag = "0"). Read-out during EI status (interrupt flag = "1") will cause malfunction. (5) Write the interrupt mask register (EIK) only in the DI status (interrupt flag = "0"). Writing during EI status (interrupt flag = "1") will cause malfunction. 24 EPSON S1C60N16 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) 4.5 Output Ports (R00-R03, R10-R13) 4.5.1 Configuration of output ports The S1C60N16 Series has eight bits (4 bits x 2) of general output ports. Output specifications of the output ports can be selected individually with the mask option. Two kinds of output specifications are available: complementary output and Pch open drain output. Further, the mask option enables the output ports R10-R13 to be used as special output ports. Figure 4.5.1.1 shows the configuration of the output ports. Data bus VDD Register Rxx Complementary Pch open drain Address VSS Mask option Fig. 4.5.1.1 Configuration of output ports 4.5.2 Mask option The mask option enables the following output port selection. (1) Output specifications of output ports Output specifications for the output ports (R00-R03, R10-R13) enable selection of either complementary output or Pch open drain output for each of the eight bits. However, even when Pch open drain output is selected, voltage exceeding source voltage must not be applied to the output port. (2) Special output In addition to the regular DC output, special output can be selected for the output ports R10-R13 as shown in Table 4.5.2.1. Figure 4.5.2.1 shows the structure of the output ports R10-R13. Table 4.5.2.1 Special output Output port R10 R13 R11 R12 S1C60N16 TECHNICAL MANUAL Special output BZ output BZ output (selectable only when R10 is used as BZ output) SIOF output FOUT output EPSON 25 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) BZ R10 Register R10 R13 Data bus Register R13 SIOF R11 Register R11 FOUT R12 Register R12 Address 2ECH Mask option Fig. 4.5.2.1 Structure of output port R10-R13 BZ, BZ (R10, R13) BZ and BZ are the buzzer signal output for driving the piezoelectric buzzer. The buzzer signal is generated by demultiplicaion of fOSC1. The buzzer signal frequency can be selected by software. Also, a digital envelope can be added to the buzzer signal. See Section 4.11, "Sound Generator", for details. Notes: * When the BZ and BZ output signals are turned ON or OFF, a hazard can result. * When DC output is set for the output port R10, the output port R13 cannot be set for BZ output. Figure 4.5.2.2 shows the output waveform for BZ and BZ. R00(R03) register "0" "1" "0" BZ output (R10 terminal) BZ output (R13 terminal) Fig. 4.5.2.2 Output waveform of BZ and BZ SIOF (R11) When the output port R11 is set for SIOF output, it outputs the signal indicating the running status (RUN/STOP) of the serial interface. See Section 4.7, "Serial Interface", for details. FOUT (R12) When the output port R12 is set for FOUT output, it outputs the clock of fOSC1 or the demultiplied fOSC1. The clock frequency is selectable with the mask options, from the frequencies listed in Table 4.5.2.2. Table 4.5.2.2 FOUT clock frequency Setting value fOSC1 / 1 fOSC1 / 2 fOSC1 / 4 fOSC1 / 8 fOSC1 / 16 fOSC1 / 32 fOSC1 / 64 fOSC1 / 128 Clock frequency (Hz) * 32,768 16,384 8,192 4,096 2,048 1,024 512 256 When fOSC1 = 32.768 kHz Note: A hazard may occur when the FOUT signal is turned ON or OFF. 26 EPSON S1C60N16 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) 4.5.3 Control of output ports Table 4.5.3.1 lists the output ports' control bits and their addresses. Table 4.5.3.1 Control bits of output ports Address Register D3 D2 D1 D0 R03 R02 R01 R00 2EBH R/W R11 R13 R12 2ECH SIOF R10 R/W R/W R R/W Name R03 R02 R01 R00 R13 R12 R11 SIOF R10 1 Initial value at initial reset 2 Not set in the circuit Comment 1 0 Init 1 0 High Low Output port (R03) 0 High Low Output port (R02) 0 High Low Output port (R01) 0 High Low Output port (R00) 0 High/On Low/Off Output port (R13)/BZ output control 0 High/On Low/Off Output port (R12)/FOUT output control 0 High Low Output port (R11) 0 Run Stop Output port (SIOF) 0 High/On Low/Off Output port (R10)/BZ output control 3 Always "0" being read 5 Undefined 4 Reset (0) immediately after being read R00-R03, R10-R13 (when DC output): Output port data (2EBH, 2ECH) Sets the output data for the output ports. When "1" is written : High output When "0" is written : Low output Read-out : Valid The output port terminals output the data written in the corresponding registers (R00-R03, R10-R13) without changing it. When "1" is written in the register, the output port terminal goes high (VDD), and when "0" is written, the output port terminal goes low (VSS). At initial reset, all registers are set to "0". R10, R13 (when BZ and BZ output is selected): Buzzer output control (2ECH*D0 and D3) These bits control the output of the buzzer signals (BZ, BZ). When "1" is written : Buzzer signal is output When "0" is written : Low level (DC) is output Read-out : Valid BZ is output from terminal R13. With the mask option, selection can be made perform this output control by R13, or to perform output control simultaneously with BZ by R10. * When R13 controls BZ output BZ output and BZ output can be controlled independently. BZ output is controlled by writing data to R10, and BZ output is controlled by writing data to R13. * When R10 controls BZ output BZ output and BZ output can be controlled simultaneously by writing data to R10 only. For this case, R13 can be used as a one-bit general register having both read and write functions, and data of this register exerts no affect on BZ output (output from the R13 pin). At initial reset, registers R10 and R13 are set to "0". R11 (when SIOF output is selected): Serial interface status (2ECH*D1) Indicates the running status of the serial interface. When "1" is read out : RUN When "0" is read out : STOP Writing : Valid See Section 4.7, "Serial Interface", for details of SIOF. This bit is exclusively for reading out, so data cannot be written to it. S1C60N16 TECHNICAL MANUAL EPSON 27 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) R12 (when FOUT is selected): FOUT output control (2ECH*D2) Controls the FOUT (clock) output. When "1" is written : Clock output When "0" is written : Low level (DC) output Read-out : Valid FOUT output can be controlled by writing data to R12. At initial reset, this register is set to "0". 4.5.4 Programming note When BZ, BZ and FOUT are selected with the mask option, a hazard may be observed in the output waveform when the data of the output register changes. 28 EPSON S1C60N16 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) 4.6 I/O Ports (P00-P03, P10-P13) 4.6.1 Configuration of I/O ports Data bus The S1C60N16 Series has eight bits (4 bits x 2) of general-purpose I/O ports. Figure 4.6.1.1 shows the configuration of the I/O ports. The four bits of each of the I/O ports P00-P03 and P10-P13 can be set to either input mode or output mode. Modes can be set by writing data to the I/O control register. Input control Register P Address Address I/O control register VSS Fig. 4.6.1.1 Configuration of I/O port The P10-P12 I/O port terminals are shared with the serial interface input/output terminals and the serial interface is enabled by mask option. 4.6.2 Mask option (1) Output specification The output specification during output mode (IOC = "1") of these I/O ports can be set with the mask option for either complementary output or Pch open drain output. This setting can be performed for each bit of each port. However, when Pch open drain output has been selected, voltage in excess of the power voltage must not be applied to the port. (2) Serial interface The serial interface can be enabled by mask option. When the serial interface is enabled, the P10, P11 and P12 terminals are used as the serial I/O port. 4.6.3 I/O control register and I/O mode Input or output mode can be set for the four bits of I/O port P00-P03 and I/O port P10-P13 by writing data into the corresponding I/O control register IOC0 and IOC1. To set the input mode, "0" is written to the I/O control register. When an I/O port is set to input mode, it becomes high impedance status and works as an input port. However, the input line is pulled down when input data is read. The output mode is set when "1" is written to the I/O control register. When an I/O port set to output mode works as an output port, it outputs a high signal (VDD) when the port output data is "1", and a low signal (VSS) when the port output data is "0". At initial reset, the I/O control registers are set to "0", and the I/O port enters the input mode. When the serial interface is used, the IOC1 register controls only the P13 port. S1C60N16 TECHNICAL MANUAL EPSON 29 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) 4.6.4 Control of I/O ports Table 4.6.4.1 lists the I/O ports' control bits and their addresses. Table 4.6.4.1 I/O port control bits Address Register D3 D2 D1 P03 P02 P01 2EDH R/W TMRST SWRUN SWRST 2EEH W R/W W P13 P12 P11 2FDH R/W 0 CLKCHG OSCC 2FEH R 1 Initial value at initial reset 2 Not set in the circuit R/W Comment 1 0 Name Init 1 P03 Low - 2 High P00 - 2 High I/O port data (P00-P03) P02 Low - 2 High Output latch is reset at initial reset P01 Low - 2 High P00 Low TMRST3 Reset Reset Clock timer reset - IOC0 SWRUN 0 Run Stop Stopwatch timer Run/Stop SWRST3 Reset Reset Stopwatch timer reset - R/W IOC0 0 Output Input I/O control register 0 (P00-P03) P13 - 2 High Low P10 - 2 High I/O port data (P10-P13) P12 Low - 2 High Output latch is reset at initial reset P11 Low - 2 High P10 Low 0 3 Unused - 2 - - IOC1 CLKCHG 0 OSC3 OSC1 CPU clock switch OSCC 0 OSC3 oscillation On/Off On Off IOC1 0 Output Input I/O control register (P10-P13) 3 Always "0" being read 5 Undefined 4 Reset (0) immediately after being read D0 P00-P03, P10-P13: I/O port data (2EDH, 2FDH) I/O port data can be read and output data can be set through these ports. When writing data When "1" is written : High level When "0" is written : Low level When an I/O port is set to the output mode, the written data is output unchanged from the I/O port terminal. When "1" is written as the port data, the port terminal goes high (VDD), and when "0" is written, the level goes low (VSS). Port data can be written also in the input mode. When reading data out When "1" is read out : High level When "0" is read out : Low level The terminal voltage level of the I/O port is read out. When the I/O port is in the input mode the voltage level being input to the port terminal can be read out; in the output mode the output voltage level can be read. When the terminal voltage is high (VDD) the port data that can be read is "1", and when the terminal voltage is low (VSS) the data is "0". Further, the built-in pull-down resistance goes ON during read-out, so that the I/O port terminal is pulled down. The data registers of the ports (P10-P12) that are set as input/output for the serial interface can be used as general purpose registers that do not affect the input/output. Notes: * When the I/O port is set to the output mode and a low-impedance load is connected to the port terminal, the data written to the register may differ from the data read out. * When the I/O port is set to the input mode and a low-level voltage (VSS) is input, erroneous input results if the time constant of the capacitive load of the input line and the built-in pull-down resistance load is greater than the read-out time. When the input data is being read out, the time that the input line is pulled down is equivalent to 1.5 cycles of the CPU system clock. However, the electric potential of the terminals must be settled within 0.5 cycles. If this condition cannot be fulfilled, some measure must be devised such as arranging pull-down resistance externally, or performing multiple read-outs. 30 EPSON S1C60N16 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) IOC0, IOC1: I/O control registers (2EEH*D0, 2FEH*D0) The input and output modes of the I/O ports can be set with these registers. When "1" is written : Output mode When "0" is written : Input mode Read-out : Valid The input and output modes of the I/O ports are set in units of four bits. IOC0 sets the mode for P00-P03, and IOC1 sets the mode for P10-P13. Writing "1" to the I/O control register makes the corresponding I/O port enter the output mode, and writing "0" induces the input mode. At initial reset, these two registers are set to "0", so the I/O ports are in the input mode. When the serial interface is used, the IOC1 register controls only the P13 port. 4.6.5 Programming notes (1) When input data are changed from high to low by built-in pull-down resistance, the fall of the waveform is delayed on account of the time constant of the pull-down resistance and input gate capacitance. Consequently, if data is read out while the CPU is running in the OSC3 oscillation circuit, data must be read out continuously for about 500 sec. (2) When the I/O port is set to the output mode and the data register has been read, the terminal data instead of the register data can be read out. Because of this, if a low-impedance load is connected and read-out performed, the value of the register and the read-out result may differ. S1C60N16 TECHNICAL MANUAL EPSON 31 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) 4.7 Serial Interface 4.7.1 Configuration of serial interface The S1C60N16 Series has a built-in synchronous clock type 8 bits serial interface that can be enabled by mask option. The configuration of the serial interface is shown in Figure 4.7.1.1. The CPU, via the 8 bits shift register, can read the serial input data from the SIN (P10) terminal. Moreover, via the same 8 bits shift register, it can convert parallel data to serial data and output it to the SOUT (P11) terminal. The synchronous clock for serial data input/output may be set by selecting by software any one of 3 types of master mode (internal clock mode: when the S1C60N16 Series is to be the master for serial input/output) and a type of slave mode (external clock mode: when the S1C60N16 Series is to be the slave for serial input/output). Furthermore, the R11 output port can be configured to output the SIOF signal, which indicates whether the serial interface in master or slave mode is ready to transmit/receive or not, by mask option. Also this option enables the SIOF (2ECH*D1) bit that indicates the serial interface operating status. SD0-SD7 Shift register (8 bits) SIN (P10) SCS0 SE2 SCS1 Serial clock selector SCLK (P12) Output latch Serial clock generator SCTRG Serial clock counter Serial I/F interrupt control circuit System clock Serial I/F activating circuit SOUT (P11) ISIO EISIO SIOF (R11) Fig. 4.7.1.1 Configuration of serial interface The SIN (P10) and SCLK (P12) terminals have a pull-down resistor. However, the SCLK (P12) terminal is pulled down to low in external clock mode and the pull-down resistor is disabled in internal clock mode. 4.7.2 Mask option The serial interface may be selected for the following by mask option. (1) Whether the serial interface is used or not may be selected. When "use" is selected, the following I/O port terminals are configured as the serial I/O terminals. P10 SIN (data input) P11 SOUT (data output) P12 SCLK (clock input/output) (2) Either complementary output or Pch open drain as output specification for the SOUT (P11) terminal may be selected. However, even if Pch open drain has been selected, application of voltage exceeding power source voltage to the SOUT (P11) terminal will be prohibited. (3) As output specification during output mode, either complementary output or Pch open drain output may be selected for the SCLK (P12) terminal. (4) Positive or negative logic can be selected for the signal logic of the SIO function. However, keep in mind that only pull-down resistance can be set for the input mode (pull-up resistance is not built-in). 32 EPSON S1C60N16 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) (5) LSB first or MSB first as input/output permutation of serial data may be selected in the SIO function. (6) The output port R11 (see Section 4.5, "Output Ports") can be configured as the SIOF signal output port to notify the external serial device whether the internal serial interface is ready to transmit/receive data or not. Also this option switches the function of the R11 output port data bit (2ECH*D1) to indicate the SIOF signal. When this option is selected, the R11 terminal cannot be used as a generalpurpose output port and the R11 port data bit (2ECH*D1) cannot be used for setting the output signal. 4.7.3 Master mode and slave mode of serial interface The serial interface of the S1C60N16 Series has two types of operation mode: master mode and slave mode. In the master mode, it uses an internal clock as synchronous clock of the built-in shift register, generates this internal clock at the SCLK (P12) terminal and controls the external (slave side) serial device. In the slave mode, the synchronous clock output from the external (master side) serial device is input from the SCLK (P12) terminal and uses it as the synchronous clock to the built-in shift register. The master mode and slave mode are selected by writing data to registers SCS1 and SCS0 (address 2F2H*D2, D3). When the master mode is selected, a synchronous clock may be selected from among 3 types as shown in Table 4.7.3.1. Table 4.7.3.1 Synchronous clock selection SCS1 0 0 1 1 SCS0 0 1 0 1 Mode Master mode Slave mode Synchronous clock CLK CLK/2 CLK/4 External clock CLK: CPU system clock At initial reset, the slave mode (external clock mode) is selected. Moreover, the synchronous clock, along with the input/output of the 8 bits serial data, is controlled as follows: * At master mode, after output of 8 clocks from the SCLK (P12) terminal, clock output is automatically suspended and SCLK (P12) terminal is fixed at low level. * At slave mode, after input of 8 clocks to the SCLK (P12) terminal, subsequent clock inputs are masked. Note: When using the serial interface in the master mode, CPU system clock is used as the synchronous clock. Accordingly, when the serial interface is operating, system clock switching (fOSC1 fOSC3) should not be performed. A sample basic serial input/output portion connection is shown in Figure 4.7.3.1. SCLK (P12) External serial device CLK SCLK (P12) External serial device CLK SOUT (P11) SOUT SOUT (P11) SOUT S1C60N16 SIN (P10) S1C60N16 SIN (P10) SIN Input terminal READY SIN R11(SIOF) Master mode Input terminal Slave mode Fig. 4.7.3.1 Sample basic connection S1C60N16 TECHNICAL MANUAL EPSON 33 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) 4.7.4 Data input/output and interrupt function The serial interface can input/output data via the internal 8 bits shift register. The shift register operates by synchronizing with either the synchronous clock output from SCLK (P12) terminal (master mode), or the synchronous clock input to SCLK (P12) (slave mode). The serial interface generates interrupt on completion of the 8 bits serial data input/output. Detection of serial data input/output is done by the counting of the synchronous clock (SCLK); the clock completes input/output operation when 8 counts (equivalent to 8 cycles) have been made and then generates interrupt. The serial data input/output procedure data is explained below: (1) Serial data output procedure and interrupt The serial interface is capable of outputting parallel data as serial data, in units of 8 bits. By setting the parallel data to 4 bits registers SD0-SD3 (address 2F0H) and SD4-SD7 (address 2F1H) individually and writing "1" to SCTRG bit (address 2E7H*D3), it synchronizes with the synchronous clock and serial data is output at the SOUT (P11) terminal. The synchronous clock used here is as follows: in the master mode, internal clock which is output to the SCLK (P12) terminal while in the slave mode, external clock which is input from the SCLK (P12) terminal. The serial output of the SOUT (P11) terminal changes with the rising edge of the clock that is input or output from the SCLK (P12) terminal. The serial data to the built-in shift register is shifted with the rising edge of the SCLK signal when SE2 bit (address 2F2H*D1) is "1" and is shifted with the falling edge of the SCLK signal when SE2 bit (address 2F2H*D1) is "0". When the output of the 8 bits data from SD0 to SD7 is completed, the interrupt factor flag ISIO (address 2F3H*D0) is set to "1" and interrupt is generated. Moreover, the interrupt can be masked by the interrupt mask register EISIO (address 2F2H*D0). (2) Serial data input procedure and interrupt The serial interface is capable of inputting serial data as parallel data, in units of 8 bits. The serial data is input from the SIN (P10) terminal, synchronizes with the synchronous clock, and is sequentially read in the 8 bits shift register. As in the above item (1), the synchronous clock used here is as follows: in the master mode, internal clock which is output to the SCLK (P12) terminal while in the slave mode, external clock which is input from the SCLK (P12) terminal. The serial data to the built-in shift register is read with the rising edge of the SCLK signal when SE2 bit is "1" and is read with the falling edge of the SCLK signal when SE2 bit is "0". Moreover, the shift register is sequentially shifted as the data is fetched. When the input of the 8 bits data from SD0 to SD7 is completed, the interrupt factor flag ISIO is set to "1" and interrupt is generated. Moreover, the interrupt can be masked by the interrupt mask register EISIO. Note, however, that regardless of the setting of the interrupt mask register, the interrupt factor flag is set to "1" after input of the 8 bits data. The data input in the shift register can be read from data registers SD0-SD7 by software. (3) Serial data input/output permutation The S1C60N16 Series allows the input/output permutation of serial data to be selected by mask option as to either LSB first or MSB first. The block diagram showing input/output permutation in case of LSB first and MSB first is provided in Figure 4.7.4.1. SIN Address [2F1H] SD7 SD6 SD5 SD4 Address [2F0H] SD3 SD2 SD1 SD0 Output latch SOUT Output latch SOUT In case of LSB first SIN Address [2F0H] SD0 SD1 SD2 SD3 Address [2F1H] SD4 SD5 SD6 SD7 In case of MSB first Fig. 4.7.4.1 Serial data input/output permutation 34 EPSON S1C60N16 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) (4) SIOF signal The SIOF signal can be output from the R11 terminal regardless of the set mode, master or slave, by mask option. For example, when the serial interface is used in slave mode (external clock mode), the SIOF signal is used to notify the master (external) serial device whether the internal serial interface is ready to transmit/receive data or not. In master mode, the serial interface operating status can be checked by reading the status bit SIOF (2ECH*D1). The SIOF signal and the SIOF bit (2ECH*D1) go "1" (high) when the S1C60N16 serial interface becomes ready to transmit/receive data; normally they are "0" (low). The SIOF signal and the SIOF bit (2ECH*D1) change from "0" to "1" immediately after "1" is written to the SCTRG bit and return from "1" to "0" when eight synchronous clocks (eight cycles) have been counted. (5) Timing chart The serial interface timing chart is shown in Figure 4.7.4.2. SCTRG SCLK SIN 8-bit shift register SOUT ISIO SIOF (a) SE2 = "1" SCTRG SCLK SIN 8-bit shift register SOUT ISIO SIOF (b) SE2 = "0" Fig. 4.7.4.2 Serial interface timing chart S1C60N16 TECHNICAL MANUAL EPSON 35 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) 4.7.5 Control of serial interface The control registers for the serial interface are explained below. Table 4.7.5.1 Control bits of serial interface Address Register D3 D2 D1 SCTRG IK10 KCP10 2E7H W R/W R11 R13 R12 SIOF 2ECH R/W R/W SD3 R SD2 SD1 2F0H R/W SD7 SD6 SD5 2F1H R/W SCS1 SCS0 SE2 2F2H R/W 0 0 0 2F3H R 1 Initial value at initial reset 2 Not set in the circuit Comment Name Init 1 1 0 SCTRG3 Trigger - Serial I/F clock trigger - K10 EIK0 Enable Mask Interrupt mask register (K10) 0 KCP10 Input comparison register (K10) 0 R Low Input port data (K10) K10 - 2 High R13 0 High/On Low/Off Output port (R13)/BZ output control R10 R12 0 High/On Low/Off Output port (R12)/FOUT output control R11 0 High Low Output port (R11) Output port (SIOF) SIOF 0 Run Stop R/W R10 0 High/On Low/On Output port (R10)/BZ output control SD3 x 5 SD0 x 5 SD2 Serial I/F data register (low-order 4 bits) x 5 SD1 x 5 SD0 SD7 x 5 SD4 x 5 SD6 Serial I/F data register (high-order 4 bits) x 5 SD5 x 5 SD4 [SCS1, 0] 0 1 2 3 SCS1 Serial I/F clock 1 EISIO Clock CLK CLK/2 CLK/4 Slave SCS0 mode selection 1 SE2 Serial I/F clock edge selection 0 EISIO 0 Enable Mask Interrupt mask register (serial I/F) 0 3 - 2 Unused - - ISIO 0 3 - 2 Unused - - 0 3 - 2 Unused - - ISIO 4 0 Interrupt factor flag (serial I/F) Yes No 3 Always "0" being read 5 Undefined 4 Reset (0) immediately after being read D0 SD0-SD3, SD4-SD7: Serial interface data registers (2F0H, 2F1H) These registers are used for writing and reading serial data. During writing operation When "1" is written : High level When "0" is written : Low level Writes serial data will be output to SOUT (P11) terminal. From the SOUT (P11) terminal, the data converted to serial data as high (VDD) level bit for bits set at "1" and as low (VSS) level bit for bits set at "0". During reading operation When "1" is read out : High level When "0" is read out : Low level The serial data input from the SIN (P10) terminal can be read by this register. The data converted to parallel data, as high (VDD) level bit "1" and as low (VSS) level bit "0" input from SIN (P10) terminal. Perform data reading only while the serial interface is halted (i.e., the synchronous clock is neither being input or output). At initial reset, these registers will be undefined. 36 EPSON S1C60N16 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) SCS1, SCS0: Clock mode selection register (2F2H*D3, D2) Selects the synchronous clock for the serial interface (SCLK). Table 4.7.5.2 Synchronous clock selection SCS1 0 0 1 1 SCS0 0 1 0 1 Mode Master mode Slave mode Synchronous clock CLK CLK/2 CLK/4 External clock CLK: CPU system clock Synchronous clock (SCLK) is selected from among the above 4 types: 3 types of internal clock and external clock. At initial reset, external clock is selected. SE2: Clock edge selection register (2F2H*D1) Selects the timing for reading in the serial data input. When "1" is written : Rising edge of SCLK When "0" is written : Falling edge of SCLK Read-out : Valid Selects whether the fetching for the serial input data to registers (SD0-SD7) at the rising edge (at "1" writing) or falling edge (at "0" writing) of the SCLK signal. Pay attention if the synchronous clock goes into reverse phase (SCLK SCLK) through the mask option. SCLK rising = SCLK falling, SCLK falling = SCLK rising When the internal clock is selected as the synchronous clock (SCLK), a hazard occurs in the synchronous clock (SCLK) when data is written to register SE2. The input data fetching timing may be selected but output timing for output data is fixed at SCLK rising edge. At initial reset, falling edge of SCLK (SE2 = "0") is selected. EISIO: Interrupt mask register (2F2H*D0) This is the interrupt mask register of the serial interface. When "1" is written : Enabled When "0" is written : Masked Read-out : Valid At initial reset, this register is set to "0" (mask). ISIO: Interrupt factor flag (2F3H*D0) This is the interrupt factor flag of the serial interface. When "1" is read out : Interrupt has occurred When "0" is read out : Interrupt has not occurred Writing : Invalid From the status of this flag, the software can decide whether the serial interface interrupt. The interrupt factor flag is reset when it has been read out. Note, however, that even if the interrupt is masked, this flag will be set to "1" after the 8 bits data input/ output. Be sure that the interrupt factor flag reading is done with the interrupt in the DI status (interrupt flag = "0"). At initial reset, this flag is set to "0". S1C60N16 TECHNICAL MANUAL EPSON 37 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) SCTRG: Clock trigger (2E7H*D3) This is a trigger to start input/output of synchronous clock. When "1" is written : Trigger When "0" is written : No operation Read-out : Always "0" When this trigger is supplied to the serial interface activating circuit, the synchronous clock (SCLK) input/output is started. As a trigger condition, it is required that data writing or reading on data registers SD0-SD7 be performed prior to writing "1" to SCTRG. (The internal circuit of the serial interface is initiated through data writing/reading on data registers SD0-SD7.) Supply trigger only once every time the serial interface is placed in the RUN state. Refrain from performing trigger input multiple times, as leads to malfunctioning. Moreover, when the synchronous clock SCLK is external clock, start to input the external clock after the trigger. SIOF (R11): Serial interface status (2ECH*D1) Indicates the running status of the serial interface. When "1" is read out : RUN status When "0" is read out : STOP status Writing : Invalid The RUN status is indicated from immediately after "1" is written to SCTRG bit through to the end of serial data input/output. The SIOF read only bit can be used only when the R11 port is configured for SIOF output by mask option. 4.7.6 Programming notes (1) If the bit data of SE2 changes while the serial interface is in the master mode, a hazard will be output to the SCLK (P12) terminal. If this poses a problem for the system, be sure to set the SCLK to the external clock if the bit data of SE2 is to be changed. (2) Be sure that read-out of the interrupt factor flag (ISIO) is done only when the serial port is in the STOP status (SIOF = "0") and the DI status (interrupt flag = "0"). If read-out is performed while the serial data is in the RUN status (during input or output), the data input or output will be suspended and the initial status resumed. Read-out during the EI status (interrupt flag = "1") causes malfunctioning. (3) When using the serial interface in the master mode, the synchronous clock uses the CPU system clock. Accordingly, do not change the system clock (fOSC1 fOSC3) while the serial interface is operating. (4) Perform data writing/reading to data registers SD0-SD7 only while the serial interface is halted (i.e., the synchronous clock is neither being input or output). (5) As a trigger condition, it is required that data writing or reading on data registers SD0-SD7 be performed prior to writing "1" to SCTRG. (The internal circuit of the serial interface is initiated through data writing/reading on data registers SD0-SD7.) Supply trigger only once every time the serial interface is placed in the RUN state. Moreover, when the synchronous clock SCLK is external clock, start to input the external clock after the trigger. (6) Be sure that writing to the interrupt mask register is done only in the DI status (interrupt flag = "0"). Writing to the interrupt mask register while in the EI status (interrupt flag = "1") may cause malfunction. 38 EPSON S1C60N16 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) 4.8 LCD Driver (COM0-COM3, SEG0-SEG37) 4.8.1 Configuration of LCD driver The S1C60N16 Series has four common terminals and 38 (SEG0-SEG37) segment terminals, so that an LCD with a maximum of 152 (38 x 4) segments can be driven. The power for driving the LCD is generated by the internal circuit, so there is no need to supply power externally. The driving method is 1/4 duty (or 1/3, 1/2 duty is selectable by mask option) dynamic drive, adopting the four types of potential (1/3 bias), VSS, VC1, VC2 and VC3. In the S1C60A16, the 1/2 bias dynamic drive that uses three types of potential, VSS, VC1 = VC2 and VC3, can be selected by setting the mask option (drive duty can also be selected from 1/4, 1/3 or 1/2). 1/2 bias drive is effective when the LCD system voltage regulator is not used. The VC1 terminal and the VC2 terminal should be connected outside the IC. The frame frequency is 32 Hz for 1/4 duty and 1/2 duty, and 42.7 Hz for 1/3 duty (in the case of fOSC1 = 32.768 kHz). Figures 4.8.1.1 to 4.8.1.6 show the drive waveform for each duty and bias. Note: "fOSC1" indicates the oscillation frequency of the oscillation circuit. S1C60N16 TECHNICAL MANUAL EPSON 39 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) VC3 VC2 VC1 VSS COM0 COM1 LCD lighting status COM0 COM1 COM2 COM3 COM2 SEG0-37 COM3 Off On VC3 VC2 VC1 VSS SEG0 -SEG37 Frame frequency Fig. 4.8.1.1 Drive waveform for 1/4 duty (1/3 bias) 40 EPSON S1C60N16 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) VC3 VC2 VC1 VSS COM0 COM1 LCD lighting status COM0 COM1 COM2 SEG0-37 COM2 Off On COM3 VC3 VC2 VC1 VSS SEG0 -SEG37 Frame frequency Fig. 4.8.1.2 Drive waveform for 1/3 duty (1/3 bias) VC3 VC2 VC1 VSS COM0 COM1 LCD lighting status COM0 COM1 SEG0-37 COM2 COM3 VC3 VC2 VC1 VSS Off On SEG0 -SEG37 Frame frequency Fig. 4.8.1.3 Drive waveform for 1/2 duty (1/3 bias) S1C60N16 TECHNICAL MANUAL EPSON 41 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) -VC3 -VC1, C2 -VSS COM0 COM1 LCD lighting status COM0 COM1 COM2 COM3 SEG0-37 COM2 Off On COM3 -VC3 -VC1, C2 -VSS SEG 0-37 Frame frequency Fig. 4.8.1.4 Drive waveform for 1/4 duty (1/2 bias) 42 EPSON S1C60N16 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) -VC3 -VC1, C2 -VSS COM0 COM1 LCD lighting status COM0 COM1 COM2 SEG0-37 COM2 Off On COM3 -VC3 -VC1, C2 -VSS SEG 0-37 Frame frequency Fig. 4.8.1.5 Drive waveform for 1/3 duty (1/2 bias) -VC3 -VC1, C2 -VSS COM0 COM1 LCD lighting status COM0 COM1 SEG0-37 COM2 Off On COM3 -VC3 -VC1, C2 -VSS SEG 0-37 Frame frequency Fig. 4.8.1.6 Drive waveform for 1/2 duty (1/2 bias) S1C60N16 TECHNICAL MANUAL EPSON 43 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) 4.8.2 Cadence adjustment of oscillation frequency In the S1C60N16 Series, the LCD drive duty can be set to 1/1 duty by software. This function enables easy adjustment (cadence adjustment) of the oscillation frequency of the oscillation circuit. The procedure to set to 1/1 duty drive is as follows: Write "1" to the CSDC1 register at address 2E8H*D3. Write the same value to all registers corresponding to COMs 0 through 3 of the display memory. The frame frequency is 32 Hz (fOSC1/1,024, when fOSC1 = 32.768 kHz). Notes: * Even when l/3 or 1/2 duty is selected by the mask option, the display data corresponding to all COM are valid during 1/1 duty driving. Hence, for 1/1 duty drive, set the same value for all display memory corresponding to COMs 0 through 3. * For cadence adjustment, set the display data corresponding to COMs 0 through 3, so that all the LCD segments go on. Figures 4.8.2.1 and 4.8.2.2 show the 1/1 duty drive waveform in 1/3 bias and 1/2 bias driving. LCD lighting status -VC3 -VC2 -VC1 -VSS COM 0-3 COM0 COM1 COM2 COM3 Frame frequency SEG0-37 Off On -VC3 -VC2 -VC1 -VSS SEG 0-37 -VC3 -VC2 -VC1 -VSS Fig. 4.8.2.1 Drive waveform for 1/1 duty (1/3 bias) LCD lighting status -VC3 -VC1, VC2 -VSS COM 0-3 COM0 COM1 COM2 COM3 Frame frequency Off SEG0-37 On -VC3 -VC1, VC2 -VSS SEG 0-37 -VC3 -VC1, VC2 -VSS Fig. 4.8.2.2 Drive waveform for 1/1 duty (1/2 bias) 44 EPSON S1C60N16 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) 4.8.3 Mask option (segment allocation) (1) Segment allocation As shown in Figure 4.1.2, segment data of the S1C60N16 Series is decided depending on display data written to the display memory at address 040H-065H (Page 0) or 240H-265H (Page 2). * The mask option enables the display memory to be allocated entirely to either Page 0 or Page 2. * The address and bits of the display memory can be made to correspond to the segment terminals (SEG0-SEG37) in any form through the mask option. This makes design easy by increasing the degree of freedom with which the liquid crystal panel can be designed. Figure 4.8.3.1 shows an example of the relationship between the LCD segments (on the panel) and the display memory (when page 0 is selected) for the case of 1/3 duty. Address Common 0 Common 1 Common 2 9A, D0 9B, D1 9B, D0 (a) (f) (e) SEG11 9A, D1 9B, D2 9A, D3 (b) (g) (d) SEG12 9D, D1 9A, D2 9B, D3 (f') (c) (p) Data D3 D2 D1 D0 09AH d c b a 09BH p g f e 09CH d' c' b' a' 09DH p' g' f' e' SEG10 Display data memory allocation Pin address allocation a a' b f e g' c d SEG10 SEG11 Common 0 b' f' g c' e' p p' d' SEG12 Common 1 Common 2 Fig. 4.8.3.1 Segment allocation (2) Drive duty According to the mask option, either 1/4, 1/3 or 1/2 duty can be selected as the LCD drive duty. Table 4.8.3.1 shows the differences in the number of segments according to the selected duty. Table 4.8.3.1 Differences according to selected duty Duty COM used 1/4 COM0-COM3 1/3 COM0-COM2 1/2 COM0-COM1 S1C60N16 TECHNICAL MANUAL Max. number of segments Frame frequency * 152 (38 x 4) fOSC1/1,024 (32 Hz) 114 (38 x 3) fOSC1/768 (42.7 Hz) 76 (38 x 2) fOSC1/1,024 (32 Hz) When fOSC1 = 32 kHz EPSON 45 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) (3) Output specification * The segment terminals (SEG0-SEG37) are selected by mask option in pairs for either segment signal output or DC output (VDD and VSS binary output). When DC output is selected, the data corresponding to COM0 of each segment terminal is output. * When DC output is selected, either complementary output or Pch open drain output can be selected for each terminal by mask option. Note: The terminal pairs are the combination of SEG (2n) and SEG (2n + 1) (where n is an integer from 0 to 18). (4) Drive bias For the drive bias of the S1C60A16, either 1/3 bias or 1/2 bias can be selected by the mask option. When using the LCD system voltage regulator, it is fixed at 1/3 bias. 4.8.4 Control of LCD driver Table 4.8.4.1 shows the LCD driver's control bits and their addresses. Figure 4.8.4.1 shows the display memory map. Table 4.8.4.1 Control bits of LCD driver Address Register D3 D2 D1 0 0 0 2D0H R CSDC1 ETI2 ETI8 2E8H R/W 1 Initial value at initial reset 2 Not set in the circuit Comment Name Init 1 1 0 0 3 Unused - 2 - - CSDC2 0 3 - 2 Unused - - 0 3 - 2 Unused - - R/W CSDC2 1 Normal All off LCD all off control CSDC1 0 Static Dynamic LCD drive switch ETI32 ETI2 0 Enable Mask Interrupt mask register (clock timer 2 Hz) ETI8 0 Enable Mask Interrupt mask register (clock timer 8 Hz) ETI32 0 Enable Mask Interrupt mask register (clock timer 32 Hz) 3 Always "0" being read 5 Undefined 4 Reset (0) immediately after being read D0 Address Low 0 Page High 4 5 0 or 2 6 1 2 3 4 5 6 7 8 9 A B C D E F Display memory (38 words x 4 bits) Page 0: R/W, Page 2: W only Unused area Fig. 4.8.4.1 Display memory map CSDC2: LCD all Off control (2D0H*D0) Controls the LCD display. When "1" is written : LCD displayed When "0" is written : LCD is all off Read-out : Valid By writing "0" to the CSDC2 register, all the LCD dots goes off, and when "1" is written, it returns to normal display. Writing "0" outputs an off waveform to the SEG terminals, and does not affect the content of the display memory. After an initial reset, CSDC2 is set to "1". CSDC1: LCD drive switch (2E8H*D3) The LCD drive format can be selected with this switch. When "1" is written : Static drive When "0" is written : Dynamic drive Read-out : Valid At initial reset, dynamic drive (CSDC1 = "0") is selected. 46 EPSON S1C60N16 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) Display memory (040H-065H or 240H-265H) The LCD segments are lit or turned off depending on this data. When "1" is written : Lit When "0" is written : Not lit Read-out : Valid for Page 0 Undefined Page 2 By writing data into the display memory allocated to the LCD segment (on the panel), the segment can be lit or put out. At initial reset, the contents of the display memory are undefined. 4.8.5 Programming notes (1) When Page 0 is selected for the display memory, the memory data and the display will not match until the area is initialized (through, for instance, memory clear processing by the CPU). Initialize the display memory by executing initial processing. (2) When Page 2 is selected for the display memory, that area becomes write-only. Consequently, data cannot be rewritten by arithmetic operations (such as AND, OR, ADD, SUB). S1C60N16 TECHNICAL MANUAL EPSON 47 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) 4.9 Clock Timer 4.9.1 Configuration of clock timer The S1C60N16 Series has a built-in clock timer that uses OSC1 (crystal oscillator) as the source oscillator. The clock timer is configured of a seven-bit binary counter that serves as the input clock, a 256 Hz signal output by the divider. Data of the four high-order bits (16 Hz-2 Hz) can be read out by the software. Figure 4.9.1.1 is the block diagram for the clock timer. Data bus Clock Timer OSC1 oscillation circuit 256 Hz Divider 128 Hz-32 Hz 16 Hz-2 Hz Watchdog timer 32 Hz, 8 Hz, 2 Hz Interrupt control Clock timer reset signal Interrupt request Fig. 4.9.1.1 Clock timer block diagram Ordinarily, this clock timer is used for all types of timing functions such as clocks. 4.9.2 Interrupt function The clock timer can cause interrupts at the falling edge of 32 Hz, 8 Hz and 2 Hz signals. Software can set whether to mask any of these frequencies. Figure 4.9.2.1 is the timing chart of the clock timer. Address Register Frequency 2E0H D0 16 Hz D1 8 Hz D2 4 Hz D3 2 Hz Clock timer timing chart 32 Hz interrupt request 8 Hz interrupt request 2 Hz interrupt request Fig. 4.9.2.1 Clock timer timing chart As shown in Figure 4.9.2.1, interrupt is generated at the falling edge of the frequencies (32 Hz, 8 Hz , 2 Hz). At this time, the corresponding interrupt factor flag (TI32, TI8, TI2) is set to "1". Selection of whether to mask the separate interrupts can be made with the interrupt mask registers (ETI32, ETI8, ETI2). However, regardless of the interrupt mask register setting, the interrupt factor flag is set to "1" at the falling edge of the corresponding signal. 48 EPSON S1C60N16 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) 4.9.3 Control of clock timer Table 4.9.3.1 shows the clock timer control bits and their addresses. Table 4.9.3.1 Control bits of clock timer Address Register Comment 1 0 Name Init 1 TM3 Clock timer data (2 Hz) 0 TM3 TM2 TM1 TM0 TM2 Clock timer data (4 Hz) 0 2E0H TM1 Clock timer data (8 Hz) 0 R TM0 Clock timer data (16 Hz) 0 CSDC1 0 Static Dynamic LCD drive switch CSDC1 ETI2 ETI8 ETI32 ETI2 0 Enable Mask Interrupt mask register (clock timer 2 Hz) 2E8H ETI8 0 Enable Mask Interrupt mask register (clock timer 8 Hz) R/W ETI32 0 Enable Mask Interrupt mask register (clock timer 32 Hz) 0 3 - 2 Unused - - 0 TI2 TI8 TI32 TI2 4 0 Interrupt factor flag (clock timer 2 Hz) Yes No 2E9H TI8 4 0 Interrupt factor flag (clock timer 8 Hz) Yes No R TI32 4 0 Interrupt factor flag (clock timer 32 Hz) Yes No TMRST3 Reset Reset Clock timer reset - TMRST SWRUN SWRST IOC0 SWRUN 0 Run Stop Stopwatch timer Run/Stop 2EEH SWRST3 Reset Reset Stopwatch timer reset - W R/W W R/W IOC0 0 Output Input I/O control register 0 (P00-P03) 1 Initial value at initial reset 3 Always "0" being read 5 Undefined 2 Not set in the circuit 4 Reset (0) immediately after being read D3 D2 D1 D0 TM0-TM3: Timer data (2E0H) The 16 Hz-2 Hz timer data of the clock timer can be read out with this register. These four bits are readout only, and writing operations are invalid. At initial reset, the timer data is initialized to "0H". ETI32, ETI8, ETI2: Interrupt mask registers (2E8H*D0-D2) These registers are used to select whether to mask the clock timer interrupt. When "1" is written : Enabled When "0" is written : Masked Read-out : Valid The interrupt mask registers (ETI32, ETI8, ETI2) are used to select whether to mask the interrupt to the separate frequencies (32 Hz, 8 Hz, 2 Hz). Writing to the interrupt mask registers can be done only in the DI status (interrupt flag = "0"). At initial reset, these registers are all set to "0". TI32, TI8, TI2: Interrupt factor flags (2E9H*D0-D2) These flags indicate the status of the clock timer interrupt. When "1" is read out : Interrupt has occurred When "0" is read out : Interrupt has not occurred Writing : Invalid The interrupt factor flags (TI32, TI8, TI2) correspond to the clock timer interrupts of the respective frequencies (32 Hz, 8 Hz, 2 Hz). The software can judge from these flags whether there is a clock timer interrupt. However, even if the interrupt is masked, the flags are set to "1" at the falling edge of the signal. These flags can be reset through being read out by the software. Also, the flags can be read out only in the DI status (interrupt flag = "0"). At initial reset, these flags are set to "0". S1C60N16 TECHNICAL MANUAL EPSON 49 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) TMRST: Clock timer reset (2EEH*D3) This bit resets the clock timer. When "1" is written : Clock timer reset When "0" is written : No operation Read-out : Always "0" The clock timer is reset by writing "1" to TMRST. The clock timer starts immediately after this. No operation results when "0" is written to TMRST. This bit is write-only, and so is always "0" at read-out. 4.9.4 Programming notes (1) When the clock timer has been reset, the interrupt factor flag (TI) may sometimes be set to "1". Consequently, perform flag read-out (reset the flag) as necessary at reset. (2) The input clock of the watchdog timer is the 2 Hz signal of the clock timer, so that the watchdog timer may be counted up at timer reset. (3) Read-out the interrupt factor flag (TI) only during the DI status (interrupt flag = "0"). Read-out during EI status (interrupt flag = "1") will cause malfunction. 50 EPSON S1C60N16 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer) 4.10 Stopwatch Timer 4.10.1 Configuration of stopwatch timer The S1C60N16 Series incorporates a 1/100 sec and 1/10 sec stopwatch timer. The stopwatch timer is configured of a two-stage, four-bit BCD counter serving as the input clock of an approximately 100 Hz signal (signal obtained by approximately demultiplying the 256 Hz signal output by the divider). Data can be read out four bits at a time by the software. Figure 4.10.1.1 is the block diagram of the stopwatch timer. Data bus OSC1 oscillation circuit 256 Hz Divider Stopwatch Timer 10 Hz SWL counter SWH counter 10 Hz, 1 Hz Interrupt control Stopwatch timer reset signal Stopwatch timer RUN/STOP signal Interrupt request Fig. 4.10.1.1 Stopwatch timer block diagram The stopwatch timer can be used as a separate timer from the clock timer. In particular, digital watch stopwatch functions can be realized easily with software. 4.10.2 Count-up pattern The stopwatch timer is configured of four-bit BCD counters SWL and SWH. The counter SWL, at the stage preceding the stopwatch timer, has an approximated 100 Hz signal for the input clock. It counts up every 1/100 sec, and generates an approximated 10 Hz signal. The counter SWH has an approximated 10 Hz signal generated by the counter SWL for the input clock. It count-up every 1/ 10 sec, and generated 1 Hz signal. Figure 4.10.2.1 shows the count-up pattern of the stopwatch timer. SWH count-up pattern SWH count value 0 Count time (sec) SWL count-up pattern 1 SWL count value Count time (sec) SWL count-up pattern 2 SWL count value Count time (sec) 1 26 256 2 3 4 5 6 7 8 9 0 26 25 25 26 26 25 25 26 26 256 256 256 256 256 256 256 256 256 26 x 6 + 25 x 4 = 1 (sec) 256 256 0 1 3 256 0 2 3 4 5 6 7 8 9 0 2 3 2 3 2 3 2 3 2 256 256 256 256 256 256 256 256 256 25 256 (sec) 1 2 3 4 5 6 7 8 9 0 3 3 3 2 3 2 3 2 3 2 256 256 256 256 256 256 256 256 256 256 26 (sec) 256 1 Hz signal generation Approximate 10 Hz signal generation Approximate 10 Hz signal generation Fig. 4.10.2.1 Count-up pattern of stopwatch timer SWL generates an approximated 10 Hz signal from the basic 256 Hz signal. The count-up intervals are 2/ 256 sec and 3/256 sec, so that finally two patterns are generated: 25/256 sec and 26/256 sec intervals. Consequently, these patterns do not amount to an accurate 1/100 sec. SWH counts the approximated 10 Hz signals generated by the 25/256 sec and 26/256 sec intervals in the ratio of 4:6, to generate a 1 Hz signal. The count-up intervals are 25/256 sec and 26/256 sec, which do not amount to an accurate 1/10 sec. S1C60N16 TECHNICAL MANUAL EPSON 51 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer) 4.10.3 Interrupt function The 10 Hz (approximate 10 Hz) and 1 Hz interrupts can be generated through the overflow of stopwatch timers SWL and SWH respectively. Also, software can set whether to separately mask the frequencies described earlier. Figure 4.10.3.1 is the timing chart for the stopwatch timer. Address Register 2E1H D0 1/100 sec (BCD) D1 Stopwatch timer (SWL) timing chart D2 D3 10 Hz interrupt request Address Register 2E2H D0 1/10 sec (BCD) D1 Stopwatch timer (SWH) timing chart D2 D3 1 Hz interrupt request Fig. 4.10.3.1 Stopwatch timer timing chart As shown in Figure 4.10.3.1, the interrupts are generated by the overflow of their respective counters ("9" changing to "0"). Also, at this time the corresponding interrupt factor flags (SWIT0, SWIT1) are set to "1". The respective interrupts can be masked separately through the interrupt mask registers (EISWIT0, EISWIT1). However, regardless of the setting of the interrupt mask registers, the interrupt factor flags are set to "1" by the overflow of their corresponding counters. 52 EPSON S1C60N16 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer) 4.10.4 Control of stopwatch timer Table 4.10.4.1 list the stopwatch timer control bits and their addresses. Table 4.10.4.1 Control bits of stopwatch timer Address Register Comment 1 0 Name Init 1 SWL3 MSB 0 SWL3 SWL2 SWL1 SWL0 SWL2 0 2E1H Stopwatch timer 1/100 sec data (BCD) SWL1 0 R SWL0 LSB 0 SWH3 MSB 0 SWH3 SWH2 SWH1 SWH0 SWH2 0 2E2H Stopwatch timer 1/10 sec data (BCD) SWH1 0 R SWH0 LSB 0 HLMOD Heavy load Normal Heavy load protection mode register (S1C60A16) 0 HLMOD 0 EISWIT1 EISWIT0 - 0 3 Unused - 2 - 2E6H EISWIT1 0 Enable Mask Interrupt mask register (stopwatch 1 Hz) R/W R R/W EISWIT0 0 Enable Mask Interrupt mask register (stopwatch 10 Hz) IK1 4 0 Interrupt factor flag (K10) Yes No IK1 IK0 SWIT1 SWIT0 IK0 4 0 Interrupt factor flag (K00-K03) Yes No 2EAH SWIT1 4 0 Interrupt factor flag (stopwatch 1 Hz) Yes No R SWIT0 4 0 Interrupt factor flag (stopwatch 10 Hz) Yes No TMRST3 Reset Reset Clock timer reset - TMRST SWRUN SWRST IOC0 SWRUN 0 Run Stop Stopwatch timer Run/Stop 2EEH SWRST3 Reset Reset Stopwatch timer reset - W R/W W R/W IOC0 0 Output Input I/O control register 0 (P00-P03) 1 Initial value at initial reset 3 Always "0" being read 5 Undefined 2 Not set in the circuit 4 Reset (0) immediately after being read D3 D2 D1 D0 SWL0-SWL3: Stopwatch timer 1/100 sec (2E1H) Data (BCD) of the 1/100 sec column of the stopwatch timer can be read out. These four bits are read-only, and cannot be used for writing operations. At initial reset, the timer data is set to "0H". SWH0-SWH3: Stopwatch timer 1/10 sec (2E2H) Data (BCD) of the 1/10 sec column of the stopwatch timer can be read out. These four bits are read-only, and cannot be used for writing operations. At initial reset, the timer data is set to "0H". EISWIT0, EISWIT1: Interrupt mask registers (2E6H*D0 and D1) These registers are used to select whether to mask the stopwatch timer interrupt. When "1" is written : Enabled When "0" is written : Masked Read-out : Valid The interrupt mask registers (EISWIT0, EISWIT1) are used to separately select whether to mask the 10 Hz and 1 Hz interrupts. At initial reset, these registers are both set to "0". S1C60N16 TECHNICAL MANUAL EPSON 53 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer) SWIT0, SWIT1: Interrupt factor flags (2EAH*D0 and D1) These flags indicate the status of the stopwatch timer interrupt. When "1" is read out : Interrupt has occurred When "0" is read out : Interrupt has not occurred Writing : Invalid The interrupt factor flags (SWIT0, SWIT1) correspond to the 10 Hz and 1 Hz interrupts respectively. With these flags, the software can judge whether a stopwatch timer interrupt has occurred. However, regardless of the interrupt mask register setting, these flags are set to "1" by the counter overflow. These flags are reset when read out by the software. Also, read-out is only possible in the DI status (interrupt flag = "0"). At initial reset, these flags are set to "0". SWRST: Stopwatch timer reset (2EEH*D1) This bit resets the stopwatch timer. When "1" is written : Stopwatch timer reset When "0" is written : No operation Read-out : Always "0" The stopwatch timer is reset when "1" is written to SWRST. When the stopwatch timer is reset in the RUN status, operation restarts immediately. Also, in the STOP status the reset data is maintained. This bit is write-only, and is always "0" at read-out. SWRUN: Stopwatch timer RUN/STOP (2EEH*D2) This bit controls RUN/STOP of the stopwatch timer. When "1" is written : RUN When "0" is written : STOP Read-out : Valid The stopwatch timer enters the RUN status when "1" is written to SWRUN, and the STOP status when "0" is written. In the STOP status, the timer data is maintained until the next RUN status or resets timer. Also, when the STOP status changes to the RUN status, the data that was maintained can be used for resuming the count. When the timer data is read out in the RUN status, correct read-out may be impossible because of the carry from the low-order bit (SWL) to the high-order bit (SWH). This occurs when read-out has extended over the SWL and SWH bits when the carry occurs. To prevent this, perform read out after entering the STOP status, and then return to the RUN status. Also, the duration of the STOP status must be within 976 sec (256 Hz 1/4 cycle). At initial reset, this register is set to "0". 4.10.5 Programming notes (1) If timer data is read out in the RUN status, the timer must be made into the STOP status, and after data is read out the RUN status can be restored. If data is read out when a carry occurs, the data cannot be read correctly. Also, the processing above must be performed within the STOP interval of 976 sec (256 Hz 1/4 cycle). (2) Read-out of the interrupt factor flag (SWIT) must be done only in the DI status (interrupt flag = "0"). Read-out during EI status (interrupt flag = "1") will cause malfunction. 54 EPSON S1C60N16 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Sound Generator) 4.11 Sound Generator 4.11.1 Configuration of sound generator The S1C60N16 Series outputs buzzer signals (BZ, BZ) to drive the piezoelectric buzzer. The frequency of the buzzer signal is software-selectable from eight kinds of demultiplied fOSC1. Further, a digital envelope can be added to the buzzer signal through duty ratio control. Figure 4.11.1.1 shows the sound generator configuration. Figure 4.11.1.2 shows the sound generator timing chart. [ENVRST] [ENVRT] Envelope generation circuit 256 Hz [BZFQ0-BZFQ2] Programmable dividing circuit fOSC1 [ ] : Register Envelope addition circuit [ENVON] [R10] Output port [R13] R10 (BZ) R13 (BZ) Fig. 4.11.1.1 Configuration of sound generator SR BZFQ0-2 ENVON ENVRT R10(register) R13(register) BZ(R10 terminal) BZ(R13 terminal register R10 control) BZ(R13 terminal register R13 control) Fig. 4.11.1.2 Timing chart of sound generator S1C60N16 TECHNICAL MANUAL EPSON 55 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Sound Generator) 4.11.2 Frequency setting The frequencies of the buzzer signals (BZ, BZ) are set by writing data to registers BZFQ0-BZFQ2. Table 4.11.2.1 lists the register setting values and the frequencies that can be set. Table 4.11.2.1 Setting of frequencies of buzzer signals 2 0 0 0 0 1 1 1 1 BZFQ Buzzer frequency (Hz) 1 0 Demultiplier ratio When fOSC1 = 32 kHz 0 0 fOSC1/8 4,096.0 0 1 fOSC1/10 3,276.8 1 0 fOSC1/12 2,730.7 1 1 fOSC1/14 2,340.6 0 0 fOSC1/16 2,048.0 0 1 fOSC1/20 1,638.4 1 0 fOSC1/24 1,365.3 1 1 fOSC1/28 1,170.3 Note: A hazard may be observed in the output waveform of the BZ and BZ signals when data of the buzzer frequency selection registers (BZFQ0-BZFQ2) changes. 4.11.3 Digital envelope A duty ratio control data envelope (with duty ratio change in eight stages) can be added to the buzzer signal (BZ, BZ). The duty ratio is the ratio of the pulse width compared with the pulse cycle. The BZ output is TH/ (TH+TL) when the high level output is TH and the low level output is TL. The BZ output (BZ inverted output) is TL/ (TH+TL). Also, care must be taken because the duty ratio differs depending on the buzzer frequency. The envelope is added by writing "1" to register ENVON. If "0" is written the duty ratio is fixed to the maximum. Also, if the envelope is added, the duty ratio is reverted to the maximum by writing "1" in register ENVRST, and the duty ratio also becomes the maximum at the start of the buzzer signal output. The decay time of the envelope (time for the duty ratio to change) can be selected with the register ENVRT. This time is 62.5 msec (16 Hz) when "0" is written, and 125 msec (8 Hz) when "1" is written. However, a maximum difference of 4 msec is taken from envelope-ON until the first change. Table 4.11.3.1 lists the duty rates and buzzer frequencies. Figure 4.11.3.1 shows the digital envelope timing chart. Table 4.11.3.1 Duty rates and buzzer frequencies BZFQ 2 1 0 Duty rate Level 1 (max.) Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Level 8 (min.) (register) 56 0 1 0 0 0 0 8/16 7/16 6/16 5/16 4/16 3/16 2/16 1/16 0 1 0 0 1 1 8/20 7/20 6/20 5/20 4/20 3/20 2/20 1/20 EPSON 0 1 1 1 0 0 12/24 11/24 10/24 9/24 8/24 7/24 6/24 5/24 0 1 1 1 1 1 12/28 11/28 10/28 9/28 8/28 7/28 6/28 5/28 S1C60N16 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Sound Generator) No change of duty level SR BZFQ0-2 ENON ENVRST ENVRT R10 (register) BZ signal duty ratio Level 1 (MAX) 2 3 4 5 6 7 8 (MIN) t01 t02 t03 t04 t05 t06 t07 t01 +0 62.5 -4 t01 = msec t02-07 = 62.5 msec t11 t12 t13 t14 t15 t16 t17 +0 125 -4 t11 = msec t12-17 = 125 msec Fig. 4.11.3.1 Digital envelope timing chart 4.11.4 Mask option (1) Selection can be made whether to output the BZ signal from the R10 terminal. (2) Selection can be made whether to output the BZ signal from the R13 terminal. However, if the BZ signal is not output the BZ signal cannot be output. (3) Selection can be made to perform the BZ signal output control through the R10 register or the R13 register. See Section 4.5, "Output Ports" for details of the above mask option. S1C60N16 TECHNICAL MANUAL EPSON 57 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Sound Generator) 4.11.5 Control of sound generator Table 4.11.5.1 lists the sound generator's control bits and their addresses. Table 4.11.5.1 Control bits of sound generator Address Register Comment Name Init 1 1 0 R13 0 High/On Low/Off Output port (R13)/BZ output control R11 R13 R12 R10 R12 0 High/On Low/Off Output port (R12)/FOUT output control SIOF 2ECH R11 0 High Low Output port (R11) R/W SIOF 0 Run Stop Output port (SIOF) R/W R/W R R10 0 High/On Low/Off Output port (R10)/BZ output control [BZFQ2-0] 0 1 2 3 BZFQ2 0 Buzzer BZFQ2 BZFQ1 BZFQ0 ENVRST Frequency fOSC1/8 fOSC1/10 fOSC1/12 fOSC1/14 BZFQ1 0 frequency 5 6 7 [BZFQ2-0] 4 2F6H BZFQ0 0 selection Frequency fOSC1/16 fOSC1/20 fOSC1/24 fOSC1/28 R/W W ENVRST3 Reset Reset - Envelope reset ENVON Envelope On/Off 0 On Off ENVON ENVRT AMPDT AMPON ENVRT 0 1.0 sec 0.5 sec Envelope cycle selection register 2F7H AMPDT 1 +>+ < - Analog comparator data R/W R R/W AMPON Analog comparator On/Off 0 On Off 1 Initial value at initial reset 3 Always "0" being read 5 Undefined 2 Not set in the circuit 4 Reset (0) immediately after being read D3 D2 D1 D0 BZFQ0-BZFQ2: Buzzer frequency selection register (2F6H*D1-D3) This is used to select the frequency of the buzzer signal. Table 4.11.5.2 Buzzer frequency BZFQ2 0 0 0 0 1 1 1 1 BZFQ1 0 0 1 1 0 0 1 1 BZFQ0 Buzzer frequency (Hz) 0 fOSC1/8 1 fOSC1/10 0 fOSC1/12 1 fOSC1/14 0 fOSC1/16 1 fOSC1/20 0 fOSC1/24 1 fOSC1/28 Buzzer frequency is selected from the above eight types that have been divided by fOSC1 (oscillation frequency of the OSC1 oscillation circuit). At initial reset, fOSC1/8 (Hz) is selected. ENVRST: Envelope reset (2F6H*D0) This is the reset input to make the duty ratio of the buzzer signal the maximum. When "1" is written : Reset input When "0" is written : No operation Read-out : Always "0" When the envelope is added to the buzzer signal, the duty ratio is made maximum through this reset input. When the envelope is not added or when the buzzer signal is not output, the reset input is invalid. ENVON: Envelope ON/OFF (2F7H*D3) This controls adding the envelope to the buzzer signal. When "1" is written : Envelope added (ON) When "0" is written : No envelope (OFF) Read-out : Valid The envelope is the digital envelope based on duty ratio control. When there is no envelope, the duty ratio is fixed to the maximum. At initial reset, no envelope (OFF) is selected. 58 EPSON S1C60N16 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Sound Generator) ENVRT: Envelope decay time (2F7H*D2) This input selects the decay time of the envelope added to the buzzer signal. When "1" is written : 1.0 sec (125 msec x 7 = 875 msec) When "0" is written : 0.5 sec (62.5 msec x 7 = 437.5 msec) Read-out : Valid The decay time of the digital envelope is decided by the time taken for the duty ratio to change. When "1" is written to ENVRT the time is 125 msec (8 Hz) units, and when "0" is written it is 62.5 msec (16 Hz) units. At initial reset, 0.5 sec (437.5 msec) is selected. R10, R13 (at BZ, BZ output selection): Special output port data (2ECH*D0, D3) These control output of the buzzer signals (BZ, BZ). When "1" is written : Buzzer signal output When "0" is written : Low level (DC) output Read-out : Valid * BZ output under R13 control BZ output and BZ output can be controlled independently. BZ output is controlled by writing data to register R10. BZ output is controlled by writing data to register R13. * BZ output under R10 control By writing data to register R10 only, BZ output and BZ output can be controlled simultaneously. In this case, register R13 can be used as a read/write one-bit general register. This register does not affect BZ output (output to pin R13). At initial reset, R10 and R13 are set to "0". 4.11.6 Programming note A hazard may be observed in the output waveform of the BZ and BZ signals when data of the output registers (R10, R13) and the buzzer frequency selection registers (BZFQ0-BZFQ2) changes. S1C60N16 TECHNICAL MANUAL EPSON 59 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Event Counter) 4.12 Event Counter 4.12.1 Configuration of event counter The S1C60N16 Series has an event counter that counts the clock signals input from outside. The event counter is configured of a pair of eight-bit binary counters (UP counters). The clock pulses are input through terminals K02 and K03 of the input port. The clock signals input from the terminals are input to the event counter via the noise rejector. The event counter detects the phases of the two clock signals. Software selection provides for two modes, the phase detection mode in which one of the counters can be chosen to input the clock signal, and the separate mode in which each clock signal is input to different counters. Figure 4.12.1.1 shows the configuration of the event counter. K02 Input port Interrupt request K03 Noise rejector Event counter 0 [EV00-EV07] [EV0RST] Phase detection circuit [EVRUN] [EVSEL] Event counter 1 [EV10-EV17] Noise rejector [EV1RST] [ ] : Register Fig. 4.12.1.1 Configuration of event counter 4.12.2 Switching count mode The event counter detects the phases of the two clock signals. Software selection provides for two modes, the phase detection mode in which one of the counters can be chosen to input the clock signal, and the separate mode in which each clock signal is input to different counters. Selection can be made by writing data to the EVSEL register. When "0" is written the phase detection mode is enabled, and when "1" is written the separate mode is enabled. In the phase detection mode, the clock signals having different phases must be input simultaneously to terminals K02 and K03. When the input from terminal K02 is fast the clock signal is input to event counter 1, and when the input from terminal K03 is fast the clock signal is input to event counter 0. In the separate mode, input from terminal K02 is made to event counter 0, and input from terminal K03 is made to event counter 1. Figure 4.12.2.1 is the timing chart for the event counter. 60 EPSON S1C60N16 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Event Counter) Terminal K02 input TP T H TP TL TP T H TP TL Noise TN Terminal K03 input EVRUN TON TOFF STOP RUN When EVSEL="0" (phase detection mode) Input to event counter 0 Input to event counter 1 When EVSEL="1" (separate mode) Input to event counter 0 Input to event counter 1 Defined time TON 1.5 Tch TOFF 1.5 Tch TN < 0.5 Tch TP 1.5 Tch TH 1.5 Tch TL 1.5 Tch Tch = 1/fch: fch, the clock frequency for the noise rejector, can be selected as fOSC1/16 or fOSC1/128 with the mask option Fig. 4.12.2.1 Event counter timing chart 4.12.3 Mask option The clock frequency of the noise rejector can be selected as fOSC1/16 or fOSC1/128. Table 4.12.3.1 lists the defined time depending on the frequency selected. Table 4.12.3.1 Defined time depending on frequency selected When fOSC1 = 32.768 kHz fOSC1/16 fOSC1/128 TN 0.24 1.95 TON 0.74 5.86 TOFF 0.74 5.86 TP 0.74 5.86 TH 0.74 5.86 TL 0.74 5.86 (Unit: msec) : Max value TN Others : Min value Selection S1C60N16 TECHNICAL MANUAL EPSON 61 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Event Counter) 4.12.4 Control of event counter Table 4.12.4.1 shows the event counter control bits and their addresses. Table 4.12.4.1 Control bits of event counter Address Register Comment 1 0 Name Init 1 EV03 0 EV03 EV02 EV01 EV00 EV02 0 2F8H Event counter 0 (low-order 4 bits) EV01 0 R EV00 0 EV07 0 EV07 EV06 EV05 EV04 EV06 0 2F9H Event counter 0 (high-order 4 bits) EV05 0 R EV04 0 EV13 0 EV13 EV12 EV11 EV10 EV12 0 2FAH Event counter 1 (low-order 4 bits) EV11 0 R EV10 0 EV17 0 EV17 EV16 EV15 EV14 EV16 0 2FBH Event counter 1 (high-order 4 bits) EV15 0 R EV14 0 EVSEL 0 Separate Phase Event counter mode selection EVSEL ENRUN EV1RST EV0RST EVRUN 0 Run Stop Event counter Run/Stop 2FCH EV1RST3 Reset Reset Event counter 1 reset - R/W W EV0RST3 Reset Reset Event counter 0 reset - 1 Initial value at initial reset 3 Always "0" being read 5 Undefined 2 Not set in the circuit 4 Reset (0) immediately after being read D3 D2 D1 D0 EV00-EV03: Event counter 0 low-order data (2F8H) The four low-order data bits of event counter 0 are read out. These four bits are read-only, and cannot be used for writing. At initial reset, event counter 0 is set to "00H". EV04-EV07: Event counter 0 high-order data (2F9H) The four high-order data bits of event counter 0 are read out. These four bits are read-only, and cannot be used for writing. At initial reset, event counter 0 is set to "00H". EV10-EV13: Event counter 1 low-order data (2FAH) The four low-order data bits of event counter 1 are read out. These four bits are read-only, and cannot be used for writing. At initial reset, event counter 1 is set to "00H". EV14-EV17: Event counter 1 high-order data (2FBH) The four high-order data bits of event counter 1 are read out. These four bits are read-only, and cannot be used for writing. At initial reset, event counter 1 is set to "00H". EV0RST: Event counter 0 reset (2FCH*D0) This is the register for resetting event counter 0. When "1" is written : Event counter 0 reset When "0" is written : No operation Read-out : Always "0" When "1" is written, event counter 0 is reset and the data becomes "00H". When "0" is written, no operation is executed. This is a write-only bit, and is always "0" at read-out. 62 EPSON S1C60N16 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Event Counter) EV1RST: Event counter 1 reset (2FCH*D1) This is the register for resetting event counter 1. When "1" is written : Event counter 1 reset When "0" is written : No operation Read-out : Always "0" When "1" is written, event counter 1 is reset and the data becomes "00H". When "0" is written, no operation is executed. This is a write-only bit, and is always "0" at read-out. EVRUN: Event counter RUN/STOP (2FCH*D2) This register controls the event counter RUN/STOP status. When "1" is written : RUN When "0" is written : STOP Read-out : Valid When "1" is written, the event counter enters the RUN status and starts receiving the clock signal input. When "0" is written, the event counter enters the STOP status and the clock signal input is ignored. (However, input to the input port is valid.) At initial reset, this register is set to "0". EVSEL: Event counter mode (2FCH*D3) This register control the count mode of the event counter. When "1" is written : Separate When "0" is written : Phase detection Read-out : Valid When "0" is written, the phases of the two clock signals are detected, and the phase detection mode is selected, in which one of the counters is chosen to input the clock signal. When "1" is written, the separate mode is selected, in which each clock signal is input to different counters. At initial reset, this register is set to "0". 4.12.5 Programming notes (1) After the event counter has written data to the EVRUN register, it operates or stops in synchronization with the falling edge of the noise rejector clock or stops. Hence, attention must be paid to the above timing when input signals (input to K02 and K03) are being received. (2) To prevent erroneous reading of the event counter data, read out the counter data several times, compare it, and use the matching data as the result. S1C60N16 TECHNICAL MANUAL EPSON 63 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Analog Comparator) 4.13 Analog Comparator 4.13.1 Configuration of analog comparator The S1C60N16 Series incorporates an MOS input analog comparator. This analog comparator, which has two differential input terminals (inverted input terminal AMPM, non-inverted input terminal AMPP), can be used for general purposes. Figure 4.13.1.1 shows the configuration of the analog comparator. VDD + AMPM - AMPDT Data bus AMPP Input control Power source AMPON control Address VSS Fig. 4.13.1.1 Configuration of analog comparator 4.13.2 Operation of analog comparator The analog comparator is ON when the AMPON register is "1", and compares the input levels of the AMPP and AMPM terminals. The result of the comparison is read from the AMPDT register. It is "1" when AMPP (+) > AMPM (-) and "0" when AMPP (+) < AMPM (-). After the analog comparator goes ON it takes a maximum of 3 msec until the output stabilizes. 64 EPSON S1C60N16 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Analog Comparator) 4.13.3 Control of analog comparator Table 4.13.3.1 lists the analog comparator control bits and their addresses. Table 4.13.3.1 Control bits of analog comparator Address Register Comment 1 0 Name Init 1 ENVON Envelope On/Off 0 On Off ENVON ENVRT AMPDT AMPON ENVRT 0 1.0 sec 0.5 sec Envelope cycle selection register 2F7H AMPDT 1 +>+ < - Analog comparator data R/W R R/W AMPON Analog comparator On/Off 0 On Off 1 Initial value at initial reset 3 Always "0" being read 5 Undefined 2 Not set in the circuit 4 Reset (0) immediately after being read D3 D2 D1 D0 AMPON: Analog comparator ON/OFF (2F7H*D0) Switches the analog comparator ON and OFF. When "1" is written : The analog comparator goes ON When "0" is written : The analog comparator goes OFF Read-out : Valid The analog comparator goes ON when "1" is written to AMPON, and OFF when "0" is written. At initial reset, AMPON is set to "0". AMPDT: Analog comparator data (2F7H*D1) Reads out the output from the analog comparator. When "1" is read out : AMPP (+) > AMPM (-) When "0" is read out : AMPP (+) < AMPM (-) Writing : Invalid AMPDT is "0" when the input level of the inverted input terminal (AMPM) is greater than the input level of the noninverted input terminal (AMPP); and "1" when smaller. At initial reset, AMPDT is set to "1". 4.13.4 Programming notes (1) To reduce current consumption, set the analog comparator to OFF when it is not necessary. (2) After setting AMPON to "1", wait at least 3 msec for the operation of the analog comparator to stabilize before reading the output data of the analog comparator from AMPDT. S1C60N16 TECHNICAL MANUAL EPSON 65 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit) 4.14 Supply Voltage Detection (SVD) Circuit 4.14.1 Configuration of SVD circuit The S1C60N16 Series has a built-in supply voltage detection (SVD) circuit, so that the software can find when the source voltage lowers. The configuration of the SVD circuit is shown in Figure 4.14.1.1. Turning the SVD operation ON/OFF is controlled through the software (SVDON). Because the power current consumption of the IC increases when the SVD operation is turned ON, set the SVD operation to OFF unless otherwise necessary. VDD Detection output SVD sampling control SVDON/ SVDDT Address 2FFH Data bus SVD circuit VSS Fig. 4.14.1.1 Configuration of SVD circuit In the S1C60N16 Series, the evaluation voltage is set as follows: S1C60N16: 2.2 V S1C60L16: 1.2 V S1C60A16: 2.2 V See Chapter 7, "Electrical Characteristics", for the evaluation voltage accuracy. 4.14.2 Detection timing of SVD circuit This section explains the timing for when the SVD circuit writes the result of the supply voltage detection to the SVD latch. Turning the SVD operation ON/OFF is controlled through the software (SVDON). The result of the source voltage detection is written to the SVD latch by the SVD circuit, and this data can be read out by the software to find the status of the source voltage. When SVDON is set to "1", SVD detection is executed. As soon as SVDON is reset to "0" the detection result is loaded to the SVD latch. To obtain a stable SVD detection result, the SVD circuit must be set to ON with at least 100 sec. Hence, to obtain the SVD detection result, follow the programming sequence below. 1. 2. 3. 4. Set SVDON to "1" Maintain at 100 sec minimum Set SVDON to "0" Read out SVDDT However, when a crystal oscillation clock (fOSC1) is selected for the CPU system clock in the S1C60N16, S1C60L16, and S1C60A16, the instruction cycles are long enough, so that there is no need for concern about maintaining 100 sec for the SVDON = "1" with the software. 66 EPSON S1C60N16 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit) 4.14.3 Control of SVD circuit Table 4.14.3.1 shows the SVD circuit's control bits and their addresses. Table 4.14.3.1 Control bits of SVD circuit Address Register D3 SVDDT 2FFH D2 D1 D0 0 0 0 SVDON R R W 1 Initial value at initial reset 2 Not set in the circuit Name Init 1 1 0 SVDDT 0 Low Normal SVD evaluation data SVDON 0 On SVD On/Off Off 0 3 - 2 - Unused - 0 3 - 2 - Unused - 0 3 - 2 - Unused - 3 Always "0" being read 4 Reset (0) immediately after being read Comment 5 Undefined SVDON/SVDDT: SVD control/SVD data (2FFH*D3) Controls the SVD operation. When "0" is written : When "1" is written : When "0" is read out : When "1" is read out : SVD OFF SVD ON Supply voltage (VDD-VSS) 2.2 V (S1C60N16/60A16)/1.2 V (S1C60L16) Supply voltage (VDD-VSS) < 2.2 V (S1C60N16/60A16)/1.2 V (S1C60L16) Note that the function of this bit when written is different to when read out. When this bit is written to, ON/OFF of the SVD detection operation is controlled; when this bit is read out, the result of the SVD detection (contents of SVD latch) is obtained. Appreciable current is consumed during operation of SVD detection, so keep SVD detection OFF except when necessary. When SVDON is set to "1", SVD detection is executed. As soon as SVDON is reset to "0" the detection result is loaded to the SVD latch. To obtain a stable detection result, the SVD circuit must be set to ON with at least 100 sec. Hence, to obtain the detection result, follow the programming sequence below. 1. 2. 3. 4. Set SVDON to "1" Maintain at 100 sec minimum Set SVDON to "0" Read out SVDDT However, when a crystal oscillation clock (fOSC1) is selected for the CPU system clock in the S1C60N16, S1C60L16, and S1C60A16, the instruction cycles are long enough, so that there is no need for concern about maintaining 100 sec for the SVDON = "1" with the software. 4.14.4 Programming notes (1) The SVD circuit takes 100 sec from the time it goes ON until a stable result is obtained. For this reason, keep the following software notes in mind: After writing "1" on SVDON, write "0" after at least 100 sec has elapsed (possible with the next instruction when the OSC1 clock is used as the CPU clock) and then read the SVDDT. (2) SVDON resides in the same bit at the same address as SVDDT, and one or the other is selected by write or read operation. This means that arithmetic operations (AND, OR, ADD, SUB and so forth) cannot be used for SVDON control. S1C60N16 TECHNICAL MANUAL EPSON 67 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Heavy Load Protection Function) 4.15 Heavy Load Protection Function (S1C60A16) 4.15.1 Outline of heavy load protection function The S1C60A16 has the heavy load protection function for when the battery load becomes heavy and the source voltage changes, such as when an external buzzer sounds or an external lamp lights. The state where the heavy load protection function is in effect is called the heavy load protection mode. Compared with the normal operation mode, this mode can reduce the output voltage variation of the constant voltage. The normal mode changes to the heavy load protection mode in the following case: * When the software changes the mode to the heavy load protection mode (HLMOD = "1") The heavy load protection mode switches the voltage regulator circuit to the high-stability mode from the low current consumption mode. Consequently, more current is consumed in the heavy load protection mode than in the normal mode. Unless it is necessary, be careful not to set the heavy load protection mode with the software. Note: The S1C60N16 and S1C60L16 do not support the heavy load protection function. 4.15.2 Control of heavy load protection function Table 4.15.2.1 shows the control bits and their addresses for the heavy load protection function. Table 4.15.2.1 Control bits of heavy load protection function Address Register Comment 1 0 Name Init 1 HLMOD Heavy load Normal Heavy load protection mode register (S1C60A16) 0 HLMOD 0 EISWIT1 EISWIT0 - 0 3 Unused - 2 - 2E6H EISWIT1 0 Enable Mask Interrupt mask register (stopwatch 1 Hz) R/W R R/W EISWIT0 0 Enable Mask Interrupt mask register (stopwatch 10 Hz) 1 Initial value at initial reset 3 Always "0" being read 5 Undefined 2 Not set in the circuit 4 Reset (0) immediately after being read D3 D2 D1 D0 HLMOD: Heavy load protection mode (2E6H*D3) Sets the IC in heavy load protection mode. When "1" is written : Heavy load protection mode is set When "0" is written : Heavy load protection mode is released Read-out : Valid When HLMOD is set to "1", the IC enters the heavy load protection mode. In the S1C60N16 and S1C60L16, HLMOD can be used as a general-purpose R/W register. 4.15.3 Programming notes (1) More current is consumed in the heavy load protection mode than in the normal mode. Unless it is necessary, be careful not to set the heavy load protection mode with the software. (2) The heavy load protection function is available only in the S1C60A16. The S1C60N16 and S1C60L16 do not support this function and HLMOD can be used as a generalpurpose R/W register that does not affect the IC's operations. 68 EPSON S1C60N16 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) 4.16 Interrupt and HALT The S1C60N16 Series provides the following interrupt settings, each of which is maskable. External interrupt: Internal interrupt: Input interrupt (two) Timer interrupt (three) Stopwatch interrupt (two) Serial interface interrupt (one) To authorize interrupt, the interrupt flag must be set to "1" (EI) and the necessary related interrupt mask registers must be set to "1" (enable). When an interrupt occurs the interrupt flag is automatically reset to "0" (DI), and interrupts after that are inhibited. When a HALT instruction is input the CPU operating clock stops, and the CPU enters the HALT status. The CPU is reactivated from the HALT status when an interrupt request occurs. If reactivation is not caused by an interrupt request, initial reset by the watchdog timer causes reactivates the CPU (when the watchdog timer is enabled). Figure 4.16.1 shows the configuration of the interrupt circuit. Interrupt vector map Table 4.16.1 Interrupt vector map Page 1 Step 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH Interrupt vector Initial reset Serial interface interrupt Input port interrupt Serial interface + Input port interrupt Clock timer interrupt Serial interface + Clock timer interrupt Input port + Clock timer interrupt Serial interface + Input port + Clock timer interrupt Stopwatch timer interrupt Serial interface + Stopwatch timer interrupt Input port + Stopwatch timer interrupt Serial interface + Input port + Stopwatch timer interrupt Clock timer + Stopwatch timer interrupt Serial interface + Clock timer + Stopwatch timer interrupt Input port + Clock timer + Stopwatch timer interrupt All interrupts The interrupt service routine start address should be written to each interrupt vector address. S1C60N16 TECHNICAL MANUAL EPSON 69 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) SWIT1 EISWIT1 SWIT0 EISWIT0 Interrupt vector TI2 ETI2 (MSB) TI8 Program counter (four low-order bits) ETI8 TI32 ETI32 (LSB) K00 KCP00 EIK00 INT (interrupt request) K01 KCP01 Interrupt flag EIK01 IK0 K02 KCP02 EIK02 K03 KCP03 EIK03 K10 Interrupt factor flag KCP10 IK1 EIK10 Interrupt mask register ISIO Input comparison register EISIO Fig. 4.16.1 Configuration of interrupt circuit 70 EPSON S1C60N16 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) 4.16.1 Interrupt factors Table 4.16.1.1 shows the factors for generating interrupt requests. The interrupt flags are set to "1" depending on the corresponding interrupt factors. The CPU operation is interrupted when any of the conditions below set an interrupt factor flag to "1". * The corresponding mask register is "1" (enabled) * The interrupt flag is "1" (EI) The interrupt factor flag is a read-only register, but can be reset to "0" when the register data is read out. At initial reset, the interrupt factor flags are reset to "0". Note: Read the interrupt factor flags only in the DI status (interrupt flag = "0"). A malfunction could result from read-out during the EI status (interrupt flag = "1"). Table 4.16.1.1 Interrupt factors Interrupt factor Clock timer 2 Hz falling edge Clock timer 8 Hz falling edge Clock timer 32 Hz falling edge Stopwatch timer 1 Hz falling edge Stopwatch timer 10 Hz falling edge Serial interface When 8-bit data input/output has completed Input (K00-K03) port rising/falling edge Input (K10) port rising/falling edge Interrupt factor flag TI2 (2E9H*D2) TI8 (2E9H*D1) TI32 (2E9H*D0) SWIT1 (2EAH*D1) SWIT0 (2EAH*D0) ISIO (2F3H*D0) IK0 IK1 (2EAH*D2) (2EAH*D3) 4.16.2 Specific masks and factor flags for interrupt The interrupt factor flags can be masked by the corresponding interrupt mask registers. The interrupt mask registers are read/write registers. They are enabled (interrupt authorized) when "1" is written to them, and masked (interrupt inhibited) when "0" is written to them. At initial reset, the interrupt mask register is set to "0". Table 4.16.2.1 shows the correspondence between interrupt mask registers and interrupt factor flags. Table 4.16.2.1 Interrupt mask registers and interrupt factor flags Interrupt mask register ETI2 (2E8H*D2) ETI8 (2E8H*D1) ETI32 (2E8H*D0) EISWIT1 (2E6H*D1) EISWIT0 (2E6H*D0) EISIO (2F2H*D0) EIK03* (2E5H*D3) EIK02* (2E5H*D2) EIK01* (2E5H*D1) EIK00* (2E5H*D0) EIK10* (2E7H*D2) Interrupt factor flag TI2 (2E9H*D2) TI8 (2E9H*D1) TI32 (2E9H*D0) SWIT1 (2EAH*D1) SWIT0 (2EAH*D0) ISIO (2F3H*D0) IK0 (2EAH*D2) IK1 (2EAH*D3) There is an interrupt mask register for each pin of the input ports. S1C60N16 TECHNICAL MANUAL EPSON 71 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) 4.16.3 Interrupt vectors When an interrupt request is input to the CPU, the CPU begins interrupt processing. After the program being executed is terminated, the interrupt processing is executed in the following order. The address data (value of program counter) of the program to be executed next is saved in the stack area (RAM). The interrupt request causes the value of the interrupt vector (page 1, 01H-0FH) to be set in the program counter. The program at the specified address is executed (execution of interrupt processing routine by software). Table 4.16.3.1 shows the correspondence of interrupt requests and interrupt vectors. Note: The processing in and above take 12 cycles of the CPU system clock. Table 4.16.3.1 Interrupt request and interrupt vectors PC Value Interrupt request PCS3 1 Stopwatch timer interrupt 0 PCS2 1 Clock timer interrupt 0 PCS1 1 Input port interrupt 0 PCS0 1 Serial interface interrupt 0 Enabled Masked Enabled Masked Enabled Masked Enabled Masked The four low-order bits of the program counter are indirectly addressed through the interrupt request. 72 EPSON S1C60N16 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) 4.16.4 Control of interrupt and HALT Table 4.16.4.1 shows the interrupt control bits and their addresses. Table 4.16.4.1 Interrupt control bits Address Register Comment Name Init 1 1 0 KCP03 0 KCP03 KCP02 KCP01 KCP00 KCP02 0 2E4H Input comparison register (K00-K03) KCP01 0 R/W KCP00 0 EIK03 0 Enable Mask EIK03 EIK02 EIK01 EIK00 EIK02 0 Enable Mask 2E5H Interrupt mask register (K00-K03) EIK01 0 Enable Mask R/W EIK00 0 Enable Mask HLMOD Heavy load Normal Heavy load protection mode register (S1C60A16) 0 HLMOD 0 EISWIT1 EISWIT0 - 0 3 Unused - 2 - 2E6H EISWIT1 0 Enable Mask Interrupt mask register (stopwatch 1 Hz) R/W R R/W EISWIT0 0 Enable Mask Interrupt mask register (stopwatch 10 Hz) SCTRG3 Trigger - Serial I/F clock trigger - SCTRG EIK10 KCP10 K10 EIK10 Enable Mask Interrupt mask register (K10) 0 2E7H KCP10 Input comparison register (K10) 0 W R/W R Low Input port data (K10) K10 - 2 High CSDC1 0 Static Dynamic LCD drive switch CSDC1 ETI2 ETI8 ETI32 ETI2 0 Enable Mask Interrupt mask register (clock timer 2 Hz) 2E8H ETI8 0 Enable Mask Interrupt mask register (clock timer 8 Hz) R/W ETI32 0 Enable Mask Interrupt mask register (clock timer 32 Hz) 0 3 - 2 Unused - - 0 TI2 TI8 TI32 TI2 4 0 Interrupt factor flag (clock timer 2 Hz) Yes No 2E9H TI8 4 0 Interrupt factor flag (clock timer 8 Hz) Yes No R TI32 4 0 Interrupt factor flag (clock timer 32 Hz) Yes No IK1 4 0 Interrupt factor flag (K10) Yes No IK1 IK0 SWIT1 SWIT0 IK0 4 0 Interrupt factor flag (K00-K03) Yes No 2EAH SWIT1 4 0 Interrupt factor flag (stopwatch 1 Hz) Yes No R SWIT0 4 0 Interrupt factor flag (stopwatch 10 Hz) Yes No [SCS1, 0] 0 1 2 3 SCS1 Serial I/F clock 1 SCS1 SCS0 SE2 EISIO Clock CLK CLK/2 CLK/4 Slave SCS0 mode selection 1 2F2H SE2 Serial I/F clock edge selection 0 R/W EISIO 0 Enable Mask Interrupt mask register (serial I/F) 0 3 - 2 Unused - - 0 0 0 ISIO 0 3 - 2 Unused - - 2F3H 0 3 - 2 Unused - - R ISIO 4 0 Interrupt factor flag (serial I/F) Yes No 1 Initial value at initial reset 3 Always "0" being read 5 Undefined 2 Not set in the circuit 4 Reset (0) immediately after being read D3 D2 D1 S1C60N16 TECHNICAL MANUAL D0 EPSON 73 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) ETI32, ETI8, ETI2: Interrupt mask registers (2E8H*D0-D2) TI32, TI8, TI2: Interrupt factor flags (2E9H*D0-D2) See Section 4.9, "Clock Timer". EISWIT0, EISWIT1: Interrupt mask registers (2E6H*D0-D1) SWIT0, SWIT1: Interrupt factor flags (2EAH*D0-D1) See Section 4.10, "Stopwatch Timer". EISIO: Interrupt mask register (2F2H*D0) ISIO: Interrupt factor flag (2F3H*D0) See Section 4.7, "Serial Interface". KCP00-KCP03: Input comparison registers (2E4H) EIK00-EIK03: Interrupt mask registers (2E5H) IK0: Interrupt factor flag (2EAH*D2) See Section 4.4, "Input Ports". KCP10: Input comparison register (2E7H*D1) EIK10: Interrupt mask register (2E7H*D2) IK1: Interrupt factor flag (2EAH*D3) See Section 4.4, "Input Ports". 4.16.5 Programming notes (1) When the interrupt mask register (EIK) is set to "0", the interrupt factor flag (IK) of the input port cannot be set even though the terminal status of the input port has changed. (2) The interrupt factor flags of the clock timer, stopwatch timer and serial interface (TI, SWIT, ISIO) are set when the timing condition is established, even if the interrupt mask registers (ETI, EISWIT, EISIO) are set to "0". (3) Read out the interrupt factor flags only in the DI status (interrupt flag = "0"). If read-out is performed in the EI status (interrupt flag = "1") a malfunction will result. (4) Writing to the interrupt mask register only in the DI status (interrupt flag = "0"). Writing to the interrupt mask register while in the EI status (interrupt flag = "1") may cause malfunction. 74 EPSON S1C60N16 TECHNICAL MANUAL CHAPTER 5: SUMMARY OF NOTES CHAPTER 5 SUMMARY OF NOTES 5.1 Notes for Low Current Consumption The S1C60N16 Series contains control registers for each of the circuits so that current consumption can be lowered. These control registers lower the current consumption through programs that operate the circuits at the minimum levels. The following text explains the circuits that can control operation and their control registers. Refer to these when putting programs together. Table 5.1.1 Circuits and control register Circuit (and item) Control register Order of consumed current CPU CPU operating frequency (S1C60A16) Heavy load protection mode (S1C60A16) SVD circuit Analog comparator HALT instruction CLKCHG, OSCC See Electrical Characteristics (Chapter 7) See Electrical Characteristics (Chapter 7) HLMOD See Electrical Characteristics (Chapter 7) SVDON Several tens A Several tens A AMPON Below are the circuit statuses at initial reset. CPU: CPU operating frequency (S1C60A16): Operating status Low speed side (CLKCHG = "0"), OSC3 oscillation circuit stop status (OSCC = "0") Heavy load protection mode (S1C60A16): Normal operating mode (HLMOD = "0") SVD circuit: OFF status (SVDON = "0") Analog comparator: OFF status (AMPON = "0") Also, be careful about panel selection because the current consumption can differ by the order of several A on account of the LCD panel characteristics. S1C60N16 TECHNICAL MANUAL EPSON 75 CHAPTER 5: SUMMARY OF NOTES 5.2 Summary of Notes by Function Here, the cautionary notes are summed up by function category. Keep these notes well in mind when programming. Memory Memory is not mounted in unused area within the memory map and in memory area not indicated in this manual. For this reason, normal operation cannot be assured for programs that have been prepared with access to these areas. Watchdog timer When the watchdog timer is being used, the software must reset it within 3-second cycles, and timer data (WD0-WD2) cannot be used for timer applications. Oscillation circuit (S1C60A16) (1) It takes at least 5 msec from the time the OSC3 oscillation circuit goes ON until the oscillation stabilizes. Consequently, when switching the CPU operation clock from OSC1 to OSC3, do this after a minimum of 5 msec have elapsed since the OSC3 oscillation went ON. Further, the oscillation stabilization time varies depending on the external oscillator characteristics and conditions of use, so allow ample margin when setting the wait time. (2) When switching the clock form OSC3 to OSC1, use a separate instruction for switching the OSC3 oscillation OFF. An error in the CPU operation can result if this processing is performed at the same time by the one instruction. Input port (1) When input ports are changed from high to low by pull-down resistance, the fall of the waveform is delayed on account of the time constant of the pull-down resistance and input gate capacitance. Hence, when fetching input ports, set an appropriate wait time. Particular care needs to be taken of the key scan during key matrix configuration. Aim for a wait time of about 1 msec. (2) When "Use" is selected with the noise rejector mask option, a maximum delay of 1 msec occurs from time the interrupt conditions are established until the interrupt factor flag (IK) is set to "1" (until the interrupt is actually generated). Hence, pay attention to the timing when reading out (resetting) the interrupt factor flag. For example, when performing a key scan with the key matrix, the key scan changes the input status to set the interrupt factor flag, so it has to be read out to reset it. However, if the interrupt factor flag is read out immediately after key scanning, the delay will cause the flag to be set after read-out, so that it will not be reset. (3) Input interrupt programming related precautions Port K input Active status Active status Input comparison register Falling edge interrupt Rising edge interrupt Mask register Factor flag set Not set Factor flag set When the content of the mask register is rewritten while the port K input is in the active status, the input interrupt factor flags are set at and , being the interrupt due to the falling edge and the interrupt due to the rising edge. Fig. 5.2.1 Input interrupt timing 76 EPSON S1C60N16 TECHNICAL MANUAL CHAPTER 5: SUMMARY OF NOTES When using an input interrupt, if you rewrite the content of the mask register, when the value of the input terminal which becomes the interrupt input is in the active status, the factor flag for input interrupt may be set. Therefore, when using the input interrupt, the active status of the input terminal implies input terminal = low status, when the falling edge interrupt is effected and input terminal = high status, when the rising edge interrupt is effected. When an interrupt is triggered at the falling edge of an input terminal, a factor flag is set with the timing of shown in Figure 5.2.1. However, when clearing the content of the mask register with the input terminal kept in the low status and then setting it, the factor flag of the input interrupt is again set at the timing that has been set. Consequently, when the input terminal is in the active status (low status), do not rewrite the mask register (clearing, then setting the mask register), so that a factor flag will only set at the falling edge in this case. When clearing, then setting the mask register, set the mask register, when the input terminal is not in the active status (high status). When an interrupt is triggered at the rising edge of the input terminal, a factor flag will be set at the timing of shown in Figure 5.2.1. In this case, when the mask registers cleared, then set, you should set the mask register, when the input terminal is in the low status. In addition, when the mask register = "1" and the content of the input comparison register is rewritten in the input terminal active status, an input interrupt factor flag may be set. Thus, you should rewrite the content of the input comparison register in the mask register = "0" status. Output port When BZ, BZ and FOUT are selected with the mask option, a hazard may be observed in the output waveform when the data of the output register changes. I/O port (1) When input data are changed from high to low by built-in pull-down resistance, the fall of the waveform is delayed on account of the time constant of the pull-down resistance and input gate capacitance. Consequently, if data is read out while the CPU is running in the OSC3 oscillation circuit, data must be read out continuously for about 500 sec. (2) When the I/O port is set to the output mode and the data register has been read, the terminal data instead of the register data can be read out. Because of this, if a low-impedance load is connected and read-out performed, the value of the register and the read-out result may differ. Serial interface (1) If the bit data of SE2 changes while SCLK is in the master mode, a hazard will be output to the SCLK pin. If this poses a problem for the system, be sure to set the SCLK to the external clock if the bit data of SE2 is to be changed. (2) Be sure that read-out of the interrupt factor flag (ISIO) is done only when the serial port is in the STOP status (SIOF = "0") and the DI status (interrupt flag = "0"). If read-out is performed while the serial data is in the RUN status (during input or output), the data input or output will be suspended and the initial status resumed. Read-out during the EI status (interrupt flag = "1") causes malfunctioning. (3) When using the serial interface in the master mode, the synchronous clock uses the CPU system clock. Accordingly, do not change the system clock (fOSC1 fOSC3) while the serial interface is operating. (4) Perform data writing/reading to data registers SD0-SD7 only while the serial interface is halted (i.e., the synchronous clock is neither being input or output). (5) As a trigger condition, it is required that data writing or reading on data registers SD0-SD7 be performed prior to writing "1" to SCTRG. (The internal circuit of the serial interface is initiated through data writing/reading on data registers SD0-SD7.) Supply trigger only once every time the serial interface is placed in the RUN state. Moreover, when the synchronous clock SCLK is external clock, start to input the external clock after the trigger. S1C60N16 TECHNICAL MANUAL EPSON 77 CHAPTER 5: SUMMARY OF NOTES LCD driver (1) When Page 0 is selected for the display memory, the memory data and the display will not match until the area is initialized (through, for instance, memory clear processing by the CPU). Initialize the display memory by executing initial processing. (2) When Page 2 is selected for the display memory, that area becomes write-only. Consequently, data cannot be rewritten by arithmetic operations (such as AND, OR, ADD, SUB). Clock timer (1) When the clock timer has been reset, the interrupt factor flag (TI) may sometimes be set to "1". Consequently, perform flag read-out (reset the flag) as necessary at reset. (2) The input clock of the watchdog timer is the 2 Hz signal of the clock timer, so that the watchdog timer may be counted up at timer reset. Stopwatch timer If timer data is read out in the RUN status, the timer must be made into the STOP status, and after data is read out the RUN status can be restored. If data is read out when a carry occurs, the data cannot be read correctly. Also, the processing above must be performed within the STOP interval of 976 sec (256 Hz 1/4 cycle). Sound generator A hazard may be observed in the output waveform of the BZ and BZ signals when data of the output registers (R10, R13) and the buzzer frequency selection registers (BZFQ0-BZFQ2) changes. Event counter (1) After the event counter has written data to the EVRUN register, it operates or stops in synchronization with the falling edge of the noise rejector clock or stops. Hence, attention must be paid to the above timing when input signals (input to K02 and K03) are being received. (2) To prevent erroneous reading of the event counter data, read out the counter data several times, compare it, and use the matching data as the result. Analog comparator (1) To reduce current consumption, set the analog comparator to OFF when it is not necessary. (2) After setting AMPON to "1", wait at least 3 msec for the operation of the analog comparator to stabilize before reading the output data of the analog comparator from AMPDT. Supply voltage detection (SVD) circuit (1) The SVD circuit takes 100 sec from the time it goes ON until a stable result is obtained. For this reason, keep the following software notes in mind: After writing "1" on SVDON, write "0" after at least 100 sec has elapsed (possible with the next instruction when the OSC1 clock is used as the CPU clock) and then read the SVDDT. (2) SVDON resides in the same bit at the same address as SVDDT, and one or the other is selected by write or read operation. This means that arithmetic operations (AND, OR, ADD, SUB and so forth) cannot be used for SVDON control. Heavy load protection function (S1C60A16) (1) More current is consumed in the heavy load protection mode than in the normal mode. Unless it is necessary, be careful not to set the heavy load protection mode with the software. (2) The heavy load protection function is available only in the S1C60A16. The S1C60N16 and S1C60L16 do not support this function and HLMOD can be used as a generalpurpose R/W register that does not affect IC's operations. 78 EPSON S1C60N16 TECHNICAL MANUAL CHAPTER 5: SUMMARY OF NOTES Interrupt and HALT (1) When the interrupt mask register (EIK) is set to "0", the interrupt factor flag (IK) of the input port cannot be set even though the terminal status of the input port has changed. (2) The interrupt factor flags of the clock timer, stopwatch timer and serial interface (TI, SWIT, ISIO) are set when the timing condition is established, even if the interrupt mask registers (ETI, EISWIT, EISIO) are set to "0". (3) Read out the interrupt factor flags only in the DI status (interrupt flag = "0"). If read-out is performed in the EI status (interrupt flag = "1") a malfunction will result. (4) Writing to the interrupt mask register only in the DI status (interrupt flag = "0"). Writing to the interrupt mask register while in the EI status (interrupt flag = "1") may cause malfunction. S1C60N16 TECHNICAL MANUAL EPSON 79 CHAPTER 5: SUMMARY OF NOTES 5.3 Precautions on Mounting <Oscillation Circuit> Oscillation characteristics change depending on conditions (board pattern, components used, etc.). In particular, when using a crystal oscillator, use the oscillator manufacturer's recommended values for constants such as capacitance and resistance. Disturbances of the oscillation clock due to noise may cause a malfunction. Consider the following points to prevent this: (1) Components which are connected to the OSC1, OSC2, OSC3 and OSC4 terminals, such as oscillators, resistors and capacitors, should be connected in the shortest line. (2) As shown in the right hand figure, make a VSS pattern as large as possible at circumscription of the OSC1/OSC3 and OSC2/OSC4 terminals and the components connected to these terminals. Furthermore, do not use this VSS pattern for any purpose other than the oscillation system. Sample VDD pattern OSC2 OSC1 VSS In order to prevent unstable operation of the oscillation circuit due to current leak between OSC1/OSC3 and VDD, please keep enough distance between OSC1/OSC3 and VDD or other signals on the board pattern. <Reset Circuit> The power-on reset signal which is input to the RESET terminal changes depending on conditions (power rise time, components used, board pattern, etc.). Decide the time constant of the capacitor and resistor after enough tests have been completed with the application product. When the built-in pull-down resistor is added to the RESET terminal by mask option, take into consideration dispersion of the resistance for setting the constant. In order to prevent any occurrences of unnecessary resetting caused by noise during operating, components such as capacitors and resistors should be connected to the RESET terminal in the shortest line. <Power Supply Circuit> Sudden power supply variation due to noise may cause malfunction. Consider the following points to prevent this: (1) The power supply should be connected to the VDD and VSS terminal with patterns as short and large as possible. (2) When connecting between the VDD and VSS terminals with a bypass capacitor, the terminals should be connected as short as possible. Bypass capacitor connection example VDD VDD VSS VSS (3) Components which are connected to the VD1, VC1, VC2, VC3 terminals, such as a capacitor, should be connected in the shortest line. 80 EPSON S1C60N16 TECHNICAL MANUAL CHAPTER 5: SUMMARY OF NOTES <Arrangement of Signal Lines> In order to prevent generation of electromagnetic induction noise caused by mutual inductance, do not arrange a large current signal line near the circuits that are sensitive to noise such as the oscillation unit. When a signal line is parallel with a high-speed line in long distance or intersects a high-speed line, noise may generated by mutual interference between the signals and it may cause a malfunction. Do not arrange a high-speed signal line especially near circuits that are sensitive to noise such as the oscillation unit. Prohibited pattern OSC2 OSC1 VSS Large current signal line High-speed signal line <Precautions for Visible Radiation (when bare chip is mounted)> Visible radiation causes semiconductor devices to change the electrical characteristics. It may cause this IC to malfunction. When developing products which use this IC, consider the following precautions to prevent malfunctions caused by visible radiations. (1) Design the product and implement the IC on the board so that it is shielded from visible radiation in actual use. (2) The inspection process of the product needs an environment that shields the IC from visible radiation. (3) As well as the face of the IC, shield the back and side too. S1C60N16 TECHNICAL MANUAL EPSON 81 CHAPTER 6: BASIC EXTERNAL WIRING DIAGRAM CHAPTER 6 BASIC EXTERNAL WIRING DIAGRAM S1C60N16 and S1C60L16 COM3 SEG37 COM0 SEG0 LCD panel CB CA RESET K00 : K03 K10 VDD VC1 VC2 VC3 S1C60N16 S1C60L16 CGX X'tal Crystal oscillator Trimmer capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Protection resistor Protection resistor R10 (BZ) R13 (BZ) R11 VD1 Lamp X'tal CGX C1 C2 C3 C4 C5 CP RA1 RA2 + OSC2 R12 (FOUT) O C4 OSC1 AMPM AMPP R00 : R03 C3 C5 OSC3 N.C. OSC4 N.C. CP 3.0 V (S1C60N16) or 1.5 V (S1C60L16) TEST VSS Piezo 32.768 kHz, CI = 35 k 5-25 pF 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 3.3 F 100 100 R10 (BZ) I/O P00 : P03 P10 : P13 C2 R13 (BZ) I C1 RA2 RA1 Piezo When the piezoelectric buzzer is driven directly Note: The above table is simply an example, and is not guaranteed to work. 82 EPSON S1C60N16 TECHNICAL MANUAL CHAPTER 6: BASIC EXTERNAL WIRING DIAGRAM S1C60A16 COM3 SEG0 SEG37 COM0 LCD panel CB CA RESET K00 : K03 K10 VDD VC1 P00 : P03 P10 : P13 VC3 S1C60A16 CGX X'tal OSC2 VD1 Lamp X'tal CGX CR CGC CDC RCR C1 C2 C3 C4 C5 CP RA1 RA2 Crystal oscillator Trimmer capacitor Ceramic oscillator Gate capacitor Drain capacitor Resistor for CR oscillation Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Protection resistor Protection resistor R10 (BZ) R11 R13 (BZ) OSC4 + 1 C5 3.0 V CP CGC OSC3 R12 (FOUT) O C4 OSC1 AMPM AMPP R00 : R03 C3 RCR CR CDC 3 2 TEST VSS Piezo 32.768 kHz, CI = 35 k 5-25 pF 1 MHz 100 pF 100 pF 40 k (1 MHz) 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 3.3 F 100 100 1 Crystal oscillation 2 CR oscillation 3 Ceramic oscillation R10 (BZ) I/O VC2 C2 R13 (BZ) I C1 RA2 RA1 Piezo When the piezoelectric buzzer is driven directly Note: The above table is simply an example, and is not guaranteed to work. S1C60N16 TECHNICAL MANUAL EPSON 83 CHAPTER 7: ELECTRICAL CHARACTERISTICS CHAPTER 7 ELECTRICAL CHARACTERISTICS 7.1 Absolute Maximum Rating S1C60N16 and S1C60A16 (VSS=0V) Item Rated value Unit Symbol Supply voltage -0.5 to 4.5 V VDD Input voltage (1) VI -0.5 to VDD + 0.3 V Input voltage (2) VIOSC -0.5 to VD1 + 0.3 V Permissible total output current 1 IVDD 10 mA Operating temperature Topr -20 to 70 C Storage temperature Tstg -65 to 150 C Soldering temperature / time Tsol 260C, 10sec (lead section) - Permissible dissipation 2 PD 250 mW 1 The permissible total output current is the sum total of the current (average current) that simultaneously flows from the output pin (or is drawn in). 2 In case of plastic package. S1C60L16 (VSS=0V) Item Rated value Unit Symbol Supply voltage 0.5 to 2.0 V VDD Input voltage (1) VI -0.5 to VDD + 0.3 V Input voltage (2) VIOSC -0.5 to VD1 + 0.3 V Permissible total output current 1 IVDD 10 mA Operating temperature Topr -20 to 70 C Storage temperature Tstg -65 to 150 C Soldering temperature / time Tsol 260C, 10sec (lead section) - Permissible dissipation 2 PD 250 mW 1 The permissible total output current is the sum total of the current (average current) that simultaneously flows from the output pin (or is drawn in). 2 In case of plastic package. 7.2 Recommended Operating Conditions S1C60N16 Item Supply voltage Oscillation frequency Symbol VDD fOSC1 Condition Min. 2.2 - (Ta=-20 to 70C) Typ. Max. Unit 3.0 3.6 V 32.768 - kHz Condition Min. 1.2 - (Ta=-20 to 70C) Typ. Max. Unit 1.5 1.8 V 32.768 - kHz Condition Min. 2.2 - 50 (Ta=-20 to 70C) Typ. Max. Unit 3.0 3.6 V 32.768 - kHz 1000 1200 kHz VSS=0V Crystal oscillation S1C60L16 Item Supply voltage Oscillation frequency Symbol VDD fOSC1 VSS=0V Crystal oscillation S1C60A16 Item Supply voltage Oscillation frequency (1) Oscillation frequency (2) 84 Symbol VDD fOSC1 fOSC3 VSS=0V Crystal oscillation duty 505% EPSON S1C60N16 TECHNICAL MANUAL CHAPTER 7: ELECTRICAL CHARACTERISTICS 7.3 DC Characteristics S1C60N16 and S1C60A16 Unless otherwise specified: VDD=3.0V, VSS=0V, fOSC1=32.768kHz, Ta=25C, VD1/VC1-VC3 are internal voltage, C1-C5=0.1F Item Min. Symbol Condition High level input voltage (1) VIH1 0.8*VDD K00-03, K10, P00-03, P10-13 High level input voltage (2) VIH2 0.9*VDD RESET, TEST Low level input voltage (1) VIL1 K00-03, K10, P00-03, P10-13 0 Low level input voltage (2) VIL2 RESET, TEST 0 High level input current (1) IIH1 K00-03, K10, P00-03, P10-13 VIH1=3.0V 0 No pull-down AMPP, AMPM High level input current (2) VIH2=3.0V 3 IIH2 K00-03, K10 With pull-down High level input current (3) 3 VIH3=3.0V IIH3 P00-03, P10-13, RESET, TEST With pull-down Low level input current -0.5 VIL=VSS IIL K00-03, K10, P00-03, P10-13 AMPP, AMPM, RESET, TEST High level output current VOH1=0.9*VDD IOH1 R00-03, R10-13, P00-03, P10-13 Low level output current VOL1=0.1*VDD IOL1 R00-03, R10-13, P00-03, P10-13 3.0 Common output current IOH2 VOH2=VC3-0.05V COM0-3 3 VOL2=VSS+0.05V IOL2 Segment output current IOH3 VOH3=VC3-0.05V SEG0-37 (during LCD output) 3 VOL3=VSS+0.05V IOL3 Segment output current IOH4 SEG0-37 VOH4=0.9*VDD (during DC output) 200 VOL4=0.1*VDD IOL4 Typ. Max. Unit 0 V 0 V 0.2*VDD V 0.1*VDD V A 0.5 10 A 10 A 0 A -0.9 mA mA A A A A A A -3 -3 -200 S1C60L16 Unless otherwise specified: VDD=1.5V, VSS=0V, fOSC1=32.768kHz, Ta=25C, VD1/VC1-VC3 are internal voltage, C1-C5=0.1F Item Condition Symbol Min. High level input voltage (1) VIH1 K00-03, K10, P00-03, P10-13 0.8*VDD High level input voltage (2) VIH2 RESET, TEST 0.9*VDD Low level input voltage (1) VIL1 K00-03, K10, P00-03, P10-13 0 Low level input voltage (2) RESET, TEST 0 VIL2 High level input current (1) VIH1=1.5V 0 IIH1 K00-03, K10, P00-03, P10-13 No pull-down AMPP, AMPM High level input current (2) 1.5 VIH2=1.5V IIH2 K00-03, K10 With pull-down High level input current (3) 1.5 VIH3=1.5V IIH3 P00-03, P10-13, RESET, TEST With pull-down Low level input current -0.5 VIL=VSS IIL K00-03, K10, P00-03, P10-13 AMPP, AMPM, RESET, TEST High level output current VOH1=0.9*VDD IOH1 R00-03, R10-13, P00-03, P10-13 Low level output current VOL1=0.1*VDD IOL1 R00-03, R10-13, P00-03, P10-13 700 Common output current IOH2 VOH2=VC3-0.05V COM0-3 3 VOL2=VSS+0.05V IOL2 Segment output current VOH3=VC3-0.05V SEG0-37 IOH3 (during LCD output) 3 IOL3 VOL3=VSS+0.05V Segment output current VOH4=0.9*VDD IOH4 SEG0-37 (during DC output) 100 VOL4=0.1*VDD IOL4 S1C60N16 TECHNICAL MANUAL EPSON Typ. Max. Unit 0 V 0 V 0.2*VDD V 0.1*VDD V A 0.5 5 A 5 A 0 A -150 A A A A A A A A -3 -3 -100 85 CHAPTER 7: ELECTRICAL CHARACTERISTICS 7.4 Analog Circuit Characteristics and Current Consumption S1C60N16 Unless otherwise specified: VDD=3.0V, VSS=0V, fOSC1=32.768kHz, Ta=25C, CG=25pF, VD1/VC1-VC3 are internal voltage, C1-C5=0.1F Min. Typ. Condition Item Symbol 0.90 0.98 Connect 1 M load resistor between VSS and VC1 LCD drive voltage VC1 (without panel load) 2*VC1 VC2 Connect 1 M load resistor between VSS and VC2 (without panel load) x0.9 Connect 1 M load resistor between VSS and VC3 VC3 3*VC1 x0.9 (without panel load) 2.20 VSVD 2.05 SVD voltage SVD circuit response time tSVD Analog comparator VIP 0.3 Non-inverted input (AMPP) VIM input voltage Inverted input (AMPM) Analog comparator VOF offset voltage tAMP VIP=1.5V Analog comparator VIM=VIP15mV response time IOP During HALT Without Current consumption 0.7 panel load During operation 1 1.4 1 The SVD circuit and analog comparator are in the OFF status. Max. 1.06 Unit V 2*VC1 V +0.1 3*VC1 V +0.1 2.35 V 100 s VDD-0.9 V 10 mV 3 ms 1.0 2.0 A A Max. 1.06 Unit V S1C60L16 Unless otherwise specified: VDD=1.5V, VSS=0V, fOSC1=32.768kHz, Ta=25C, CG=25pF, VD1/VC1-VC3 are internal voltage, C1-C5=0.1F Min. Typ. Condition Item Symbol 0.90 0.98 Connect 1 M load resistor between VSS and VC1 LCD drive voltage VC1 (without panel load) 2*VC1 VC2 Connect 1 M load resistor between VSS and VC2 (without panel load) x0.9 Connect 1 M load resistor between VSS and VC3 VC3 3*VC1 x0.9 (without panel load) 1.20 VSVD 1.10 SVD voltage SVD circuit response time tSVD Analog comparator VIP 0.3 Non-inverted input (AMPP) VIM input voltage Inverted input (AMPM) VOF Analog comparator offset voltage tAMP VIP=1.1V Analog comparator VIM=VIP30mV response time IOP During HALT Without Current consumption 0.7 panel load During operation 1 1.4 1 The SVD circuit and analog comparator are in the OFF status. 86 EPSON 2*VC1 V +0.1 3*VC1 V +0.1 1.30 V 100 s VDD-0.9 V 10 mV 3 ms 1.0 2.0 A A S1C60N16 TECHNICAL MANUAL CHAPTER 7: ELECTRICAL CHARACTERISTICS S1C60A16 Unless otherwise specified: VDD=3.0V, VSS=0V, fOSC1=32.768kHz, Ta=25C, CG=25pF, VD1/VC1-VC3 are internal voltage, C1-C5=0.1F Item Symbol Condition Min. Typ. LCD drive voltage VC1 Connect 1 M load resistor between VSS and VC1 0.90 0.98 (without panel load) VC2 Connect 1 M load resistor between VSS and VC2 2*VC1 (without panel load) x0.9 Connect 1 M load resistor between VSS and VC3 3*VC1 VC3 (without panel load) x0.9 SVD voltage VSVD 2.05 2.20 SVD circuit response time tSVD Non-inverted input (AMPP) 0.3 Analog comparator VIP Inverted input (AMPM) VIM input voltage Analog comparator VOF offset voltage Analog comparator tAMP VIP=1.5V response time VIM=VIP15mV Current consumption 1.5 IOP1 During HALT, OSC3: OFF Without (normal operation mode) 2.4 panel load During operation 1, OSC3: OFF 50 During operation at 1MHz 1, OSC3 (Ceramic): ON 85 During operation at 1MHz 1, OSC3 (CR): ON Current consumption 10.5 During HALT, OSC3: OFF Without IOP2 (heavy load protection mode) 11.5 During operation 1, OSC3: OFF panel load 60 During operation at 1MHz 1, OSC3 (Ceramic): ON 95 During operation at 1MHz 1, OSC3 (CR): ON 1 The SVD circuit and analog comparator are in the OFF status. S1C60N16 TECHNICAL MANUAL EPSON Max. 1.06 Unit V 2*VC1 V +0.1 V 3*VC1 +0.1 V 2.35 s 100 VDD-0.9 V 10 mV 3 ms 2.5 4.0 80 A A A 130 A 15.0 17.0 95 A A A 145 A 87 CHAPTER 7: ELECTRICAL CHARACTERISTICS 7.5 Oscillation Characteristics The oscillation characteristics change depending on the conditions (components used, board pattern, etc.). Use the following characteristics as reference values. S1C60N16 and S1C60A16 (OSC1 crystal oscillation circuit) Unless otherwise specified: VDD=3.0V, VSS=0V, Crystal: Q13MC146, CG=25pF, CD=built-in, Ta=25C Item Condition Symbol Oscillation start voltage tsta5sec (VDD) Vsta Oscillation stop voltage tstp10sec (VDD) Vstp Built-in capacitance (drain) Including the parasitic capacitance inside the IC CD Frequency/voltage deviation f/V VDD=2.2 to 3.6V Frequency/IC deviation f/IC Frequency adjustment range f/CG CG=5 to 25pF (VDD) Harmonic oscillation start voltage Vhho Permitted leak resistance Rleak Between OSC1 and VDD Min. 2.2 2.2 Typ. Max. 15 -10 35 5 10 45 3.6 200 Unit V V pF ppm ppm ppm V M S1C60L16 (OSC1 crystal oscillation circuit) Unless otherwise specified: VDD=1.5V, VSS=0V, Crystal: Q13MC146, CG=25pF, CD=built-in, Ta=25C Item Condition Symbol Oscillation start voltage tsta5sec (VDD) Vsta Oscillation stop voltage tstp10sec (VDD) Vstp Built-in capacitance (drain) Including the parasitic capacitance inside the IC CD Frequency/voltage deviation f/V VDD=1.2 to 1.8V Frequency/IC deviation f/IC Frequency adjustment range f/CG CG=5 to 25pF (VDD) Harmonic oscillation start voltage Vhho Between OSC1 and VDD Permitted leak resistance Rleak Min. 1.2 1.2 Typ. Max. 15 -10 35 5 10 45 1.8 200 Unit V V pF ppm ppm ppm V M S1C60A16 (OSC3 CR oscillation circuit) Unless otherwise specified: VDD=3.0V, VSS=0V, RCR=40k, Ta=25C Item Symbol Oscillation frequency dispersion fOSC3 (VDD) Oscillation start voltage Vsta Oscillation start time VDD=2.2 to 3.6V tsta Oscillation stop voltage Vstp (VDD) Condition Min. -30 2.2 Typ. 1MHz Max. 30 3 2.2 Unit % V ms V S1C60A16 (OSC3 ceramic oscillation circuit) Unless otherwise specified: VDD=3.0V, VSS=0V, Ceramic oscillator: 1MHz, CGC=CDC=100pF, Ta=25C Item Symbol Condition Oscillation start voltage Vsta (VDD) Oscillation start time tsta VDD=2.2 to 3.6V Oscillation stop voltage Vstp (VDD) 88 EPSON Min. 2.2 Typ. Max. 5 2.2 Unit V ms V S1C60N16 TECHNICAL MANUAL CHAPTER 7: ELECTRICAL CHARACTERISTICS 7.6 Serial Interface AC Characteristics Clock synchronous master mode * During 32 kHz operation Condition: VDD=3.0V, VSS=0V, Ta=25C, VIH1=0.8VDD, VIL1=0.2VDD, VOH=0.8VDD, VOL=0.2VDD Min. Typ. Item Symbol Transmitting data output delay time tsmd tsms 10 Receiving data input set-up time tsmh 5 Receiving data input hold time Max. 5 Unit s s s Max. 10 Unit s s s Clock synchronous slave mode * During 32 kHz operation Condition: VDD=3.0V, VSS=0V, Ta=25C, VIH1=0.8VDD, VIL1=0.2VDD, VOH=0.8VDD, VOL=0.2VDD Item Symbol Min. Typ. Transmitting data output delay time tssd tsss Receiving data input set-up time 10 Receiving data input hold time tssh 5 <Master mode> SCLK OUT SOUT VOH VOL tsmd VOH VOL tsms tsmh VIH1 VIL1 SIN <Slave mode> SCLK IN SOUT VIH1 VIL1 tssd VOH VOL tsss SIN S1C60N16 TECHNICAL MANUAL tssh VIH1 VIL1 EPSON 89 CHAPTER 8: PACKAGE CHAPTER 8 PACKAGE 8.1 Plastic Package QFP14-80pin (Unit: mm) 140.4 120.1 60 41 61 140.4 120.1 40 INDEX 80 21 1.40.1 20 0.5 +0.1 0.18 -0.05 +0.05 0.125 -0.025 0 10 0.2 0.5 0.1 1.7max 1 1 90 EPSON S1C60N16 TECHNICAL MANUAL CHAPTER 8: PACKAGE 8.2 Ceramic Package for Test Samples QFP5-80pin (Unit: mm) 26.8 0.15 20.0 0.18 80 25 0.35 0.05 24 0.95 0.08 0.05 0.76 0.08 0.80 0.8 0.4 0.08 1 0.15 40 0.14 65 20.9 41 14.0 64 Grass S1C60N16 TECHNICAL MANUAL EPSON 91 CHAPTER 9: PAD LAYOUT CHAPTER 9 PAD LAYOUT 9.1 Diagram of Pad Layout 79 15 10 5 1 20 75 25 Y 30 40 X 65 Die No. 35 (0, 0) 2.72 mm 70 45 50 55 60 2.74 mm Chip thickness: 400m Pad opening: 85m 92 EPSON S1C60N16 TECHNICAL MANUAL CHAPTER 9: PAD LAYOUT 9.2 Pad Coordinates (Unit: m) No. Pad name 1 P13 2 P12 3 P11 4 P10 5 P03 6 P02 7 P01 8 P00 9 R13 10 R12 11 R11 12 R10 13 R03 14 R02 15 R01 16 R00 17 K00 18 K01 19 K02 20 K03 21 K10 22 VSS AMPM 23 AMPP 24 OSC1 25 OSC2 26 VD1 27 X 952 842 732 622 511 401 291 181 59 -50 -160 -271 -381 -491 -601 -712 -834 -944 -1,236 -1,236 -1,236 -1,236 -1,236 -1,236 -1,236 -1,236 -1,236 S1C60N16 TECHNICAL MANUAL Y 1,230 1,230 1,230 1,230 1,230 1,230 1,230 1,230 1,230 1,230 1,230 1,230 1,230 1,230 1,230 1,230 1,230 1,230 1,169 1,059 948 828 718 608 497 387 277 No. Pad name 28 OSC3 29 OSC4 30 VDD 31 VC3 32 VC2 33 VC1 34 CB 35 CA 36 COM3 37 COM2 38 COM1 39 COM0 40 SEG37 41 SEG36 42 SEG35 43 SEG34 44 SEG33 45 SEG32 46 SEG31 47 SEG30 48 SEG29 49 SEG28 50 SEG27 51 SEG26 52 SEG25 53 SEG24 54 SEG23 X -1,236 -1,236 -1,236 -1,236 -1,236 -1,236 -1,236 -1,236 -1,236 -1,236 -1,236 -1,200 -1,090 -980 -869 -759 -649 -539 -428 -318 -208 -98 12 122 232 343 453 EPSON Y 167 56 -53 -163 -274 -384 -494 -604 -715 -825 -935 -1,230 -1,230 -1,230 -1,230 -1,230 -1,230 -1,230 -1,230 -1,230 -1,230 -1,230 -1,230 -1,230 -1,230 -1,230 -1,230 No. Pad name 55 SEG22 56 SEG21 57 SEG20 58 SEG19 59 SEG18 60 SEG17 61 SEG16 62 SEG15 63 SEG14 64 SEG13 65 SEG12 66 SEG11 67 SEG10 68 SEG9 69 SEG8 70 SEG7 71 SEG6 72 SEG5 73 SEG4 74 SEG3 75 SEG2 76 SEG1 77 SEG0 78 RESET 79 TEST - - X 563 673 784 894 1,092 1,202 1,236 1,236 1,236 1,236 1,236 1,236 1,236 1,236 1,236 1,236 1,236 1,236 1,236 1,236 1,236 1,236 1,236 1,236 1,236 Y -1,230 -1,230 -1,230 -1,230 -1,230 -1,230 -776 -666 -556 -446 -335 -225 -115 -5 105 215 325 435 546 656 766 876 987 1,114 1,224 93 REVISION HISTORY Revision History Code No. 404539503 Page 1, 3, 4, 90 5 6 8 9 39 46 Contents Package Deleted QFP5-80pin(S2) Option List: 3. MULTIPLE KEY ENTRY RESET 2. Not Use (Old) TIME AUTHORIZE ..... 1. Use 2. Use (New) TIME AUTHORIZE ..... 1. Not Use Option List: 17. LCD BIAS & POWER SOURCE 1. 1/3 Bias, Regulator Used, LCD 3 V (Old) S1C60N16 ..... 2. 1/3 Bias, Regulator Not Used, LCD 3 V 3. 1/2 Bias, Regulator Not Used, LCD 3 V 1. 1/3 Bias, Regulator Used, LCD 3 V S1C60L16 ..... 2. 1/2 Bias, Regulator Not Used, LCD 3 V 1. 1/3 Bias, Regulator Used, LCD 3 V (New) S1C60N16 ..... 1. 1/3 Bias, Regulator Used, LCD 3 V S1C60L16 ..... Power Supply (Old) The LCD system voltage regulator can be disabled by mask option. ... Fig. 2.1.2 External elements when LCD system voltage regulator is not used (New) The LCD system voltage regulator in the S1C60A16 can be disabled by mask option. ... Fig. 2.1.2 External elements when LCD system voltage regulator is not used (S1C60A16) Initial Reset: Configuration of initial reset circuit Modified Figure 2.2.1 LCD Driver: Configuration of LCD driver (Old) Moreover, the 1/2 bias dynamic drive that uses three types of potential, VSS, VC1 = VC2 and VC3, can be selected by setting the mask option (drive duty can also be selected from 1/4, 1/3 or 1/2). (New) In the S1C60A16, the 1/2 bias dynamic drive that uses three types of potential, VSS, VC1 = VC2 and VC3, can be selected by setting the mask option (drive duty can also be selected from 1/4, 1/3 or 1/2). LCD Driver: Drive bias (Old) For the drive bias of the S1C60N16 or the S1C60L16, either 1/3 bias or 1/2 bias can be selected by the mask option. (New) For the drive bias of the S1C60A16, either 1/3 bias or 1/2 bias can be selected by the mask option. International Sales Operations AMERICA ASIA EPSON ELECTRONICS AMERICA, INC. EPSON (CHINA) CO., LTD. 2580 Orchard Parkway, San Jose, CA 95131, USA Phone: +1-800-228-3964 7F, Jinbao Bldg., No.89 Jinbao St., Dongcheng District, Beijing 100005, CHINA Phone: +86-10-8522-1199 Fax: +86-10-8522-1125 Fax: +1-408-922-0238 EUROPE EPSON EUROPE ELECTRONICS GmbH Riesstrasse 15, 80992 Munich, GERMANY Phone: +49-89-14005-0 Fax: +49-89-14005-110 SHANGHAI BRANCH 7F, Block B, Hi-Tech Bldg., 900 Yishan Road, Shanghai 200233, CHINA Phone: +86-21-5423-5577 Fax: +86-21-5423-4677 SHENZHEN BRANCH 12F, Dawning Mansion, Keji South 12th Road, Hi-Tech Park, Shenzhen 518057, CHINA Phone: +86-755-2699-3828 Fax: +86-755-2699-3838 EPSON HONG KONG LTD. 20/F, Harbour Centre, 25 Harbour Road, Wanchai, Hong Kong Phone: +852-2585-4600 Fax: +852-2827-4346 Telex: 65542 EPSCO HX EPSON TAIWAN TECHNOLOGY & TRADING LTD. 14F, No. 7, Song Ren Road, Taipei 110, TAIWAN Phone: +886-2-8786-6688 Fax: +886-2-8786-6660 EPSON SINGAPORE PTE., LTD. 1 HarbourFront Place, #03-02 HarbourFront Tower One, Singapore 098633 Phone: +65-6586-5500 Fax: +65-6271-3182 SEIKO EPSON CORP. KOREA OFFICE 5F, KLI 63 Bldg., 60 Yoido-dong, Youngdeungpo-Ku, Seoul 150-763, KOREA Phone: +82-2-784-6027 Fax: +82-2-767-3677 SEIKO EPSON CORP. MICRODEVICES OPERATIONS DIVISION Device Sales & Marketing Dept. 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-42-587-5814 Fax: +81-42-587-5117 Document Code: 404539503 First Issue October 2002 Revised March 2011 in JAPAN L