TPS796 www.ti.com SLVS351O - SEPTEMBER 2002 - REVISED NOVEMBER 2013 Ultralow-Noise, High PSRR, Fast, RF, 1A Low-Dropout Linear Regulators FEATURES DESCRIPTION * 1A Low-Dropout Regulator With Enable * Available in Fixed and Adjustable (1.2V to 5.5V) Versions * High PSRR (53dB at 10kHz) * Ultralow-Noise (40VRMS, TPS79630) * Fast Start-Up Time (50s) * Stable With a 1F Ceramic Capacitor * Excellent Load/Line Transient Response * Very Low Dropout Voltage (250mV at Full Load, TPS79630) * 3 x 3 SON PowerPADTM, SOT223-6, and DDPAK-5 Packages The TPS796xx family of low-dropout (LDO) lowpower linear voltage regulators features high power supply rejection ratio (PSRR), ultralow-noise, fast start-up, and excellent line and load transient responses in small outline, 3 x 3 SON, SOT223-6, and DDPAK-5 packages. Each device in the family is stable with a small 1F ceramic capacitor on the output. The family uses an advanced, proprietary BiCMOS fabrication process to yield extremely low dropout voltages (for example, 250mV at 1A). Each device achieves fast start-up times (approximately 50s with a 0.001F bypass capacitor) while consuming very low quiescent current (265 A typical). Moreover, when the device is placed in standby mode, the supply current is reduced to less than 1A. The TPS79630 exhibits approximately 40VRMS of output voltage noise at 3.0V output, with a 0.1F bypass capacitor. Applications with analog components that are noise sensitive, such as portable RF electronics, benefit from the high PSRR, low noise features, and the fast response time. 1 234 APPLICATIONS RF: VCOs, Receivers, ADCs Audio BluetoothTM, Wireless LAN Cellular and Cordless Telephones Handheld Organizers, PDAs DRB PACKAGE 3mm x 3mm SON (TOP VIEW) EN IN GND OUT NR/FB IN 1 IN 2 OUT 3 OUT 4 1 2 3 4 5 8 EN 7 NC 0.7 80 70 5 NR/FB IOUT = 1 mA 60 6 GND KTT (DDPAK) PACKAGE (TOP VIEW) EN IN GND OUT NR/FB TPS79630 OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY 6 GND 1 2 3 4 5 Ripple Rejection - dB DCQ PACKAGE SOT223-6 (TOP VIEW) TPS79630 RIPPLE REJECTION vs FREQUENCY 50 Output Spectral Noise Density - mV/OHz * * * * * VIN = 4 V COUT = 10 mF CNR = 0.01 mF IOUT = 1 A 40 30 20 10 0 1 10 100 1k 10k 100k Frequency (Hz) 1M 10M 0.6 VIN = 5.5 V COUT = 2.2 mF CNR = 0.1 mF 0.5 0.4 0.3 IOUT = 1 mA 0.2 0.1 IOUT = 1.5 A 0.0 100 1k 10k 100k Frequency (Hz) 1 2 3 4 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments Inc. Bluetooth is a trademark of Bluetooth SIG, Inc. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2002-2013, Texas Instruments Incorporated TPS796 SLVS351O - SEPTEMBER 2002 - REVISED NOVEMBER 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT TPS796xx yyy z (1) (2) VOUT (2) XX is nominal output voltage (for example, 28 = 2.8V, 01 = Adjustable). YYY is package designator. Z is package quantity. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Output voltages from 1.3V to 4.9V in 100mV increments are available; minimum order quantities may apply. Contact factory for details and availability. ABSOLUTE MAXIMUM RATINGS (1) Over operating temperature range (unless otherwise noted). UNIT VIN range -0.3V to 6V VEN range -0.3V to VIN + 0.3V VOUT range 6V Peak output current Internally limited ESD rating, HBM 2kV ESD rating, CDM 500V Continuous total power dissipation See Thermal Information Table Junction temperature range, TJ -40C to +150C Storage temperature range, Tstg -65C to +150C (1) 2 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Submit Documentation Feedback Copyright (c) 2002-2013, Texas Instruments Incorporated TPS796 www.ti.com SLVS351O - SEPTEMBER 2002 - REVISED NOVEMBER 2013 THERMAL INFORMATION TPS796xx (3) THERMAL METRIC (1) (2) JA Junction-to-ambient thermal resistance (4) JCtop Junction-to-case (top) thermal resistance (5) (6) DRB DCQ KTT 8 PINS 6 PINS 5 PINS 47.8 70.4 25 83 70 35 JB Junction-to-board thermal resistance N/A N/A N/A JT Junction-to-top characterization parameter (7) 2.1 6.8 1.5 JB Junction-to-board characterization parameter (8) 17.8 30.1 8.52 JCbot Junction-to-case (bottom) thermal resistance (9) 12.1 6.3 0.4 (1) (2) (3) (4) (5) (6) (7) (8) (9) UNITS C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A. For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator. Thermal data for the DRB, DCQ, and DRV packages are derived by thermal simulations based on JEDEC-standard methodology as specified in the JESD51 series. The following assumptions are used in the simulations: (a) i. DRB: The exposed pad is connected to the PCB ground layer through a 2x2 thermal via array. . ii. DCQ: The exposed pad is connected to the PCB ground layer through a 3x2 thermal via array. . iii. KTT: The exposed pad is connected to the PCB ground layer through a 5x4 thermal via array. (b) i. DRB: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper coverage. . ii. DCQ: Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage. . iii. KTT: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper coverage. (c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in x 3in copper area. To understand the effects of the copper area on thermal performance, see the Power Dissipation and Estimating Junction Temperature sections of this data sheet. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data to obtain JA using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, JB, estimates the junction temperature of a device in a real system and is extracted from the simulation data to obtain JA using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Copyright (c) 2002-2013, Texas Instruments Incorporated Submit Documentation Feedback 3 TPS796 SLVS351O - SEPTEMBER 2002 - REVISED NOVEMBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS Over recommended operating temperature range (TJ = -40C to +125C), VEN = VIN,, VIN = VOUT(nom) + 1 V (1), IOUT = 1mA, COUT = 10F, and CNR = 0.01F, unless otherwise noted. Typical values are at +25C. PARAMETER TEST CONDITIONS MIN VIN Input voltage (1) VFB Internal reference (TPS79601) 1.200 IOUT Continuous output current Output TPS79601 voltage range Output voltage TPS79601 (2) Accuracy UNIT 5.5 V 1.250 V 1 A 1.225 5.5 - VDD V 1.02VOUT V 0.98VOUT 1.225 MAX 0 0A IOUT 1A, VOUT + 1V VIN 5.5V (1) VOUT Fixed VOUT < 5V 0A IOUT 1A, VOUT + 1V VIN 5.5V (1) -2.0 +2.0 % Fixed VOUT = 5V 0A IOUT 1A, VOUT + 1V VIN 5.5V (1) -3.0 +3.0 % 0.12 %/V Output voltage line regulation (VOUT%/VIN) (1) VOUT + 1V VIN 5.5V Load regulation (VOUT%/IOUT) 0A IOUT 1A TPS79628 TPS79628DRB Dropout voltage (3) TPS79630 (VIN = VOUT (nom) - 0.1V) TPS79633 TPS79650 5 365 52 90 IOUT = 1A 250 345 IOUT = 1A 220 325 200 300 IOUT = 250mA IOUT = 1A Ground pin current 0A IOUT 1A Shutdown current (4) VEN = 0V, 2.7V VIN 5.5V FB pin current VFB = 1.225V 2.4 A 265 385 A 0.07 1 A 1 A 59 f = 100Hz, IOUT = 1A 54 f = 10kHz, IOUT = 1A 53 BW = 100Hz to 100kHz, IOUT = 1A Time, start-up (TPS79630) RL = 3, COUT = 1F EN pin current VEN = 0V UVLO threshold VCC rising mV 4.2 f = 100Hz, IOUT = 10mA f = 100kHz, IOUT = 1A Output noise voltage (TPS79630) mV 270 VOUT = 0V TPS79630 0.05 IOUT = 1A Output current limit Power-supply ripple rejection TYP 2.7 dB 42 CNR = 0.001F 54 CNR = 0.0047F 46 CNR = 0.01F 41 CNR = 0.1F 40 CNR = 0.001F 50 CNR = 0.0047F 75 CNR = 0.01F VRMS s 110 -1 1 A 2.25 2.65 V UVLO hysteresis 100 mV High-level enable input voltage 2.7V VIN 5.5V 1.7 VIN V Low-level enable input voltage 2.7V VIN 5.5V 0 0.7 V (1) (2) (3) (4) 4 Minimum VIN = VOUT + VDO or 2.7V, whichever is greater. TPS79650 is tested at VIN = 5.5V. Tolerance of external resistors not included in this specification. VDO is not measured for TPS79618 and TPS79625 because minimum VIN = 2.7V. For adjustable version, this applies only after VIN is applied; then VEN transitions high to low. Submit Documentation Feedback Copyright (c) 2002-2013, Texas Instruments Incorporated TPS796 www.ti.com SLVS351O - SEPTEMBER 2002 - REVISED NOVEMBER 2013 FUNCTIONAL BLOCK DIAGRAM--ADJUSTABLE VERSION IN OUT Current Sense UVLO SHUTDOWN ILIM _ GND R1 + FB EN UVLO R2 Thermal Shutdown Quickstart Bandgap Reference 1.225 V VIN 250 k External to the Device VREF FUNCTIONAL BLOCK DIAGRAM--FIXED VERSION IN OUT UVLO Current Sense GND SHUTDOWN ILIM _ EN R1 + UVLO Thermal Shutdown R2 Quickstart VIN Bandgap Reference 1.225 V R2 = 40k 250 k VREF NR Table 1. Terminal Functions TERMINAL NAME SOT223 (DCQ) DDPAK (KTT) SON (DRB) DESCRIPTION NR 5 5 Connecting an external capacitor to this pin bypasses noise generated by the internal bandgap. This improves power-supply rejection and reduces output noise. FB 5 5 This terminal is the feedback input voltage for the adjustable device. EN 1 8 Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown mode. EN can be connected to IN if not used. GND 3, Tab IN 2 1, 2 Unregulated input to the device. OUT 4 3, 4 Output of the regulator. 6, PowerPAD Regulator ground Copyright (c) 2002-2013, Texas Instruments Incorporated Submit Documentation Feedback 5 TPS796 SLVS351O - SEPTEMBER 2002 - REVISED NOVEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS TPS79630 OUTPUT VOLTAGE vs OUTPUT CURRENT TPS79628 OUTPUT VOLTAGE vs JUNCTION TEMPERATURE TPS79628 GROUND CURRENT vs JUNCTION TEMPERATURE 2.795 4 3.05 VIN = 4 V COUT = 10 F TJ = 25C 3.04 3.03 350 VIN = 3.8 V COUT = 10 F IOUT = 1 mA 3 2.790 3.02 330 VOUT (V) 3.00 2.99 2.98 IGND (A) 3.01 VOUT (V) VIN = 3.8 V COUT = 10 F 340 2 2.785 IOUT = 1 A 320 IOUT = 1 A 310 1 2.780 IOUT = 1 mA 2.97 300 2.96 2.95 0.0 0.2 0.4 0.6 0.8 0 2.775 -40 -25 -10 5 1.0 20 35 50 65 80 95 110 125 TJ (C) TJ (C) Figure 2. Figure 3. TPS79630 OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY TPS79630 OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY TPS79630 OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY 0.7 0.6 VIN = 5.5 V COUT = 2.2 F CNR = 0.1 F 0.6 0.5 0.4 0.3 IOUT = 1 mA 0.2 0.1 IOUT = 1.5 A 0.0 100 1k 10k 2.5 VIN = 5.5 V COUT = 10 F CNR = 0.1 F 0.5 0.4 IOUT = 1 mA 0.3 0.2 IOUT = 1 A 0.1 0.0 100 100k Output Spectral Noise Density - V//Hz Output Spectral Noise Density - V//Hz Figure 1. 1k 10k CNR = 0.01 F CNR = 0.1 F 1.5 CNR = 0.0047 F 1.0 CNR = 0.001 F 0.5 0.0 100 100k 1k 10k Frequency (Hz) Frequency (Hz) Figure 4. Figure 5. Figure 6. TPS79630 ROOT MEAN SQUARED OUTPUT NOISE vs BYPASS CAPACITANCE TPS79628 DROPOUT VOLTAGE vs JUNCTION TEMPERATURE TPS79630 RIPPLE REJECTION vs FREQUENCY 350 60 300 50 70 IOUT = 1 A Ripple Rejection - dB 20 200 150 100 IOUT = 250 mA COUT = 10 F BW = 100 Hz to 100 kHz 0 0.001 F 0.0047 F 0.01 F 50 0.1 F IOUT = 1 mA 60 40 30 IOUT = 250 mA 0 -40-25 -10 5 20 35 50 65 80 95 110 125 50 VIN = 4 V COUT = 10 F CNR = 0.01 F IOUT = 1 A 40 30 20 10 0 1 10 100 1k 10k 100k CNR (F) TJ (_C) Frequency (Hz) Figure 7. Figure 8. Figure 9. Submit Documentation Feedback 100k 80 VIN = 2.7 V COUT = 10 F 250 10 2.0 VIN = 5.5 V COUT = 10 F IOUT = 1 A Frequency (Hz) VDO (mV) RMS - Root Mean Squared Output Noise - VRMS Output Spectral Noise Density - V//Hz IOUT (A) 6 290 -40 -25 -10 5 20 35 50 65 80 95 110 125 1M 10M Copyright (c) 2002-2013, Texas Instruments Incorporated TPS796 www.ti.com SLVS351O - SEPTEMBER 2002 - REVISED NOVEMBER 2013 TYPICAL CHARACTERISTICS (continued) TPS79630 RIPPLE REJECTION vs FREQUENCY TPS79630 RIPPLE REJECTION vs FREQUENCY 80 VIN = 4 V COUT = 10 F CNR = 0.1 F 60 50 Ripple Rejection - dB IOUT = 1 mA VIN = 4 V COUT = 2.2 F CNR = 0.01 F 70 IOUT = 1 A 40 30 20 IOUT = 1 mA 60 VIN = 4 V, COUT = 10 F, IOUT = 1.0 A 2.75 2.50 IOUT = 1 A 40 30 Enable CNR = 0.001 F 2 50 CNR = 0.0047 F 2.25 VOUT (V) 70 Ripple Rejection - dB START-UP TIME 3 80 1.75 1.50 CNR = 0.01 F 1.25 1 20 10 10 0 0 0.75 0.50 0.25 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M 300 400 500 600 Figure 10. Figure 11. Figure 12. TPS79618 LINE TRANSIENT RESPONSE TPS79630 LINE TRANSIENT RESPONSE TPS79628 LOAD TRANSIENT RESPONSE 1 dv 1V + ms dt IOUT = 1 A COUT = 10 F CNR = 0.01 F IOUT (A) 5 3 4 IOUT = 1 A COUT = 10 F CNR = 0.01 F 3 VOUT (mV) 0 -20 -40 dv 1V + ms dt 150 20 0 -20 -40 20 40 60 80 100 120 140 160 180 200 0 0 -1 VOUT (mV) 40 20 20 40 60 80 100 120 140 160 180 200 VIN = 3.8 V COUT = 10 F CNR = 0.01 F di 1A + ms dt 75 0 -75 -150 0 100 200 300 400 500 600 700 800 900 1000 t (s) t (s) Figure 13. Figure 14. Figure 15. TPS79625 TPS79630 DROPOUT VOLTAGE vs OUTPUT CURRENT TPS79601 DROPOUT VOLTAGE vs INPUT VOLTAGE POWER UP/POWER DOWN t (s) 300 350 4.0 VOUT = 2.5 V RL = 10 CNR = 0.01 F 3.0 200 t (ms) 4 3.5 100 Frequency (Hz) 2 0 0 Frequency (Hz) 6 40 300 250 TJ = 125C TJ = 125C 250 2.5 2.0 200 VDO (mV) 200 VDO (mV) 500 mV/Div 0 1 5 2 VOUT (mV) 10 VIN (V) VIN (V) 1 TJ = 25C 150 1.5 100 1.0 VOUT TJ = -40C 0 1 2 3 4 5 6 7 8 9 10 0 0 100 200 300 400 500 600 700 800 9001000 200 s/Div IOUT (mA) Figure 16. Figure 17. Copyright (c) 2002-2013, Texas Instruments Incorporated IOUT = 1 A COUT = 10 F CNR = 0.01 F 50 50 0 0 TJ = -40C 100 VIN 0.5 TJ = 25C 150 2.5 3.0 3.5 4.0 4.5 5.0 VIN (V) Figure 18. Submit Documentation Feedback 7 TPS796 SLVS351O - SEPTEMBER 2002 - REVISED NOVEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) TPS79630 TYPICAL REGIONS OF STABILITY EQUIVALENT SERIES RESISTANCE (ESR) vs OUTPUT CURRENT TPS79630 TYPICAL REGIONS OF STABILITY EQUIVALENT SERIES RESISTANCE (ESR) vs OUTPUT CURRENT Region of Instability 10 1 Region of Stability 0.1 COUT = 2.2 F Region of Instability 10 1 Region of Stability 0.1 0.01 0.01 1 8 ESR - Equivalent Series Resistance - ESR - Equivalent Series Resistance - COUT = 1 F ESR - Equivalent Series Resistance - 100 100 10 30 60 125 250 500 750 1000 TPS79630 TYPICAL REGIONS OF STABILITY EQUIVALENT SERIES RESISTANCE (ESR) vs OUTPUT CURRENT 100 COUT = 10.0 F Region of Instability 10 1 Region of Stability 0.1 0.01 1 10 30 60 125 250 500 750 1000 1 10 30 60 125 250 500 750 1000 IOUT (mA) IOUT (mA) IOUT (mA) Figure 19. Figure 20. Figure 21. Submit Documentation Feedback Copyright (c) 2002-2013, Texas Instruments Incorporated TPS796 www.ti.com SLVS351O - SEPTEMBER 2002 - REVISED NOVEMBER 2013 APPLICATION INFORMATION The TPS796xx family of low-dropout (LDO) regulators has been optimized for use in noise-sensitive equipment. The device features extremely low dropout voltages, high PSRR, ultralow output noise, low quiescent current (265A typically), and enable input to reduce supply currents to less than 1A when the regulator is turned off. A typical application circuit is shown in Figure 22. VIN IN VOUT OUT TPS796xx 2.2F EN GND 1 F NR 0.01F Figure 22. Typical Application Circuit External Capacitor Requirements Although not required, it is good analog design practice to place a 0.1F to 2.2F capacitor near the input of the regulator to counteract reactive input sources. A 2.2F or larger ceramic input bypass capacitor, connected between IN and GND and located close to the TPS796xx, is required for stability and improves transient response, noise rejection, and ripple rejection. A higher-value input capacitor may be necessary if large, fast-rise-time load transients are anticipated and the device is located several inches from the power source. Like most low dropout regulators, the TPS796xx requires an output capacitor connected between OUT and GND to stabilize the internal control loop. The minimum recommended capacitor is 1F. Any 1F or larger ceramic capacitor is suitable. The internal voltage reference is a key source of noise in an LDO regulator. The TPS796xx has an NR pin which is connected to the voltage reference through a 250k internal resistor. The 250k internal resistor, in conjunction with an external bypass capacitor connected to the NR pin, creates a lowpass filter to reduce the voltage reference noise and, therefore, the noise at the regulator output. In order for the regulator to operate properly, the current flow out of the NR pin must be at a minimum, because any leakage current creates an IR drop across the internal resistor, thus creating an output error. Therefore, the bypass capacitor must have minimal leakage current. The bypass capacitor should be no more than 0.1F in order to ensure that it is fully charged during the quickstart time provided by the internal switch shown in the functional block diagram. Copyright (c) 2002-2013, Texas Instruments Incorporated For example, the TPS79630 exhibits 40VRMS of output voltage noise using a 0.1F ceramic bypass capacitor and a 10F ceramic output capacitor. Note that the output starts up slower as the bypass capacitance increases due to the RC time constant at the bypass pin that is created by the internal 250k resistor and external capacitor. Board Layout Recommendation to Improve PSRR and Noise Performance To improve ac measurements like PSRR, output noise, and transient response, it is recommended that the board be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at the ground pin of the device. In addition, the ground connection for the bypass capacitor should connect directly to the ground pin of the device. Regulator Mounting The tab of the SOT223-6 package is electrically connected to ground. For best thermal performance, the tab of the surface-mount version should be soldered directly to a circuit-board copper area. Increasing the copper area improves heat dissipation. Solder pad footprint recommendations for the devices are presented in an application bulletin Solder Pad Recommendations for Surface-Mount Devices, literature number AB-132, available for download from the TI web site (www.ti.com). Programming the TPS79601 Adjustable LDO Regulator The output voltage of the TPS79601 adjustable regulator is programmed using an external resistor divider (see Figure 23). The output voltage is calculated using Equation 1: V OUT + VREF 1) R1 R2 (1) where: * VREF = 1.2246V typ (the internal reference voltage) Resistors R1 and R2 should be chosen for approximately 40A divider current. Lower value resistors can be used for improved noise performance, but the device wastes more power. Higher values should be avoided, as leakage current at FB increases the output voltage error. Submit Documentation Feedback 9 TPS796 SLVS351O - SEPTEMBER 2002 - REVISED NOVEMBER 2013 www.ti.com Regulator Protection The recommended design procedure is to choose R2 = 30.1k to set the divider current at 40A, C1 = 15pF for stability, and then calculate R1 using Equation 2: R1 + VV OUT REF *1 The TPS796xx PMOS-pass transistor has a built-in back diode that conducts reverse current when the input voltage drops below the output voltage (for example, during power-down). Current is conducted from the output to the input and is not internally limited. If extended reverse voltage operation is anticipated, external limiting might be appropriate. R2 (2) In order to improve the stability of the adjustable version, it is suggested that a small compensation capacitor be placed between OUT and FB. The approximate value of this capacitor can be calculated as Equation 3: (3 x 10 -7) x (R1 ) R2) C1 + (R1 x R2) (3) The TPS796xx features internal current limiting and thermal protection. During normal operation, the TPS796xx limits output current to approximately 2.8A. When current limiting engages, the output voltage scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds approximately +165C, thermal-protection circuitry shuts it down. Once the device has cooled down to below approximately +140C, regulator operation resumes. The suggested value of this capacitor for several resistor ratios is shown in the table in Figure 23. If this capacitor is not used (such as in a unity-gain configuration) then the minimum recommended output capacitor is 2.2F instead of 1F. VIN IN 2.2 F OUT TPS79601 EN GND OUTPUT VOLTAGE PROGRAMMING GUIDE VOUT R1 FB R2 C1 1 F OUTPUT VOLTAGE R1 R2 C1 1.8 V 14.0 k 30.1 k 33 pF 3.6V 57.9 k 30.1 k 15 pF Figure 23. TPS79601 Adjustable LDO Regulator Programming 10 Submit Documentation Feedback Copyright (c) 2002-2013, Texas Instruments Incorporated TPS796 www.ti.com SLVS351O - SEPTEMBER 2002 - REVISED NOVEMBER 2013 THERMAL INFORMATION Knowing the device power dissipation and proper sizing of the thermal plane that is connected to the tab or pad is critical to avoiding thermal shutdown and ensuring reliable operation. Power dissipation of the device depends on input voltage and load conditions and can be calculated using Equation 4: P D + VIN * VOUT I OUT (4) Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input voltage necessary to achieve the required output voltage regulation. On the SON (DRB) package, the primary conduction path for heat is through the exposed pad to the printed circuit board (PCB). The pad can be connected to ground or be left floating; however, it should be attached to an appropriate amount of copper PCB area to ensure the device does not overheat. On both SOT-223 (DCQ) and DDPAK (KTT) packages, the primary conduction path for heat is through the tab to the PCB. That tab should be connected to ground. The maximum junction-toambient thermal resistance depends on the maximum ambient temperature, maximum device junction temperature, and power dissipation of the device and can be calculated using Equation 5: ()125OC * T A) R qJA + PD (5) Copyright (c) 2002-2013, Texas Instruments Incorporated Knowing the maximum RJA, the minimum amount of PCB copper area needed for appropriate heatsinking can be estimated using Figure 24. 160 DCQ DRB KTT 140 120 qJA (C/W) POWER DISSIPATION 100 80 60 40 20 0 0 Note: 1 2 4 5 7 3 6 Board Copper Area (in2) 8 9 10 JA value at board size of 9in2 (that is, 3in x 3in) is a JEDEC standard. Figure 24. JA vs Board Size Figure 24 shows the variation of JA as a function of ground plane copper area in the board. It is intended only as a guideline to demonstrate the effects of heat spreading in the ground plane and should not be used to estimate actual thermal performance in real application environments. NOTE: When the device is mounted on an application PCB, it is strongly recommended to use JT and JB, as explained in the Estimating Junction Temperature section. Submit Documentation Feedback 11 TPS796 SLVS351O - SEPTEMBER 2002 - REVISED NOVEMBER 2013 www.ti.com ESTIMATING JUNCTION TEMPERATURE 35 YJB: TJ = TB + YJB * PD 30 YJT and YJB (C/W) Using the thermal metrics JT and JB, as shown in the Thermal Information table, the junction temperature can be estimated with corresponding formulas (given in Equation 6). For backwards compatibility, an older JC,Top parameter is listed as well. YJT: TJ = TT + YJT * PD (6) For more information about measuring TT and TB, see the application note SBVA025, Using New Thermal Metrics, available for download at www.ti.com. By looking at Figure 25, the new thermal metrics (JT and JB) have very little dependency on board size. That is, using JT or JB with Equation 6 is a good way to estimate TJ by simply measuring TT or TB, regardless of the application board size. 20 15 10 DCQ YJT 5 Where PD is the power dissipation shown by Equation 5, TT is the temperature at the center-top of the IC package, and TB is the PCB temperature measured 1mm away from the IC package on the PCB surface (as Figure 26 shows). NOTE: Both TT and TB can be measured on actual application boards using a thermo-gun (an infrared thermometer). DCQ DRB YJB KTT 25 DRB YJT 0 0 1 2 3 4 5 7 6 8 9 10 Board Copper Area (in2) Figure 25. JT and JB vs Board Size For a more detailed discussion of why TI does not recommend using JC(top) to determine thermal characteristics, refer to application report SBVA025, Using New Thermal Metrics, available for download at www.ti.com. For further information, refer to application report SPRA953, IC Package Thermal Metrics, also available on the TI website. (1) TB 1mm KTT YJT TT on top of IC X TT on top of IC TB on PCB surface TB on PCB TT surface (2) 1mm X 1mm (a) Example DRB (SON) Package Measurement (b) Example DCQ (SOT-223) Package Measurement (1) TT is measured at the center of both the X- and Y-dimensional axes. (2) TB is measured below the package lead on the PCB surface. (c) Example KTT (DDPAK) Package Measurement Figure 26. Measuring Points for TT and TB 12 Submit Documentation Feedback Copyright (c) 2002-2013, Texas Instruments Incorporated TPS796 www.ti.com SLVS351O - SEPTEMBER 2002 - REVISED NOVEMBER 2013 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision N (January 2011) to Revision O Page * Changed Power-Supply Ripple Rejection 3rd test condition from "f = 10Hz" to "f = 10kHz" (typo) ..................................... 4 * Changed Power-Supply Ripple Rejection 4th test condition from "f = 100Hz" to "f = 100kHz" (typo) ................................. 4 Changes from Revision M (October 2010) to Revision N * Page Corrected typo in front-page figure ....................................................................................................................................... 1 Changes from Revision L (August 2010) to Revision M * Page Corrected typo in Figure 26 ................................................................................................................................................ 12 Copyright (c) 2002-2013, Texas Instruments Incorporated Submit Documentation Feedback 13 PACKAGE OPTION ADDENDUM www.ti.com 16-Oct-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) TPS79601DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 PS79601 TPS79601DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PS79601 TPS79601DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 PS79601 TPS79601DCQRG4 ACTIVE SOT-223 DCQ 6 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PS79601 TPS79601DRBR ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 CES TPS79601DRBRG4 ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 CES TPS79601DRBT ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 CES TPS79601DRBTG4 ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 CES TPS79601KTT OBSOLETE DDPAK/ TO-263 KTT 5 TBD Call TI Call TI -40 to 125 TPS79601KTTR ACTIVE DDPAK/ TO-263 KTT 5 500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 TPS 79601 TPS79601KTTRG3 ACTIVE DDPAK/ TO-263 KTT 5 500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 TPS 79601 TPS79601KTTT ACTIVE DDPAK/ TO-263 KTT 5 50 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 TPS 79601 TPS79601KTTTG3 ACTIVE DDPAK/ TO-263 KTT 5 50 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 TPS 79601 TPS79613DRBR ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CCT TPS79613DRBRG4 ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CCT TPS79613DRBT ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CCT TPS79613DRBTG4 ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CCT Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 16-Oct-2013 Status (1) Package Type Package Pins Package Drawing Qty TPS79618DCQ ACTIVE SOT-223 DCQ 6 TPS79618DCQG4 ACTIVE SOT-223 DCQ 6 TPS79618DCQR ACTIVE SOT-223 DCQ 6 TPS79618DCQRG4 ACTIVE SOT-223 DCQ 6 TPS79618KTT OBSOLETE DDPAK/ TO-263 KTT 5 TPS79618KTTR ACTIVE DDPAK/ TO-263 KTT 5 TPS79618KTTRG3 ACTIVE DDPAK/ TO-263 KTT TPS79618KTTT ACTIVE DDPAK/ TO-263 TPS79618KTTTG3 ACTIVE TPS79625DCQ 78 Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TBD Call TI Call TI -40 to 125 2500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 PS79618 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PS79618 TBD Call TI Call TI -40 to 125 500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR TPS 79618 5 500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR TPS 79618 KTT 5 50 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 TPS 79618 DDPAK/ TO-263 KTT 5 50 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 TPS 79618 ACTIVE SOT-223 DCQ 6 78 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PS79625 TPS79625DCQG4 ACTIVE SOT-223 DCQ 6 TBD Call TI Call TI -40 to 125 TPS79625DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 PS79625 TPS79625DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PS79625 TPS79625KTT OBSOLETE DDPAK/ TO-263 KTT 5 TBD Call TI Call TI -40 to 125 TPS79625KTTR ACTIVE DDPAK/ TO-263 KTT 5 500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR TPS 79625 TPS79625KTTRG3 ACTIVE DDPAK/ TO-263 KTT 5 500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR TPS 79625 TPS79625KTTT ACTIVE DDPAK/ TO-263 KTT 5 50 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 TPS 79625 TPS79625KTTTG3 ACTIVE DDPAK/ TO-263 KTT 5 50 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 TPS 79625 Addendum-Page 2 PS79618 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 16-Oct-2013 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) TPS79628DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PS79628 TPS79628DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PS79628 TPS79628DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PS79628 TPS79628DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PS79628 TPS79628DRBR ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 AMI TPS79628DRBRG4 ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 AMI TPS79628DRBT ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 AMI TPS79628DRBTG4 ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 AMI TPS79628KTT OBSOLETE DDPAK/ TO-263 KTT 5 TBD Call TI Call TI -40 to 125 TPS79628KTTT ACTIVE DDPAK/ TO-263 KTT 5 50 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 TPS 79628 TPS79628KTTTG3 ACTIVE DDPAK/ TO-263 KTT 5 50 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 TPS 79628 TPS79630DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PS79630 TPS79630DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PS79630 TPS79630DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PS79630 TPS79630DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PS79630 TPS79630KTT OBSOLETE DDPAK/ TO-263 KTT 5 TBD Call TI Call TI -40 to 125 TPS79630KTTR ACTIVE DDPAK/ TO-263 KTT 5 500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR TPS 79630 TPS79630KTTRG3 ACTIVE DDPAK/ TO-263 KTT 5 500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR TPS 79630 Addendum-Page 3 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 16-Oct-2013 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) TPS79630KTTT ACTIVE DDPAK/ TO-263 KTT 5 50 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 TPS 79630 TPS79630KTTTG3 ACTIVE DDPAK/ TO-263 KTT 5 50 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 TPS 79630 TPS79633DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 PS79633 TPS79633DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PS79633 TPS79633DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 PS79633 TPS79633DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PS79633 TPS79633KTT OBSOLETE DDPAK/ TO-263 KTT 5 TBD Call TI Call TI -40 to 125 TPS79633KTTR ACTIVE DDPAK/ TO-263 KTT 5 500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR TPS79633KTTRG3 ACTIVE DDPAK/ TO-263 KTT 5 500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 TPS 79633 TPS79633KTTT ACTIVE DDPAK/ TO-263 KTT 5 50 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 TPS 79633 TPS79633KTTTG3 ACTIVE DDPAK/ TO-263 KTT 5 50 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 TPS 79633 TPS79650DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PS79650 TPS79650DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PS79650 TPS79650DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PS79650 TPS79650DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PS79650 TPS79650DRBR ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 BYZ TPS79650DRBRG4 ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 BYZ TPS79650DRBT ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 BYZ Addendum-Page 4 TPS 79633 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 16-Oct-2013 Status (1) TPS79650DRBTG4 Package Type Package Pins Package Drawing Qty ACTIVE SON DRB 8 250 Eco Plan Lead/Ball Finish (2) Green (RoHS & no Sb/Br) MSL Peak Temp Op Temp (C) Device Marking (3) CU NIPDAU Level-2-260C-1 YEAR (4/5) -40 to 125 BYZ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPS79633 : * Automotive: TPS79633-Q1 Addendum-Page 5 Samples PACKAGE OPTION ADDENDUM www.ti.com 16-Oct-2013 NOTE: Qualified Version Definitions: * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 6 PACKAGE MATERIALS INFORMATION www.ti.com 16-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS79601DCQRG4 SOT-223 DCQ 6 0 330.0 12.4 7.05 7.45 1.88 8.0 12.0 Q3 TPS79601DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS79601DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS79601KTTR DDPAK/ TO-263 KTT 5 500 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2 TPS79601KTTT DDPAK/ TO-263 KTT 5 50 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2 TPS79613DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS79613DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS79618DCQRG4 SOT-223 DCQ 6 2500 330.0 12.4 7.05 7.45 1.88 8.0 12.0 Q3 TPS79618KTTR DDPAK/ TO-263 KTT 5 500 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2 TPS79618KTTT DDPAK/ TO-263 KTT 5 50 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2 TPS79625DCQRG4 SOT-223 DCQ 6 2500 330.0 12.4 7.05 7.45 1.88 8.0 12.0 Q3 TPS79625KTTR DDPAK/ TO-263 KTT 5 500 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2 TPS79625KTTT DDPAK/ TO-263 KTT 5 50 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2 TPS79628DCQR SOT-223 DCQ 6 2500 330.0 12.4 6.8 7.3 1.88 8.0 12.0 Q3 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Oct-2013 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS79628DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS79628DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS79628KTTT DDPAK/ TO-263 KTT 5 50 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2 TPS79630DCQR SOT-223 DCQ 6 2500 330.0 12.4 6.8 7.3 1.88 8.0 12.0 Q3 TPS79630KTTR DDPAK/ TO-263 KTT 5 500 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2 TPS79630KTTT DDPAK/ TO-263 KTT 5 50 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2 TPS79633DCQRG4 SOT-223 DCQ 6 2500 330.0 12.4 7.05 7.45 1.88 8.0 12.0 Q3 TPS79633KTTR DDPAK/ TO-263 KTT 5 500 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2 TPS79633KTTT DDPAK/ TO-263 KTT 5 50 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2 TPS79650DCQR SOT-223 DCQ 6 2500 330.0 12.4 6.8 7.3 1.88 8.0 12.0 Q3 TPS79650DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS79650DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS79601DCQRG4 SOT-223 DCQ 6 0 358.0 335.0 35.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 16-Oct-2013 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS79601DRBR SON DRB 8 3000 367.0 367.0 35.0 TPS79601DRBT SON DRB 8 250 210.0 185.0 35.0 TPS79601KTTR DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0 TPS79601KTTT DDPAK/TO-263 KTT 5 50 367.0 367.0 45.0 TPS79613DRBR SON DRB 8 3000 367.0 367.0 35.0 TPS79613DRBT SON DRB 8 250 210.0 185.0 35.0 TPS79618DCQRG4 SOT-223 DCQ 6 2500 358.0 335.0 35.0 TPS79618KTTR DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0 TPS79618KTTT DDPAK/TO-263 KTT 5 50 367.0 367.0 45.0 TPS79625DCQRG4 SOT-223 DCQ 6 2500 358.0 335.0 35.0 TPS79625KTTR DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0 TPS79625KTTT DDPAK/TO-263 KTT 5 50 367.0 367.0 45.0 TPS79628DCQR SOT-223 DCQ 6 2500 358.0 335.0 35.0 TPS79628DRBR SON DRB 8 3000 367.0 367.0 35.0 TPS79628DRBT SON DRB 8 250 210.0 185.0 35.0 TPS79628KTTT DDPAK/TO-263 KTT 5 50 367.0 367.0 45.0 TPS79630DCQR SOT-223 DCQ 6 2500 358.0 335.0 35.0 TPS79630KTTR DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0 TPS79630KTTT DDPAK/TO-263 KTT 5 50 367.0 367.0 45.0 TPS79633DCQRG4 SOT-223 DCQ 6 2500 358.0 335.0 35.0 TPS79633KTTR DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0 TPS79633KTTT DDPAK/TO-263 KTT 5 50 367.0 367.0 45.0 TPS79650DCQR SOT-223 DCQ 6 2500 358.0 335.0 35.0 TPS79650DRBR SON DRB 8 3000 367.0 367.0 35.0 TPS79650DRBT SON DRB 8 250 210.0 185.0 35.0 Pack Materials-Page 3 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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