VRS1100 VERSA Datasheet Rev 1.1 VERSA 1100: 64KB Program + 64KB Data ISP/IAP FLASH memory 1KB RAM, 40 MHz, 8-Bit MCU Datasheet Rev 1.1 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 1 VRS1100 VERSA Datasheet Rev 1.1 Feature Set * * * * * * * * * * * * * * * * * * * General 8051 pin compatible 64K Program + 64K Data Flash memory In-System / In-Application Flash Programming (ISP/IAP) Program voltage: 5V 1024 Bytes on chip data RAM Four 8-bit I/Os + one 4-bit I/O 4 PWM outputs on P1.3 to P1.7 One Full Duplex UART serial port Three 16-bit Timers/Counters Watch Dog Timer Bit operation instruction 8-bit Unsigned Multiply and Division instructions BCD arithmetic Direct and Indirect Addressing Two Levels of Interrupt Priority and Nested Interrupts Power saving modes Code protection function Low EMI (inhibit ALE) Operating Temperature Range -40C to +85C P2.6/A14 P2.5/A13 #PSEN P2.7/A15 P4.1 ALE P0.7/AD7 #EA FIGURE 2: VRS1100 QFP-44 AND PLCC-44 PIN OUT DIAGRAMS P0.5/AD5 P0.6/AD6 The VRS1100 is an 8-bit microcontroller with 64K Program Flash + 64K Data Flash memory and 1K of RAM. The Flash memory In-System / In-Application Programmable (ISP/IAP). The VRS1100 is based on the architecture of the standard 8051 microcontroller. A boot program can be programmed in the upper section of the Flash memory to allow In-System Programming of the Flash memory through the UART interface. The In-Application Programming feature of the Flash allows the processor to perform sector erase and programming operations on the Flash memory. The VRS1100's features and powerful instruction set make it a versatile and cost effective controller for applications that require large amount of non-volatile data storage or the ability to perform its own Firmware code update. The VRS1100 is supported by parallel programmers available from Goal Semiconductor or other 3rd party commercial programmers. The VRS1100 is available in PLCC-44, QFP-44 and DIP-40 packages in industrial temperature range. P0.4/AD4 Overview 33 FIGURE 1: VRS1100 FUNCTIONAL DIAGRAM 23 22 34 P0.3/AD3 P0.2/AD2 P0.1/AD1 8051 PROCESSOR P2.3/A11 P2.2/A10 P0.0/AD0 VDD ADDRESS/ DATA BUS P2.1/A9 P2.0/A8 VRS1100 QFP-44 P4.2 T2/P1.0 P4.0 VSS T2EX/P1.1 PWM0/P1.2 64k x 8 Program FLASH PORT 0 1024 Bytes of RAM PORT 1 8 UART PORT 2 8 2 INTERRUPT INPUTS PORT 3 8 PORT 4 4 8 XTAL1 XTAL2 PWM1/P1.3 PWM2/P1.4 44 12 11 T0/P3.4 T1/P3.5 #RD/P3.7 #WR/P3.6 P0.3/AD3 #INT1/P3.3 P0.2/AD2 P0.1/AD1 P4.3 TXD/P3.1 #INT0/P3.2 VDD P0.0/AD0 RES RXD/P3.0 T2/P1.0 P4.2 P1.7 T2EX/P1.1 P1.6 PWM3/P1.5 1 PWM2/P1.4 PWM1/P1.3 PWM0/P1.2 64k x 8 Data FLASH P2.4/A12 TIMER 0 TIMER 2 RESET POWER CONTROL WATCHDOG TIMER 6 PWM3/P1.5 40 39 1 TIMER 1 7 P1.6 P1.7 RES PWM 4 P0.7/AD7 #EA VRS1000 PLCC-44 RXD/P3.0 P4.3 TXD/P3.1 P4.1 ALE #INT0/P3.2 #INT1/P3.3 T0/P3.4 #PSEN P2.7/A15 17 29 P2.1/A9 P2.2/A10 P2.3/A11 P2.0/A8 VSS P4.0 XTAL1 #RD/P3.7 XTAL2 #WR/P3.6 P2.6/A14 P2.5/A13 28 18 P2.4/A12 T1/P3.5 P0.4/AD4 P0.5/AD5 P0.6/AD6 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 2 VRS1100 VERSA Datasheet Rev 1.1 Pin Descriptions for QFP-44/PLCC-44 20 26 21 27 22 28 23 29 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VDD 33 32 31 30 29 28 27 26 25 24 23 34 22 35 21 36 20 37 19 VRS1100 QFP-44 38 18 P4.2 T2/P1.0 39 40 16 T2EX/P1.1 PWM0/P1.2 41 15 42 14 PWM1/P1.3 PWM2/P1.4 44 17 43 13 1 2 3 4 5 6 7 8 9 39 34 40 35 41 36 42 37 43 38 39 44 1 40 2 41 3 42 4 43 44 5 6 PWM Channel 0 PWM0 O P1.2 I/O Bit 2 of Port 1 PWM1 O PWM Channel 1 P1.3 I/O Bit 3 of Port 1 PWM2 O PWM Channel 2 P1.4 I/O Bit 4 of Port 1 12 10 11 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8 P4.0 VSS XTAL1 XTAL2 #RD/P3.7 #WR/P3.6 6 5 P0.2/AD2 25 33 P0.3/AD3 19 38 PWM3/P1.5 7 1 44 43 42 41 40 39 P1.6 8 38 P1.7 RES 9 1 0 1 37 RXD/P3.0 P4.3 TXD/P3.1 #INT0/P3.2 #INT1/P3.3 T0/P3.4 T1/P3.5 4 3 2 36 VRS1100 PLCC-44 1 1 2 1 35 34 33 3 1 4 1 32 31 5 1 6 17 30 29 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 #EA P4.1 ALE #PSEN P2.7/A15 P2.6/A14 P2.5/A13 18 19 20 21 22 23 24 25 26 27 28 P2.4/A12 24 32 P0.1/AD1 18 37 VDD P0.0/AD0 20 21 22 23 31 P2.1/A9 P2.2/A10 P2.3/A11 14 15 16 17 36 P2.0/A8 19 30 T2EX/P1.1 13 32 33 34 35 T2/P1.0 P4.2 18 26 27 28 29 VSS P4.0 12 31 XTAL1 17 25 Function Bit 6 of Port 2 Bit 14 of External Memory Address Bit 7 of Port 2 Bit 15 of External Memory Address Program Store Enable Address Latch Enable Bit 1 of Port 4 External Access Bit 7 Of Port 0 Data/Address Bit 7 of External Memory Bit 6 of Port 0 Data/Address Bit 6 of External Memory Bit 5 of Port 0 Data/Address Bit 5 of External Memory Bit 4 of Port 0 Data/Address Bit 4 of External Memory Bit 3 Of Port 0 Data/Address Bit 3 of External Memory Bit 2 of Port 0 Data/Address Bit 2 of External Memory Bit 1 of Port 0 & Data Address Bit 1 of External Memory Bit 0 Of Port 0 & Data Address Bit 0 of External Memory VCC Bit 2 of Port 4 Timer 2 Clock Out Bit 0 of Port 1 Timer 2 Control Bit 1 of Port 1 PWM2/P1.4 11 30 I/O I/O O I/O O O O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I I/O PWM1/P1.3 PWM0/P1.2 16 24 Name P2.6 A14 P2.7 A15 #PSEN ALE P4.1 #EA P0.7 AD7 P0.6 AD6 P0.5 AD5 P0.4 AD4 P0.3 AD3 P0.2 AD2 P0. 1 AD1 P0.0 AD0 VDD P4.2 T2 P1.0 T2EX P1.1 #RD/P3.7 XTAL2 10 PLCC - 44 #WR/P3.6 15 QFP - 44 P2.6/A14 P2.5/A13 9 T0/P3.4 T1/P3.5 14 #PSEN P2.7/A15 8 #INT1/P3.3 13 P4.1 ALE 12 7 P4.3 TXD/P3.1 6 #INT0/P3.2 11 P0.7/AD7 #EA 5 RES RXD/P3.0 8 9 10 Function PWM Channel 3 Bit 5 of Port 1 Bit 6 of Port 1 Bit 7 of Port 1 Reset Receive Data Bit 0 of Port 3 Bit 3 of Port 4 Transmit Data & Bit 1 of Port 3 External Interrupt 0 Bit 2 of Port 3 External Interrupt 1 Bit 3 of Port 3 Timer 0 Bit 4 of Port 3 Timer 1 & 3 Bit 5 of Port Ext. Memory Write Bit 6 of Port 3 Ext. Memory Read Bit 7 of Port 3 Oscillator/Crystal Output Oscillator/Crystal In Ground Bit 0 of Port 4 Bit 0 of Port 2 Bit 8 of External Memory Address Bit 1 of Port 2 Bit 9 of External Memory Address Bit 2 of Port 2 Bit 10 of External Memory Address Bit 3 of Port 2 & Bit 11 of External Memory Address Bit 4 of Port 2 Bit 12 of External Memory Address Bit 5 of Port 2 Bit 13 of External Memory Address P1.7 7 2 3 4 I/O O I/O I/O I/O I I I/O I/O O I/O I I/O I I/O I I/O I I/O O I/O O I/O O I I/O I/O O I/O O I/O O I/O O I/O O I/O O P1.6 1 Name PWM3 P1.5 P1.6 P1.7 RES RXD P3.0 P4.3 TXD P3.1 #INT0 P3.2 #INT1 P3.3 T0 P3.4 T1 P3.5 #WR P3.6 #RD P3.7 XTAL2 XTAL1 VSS P4.0 P2.0 A8 P2.1 A9 P2.2 A10 P2.3 A11 P2.4 A12 P2.5 A13 P0.5/AD5 P0.6/AD6 PLCC - 44 PWM3/P1.5 QFP - 44 P0.4/AD4 TABLE 1: PIN DESCRIPTIONS FOR QFP-44/PLCC-44 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 3 VRS1100 VERSA Datasheet Rev 1.1 VRS1100 DIP40 Pin Descriptions TABLE 2: VRS1100 PIN DESCRIPTIONS FOR DIP40 PACKAGE DIP40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name I/O T2 P1.0 T2EX P1.1 PWM0 P1.2 PWM1 P1.3 PWM2 P1.4 PWM3 P1.5 P1.6 P1.7 RESET RXD P3.0 TXD P3.1 #INT0 P3.2 #INT1 P3.3 T0 P3.4 T1 P3.5 #WR P3.6 #RD P3.7 XTAL2 XTAL1 VSS I I/O I I/O O I/O O I/O O I/O O I/O I/O I/O I I I/O O I/O I I/O I I/O I I/O I I/O O I/O O I/O O I - DIP40 Function Timer 2 Clock Out Bit 0 of Port 1 Timer 2 Control Bit 1 of Port 1 PWM Channel 0 Bit 2 of Port 1 PWM Channel 1 Bit 3 of Port 1 PWM Channel 2 Bit 4 of Port 1 PWM Channel 3 Bit 5 of Port 1 Bit 6 of Port 1 Bit 7 of Port 1 Reset Receive Data Bit 0 of Port 3 Transmit Data & Bit 1 of Port 3 External Interrupt 0 Bit 2 of Port 3 External Interrupt 1 Bit 3 of Port 3 Timer 0 Bit 4 of Port 3 Timer 1 & 3 Bit 5 of Port Ext. Memory Write Bit 6 of Port 3 Ext. Memory Read Bit 7 of Port 3 Oscillator/Crystal Output Oscillator/Crystal In Ground 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 T2 / P1.0 1 40 VDD T2EX / P1.1 2 39 P0.0 / AD0 PWM0 / P1.2 3 38 P0.1 / AD1 39 PWM1 / P1.3 4 37 P0.2 / AD2 PWM2 / P1.4 5 36 40 P0.3 / AD3 PWM3 / P1.5 6 35 P0.4 / AD4 P1.6 7 34 P0.5 / AD5 P1.7 8 33 P0.6 / AD6 RESET 9 32 P0.7 / AD7 31 #EA / VPP VRS1100-DAI40 RXD / P3.0 10 TXD / P3.1 11 30 ALE #INT0 / P3.2 12 29 PSEN #INT1 / P3.3 13 28 P2.7 / A15 T0 / P3.4 14 27 P2.6 / A14 T1 / P3.5 15 26 P2.5 / A13 #WR / P3.6 16 25 P2.4 / A12 #RD / P3.7 17 24 P2.3 / A11 XTAL2 18 23 P2.2 / A10 XTAL1 19 22 P2.1 / A9 VSS 20 21 P2.0 / A8 38 Name I/O P2.0 A8 P2.1 A9 P2.2 A10 P2.3 A11 P2.4 A12 P2.5 A13 P2.6 A14 P2.7 A15 #PSEN ALE #EA / VPP P0.7 I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O O O AD7 I/O I I/O P0.6 I/O AD6 I/O P0.5 I/O AD5 I/O P0.4 I/O AD4 I/O P0.3 I/O AD3 I/O P0.2 I/O AD2 I/O P0. 1 AD1 P0.0 AD0 VDD I/O I/O I/O I/O - Function Bit 0 of Port 2 Bit 8 of External Memory Address Bit 1 of Port 2 Bit 9 of External Memory Address Bit 2 of Port 2 Bit 10 of External Memory Address Bit 3 of Port 2 & Bit 11 of External Memory Address Bit 4 of Port 2 Bit 12 of External Memory Address Bit 5 of Port 2 Bit 13 of External Memory Address Bit 6 of Port 2 Bit 14 of External Memory Address Bit 7 of Port 2 Bit 15 of External Memory Address Program Store Enable Address Latch Enable External Access Flash programming voltage input Bit 7 Of Port 0 Data/Address Bit 7 of External Memory Bit 6 of Port 0 Data/Address Bit 6 of External Memory Bit 5 of Port 0 Data/Address Bit 5 of External Memory Bit 4 of Port 0 Data/Address Bit 4 of External Memory Bit 3 Of Port 0 Data/Address Bit 3 of External Memory Bit 2 of Port 0 Data/Address Bit 2 of External Memory Bit 1 of Port 0 & Data Address Bit 1 of External Memory Bit 0 Of Port 0 & Data Address Bit 0 of External Memory Supply input 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 4 VRS1100 VERSA Datasheet Rev 1.1 Instruction Set The following table describes the instruction set of the VRS1100. The instructions are binary code compatible and perform the same functions as the industry standard 8051 ones. TABLE 3: LEGEND FOR INSTRUCTION SET TABLE Symbol A Rn Direct @Ri rel bit #data #data 16 addr 16 addr 11 Function Accumulator Register R0-R7 Internal register address Internal register pointed to by R0 or R1 (except MOVX) Two's complement offset byte Direct bit address 8-bit constant 16-bit constant 16-bit destination address 11-bit destination address TABLE 4: VRS1100 INSTRUCTION SET Mnemonic Description Arithmetic instructions Add register to A ADD A, Rn Add direct byte to A ADD A, direct Add data memory to A ADD A, @Ri Add immediate to A ADD A, #data Add register to A with carry ADDC A, Rn Add direct byte to A with carry ADDC A, direct Add data memory to A with carry ADDC A, @Ri Add immediate to A with carry ADDC A, #data Subtract register from A with borrow SUBB A, Rn Subtract direct byte from A with borrow SUBB A, direct Subtract data mem from A with borrow SUBB A, @Ri Subtract immediate from A with borrow SUBB A, #data Increment A INC A Increment register INC Rn Increment direct byte INC direct Increment data memory INC @Ri Decrement A DEC A Decrement register DEC Rn Decrement direct byte DEC direct Decrement data memory DEC @Ri Increment data pointer INC DPTR Multiply A by B MUL AB Divide A by B DIV AB Decimal adjust A DA A Logical Instructions AND register to A ANL A, Rn AND direct byte to A ANL A, direct AND data memory to A ANL A, @Ri AND immediate to A ANL A, #data AND A to direct byte ANL direct, A AND immediate data to direct byte ANL direct, #data OR register to A ORL A, Rn OR direct byte to A ORL A, direct OR data memory to A ORL A, @Ri OR immediate to A ORL A, #data OR A to direct byte ORL direct, A OR immediate data to direct byte ORL direct, #data Exclusive-OR register to A XRL A, Rn Exclusive-OR direct byte to A XRL A, direct Exclusive-OR data memory to A XRL A, @Ri Exclusive-OR immediate to A XRL A, #data Exclusive-OR A to direct byte XRL direct, A Exclusive-OR immediate to direct byte XRL direct, #data Clear A CLR A Compliment A CPL A Swap nibbles of A SWAP A Rotate A left RL A Rotate A left through carry RLC A Rotate A right RR A Rotate A right through carry RRC A Size (bytes) Instr. Cycles 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 4 4 1 1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 2 2 3 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 2 1 1 1 1 1 2 1 1 1 1 1 1 1 Mnemonic Description Boolean Instruction Clear Carry bit CLR C Clear bit CLR bit Set Carry bit to 1 SETB C Set bit to 1 SETB bit Complement Carry bit CPL C Complement bit CPL bit Logical AND between Carry and bit ANL C,bit Logical AND between Carry and not bit ANL C,#bit Logical ORL between Carry and bit ORL C,bit Logical ORL between Carry and not bit ORL C,#bit Copy bit value into Carry MOV C,bit Copy Carry value into Bit MOV bit,C Data Transfer Instructions Move register to A MOV A, Rn Move direct byte to A MOV A, direct Move data memory to A MOV A, @Ri Move immediate to A MOV A, #data Move A to register MOV Rn, A Move direct byte to register MOV Rn, direct Move immediate to register MOV Rn, #data Move A to direct byte MOV direct, A Move register to direct byte MOV direct, Rn Move direct byte to direct byte MOV direct, direct Move data memory to direct byte MOV direct, @Ri Move immediate to direct byte MOV direct, #data Move A to data memory MOV @Ri, A Move direct byte to data memory MOV @Ri, direct Move immediate to data memory MOV @Ri, #data Move immediate to data pointer MOV DPTR, #data MOVC A, @A+DPTR Move code byte relative DPTR to A Move code byte relative PC to A MOVC A, @A+PC Move external data (A8) to A MOVX A, @Ri Move external data (A16) to A MOVX A, @DPTR Move A to external data (A8) MOVX @Ri, A Move A to external data (A16) MOVX @DPTR, A Push direct byte onto stack PUSH direct Pop direct byte from stack POP direct Exchange A and register XCH A, Rn Exchange A and direct byte XCH A, direct Exchange A and data memory XCH A, @Ri Exchange A and data memory nibble XCHD A, @Ri Branching Instructions Absolute call to subroutine ACALL addr 11 Long call to subroutine LCALL addr 16 Return from subroutine RET Return from interrupt RETI Absolute jump unconditional AJMP addr 11 Long jump unconditional LJMP addr 16 Short jump (relative address) SJMP rel Jump on carry = 1 JC rel Jump on carry = 0 JNC rel Jump on direct bit = 1 JB bit, rel Jump on direct bit = 0 JNB bit, rel Jump on direct bit = 1 and clear JBC bit, rel Jump indirect relative DPTR JMP @A+DPTR Jump on accumulator = 0 JZ rel Jump on accumulator 1= 0 JNZ rel Compare A, direct JNE relative CJNE A, direct, rel Compare A, immediate JNE relative CJNE A, #d, rel Compare reg, immediate JNE relative CJNE Rn, #d, rel Compare ind, immediate JNE relative CJNE @Ri, #d, rel Decrement register, JNZ relative DJNZ Rn, rel Decrement direct byte, JNZ relative DJNZ direct, rel Miscellaneous Instruction No operation NOP Rn: Any of the register R0 to R7 @Ri: Indirect addressing using Register R0 or R1 #data: immediate Data provided with Instruction #data16: Immediate data included with instruction bit: address at the bit level rel: relative address to Program counter from +127 to -128 Addr11: 11-bit address range Addr16: 16-bit address range #d: Immediate Data supplied with instruction Size (bytes) Instr. Cycles 1 2 1 2 1 2 2 2 2 2 2 2 1 1 1 1 1 1 2 2 2 2 1 2 1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 3 1 1 1 1 1 1 2 2 1 2 1 1 1 1 1 1 1 2 1 1 2 2 2 2 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 2 3 1 1 2 3 2 2 2 3 3 3 1 2 2 3 3 3 3 2 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 5 VRS1100 VERSA Datasheet Rev 1.1 Special Function Registers (SFR) Addresses 80h to FFh of the SFR address space can be accessed in direct addressing mode only. The following table lists the VRS1100 Special Function Registers. TABLE 5: SPECIAL FUNCTION REGISTERS (SFR) SFR Register P0 SP DPL DPH MPAGE DBANK PCON TCON TMOD TL0 TL1 TH0 TH1 P1 WDTKEY SCON SBUF PWME WDTCTRL P2 PWMC PWMD0 PWMD1 PWMD2 PWMD3 IE P3 IP SYSCON T2CON RCAP2L RCAP2H TL2 TH2 PSW P4 ACC B IAPFADHI IAPFADLO IAPFDATA IAPFCTRL SFR Adrs 80h 81h 82h 83h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 90h 97h 98h 99h 9Bh 9Fh A0h A3h A4h A5h A6h A7h A8h B0h B8h BFh C8h CAh CBh CCh CDh D0h D8h E0h F0h F4h F5h F6h F7h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BSE SMOD TF1 GATE1 SM0 WDTE PWMD0.4 PWMD1.4 PWMD2.4 PWMD3.4 EA WDR TF2 - TR1 C/T1 SM1 PWMD0.3 PWMD1.3 PWMD2.3 PWMD3.3 EXF2 - TF0 M1.1 SM2 PWM3E CLEAR PWMD0.2 PWMD1.2 PWMD2.2 PWMD3.2 ET2 PT2 RCLK - TR0 M0.1 REN PWM2E PWMD0.1 PWMD1.1 PWMD2.1 PWMD3.1 ES PS TCLK - BS3 GF1 IE1 GATE0 TB8 PWM1E PWMD0.0 PWMD1.0 PWMD2.0 PWMD3.0 ET1 PT1 DATAFE EXEN2 - BS2 GF0 IT1 C/T0 RB8 PWM0E PS2 NP0.2 NP1.2 NP2.2 NP3.2 EX1 PX1 IAPE TR2 - BS1 PDOWN IE0 M1.0 TI PS1 PDCK1 NP0.1 NP1.1 NP2.1 NP3.1 ET0 PT0 XRAME C/T2 - BS0 IDLE IT0 M0.0 RI PS0 PDCK0 NP0.0 NP1.0 NP2.0 NP3.0 EX0 PX0 ALEI CP/RL2 - CY FA15 FA7 FD7 IAPSTART AC FA14 FA6 FD6 F0 FA13 FA5 FD5 FZONE RS1 FA12 FA4 FD4 RS0 P4.3 FA11 FA3 FD3 OV P4.2 FA10 FA2 FD2 P4.1 FA9 FA1 FD1 P P4.0 FA8 FA0 FD0 IAPFCT1 IAPFCT0 Reset Value 1111 1111b 0000 0111b 0000 0000b 0000 0000b 0000 0000b 0000 0001b 0000 0000b 0000 0010b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 1111 1111b 0000 0000b 0000 0000b 0111 1111b 0000 0000b 0000 0000b 1111 1111b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 1111 1011b 0000 0000b 0000 1010b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0001b ****1111b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 6 VRS1100 VERSA Datasheet Rev 1.1 VRS1100 Program + Data Flash Memory The VRS1100 includes 64K of Program Flash memory that can be used as program memory but can also be used as non-volatile data storage memory using the InApplication Programming feature (IAP). The VRS1100 also includes 64K of Data storage Flash memory that can also be In-Application programmed. parallel programmer software (ISP Page Config) at the moment the device is programmed. FIGURE 4: VERSAMCU-PPR PROGRAM INTERFACE WINDOW ISP Boot Program Memory Zone The upper portion of the VRS1100 Flash program memory can be reserved to hold an ISP boot program. This boot program can be used to perform the Flash memory programming using the serial interface or any other method by making use of the In-Application Programming (IAP) feature of the VRS1100 which allows the processor to load the program or data from an external device or system and program it into the Flash memory (See the VRS1100 IAP feature section) The size of the memory block reserved for the ISP boot program (when activated) is adjustable from 512 Bytes up to 4k Bytes in increments of 512 Bytes, using the ISP Page Config parameter. FA00h ISPCFG=8 ISPCFG=6 ISPCFG=5 ISPCFG=4 ISPCFG=3 If an Erase operation is performed using a parallel programmer, the entire flash memory, including the ISP Boot program memory zone will be erased. FE00h FC00h ISPCFG=7 ISP Program Size = ISP Page Config value x 512Bytes FFFFh ISPCFG=2 ISPCFG=1 FIGURE3: VRS1100-ISP PROGRAM SIZE VS ISP CONFIG. VALUE When programming the ISP boot program into the VRS1100, the "lock bit" option must be activated in order to protect the ISP flash memory zone from being inadvertently erased when the Flash Erase operations are performed under the control of the ISP boot program but also to prevent the VRS1100 flash memory to be read back using a parallel programmer. ISP Boot Program Start Conditions F800h F600h F400h F200h F000h Setting the ISP page configuration to a value other than 0 will make the Processor jump to the base address of the ISP boot code when a hardware reset is performed, provided that the value FFh is present at program address 0000h. 0000h Programming the ISP Boot Program The ISP boot program is programmed into the device using a parallel programmer such as our low cost VERSAMCU-PPR or one of the commercial parallel programmers supporting the VRS1100. The Flash memory reserved for the ISP program is defined in the 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 7 VRS1100 VERSA Datasheet Rev 1.1 An alternate way to force the VRS1100 to jump to the ISP Boot program is to keep pin P2.6 & P2.7 or pin P4.3 alone to a Low logic level during an Hardware Reset. As shown in the picture below: FIGURE 5: VRS1100 ALTERNATE ISP BOOT PROGRAM ACCESS 10ms 10ms VRS1100 ISPV2 Firmware boot program For your convenience, Goal Semiconductor Inc. has developed an ISP boot program for the VRS1000 that also works for the VRS1100. This boot program is called the ISPV2 Firmware and resides in the upper 3.5K of the VRS1100 Program Flash memory, from F200h to FFFFh. The ISPV2 Firmware allows programming of the VRS1100 on the final application PCB using the device's UART interface. Goal Semiconductor Inc. offers the possibility to order VRS1100 devices with the ISPV2 firmware already programmed into their Flash memory. The ordering information section shows the corresponding part numbers. P2.7 P2.6 The hardware interface to program the VRS1100 Flash Program memory using the ISPV2 Firmware is very simple. An example of interface is shown below. Other configurations are also possible. RES FIGURE 6: VRS1100 INTERFACE FOR IN-SYSTEM PROGRAMMING VRS1100 To PC 51k 10ms RS232 interf. 10ms RS232 Transceiver OR... P4.3 PNP (with ISPV2 Firmware) TXD RXD Creset 150k RES RES It is also possible to access the ISP boot program by using the LJMP instruction. When the ISP page configuration is set to 0 at the moment the device is programmed using a parallel programmer, the ISP boot feature will be disabled. Rreset A WindowsTM's based programming software called the "GoalTender VRS1000-ISPV2 In-System Serial Programmer" which provides an easy to use interface to communicate with the ISPV2 firmware is available free on our web site. You can also program the ISPV2 Firmware into the VRS1100 Program flash memory using a parallel programmer. The ISPV2 Firmware source code is included with the GoalTender VRS1000-ISPV2 software. For more information regarding features and uses of the ISPV2 Firmware, please consult the "VRS1000 ISPV2 Firmware User Guide.pdf" available on Goal Semiconductor Inc.'s Web site. 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 8 VRS1100 VERSA Datasheet Rev 1.1 Note: The current ISPV2 Firmware and GoalTender software does not allow VRS1100 Data Flash memory programming. Future versions of both the ISP Firmware and GoalTender software will provide support for VRS1100 Data Flash memory programming. VRS1100 IAP feature The VRS1100 IAP feature refers to the ability for the processor to self-program its Program and Data Flash memory from within the user program. Five SFR registers serve to control the IAP operation. The description of these registers is given below. Setting to 1 the DFLASHE bit of the SYSCON register is used to activate the 64K of on chip Data Flash memory which is disabled by default. The IAPE bit is used to Activate the IAP function. When set to 1, the XRAME bit allows the user to enable the on-chip expanded 768 Bytes of RAM. Bit 0 of this register is the ALE output inhibit bit. Setting this bit to 1 will inhibit the Fosc/6Hz clock signal output to the ALE pin. IAP Flash Address and Data Registers The IAPFADHI and IAPADLO registers are used to specify the address at which the IAP function will be performed. TABLE 7:IAP FLASH ADDRESS HIGH (IAPFADHI) - SFR F4H System Control Register 7 The System Control register controls the activation of the Data Flash, the Expanded RAM and serves to monitor the Watch Dog Timer Status. TABLE 6: SYSTEM CONTROL REGISTER (SYSCON) - SFR BFH 7 WDR 6 5 Unused 4 3 2 1 0 DFLASHE IAPE XRAME ALEI 6 5 4 3 2 IAPFADHI[15:8] 1 0 1 0 TABLE 8:IAP FLASH ADDRESS LOW (IAPFADLO) - SFR F5H 7 6 5 4 3 2 IAPFADLO[15:8] The IAPFDATA SFR register contains the Data byte required to perform the IAP function. TABLE 9:IAP FLASH DATA REGISTER (IAPFDATA) - SFR F6H Bit 7 Mnemonic WDR 6 5 4 3 Unused Unused Unused DFLASHE 2 IAPE 1 0 XRAME ALEI Description This is the Watch Dog Timer reset bit. It will be set to 1 when the reset signal generated by WDT overflows. Data Flash memory Enable 0: Data Flash is Disabled 1: Data Flash is Enabled IAP function enable bit 0: IAP is Disabled 1: ISP is Enabled 768 byte on-chip enable bit ALE output inhibit bit, which is used to reduce EMI. 0: ALE active 1: ALE activity is inhibited 7 6 5 4 3 2 IAPFDATA[7:0] 1 0 The WDR bit of the SYSCON register indicates if the system has been reset due to the overflow of the Watch Dog Timer. For this reason users should check the WDR bit whenever an unpredicted reset occurs. 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 9 VRS1100 VERSA Datasheet Rev 1.1 activated. Care should be taken when performing Flash Erase under final application program control. IAP Flash Control Register The VRS1100 IAP functions operation is controlled by the IAP Flash Control register, IAPFCTRL. TABLE 10:IAP FLASH CONTROL REGISTER (IAPFCTRL) - SFR F7H 7 6 5 4 3 2 IAPFCTRL[15:8] 1 0 Bit 7 6 Mnemonic IAPSTART Unused 5 FZONE 4 3 2 1 0 Unused Unused Unused Description IAP Selected operation Start sequence Flash Zone Select for IAP Flash operations: 0: Flash Program Zone 1: Flash Data Zone - IAPFCT[1:0] Flash Memory IAP Function (see below) The VRS1100 IAP operations can be performed on either the 64K Flash Program memory zone or the 64K Data Flash memory Zone. The FZONE bit selects the area on which the IAP operations will be performed. In fact, the FZONE bit acts as the seventeenth bit of the 128K flash address. It is important to note that for security reasons the IAPSTART bit of the IAPFCTRL register is configured as read only by default. In order to access the IAPSTART bit and to write a 1 into it the following operation sequence must be performed first: MOV MOV MOV IAPFDATA,#55h IAPFDATA,#AAh IAPFDATA,#55h Then the IAPSTART bit can be set to 1. Once the start bit is set to 1, the IAP sub-system will read the content of the IAP Flash Address and Data register and hold the VRS1100 program counter to its current value until the IAP operation is completed. When the IAP operation is complete, the IAPSTART bit is cleared and the program continues its execution. IAP Byte Program in the VRS1100 Program Flash FZONE = 0: IAP functions target Program Flash FZONE = 1: IAP functions target Data Flash The IAP byte program function is used to program a byte into the specified Program memory location under the control of the IAP feature. The following program example shows how to do it: Setting the IAPSTART bit to 1 starts the execution of the IAP command specified by the IAPFCT[1:0] bit of the IAP Flash Control register. IAP_PROG: MOV MOV MOV If the IAPSTART bit equals 0, no IAP operations will be performed. The IAP sub-system handles four different functions. The IAP function to perform is defined by the IAPFCT bits value as shown below: TABLE 11:IAP FUNCTIONS IAPFCT[1:0] Bits value 00 01 10 11 IAP Function Flash Byte Program Flash Erase Protect Flash Page Erase Flash Erase The Flash Erase function when activated will erase the entire VRS1100 Flash memory except the ISP boot program if the ISP config bit (lock) bit have been IAPFDATA,#55H IAPFDATA,#0AAH IAPFDATA,#55H ;Sequence to Enable Writing ; the IAPSTART bit MOV SYSCON,#04H ;ENABLE IAP FUNCTION MOV IAPFADHI, FADRSH ;Set MSB of address to program MOV IAPFADLO,FADRSL ;Set LSB of address to program MOV IAPFDATA,FDATA ;Set Data to Program MOV IAPFCTRL,#80H ;Set the IAP Start bit + Byte Program ;**The program Counter will stop until the IAP function is completed IAP Byte Program in the VRS1100 Data Flash The IAP byte program function can also be used to program a byte into the specified Data Flash memory location under the control of the IAP feature. The following program example shows how to do it: IAP_PROG: MOV MOV MOV MOV IAPFDATA,#55H IAPFDATA,#0AAH IAPFDATA,#55H ;Sequence to Enable Writing ; the IAPSTART bit SYSCON,#0CH ;ENABLE IAP FUNCTION + Enable ;Data Flash MOV IAPFADHI, FADRSH ;Set MSB of address to program MOV IAPFADLO,FADRSL ;Set LSB of address to program MOV IAPFDATA,FDATA ;Set Data to Program MOV IAPFCTRL,#A0H ;Set the IAP Start bit + FZONE bit ;**The program Counter will stop until the IAP function is completed 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 10 VRS1100 VERSA Datasheet Rev 1.1 IAP Chip Protect Function IAP Page Erase Function By using the IAP feature, it is possible to perform Page erase of the VRS1100 Program or Data Flash memory with the exception of the memory area occupied by the ISP boot program. Each page is 512 Bytes in size. To perform a given flash page erase, the page address is specified by the XY (hex) value written into the IAPFADHI register (The value 00h must be written into the IAPFADLO registers) The chip protect function when executed makes the chip Flash memory content read as 00h when an attempt is made to read it. ISP/AIP operation Durations The following table shows the time required to perform the ISP/IAP operations for an oscillator clock of 40MHz. If the "Y" portion of the IAPFADHI register represents an even number, the page that will be erased corresponds to the range XY00h to X(Y+1)FFh If the "Y" portion of the IAPFADHI register represents an odd number, the page that will be erased corresponds to the range X(Y-1)00h to XYFFh The following program example shows how to erase the page corresponding to the address B000h-CFFFh in Program Memory zone: ;** Erase Flash Program page located at address B000h to CFFFh. PageErase: MOV IAPFDATA,#55H ;Sequence to Enable Writing MOV IAPFDATA,#0AAH ; the IAPSTART bit MOV IAPFDATA,#55H MOV MOV MOV MOV SYSCON,#04H IAPFADHI, #0B0h IAPFADLO,#00h IAPFCTRL,#82H ;Enable IAP ;Set MSB of Page address to erase ;Set LSB of address = 00 ;Set the IAP Start Bit The following example shows how to erase the same page in the Data Flash memory zone: ;** Erase Flash Data page located at address B000h to CFFFh. PageErase: MOV IAPFDATA,#55H ;Sequence to Enable Writing MOV IAPFDATA,#0AAH ; the IAPSTART bit MOV IAPFDATA,#55H MOV MOV MOV MOV SYSCON,#0CH IAPFADHI, #0B0h IAPFADLO,#00h IAPFCTRL,#A2H ;Enable IAP + Data Flash ;Set MSB of Page address to erase ;Set LSB of address = 00 ;Set The IAP Start bit + FZONE bit IAP Chip Erase Function The IAP chip erase function will erase the entire flash memory content with the exception of the ISP boot program area. Running this function will also automatically unprotect the flash memory. Operation Max Duration (Fosc = 40MHz) 30us 10ms 3sec 400us Byte Program Page Erase Chip Erase Chip Protect All ISP/IAP operations require the supply voltage to be 5V to execute properly. Program Status Word Register The register below contains the program state flags. These flags may be read or written to by the user. TABLE 12: PROGRAM STATUS WORD REGISTER (PSW) - SFR DOH 7 CY Bit 7 6 5 4 3 2 1 0 RS1 0 0 1 1 6 AC 5 F0 Mnemonic CY AC F0 RS1 RS0 OV P RS0 0 1 0 1 4 RS1 3 RS0 2 OV 1 - 0 P Description Carry Bit Auxiliary Carry Bit from bit 3 to 4. User definer flag R0-R7 Registers bank select bit 0 R0-R7 Registers bank select bit 1 Overflow flag Parity flag Active Bank 0 1 2 3 Address 00h-07h 08h-0Fh 10h-17h 18-1Fh 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 11 VRS1100 VERSA Datasheet Rev 1.1 Data Pointer The VRS1100 has one 16-bit data pointer. The DPTR is accessed through two SFR addresses: DPL located at address 82h and DPH located at address 83h. Stack Pointer The Stack Pointer is a register located at address 81h of the SFR register area whose value corresponds to the address of the last item that was put on the processor stack. Each time new data is put on the Stack Pointer, the value of the Stack Pointer is incremented. By default, the Stack Pointer value is 07h, but it is possible to out the processor stack pointer anywhere in the 00h to FFh range of RAM memory. Each time a function call is performed or an interrupt is serviced, the 16-bit return address (two bytes) is stored on the stack. It is also possible to put data manually on the Stack by using the PUSH and POP functions. Data Memory The VRS1100 has 1K of on-chip RAM: 256 Bytes are configured like the internal memory structure of a standard 8052, while the remaining 768 Bytes can be accessed using external memory addressing (MOVX). As mentioned earlier, it also includes a large block of 64K of Data Flash that is mapped on the processor's external memory bus for Read access. FIGURE 7: VRS1100 DATA MEMORY STRUCTURE FFFFh IF DFLASHE = 1 Data Flash Mapped as External Memory Use MOVX to Read 02FFh 02FFh FFh 80h 7Fh 00h FFh Upper 128 bytes (Can only be accessed in indirect addressing mode) Lower 128 bytes (Can be accessed in indirect and direct addressing mode) SFR (Can only be accessed in direct addressing mode) 80h IF XRAME = 1 and DFLASHE = 1 Expanded 768 bytes (Can by accessed by direct external addressing mode, using the MOVX instruction) Data Flash Mapped as External Memory Use MOVX to Read (XRAME=1) 0000h The DFLASHE and XRAME bits of the SYSCON register defines which area the MOVX instruction will target: DFLASHE XRAME 0 0 1 1 0 1 0 1 MOVX <= 2FFh Ext. Memory Int. RAM Int. Data Flash Int. RAM MOVX > 2FFh Ext. Memory Ext. Memory Int. Data Flash Int. Data Flash Lower 128 bytes (00h to 7Fh, Bank 0 & Bank 1) The lower 128 bytes of data memory (from 00h to 7Fh) can be summarized in the following points: o Address range 00h to 7Fh can be accessed in direct and indirect addressing modes. o Address range 00h to 1Fh includes R0-R7 registers area. o Address range 20h to 2Fh is bit addressable. o Address range 30h to 7Fh is not bit addressable and can be used as generalpurpose storage. Upper 128 bytes (80h to FFh, Bank 2 & Bank 3) The upper 128 bytes of the data memory ranging from 80h to FFh can be accessed using indirect addressing or by using the bank mapping in direct addressing mode. Expanded RAM Access Using the MOVX @DPTR Instruction (0000-02FF, Bank4-Bank15) The 768 Bytes of the expanded RAM data memory occupy addresses 0000h to 02FFh. It can be accessed using external direct addressing (i.e. using the MOVX instruction) or by using bank mapping direct addressing. Note that in the case of indirect addressing using the MOVX @DPTR instruction, if the address is larger than 02FFh and the Data Flash is disabled (DFLASHE=0), the VRS1100 will generate the external memory control signal automatically. The MPAGE register (extra Read Data Pointer) 0000h By default after reset, the expanded RAM area and the Data Flash areas are disabled. They can be enabled by setting the XRAME and the DFLASHE bit respectively of the SYSCON register which is located at address BFh in the SFR. The VRS1100 includes a second data pointer called MPAGE, which is dedicated for Data Flash and external RAM read access using the MOVX @Ri (I=0,1) instruction. The MPAGE register serves to define the high byte of the Address and the content of the Ri register defines the content of the Low Byte of the Address. The operation of the MPAGE register is 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 12 VRS1100 VERSA Datasheet Rev 1.1 similar to the MOVX @DPTR that is available for the "external" RAM access, but it is limited to read function. The default setting of the MPAGE register is 00h The windowed access to all the 1K on-chip RAM in the range of 40h-7Fh is described in the following table. TABLE 15: BANK MAPPING DIRECT ADDRESSING MODE BS3 BS2 BS1 BSO 040h~07fh mapping address 0 0 0 0 000h-03Fh 0 0 0 1 040h-07Fh 0 0 1 0 080h-0BFh Data Bank Control Register 0 0 1 1 0C0h-0FFh The DBANK register allows the user to enable the Data Bank Select function and map the entire content of the RAM memory in the range of 40h to 7Fh for applications that would require direct addressing of the expanded RAM content. 0 1 0 0 0000h-003Fh 0 1 0 1 0040h-007Fh 0 1 1 0 0080h-00BFh 0 1 1 1 00C0h-00FFh The Data Bank Select function is activated by setting to 1 the Data Bank Select enable bit (BSE) of the DBANK register. Setting this bit to zero disables this function. The four least significant bits of this register controls the mapping of the entire 1K Byte on-chip RAM space into the 040h-07Fh range. 1 0 0 0 0100h-013Fh 1 0 0 1 0140h-017Fh 1 0 1 0 0180h-01BFh 1 0 1 1 01C0h-01FFh 1 1 0 0 0200h-023Fh 1 1 0 1 0240h-027Fh 1 1 1 0 0280h-02BFh 1 1 1 1 02C0h-02FFh TABLE 13: MPAGE REGISTER (MPAGE) - SFR 85H 7 6 5 4 3 MPAGE[7:0] 2 1 0 TABLE 14: DATA BANK CONTROL REGISTER (DBANK) - SFR 86H 7 BSE Bit 7 6 5 4 3 2 1 0 6 5 Unused Mnemonic BSE Unused Unused Unused BS3 BS2 BS1 BS0 4 3 BS3 2 BS2 1 BS1 0 BS0 Description Data Bank Select Enable Bit BSE=1, Data Bank Select enabled BSE=0, Data Bank Select disabled Allows the mapping of the 1K RAM into the 040h - 07Fh RAM space Note Lower 128 byte RAM Lower 128 byte RAM Upper 128 byte RAM Upper 128 byte RAM On-chip expanded 768 byte RAM On-chip expanded 768 byte RAM On-chip expanded 768 byte RAM On-chip expanded 768 byte RAM On-chip expanded 768 byte RAM On-chip expanded 768 byte RAM On-chip expanded 768 byte RAM On-chip expanded 768 byte RAM On-chip expanded 768 byte RAM On-chip expanded 768 byte RAM On-chip expanded 768 byte RAM On-chip expanded 768 byte RAM Example: User writes #55h to address 203h: MOV DBANK, #8CH MOV A, #55H ;Set bank mapping 40h-07Fh 0200h-023Fh ;Store #55H to A MOV 43H, A ;Write #55H to 0203h ;address 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com to 13 VRS1100 VERSA Datasheet Rev 1.1 Power Control Register The VRS1100 provides two power saving modes: Idle and Power Down, which are controlled by the PDOWN and IDLE bits of the PCON register at address 87h. TABLE 16: POWER CONTROL REGISTER (PCON) - SFR 87H 7 Bit 7 6 5 4 Unused Mnemonic SMOD 3 2 1 RAMS1 0 RAMS0 Description 1: Double the baud rate of the serial port frequency that was generated by Timer 1. 0: Normal serial port baud rate generated by Timer 1. 6 5 4 3 2 1 0 GF1 GF0 PDOWN IDLE General Purpose Flag General Purpose Flag Power down mode control bit Idle mode control bit In Idle mode, the processor's clock is stopped but the peripherals remains active. The content of the RAM, I/O state and SFR registers are maintained. Timer operation is maintained, as well as the external interrupts and UARTs. The Idle mode is useful for applications in which stopping the processor to save power is required. The processor will be woken up when an external event, triggering an interrupt, occurs. However, because only the processor clock is stopped in Idle Mode, the power saving is likely to be in the order of 65% compared to normal operating mode In Power Down mode, the oscillator of the VRS1100 is stopped. This means that the clock to all peripherals is stopped. The content of the RAM and the SFR registers, however, is maintained. The only way to exit of the Power Down mode is by a hardware Reset. The Watch Dog Timer is stopped in Power Down. When the VRS1100 is in Power Down, its current consumption drops to about 50uA. The SMOD bit of the PCON register controls the oscillator divisor applied to the Timer 1 when used as a baud rate generator for the UART. Setting this bit to 1 has an effect of doubling the UART's baud rate generator's frequency. 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 14 VRS1100 VERSA Datasheet Rev 1.1 Input/Output Ports The VRS1100 has 36 bi-directional lines grouped in four 8-bit I/O ports and one 4-bit I/O port. These I/Os can be individually configured as input or output. Except for the P0 I/Os, which are of the open drain type, each I/O is made of a transistor connected to ground and a dynamic pull-up resistor made of a combination of transistors. Writing a 0 in a given I/O port bit register will activate the transistor connected to ground, this will bring the I/O to a LOW level. Writing a 1 into a given I/O port bit register de-activates the transistor between the pin and ground. In this case an internal weak pull-up resistor will bring the pin to a HIGH level (except for Port 0 which is open-drain). To use a given I/O as an input, one must write a 1 into its associated port register bit. By default, upon reset all the I/Os are configured as input. The VRS1100 I/O ports are not designed to source current. Structure of the P1, P2, P3 and P4 Ports The following figure gives a general idea of the structure of one of the lines of the P1, P2 and P3 ports. For these ports, the output stage is composed of a transistor (X1) and transistors configured as pull-ups. It is important to note that the figure below does not show the intermediary logic that connects the output of the register and the output stage together because this logic varies with the auxiliary function of each port. Each line may be used independently as a logical input or output. When used as an input, as mentioned earlier, the corresponding bit register must be high. This would correspond to #Q=0 in Figure 2. The transistor would be off (open-circuited) and current would flow from the VCC to the pin, generating a logical high at the output. Also, note that if an external device with a logical low value is connected to the pin, the current will flow out of the pin. The presence of the pull-up resistance even when the I/O's are configured as input means that a small current is likely to flow from the VRS1100 I/O's pull-up resistors to the driving circuit when the inputs are driven Low. For this reason, the VRS1100 I/O ports P1, P2, P3 and P4 are called "quasi bi-directional". Structure of Port 0 The internal structure of P0 is shown in the next figure. The auxiliary function of this port requires a particular logic. As opposed to the other ports, P0 is truly bidirectional. In other words, when used as an input, it is considered to be in a floating logical state (high impedance state). This arises from the absence of the internal pull-up resistance. The pull-up resistance is actually replaced by a transistor that is only used when the port functions to access external memory/data bus (EA=0). When used as an I/O port, P0 acts as an open drain port and the use of an external pull-up resistor is likely to be required for most applications. FIGURE 9: PORT P0'S PARTICULAR STRUCTURE FIGURE 8: GENERAL STRUCTURE OF THE OUTPUT STAGE OF P1, P2, P3 AND P4 Address A0/A7 Read Register Read Register Control Vcc Vcc Pull-up Network Internal Bus Internal Bus Q Write to Register D Flip-Flop Write to Register Q Q IC Pin D Flip-Flop IC Pin Q X1 X1 Read Pin Read Pin 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 15 VRS1100 VERSA Datasheet Rev 1.1 When P0 is used as an external memory bus input (for a MOVX instruction, for example), the outputs of the register are automatically forced to 1. Port P0 and P2 as Address and Data Bus The output stage may receive data from two sources The P0 register located at address 80h controls the P0 individual pin direction when used as I/O. The P0 register is bit addressable. o The outputs of register P0 or the bus address itself multiplexed with the data bus for P0. o The outputs of the P2 register or the high part (A8/A15) of the bus address for the P2 port. TABLE 17: PORT 0 REGISTER (P0) - SFR 80H 7 P0.7 6 P0.6 Bit 7 6 5 4 3 2 1 0 5 P0.5 Mnemonic P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 4 P0.4 3 P0.3 2 P0.2 1 P0.1 0 P0.0 Description For each bit of the P0 register correspond to an I/O line: 0: Output transistor pull the line to 0V 1: The output transistor is blocked so the pull-up brings the I/O to 5V. FIGURE 10: P2 PORT STRUCTURE Read Register Vcc Address Pull-up Network Q Internal Bus IC Pin D Flip-Flop Write to Register X1 Q Control Port 2 Read Pin The Port P2 is very similar to Port 1 and Port 3 with the difference that the alternate function of P2 is to act as A8-A15 lines of the address bus when the EA line of the VRS1100 is held low at reset time or when MOVX instruction is executed. When the ports are used as an address or data bus, the special function registers P0 and P2 are disconnected from the output stage. The 8 bits of the P0 register are forced to 1 and the content of the P2 register remains constant. Like the P1, P2 and P3 registers, the P2 register is bit addressable. Port 1 TABLE 18: PORT 2 REGISTER (P2) - SFR A0H 7 P2.7 Bit 7 6 5 4 3 2 1 0 6 P2.6 5 P2.5 Mnemonic P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 4 P2.4 3 P2.3 2 P2.2 1 P2.1 0 P2.0 Description For each bit of the P2 register correspond to an I/O line: 0: Output transistor pull the line to 0V 1: The output transistor is blocked so the pull-up brings the I/O to 5V. The P1 register controls the direction of the Port 1 I/O pins. A 1 to the corresponding bit makes the port act as an output presenting a logic 1 to the corresponding I/O pin or renders it possible to use the I/O pin as an input. Writing a 0 activates the output "pull-down" transistor which will force the corresponding I/O line going to a logic Low. TABLE 19: PORT 1 REGISTER (P2) - SFR 90H 7 P1.7 Bit 7 6 5 4 3 2 1 0 6 P1.6 5 P1.5 Mnemonic P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 4 P1.4 3 P1.3 2 P1.2 1 P1.1 0 P1.0 Description For each bit of the P1 register correspond to an I/O line: 0: Output transistor pull the line to 0V 1: The output transistor is blocked so the pull-up bring the I/O to 5V. 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 16 VRS1100 VERSA Datasheet Rev 1.1 FIGURE 11: P3 PORT STRUCTURE Auxiliary Port 1 Functions Auxiliary Function: Output Read Register Vcc The Port 1 I/O pins are shared with the PWM outputs, Timer 2 EXT and T2 inputs as shown below: Pin P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 Mnemonic T2 T2EX Function Timer 2 counter input Timer2 Auxiliary input PWM0 PWM1 PWM2 PWM1 output PWM2 output PWM3 PWM3 output PWM4 PWM4 output D Flip-Flop Write to Register PWM0 output Q Read Pin Auxiliary Function: Input The following table describes the auxiliary function of the Port 3 I/O pins. TABLE 21: P3 AUXILIARY FUNCTION TABLE The Port 3 structure is similar to the structure of the Port 1. The P3 register controls the P3 pins operation. TABLE 20: PORT 3 REGISTER (P3) - SFR B0H Bit 7 6 5 4 3 2 1 0 Q Internal Bus Port 3 7 P3.7 IC Pin X1 6 P3.6 5 P3.5 Mnemonic P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 4 P3.4 3 P3.3 2 P3.2 1 P3.1 0 P3.0 Description For each bit of the P3 register correspond to an I/O line: 0: Output transistor pull the line to 0V 1: The output transistor is blocked so the pull-up brings the I/O to 5V. To configure P3 pins as input or use alternate P3 function the corresponding bit must be set to 1. Pin P3.0 Mnemonic RXD P3.1 TXD P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 INT0 INT1 T0 T1 WR RD Function Serial Port: Receive data in asynchronous mode. Input and output data in synchronous mode. Serial Port: Transmit data in asynchronous mode. Output clock value in synchronous mode. External Interrupt 0 Timer 0 Control Input External Interrupt 1 Timer 1 Control Input Timer 0 Counter Input Timer 1 Counter Input Write signal for external memory Read signal for external memory Auxiliary P3 Port Functions The Port 3 I/O pins are shared with the UART interface, INT0 and INT1 interrupts, Timer 0 and Timer 1 inputs and finally the #WR and #RD lines when external memory access is performed. To maintain the correct functionality of the line in auxiliary function mode, it is necessary that the Q output of register is held stable at 1. Conversely, if the pull-down transistor continues conducting, it will set the IC pin at a voltage of approximately 0. 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 17 VRS1100 VERSA Datasheet Rev 1.1 Port 4 Port 4 has four pins and its port address is located at 0D8H. TABLE 22: PORT 4 (P4) - SFR D8H 7 Bit 7 6 5 4 3 2 1 0 6 5 Unused Mnemonic Unused Unused Unused Unused P4.3 P4.2 P4.1 P4.0 4 3 P4.3 2 P4.2 1 P4.1 0 P4.0 Description Used to output the setting to pins P4.3, P4.2, P4.1, P4.0 respectively. TABLE 23: LIST OF INSTRUCTIONS THAT READ AND MODIFY THE PORT USING REGISTER VALUES Instruction ANL ORL XRL JBC CPL INC DEC DJNZ MOV P.,C CLR P.x SETB P.x Function Logical AND ex: ANL P0, A Logical OR ex: ORL P2, #01110000B Exclusive OR ex: XRL P1, A Jump if the bit of the port is set to 0 Complement one bit of the port Increment the port register by 1 Decrement the port register by 1 Decrement by 1 and jump if the result is not equal to 0 Copy the held bit C to the port Set the port bit to 0 Set the port bit to 1 Software Particularities Concerning the Ports Port Operation Timing Some instructions allow the user to read the logic state of the output pin, while others allow the user to read the content of the associated port register. These instructions are called read-modify-write instructions. A list of these instructions may be found in the table below. Writing to a Port (Output) Upon execution of these instructions, the content of the port register (at least 1 bit) is modified. The other read instructions take the present state of the input into account. For example, the instruction ANL P3,#01h obtains the value in the P3 register; performs the desired logic operation with the constant 01h; and recopies the result into the P3 register. When users want to take the present state of the inputs into account, they must first read these states and perform an AND operation between the reading and the constant. Reading a Port (Input) When an operation induces a modification of the content in a port register, the new value is placed at the output of the D flip-flop during the last machine cycle that the instruction needed to execute. In order to get sampled, the signal duration present on the I/O inputs must have a duration longer than Fosc/12. MOV A, P3; State of the inputs in the accumulator ANL A, #01; AND operation between P3 and 01h When the port is used as an output, the register contains information on the state of the output pins. Measuring the state of an output directly on the pin is inaccurate because the electrical level depends mostly on the type of charge that is applied to it. The functions shown below take the value of the register rather than that of the pin. 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 18 VRS1100 VERSA Datasheet Rev 1.1 I/O Ports Driving Capability The maximum allowable continuous current that the device can sink on I/O port is defined by the following Maximum sink current on one given I/O Maximum total sink current for P0 Maximum total sink current for P1, 2, 3 Maximum total sink current on all I/O 10mA 26mA 15mA 71mA It is not recommended to exceed the sink current expressed in the above table. Doing so is likely to make the low-level output voltage exceed the device's specification and it is likely to affect the device's reliability. The VRS1100 I/O ports are not designed to source current. VRS1100 Timers The VRS1100 includes three 16-bit timers: Timer 0, Timer 1 and Timer 2. The Timers can operate in two specific modes: o Event counting mode o Timer mode When operating in event counting mode, the counter is incremented each time an external event, such as a transition in the logical state of the Timer input (T0, T1, T2 input), is detected. When operating in Timer mode, the counter is incremented by the microcontroller's system clock (Fosc/12) or by a divided version of it. Timer 0 and Timer 1 Timers 0 and 1 have four Modes of operation. These Modes allow the user to change the size of the counting register or to authorize an automatic reload when provided with a specific value. Timer 1 can also be used as a baud rate generator to generate communication frequencies for the serial interface. Timer 1 and Timer 0 are configured by the TMOD and TCON registers. TABLE 24: TIMER MODE CONTROL REGISTER (TMOD) - SFR 89H 7 6 5 4 3 2 1 0 GATE1 C/T1 T1M1 T1M0 GATE0 C/T0 T0M1 T0M0 Bit 7 Mnemonic GATE1 6 C/T1 5 4 3 T1M1 T1M0 GATE0 2 C/T0 1 0 T0M1 T0M0 Description 1: Enables external gate control (pin INT1 for Counter 1). When INT1 is high, and TRx bit is set (see TCON register), a counter is incremented every falling edge on the T1IN input pin. Selects timer or counter operation (Timer 1). 1 = A counter operation is performed 0 = The corresponding register will function as a timer. Selects the operating mode of Timer/Counter 1 If set, enables external gate control (pin INT0 for Counter 0). When INT0 is high, and TRx bit is set (see TCON register), a counter is incremented every falling edge on the T0IN input pin. Selects timer or counter operation (Timer 0). 1 = A counter operation is performed 0 = The corresponding register will function as a timer. Selects the operating mode of Timer/Counter 0. The table below summarizes the four modes of operation of Timers 0 and 1. The timer operating mode is selected by the bits T1M1/T1M0 and T0M1/T0M0 of the TMOD register. TABLE 25: TIMER/COUNTER MODE DESCRIPTION SUMMARY M1 M0 Mode Function 0 0 1 0 1 0 Mode 0 Mode 1 Mode 2 1 1 Mode 3 13-bit Counter 16-bit Counter 8-bit auto-reload Counter/Timer. The reload value is kept in TH0 or TH1, while TL0 or TL1 is incremented every machine cycle. When TLx overflows, the value of THx is copied to TLx. If Timer 1 M1 and M0 bits are set to 1, Timer 1 stops. 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 19 VRS1100 VERSA Datasheet Rev 1.1 Timer 0, Timer 1 Counter / Timer Functions TABLE 26: TIMER 0 AND 1 CONTROL REGISTER (TCON) -SFR 88H Timing Function 7 6 5 4 3 2 1 0 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 When Timer 1 or Timer 0 is configured to operate as a Timer, its value is automatically incremented at every machine cycle. Once the Timer value rolls over, a flag is raised and the counter acquires a value of zero. The overflow flags (TF0 and TF1) are located in the TCON register. Bit 7 Mnemonic TF1 Description Timer 1 Overflow Flag. Set by hardware on Timer/Counter overflow. Cleared by hardware on Timer/Counter overflow. Cleared by hardware when processor vectors to interrupt routine. 6 TR1 The TR0 and TR1 bit of the TCON register gates the corresponding timer operation. In order for the Timer to run, the corresponding TRx bit must be set to 1. 5 TF0 4 TR0 3 IE1 2 IT1 1 IE0 0 IT0 Timer 1 Run Control Bit. Set/cleared by software to turn Timer/Counter on or off. Timer 0 Overflow Flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when processor vectors to interrupt routine. Timer 0 Run Control Bit. Set/cleared by software to turn Timer/Counter on or off. Interrupt Edge Flag. Set by hardware when external interrupt edge is detected. Cleared when interrupt processed. Interrupt 1 Type Control Bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. Interrupt 0 Edge Flag. Set by hardware when external interrupt edge is detected. Cleared when interrupt processed. Interrupt 0 Type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. The IT0 and IT1 bits of the TCON register controls the event that will trigger the External Interrupt as follow: IT0 = 0: The INT0, if enabled, occurs if a Low Level is present on P3.2 IT0 = 1: The INT0, if enabled, occurs if a High to Low transition is detected on P3.2 IT1 = 0: The INT1, if enabled, occurs if a Low Level is present on P3.3 IT1 = 1: The INT1, if enabled, occurs if a High to Low transition is detected on P3.3 The IE0 and IE1 bit of the TCON register are External flags that indicate that a transition has been detected on the INT0 and INT1 interrupt pins respectively. If the external interrupt is configured as edge sensitive, the corresponding IE0 and IE1 flag is automatically cleared when the corresponding interrupt is serviced. On the other hand, if the external interrupt is configured as level sensitive, then the corresponding flag must be cleared by the software. Counting Function When operating as a counter, the Timer's register is incremented at every falling edge of the T0 and T1 signals located at the input of the timer. When the sampling circuit sees a high immediately followed by a low in the next machine cycle, the counter is incremented. Two machine cycles are required to detect and record an event. In order to be properly sampled, the duration of the event present to the Timer input should be greater than 1/24 of the oscillator frequency. Timer 0 / Timer 1 Operating Modes The user may change the operating mode by setting the M1 and M0 bits of the TMOD SFR. 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 20 VRS1100 VERSA Datasheet Rev 1.1 Mode 0 A schematic representation of this mode of operation is presented in the figure below. In Mode 0, the Timer operates as 13-bit counter the 5 LSB of the counter is made out of the TLx register and the 8 upper bits are made of THx register. When an overflow causes the value of the register to roll over to 0, the TFx interrupt signal goes to 1. The count value is validated as soon as TRx goes to 1 and the GATE bit is 0, or when INTx is 1. FIGURE 13: TIMER/COUNTER 1 MODE 2: 8-BIT AUTOMATIC RELOAD Fosc /12 0 1 C/T1 / C/T0 = 1 TL1 / TL0 0 7 C/T1 / C/T0 = 1 Control T1 / T0 Pin Reload 0 7 TH1 / TH0 TR1 / TR0 GATE1 / GATE0 TF1 / TF0 FIGURE 12: TIMER/COUNTER 1 MODE 0: 13-BIT COUNTER INT INT1 / INT0 pin Mode 3 In Mode 3 the Timer 1 is blocked as if its control bit, TR1, was set to 0. In this mode, Timer 0's registers TL0 and TH0 are configured as two separate 8-bit counters. Also, the TL0 counter uses Timer 0's control bits C/T, GATE, TR0, INT0, TF0 and the TH0 counter is held in Timer Mode (counting machine cycles) and gains control over TR1 and TF1 from Timer 1. At this point, TH0 controls the Timer 1 interrupt. /12 Fosc 0 C/T1 / C/T0 =0 1 C/T1 / CT0 =1 TL1 / TL0 CLK 0 4 7 Mode 0 Control T1/T0 pin Mode 1 TR1/TR0 GATE1 / GATE0 0 TH1 / TH0 7 INT1 / INT0 pin TF1 / TF0 INT Mode 1 FIGURE 14: TIMER/COUNTER 0 MODE 3 TH0 CLK Mode 1 is almost identical to Mode 0. The difference is that in Mode 1, the counter/timer uses the full 16-bits of the Timer. 7 Control TF1 TR1 Fosc TL0 C/T =0 CLK 1 T0PIN INTERRUPT /12 0 Mode 2 In this Mode, the register of the Timer is configured as an 8-bit automatically re-loadable Counter/Timer. In Mode 2, it is the lower byte TLx that is used as the counter. In the event of a counter overflow, the TFx flag is set to 1 and the value contained in THx, which is preset by software, is reloaded into the TLx counter. The value of THx remains unchanged. 0 0 7 C/T =1 Control TF0 INTERRUPT TR0 GATE INT0 PIN 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 21 VRS1100 VERSA Datasheet Rev 1.1 Timer 2 Timer 2 of the VRS1100 is a 16-bit Timer/Counter. Similar to Timers 0 and 1, Timer 2 can operate either as an event counter or as a timer. The user may switch functions by writing to the C/T2 bit located in the T2CON special function register. Timer 2 has three operating modes: "Auto-Load" "Capture", and "Baud Rate Generator". The T2CON SFR configures the modes of operation of Timer 2. The table below describes each bit in the T2CON special function register. TABLE 27: TIMER 2 CONTROL REGISTER (T2CON) -SFR C8H 7 6 5 4 3 2 1 0 TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 Bit Mnemonic 7 TF2 6 5 4 3 2 Capture/Reload Select. 1: Capture of Timer 2 value into RCAP2H, RCAP2L is performed if EXEN2=1 and a negative transitions occurs on the T2EX pin. The capture mode requires RCLK and TCLK to be 0. 0 EXF2 RCLK TCLK EXEN2 TR2 1 C/T2 Description Timer 2 Overflow Flag: Set by an overflow of Timer 2 and must be cleared by software. TF2 will not be set when either RCLK =1 or TCLK =1. Timer 2 external flag change in state occurs when either a capture or reload is caused by a negative transition on T2EX and EXEN2=1. When Timer 2 is enabled, EXF=1 will cause the CPU to Vector to the Timer 2 interrupt routine. Note that EXF2 must be cleared by software. Serial Port Receive Clock Source. 1: Causes Serial Port to use Timer 2 overflow pulses for its receive clock in Modes 1 and 3. 0: Causes Timer 1 overflow to be used for the Serial Port receive clock. Serial Port Transmit Clock. 1: Causes Serial Port to use Timer 2 overflow pulses for its transmit clock in Modes 1 and 3. 0: Causes Timer 1 overflow to be used for the Serial Port transmit clock. Timer 2 External Mode Enable. 1: Allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the Serial Port. 0: Causes Timer 2 to ignore events at T2EX. Start/Stop Control for Timer 2. 1: Start Timer 2 0: Stop Timer 2 Timer or Counter Select (Timer 2) 1: External event counter falling edge triggered. 0: Internal Timer (OSC/12) CP/RL2 0: Auto-reload reloads will occur either with Timer 2 overflows or negative transitions at T2EX when EXEN2=1. When either RCK =1 or TCLK =1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow. The possible combinations of control bits that may be used for the mode selection of Timer 2 are shown below: TABLE 28: TIMER 2 MODE SELECTION BITS RCLK + TCLK CP/RL2 TR2 MODE 0 0 0 1 1 1 1 X 1 X X 0 16-bit Auto-Reload Mode 16-bit Capture Mode Baud Rate Generator Mode Timer 2 stops The details of each mode are described below. Timer 2 Capture Mode In Capture Mode the EXEN2 bit value defines if the external transition on the T2EX pin will be able to trigger the capture of the timer value. When EXEN2 = 0, Timer 2 acts as a 16-bit timer or counter, which, upon overflowing, will set bit TF2 (Timer 2 overflow bit). This overflow can be used to generate an interrupt. FIGURE 15: TIMER 2 IN CAPTURE MODE FOSC /12 0 TIMER 0 TL2 TH2 7 0 7 0 7 C/T2 1 COUNTER T2 pin 0 RCAP2L RCAP2H 7 TR2 TF2 EXF2 T2EX pin EXEN2 Timer 2 Interrupt When EXEN2 = 1, the above still applies. In addition, it is possible to allow a 1 to 0 transition at the T2EX input to cause the current value stored in the Timer 2 registers (TL2 and TH2) to be captured into the 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 22 VRS1100 VERSA Datasheet Rev 1.1 RCAP2L and RCAP2H registers. Furthermore, the transition at T2EX causes bit EXF2 in T2CON to be set, and EXF2, like TF2, can generate an interrupt. Note that both EXF2 and TF2 share the same interrupt vector. Timer 2 Auto-Reload Mode In this mode, there are also two options. The user may choose either option by writing to bit EXEN2 in T2CON. If EXEN2 = 0, when Timer 2 rolls over, it not only sets TF2, but also causes the Timer 2 registers to be reloaded with the 16-bit value in the RCAP2L and RCAP2H registers previously initialised. In this mode, Timer 2 can be used as a baud rate generator source for the serial port. Timer 2 Baud Rate Generator Mode Timer 2 can be used for UART Baud Rate. This Mode is activated when RCLK is set to 1 and/or TCLK is set to 1. This Mode will be described in the serial port section. FIGURE 17: TIMER 2 IN AUTOMATIC BAUD GENERATOR MODE FOSC /2 0 TIMER 1 TH2 7 0 7 0 7 COUNTER T2 pin 0 RCAP2L TR2 RCAP2H 1 0 0 Timer 1 Overflow /2 If EXEN2=1, then Timer 2 still performs the above operation, but a 1 to 0 transition at the external T2EX input will also trigger an anticipated reload of the Timer 2 with the value stored in RCAP2L, RCAP2H and set EXF2. TL2 0 C/T2 /16 TX Clock /16 RX Clock 1 0 1 SMOD T2EX pin TCLK 7 RCLK EXF2 Timer 2 Interrupt Request EXEN2 UART Serial Port FIGURE 16: TIMER 2 IN AUTO-RELOAD MODE FOSC The serial port on the VRS1100 can operate in full duplex; in other words, it can transmit and receive data simultaneously. It is possible to have different communication speeds for Transmission and Reception by assigning one timer for transmission and one timer for reception. /12 0 TIMER 0 C/T2 1 TL2 TH2 7 0 7 0 7 COUNTER T2 pin 0 TR2 RCAP2L RCAP2H 7 TF2 T2EX pin EXF2 EXEN2 Timer 2 Interrupt The VRS1100 serial port includes a double buffering feature on reception buffer, which allows to start reception of a byte even if the one previously received has not been retrieved from the receive register by the processor. However, if the first byte still has not been read by the time reception of the second byte is complete, the byte present in the receive buffer will be lost. One SFR register, SBUF, gives access to the Transmit and Receive registers of the serial port. When a read operation is performed on the SBUF register, it will access the receive register. When a write operation is performed on the SBUF, the transmit register will be loaded with the value. 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 23 VRS1100 VERSA Datasheet Rev 1.1 UART Control Register TABLE 30: SERIAL PORT MODES OF OPERATION th The serial port control register, SCON contains the 9 data bit for transmit and receive (TB8 and RB8) and all the mode selection bits. SCON also contains the serial port interrupt bits (TI and RI). TABLE 29: SERIAL PORT CONTROL REGISTER (SCON) - SFR 98H 7 6 5 4 3 2 1 0 SM0 SM1 SM2 REN TB8 RB8 TI RI Bit 7 Mnemonic SM0 6 SM1 5 SM2 Description Bit to select mode of operation (see table below) Bit to select mode of operation (see table below) Multiprocessor communication is possible in Modes 2 and 3. In Modes 2 or 3 if SM2 is set to 1, RI will th not be activated if the received 9 data bit (RB8) is 0. 4 REN 3 TB8 2 1 0 RB8 In Mode 1, if SM2 = 1 then RI will not be activated if a valid stop bit was not received. Serial Reception Enable Bit This bit must be set by software and cleared by software. 1: Serial reception enabled 0: Serial reception disabled th 9 data bit transmitted in Modes 2 and 3 This bit must be set by software and cleared by software. th 9 data bit received in Modes 2 and 3. TI In Mode 1, if SM2 = 0, RB8 is the stop bit that was received. In Mode 0, this bit is not used. This bit must be cleared by software. Transmission Interrupt flag. RI Automatically set to 1 when: th * The 8 bit has been sent in Mode 0. * Automatically set to 1 when the stop bit has been sent in the other modes. This bit must be cleared by software. Reception Interrupt flag SM0 SM1 Mode Description Baud Rate 0 0 1 0 1 0 0 1 2 Shift Register 8-bit UART 9-bit UART 1 1 3 9-bit UART Fosc/12 Variable Fosc/64 or Fosc/32 Variable UART Operating Modes The VRS1100's serial port can operate in four different Modes. In all four Modes, a transmission is initiated by an instruction that uses the SBUF register as a destination register. In Mode 0, reception is initiated by setting RI to 0 and REN to 1. An incoming start bit initiates reception in the other modes provided that REN is set to 1. The following paragraphs describe the four Modes. UART Operation in Mode 0 In this Mode, the serial data exits and enters through the RXD pin. TXD is used to output the shift clock. The signal is composed of 8 data bits starting with the LSB. The baud rate in this mode is 1/12 the oscillator frequency. FIGURE 18: SERIAL PORT MODE 0 BLOCK DIAGRAM Internal Bus 1 Write to SBUF Q S SBUF RXD P3.0 D Shift CLK ZERO DETECTOR Shift Clock TXD P3.1 Shift Start TX Control Unit TX Clock Fosc/12 Send TI Serial Port Interrupt RI RX Clock Receive RX Control Unit Automatically set to 1 when: th * The 8 bit has been received in Mode 0. * Automatically set to 1 when the stop bit has been sent in the other modes (see SM2 exception). This bit must be cleared by software. RI REN Start Shift 1 RXD P3.0 Input Function 1 1 1 1 1 1 0 Shift Register RXD P3.0 SBUF READ SBUF Internal Bus 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 24 VRS1100 VERSA Datasheet Rev 1.1 UART Transmission in Mode 0 UART Operation in Mode 1 Any instruction that uses SBUF as a destination register may initiate a transmission. The "write to SBUF" signal also loads a 1 into the 9th position of the transmit shift register and tells the TX control block to begin a transmission. The internal timing is such that one full machine cycle will elapse between a write to SBUF instruction and the activation of SEND. For an operation in Mode 1, 10 bits are transmitted (through TXD) or received (through RXD). The transactions are composed of: a Start bit (Low); 8 data bits (LSB first) and one Stop bit (high). The reception is completed once the Stop bit sets the RB8 flag in the SCON register. Either Timer 1 or Timer 2 controls the baud rate in this mode. The SEND signal enables the output of the shift register to the alternate output function line of P3.0 and enables SHIFT CLOCK to the alternate output function line of P3.1. The following diagram shows the serial port structure when configured in Mode 1. FIGURE 19: SERIAL PORT MODE 1 AND 3 BLOCK DIAGRAM Internal Bus At every machine cycle in which SEND is active, the contents of the transmit shift register are shifted to the right by one position. Zeros come in from the left as data bits shift out to the right. The TX control block sends its final shift and deactivates SEND while setting T1 after one condition is fulfilled: When the MSB of the data byte is at the output position of the shift register; the 1 that was initially loaded into the 9th position is just to the left of the MSB; and all positions to the left of that contain zeros. Once these conditions are met, the de-activation of SEND and the setting of T1 occur at T1 of the 10th machine cycle after the "write to SBUF" pulse. UART Reception in Mode 0 1 Write to SBUF Timer 1 Overflow Q S SBUF CLK Timer 2 Overflow /2 ZERO DETECTOR 0 1 SMOD 0 Shift Start 1 /16 0 TX Clock 1 RCLK Send TI /16 Serial Port Interrupt RX Clock 1-0 Transition Detector RXD Data TX Control Unit TCLK Start Bit Detector RI Load SBUF RX Control Unit SHIFT 9-Bit Shift Register Shift LOAD SBUF When REN and R1 are set to 1 and 0 respectively, reception is initiated. The bits 11111110 are written to the receive shift register at the end of the next machine cycle by the RX control unit. In the following phase, the RX control unit will activate RECEIVE. TXD D SBUF READ SBUF Internal Bus The contents of the receive shift register are shifted one position to the left at the end of every machine cycle during which RECEIVE is active. The value that comes in from the right is the value that was sampled at the P3.0 pin. 1's are shifted out to the left as data bits are shifted in from the right. The RX control block is flagged to do one last shift and load SBUF when the 0 that was initially loaded into the rightmost position arrives at the leftmost position in the shift register. 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 25 VRS1100 VERSA Datasheet Rev 1.1 UART Transmission in Mode 1 Transmission is initiated by any instruction that makes use of SBUF as a destination register. The 9th bit position of the transmit shift register is loaded by the "write to SBUF" signal. This event also flags the TX Control Unit that a transmission has been requested. It is after the next rollover in the divide-by-16 counter when transmission actually begins. It follows that the bit times are synchronized to the divide-by-16 counter and not to the "write to SBUF" signal. When a transmission begins, it places the start bit at TXD. Data transmission is activated one bit time later. This activation enables the output bit of the transmit shift register to TXD. One bit time after that, the first shift pulse occurs. In this Mode, zeros are clocked in from the left as data bits are shifted out to the right. When the most significant bit of the data byte is at the output position of the shift register, the 1 that was initially loaded into the 9th position is to the immediate left of the MSB, and all positions to the left of that contain zeros. This condition flags the TX Control Unit to shift one more time. UART Reception in Mode 1 A one to zero transition at pin RXD will initiate reception. It is for this reason that RXD is sampled at a rate of 16 multiplied by the baud rate that has been established. When a transition is detected, 1FFh is written into the input shift register and the divide-by-16 counter is immediately reset. The divide-by-16 counter is reset in order to align its rollovers with the boundaries of the incoming bit times. In total, there are 16 states in the counter. During the 7th, 8th and 9th counter states of each bit time; the bit detector samples the value of RXD. The accepted value is the value that was seen in at least two of the three samples. The purpose of doing this is for noise rejection. If the value accepted during the first bit time is not zero, the receive circuits are reset and the unit goes back to searching for another one to zero transition. All false start bits are rejected by doing this. If the start bit is valid, it is shifted into the input shift register, and the reception of the rest of the frame will proceed. For a receive operation, the data bits come in from the right as 1's shift out on the left. As soon as the start bit arrives at the leftmost position in the shift register, (9bit register), it tells the UART's receive controller block to perform one last shift operation: to set RI and to load SBUF and RB8. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated: o o Either SM2 = 0 or the received stop bit = 1 RI = 0 If both conditions are met, the stop bit goes into RB8, the 8 data bits go into SBUF, and RI is activated. If one of these conditions is not met, the received frame is completely lost. At this time, whether the above conditions are met or not, the unit goes back to searching for a one to zero transition in RXD. UART Operation in Mode 2 In Mode 2 a total of 11 bits are transmitted (through TXD) or received (through RXD). The transactions are composed of: a Start bit (Low), 8 data bits (LSB first), a programmable 9th data bit, and one Stop bit (High). For transmission, the 9th data bit comes from the TB8 bit of SCON. For example, the parity bit P in the PSW could be moved into TB8. In the case of receive, the 9th data bit is automatically written into RB8 of the SCON register. 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 26 VRS1100 VERSA Datasheet Rev 1.1 UART Operation in Mode 3 In Mode 2, the baud rate is programmable to either 1/32 or 1/64 the oscillator frequency. In Mode 3, 11 bits are transmitted (through TXD) or received (through RXD). The transactions are composed of: a Start bit (Low), 8 data bits (LSB first), a programmable 9th data bit, and one Stop bit (High). FIGURE 20: SERIAL PORT MODE 2 BLOCK DIAGRAM Internal Bus 1 Write to SBUF Q S Fosc/2 SBUF TXD D Mode 3 is identical to Mode 2 in all respects but one: the baud rate. Either Timer 1 or Timer 2 generates the baud rate in Mode 3. CLK ZERO DETECTOR /2 FIGURE 21: SERIAL PORT MODE 3 BLOCK DIAGRAM 0 1 Shift Stop SMOD Start /16 Start 1 Serial Port Interrupt RX Clock Control Write to SBUF Send TI /16 1-0 Transition Detector Internal Bus TX Control Unit TX Clock Sample Data RI Timer 1 Overflow RX Control Unit SHIFT Q S SBUF TXD D Load SBUF CLK Timer 2 Overflow /2 ZERO DETECTOR 0 1 SMOD RXD Bit Detector 0 Start 1 SBUF READ SBUF 0 Data TX Control Unit /16 Shift LOAD SBUF Shift TCLK 9-Bit Shift Register TX Clock 1 RCLK Send TI /16 SAMPLE RX Clock 1-0 Transition Detector Start Serial Port Interrupt RI Load SBUF RX Control Unit SHIFT Internal Bus RXD Bit Detector 9-Bit Shift Register Shift LOAD SBUF SBUF READ SBUF Internal Bus 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 27 VRS1100 VERSA Datasheet Rev 1.1 UART in Mode 2 and 3: Additional Information UART Reception in Mode 2 and Mode 3 As mentioned earlier, for an operation in Modes 2 and 3, 11 bits are transmitted (through TXD) or received (through RXD). The signal comprises of: a logical low Start bit, 8 data bits (LSB first), a programmable 9th data bit, and one logical high Stop bit. On transmit, (TB8 in SCON) can be assigned the value of 0 or 1. On receive; the 9th data bit goes into RB8 in SCON. The baud rate is programmable to either 1/32 or 1/64 the oscillator frequency in Mode 2. Mode 3 may have a variable baud rate generated from either Timer 1 or Timer 2 depending on the states of TCLK and RCLK. One to zero transitions on the RXD pin initiate reception. For this reason the RXD is sampled at a rate of 16 multiplied by the baud rate that has been established. When a transition is detected, the 1FFh is written into the input shift register and the divide-by-16 counter is immediately reset. UART Transmission in Mode 2 and Mode 3 The transmission is initiated by any instruction that makes use of SBUF as the destination register. The 9th bit position of the transmit shift register is loaded by the "write to SBUF" signal. This event also informs the UART transmission control unit that a transmission has been requested. After the next rollover in the divide-by16 counter, a transmission actually starts at the beginning of the machine cycle. It follows that the bit times are synchronized to the divide-by-16 counter and not to the "write to SBUF" signal, as in the previous mode. Transmissions begin when the SEND signal is activated, which places the Start bit on TXD pin. Data is activated one bit time later. This activation enables the output bit of the transmit shift register to the TXD pin. The first shift pulse occurs one bit time after that. The first shift clocks a Stop bit (1) into the 9th bit position of the shift register on TXD. Thereafter, only zeros are clocked in. Thus, as data bits shift out to the right, zeros are clocked in from the left. When TB8 is at the output position of the shift register, the stop bit is just to the left of TB8, and all positions to the left of that contain zeros. This condition signals to the TX control unit to shift one more time and set TI, while deactivating SEND. This occurs at the 11th divide-by16 rollover after "write to SBUF". During the 7th, 8th and 9th counter states of each bit time; the bit detector samples the value of RXD. The accepted value is the value that was seen in at least two of the three samples. If the value accepted during the first bit time is not zero, the receive circuits are reset and the unit goes back to searching for another one to zero transition. If the start bit is valid, it is shifted into the input shift register, and the reception of the rest of the frame will proceed. For a receive operation, the data bits come in from the right as 1's shift out on the left. As soon as the start bit arrives at the leftmost position in the shift register (9-bit register), it tells the RX control block to do one more shift, to set RI, and to load SBUF and RB8. The signal to set RI and to load SBUF and RB8 will be generated if, and only if, the following conditions are satisfied at the instance when the final shift pulse is generated: - Either SM2 = 0 or the received 9th bit equal 1 RI = 0 If both conditions are met, the 9th data bit received goes into RB8, and the first 8 data bits go into SBUF. If one of these conditions is not met, the received frame is completely lost. One bit time later, whether the above conditions are met or not, the unit goes back to searching for a one to zero transition at the RXD input. Please note that the value of the received stop bit is unrelated to SBUF, RB8 or RI. 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 28 VRS1100 VERSA Datasheet Rev 1.1 The value to put into the TH1 register is defined by the following formula: UART Baud Rates In Mode 0, the baud rate is fixed and can be represented by the following formula: TH1 = 256 - Mode 0 Baud Rate = Oscillator Frequency 12 In Mode 2, the baud rate depends on the value of the SMOD bit in the PCON SFR. From the formula below, we can see that if SMOD = 0 (which is the value on reset), the baud rate is 1/32 the oscillator frequency. Mode 2 Baud Rate = 2SMOD x (Oscillator Frequency) 64 The Timer 1 and/or Timer 2 overflow rate determines the baud rates in Modes 1 and 3. Generating UART Baud Rate with Timer 1 When Timer 1 functions as a baud rate generator, the baud rate in Modes 1 and 3 are determined by the Timer 1 overflow rate. Mode 1,3 Baud Rate = 2SMODx Timer 1 Overflow Rate 32 2SMODx Fosc 32 x 12x (Baud Rate) Generating UART Baud Rates with Timer 2 Timer 2 is often preferred to generate the baud rate, as it can be easily configured to operate as a 16-bit timer with auto-reload. This allows for much better resolution than using Timer 1 in 8-bit auto-reload mode. The baud rate using Timer 2 is defined as: Mode 1,3 Baud Rate = Timer 2 Overflow Rate 16 The timer can be configured as either a timer or a counter in any of its 3 running modes. In most typical applications, it is configured as a timer (C/T2 is set to 0). To make the Timer 2 operate as a baud rate generator, the TCLK and RCLK bits of the T2CON register must be set to 1. The baud rate generator mode is similar to the autoreload mode in that an overflow in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software. However, when Timer 2 is configured as a baud rate generator, its clock source is Osc/2. Timer 1 must be configured as an 8-bit timer (TL1) with auto-reload with TH1 value when an overflow occurs (Mode 2). In this application, the Timer 1 interrupt should be disabled. The two following formulas can be used to calculate the baud rate and the reload value to put in the TH1 register. Mode 1,3 Baud Rate = SMOD x Fosc 2 32 x 12(256 - TH1) 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 29 VRS1100 VERSA Datasheet Rev 1.1 The following formula can be used to calculate the baud rate in modes 1 and 3 using the Timer 2: Modes 1, 3 Baud Rate = Oscillator Frequency 32x[65536 - (RCAP2H, RCAP2L)] The formula below is used to define the reload value to put into the RCAP2h, RCAP2L registers to achieve a given baud rate. (RCAP2H, RCAP2L) = 65536 - Fosc 32x[Baud Rate] In the above formula, RCAP2H and RCAP2L are the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. Note that a rollover in TH2 does not set TF2, and will not generate an interrupt. Because of this, Timer 2 interrupt does not have to be disabled when Timer 2 is configured in baud rate generator mode. Furthermore, when Timer 2 is configured as UART baud rate generator and running (TR2 is set to 1), the user should not try to perform read or write operations to the TH2 or TL2 and RCAP2H, RCAP2L registers 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 30 VRS1100 VERSA Datasheet Rev 1.1 Timer 1 Reload Value in Modes 1 & 3 for UART Baud Rate The following table gives examples of Timer 1, 8-bit reload value when used as a UART Baud Rate generator and the SMOD bit of the PCON register is set to 1. 115200bps 57600bps 38400bps 31250bps 19200bps 9600bps 2400bps 1200bps 300bps 22.184MHz FFh Feh FDh FAh F4h D0h A0h - 16.000MHz DDh BBh - 14.745MHz FEh FCh F8h E0h C0h 00h 12.000MHz FEh E6h CCh 30h 11.059MHz FFh FDh FAh E8h D0h 40h 8.000MHz DDh 75h 3.57MHz C2h Timer 2 Reload Value in Modes 1 & 3 for UART Baud Rate Here are examples of [RCAP2H, RCAP2L] reload values for Timer 2 when it is used as baud rate generator for the VRS1100 UART 230400bps 115200bps 57600bps 38400bps 31250bps 19200bps 9600bps 2400bps 1200bps 300bps 22.184MHz FFFDh FFFAh FFF4h FFEEh FFEAh FFDCh FFB8h FEE0h FDC0h F700h 16.000MHz FFF3h FFF0h FFE6h FFCCh FF30h FE5Fh F97Dh 14.745MHz FFFEh FFFCh FFF8h FFF4h FFF1h FFE8h FFD0h FF40h FE80h FA00h 12.000MHz FFF4h FFD9h FF64h FEC7h FB1Eh 11.059MHz FFFDh FFFAh FFF7h FFF5h FFEEh FFDCh FF70h FEE0h FB80h 8.000MHz FFF8h FFF3h FFE6h FF98h FF30h FCBEh 3.57MHz FFD1h FFA3h FE8Bh UART initialization in Mode 3 using Timer 1 UART initialization in Mode 3, using Timer 2 ;*** INTIALIZE THE UART @ 9600BPS, Fosc=11.0592MHz ;*** INTIALIZE THE UART @57600BPS, Fosc=11.0592MHz INISER0T1I: MOV A,T2CON ANL A,#11001111B MOV T2CON,A MOV PCON,#80H MOV TL1,#0FAH MOV TH1,#0FAH INISER0T2I: MOV ;RETRIEVE CURRENT VALUE OF T2CON ;RCLK & TCLK BIT = 0 -> TO USE TIMER1 ;BAUD RATE GENERATOR SOURCE FOR UART ;SET THE SMOD BIT TO 1 ;CONFIG TIMER1 AT 8BIT WITH AUTO-RELOAD ;CALCULATE THE TIMER 1 RELOAD VALUE ;TH1 = [(2^SMOD) * Fosc] / (32 * 12 * Fcomm) ;TH1 FOR 9600BPS @ 11.059MHz = FAh MOV SCON,#05Ah ;CONFIG SCON_0 MODE_1 MOV TMOD,#00100000B ;CONFIG TIMER 1 IN MODE 2, 8BIT ; + AUTO RELOAD MOV TCON,#01000000B ;START TIMER1 CLR CLR SCON.0 SCON.1 ;CLEAR UART RX, TX FLAGS MOV SBUF,#DATA ;SEND ONE BYTE ON THE SERIAL PORT MOV MOV SCON,#05Ah ;CONFIG SCON_0 MODE_1, ;CALCULATE RELOAD VALUE WITH T2 ;RCAP2H,RCAP2L = 65536 - [ Fosc / (32*Fcomm)] RCAP2H,#0FFh RCAP2L,#0DCh ;RELOAD VALUE 57600bps, 11.059MHz =FFFAh ; MOV T2CON,#034h ;SERIAL PORT0, TIMER2 RELOAD START CLR CLR SCON.0 SCON.1 ;CLEAR UART RX, TX FLAGS MOV SBUF,#DATA ;SEND ONE BYTE ON THE SERIAL PORT 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 31 VRS1100 VERSA Datasheet Rev 1.1 Interrupt Vectors Interrupts The VRS1100 has 8 interrupt sources (9 if we include the WDT) and 7 interrupt vectors (including reset) to handle them. The interrupt can be enabled via the IE register shown below: TABLE 31: IE INTERRUPT ENABLE REGISTER -SFR A8H 7 6 5 4 3 EA - ET2 ES ET1 Bit 7 Mnemonic EA 6 - 5 4 3 2 1 0 ET2 ES ET1 EX1 ET0 EX0 2 EX1 1 0 ET0 EX0 Description Disables All Interrupts 0: no interrupt acknowledgment 1: Each interrupt source is individually enabled or disabled by setting or clearing its enable bit. Reserved Timer 2 Interrupt Enable Bit Serial Port Interrupt Enable Bit Timer 1 Interrupt Enable Bit External Interrupt 1 Enable Bit Timer 0 Interrupt Enable Bit External Interrupt 0 Enable Bit The following figure illustrates the various interrupt sources on the VRS1100. IT0 IE0 TF1 T1 RI IT1 Interrupt Source RESET (+ WDT) INT0 Timer 0 INT1 Timer 1 Serial Port Timer 2 Flag WDR IE0 TF0 IE1 TF1 RI+TI TF2+EXF2 Vector Address 0000h* 0003h 000Bh 0013h 001Bh 0023h 002Bh *If location 0000h = FFh, the PC jump to the ISP program. External Interrupts The VRS1100 has two external interrupt inputs named INT0 and INT1. These interrupt lines are shared with P3.2 and P3.3. The bits IT0 and IT1 of the TCON register determine whether the external interrupts are level or edge sensitive. If ITx = 0, the interrupt will occur when a logic low condition is present on the interrupt pin. TF0 INT1 TABLE 32: INTERRUPT VECTOR ADDRESS If ITx = 1, the interrupt will be raised when a 1-> 0 transition occurs at the interrupt pin. The duration of the transition must be at least equal to 12 oscillator cycles. FIGURE 22: INTERRUPT SOURCES INT0 The table shown below specifies each interrupt source, its flag and its vector address. IE1 INTERRUPT SOURCES The state of the external interrupt, when enabled, can be monitored using the flags, IE0 and IE1 of the TCON register that are set when the interrupt condition occurs. In the case where the interrupt was configured as edge sensitive, the associated flag is automatically cleared when the interrupt is serviced. If the interrupt is configured as level sensitive, then the interrupt flag must be cleared by the software. TF2 EXF2 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 32 VRS1100 VERSA Datasheet Rev 1.1 Timer 0 and Timer 1 Interrupt Execution of an Interrupt Both Timer 0 and Timer 1 can be configured to generate an interrupt when a rollover of the timer/counter occurs (except Timer 0 in Mode 3). When the processor receives an interrupt request, an automatic jump to the desired subroutine occurs. This jump is similar to executing a branch to a subroutine instruction: the processor automatically saves the address of the next instruction on the stack. An internal flag is set to indicate that an interrupt is taking place, and then the jump instruction is executed. An interrupt subroutine must always end with the RETI instruction. This instruction allows users to retrieve the return address placed on the stack. The TF0 and TF1 flags serve to monitor timer overflow occurring from Timer 0 and Timer 1. These interrupt flags are automatically cleared when the interrupt is serviced. Timer 2 interrupt Timer 2 interrupt can occur if TF2 and/or EXF2 flags are set to 1 and if the Timer 2 interrupt is enabled. The RETI instruction also allows updating of the internal flag that will take into account an interrupt with the same priority. The TF2 flag is set when a rollover of Timer 2 Counter/Timer occurs. The EXF2 flag can be set by a 1->0 transition on the T2EX pin by the software. Interrupt Enable and Interrupt Priority Note that neither flag is cleared by the hardware upon execution of the interrupt service routine. The service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt. These flag bits will have to be cleared by the software. When the VRS1100 is initialized, all interrupt sources are inhibited by the bits of the IE register being reset to 0. It is necessary to start by enabling the interrupt sources that the application requires. This is achieved by setting bits in the IE register, as discussed previously. Every bit that generates interrupts can either be cleared or set by the software, yielding the same result as when the operation is done by the hardware. In other words, pending interrupts can be cancelled and interrupts can be generated by the software. This register is part of the bit addressable internal RAM. For this reason, it is possible to modify each bit individually in one instruction without having to modify the other bits of the register. All interrupts can be inhibited by setting EA to 0. Serial Port Interrupt The order in which interrupts are serviced is shown in the following table: The serial port can generate an interrupt upon byte reception or once the byte transmission is completed. Those two conditions share the same interrupt vector and it is up to the interrupt service routine to find out what caused the interrupt by looking at the serial interrupt flags RI and TI. Note that neither of these flags is cleared by the hardware upon execution of the interrupt service routine. The software must clear these flags. TABLE 33: INTERRUPT PRIORITY Interrupt Source RESET + WDT (Highest Priority) IE0 TF0 IE1 TF1 RI+TI TF2+EXF2 (Lowest Priority) 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 33 VRS1100 VERSA Datasheet Rev 1.1 TABLE 35: WATCH DOG TIMER KEY REGISTER: WDTKEY - SFR 97H Modifying the Order of Priority 7 The VRS1100 allows the user to modify the natural priority of the interrupts. One may modify the order by programming the bits in the IP (Interrupt Priority) register. When any bit in this register is set to 1, it gives the corresponding source a greater priority than interrupts coming from sources that don't have their corresponding IP bit set to 1. The IP register is represented in the table below. TABLE 34: IP INTERRUPT PRIORITY REGISTER -SFR B8H 7 6 5 4 3 EA - ET2 ES ET1 2 EX1 1 0 ET0 EX0 Bit 7 6 Mnemonic - Description 5 4 3 2 1 0 PT2 PS PT1 PX1 PT0 PX0 Gives Timer 2 Interrupt Higher Priority Gives Serial Port Interrupt Higher Priority Gives Timer 1 Interrupt Higher Priority Gives INT1 Interrupt Higher Priority Gives Timer 0 Interrupt Higher Priority Gives INT0 Interrupt Higher Priority The Watch Dog Timer The VRS1100 Watch Dog Timer (WDT) is a 16-bit free-running counter operating from an independent 250KHz internal RC oscillator. The overflow of the Watch Dog Timer counter will reset the processor. The WDT is a useful safety measure for systems that could be affected by noise, power glitches and other conditions that can cause the software to go into infinite dead loops or runaways by giving a recovery mechanism from abnormal software conditions. Watch Dog Timer Registers The configuration and use of the VRS1100 Watch Dog Timer is handled by three registers: WDTKEY, WDTCTRL and SYSCON. The WDTKEY register provides protection level to ensure that the Watch Dog Timer doesn't get inadvertently reset in case of program malfunction. Bit 7:0 6 Mnemonic WDTKEY 5 4 3 WDTKEY7:0 2 1 0 Description Watch Dog Key The WDTCTRL register is by default configured as a Read-Only register. To modify its contents, two consecutive write operations to the WDTKEY register must be performed first: MOV MOV WDTKEY,#01Eh WDTKEY,#0E1h Once the configuration or WDT reset operation is completed, the WDTCTRL register can be put back in Read-Only by writing the following sequence into the WDTKEY register: MOV MOV WDTKEY,#0E1h WDTKEY,#01Eh Once the WDT operation is activated, the users software must clear it periodically. In the case where the WDT is not cleared, its overflow will trigger a reset of the VRS1100. TABLE 36: WATCH DOG TIMER CONTROL (WDTCTRL) - SFR 9FH 7 6 WDTE Unused Bit 7 Mnemonic WDTE 6 5 [4:3] 2 1 0 Unused WDTCLR Unused WDTPS2 WDTPS1 WDTPS0 5 WDT CLR 4 3 Unused 2 WDT PS2 1 WDT PS1 0 WDT PS0 Description Watch Dog Timer Enable Bit 0: Watch Dog Timer is disabled 1: Watch Dog Timer is enabled Watch Dog Timer Counter Clear Bit Clock Source Divider Bit 2 Clock Source Divider Bit 1 Clock Source Divider Bit 0 The WDT timeout delay can be adjusted by configuring the clock divider input for the time base source clock of the WDT. To select the divider value, the [WDTPS2~WDTPS0] bits of the WDT Control Register should be set accordingly. The next table gives the approximate timeout period the user will obtain for different values of the WDTPSx bits of the Watch Dog Timer Register. 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 34 VRS1100 VERSA Datasheet Rev 1.1 TABLE 37: WDT TIMEOUT PERIOD AT WDT initialization Example WDTPS [2:0] WDT Period 000 2.05ms 001 4.10ms 010 8.19ms 011 16.38ms 100 32.77ms 101 65.54ms 110 131.07ms 111 262.14ms To enable the WDT, the user must set bit 7 (WDTE) of the WDTCTRL register to 1. Once WDTE has been set to 1, the 16-bit counter will start to count using the internal 250kHz oscillator as clock source, divided according to the value of the WDTPS2~WDTPS0 bits. Clearing the WDT is accomplished by setting the WDTCLR bit of the WDTCTRL to 1. This action will clear the contents of the 16-bit counter and force it to restart. In the case where the Watch Dog Timer overflows, the Watch Dog Timer will reset the processor and the WDR bit (7) of SYSCON register will be set to 1 and the WDTE bit will be cleared to 0. The user should check the WDR bit if an unpredicted reset has taken place. The user should check the WDR bit of the SYSCON register whenever an unpredicted reset has taken place. If the WDR bit is set, this mean the Processor Reset was caused by the Watch Dog Timer. The following program example shows the initialization sequence of the Watch Dog Timer and the routine to periodically clear it. ;*** VARIABLE DEFINITION *** CPTR PORTVAL EQU EQU 020H 00H ;*** PROGRAM START HERE **** ORG 0000h LJMP START ;*** MAIN PROGRAM START *** ORG 0100h ;*** CHECK IF RESET WAS CAUSED BY THE WATCHDOG TIMER START: MOV A,SYSCON ANL A,#80H JNZ WDTRESET ;WDT BIT SET -> WE GOT A WDT RESET INITWDT: MOV MOV WDTKEY,#01EH ;UNLOCK THE WDTCTRL REG ACCESS IN WDTKEY,#0E1H ;WRITING MODE MOV WDTCTRL,#10000010B ;CONFIG THE WATCHDOG TIMER ;BIT 7 - WDTEN=1 WATCHDOG TIMER ENABLE ;BIT 6 - UNUSED ;BIT 5 - WDTCLR=1 WATCHDOG CLEAR ;BIT 4:3 - UNUSED ;BIT 2:0 - WDTCLK=010 - WDT TIMEOUT = 8mS MOV MOV MOV WDTRESET: NOP MOV CPL MOV MOV WDTKEY,#0E1H ;LOCK THE WDTCTRL ACCESS IN WRITING WDTKEY,#01EH PORTVAL,#00H ;INIT PORT VALUE TO 00H A,PORTVAL A PORTVAL,A P1,A ;IF THE WDT CAUSE THE RESET INIT PORTVAL ;TOGGLE P1 VALUE ;*** SEQUENCE TO CLEAR THE WATCHDOG TIMER (SAME AS CONFIG) LOOP: ;MOV WDTKEY,#01EH ;UNLOCK THE WDTCTRL REG ACCESS IN ;WRITING MODE ;MOV WDTKEY,#0E1H ;MOV WDTCTRL,#10100010B ;CONFIG THE WDT TIMER ;BIT 7 - WDTEN=1 WDT ENABLE ;BIT 6 - UNUSED ;BIT 5 - WDTCLR=1 WDT CLEAR ;BIT 4:3 - UNUSED ;BIT 2:0 - WDTCLK=010 - WDT TIMEOUT = 8mS ;MOV ;MOV WDTKEY,#0E1H ;LOCK THE WDTCTRL ACCESS IN WRITING WDTKEY,#01EH (...) LJMP LOOP 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 35 VRS1100 VERSA Datasheet Rev 1.1 Pulse Width Modulation (PWM) PWM Output Enable Register TABLE 38: PWM OUTPUT ENABLE REGISTER (PWME) - SFR 9BH The Pulse Width Modulation (PWM) module has 4 Outputs. Each output uses an 8-bit PWM data register (PWMD) to set the number of continuous pulses within a PWM frame cycle. PWM Function Description: Each 8-bit PWM output is composed of an 8-bit register that consists of a 5-bit PWM (5 MSBs) and a 3-bit (LSBs) Narrow Pulse Generator (NP). The 5-bit PWM determines the duty cycle of the output. The 3-bit NPx generates and inserts narrow pulses among the PWM frame made of 8 cycles. The number of pulses generated is equal to the number programmed in the 3-bit NP. The NP is used to generate an equivalent 8-bit resolution PWM type DAC with a reasonably high repetition rate through a 5bit PWM clock speed. The PDCK[1:0] settings of the PWMC (A3h) register is used to derive the PWM clock from Fosc. PWM Clock = Fosc 2(PDCK [1:0] +1) The PWM output cycle frame repetition rate (frequency) is calculated using the following formula: PWM Clock = 7 6 5 PWM3E 2 PWM0E 1 -3 PWM1E Bit 7:6 5 4 3 Mnemonic PWM3E PWM2E PWM1E 2 PWM0E 1:0 - 4 PWM2E 0 - Description When bit is set to one, the corresponding PWM pin is active as a PWM function. When the bit is cleared, the corresponding PWM pin is active as an I/O pin. These five bits are cleared upon reset. PWM Registers -PWM Control Register The table below represents the PWM Control Register. TABLE 39: PWM CONTROL REGISTER (PWMC) - SFR A3H 7 6 Bit [7:2] 1 0 5 4 Unused Mnemonic Unused PDCK1 PDCK0 3 2 1 0 PDCK1 PDCK0 Description Input Clock Frequency Divider Bit 1 Input Clock Frequency Divider Bit 0 The following table shows the relationship between the values of PDCK1/PDCK0 and the value of the divider. Numerical values of the corresponding frequencies are also provided. PDCK1 PDCKO Divider 0 0 1 1 0 1 0 1 2 4 8 16 PWM clock, Fosc=20MHz 10MHz 5MHz 2.5MHz 1.25MHz PWM clock, Fosc=24MHz 12MHz 6MHz 3MHz 1.5MHz Fosc 32 x 2(PDCK [1:0] +1) 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 36 VRS1100 VERSA Datasheet Rev 1.1 PWM Data Registers The tables below show the PWM Data Registers. The PWMDx bits hold the content of the PWM Data Register and determine the duty cycle of the PWM output waveform. The NPx[2:0] bits will insert narrow pulses in the 8-PWM-cycle frame. TABLE 40: PWM DATA REGISTER 0 (PWMD0) - SFR A4H 7 PWMD0.4 6 PWMD0.3 5 PWMD0.2 4 PWMD0.1 3 PWMD0.0 2 NP0.2 1 NP0.1 0 NP0.0 Bit 7 6 5 4 3 2 1 0 Mnemonic PWMD0.4 PWMD0.3 PWMD0.2 PWMD0.1 PWMD0.0 NP0.2 NP0.1 NP0.0 Description Contents of PWM Data Register 0 Bit 4 Contents of PWM Data Register 0 Bit 3 Contents of PWM Data Register 0 Bit 2 Contents of PWM Data Register 0 Bit 1 Contents of PWM Data Register 0 Bit 0 Inserts Narrow Pulses in a 8-PWM-Cycle Frame TABLE 41: PWM DATA REGISTER 1 (PWMD1) - SFR A5H 7 PWMD1.4 6 PWMD1.3 5 PWMD1.2 4 PWMD1.1 3 PWMD1.0 2 NP1.2 1 NP1.1 0 NP1.0 Bit 7 6 5 4 3 2 1 0 Mnemonic PWMD1.4 PWMD1.3 PWMD1.2 PWMD1.1 PWMD1.0 NP1.2 NP1.1 NP1.0 Description Contents of PWM Data Register 1 Bit 4 Contents of PWM Data Register 1 Bit 3 Contents of PWM Data Register 1 Bit 2 Contents of PWM Data Register 1 Bit 1 Contents of PWM Data Register 1 Bit 0 Inserts Narrow Pulses in a 8-PWM-Cycle Frame Bit 7 6 5 4 3 2 1 0 Mnemonic PWMD2.4 PWMD2.3 PWMD2.2 PWMD2.1 PWMD2.0 NP2.2 NP2.1 NP2.0 Description Contents of PWM Data Register 2 Bit 4 Contents of PWM Data Register 2 Bit 3 Contents of PWM Data Register 2 Bit 2 Contents of PWM Data Register 2 Bit 1 Contents of PWM Data Register 2 Bit 0 Inserts Narrow Pulses in a 8-PWM-Cycle Frame TABLE 43: PWM DATA REGISTER 3 (PWMD3) - SFR A7H 7 PWMD3.4 6 PWMD3.3 5 PWMD3.2 4 PWMD3.1 3 PWMD3.0 2 NP3.2 1 NP3.1 0 NP3.0 Bit 7 6 5 4 3 2 1 Mnemonic PWMD3.4 PWMD3.3 PWMD3.2 PWMD3.1 PWMD3.0 NP3.2 NP3.1 Description Contents of PWM Data Register 3 Bit 4 Contents of PWM Data Register 3 Bit 3 Contents of PWM Data Register 3 Bit 2 Contents of PWM Data Register 3 Bit 1 Contents of PWM Data Register 3 Bit 0 Inserts Narrow Pulses in a 8-PWM-Cycle Frame The table below shows the number of PWM cycles inserted in an 8-cycle frame vs the NPx value. NP[2:0] 000 001 010 011 100 101 110 111 Number of PWM cycles inserted in an 8-cycle frame 0 1 2 3 4 5 6 7 TABLE 42: PWM DATA REGISTER 2 (PWMD2) - SFR A6H 7 PWMD2.4 6 PWMD2.3 5 PWMD2.2 4 PWMD2.1 3 PWMD2.0 2 NP2.2 1 NP2.1 0 NP2.0 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 37 VRS1100 VERSA Datasheet Rev 1.1 Example of PWM Timing Diagram MOV PWMD0 #83H MOV PWME, #08H ; PWMD04:0]=10h (=16T high, 16T low), NP02:0] = 3 ; Enable P1.3 as PWM output pin FIGURE 23: PWM TIMING DIAGRAM 1st Cycle frame 2nd Cycle frame 32T 32T 16 3rd Cycle frame 4th Cycle frame 32T 32T 16 1T 5th Cycle frame 32T 16 1T 6th Cycle frame 7th Cycle frame 8th Cycle frame 32T 32T 32T 16 16 1T (Narrow pulse inserted by NP0[2:0]=3) PWM clock= 1/T= Fosc / 2^(PDIV+1) The SPWM output cycle frame frequency = SPWM clock/32 = [Fosc/2^(PDIV+1)]/32 If Fosc = 20MHz, PDCK[1:0] of PWMC = #03H, then PWM clock = 20MHz/2^4 = 20MHz/16 = 1.25MHz. PWM output cycle frame frequency = (20MHz/2^4)/32 = 39.1 kHz. 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 38 VRS1100 VERSA Datasheet Rev 1.1 Crystal consideration The crystal connected to the VRS1100 oscillator input should be of a parallel type, operating in fundamental mode. The user should check the specific crystal or ceramic resonator technical literature available or contact the manufacturer to select the appropriate values for the external components. The following table shows the value of capacitors and feedback resistor that must be used at different operating frequencies. Valid for VRS1100 XTAL 3MHz C1 30 pF C2 30 pF R open XTAL C1 C2 R 16MHz 30 pF 30 pF open XTAL1 XTAL 6MHz 30 pF 30 pF open 9MHz 30 pF 30 pF open 12MHz 30 pF 30 pF open 25MHz 15 pF 15 pF 62K 33MHz 5 pF 5 pF 6.8K 40MHz 2 pF 2 pF 4.7K VRS1100 R XTAL2 C1 C2 Note: Oscillator circuits may differ with different crystals or ceramic resonators in higher oscillation frequency. Crystals or ceramic resonator characteristics vary from one manufacturer to the other. 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 39 VRS1100 VERSA Datasheet Rev 1.1 Operating Conditions TABLE 44: OPERATING CONDITIONS Symbol TA TS VCC5 Fosc 40 Description Operating temperature Storage temperature Supply voltage Oscillator Frequency Min. -40 -55 4.5 3.0 Typ. 25 25 5.0 - Max. +85 155 5.5 40 Unit C C V MHz Remarks Ambient temperature under bias For 5V application DC Characteristics TABLE 45: DC CHARACTERISTICS Symbol VIL1 VIL2 VIH1 VI H2 VOL1 VOL2 Parameter Input Low Voltage Input Low Voltage Input High Voltage Input High Voltage Output Low Voltage Output Low Voltage Valid P o r t 0 ,1,2,3,4,#EA RES, XTAL1 P o r t 0,1,2,3,4,#EA RES, XTAL1 Port 0, ALE, #PSEN P o r t 1,2,3,4 VOH1 Output High Voltage Port 0 VOH2 Output High Voltage Port 1,2,3,4,ALE,#PSEN IIL Logical 0 Input Current ITL ILI R RES C -10 Logical Transition Current Input Leakage Current Reset Pull-down Resistance Max. 1.0 0.8 VCC+0.5 VCC+0.5 0.45 0.45 Unit V V V V V V V V V V Test Conditions VCC=5V VCC=5V VCC=5V VCC=5V IOL=3.2mA IOL=1.6mA IOH=-800uA IOH=-80uA IOH=-60uA IOH=-10uA P o r t 1,2,3,4 -75 uA Vin=0.45V P o r t 1,2,3,4 -650 uA Vin=2.OV P o r t 0, #EA +10 uA 0.45V<Vin<VCC 300 Kohm 10 pF Fre=1 MHz, Ta=25C mA mA mA mA mA mA uA Active mode, 40MHz Active mode 25MHz Active mode 16MHz Idle mode, 40MHz Idle mode 25MHz Idle mode, 16MHz Power down mode RES Pin Capacitance Min. -0.5 0 2.0 70% VCC 2.4 90%VCC 2.4 90% VCC 50 20 IC C Power Supply Current VDD 6.5 50 FIGURE 24: ICC ACTIVE MODE TEST CIRCUIT Vcc Vcc Icc RST VCC PO EA 8 VRS1100 (NC) XTAL2 Clock Signal XTAL1 VSS 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 40 VRS1100 VERSA Datasheet Rev 1.1 AC Characteristics TABLE 46: AC CHARACTERISTICS Symbol T LHLL T AVLL T LLAX T LLIV T LLPL T PLPH T PLIV T PXIX T PXIZ T AVI V T PLAZ T RLRH T WLWH T RLDV T RHDX T RHDZ T LLDV T AVDV T LLYL T AVYL T QVWH T QVWX T WHQX T RLAZ T YALH T CHCL T CLCX T CLCH T CHCX T , T C LCL Parameter ALE Pulse Width Address Valid to ALE Low Address Hold after ALE Low ALE Low to Valid Instruction In ALE Low to #PSEN low #PSEN Pulse Width #PSEN Low to Valid Instruction In Instruction Hold after #PSEN Instruction Float after #PSEN Address to Valid Instruction In #PSEN Low to Address Float #RD Pulse Width #WR Pulse Width #RD Low to Valid Data In Data Hold after #RD Data Float after #RD ALE Low to Valid Data In Address to Valid Data In ALE low to #WR High or #RD Low Address Valid to #WR or #RD Low Data Valid to #WR High Data Valid to #WR Transition Data Hold after #WR #RD Low to Address Float #W R or #RD High to ALE High Clock Fall Time Clock Low Time Clock Rise Time Clock High Time Clock Period Valid Cycle RD/WRT RD/WRT RD/WRT RD RD RD RD RD RD RD RD RD WRT RD RD RD RD RD RD/WRT RD/WRT WRT WRT WRT RD RD/WRT Fosc 16 Min. 115 43 53 Type Max. Variable Fosc Min. 2xT - 10 T - 20 T - 10 Type 240 53 173 4xT - 10 T - 10 3xT - 15 177 0 3xT -10 0 87 292 10 365 365 T + 25 5xT - 20 10 6xT - 10 6xT - 10 302 0 178 230 403 38 73 53 63 Max. 5xT - 10 0 145 590 542 197 72 2xT + 20 8xT - 10 9xT - 20 3xT + 10 3xT - 10 4xT - 20 7xT - 35 T - 25 T + 10 5 T+10 T -10 1/fosc 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com Unit nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS 41 VRS1100 VERSA Datasheet Rev 1.1 Data Memory Read Cycle Timing The following timing diagram shows what occurs at each signal during a Data Memory Read Cycle. FIGURE 25: DATA MEMORY READ CYCLE TIMING T12 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T1 T2 T3 OSC 1 ALE 2 #PSEN 5 #RD 7 3 ADDRESS A15-A8 PORT2 3 PORT0 INST in Float A7-A0 4 6 Float 8 Data in Float ADDRESS or Float 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 42 VRS1100 VERSA Datasheet Rev 1.1 Program Memory Read Cycle Timing The following timing diagram shows what occurs at each signal during a Program Memory Read Cycle. FIGURE 26: PROGRAM MEMORY READ CYCLE T12 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T1 T2 T3 OSC ALE 1 2 5 #PSEN 7 #RD,#WR 3 ADDRESS A15-A8 PORT2 PORT0 Float 3 4 6 A7-A0 Float INST in ADDRESS A15-A8 8 Float A7-A0 Float INST in Float 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 43 VRS1100 VERSA Datasheet Rev 1.1 Data Memory Write Cycle Timing The following timing diagram shows what occurs at each signal during a Data Memory Write Cycle. FIGURE 27: DATA MEMORY WRITE CYCLE TIMING T12 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T1 T2 T3 OSC ALE 1 #PSEN 6 5 #WR 2 ADDRESS A15-A8 PORT2 2 PORT0 INST in Float A7-A0 3 4 Data out ADDRESS or Float 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 44 VRS1100 VERSA Datasheet Rev 1.1 I/O Ports Timing The following timing diagram shows what occurs during I/O Port Timing. FIGURE 28: I/O PORTS TIMING T7 T8 T9 T10 T11 T12 T1 T2 T3 T4 T5 T6 T7 T8 X1 Sampled Inputs P0,P1 Sampled Inputs P2,P3 Output by Mov Px, Src RxD at Serial Port Shift Clock Mode 0 Current Data Next Data Sampled 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 45 VRS1100 VERSA Datasheet Rev 1.1 Timing Requirement of the External Clock (VSS = 0v is assumed) FIGURE 29: TIMING REQUIREMENT OF EXTERNAL CLOCK (VSS= 0.0V IS ASSUMED) TCLCL Vdd - 0.5V 0.45V 70% Vdd 20% Vdd-0.1V TCLCX TCHCX TCHCL TCLCH External Program Memory Read Cycle The following timing diagram shows what occurs at each signal during an External Program Memory Read Cycle. FIGURE 30: EXTERNAL PROGRAM MEMORY READ CYCLE TPLPH #PSEN TLLPL ALE TLHLL TAVLL PORT 0 TPXIZ TLLAX A0-A7 TPLIV TPLAZ TPXIX Instruction IN A0-A7 TAVIV PORT2 P2.0-P2.7 or AB-A15 from DPH A8-A15 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 46 VRS1100 VERSA Datasheet Rev 1.1 External Data Memory Read Cycle The following timing diagram shows what occurs at each signal during an External Data Memory Read Cycle. FIGURE 31: EXTERNAL DATA MEMORY READ CYCLE #PSEN TYHLH ALE TLLDV TRLRH TLLYL #RD TAVLL PORT 0 TRLDV TLLAX TRLAZ A0-A7 From Ri or DPL TRHDZ TRHDX DATA IN A0-A7 From PCL INSTRL IN TAVYL TAVDV PORT 2 P2.0-P2.7 or A8 -A15 from DPH A8-A15 from PCH 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 47 VRS1100 VERSA Datasheet Rev 1.1 External Data Memory Write Cycle The following timing diagram shows what occurs at each signal during an External Data Memory Write Cycle. FIGURE 32: EXTERNAL DATA MEMORY WRITE CYCLE #PSEN TYHLH ALE TLHLL TLLYL #WR TAVLL TWLWH TQVWX TWHQX TLLAX TQVWH PORT 0 A0-A7 From Ri or DPL DATA OUT A0-A7 From PCL INSTRL IN TAVYL PORT 2 P2.0-P2.7 or A8-A15 from DPH A8-A15 from PCH . 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 48 VRS1100 VERSA Datasheet Rev 1.1 Plastic Chip Carrier (PLCC) VRS1100 L E GE HE Y D A2 HD A A1 TABLE 47: DIMENSIONS OF PLCC-44 CHIP CARRIER C e b1 b GD Note: 1. Dimensions D & E do not include interlead Flash. 2. Dimension B1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inch 4. General appearance spec should be based on final visual inspection spec. Symbol A Al A2 bl b C D E e GD GE HD HE L y Dimension in inch Minimal/Maximal -/0.185 0.020/0.145/0.155 0.026/0.032 0.016/0.022 0.008/0.014 0.648/0.658 0.648/0.658 0.050 BSC 0.590/0.630 0.590/0.630 0.680/0.700 0.680/0.700 0.090/0.110 -/0.004 / Dimension in mm Minimal/Maximal -/4.70 0.51/ 3.68/3.94 0.66/0.81 0.41/0.56 0.20/0.36 16.46/16.71 16.46/16.71 1.27 BSC 14.99/16.00 14.99/16.00 17.27/17.78 17.27/17.78 2.29/2.79 -/0.10 / 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 49 VRS1100 VERSA Datasheet Rev 1.1 C Plastic Quad Flat Package (QFP) L L1 S S 2 VRS1100 D2 D1 D R1 b A2 Gage Plane 0.25mm A1 3 R2 A E2 E1 E TABLE 48: DIMENSIONS OF QFP-44 CHIP CARRIER Symbol e1 Seating Plane e Note: 1. Dimensions D1 and E1 do not include mold protrusion. 2. Allowance protrusion is 0.25mm per side. 3. Dimensions D1 and E1 do not include mold mismatch and are determined datum plane. 4. Dimension b does not include dambar protrusion. 5. Allowance dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the lead foot. C A Al A2 b c D D1 D2 E E1 E2 e L L1 R1 R2 S 0 1 2 3 C Dimension in in. Minimal/Maximal -/0.100 0.006/0.014 0.071 / 0.087 0.012/0.018 0.004 / 0.009 0.520 BSC 0.394 BSC 0.315 0.520 BSC 0.394 BSC 0.315 0.031 BSC 0.029 / 0.041 0.063 0.005/0.005/0.012 0.008/0/7 0/ 10 REF 7 REF 0.004 Dimension in mm Minimal/Maximal -/2.55 0.15/0.35 1.80/2.20 0.30/0.45 0.09/0.20 13.20 BSC 10.00 BSC 8.00 13.20 BSC 10.00 BSC 8.00 0.80 BSC 0.73/1.03 1.60 0.13/0.13/0.30 0.20/as left as left as left as left 0.10 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 50 VRS1100 VERSA Datasheet Rev 1.1 Ordering Information Device Number Structure VRS abc -X Y Z FF Operating Frequency 40: 40MHz oscillator frequency Temperature Range I: Industrial ( -40C to +85C ) Operating Voltage A: 4.5V - 5.5V Package Options P: PLCC-44 pins Q: QFP-44 pins D; DIP-40pins Product Number 1100 - 64K Program + 64K Data Flash & 1K RAM Device Family VRS: VERSA MCU VRS1100 Ordering Options (No ISPV2 Firmware programming) Device Number VRS1100-PAI40 VRS1100-QAI40 VRS1100-DAI40 Flash Size RAM Size Package Option Voltage Temperature Frequency 64K 64K 64K 1K 1K 1K PLCC-44 QFP-44 DIP-40 4.5V to 5.5V 4.5V to 5.5V 4.5V to 5.5V -40C to +85C -40C to +85C -40C to +85C 40MHz 40MHz 40MHz VRS1100 Ordering Options (With ISPV2 Firmware preprogrammed) Device Number Flash Size RAM Size Package Option Voltage Temperature Frequency VRS1100-PAI40-ISPV2 VRS1100-QAI40-ISPV2 VRS1100-DAI40-ISPV2 64K 64K 64K 1K 1K 1K PLCC-44 QFP-44 DIP-40 4.5V to 5.5V 4.5V to 5.5V 4.5V to 5.5V -40C to +85C -40C to +85C -40C to +85C 40MHz 40MHz 40MHz Disclaimers Right to make change - Goal Semiconductor reserves the right to make changes to its products - including circuitry, software and services - without notice at any time. Customers should obtain the most current and relevant information before placing orders. Use in applications - Goal Semiconductor assumes no responsibility or liability for the use of any of its products, and conveys no license or title under any patent, copyright or mask work right to these products and makes no representations or warranties that these products are free from patent, copyright or mask work right infringement unless otherwise specified. Customers are responsible for product design and applications using Goal Semiconductor parts. Goal Semiconductor assumes no liability for applications assistance or customer product design. Life support - Goal Semiconductor products are not designed for use in life support systems or devices. Goal Semiconductor customers using or selling Goal products for use in such applications do so at their own risk and agree to fully indemnify Goal Semiconductor for any damages resulting from such applications. 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 51