DS062 (v3.0) February 8, 2000 www.xilinx.com 1
Preliminary Product Specification 1-800-255-7778
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Features
XQ1701L/XQR1701L
QM L C e rt if ie d
Configuration one-time programmable (OTP) read-only
memory designed to store configuration bitstreams of
Xilinx FP GA d evice s
Simple interface to the FPGA; require s only one user
I/O p i n
Cascadable for storing longer or multiple bitstreams
Programmable reset pola rity (active High or active
Low) for c om patibility with different FPGA solutions
Supports XQ4000XL/V irtex fast conf iguration mode
(15.0 MHz)
Available in 44-pin cera mic LCC (M grade ) package
Available in 20-pin SOIC package (XQ1701L only)
Programming support by leading programmer
manufacturers.
Design support using the Xilinx Alliance and
Found ation ser ies software packages.
XQR1701 L (only)
Fabricated on Epitaxial Silicon to improve latch
performance (parts are immune to Single Event
Latch-up)
Single Event Bit Upset immune
Total Dose tolerance in excess of 50K rads(Si)
All lots subjected to TID Lot Qualification in accordance
with method 1019 (dose rate ~9.0 rads(Si)/sec )
XQ1701 L (only)
Also av ai l abl e under the f ollo wing Standard Microcircuit
Drawing (SMD): 5962-9951401. For more information
contact hte Defense Supply Cent er Columbus (DSCC):
http://www.dscc.dla.mil/Programs/Smcr/
Description
The QPRO series XQ1701 L are X ili nx 3.3V hi gh-density
configuration PROMs. The XQR1701L are radiation hard-
ened. These de vices are manufactured on Xilinx QML certi-
fied manufacturing lines utilizing epitaxial substrates and
TID lot qualification (per method 1019).
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after the rising clock edge, data appears on the PROM
DATA output pin t hat is connected to the FPGA DIN pin. The
FP GA generate s the ap propri ate number of clock pulses to
complete the configuration. Once configured, it disabl es the
PROM. When the FPGA is in Slav e Serial mode, the PROM
and the FPGA must both be clocked by an incoming signal.
Figure 1 shows a simplied block diagram.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded wit h other members of the family.
Fo r device programmi ng, either the Xilinx Allianc e or Foun-
dation series development system compiles the FPGA
design f ile into a s tan dard Hex for mat, which is then trans-
ferred to most comm ercial PROM programmers.
0QPRO Series Configuration
PROMs (XQ) including
Radiation -Hardened Series (XQR)
DS062 (v3.0) February 8, 2000 02Preliminary Product Speci fication
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QPRO Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR)
2www.xilinx.com DS062 (v3. 0) February 8, 2000
1-800-255-7778 Preliminary Product Specification
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Pin Description
DATA
Data output is in a high-impedance state when either CE or
OE are inactive. Dur ing programming, the DATA pin is I/O.
Note that OE can be progr ammed to be ei ther active Hi gh or
active Low.
CLK
Each rising edge on the CLK input increments the internal
address counter, if both CE and OE are active.
RESET/OE
When High, t his input hol ds the ad dress counter res et and
puts the DATA outp ut in a high-impedance state. The polar-
ity of this input pin is progr ammable as either RESET/OE or
OE/RESET. To avoid confusion, this document describes
th e pin as RESET/OE, although the opposite polarity is pos-
sible on all devices. When RESET is active, the address
counter is held at "0", and puts the DATA output in a
high-impedanc e sta te. The polarity of this input is program-
mable. The default is active High RESET, but the preferred
option is active Low RE SET, because it can be driven by the
FPGA s INIT pin.
The polarity of this pin is controlled in the programmer inter-
face. This input pin is easily inverted using the Xilinx
HW-130 Programmer. Third-party programmers have differ-
ent methods to invert this pin.
CE
When High, this pin disables the internal address counter,
puts the DATA output in a high-impedance state, and forces
the device into low-ICC standby mode.
CEO
Chip Enable output, to b e con nected to the CE input of the
next PROM i n the daisy chain. This out put is Low when the
CE and OE inputs are both active AND the inte rnal address
counter has been incremented beyond its Terminal Count
(TC) value. In other words: when the PROM has been read,
CEO wi ll follo w CE as lon g as OE is acti ve. When OE goes
i n a c tive , C EO sta ys High until the PROM is reset. Note that
OE can be programmed to be either active High or active
Low.
VPP
Programming voltage. No overshoot above the specified
max voltage is per m it ted on this pin. For norma l read oper-
ation, this pin must be connected to VCC. Failure to do so
may lead to unpredictable, temperature-dependent opera-
tion and severe problems in circuit debug ging. Do not leave
VPP floating!
VCC and GND
Positive su pply and groun d pins.
Figure 1: Simplified Block Diagram (does not show program ming circuit)
EPROM
Cell
Matrix
Address Counter
CE
DATA
OE
Output
CLK
VCC VPP GND
DS027_01_021500
TC
OE
RESET/
OE/
RESET
or CEO
QPRO Series Configuratio n PROMs (XQ) including Radiation-Hardened Series (XQR)
DS062 (v3.0) February 8, 2000 www.xilinx.com 3
Preliminary Product Specification 1-800-255-7778
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PROM Pinouts
Capacity
Xilinx FPGAs and Compatible PROMs.
Controlling PROMs
Connecting the FPGA device with the PROM.
The DATA output(s) of the of the PROM(s) drives the
DIN input of the lead FPGA device.
The Master FPGA CCLK output drives the CLK input(s)
of the PROM(s).
The CEO output of a PROM dri ves the CE input of the
next PROM in a daisy chain (if any).
The RESET/OE input of all PROMs is best driven by
the INIT output of the lead FPGA device. This
connection assures that the PROM address counter is
reset before the start of any (re)configuration, even
when a reconfiguration is initiated by a VCC glitch.
Other methodssuch as driving RESET/O E fr om LD C
or system resetassume the PROM internal
power-on-reset is always in step with the FPGAs
internal power-on-reset. This may not be a safe
assumption.
The PROM CE input can be driven from either the LDC
or DONE pins. Using LDC avoids potential contention
on the DIN pin.
The CE input of the lead (or only) PROM is driven by
the DONE output of the lead FPGA device, provided
that DONE is not permanently grounded. Otherwise,
LDC can be used to drive CE, but must then be
unconditionally High during user operation. CE can
also be pe rmane ntly tied Low, but this keeps the DATA
output active and causes an unnecessary supply
current of 10 mA maximum.
FPGA Master Se rial Mode Summary
The I /O and logic func tions of the Configurable Log ic Block
(CLB) and their associated interconnections are established
by a configuration program. The program is loaded either
automatically upon power up, or on command, depending
on the stat e of the three F PG A mode pins. In Master Seria l
mode, the FPGA automatically loads the configuration pro-
gram from an external memory. The Xilinx PROMs have
been designed for compatibility with the Master Serial
mode.
Upon power-up or reconfiguration, an FPGA enters the
Master Serial mode whenever all three of the FPGA
mode-select pins are Low (M0=0, M1=0, M2=0). Data is
read from the PROM sequentially on a single data line. Syn-
chronization is provided by the rising edge of the temporary
signal CCLK, which is generated during configuration.
Master Serial Mode provides a simple configuration inter-
face. Only a serial data line and two control lines are
required to configure an FPGA. Data from the PROM is
read sequenti ally, accessed via the internal address and bit
coun ters which a re increment ed on ever y valid risin g edge
of CCLK.
If the user-programmable, dual-function DIN pin on the
FPGA is used only for configuration, it m ust still be held at a
defined level during normal operation. The Xilinx FPGA
families take care of this automatically with an on-chip
default pull-up resistor.
Pin Name 44-Pin CLCC
DATA 2
CLK 5
RESET/OE (OE/RESET)19
CE 21
GND 3, 24
CEO 27
VPP 41
VCC 44
Devices Co nf i gu ra ti on B i ts
XQR1701L 1,048,576
XQ1701L 1,048,576
De vice Configuration Bits XQ(R)1701L
PROMs
XQ(R)4013XL 393,632 1
XQ(R)4036XL 832,528 1
XQ(R)4062XL 1,433,864 2
XQ(R)4013XL 393,632 1
XQ(R)4036XL 832,528 1
XQ(R)4062XL 1,433,864 2
XQV(R)300 1,751,840 2
XQV(R)600 3,608,000 4
XQV(R)1000 6,127,776 6
QPRO Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR)
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1-800-255-7778 Preliminary Product Specification
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Programming the FPGA With Counters
Unchanged Upon Completion
When multiple FPGA-configurations for a sin gle FPGA are
stored in a PROM, the OE pin should be tied Low. Upon
power-up, the inter nal address count ers are reset and con-
figuration begins with the first program stored in memory.
Since the OE pin is held Low, the address c oun ters are left
unchanged after configuration is complete. Therefore, to
reprogram the FPGA with another program , the DONE l ine
is pulled Low and configuration begins at the last value of
the address counters.
This method f ails if a user applies RESET during the FPGA
configuration process. The FPGA aborts the configuration
and then re star ts a new configuration, as intended , but the
PROM does not reset its address counter, since it never
saw a High level on its OE input. The new configuration,
therefore, reads the rema ining data in the PROM and inter-
prets it as preamble, length count etc. Since the FPGA is
the master , it issues the necessary number of CCLK pulses,
up to 16 million (224) and DONE goes High. However, the
FPGA configuration will be completely wrong, with potential
contentions inside the FPGA and on its output pins. This
method must, therefore, never be used when there is any
chance of external reset during configuration.
Cascading Configuration PROMs
For multiple FPGAs configured as a daisy-chain, or for
future FPGAs requiring larger configuration memories, cas-
cade d PROM s provide additiona l memory. After the last bit
from the first PROM is read, the next clock signal to the
PROM asserts its CEO output Low and disables its DATA
line. The second PROM recognizes the Low level on its CE
input and enables its DATA output. See Figure 2.
After configuration is complete, the address counters of all
cascaded PROMs are reset if the FPGA RESET pin goes
Low, assuming the PROM reset polarity option has been
inverted.
To reprogram the FPGA with another program, the DONE
line g oes Low and c onfiguration begins where the address
counters had stopped. In this case, avoid contention
between DATA and the configur ed I/O use of DIN.
QPRO Series Configuratio n PROMs (XQ) including Radiation-Hardened Series (XQR)
DS062 (v3.0) February 8, 2000 www.xilinx.com 5
Preliminary Product Specification 1-800-255-7778
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Figure 2: Master Serial Mode. The one-time-programmable PR OM supports automatic loading of configuration programs.
Multiple devices can be cascaded to support additional FPGAs. An early DONE inhibits the PROM data output one CCLK
cycle before the FPGA I/Os become active.
DIN
DOUT
CCLK
INIT
DONE
PROM
DATA
CLK
CE CE
FPGA
(Low Resets the Address Pointer)
* For mode pin connections,
refer to the appropriate FPGA data sheet.
Vcc
VCC
VCC
OPTIONAL
Daisy-chained
FPGAs with
Different
configurations
OPTIONAL
Slave FPGAs
with Identical
Configurations
RESET RESET
DS027_02_060100
CCLK
(Output)
DIN
DOUT
(Output)
OE/RESET
MODES*
VPP
VPP
Cascaded
Serial
Memory
DATA
CLK
CEO
OE/RESET
3.3V
4.7K
QPRO Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR)
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1-800-255-7778 Preliminary Product Specification
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Standby Mode
The PROM enters a low-pow er standby mode whenev er CE
is asser ted High. The output remains in a high-impedance
state regardless of the state of the OE input.
Programming
The devices ca n be program m ed on programm ers supplied
by Xilinx or qualified third-party vendors. The user must
ensure that the appropriate programming algorithm and the
latest version of the programmer software are used. The
wrong choice can permanently dam age the device.
Radiation Characteristics (XQR1701L only)
Table 1: Truth Table for Control Inputs
Cont r ol Inputs
Internal Address
Outputs
RESET CE DATA CEO ICC
Inactive Low If address < TC(1): increment
If address > TC(1): dont change Active
High-Z High
Low Active
Reduced
Active Low He ld reset High-Z High Active
Inactive H igh Not changing High-Z High Standby
Active H igh Held reset Hi gh-Z High Standby
Notes:
1. The XC1700 RESET input has programm able pola rity
1. TC = Terminal Count = highest addres s value. TC + 1 = address 0.
Symbol Description Min Max Units
TID To tal ionizing dose, Method 1019 50K rads(Si)
SEL Single event latc h-up.
Heavy ion saturation cross section, LET1 > 120 MeV cm2/mg 0(cm
2/Device)
SEU Sing le event bit up se t.
Heavy ion sa tura tion cross secti o n
LET > 120 MeV cm2/mg
0(cm
2/Bit)
SEFI2Single event fun ction al interupt,
Heavy ion saturation cross section ,
10% saturated intercept at LET = 6.0 MeV cm2/mg
1.2e-5 (cm2/Device)
Notes:
1. Single Event Effects testing was perform ed with heavy ion to a maximum LET of 120 MeV-cm2/mg.
QPRO Series Configuratio n PROMs (XQ) including Radiation-Hardened Series (XQR)
DS062 (v3.0) February 8, 2000 www.xilinx.com 7
Preliminary Product Specification 1-800-255-7778
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Absolute Maximu m Ratings
Operating Conditions
DC Char ac te ri sti cs Ove r Op er at ing Con ditio n
Symbol Description Conditions Units
VCC Suppl y voltage relative to GND 0.5 to +4.0 V
VPP Supply volt age relative to GND 0 .5 to +12.5 V
VIN Input voltage relativ e to GND 0.5 to VCC +0.5 V
VTS Voltage applied to High-Z output 0.5 to VCC +0.5 V
TSTG Storage temperature (ambient) 65 to +150 °C
TSOL Max imum solder ing tempe rature (10s @ 1/16 in.) +260 °C
Notes:
1. Stresses beyond those l isted under Abs olute Maximum Rati ngs may cause permanent damage to the device . These are str ess
ratings onl y, and function al operation of the device at these or any other conditions beyond those list ed under O perati ng Conditions
is not imp lied. Exposure to Absolute Maxim um Ratings condition s for extended pe riod s of ti m e may affec t device reliabili ty.
Symbol Description Min Max Units
VCC(1) Supply voltage relative to GND
cer a mic p ackage (TC = 55°C to +125°C)
plastic package (TJ = 55°C to +125°C)
Military 3.0 3.6 V
Notes:
1. During normal read operatio n VPP MUST be connected to VCC.
Symbol Description Min Max Units
VIH High-level input voltage 2 VCC V
VIL Low-level input voltage 0 0.8 V
VOH High-lev el output voltage (IOH = 3 mA) 2.4 - V
VOL Lo w-le vel output voltage (IOL = +3 m A) - 0.4 V
ICCA Supply current, active mo de (at maximum frequen cy) - 10 mA
ICCS Supply current, standby m ode (XQ1701L) - 100 µA
ICCS(1) Supply c urrent, standby mode
(XQR1701L ) Pre-rad (TID) - 300 µA
Post-rad (TID) - 3 mA
ILInput or outp ut leakage current 10 10 µA
CIN Input capacitance (VIN = GND, f = 1.0 MHz) - 10 pF
COUT O utput capacita nce (VIN = GND, f = 1.0 MHz) - 10 pF
Notes:
1. ICCS, Standby Current is measured at +125°C for pre- radiation specifi cations and at room temperatur e for post-rad iat ion
specifications.
QPRO Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR)
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1-800-255-7778 Preliminary Product Specification
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AC Characteristics Over Operating Condition
Symbol Description
XQ(R)1701L
UnitsMin Max
TOE OE to data delay - 30 ns
TCE CE to data delay - 45 ns
TCAC CLK to data d elay - 45 ns
TDF CE or O E to data float delay(2,3) -50ns
TOH Data hold from CE, O E, or C L K(3) 0-ns
TCYC Clock periods 67 - ns
TLC CLK Low time (3) 25 - ns
THC CLK High time(3) 25 - ns
TSCE CE setup time to CL K (to guarantee proper counting) 25 - ns
THCE CE hold tim e to CLK (to guarantee proper counting) 0 - ns
THOE OE hold time (guarantees counte rs are reset) 25 - ns
Notes:
1. A C test load = 50 pF
2. Float delays are measured with 5 pF AC lo ads. Tra nsition is mea sured at ±200 mV from stea dy state active levels.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.
RESET/OE
CE
CLK
DATA TCE
TOE
TLC
TSCE TSCE THCE
THOE
TCAC TOH TDF
TOH
THC
DS027_03_021500
TCYC
QPRO Series Configuratio n PROMs (XQ) including Radiation-Hardened Series (XQR)
DS062 (v3.0) February 8, 2000 www.xilinx.com 9
Preliminary Product Specification 1-800-255-7778
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AC Characteristics Over Operating Condition When Cascading
Symbol Description Min Max Units
TCDF CLK to data float delay(2,3) -50 ns
TOCK CLK to CEO delay(3) -30 ns
TOCE CE to C EO delay(3) -35 ns
TOOE RESET/OE to CEO delay(3) -30 ns
Notes:
1. A C test load = 50 pF
2. Float delays are measured with 5 pF AC lo ads. Tra nsition is mea sured at ±200 mV from stea dy state active levels.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.
RESET/OE
CLK
DATA
CE
TOOE
CEO
First Bit Last Bit
TOCE
TOCK
TCDF
DS027_04_021500
TOCE
QPRO Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR)
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Ordering Information
Valid Ordering Combinations
Revision History
The following table shows the revision histor y for this docum ent.
XQ1701LCC44M XQR1701LCC44M
XQ1701LSO20N
XQR1701L CC44 M
Opera t ing Range/ P rocessing
M = Military (TC = 55° to +12 5 °C)
QML certified to MIL-PRF-38535
N = Military Plastic (TJ = 55° to +125°C)
Dev ice Num ber
XQ1701L
XQR1701L Package T ype
CC44 = 44-pin Ceramic Chip Carrier
SO20 = 20-pin Plastic Small Outline Package
5962 9951401 Q Y A
Lead F inish
A = So lder Dip
B = Solder Plate
Generic Standard
Microcircuit Drawing
(SMD)
Device Type
XQ1701L Packag e Type
Y = 44-pin Ceramic Chip Carrier
X = 2 0- pin P las ti c S mall Out lin e Package
QM L C erti fied
Date Version Revision
04/20/00 1.0 Initial Release
06/01/00 2.0 Combined XQR17 00L Rad-Hard and X Q1701 L devices, added XQ17 04L and updated
format.
02/08/01 3.0 Removed th e XQ1 704L and XQR1704L