TMP102AIDRLR - Texas Instruments

FEATURES DESCRIPTION

APPLICATIONS

Diode

Temp.

Sensor

A/D

Converter

OSC

Control

Logic

Serial

Interface

Config.

andTemp.

TMP102

Temperature

SCL 1

ALERT

SDA

GND 2 5 V+

ADD0

TMP102

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............................................................................................................................................... SBOS397B – AUGUST 2007 – REVISED OCTOBER 2008

Low Power Digital Temperature SensorWith SMBus™/Two-Wire Serial Interface in SOT563

•TINY SOT563 PACKAGE

The TMP102 is a two-wire, serial output temperaturesensor available in a tiny SOT563 package. Requiring•ACCURACY: 0.5 ° C ( – 25 ° C to +85 ° C)

no external components, the TMP102 is capable of•LOW QUIESCENT CURRENT:

reading temperatures to a resolution of 0.0625 ° C.10 µA Active (max)

The TMP102 features SMBus and two-wire interface1µA Shutdown (max)

compatibility, and allows up to four devices on one•SUPPLY RANGE: 1.4V to 3.6V

bus. It also features an SMB alert function.•RESOLUTION: 12 Bits

The TMP102 is ideal for extended temperature•DIGITAL OUTPUT: Two-Wire Serial Interface

measurement in a variety of communication,computer, consumer, environmental, industrial, andinstrumentation applications. The device is specified•PORTABLE AND BATTERY-POWERED

for operation over a temperature range of – 40 ° C toAPPLICATIONS

+125 ° C.•POWER-SUPPLY TEMPERATUREMONITORING

•COMPUTER PERIPHERAL THERMALPROTECTION

•NOTEBOOK COMPUTERS•BATTERY MANAGEMENT

•OFFICE MACHINES•THERMOSTAT CONTROLS•ELECTROMECHANICAL DEVICETEMPERATURES

•GENERAL TEMPERATURE MEASUREMENTS:Industrial ControlsTest Equipment

Medical Instrumentations

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2SMBus is a trademark of Intel, Inc.3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Copyright © 2007 – 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

ABSOLUTE MAXIMUM RATINGS

(1)

PIN CONFIGURATION

SDA

V+

ADD0

SCL

GND

ALERT

CBZ

TMP102

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION

(1)

PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR PACKAGE MARKING

TMP102 SOT563 DRL CBZ

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIweb site at www.ti.com .

PARAMETER TMP102 UNIT

Supply Voltage 3.6 VInput Voltage

(2)

– 0.5 to +3.6 VOperating Temperature – 55 to +150 ° CStorage Temperature – 60 to +150 ° CJunction Temperature +150 ° CHuman Body Model (HBM) 2000 VESD Rating Charged Device Model (CDM) 1000 VMachine Model (MM) 200 V

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods maydegrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyondthose specified is not supported.(2) Input voltage rating applies to all TMP102 input voltages.

DRL Package

SOT563

Top View

Product Folder Link(s): TMP102

ELECTRICAL CHARACTERISTICS

TMP102

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............................................................................................................................................... SBOS397B – AUGUST 2007 – REVISED OCTOBER 2008

At T

= +25 ° C and V

= +1.4V to +3.6V, unless otherwise noted.

TMP102

PARAMETER CONDITIONS MIN TYP MAX UNIT

TEMPERATURE INPUT

Range – 40 +125 ° C

Accuracy (Temperature Error) – 25 ° C to +85 ° C 0.5 2 ° C

– 40 ° C to +125 ° C 1 3 ° C

vs Supply 0.2 0.5 ° C/V

Resolution 0.0625 ° C

DIGITAL INPUT/OUTPUT

Input Logic Levels:

0.7 (V+) 3.6 V

– 0.5 0.3 (V+) V

Input Current I

0 < V

< 3.6V 1 µA

Output Logic Levels:

SDA V+ > 2V, I

= 3mA 0 0.4 V

V+ < 2V, I

= 3mA 0 0.2 (V+) V

ALERT V+ > 2V, I

= 3mA 0 0.4 V

V+ < 2V, I

= 3mA 0 0.2 (V+) V

Resolution 12 Bit

Conversion Time 26 35 ms

Conversion Modes CR1 = 0, CR0 = 0 0.25 Conv/s

CR1 = 0, CR0 = 1 1 Conv/s

CR1 = 1, CR0 = 0 (default) 4 Conv/s

CR1 = 1, CR0 = 1 8 Conv/s

Timeout Time 30 40 ms

POWER SUPPLY

Operating Supply Range +1.4 +3.6 V

Quiescent Current I

Serial Bus Inactive, CR1 = 1, CR0 = 0 (default) 7 10 µA

Serial Bus Active, SCL Frequency = 400kHz 15 µA

Serial Bus Active, SCL Frequency = 3.4MHz 85 µA

Shutdown Current I

Serial Bus Inactive 0.5 1 µA

Serial Bus Active, SCL Frequency = 400kHz 10 µA

Serial Bus Active, SCL Frequency = 3.4MHz 80 µA

TEMPERATURE RANGE

Specified Range – 40 +125 ° C

Operating Range – 55 +150 ° C

Thermal Resistance, SOT563 θ

260 ° C/W

Product Folder Link(s): TMP102

TYPICAL CHARACTERISTICS

Temperature( C)°

-60 -20 40 60 140 160

I (mA)

3.6VSupply

-40 0 20 80 100 120

1.4VSupply

Temperature( C)°

-60 -40 0 40 140 160

I (mA)

3.6VSupply

1.4VSupply

-20 20 60 80 100 120

Temperature( C)°

-60 -20 40 60 140 160

ConversionTime(ms)

3.6VSupply

1.4VSupply

-40 200 80 100 120

100

BusFrequency(Hz)

1k 10k 100k 1M 10M

I ( A)m

- °55 C

+25 C°

+125 C°

2.0

1.5

1.0

0.5

-0.5

-1.0

-1.5

-2.0

Temperature( C)°

-60 -40 40 60 140 160

TemperatureError( C)°

-20 200 80 100 120

-0.45

-0.35

-0.25

-0.15

-0.05

0.05

0.15

0.25

0.35

0.45

TemperatureError( C)°

Population

TMP102

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At T

= +25 ° C and V+ = 3.3V, unless otherwise noted.

QUIESCENT CURRENT vs TEMPERATURE(4 Conversions per Second) SHUTDOWN CURRENT vs TEMPERATURE

Figure 1. Figure 2.

QUIESCENT CURRENT vs BUS FREQUENCYCONVERSION TIME vs TEMPERATURE (Temperature at 3.3V Supply)

Figure 3. Figure 4.

TEMPERATURE ERROR vs TEMPERATURE TEMPERATURE ERROR AT +25 ° C

Figure 5. Figure 6.

Product Folder Link(s): TMP102

APPLICATION INFORMATION

POINTER REGISTER

TMP102

0.01mF

V+

GND

3ALERT

(Output)

4ADD0

SCL

SDA

Two-Wire

Controller

NOTE:SCL,SDA,andALERT

pinsrequirepull-upresistors.

I/O

Control

Interface

SCL

SDA

Temperature

Configuration

TLOW

THIGH

Pointer

TMP102

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The TMP102 is a digital temperature sensor that isoptimal for thermal-management and thermal- Figure 8 shows the internal register structure of theprotection applications. The TMP102 is two-wire- and TMP102. The 8-bit Pointer Register of the device isSMBus interface-compatible, and is specified over a used to address a given data register. The Pointertemperature range of – 40 ° C to +125 ° C. Register uses the two LSBs (see Table 11 ) to identifywhich of the data registers should respond to a readPull-up resistors are required on SCL, SDA, and

or write command. Table 1 identifies the bits of theALERT. A 0.01 µF bypass capacitor is recommended,

Pointer Register byte. During a write command, P2as shown in Figure 7 .

through P7 must always be '0'. Table 2 describes thepointer address of the registers available in theTMP102. Power-up reset value of P1/P0 is '00'. Bydefault, the TMP102 reads the temperature onpower-up.

Figure 7. Typical Connections

The temperature sensor in the TMP102 is the chipitself. Thermal paths run through the package leads,as well as the plastic package. The lower thermalresistance of metal causes the leads to provide theprimary thermal path.

To maintain accuracy in applications requiring air or

Figure 8. Internal Register Structuresurface temperature measurement, care should betaken to isolate the package and leads from ambientair temperature. A thermally-conductive adhesive is Table 1. Pointer Register Bytehelpful in achieving accurate surface temperature

P7 P6 P5 P4 P3 P2 P1 P0measurement.

0 0 0 0 0 0 Register Bits

Table 2. Pointer Addresses

P1 P0 REGISTER

0 0 Temperature Register (Read Only)0 1 Configuration Register (Read/Write)1 0 T

LOW

HIGH

Product Folder Link(s): TMP102

TEMPERATURE REGISTER

TMP102

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indicates Normal mode (EM bit = '0') or Extendedmode (EM bit = '1') and can be used to distinguishThe Temperature Register of the TMP102 is

between the two temperature register data formats.configured as a 12-bit, read-only register

The unused bits in the Temperature Register always(Configuration Register EM bit = '0', see the Extended

read '0'.Mode section), or as a 13-bit, read-only register(Configuration Register EM bit = '1') that stores the

Table 3. Byte 1 of Temperature Register

(1)output of the most recent conversion. Two bytes must

D7 D6 D5 D4 D3 D2 D1 D0be read to obtain data, and are described in Table 3and Table 4 . Note that byte 1 is the most significant

T11 T10 T9 T8 T7 T6 T5 T4byte, followed by byte 2, the least significant byte.

(T12) (T11) (T10) (T9) (T8) (T7) (T6) (T5)The first 12 bits (13 bits in Extended mode) are used

(1) Extended mode 13-bit configuration shown in parenthesis.to indicate temperature. The least significant bytedoes not have to be read if that information is not

Table 4. Byte 2 of Temperature Register

(1)needed. The data format for temperature issummarized in Table 5 and Table 6 . One LSB equals

D7 D6 D5 D4 D3 D2 D1 D00.0625 ° C. Negative numbers are represented in

T3 T2 T1 T0 0 0 0 0binary twos complement format. Following power-up

(T4) (T3) (T2) (T1) (T0) (0) (0) (1)or reset, the Temperature Register will read 0 ° C until

(1) Extended mode 13-bit configuration shown in parenthesis.the first conversion is complete. Bit D0 of byte 2

Table 5. 12-Bit Temperature Data Format

(1)

TEMPERATURE ( ° C) DIGITAL OUTPUT (BINARY) HEX

128 0111 1111 1111 7FF127.9375 0111 1111 1111 7FF100 0110 0100 0000 64080 0101 0000 0000 50075 0100 1011 0000 4B050 0011 0010 0000 32025 0001 1001 0000 1900.25 0000 0000 0100 0040 0000 0000 0000 000– 0.25 1111 1111 1100 FFC– 25 1110 0111 0000 E70– 55 1100 1001 0000 C90

(1) The resolution for the Temp ADC in Internal Temperature mode is 0.0625 ° C/count.

For positive temperatures (for example, +50 ° C):Twos complement is not performed on positive numbers. Therefore, simply convert the number to binarycode with the 12-bit, left-justified format, and MSB = 0 to denote a positive sign.Example: (+50 ° C)/(0.0625 ° C/count) = 800 = 320h = 0011 0010 0000

For negative temperatures (for example, – 25 ° C):Generate the twos complement of a negative number by complementing the absolute value binary numberand adding 1. Denote a negative number with MSB = 1.Example: (| – 25 ° C|)/(0.0625 ° C/count) = 400 = 190h = 0001 1001 0000Twos complement format: 1110 0110 1111 + 1 = 1110 0111 0000

Product Folder Link(s): TMP102

CONFIGURATION REGISTER ALERT (AL Bit)

CONVERSION RATE

EXTENDED MODE (EM)

TMP102

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Table 6. 13-Bit Temperature Data Format

TEMPERATURE ( ° C) DIGITAL OUTPUT (BINARY) HEX

150 0 1001 0110 0000 0960128 0 1000 0000 0000 0800127.9375 0 0111 1111 1111 07FF100 0 0110 0100 0000 064080 0 0101 0000 0000 050075 0 0100 1011 0000 04B050 0 0011 0010 0000 032025 0 0001 1001 0000 01900.25 0 0000 0000 0100 00040 0 0000 0000 0000 0000– 0.25 1 1111 1111 1100 1FFC– 25 1 1110 0111 0000 1E70– 55 1 1100 1001 0000 1C90

The Configuration Register is a 16-bit read/write The AL bit is a read-only function. Reading the AL bitregister used to store bits that control the operational will provide information about the comparator modemodes of the temperature sensor. Read/write status. The state of the POL bit inverts the polarity ofoperations are performed MSB first. The format and data returned from the AL bit. For POL = 0, the AL bitpower-up/reset value of the Configuration Register is will read as '1' until the temperature equals orshown in Table 7 . For compatibility, the first byte exceeds T

HIGH

for the programmed number ofcorresponds to the Configuration Register in the consecutive faults, causing the AL bit to read as '0'.TMP75 and TMP275 . All registers are updated byte The AL bit will continue to read as '0' until theby byte. temperature falls below T

LOW

for the programmednumber of consecutive faults, when it will again readTable 7. Configuration and Power-Up/Reset as '1'. The status of the TM bit does not affect theFormat

status of the AL bit.BYTE D7 D6 D5 D4 D3 D2 D1 D0

OS R1 R0 F1 F0 POL TM SD1

The conversion rate bits, CR1 and CR0, configure the01100000

TMP102 for conversion rates of 8Hz, 4Hz, 1Hz, orCR1 CR0 AL EM 0 0 0 02

0.25Hz. The default rate is 4Hz. The TMP102 has a10100000

typical conversion time of 26ms. To achieve differentconversion rates, the TMP102 makes a conversionand after that powers down and waits for theappropriate delay set by CR1 and CR0. Table 8The Extended mode bit configures the device for

shows the settings for CR1 and CR0.Normal mode operation (EM = 0) or Extended modeoperation (EM = 1). In Normal mode, the

Table 8. Conversion Rate SettingsTemperature Register and high- and low-limit

CR1 CR0 CONVERSION RATEregisters use a 12-bit data format. Normal mode isused to make the TMP102 compatible with the

0 0 0.25HzTMP75 .

0 1 1HzExtended mode (EM = 1) allows measurement of

1 0 4Hz (default)temperatures above +128 ° C by configuring the

1 1 8HzTemperature Register, and high- and low-limitregisters, for 13-bit data format.

Product Folder Link(s): TMP102

Startup Startof

Conversion

Delay(1)

NOTE:(1)DelayissetbyCR1andCR0.

26ms

Measured

Temperature

THIGH

TLOW

TMP102 ALERTPIN

(ComparatorMode)

POL=0

TMP102 ALERTPIN

(InterruptMode)

POL=0

TMP102 ALERTPIN

(ComparatorMode)

POL=1

TMP102 ALERTPIN

(InterruptMode)

POL=1

Read Read

Time

Read

SHUTDOWN MODE (SD)

FAULT QUEUE (F1/F0)

THERMOSTAT MODE (TM)

POLARITY (POL)

TMP102

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After power-up or general-call reset, the TMP102immediately starts a conversion, as shown inFigure 9 . The first result is available after 26ms(typical). The active quiescent current duringconversion is 40 µA (typical at +27 ° C). The quiescentcurrent during delay is 2.2 µA (typical at +27 ° C).

Figure 9. Conversion Start

The Shutdown mode bit saves maximum power by

Figure 10. Output Transfer Function Diagramsshutting down all device circuitry other than the serialinterface, reducing current consumption to typicallyless than 0.5 µA. Shutdown mode is enabled whenthe SD bit is '1'; the device shuts down when current

A fault condition exists when the measuredconversion is completed. When SD is equal to '0', the

temperature exceeds the user-defined limits set in thedevice maintains a continuous conversion state.

HIGH

and T

LOW

registers. Additionally, the number offault conditions required to generate an alert may beprogrammed using the fault queue. The fault queue isThe Thermostat mode bit indicates to the device

provided to prevent a false alert as a result ofwhether to operate in Comparator mode (TM = 0) or

environmental noise. The fault queue requiresInterrupt mode (TM = 1). For more information on

consecutive fault measurements in order to triggercomparator and interrupt modes, see the High- and

the alert function. Table 9 defines the number ofLow-Limit Registers section.

measured faults that may be programmed to triggeran alert condition in the device. For T

HIGH

and T

LOWregister format and byte order, see the High- andLow-Limit Registers section.The Polarity bit allows the user to adjust the polarityof the ALERT pin output. If POL = 0, the ALERT pin

Table 9. TMP102 Fault Settingswill be active low, as shown in Figure 10 . For POL =

F1 F0 CONSECUTIVE FAULTS1, the ALERT pin will be active high, and the state ofthe ALERT pin is inverted.

0 0 10 1 21 0 41 1 6

Product Folder Link(s): TMP102

CONVERTER RESOLUTION (R1/R0)

ONE-SHOT/CONVERSION READY (OS)

HIGH- AND LOW-LIMIT REGISTERS

BUS OVERVIEW

TMP102

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Both operational modes are represented in Figure 10 .Table 10 and Table 11 describe the format for theR1/R0 are read-only bits. The TMP102 converter

HIGH

and T

LOW

registers. Note that the mostresolution is set on start up to '11'. This sets the

significant byte is sent first, followed by the leasttemperature register to a 12 bit-resolution.

significant byte. Power-up reset values for T

HIGH

andT

LOW

are: T

HIGH

= +80 ° C and T

LOW

= +75 ° C. Theformat of the data for T

HIGH

and T

LOW

is the same asfor the Temperature Register.The TMP102 features a One-Shot TemperatureMeasurement mode. When the device is in Shutdown

Table 10. Bytes 1 and 2 of T

HIGH

(1)mode, writing a ‘ 1 ’ to the OS bit starts a singletemperature conversion. During the conversion, the

BYTE D7 D6 D5 D4 D3 D2 D1 D0OS bit reads '0'. The device returns to the shutdown

H11 H10 H9 H8 H7 H6 H5 H41state at the completion of the single conversion. After

(H12) (H11) (H10) (H9) (H8) (H7) (H6) (H5)the conversion, the OS bit reads '1'. This feature is

BYTE D7 D6 D5 D4 D3 D2 D1 D0useful for reducing power consumption in the

H3 H2 H1 H0 0 0 0 0TMP102 when continuous temperature monitoring is

2not required.

(H4) (H3) (H2) (H1) (H0) (0) (0) (0)

(1) Extended mode 13-bit configuration shown in parenthesis.As a result of the short conversion time, the TMP102can achieve a higher conversion rate. A single

Table 11. Bytes 1 and 2 of T

LOW

(1)conversion typically takes 26ms and a read can takeplace in less than 20 µs. When using One-Shot mode,

BYTE D7 D6 D5 D4 D3 D2 D1 D030 or more conversions per second are possible.

L11 L10 L9 L8 L7 L6 L5 L41

(L12) (L11) (L10) (L9) (L8) (L7) (L6) (L5)

BYTE D7 D6 D5 D4 D3 D2 D1 D0In Comparator mode (TM = 0), the ALERT pin

L3 L2 L1 L0 0 0 0 0becomes active when the temperature equals or

(L4) (L3) (L2) (L1) (L0) (0) (0) (0)exceeds the value in T

HIGH

and generates a

(1) Extended mode 13-bit configuration shown in parenthesis.consecutive number of faults according to fault bitsF1 and F0. The ALERT pin remains active until thetemperature falls below the indicated T

LOW

value forthe same number of faults.

The device that initiates the transfer is called aIn Interrupt mode (TM = 1), the ALERT pin becomes

master, and the devices controlled by the master areactive when the temperature equals or exceeds the

slaves. The bus must be controlled by a mastervalue in T

HIGH

for a consecutive number of fault

device that generates the serial clock (SCL), controlsconditions (as shown in Table 9 ). The ALERT pin

the bus access, and generates the START and STOPremains active until a read operation of any register

conditions.occurs, or the device successfully responds to the

To address a specific device, a START condition isSMBus Alert Response address. The ALERT pin will

initiated, indicated by pulling the data-line (SDA) fromalso be cleared if the device is placed in Shutdown

a high to low logic level while SCL is high. All slavesmode. Once the ALERT pin is cleared, it becomes

on the bus shift in the slave address byte on theactive again only when temperature falls below T

LOW

rising edge of the clock, with the last bit indicatingand remains active until cleared by a read operation

whether a read or write operation is intended. Duringof any register or a successful response to the

the ninth clock pulse, the slave being addressedSMBus Alert Response address. Once the ALERT

responds to the master by generating anpin is cleared, the above cycle repeats, with the

Acknowledge and pulling SDA low.ALERT pin becoming active when the temperatureequals or exceeds T

HIGH

. The ALERT pin can also be

Data transfer is then initiated and sent over eightcleared by resetting the device with the General Call

clock pulses followed by an Acknowledge Bit. DuringReset command. This action also clears the state of

data transfer SDA must remain stable while SCL isthe internal registers in the device, returning the

high, because any change in SDA while SCL is highdevice to Comparator mode (TM = 0).

will be interpreted as a START or STOP signal.

Once all data have been transferred, the mastergenerates a STOP condition indicated by pulling SDAfrom low to high, while SCL is high.

Product Folder Link(s): TMP102

SERIAL INTERFACE

SERIAL BUS ADDRESS

SLAVE MODE OPERATIONS

Slave Receiver Mode:

WRITING/READING OPERATION

Slave Transmitter Mode:

TMP102

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This action is accomplished by issuing a slaveaddress byte with the R/ W bit low, followed by theThe TMP102 operates as a slave device only on the

Pointer Register byte. No additional data aretwo-wire bus and SMBus. Connections to the bus are

required. The master can then generate a STARTmade via the open-drain I/O lines SDA and SCL. The

condition and send the slave address byte with theSDA and SCL pins feature integrated spike

R/ W bit high to initiate the read command. Seesuppression filters and Schmitt triggers to minimize

Figure 14 for details of this sequence. If repeatedthe effects of input spikes and bus noise. The

reads from the same register are desired, it is notTMP102 supports the transmission protocol for both

necessary to continually send the Pointer Registerfast (1kHz to 400kHz) and high-speed (1kHz to

bytes, because the TMP102 remembers the Pointer3.4MHz) modes. All data bytes are transmitted MSB

operation.

Note that register bytes are sent with the mostsignificant byte first, followed by the least significantTo communicate with the TMP102, the master must

byte.first address slave devices via a slave address byte.The slave address byte consists of seven addressbits, and a direction bit indicating the intent ofexecuting a read or write operation. The TMP102 can operate as a slave receiver or slavetransmitter. As a slave device, the TMP102 neverThe TMP102 features an address pin to allow up to

drives the SCL line.four devices to be addressed on a single bus.Table 12 describes the pin logic levels used toproperly connect up to four devices.

The first byte transmitted by the master is the slaveTable 12. Address Pin and Slave Addresses address, with the R/ W bit low. The TMP102 thenacknowledges reception of a valid address. The nextDEVICE TWO-WIRE

A0 PIN CONNECTION

byte transmitted by the master is the PointerADDRESS

of the Pointer Register byte. The next byte or bytes1001001 V+

are written to the register addressed by the Pointer1001010 SDA

transfer by generating a START or STOP condition.

Accessing a particular register on the TMP102 is

The first byte transmitted by the master is the slaveaccomplished by writing the appropriate value to the

address, with the R/ W bit high. The slavePointer Register. The value for the Pointer Register is

acknowledges reception of a valid slave address. Thethe first byte transferred after the slave address byte

next byte is transmitted by the slave and is the mostwith the R/ W bit low. Every write operation to the

significant byte of the register indicated by the PointerTMP102 requires a value for the Pointer Register

data byte. The next byte transmitted by the slave isWhen reading from the TMP102, the last value stored the least significant byte. The master acknowledgesin the Pointer Register by a write operation is used to reception of the data byte. The master can terminatedetermine which register is read by a read operation. data transfer by generating a Not-Acknowledge onTo change the register pointer for a read operation, a reception of any data byte, or generating a START ornew value must be written to the Pointer Register. STOP condition.

Product Folder Link(s): TMP102

SMBus ALERT FUNCTION HIGH-SPEED (Hs) MODE

TIMEOUT FUNCTION

NOISE

GENERAL CALL

TMP102

SCL SDA

GND V+

ALERT ADD0

CF10nF³

RF5k£ W

SupplyVoltage

TMP102

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The TMP102 supports the SMBus Alert function. In order for the two-wire bus to operate at frequenciesWhen the TMP102 operates in Interrupt mode (TM = above 400kHz, the master device must issue an'1'), the ALERT pin may be connected as an SMBus Hs-mode master code (00001xxx) as the first byteAlert signal. When a master senses that an ALERT after a START condition to switch the bus tocondition is present on the ALERT line, the master high-speed operation. The TMP102 does notsends an SMBus Alert command (00011001) to the acknowledge this byte, but switches its input filters onbus. If the ALERT pin is active, the device SDA and SCL and its output filters on SDA to operateacknowledges the SMBus Alert command and in Hs-mode, allowing transfers at up to 3.4MHz. Afterresponds by returning its slave address on the SDA the Hs-mode master code has been issued, theline. The eighth bit (LSB) of the slave address byte master transmits a two-wire slave address to initiate aindicates if the ALERT condition was caused by the data transfer operation. The bus continues to operatetemperature exceeding T

HIGH

or falling below T

LOW

. in Hs-mode until a STOP condition occurs on the bus.For POL = '0', this bit is low if the temperature is Upon receiving the STOP condition, the TMP102greater than or equal to T

HIGH

; this bit is high if the switches the input and output filters back totemperature is less than T

LOW

. The polarity of this bit fast-mode operation.is inverted if POL = '1'. Refer to Figure 15 for detailsof this sequence.

If multiple devices on the bus respond to the SMBus

The TMP102 resets the serial interface if SCL is heldAlert command, arbitration during the slave address

low for 30ms (typ). The TMP102 releases the bus if itportion of the SMBus Alert command determines

is pulled low and waits for a START condition. Towhich device will clear its ALERT status. The device

avoid activating the timeout function, it is necessarywith the lowest two-wire address wins the arbitration.

to maintain a communication speed of at least 1kHzIf the TMP102 wins the arbitration, its ALERT pin

for SCL operating frequency.becomes inactive at the completion of the SMBusAlert command. If the TMP102 loses the arbitration,its ALERT pin remains active.

The TMP102 is a very low-power device andgenerates very low noise on the supply bus. Applyingan RC filter to the V+ pin of the TMP102 can furtherThe TMP102 responds to a two-wire General Call

reduce any noise the TMP102 might propagate toaddress (0000000) if the eighth bit is '0'. The device

other components. R

in Figure 11 should be lessacknowledges the General Call address and

than 5k Ωand C

should be greater than 10nF.responds to commands in the second byte. If thesecond byte is 00000110, the TMP102 internalregisters are reset to power-up values. The TMP102does not support the General Address acquirecommand.

Figure 11. Noise Reduction

Product Folder Link(s): TMP102

TIMING DIAGRAMS

TMP102

SBOS397B – AUGUST 2007 – REVISED OCTOBER 2008 ...............................................................................................................................................

www.ti.com

Data Transfer: The number of data bytes transferredbetween a START and a STOP condition is notThe TMP102 is two-wire and SMBus compatible.

limited and is determined by the master device. It isFigure 12 to Figure 15 describe the various

also possible to use the TMP102 for single byteoperations on the TMP102. Parameters for Figure 12

updates. To update only the MS byte, terminate theare defined in Table 13 . Bus definitions are:

communication by issuing a START or STOPcommunication on the bus.Bus Idle: Both SDA and SCL lines remain high.

Acknowledge: Each receiving device, whenStart Data Transfer: A change in the state of the

addressed, is obliged to generate an AcknowledgeSDA line, from high to low, while the SCL line is high,

bit. A device that acknowledges must pull down thedefines a START condition. Each data transfer is

SDA line during the Acknowledge clock pulse in suchinitiated with a START condition.

a way that the SDA line is stable low during the highStop Data Transfer: A change in the state of the

period of the Acknowledge clock pulse. Setup andSDA line from low to high while the SCL line is high

hold times must be taken into account. On a masterdefines a STOP condition. Each data transfer is

receive, the termination of the data transfer can beterminated with a repeated START or STOP

signaled by the master generating acondition.

Not-Acknowledge ('1') on the last byte that has beentransmitted by the slave.

Table 13. Timing Diagram Definitions

FAST MODE HIGH-SPEED MODE

PARAMETER TEST CONDITIONS MIN MAX MIN MAX UNIT

(SCL)

SCL Operating Frequency, V

> 1.7V 0.001 0.4 0.001 3.4 MHzf

(SCL)

SCL Operating Frequency, V

< 1.7V 0.001 0.4 0.001 2.75 MHzBus Free Time Between STOP and STARTt

(BUF)

600 160 nsConditionHold time after repeated START condition.t

(HDSTA)

100 100 nsAfter this period, the first clock is generated.t

(SUSTA)

Repeated START Condition Setup Time 100 100 nst

(SUSTO)

STOP Condition Setup Time 100 100 nst

(HDDAT)

Data Hold Time 0 0 nst

(SUDAT)

Data Setup Time 100 10 nst

(LOW)

SCL Clock Low Period, V

> 1.7V 1300 160 nst

(LOW)

SCL Clock Low Period, V

< 1.7V 1300 200 nst

(HIGH)

SCL Clock High Period 600 60 nst

Clock/Data Fall Time 300 nst

Clock/Data Rise Time 300 160 nst

Clock/Data Rise Time for SCLK ≤100kHz 1000 ns

Product Folder Link(s): TMP102

TWO-WIRE TIMING DIAGRAMS

SCL

SDA

t(LOW) tRtFt(HDSTA)

t(HDSTA)

t(HDDAT)

t(BUF)

t(SUDAT)

t(HIGH) t(SUSTA) t(SUSTO)

P S S P

Frame1Two-WireSlaveAddressByte Frame2PointerRegisterByte

Frame4DataByte2

StartBy

Master

ACKBy

TMP102

ACKBy

TMP102

ACKBy

TMP102

StopBy

Master

1 9 1

D7 D6 D5 D4 D3 D2 D1 D0

Frame3DataByte1

ACKBy

TMP102

SDA

(Continued)

SCL

(Continued)

D6 D5 D4 D3 D2 D1 D0

SDA

SCL

0 0 1 0 A1(1) A0(1) R/W 0 0 0 0 0 0 P1 P0 ¼

NOTE:(1)ThevalueofA0andA1aredeterminedbytheADD0pin.

TMP102

www.ti.com

............................................................................................................................................... SBOS397B – AUGUST 2007 – REVISED OCTOBER 2008

Figure 12. Two-Wire Timing Diagram

Figure 13. Two-Wire Timing Diagram for Write Word Format

Product Folder Link(s): TMP102

Frame1Two-WireSlaveAddressByte Frame2PointerRegisterByte

StartBy

Master

ACKBy

TMP102

ACKBy

TMP102

Frame3Two-WireSlaveAddressByte Frame4DataByte1ReadRegister

StartBy

Master

ACKBy

TMP102

ACKBy

Master(2)

From

TMP102

1 9 1 9

SDA

SCL

0 0 1 R/W 0 0 0 0 0 0 P1 P0

SDA

(Continued)

SCL

(Continued)

SDA

(Continued)

SCL

(Continued)

1 0 0 1

0A1(1) A0(1)

0A1(1) A0(1) R/W D7 D6 D5 D4 D3 D2 D1 D0

Frame5DataByte2ReadRegister

StopBy

Master

ACKBy

Master(3)

From

TMP102

D7 D6 D5 D4 D3 D2 D1 D0

StopBy

Master

NOTE: (1)ThevalueofA0andA1aredeterminedbytheADD0pin.

(2)MastershouldleaveSDAhightoterminateasingle-bytereadoperation.

(3)MastershouldleaveSDAhightoterminateatwo-bytereadoperation.

NOTE:(1)ThevalueofA0andA1aredeterminedbytheADD0pin.

Frame1SMBusALERTResponseAddressByte Frame2SlaveAddressFromTMP102

StartBy

Master

ACKBy

TMP102

From

TMP102

NACKBy

Master

StopBy

Master

1 9 1 9

SDA

SCL

ALERT

0 0 0 1 1 0 0 R/W 1 0 0 1 A1 A0

Status

TMP102

SBOS397B – AUGUST 2007 – REVISED OCTOBER 2008 ...............................................................................................................................................

www.ti.com

Figure 14. Two-Wire Timing Diagram for Read Word Format

Figure 15. Timing Diagram for SMBus ALERT

Product Folder Link(s): TMP102

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

TMP102AIDRLR ACTIVE SOT DRL 6 4000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TMP102AIDRLRG4 ACTIVE SOT DRL 6 4000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TMP102AIDRLT ACTIVE SOT DRL 6 250 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TMP102AIDRLTG4 ACTIVE SOT DRL 6 250 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 22-Oct-2008

Addendum-Page 1

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

TMP102AIDRLT SOT DRL 6 250 180.0 9.5 1.78 1.78 0.69 4.0 8.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 1-Aug-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TMP102AIDRLT SOT DRL 6 250 180.0 180.0 30.0

PACKAGE MATERIALS INFORMATION

www.ti.com 1-Aug-2012

Pack Materials-Page 2

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