CY7C144E
8 K × 8 Dual-port Static RAM
with SEM, INT, BUSY
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 001-63982 Rev. *B Revised October 12, 2011
Features
■True dual-ported memory cells that enable simultaneous reads
of the same memory location
■8 K × 8 organization (CY7C144E)
■0.35-micron CMOS for optimum speed and power
■High-speed access: 15 ns
■Low operating power: ICC = 180 mA (typical),
standby ISB3 = 0.05 mA (typical)
■Fully asynchronous operation
■Automatic power-down
■TTL compatible
■Master / slave select pin enables bus width expansion to 16-bits
or more
■Busy arbitration scheme provided
■Semaphores included to permit software handshaking
between ports
■INT flag for port-to-port communication
■Available in 68-pin PLCC and 64-pin TQFP
■Pb-free packages available
Functional Description
The CY7C144E is a high speed CMOS 8 K × 8 dual port static
RAM. Various arbitration schemes are included on the
CY7C144E to handle situations when multiple processors
access the same piece of data. Two ports are provided permitting
independent, asynchronous access for reads and writes to any
location in memory. The CY7C144E can be used as a
standalone 64-Kbit dual-port static RAM or multiple devices can
be combined in order to function as a 16-bit or wider master /
slave dual-port static RAM. An M/S pin is provided for
implementing 16-bit or wider memory applications without the
need for separate master and slave devices or additional
discrete logic. Application areas include interprocessor /
multiprocessor designs, communications status buffering, and
dual-port video / graphics memory.
Each port has independent control pins: chip enable (CE), read
or write enable (R/W), and output enable (OE). Two flags, BUSY
and INT, are provided on each port. BUSY signals that the port
is trying to access the same location currently being accessed
by the other port. The interrupt flag (INT) permits communication
between ports or systems by means of a mail box. The
semaphores are used to pass a flag, or token, from one port to
the other to indicate that a shared resource is in use. The
semaphore logic is comprised of eight shared latches. Only one
side can control the latch (semaphore) at any time. Control of a
semaphore indicates that a shared resource is in use. An
automatic power-down feature is controlled independently on
each port by a chip enable (CE) pin or SEM pin.
R/W L
CEL
OEL
A12L
A0L A0R
A12R
R/W R
CER
OER
CE R
OE R
CEL
OEL
R/W LR/W R
I/O
7L
I/O
0L
I/O 7R
I/O 0R
INTERRUPT
SEMAPHORE
ARBITRATION
CONTROL
I/O
CONTROL
I/O
MEMORY
ARRAY ADDRESS
DECODER
ADDRESS
DECODER
SEM LSEM
R
BUSYLBUSYR
INT LINT
R
M/S
[1, 2]
[2]
[1, 2]
[2]
Logic Block Diagram
Notes
1. BUSY is an output in master mode and an input in slave mode.
2. Interrupt: push-pull output and requires no pull-up resistor.
[+] Feedback
CY7C144E
Document #: 001-63982 Rev. *B Page 2 of 22
Contents
Pin Configuration .............................................................3
Architecture ...................................................................... 4
Functional Description .....................................................4
Write Operation ...........................................................4
Read Operation ........................................................... 4
Interrupts .....................................................................4
Busy ............................................................................ 4
Master/Slave ...............................................................5
Semaphore Operation ................................................. 5
Maximum Ratings .............................................................7
Operating Range ............................................................... 7
Electrical Characteristics .................................................7
Capacitance ......................................................................8
Switching Characteristics ................................................ 9
Switching Waveforms .................................................... 11
Ordering Code Definitions ......................................... 18
Package Diagrams .......................................................... 19
Acronyms ........................................................................ 21
Reference Documents .................................................... 21
Document Conventions ................................................. 21
Units of Measure ....................................................... 21
Document History Page ................................................. 22
Sales, Solutions, and Legal Information ...................... 22
Worldwide Sales and Design Support ....................... 22
Products .................................................................... 22
PSoC Solutions ......................................................... 22
[+] Feedback
CY7C144E
Document #: 001-63982 Rev. *B Page 3 of 22
Table 1. Selection Guide
Description 7C144E-15 7C144E-25 7C144E-55 Unit
Maximum access time 15 25 55 ns
Typical operating current 190 180 180 mA
Typical Standby Current for ISB1 (both ports
TTL level)
50 45 45 mA
Typical Standby Current for ISB3 (both ports
CMOS level)
0.05 0.05 0.05 mA
Pin Configuration
Figure 1. 68-pin PLCC (Top View) Figure 2. 64-pin TQFP (Top View)
IO
IO
IO
IO
IO
IO
IO
L
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
67
60
59
58
57
56
55
54
53
52
51
50
49
48
3132 3334353637 383940414243
5 4 3 2 168 666564 636261
A
A4L
A3L
A2L
A1L
A0L
INTL
BUSY
L
GND
M/S
BUSY
R
INTR
A0R
IO 2L
IO 3L
IO 4L
IO 5L
GND
IO 6L
IO 7L
V
CC
GND
0R
1R
2R
V
CC
A
2728 29 30
98 76
47
46
45
44
A1R
A2R
A3R
A4R
3R
4R
5R
6R
25
26
6L
7L
A
8L
A
9L
A
A
10L
11L
VCC
NC
NC
CEL
SEM L
R/ WL
OEL
NC
IO
IO 1L
0L
A
A
6R
7R
A
8R
A
9R
A10R
NC
NC
CER
SEM
R
R/W
R
OER
IO7R
GND
A11R
A
5R
A5L
NC
A12
12R
CY7C144E
A
[3]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 50
32 49
16
GND
OER
IO 2L
IO 3L
IO 4L
IO 5L
IO 6L
IO 7L
VCC
GND
IO 0R
IO 1R
IO 2R
IO 3R
IO 4R
IO 5R
IO 6R
GND
VCC
A4L
A3L
A2L
A1L
A0L
GND
BUSY
L
BUSY
R
M/S
A0R
A1R
A2R
A3R
A4R
INT
L
INT
R
IO 7R
A5R
12R
A
11R
A
10R
A9R
A8R
A7R
A6R
NC
CER
SEMR
R/WR
VCC
OEL
IO 1L
IO 0L
A5L
A12 L
A11L
A10L
A9L
A8L
A7L
A6L
NC
CEL
SEML
R/ W L
CY7C144E
A
[+] Feedback
CY7C144E
Document #: 001-63982 Rev. *B Page 4 of 22
Architecture
The CY7C144E consists of a an array of 8 K words of 8 bits each
of dual-port RAM cells, I/O, address lines, and control signals
(CE, OE, R/W). These control pins permit independent access
for reads / writes to any location in memory. To handle simulta-
neous writes or reads to the same location, a BUSY pin is
provided on each port. Two interrupt (INT) pins can be used for
port-to-port communication. Two semaphore (SEM) control pins
are used for allocating shared resources. With the M/S pin, the
CY7C144E can function as a Master (BUSY pins are outputs) or
as a slave (BUSY pins are inputs). The CY7C144E has an
automatic power-down feature controlled by CE. Each port is
provided with its own output enable control (OE), which allows
data to be read from the device.
Functional Description
Write Operation
Data must be set up for a duration of tSD before the rising edge
of R / W to guarantee a valid write. A write operation is controlled
by either the OE pin (see Figure 7 on page 12) or the R / W pin
(see Figure 8 on page 12). Data can be written to the device
tHZOE after the OE is deasserted or tHZWE after the falling edge
of R / W. Required inputs for non-contention operations are
summarized in Table 3 on page 5.
If a location is being written to by one port and the opposite port
attempts to read that location, a port-to-port flowthrough delay
must be met before the data is read on the output; otherwise the
data read is not deterministic. Data will be valid on the port tDDD
after the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE and
CE pins. Data will be available tACE after CE or tDOE after OE are
asserted. If the user of the CY7C144E wishes to access a
semaphore flag, then the SEM pin must be asserted instead of
the CE pin.
Interrupts
The interrupt flag (INT) permits communications between
ports.When the left port writes to location 1FFF, the right port’s
interrupt flag (INTR) is set. This flag is cleared when the right port
reads that same location. Setting the left port’s interrupt flag
(INTL) is accomplished when the right port writes to location
1FFE. This flag is cleared when the left port reads the specified
location 1FFE. The message at 1FFF or 1FFE is user-defined.
See Table 4 on page 6 for input requirements for INT. INTR and
INTL are push-pull outputs and do not require pull-up resistors to
operate.
Busy
The CY7C144E provides on-chip arbitration to alleviate simulta-
neous memory location access (contention). If both ports’ CEs
are asserted and an address match occurs within tPS of each
other the Busy logic determines which port has access. If tPS is
violated, one port will definitely gain permission to the location,
but it is not guaranteed which one. BUSY will be asserted tBLA
Table 2. Pin Definitions
Left Port Right Port Description
I/O0L-7L I/O0R-7R Data bus I/O
A0L-12L A0R-12R Address lines
CELCERChip enable
OELOEROutput enable
R/WLR/WRRead / write enable
SEML SEMRSemaphore enable. When asserted LOW, allows access to eight semaphores. The three least significant
bits of the address lines will determine which semaphore to write or read. The I/O0 pin is used when writing
to a semaphore. Semaphores are requested by writing a 0 into the respective location.
INTLINTRInterrupt Flag. INTL is set when right port writes location 1FFE and is cleared when left port reads location
1FFE. INTR is set when left port writes location 1FFF[4] and is cleared when right port reads location
1FFF[4].
BUSYLBUSYRBusy flag
M/S Master or slave select
VCC Power
GND Ground
Notes
3. This pin is NC.
4. 8K x 8 (CY7C144E): 1FFE(left port) and 1FFF(right port)
[+] Feedback
CY7C144E
Document #: 001-63982 Rev. *B Page 5 of 22
Master/Slave
An M/S pin is provided in order to expand the word width by
configuring the device as either a master or a slave. The BUSY
output of the master is connected to the BUSY input of the slave.
This enables the device to interface to a master device with no
external components.Writing of slave devices must be delayed
until after the BUSY input has settled. Otherwise, the slave chip
may begin a write cycle during a contention situation.When
presented a HIGH input, the M/S pin allows the device to be used
as a master and therefore the BUSY line is an output. BUSY can
then be used to send the arbitration outcome to a slave.
Semaphore Operation
The CY7C144E provides eight semaphore latches which are
separate from the dual-port memory locations. Semaphores are
used to reserve resources that are shared between the two
ports.The state of the semaphore indicates that a resource is in
use. For example, if the left port wants to request a given
resource, it sets a latch by writing a 0 to a semaphore location.
The left port then verifies its success in setting the latch by
reading it. After writing to the semaphore, SEM or OE must be
deasserted for tSOP before attempting to read the semaphore.
The semaphore value is available tSWRD + tDOE after the rising
edge of the semaphore write. If the left port was successful
(reads a 0), it assumes control over the shared resource,
otherwise (reads a 1) it assumes the right port has control and
continues to poll the semaphore.When the right side has relin-
quished control of the semaphore (by writing a 1), the left side
will succeed in gaining control of the semaphore. If the left side
no longer requires the semaphore, a 1 is written to cancel its
request.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip enable for the semaphore latches (CE
must remain HIGH during SEM LOW). A0–2 represents the
semaphore address. OE and R/W are used in the same manner
as a normal memory access.When writing or reading a
semaphore, the other address pins have no effect.
When writing to the semaphore, only I/O0 is used. If a 0 is written
to the left port of an unused semaphore, a 1 appears at the same
semaphore address on the right port. That semaphore can now
only be modified by the side showing 0 (the left port in this case).
If the left port now relinquishes control by writing a 1 to the
semaphore, the semaphore will be set to 1 for both sides.
However, if the right port had requested the semaphore (written
a 0) while the left port had control, the right port would immedi-
ately own the semaphore as soon as the left port released it.
Table 5 on page 6 shows sample semaphore operations.
When reading a semaphore, all eight data lines output the
semaphore value. The read value is latched in an output register
to prevent the semaphore from changing state during a write
from the other port. If both ports attempt to access the
semaphore within tSPS of each other, the semaphore is definitely
obtained by one side or the other, but there is no guarantee which
side controls the semaphore. Initialization of the semaphore is
not automatic and must be reset during initialization program at
power-up. All Semaphores on both sides should have a one
written into them at initialization from both sides to assure that
they are free when needed.
Table 3. Non-Contending Read/Write
Inputs Outputs Operation
CE R/W OE SEM I/O07
H X X H High Z Power-down
H H L L Data out Read data in semaphore
X X H X High Z I/O lines disabled
H X L Data in Write to semaphore
L H L H Data out Read
L L X H Data in Write
L X X L Illegal condition
[+] Feedback
CY7C144E
Document #: 001-63982 Rev. *B Page 6 of 22
Table 4. Interrupt Operation Example (assumes BUSYL = BUSYR = HIGH)
Function Left Port Right Port
R/W CE OE A012 (CY7C144E) INT R/W CE OE A012 (CY7C144E) INT
Set left INT XXX X L L LX 1FFE X
Reset left INT X L L 1FFE H X L L X X
Set right INT LLX 1FFF X XXX X L
Reset right INT X X X X X X L L 1FFF H
Table 5. Semaphore Operation Example
Function I/O0-7 Left I/O0-7 Right Status
No action 1 1 Semaphore free
Left port writes semaphore 0 1 Left port obtains semaphore
Right port writes 0 to semaphore 0 1 Right side is denied access
Left port writes 1 to semaphore 1 0 Right port is granted access to semaphore
Left port writes 0 to semaphore 1 0 No change. Left port is denied access
Right port writes 1 to semaphore 0 1 Left port obtains semaphore
Left port writes 1 to semaphore 1 1 No port accessing semaphore address
Right port writes 0 to semaphore 1 0 Right port obtains semaphore
Right port writes 1 to semaphore 1 1 No port accessing semaphore
Left port writes 0 to semaphore 0 1 Left port obtains semaphore
Left port writes 1 to semaphore 1 1 No port accessing semaphore
[+] Feedback
CY7C144E
Document #: 001-63982 Rev. *B Page 7 of 22
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.[5]
Storage temperature ................................ –65 C to +150 C
Ambient temperature with
power applied ........................................... –55 C to +125 C
Supply voltage to ground potential ...............–0.3 V to +7.0 V
DC voltage applied to outputs
in High Z state ..............................................–0.5 V to +7.0 V
DC input voltage[6] ........................................–0.5 V to +7.0 V
Output current into outputs (LOW) .............................. 20 mA
Static discharge voltage........................................... >2001 V
(per MIL-STD-883, Method 3015)
Latch-up current ..................................................... >200 mA
Operating Range
Range
Ambient
Temperature VCC
Commercial 0 C to +70 C 5 V 10%
Industrial –40 C to +85 C 5 V 10%
Electrical Characteristics
Over the operating range
Parameter Description Test Conditions 7C144E-15 7C144E-25 7C144E-55 Unit
Min Typ Max Min Typ Max Min Typ Max
VOH Output HIGH voltage VCC = Min, IOH = 4.0 mA 2.4 – – 2.4 – – 2.4 – V
VOL Output LOW voltage VCC = Min, IOL = 4.0 mA – – 0.4 – – 0.4 – – 0.4 V
VIH Input HIGH voltage 2.2 – – 2.2 – – 2.2 – V
VIL Input LOW voltage – – 0.8 – – 0.8 – – 0.8 V
IIX Input leakage current GND < VI < VCC 10–+1010 – +10 10 – +10 A
IOZ Output leakage current Outputs disabled, GND < VO < VCC 10–+1010 – +10 10 – +10 A
ICC Operating current VCC = Max, IOUT = 0 mA
Outputs disabled
Com’l – 190 280 – 180 275 – 180 275 mA
Ind – 215 305 – 215 305 – 215 305
ISB1 Standby current
(Both ports TTL levels)
CEL and CER > VIH,
f = fMAX[7] Com’l – 50 70 – 45 65 – 45 65 mA
Ind – 65 95 – 65 95 – 65 95
ISB2 Standby current
(One port TTL level)
CEL or CER > VIH,
f = fMAX[7] Com’l – 120 180 – 110 160 – 110 160 mA
Ind – 135 205 – 135 205 – 135 205
ISB3 Standby current
(Both ports CMOS levels)
Both ports
CE and CER > VCC – 0.2 V,
VIN > VCC – 0.2 V
or VIN < 0.2 V, f = 0[7]
Com’l – 0.05 0.5 – 0.05 0.5 – 0.05 0.5 mA
Ind – 0.05 0.5 – 0.05 0.5 – 0.05 0.5
ISB4 Standby current
(One port CMOS level)
One port
CEL or CER > VCC – 0.2 V,
VIN > VCC – 0.2 V or
VIN < 0.2 V, Active
Port outputs, f = fMAX[7]
Com’l – 110 160 – 100 140 – 100 140 mA
Ind – 125 175 – 125 175 – 125 175
Notes
5. The voltage on any input or I/O pin cannot exceed the power pin during power-up.
6. Pulse width < 20 ns.
7. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change.
This applies only to inputs at CMOS level standby ISB3.
[+] Feedback
CY7C144E
Document #: 001-63982 Rev. *B Page 8 of 22
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions Max Unit
CIN Input capacitance TA = 25 C, f = 1 MHz,
VCC = 5.0 V
10 pF
COUT Output capacitance 10 pF
Figure 3. AC Test Loads and Waveforms
3.0V
GND
90% 90%
10%
3ns 3ns
10%
ALL INPUT PULSES
(a) Normal Load (Load1)
5V
OUTPUT
C= 30pF
VTH = 1.4V
OUTPUT
C = 30pF
(b) Th évenin Equivalent (Load 1) (c) Three-State Delay (Load 3)
C= 30pF
OUTPUT
Load (Load 2)
5V
OUTPUT
C= 5pF
R1 = 893
R2 = 347
RTH = 250R1 = 893
R = 347
[+] Feedback
CY7C144E
Document #: 001-63982 Rev. *B Page 9 of 22
Switching Characteristics
Over the operating range[8]
Parameter Description 7C144E-15 7C144E-25 7C144E-55 Unit
Min Max Min Max Min Max
READ CYCLE
tRC Read cycle time 15 – 25 – 55 – ns
tAA Address to data valid – 15 – 25 – 55 ns
tOHA Output hold from address change 3 – 3 – 3 – ns
tACE CE LOW to data valid – 15 – 25 – 55 ns
tDOE OE LOW to data valid – 10 – 15 – 25 ns
tLZOE[9, 10] OE Low to Low Z 3 – 3 – 3 – ns
tHZOE[9, 10] OE HIGH to High Z – 10 – 15 – 25 ns
tLZCE[9, 10] CE LOW to Low Z 3–3–3–ns
tHZCE[9, 10] CE HIGH to High Z –10–15–25ns
tPU[10] CE LOW to power-up 0–0–0–ns
tPD[10] CE HIGH to power-down – 15 – 25 – 55 ns
WRITE CYCLE
tWC Write cycle time 15 – 25 – 55 – ns
tSCE CE LOW to write end 12 – 20 – 45 – ns
tAW Address setup to write end 12 – 20 – 45 – ns
tHA Address hold from write end 0 – 2 – 2 – ns
tSA Address setup to write start 0 – 0 – 0 – ns
tPWE Write pulse width 12 – 20 – 40 – ns
tSD Data setup to write end 10 – 15 – 25 – ns
tHD Data hold from write end 0 – 0 – 0 – ns
tHZWE[10] R/W LOW to High Z – 10 – 15 – 25 ns
tLZWE[10] R/W HIGH to Low Z 3 – 3 – 3 – ns
tWDD[11] Write pulse to data delay – 30 – 50 – 70 ns
tDDD[11] Write data valid to read data valid – 25 – 30 – 40 ns
Notes
8. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOI/IOH
and 30-pF load capacitance.
9. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
10. Test conditions used are Load 3. This parameter is guaranteed but not tested.
11. For information on part-to-part delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform.
[+] Feedback
CY7C144E
Document #: 001-63982 Rev. *B Page 10 of 22
BUSY TIMING[12]
tBLA BUSY LOW from address match – 15 – 20 – 30 ns
tBHA BUSY HIGH from address
mismatch
–15–20–30ns
tBLC BUSY LOW from CE LOW –15–20–30ns
tBHC BUSY HIGH from CE HIGH –15–20–30ns
tPS Port setup for priority 5 – 5 – 5 – ns
tWB R/W LOW after BUSY LOW 0–0–0–ns
tWH R/W HIGH after BUSY HIGH13–20–30–ns
tBDD BUSY HIGH to data valid[13] –15–25–55ns
INTERRUPT TIMING[12]
tINS INT Set time – 15 – 25 – 35 ns
tINR INT Reset time –15–25–35ns
SEMAPHORE TIMING
tSOP SEm flag update pulse (OE or
SEM)
10–10–20–ns
tSWRD SEm flag write to read time 5 – 5 – 5 – ns
tSPS SEm flag contention
window
5–5–5–ns
tSAA SEM Address Access Time – 15 – 20 – 20
Switching Characteristics (continued)
Over the operating range[8]
Parameter Description 7C144E-15 7C144E-25 7C144E-55 Unit
Min Max Min Max Min Max
Note
12. Test conditions used are Load 2.
13. tBDD is a calculated parameter and is the greater of tWDD – tPWE (actual) or tDDD – tSD (actual).
[+] Feedback
CY7C144E
Document #: 001-63982 Rev. *B Page 11 of 22
Switching Waveforms
Figure 4. Read Cycle No. 1 (Either Port Address Access)[14, 15]
Figure 5. Read Cycle No. 2 (Either Port CE/OE Access)[14, 16, 17]
Figure 6. Read Timing with Port-to-port Delay (M/S = L)[18, 19]
tRC
tAA
tOHA
DATA VALIDPREVIOUS DATA VALID
DATA OUT
ADDRESS
tACE
tLZOE
tDOE
tHZOE
tHZCE
DATA VALID
DATA OUT
SEM or CE
OE
tLZCE
tPU
ICC
ISB
tPD
VALID
tDDD
tWDD
MATCH
MATCH
R/WR
DATAINR
DATAOUTL
tWC
ADDRESSR
tPWE
VALID
tSD tHD
ADDRESSL
Notes
14. R/W is HIGH for read cycle.
15. Device is continuously selected CE = LOW and OE = LOW. This waveform cannot be used for semaphore reads.
16. Address valid prior to or coincident with CE transition LOW.
17. CEL = L, SEM = H when accessing RAM. CE = H, SEM = L when accessing semaphores.
18. BUSY = HIGH for the writing port.
19. CEL = CER = LOW.
[+] Feedback
CY7C144E
Document #: 001-63982 Rev. *B Page 12 of 22
Figure 7. Write Cycle No. 1: OE Three-state Data I/Os (Either Port)[20, 21, 22]
Figure 8. Write Cycle No. 2: R/W Three-state Data I/Os (Either Port)[20, 22, 23]
Switching Waveforms (continued)
tAW
tWC
DATA VALID
HIGH IMPEDANCE
tSCE
tSA
tPWE
tHD
tSD
tHA
tHZOE tLZOE
SEM OR CE
R/W
ADDRESS
OE
DATA OUT
DATA IN
tAW
tWC
tSCE
tSA tPWE
tHD
tSD
tHZWE
tHA
HIGH IMPEDANCE
SEM OR CE
R/W
ADDRESS
DATA OUT
DATA IN
tLZWE
DATAVALID
Notes
20. The internal write time of the memory is defined by the overlap of CE or SEM LOW and R/W LOW. Both signals must be LOW to initiate a write, and either signal can
terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
21. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be
placed on the bus for the required tSD. If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply and the write pulse can
be as short as the specified tPWE.
22. R/W must be HIGH during all address transitions.
23. Data I/O pins enter high impedance when OE is held LOW during write.
[+] Feedback
CY7C144E
Document #: 001-63982 Rev. *B Page 13 of 22
Figure 9. Semaphore Read After Write Timing, Either Side[24]
Figure 10. Semaphore Contention[25, 26, 27]
Switching Waveforms (continued)
tSOP
tAA
SEM
R/W
OE
I/O0
VALID ADDRESS VALID ADDRESS
tHD
DATA IN VALID DATA OUT VALID
tOHA
A0A2
tAW
tHA
tACE
tSOP
tSCE
tSD
tSA tPWE
tSWRD tDOE
WRITE CYCLE READ CYCLE
MATCH
tSPS
A0LA2L
MATCH
R/WL
SEML
A0RA2R
R/WR
SEMR
Notes
24. CE = HIGH for the duration of the above timing (both write and read cycle).
25. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH
26. Semaphores are reset (available to both ports) at cycle start.
27. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore.
[+] Feedback
CY7C144E
Document #: 001-63982 Rev. *B Page 14 of 22
Figure 11. Read with BUSY (M/S = HIGH)[19]
Figure 12. Write Timing with Busy Input (M/S = LOW)
Switching Waveforms (continued)
VALID
tDDD
tWDD
MATCH
MATCH
R/WR
DATAINR
DATA OUTL
tWC
ADDRESSR
tPWE
VALID
tSD tHD
ADDRESSL
tPS
tBLA tBHA
tBDD
BUSY
L
tPWE
R/W
BUSY
tWB tWH
[+] Feedback
CY7C144E
Document #: 001-63982 Rev. *B Page 15 of 22
Figure 13. Busy Timing Diagram No. 1 (CE Arbitration)[28]
Figure 14. Busy Timing Diagram No. 2 (Address Arbitration)[28]
Switching Waveforms (continued)
ADDRESS MATCH
tPS
tBLC tBHC
ADDRESS MATCH
tPS
tBLC tBHC
ADDRESSL,R
BUSY
R
CEL
CER
BUSY
L
CER
CEL
ADDRESSL,R
CEL Valid First:
CER Valid First:
ADDRESS MATCH
tPS
ADDRESSL
BUSY R
ADDRESS MISMATCH
tRC or tWC
tBLA tBHA
ADDRESSR
ADDRESS MATCH ADDRESS MISMATCH
tPS
ADDRESSL
BUSY
L
tRC or tWC
tBLA tBHA
ADDRESSR
Left Address Valid First:
Right Address Valid First:
Note
28. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted.
[+] Feedback
CY7C144E
Document #: 001-63982 Rev. *B Page 16 of 22
Figure 15. Interrupt Timing Diagrams
Switching Waveforms (continued)
WRITE 1FFF
t
WC
t
HA
Left Side Sets INTR
ADDRESS
L
R/W
L
CE
L
INT
R
t
INS
[29]
[30]
[31
Right Side Clears INTR
READ 1FFF
tRC
tINR
WRITE 1FFE
tWC
Right Side Sets INTL
Left Side Clears INTL
READ 1FFE
tINR
tRC
ADDRESS R
CEL
R/W
L
INT
L
OEL
ADDRESS R
R/WR
CE R
INTL
ADDRESSR
CER
R/WR
INTR
OE R
tHA
tINS
[30]
[29]
[30]
[30]
[31]
[31]
[31]
Notes
29. tHA depends on which enable pin (CEL or R/WL) is deasserted first.
30. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.
31. 8 K × 8 (CY7C144E): 1FFE(left port) and 1FFF(right port).
[+] Feedback
CY7C144E
Document #: 001-63982 Rev. *B Page 17 of 22
Figure 16. Typical DC and AC Characteristics
1.4
1.0
0.4
4.0 4.5 5.0 5.5 6.0 55 25 125
1.2
1.0
120
80
0 1.0 2.0 3.0 4.0
Output Source Current (mA)
Supply Voltage (V)
Normalized Supply Current
Vs. Supply Voltage
Normalized Supply Current
Vs. Ambient Temperature
Ambient Temperature (°C) Output Voltage (V)
Output Source Current
Vs. Output Voltage
0.0
0.8
0.8
0.6
0.6
Normalized ICC, ISB
VCC = 5.0V
VIN = 5.0V
0
ICC
ICC
1.6
1.4
1.2
1.0
0.8
55 125
Normalized tAA
Normalized Access Time
Vs. Ambient Temperature
Ambient Temperature (°C)
1.4
1.3
1.2
1.0
0.9
4.0 4.5 5.0 5.5 6.0
Normalized tAA
Supply Voltage (V)
Normalized Access Time
Vs. Supply Voltage
120
140
100
60
40
20
0.0 1.0 2.0 3.0 4.0
Output Sink Current (mA)
0
80
Output Voltage (V)
Output Sink Current
Vs. Output Voltage
TA = 25°C
0.6
0.8
1.25
1.0
0.75
10
Normalized ICC
0.50
Normalized Icc Vs. Cycle Time
Cycle Frequency (MHz)
Normalized tPC
25.0
30.0
20.0
10.0
5.0
0 200 400 600 800
Delta tAA (ns)
0
15.0
Supply Voltage (V)
Typical Power-on Current
Vs. Supply Voltage
CAPACITANCE (pF)
Typical Access Time Change
Vs. Output Loading
1000 28
0.2
0.6
1.2
ISB3
NORMALIZED ICC, ISB
0.2
0.4
ISB3
25
1.1
5.0
VCC = 5.0V
TA = 25°C
40
160
200
5.0
40 66
1.00
0.25
0 1.0 2.0 3.0 5.0
0.0 4.0
0.50
0.75
VCC = 5.0V
VCC = 5.0V
TA = 25°C
VCC = 4.5V
TA = 25°C
VIN = 5.0V
TA = 25°C
VCC = 5.0V
[+] Feedback
CY7C144E
Document #: 001-63982 Rev. *B Page 18 of 22
Ordering Information
Speed
(ns) Ordering Code
Package
Diagram Package Type Operating
Range
15 CY7C144E-15AXC 51-85046 64-pin TQFP (Pb-free) Commercial
CY7C144E-15JXI 51-85005 68-pin plastic leaded chip carrier (Pb-free) Industrial
CY7C144E-15AXI 51-85046 64-pin TQFP (Pb-free) Industrial
25 CY7C144E-25AXC 51-85046 64-pin Thin Quad Flat Pack (Pb-free) Commercial
55 CY7C144E-55AXC 51-85046 64-pin TQFP (Pb-free) Commercial
CY7C144E-55JXC 51-85005 68-pin plastic leaded chip carrier (Pb-free) Commercial
Ordering Code Definitions
Temperature Grade: I = Industrial, C = Commercial
Package Type = A/J, Pb-free = X
Speed Grade = 15 ns / 25 ns / 55 ns
Process Version R4 = E
Technology: CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
7CY C xxx I/C
xx xx
[+] Feedback
CY7C144E
Document #: 001-63982 Rev. *B Page 21 of 22
Acronyms
Reference Documents
CY7C144, CY7C145 8K × 8/9 Dual-Port Static RAM with SEM,
INT, BUSY (38-06034)
Document Conventions
Units of Measure
Table 6. Acronyms Used
Acronym Description
CMOS complementary metal oxide semiconductor
CE chip enable
I/O input/output
OE output enable
SRAM static random access memory
TSOP thin small outline package
WE write enable
Table 7. Units of Measure
Symbol Unit of Measure
ns nano second
Vvolt
µA micro ampere
mA milli ampere
pF pico Farad
°C degree Celsius
Wwatt
[+] Feedback
Document #: 001-63982 Rev. *B Revised October 12, 2011 Page 22 of 22
All products and company names mentioned in this document may be the trademarks of their respective holders.
CY7C144E
© Cypress Semiconductor Corporation, 2010-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document History Page
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive cypress.com/go/automotive
Clocks & Buffers cypress.com/go/clocks
Interface cypress.com/go/interface
Lighting & Power Control cypress.com/go/powerpsoc
cypress.com/go/plc
Memory cypress.com/go/memory
Optical & Image Sensing cypress.com/go/image
PSoC cypress.com/go/psoc
Touch Sensing cypress.com/go/touch
USB Controllers cypress.com/go/USB
Wireless/RF cypress.com/go/wireless
PSoC Solutions
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
Document Title: CY7C144E 8 K × 8 Dual-port Static RAM with SEM, INT, BUSY
Document Number: 001-63982
Revision ECN Orig. of
Change
Submission
Date Description of Change
** 3038037 ADMU 09/24/10 New data sheet
*A 3395887 ADMU 10/05/11 Changed status from Preliminary to Final.
Removed CY7C138E and related information.
*B 3403147 ADMU 10/12/2011 No technical updates.
[+] Feedback
