19-2437; Rev 1; 10/02 KIT ATION EVALU E L B AVAILA 4-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5 7 Matrix LED Display Driver Features High-Speed 26MHz with SPI-/QSPI-TM/ MICROWIRETM-Compatible Serial Interface 2.7V to 5.5V Operation Drives Four Monocolor or Two Bicolor CathodeRow 5 7 Matrix Displays Built-In ASCII 104-Character Font 24 User-Definable Characters Available Automatic Blinking Control for Each Segment 36A Low-Power Shutdown (Data Retained) 16-Step Digital Brightness Control Display Blanked on Power-Up Slew-Rate-Limited Segment Drivers for Lower EMI 36-Pin SSOP and 40-Pin DIP Packages Applications Message Boards Medical Equipment Audio/Video Equipment Industrial Displays Gaming Machines Ordering Information TEMP RANGE PIN-PACKAGE MAX6952EAX PART -40C to +85C 36 SSOP MAX6952EPL -40C to +85C 40 PDIP Pin Configurations appear at end of data sheet. SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. Typical Application Circuit DIGIT 0 3.3V V+ V+ 100nF 47F GND GND GND MAX6952 3.3V 4.7k CLK DIN CS DOUT BLINK OSC ISET CSET 26pF RSET 53.6k O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15 O16 O17 O18 O19 O20 O21 O22 O23 DIGIT 1 O14 O15 O16 O17 O18 C1 C2 C3 C4 C5 O19 O20 O21 O22 O23 C1 C2 C3 C4 C5 O0 R1 O0 R1 O1 R2 O1 R2 O2 R3 O2 R3 O3 R4 O3 R4 O4 R5 O4 R5 O5 R6 O5 R6 O6 R7 O6 R7 DIGIT 3 DIGIT 2 O14 O15 O16 O17 O18 C1 C2 C3 C4 C5 O19 O20 O21 O22 O23 C1 C2 C3 C4 C5 O7 R1 O7 R1 O8 R2 O8 R2 O9 R3 O9 R3 O10 R4 O10 R4 O11 R5 O11 R5 O12 R6 O12 R6 O13 R7 O13 R7 ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 MAX6952 General Description The MAX6952 is a compact cathode-row display driver that interfaces microprocessors to 5 7 dot-matrix LED displays through an SPITM-compatible serial interface. The MAX6952 drives up to four digits (140 LEDs). Included on chip are an ASCII 104-character font, multiplex scan circuitry, column and row drivers, and static RAM that stores each digit, as well as font data for 24 user-definable characters. The segment current for the LEDs is set by an internal digit-by-digit digital brightness control. The device includes a low-power shutdown mode, segment blinking (synchronized across multiple drivers, if desired), and a test mode that forces all LEDs on. The LED drivers are slew rate limited to reduce EMI. For a 2-wire interfaced version, refer to the MAX6953 data sheet. An EV kit is available for the MAX6952. MAX6952 4-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5 7 Matrix LED Display Driver ABSOLUTE MAXIMUM RATINGS Voltage (with respect to GND) V+ .............................................................................-0.3V to +6V All Other Pins................................................-0.3V to (V+ + 0.3V) O0-O13 Sink Current ....................................................... 500mA O14-O23 Source Current .................................................. 50mA Continuous Power Dissipation (TA = +70C) 36-Pin SSOP (derate 11.8mW/C above +70C) .....941.2mW 40-Pin PDIP (derate 16.7mW/C above +70C)........1333mW Operating Temperature Range (TMIN, TMAX) ......-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (Typical operating circuit, V+ = 3.0V to 5.5V, TA = TMIN to TMAX, unless otherwise noted.) (Note 1) PARAMETER SYMBOL Operating Supply Voltage V+ Shutdown Supply Current ISHDN Operating Supply Current I+ CONDITIONS MIN TYP 2.7 Shutdown mode, all digital inputs at V+ or GND TA = TMIN to TMAX TA = +25C MAX UNITS 5.5 V 100 A 36 80 All segments on, intensity set to full, internal oscillator, DOUT open circuit, no display load connected, blink open circuit 12 16 4 mA Master Clock Frequency (OSC Internal Oscillator) fOSC OSC = RC oscillator, RSET = 53.6k, CSET = 26pF Master Clock Frequency (OSC External Oscillator) fOSC OSC overdriven externally Dead Clock Protection Frequency fOSC 90 kHz OSC Internal/External Detection Threshold VOSC 1.7 V OSC High Time tCH OSC Low Time tCL Slow Segment Blink Period (OSC Internal Oscillator) Fast Segment Blink Period (OSC Internal Oscillator) 1 MHz 8 MHz 50 ns 50 ns fSLOWBLINK OSC = RC oscillator, RSET = 53.6k, CSET = 26pF 1 s fFASTBLINK OSC = RC oscillator, RSET = 53.6k, CSET = 26pF 0.5 s Fast or Slow Segment Duty Cycle (Note 2) 49.5 -32 50.5 Column Drive Source Current ICOLUMN VLED = 2.4V, V+ = 3.0V, TA = +25C Segment Current Slew Rate ISEG/t TA = +25oC 12.5 mA/s ISEG TA = +25oC 4 % Segment Drive Current Matching (Within IC) 2 -48 % _______________________________________________________________________________________ mA 4-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5 7 Matrix LED Display Driver (Typical operating circuit, V+ = 3.0V to 5.5V, TA = TMIN to TMAX, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LOGIC INPUTS AND OUTPUTS Input High Voltage DIN, CLK, CS VIH Input Low Voltage DIN, CLK, CS VIL Input Leakage DIN, CLK, CS, OSC IIH, IIL DOUT Output Low Voltage VOLDO 2.4 -2 ISINK = 1.6mA DOUT Output High Voltage VOHDO ISOURCE = 1.6mA Blink Output Low Voltage VOLBK ISINK = 1.6mA V +0.1 0.4 V +2 A 0.4 V V+ - 0.4V V 0.4 V TIMING CHARACTERISTICS (Figure 1) CLK Clock Period tCP 38.4 ns CLK Pulse Width High tCH 19 ns CLK Pulse Width Low tCL 19 ns CS Fall to CLK Rise Setup Time tCSS 9.5 ns CLK Rise to CS Rise Hold Time tCSH 5 ns DIN Setup Time tDS 9.5 ns DIN Hold Time tDH 0 ns CS Pulse High tCSW 19 ns DOUT Propagation Delay tDO CLOAD = 10pF 19 ns Note 1: All parameters tested at TA = +25C. Specifications over temperature are guaranteed by design. Note 2: Guaranteed by design. _______________________________________________________________________________________ 3 MAX6952 DC ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (Typical application circuit, V+ = 3.3V, LED forward voltage = 2.4V, scan limit set to 4 digits, TA = +25C, unless otherwise noted.) INTERNAL OSCILLATOR FREQUENCY vs. SUPPLY VOLTAGE V+ = 3.3V 4.00 V+ = 5V 3.90 4.3 4.2 2.0 VOLTAGE AT OSC (V) 4.10 2.5 MAX6952 toc02 V+ = 2.7V 4.20 4.4 OSCILLATOR FREQUENCY (MHz) MAX6952 toc01 4.30 INTERNAL OSCILLATOR WAVEFORM AT OSC 4.1 4.0 3.9 MAX6952 toc03 INTERNAL OSCILLATOR FREQUENCY vs. TEMPERATURE OSCILLATOR FREQUENCY (MHz) 1.5 1.0 3.8 0.5 3.7 3.6 3.80 -40 -20 0 20 40 60 0 2.5 80 3.5 5.5 4.5 0 SEGMENT SOURCE CURRENT vs. SUPPLY VOLTAGE CURRENT NORMALIZED TO 40mA 95 90 85 80 MAX6952 toc05 1.01 MAX6952 toc04 100 1.00 0.99 0.98 0.97 0.96 0.95 2.5 3.0 3.5 4.0 4.5 5.0 2.5 5.5 SUPPLY VOLTAGE (V) 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) MAX6952 toc06 WAVEFORMS AT O2 (PIN 3) AND O14 (PIN 28) 15/16 INTENSITY GROUND FOR ANODE (PIN O14) GROUND FOR CATHODE (PIN O3) 4 600 TIMELINE (ns) DEAD CLOCK OSCILLATOR FREQUENCY vs. SUPPLY VOLTAGE 105 400 200 SUPPLY VOLTAGE (V) TEMPERATURE (C) OSCILLATOR FREQUENCY (kHz) MAX6952 4-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5 7 Matrix LED Display Driver 220ms/div _______________________________________________________________________________________ 5.0 5.5 800 4-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5 7 Matrix LED Display Driver PIN NAME FUNCTION SSOP PDIP 1, 2, 3, 6-14, 23, 24 1, 2, 3, 7-15, 26, 27 O0 to O13 4, 5, 16 4, 5, 6, 18 GND Ground 15 17 ISET Segment Current Setting. Connect ISET to GND through series resistor RSET to set the peak current. 17 19 BLINK 18 20 DIN Serial Data Input. Data is loaded into the internal 16-bit shift register on the rising edge of the CLK. Serial-Clock Input. On the rising edge of CLK, data is shifted into the internal shift register. On the falling edge of CLK, data is clocked out of DOUT. CLK input is active only while CS is low. LED Cathode Drivers. O0 to O13 outputs sink current from the display's cathode rows. Blink Clock Output. Output is open drain. 19 21 CLK 20 22 DOUT 21 23 CS Chip-Select Input. Serial data is loaded into the shift register while CS is low. The last 16 bits of serial data are latched on CS's rising edge. 22 24 OSC Multiplex Clock Input. To use the internal oscillator, connect capacitor CSET from OSC to GND. To use the external clock, drive OSC with a 1MHz to 8MHz CMOS clock. 25-31, 34, 35, 36 28-34, 38, 39, 40 O14 to O23 32, 33 35, 36, 37 V+ Detailed Description The MAX6952 is a serially interfaced display driver that can drive four digits of 5 7 cathode-row dot-matrix displays. The MAX6952 can drive either four monocolor digits (Table 1) or two bicolor digits (Table 2). The MAX6952 includes a 128-character font map comprising 104 predefined characters and 24 user-definable characters. The predefined characters follow the Arial font, with the addition of the following common symbols: , , , , , , , and . The 24 user-definable characters are uploaded by the user into on-chip RAM through the serial interface and are lost when the device is powered down. Figure 1 is the MAX6952 functional diagram. Serial Data Output. Data clocked into DIN is output to DOUT 15.5 clock cycles later. Data is clocked out on the rising edge of CLK. Output is push-pull. LED Anode Drivers. O14 to O23 outputs source current to the display's anode columns. Positive Supply Voltage. Bypass V+ to GND with a 47F bulk capacitor and a 0.1F ceramic capacitor. Serial Interface The MAX6952 communicates through an SPI-compatible 4-wire serial interface. The interface has three inputs, clock (CLK), chip select (CS), and data in (DIN), and one output, data out (DOUT). CS must be low to clock data into or out of the device, and DIN must be stable when sampled on the rising edge of CLK. DOUT is stable on the rising edge of CLK. Note that while the SPI protocol expects DOUT to be high impedance when the MAX6952 is not being accessed, DOUT on the MAX6952 is never high impedance. _______________________________________________________________________________________ 5 MAX6952 Pin Description MAX6952 4-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5 7 Matrix LED Display Driver Table 1. Connection Scheme for Four Monocolor Digits DIGIT O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15 O16 O17 O18 O19 O20 O21 O22 O23 1 Digit 0 rows (cathodes) R1 to R7 Digit 1 rows (cathodes) R1 to R7 -- Digit 0 columns (anodes) C1 to C5 Digit 1 columns (anodes) C6 to C10 2 -- Digit 2 rows (cathodes) R1 to R7 Digit 3 rows (cathodes) R1 to R7 Digit 2 columns (anodes) C1 to C5 Digit 3 columns (anodes) C6 to C10 Table 2. Connection Scheme for Two Bicolor Digits DIGIT O0 O1 O2 O3 O4 1 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15 O16 O17 O18 O19 O20 O21 O22 O23 Digit 0 rows (cathodes) R1 to R14 2 Digit 0 columns (anodes) C1 to C10 -- -- - the 5 green anodes - Digit 1 rows (cathodes) R1 to R14 - the 5 red anodes - Digit 1 columns (anodes) C1 to C10 - the 5 green anodes - the 5 red anodes - Table 3. Serial-Data Format (16 Bits) D15 R/W ISET OSC D14 D13 D12 D10 D7 CURRENT SOURCE PWM BRIGHTNESS CONTROL DIVIDER/ COUNTER NETWORK ROW MULTIPLEXER D6 D5 D4 D3 D2 DATA D1 D0 LSB CLK and DIN may be used to transmit data to other peripherals. The MAX6952 ignores all activity on CLK and DIN except when CS is low. LED DRIVERS CHARACTER GENERATOR ROM BLINK SPEED SELECT RAM MAX6952 O0 TO O23 Control and Operation Using the 4-Wire Interface Controlling the MAX6952 requires sending a 16-bit word. The first byte, D15 through D8, is the command byte (Table 3), and the second byte, D7 through D0, is the data byte. Connecting Multiple MAX6952s to the 4-Wire Bus Multiple MAX6952s may be daisy-chained by connecting the DOUT of one device to the DIN of the next, and driving CLK and CS lines in parallel (Figure 6). Data at DIN propagates through the internal shift registers and appears at DOUT 15.5 clock cycles later, clocked out on the falling edge of CLK. When sending commands to daisy-chained MAX6952s, all devices are accessed at the same time. An access requires (16 x n) clock cycles, where n is the number of MAX6952s connected together. To update just one device in a daisy-chain, the user can send the no-op command (0x00) to the others. SERIAL INTERFACE Figure 1. Functional Diagram 6 D8 MSB CONFIGURATION REGISTERS CLK CS DIN DOUT D9 ADDRESS CHARACTER GENERATOR RAM BLINK D11 Writing Device Registers The MAX6952 contains a 16-bit shift register into which DIN data are clocked on the rising edge of SCLK, when CS is low. When CS is high, transitions on SCLK have no effect. When CS goes high, the 16 bits in the shift _______________________________________________________________________________________ 4-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5 7 Matrix LED Display Driver 5) Take CLK low. Figure 3 shows a write operation when 16 bits are transmitted. If fewer or greater than 16 bits are clocked into the MAX6952 between taking CS low and taking CS high again, the MAX6952 stores the last 16 bits received, including the previous transmission(s). The general case is when n bits (where n > 16) are transmitted to the MAX6952. The last bits comprising bits {n-15} to {n} are retained and are parallel loaded into the 16-bit latch as bits D15 to D0, respectively (Figure 4). Reading Device Registers Any register data within the MAX6952 may be read by sending a logic high to bit D15. The sequence is: 1) Take CLK low. 2) Take CS low. This enables the internal 16-bit shift register. 3) Clock 16 bits of data into DIN, D15 first to D0 last, observing the setup and hold times. Bit D15 is high, indicating a read command and bits D14 through D8 contain the address of the register to read. Bits D7 to D0 contain dummy data, which is discarded. Take CS high. Positions D7 through D0 in the shift register are now loaded with the data in the register addressed by bits D15 through D8. Bits Take CLK low. Issue another read or write command (which can be a no-op), and examine the bit stream at DOUT; the second 8 bits are the contents of the register addressed by bits D14 through D8 in step 3. 4) 5) 6) Digit Registers The MAX6952 uses eight digit registers to store the characters that the user wishes to display on the four 5 7 LED digits. These digit registers are implemented with two planes of 4 bytes, called P0 and P1. Each LED digit is represented by 2 bytes of memory, 1 byte in plane P0 and the other in plane P1. The digit registers are mapped so that a digit's data can be updated in plane P0, or plane P1, or both planes at the same time (Table 4). If the blink function is disabled through the Blink Enable Bit E (Table 9) in the configuration register, then the digit register data in plane P0 is used to multiplex the display. The digit register data in P1 is not used. If the blink function is enabled, then the digit register data in both plane P0 and plane P1 are alternately used to multiplex the display. Blinking is achieved by multiplexing the LED display using data planes P0 and P1 on alternate phases of the blink clock (Table 10). The data in the digit registers does not control the digit segments directly. Instead, the register data is used to address a character generator, which stores the data of a 128-character font (Table 14). The lower 7 bits of the digit data (D6 to D0) select the character from the font. The most-significant bit of the register data (D7) selects whether the font data is used directly (D7 = 0) or whether the font data is inverted (D7 = 1). The inversion feature can be used to enhance the appearance of bicolor displays by displaying, for example, a red character on a green background. Display Blink Mode The display blinking facility, when enabled, makes the driver flip automatically between displaying the digit register data in planes P0 and P1. If the digit register data for any digit is different in the two planes, then that digit appears to flip between two characters. To make a character appear to blink on or off, write the character to one plane, and use the blank character (0x20) for the other plane. Once blinking has been configured, it continues automatically without further intervention. Blink Speed The blink speed is determined by frequency of the multiplex clock, OSC, and by setting the Blink Rate Selection Bit B (Table 8) in the configuration register. The Blink Rate Selection Bit B sets either fast or slow blink speed for the whole display. Initial Power-Up On initial power-up, all control registers are reset, the display is blanked, intensities are set to minimum, and shutdown is enabled (Table 5). Configuration Register The configuration register is used to enter and exit shutdown, select the blink rate, globally enable and disable the blink function, globally clear the digit data, and reset the blink timing (Table 6). _______________________________________________________________________________________ 7 MAX6952 register are parallel loaded into a 16-bit latch. The 16 bits in the latch are then decoded and executed. The MAX6952 is written to using the following sequence: 1) Take CLK low. 2) Take CS low. This enables the internal 16-bit shift register. 3) Clock 16 bits of data into DIN, D15 first to D0 last, observing the setup and hold times. Bit D15 is low, indicating a write command. 4) Take CS high (while CLK is still high after clocking in the last data bit). MAX6952 4-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5 7 Matrix LED Display Driver tCSW CS tCL tCSS CLK tDS DIN tCH tCSH tCP tDH D15 D14 D1 D0 tDO D15 DOUT TIMING NOT TO SCALE. Figure 2. Timing Diagram CS CLK DIN D15 =0 D13 D14 D11 D12 D10 D9 D8 D6 D7 D5 D4 D3 D2 D1 D0 D15 = 0 DOUT Figure 3. 16-Bit Write Transmission to the MAX6952 CS CLK DIN BIT 1 DOUT N-15 N-14 N-13 N-12 N-11 N-31 N-30 N-29 N-28 N-27 N-10 N-9 N-8 N-7 N-6 N-5 N-4 N-3 N-2 N-1 N-26 N-25 N-24 N-23 N-22 N-21 N-20 N-19 N-18 N-17 TIMING NOT TO SCALE. Figure 4. Transmission of More than 16 Bits to the MAX6952 8 N BIT 2 _______________________________________________________________________________________ N-16 N-15 4-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5 7 Matrix LED Display Driver MAX6952 Table 4. Register Address Map ADDRESS (COMMAND BYTE) REGISTER HEX CODE D15 D14 D13 D12 D11 D10 D9 D8 No-Op R/W 0 0 0 0 0 0 0 0x00 Intensity10 R/W 0 0 0 0 0 0 1 0x01 Intensity32 R/W 0 0 0 0 0 1 0 0x02 Scan-Limit R/W 0 0 0 0 0 1 1 0x03 Configuration R/W 0 0 0 0 1 0 0 0x04 User-Defined Fonts R/W 0 0 0 0 1 0 1 0x05 Factory reserved. Do not write to this. R/W 0 0 0 0 1 1 0 0x06 Display Test R/W 0 0 0 0 1 1 1 0x07 Digit 0 Plane P0 R/W 0 1 0 0 0 0 0 0x20 Digit 1 Plane P0 R/W 0 1 0 0 0 0 1 0x21 Digit 2 Plane P0 R/W 0 1 0 0 0 1 0 0x22 Digit 3 Plane P0 R/W 0 1 0 0 0 1 1 0x23 Digit 0 Plane P1 R/W 1 0 0 0 0 0 0 0x40 Digit 1 Plane P1 R/W 1 0 0 0 0 0 1 0x41 Digit 2 Plane P1 R/W 1 0 0 0 0 1 0 0x42 Digit 3 Plane P1 R/W 1 0 0 0 0 1 1 0x43 Write Digit 0 Plane P0 and Plane P1 with Same Data (Reads as 0x00) R/W 1 1 0 0 0 0 0 0x60 Write Digit 1 Plane P0 and Plane P1 with Same Data (Reads as 0x00) R/W 1 1 0 0 0 0 1 0x61 Write Digit 2 Plane P0 and Plane P1 with Same Data (Reads as 0x00) R/W 1 1 0 0 0 1 0 0x62 Write Digit 3 Plane P0 and Plane P1 with Same Data (Reads as 0x00) R/W 1 1 0 0 0 1 1 0x63 _______________________________________________________________________________________ 9 MAX6952 4-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5 7 Matrix LED Display Driver Shutdown Mode (S Data Bit D0) Format The S bit in the configuration register selects shutdown or normal operation (Table 7). The display driver can be programmed while in shutdown mode, and shutdown mode is overridden when in display test mode. For normal operation, the S bit should be set to 1. Blink Rate Selection (B Data Bit D2) Format The B bit in the configuration register selects the blink rate. This is the speed that the segments alternate between plane P0 and plane P1 refresh data. The blink rate is determined by the frequency of the multiplex clock OSC, in addition to the setting of the B bit (Table 8). Global Blink Enable/Disable (E Data Bit D3) Format The E bit globally enables or disables the blink feature of the device (Table 9). When blink is globally enabled, then the digit data in both planes P0 and P1 are used to control the display (Table 10). Table 5. Initial Power-Up Register Status REGISTER DATA POWER-UP CONDITION ADDRESS CODE (HEX) D7 D6 D5 D4 D3 D2 D1 D0 Intensity10 1/16 (min on) 0x01 0 0 0 0 0 0 0 0 Intensity32 1/16 (min on) 0x02 0 0 0 0 0 0 0 0 Scan Limit Display 4 digits: 0 1 2 3 0x03 X X X X X X X 1 Shutdown enabled, blink speed is slow, blink disabled 0x04 0 X 0 0 0 0 X 0 Address 0x80; pointing to the first user-defined font location 0x05 1 0 0 0 0 0 0 0 REGISTER Configuration User-Defined Font Address Pointer Display Test Normal operation 0x07 X X X X X X X 0 Digit 0 Plane P0 Blank digit (0x20) 0x20 0 0 1 0 0 0 0 0 Digit 1 Plane P0 Blank digit (0x20) 0x21 0 0 1 0 0 0 0 0 Digit 2 Plane P0 Blank digit (0x20) 0x22 0 0 1 0 0 0 0 0 Digit 3 Plane P0 Blank digit (0x20) 0x23 0 0 1 0 0 0 0 0 Digit 0 Plane P1 Blank digit (0x20) 0x40 0 0 1 0 0 0 0 0 Digit 1 Plane P1 Blank digit (0x20) 0x41 0 0 1 0 0 0 0 0 Digit 2 Plane P1 Blank digit (0x20) 0x42 0 0 1 0 0 0 0 0 Digit 3 Plane P1 Blank digit (0x20) 0x43 0 0 1 0 0 0 0 0 Table 7. Shutdown Control (S Data Bit D0) Format Table 6. Configuration Register Format REGISTER Configuration Register 10 REGISTER DATA D7 P D6 X D5 R D4 T D3 E D2 B D1 X D0 S MODE REGISTER DATA D7 D6 D5 D4 D3 D2 D1 D0 Shutdown Mode P X R T E B X 0 Normal Operation P X R T E B X 1 ______________________________________________________________________________________ 4-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5 7 Matrix LED Display Driver Global Blink Timing Synchronization (T Data Bit D4) Format By setting the T bit in multiple MAX6952s at the same time (or in quick succession), the blink timing can be synchronized across all the devices (Table 11). Note that the display multiplexing sequence is also reset, which might give rise to a one-time display flicker when the register is written. Global Clear Digit Data (R Data Bit D5) Format When global digit data clear is set, the digit data for both planes P0 and P1 for all digits is cleared (Table 12). DOUT DIN CLK CLK CS CS DOUT Blink Phase Readback (P Data Bit D7) Format When the configuration register is read, the P bit reflects the state of the blink output pin at that time (Table 13). Character Generator Font Mapping The font is a 5 7 matrix comprising 104 characters in ROM, and 24 user-definable characters. The selection from the total of 128 characters is represented by the lower 7 bits of the 8-bit digit registers. The most-significant bit, shown as x in the ROM map below, is zero to light LEDs as shown by the black segments in Table 14, and 1 to display the inverse. The character map follows the Arial font for 96 characters in the x0101000 through x1111111 range. The first CLK MAX6952 DOUT DIN DIN CLK MAX6952 MAX6952 DOUT MICROCONTROLLER CS CS DIN Figure 6. MAX6952 Daisy-Chain Connection Table 8. Blink Rate Selection (B Data Bit D2) Format REGISTER DATA MODE Slow blinking (Segments are refreshed using plane P0 for 1s, plane P1 for 1s, for OSC = 4MHz.) D7 D6 D5 D4 D3 D2 D1 D0 P X R T E 0 X S Table 9. Global Blink Enable/Disable (E Data Bit D3) Format MODE REGISTER DATA D7 D6 D5 D4 D3 D2 D1 D0 Blink function is disabled. P X R T 0 B X S Blink function is enabled. P X R T 1 B X S ______________________________________________________________________________________ 11 MAX6952 When blink is globally disabled, then only the digit data in plane P0 is used to control the display. The digit data in plane P1 is ignored. MAX6952 4-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5 7 Matrix LED Display Driver indirectly accesses the font data. The font address pointer can be written, setting one of 120 addresses between 0x00 and 0xF7, but cannot be read back. The font data is written to and read from the MAX6952 indirectly, using this font address pointer. Unused font locations can be used as general-purpose scratch RAM, bearing in mind that the font registers are only 7 bits wide, not 8. Table 15 shows how the single user-defined font register 0x05 is used to set the font address pointer, write font data, and read font data. A read action always returns font data from the font address pointer position. A write action sets the 7-bit font address pointer if the MSB is set, or writes 7-bit font data to the font address pointer position if the MSB is clear. Table 10. Digit Register Mapping with Blink Globally Enabled SEGMENT'S BIT SETTING IN PLANE P1 SEGMENT'S BIT SETTING IN PLANE P0 0 0 Segment off 0 1 Segment on only during the 1st half of each blink period 1 0 Segment on only during the 2nd half of each blink period 1 1 Segment on SEGMENT BEHAVIOR The font address pointer autoincrements after a valid access to the user-definable font data. Autoincrementing allows the 120 font data entries to be written and read back very quickly because the font pointer address need only be set once. When the last data location 0xF7 is written, the font address pointer autoincrements to address 0x80. If the font address pointer is set to an out-of-range address by writing data in the 0xF8 to 0xFF range, then address 0x80 is set instead (Table 16). 32 characters map the 24 user-definable positions (RAM00 to RAM23), plus eight extra common characters in ROM. User-Defined Fonts The 24 user-definable characters are represented by 120 entries of 7-bit data, five entries per character, and are stored in the MAX6952's internal RAM. The 120 user-definable font data entries are written and read through a single register, address 0x05. An autoincrementing font address pointer in the MAX6952 Table 17 shows the user-definable font pointer base addresses. Table 11. Global Blink Timing Synchronization (T Data Bit D4) Format MODE REGISTER DATA D7 D6 D5 D4 D3 D2 D1 D0 Blink timing counters are unaffected. P X R 0 E B X S Blink timing counters are reset on the rising edge of CS. P X R 1 E B X S Table 12. Global Clear Digit Data (R Data Bit D5) Format MODE REGISTER DATA D7 D6 D5 D4 D3 D2 D1 D0 Digit data for both planes P0 and P1 are unaffected. P X 0 T E B X S Digit data for both planes P0 and P1 are cleared on the rising edge of CS. P X 1 T E B X S Table 13. Blink Phase Readback (P Data Bit D7) Format MODE REGISTER DATA D7 D6 D5 D4 D3 D2 D1 D0 P1 Blink Phase 0 X R T E B X S P0 Blink Phase 1 X R T E B X S 12 ______________________________________________________________________________________ 4-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5 7 Matrix LED Display Driver MSB x000 x001 0000 RAM00 RAM16 0001 RAM01 RAM17 0010 RAM02 RAM18 0011 RAM03 RAM19 0100 RAM04 RAM20 0101 RAM05 RAM21 0110 RAM06 RAM22 0111 RAM07 RAM23 1000 RAM08 1001 RAM09 1010 RAM10 LSB 1011 RAM11 1100 RAM12 1101 RAM13 1110 RAM14 1111 RAM15 x010 x011 x100 x101 x110 x111 Table 19 shows the six sequential write commands required to set a MAX6953's font character RAM02 with the data to display character 2 given in the font RAM illustration above. Multiplex Clock and Blink Timing The OSC pin can be fitted with capacitor CSET to GND (to use the internal RC multiplex oscillator), or driven by an external clock. The multiplex clock frequency determines the multiplex scan rate and the blink timing. The display scan rate is calculated by dividing the frequency at OSC by 5600. With OSC at 4 MHz, each display digit is enabled for 100s and the display scan rate is 714.29Hz. The on-chip oscillator may be accurate enough for applications using a single device. If an exact blink rate is required, use an external clock ranging between 1MHz and 8MHz to drive OSC. The OSC inputs of multiple MAX6952s can be tied together to a common external clock to make the devices blink at the same rate. The relative blink phasing of multiple MAX6952s can be synchronized by setting the T bit in the control register for all the devices in quick succession (Table 11). If the serial interfaces of multiple MAX6952s are daisychained by connecting DOUT of one device to DIN of the next, then synchronization is achieved automatically by updating the control register for all devices together. For MAX6952s, the devices can be synchronized by transmitting the serial data for the control register, and then toggling the CS pin for each device, either together or in quick succession. Figure 7 is the multiplex timing diagram. Blink Output The blink output indicates the blink phase, and is high during the P0 period and low during the P1 period. Blink phase status can also be read back as the P bit in the configuration register (Table 13). Typical uses for this output are: * To provide an interrupt to the processor so that segment data can be changed synchronous to the blinking. For example, a clock application may have colon segments blinking every second between hours and minute digits, and the minute display is best changed in step with the colon segments. Also, if the rising edge of blink is detected, there is half a blink period to change the P1 digit data. Similarly, if the falling edge of blink is detected, the user has half a blink period to change the P0 digit data. ______________________________________________________________________________________ 13 MAX6952 Table 18 shows an example of data (characters 0, 1, and 2) being stored in the first three user-defined font locations, illustrating the orientation of the data bits. Table 14. Character Map MAX6952 4-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5 7 Matrix LED Display Driver Table 15. Memory Mapping of User-Defined Font Register 0x05 ADDRESS CODE (HEX) REGISTER DATA SPI READ OR WRITE FUNCTION 0x85 0x00-0x7F Read Read 7-bit user-definable font data entry from current font address. MSB of the register data is clear. Font address pointer is incremented after the read. 0x05 0x00-0x7F Write Write 7-bit user-definable font data entry to current font address. Font address pointer is incremented after the write. 0x05 0x80-0xFF Write Write font address pointer with the register data. Table 16. Font Pointer Address Behavior FONT POINTER ADDRESS ACTION 0x80 to 0xF6 Valid range to set the font address pointer. Pointer autoincrements after a font data read or write, while pointer address remains in this range. 0xF7 0xF8 to 0xFF Font address resets to 0x80 after a font data read or write to this pointer address. Invalid range to set the font address pointer. Pointer is set to 0x80 if address. * If OSC is driven with an accurate frequency, blink can be used as a seconds counter or similar. Scan-Limit Register The scan-limit register sets how many monocolor digits are displayed, either two or four. A bicolor digit is connected as two monocolor digits. The multiplexing scheme drives digits 0 and 1 at the same time, then digits 2 and 3 at the same time. To increase the effective brightness of the displays, drive only two digits instead of four. By doing this, the average segment current doubles, but also doubles the number of MAX6952s required to drive a given number of digits. Because digit 1 is driven at the same time as digit 0 (and digit 3 is driven at the same time as digit 2), only 1 bit is used to set the scan limit. The bit is clear if one or two digits are to be driven, and set if three or four digits are to be driven (Table 20). Change the scan-limit register only when the MAX6952 is in shutdown mode. Intensity Registers Display brightness is controlled digitally by four pulsewidth modulators, one for each display digit. Each digit is controlled by a nibble of one of the two intensity registers, Intensity10 and Intensity32. The modulator scales the average segment current in 16 steps from a maximum of 15/16 down to 1/16 of the peak current. The minimum interdigit blanking time is, therefore, 1/16 of a cycle. The maximum duty cycle is 15/16. (Tables 21 and 22). 14 No-Op Register A write to the no-op register is ignored. Selecting External Components RSET and CSET to Set Oscillator Frequency and Segment Current The RC oscillator uses an external resistor RSET and an external capacitor CSET to set the oscillator frequency, fOSC. The allowed range of fOSC is 1MHz to 8MHz. RSET also sets the peak segment current. The recommended values of RSET and CSET set the oscillator to 4MHz, which makes the blink frequencies 0.5Hz and 1Hz. The recommended value of RSET also sets the peak current to 40mA, which makes the segment current adjustable from 2.5mA to 37.5mA in 2.5mA steps: ISEG = KI / RSET mA fOSC = KF / (RSET CSET + CSTRAY) MHz Where: KI = 2144 KF = 6000 RSET = external resistor in k CSET = external capacitor in pF CSTRAY = stray capacitance from OSC pin to GND in pF, typically 2pF The recommended value of RSET is 53.6k and the recommended value of CSET is 26pF. ______________________________________________________________________________________ 4-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5 7 Matrix LED Display Driver MAX6952 Table 17. User-Definable Font Pointer Base Address Table REGISTER DATA FONT CHARACTER ADDRESS CODE (HEX) REGISTER DATA (HEX) D7 D6 D5 D4 D3 D2 D1 D0 RAM00 0x05 0x80 1 0 0 0 0 0 0 0 RAM01 0x05 0x85 1 0 0 0 0 1 0 1 RAM02 0x05 0x8A 1 0 0 0 1 0 1 0 RAM03 0x05 0x8F 1 0 0 0 1 1 1 1 RAM04 0x05 0x94 1 0 0 1 0 1 0 0 RAM05 0x05 0x99 1 0 0 1 1 0 0 1 RAM06 0x05 0x9E 1 0 0 1 1 1 1 0 RAM07 0x05 0xA3 1 0 1 0 0 0 1 1 RAM08 0x05 0xA8 1 0 1 0 1 0 0 0 RAM09 0x05 0xAD 1 0 1 0 1 1 0 1 RAM10 0x05 0xB2 1 0 1 1 0 0 1 0 RAM11 0x05 0xB7 1 0 1 1 0 1 1 1 RAM12 0x05 0xBC 1 0 1 1 1 1 0 0 RAM13 0x05 0xC1 1 1 0 0 0 0 0 1 RAM14 0x05 0xC6 1 1 0 0 0 1 1 0 RAM15 0x05 0xCB 1 1 0 0 1 0 1 1 RAM16 0x05 0xD0 1 1 0 1 0 0 0 0 RAM17 0x05 0xD5 1 1 0 1 0 1 0 1 RAM18 0x05 0xDA 1 1 0 1 1 0 1 0 RAM19 0x05 0xDF 1 1 0 1 1 1 1 1 RAM20 0x05 0xE4 1 1 1 0 0 1 0 0 RAM21 0x05 0xE9 1 1 1 0 1 0 0 1 RAM22 0x05 0xEE 1 1 1 0 1 1 1 0 RAM23 0x05 0xF3 1 1 1 1 0 0 1 1 The recommended value of R SET is the minimum allowed value since it sets the display driver to the maximum allowed segment current. RSET can be set to a higher value to set the segment current to a lower peak value where desired. The user must also ensure that the peak current specifications of the LEDs connected to the driver are not exceeded. The effective value of CSET includes not only the actual external capacitor used, but also the stray capacitance from OSC to GND. This capacitance is usually in the 1pF to 5pF range, depending on the layout used. Display-Test Register The display-test register switches the drivers between one of two modes: normal and display test. Display-test mode turns all LEDs on by overriding, but not altering, all control and digit registers (including the shutdown register). In display-test mode, eight digits are scanned and the duty cycle is 7/16 (half power). Table 23 lists the display-test register format. Applications Information Choosing Supply Voltage to Minimize Power Dissipation The MAX6952 drives a peak current of 40mA into LEDs with a 2.4V forward-voltage drop when operated from a supply voltage of at least 3.0V. The minimum voltage drop across the internal LED drivers is, therefore (3.0V 2.4V) = 0.6V. If a higher supply voltage is used, the driver absorbs a higher voltage, and the driver's power dissipation increases accordingly. However, if the LEDs used have a higher forward voltage drop than 2.4V, the supply voltage must be raised accordingly to ensure that the driver always has at least 0.6V headroom. ______________________________________________________________________________________ 15 MAX6952 4-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5 7 Matrix LED Display Driver Table 18. User-Definable Character Storage Example FONT CHARACTER FONT ADDRESS POINTER ADDRESS CODE (HEX) FONT POINTER ADDRESS (HEX) D7 D6 D5 D4 D3 D2 D1 D0 RAM00 0x00 0x05 0x80 0 0 1 1 1 1 1 0 RAM00 0x01 0x05 0x81 0 1 0 1 0 0 0 1 RAM00 0x02 0x05 0x82 0 1 0 0 1 0 0 1 RAM00 0x03 0x05 0x83 0 1 0 0 0 1 0 1 RAM00 0x04 0x05 0x84 0 0 1 1 1 1 1 0 RAM01 0x05 0x05 0x85 0 0 0 0 0 0 0 0 RAM01 0x06 0x05 0x86 0 1 0 0 0 0 1 0 RAM01 0x07 0x05 0x87 0 1 1 1 1 1 1 1 RAM01 0x08 0x05 0x88 0 1 0 0 0 0 0 0 RAM01 0x09 0x05 0x89 0 0 0 0 0 0 0 0 RAM02 0x0A 0x05 0x8A 0 1 0 0 0 0 1 0 RAM02 0x0B 0x05 0x8B 0 1 1 0 0 0 0 1 RAM02 0x0C 0x05 0x8C 0 1 0 1 0 0 0 1 RAM02 0x0D 0x05 0x8D 0 1 0 0 1 0 0 1 RAM02 0x0E 0x05 0x8E 0 1 0 0 0 1 1 0 REGISTER DATA Table 19. Setting a Font Character to RAM Example ADDRESS CODE (HEX) REGISTER DATA (HEX) 0x05 0x8A Set font address pointer to the base address of font character RAM02. 0x05 0x42 1st 7 bits of data: 1000010 goes to font address 0x8A; pointer then autoincrements to address 0x8B. 0x05 0x61 2nd 7 bits of data: 1100001 goes to font address 0x8B; pointer then autoincrements to address 0x8C. 0x05 0x51 3rd 7 bits of data: 1010001 goes to font address 0x8C; pointer then autoincrements to address 0x8D. 0x05 0x49 4th 7 bits of data: 1001001 goes to font address 0x8D; pointer then autoincrements to address 0x8E. 0x05 0x46 5th 7 bits of data: 1000110 goes to font address 0x8E; pointer then autoincrements to address 0x8F. ACTION BEING PERFORMED Table 20. Scan Limit Register Format SCAN LIMIT ADDRESS CODE (HEX) REGISTER DATA Display digits 0 and 1 only 0x03 D7 X Display digits 0, 1, 2, and 3 0x03 X 16 D6 X D5 X D4 X D3 X D2 X D1 X D0 0 X X X X X X 1 ______________________________________________________________________________________ HEX CODE 0xX0 0xX1 4-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5 7 Matrix LED Display Driver DUTY CYCLE TYPICAL SEGMENT CURRENT (mA) ADDRESS CODE (HEX) 1/16 (min on) 2.5 0x01, 0x02 0 0 0 0 0xX0 2/16 5 0x01, 0x02 0 0 0 1 0xX1 3/16 7.5 0x01, 0x02 0 0 1 0 0xX2 4/16 10 0x01, 0x02 0 0 1 1 0xX3 5/16 12.5 0x01, 0x02 0 1 0 0 0xX4 6/16 15 0x01, 0x02 0 1 0 1 0xX5 7/16 17.5 0x01, 0x02 0 1 1 0 0xX6 8/16 20 0x01, 0x02 0 1 1 1 0xX7 9/16 22.5 0x01, 0x02 1 0 0 0 0xX8 10/16 25 0x01, 0x02 1 0 0 1 0xX9 11/16 27.5 0x01, 0x02 1 0 1 0 0xXA 12/16 30 0x01, 0x02 1 0 1 1 0xXB 13/16 32.5 0x01, 0x02 1 1 0 0 0xXC 14/16 35 0x01, 0x02 1 1 0 1 0xXD 15/16 37.5 0x01, 0x02 1 1 1 0 0xXE 15/16 (max on) 37.5 0x01, 0x02 1 1 1 1 0xXF D7 D6 D5 D4 See Table 22. D3 D2 D1 D0 HEX CODE Table 22. Intensity Register Format for Digit 1 (Address 0x01) and Digit 3 (Address 0x02) DUTY CYCLE TYPICAL SEGMENT CURRENT (mA) ADDRESS CODE (HEX) D7 D6 D5 D4 1/16 (min on) 2.5 0x01, 0x02 0 0 0 0 0x0X 2/16 5 0x01, 0x02 0 0 0 1 0x1X 3/16 7.5 0x01, 0x02 0 0 1 0 0x2X 4/16 10 0x01, 0x02 0 0 1 1 0x3X 5/16 12.5 0x01, 0x02 0 1 0 0 0x4X 6/16 15 0x01, 0x02 0 1 0 1 0x5X 7/16 17.5 0x01, 0x02 0 1 1 0 8/16 20 0x01, 0x02 0 1 1 1 D3 D2 D1 D0 HEX CODE 0x6X See Table 21. 0x7X 9/16 22.5 0x01, 0x02 1 0 0 0 10/16 25 0x01, 0x02 1 0 0 1 0x9X 11/16 27.5 0x01, 0x02 1 0 1 0 0xAX 12/16 30 0x01, 0x02 1 0 1 1 0xBX 13/16 32.5 0x01, 0x02 1 1 0 0 0xCX 14/16 35 0x01, 0x02 1 1 0 1 0xDX 15/16 37.5 0x01, 0x02 1 1 1 0 0xEX 15/16 (max on) 37.5 0x01, 0x02 1 1 1 1 0xFX 0x8X ______________________________________________________________________________________ 17 MAX6952 Table 21. Intensity Register Format for Digit 0 (Address 0x01) and Digit 2 (Address 0x02) MAX6952 4-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5 7 Matrix LED Display Driver Table 23. Display-Test Register Format REGISTER DATA MODE ADDRESS CODE (HEX) D7 D6 D5 D4 D3 D2 D1 D0 Normal operation 0x07 X X X X X X X 0 Display test 0x07 X X X X X X X 1 The voltage drop across the drivers with a nominal 5V supply (5.0V - 2.4V) = 2.6V is nearly 3 times the drop across the drivers with a nominal 3.3V supply (3.3V 2.4V) = 0.9V. In most systems, consumption is an important design criterion, and the MAX6952 should be operated from the system's 3.3V nominal supply. In other designs, the lowest supply voltage may be 5V. The issue now is to ensure the dissipation limit for the MAX6952 is not exceeded. This can be achieved by inserting a series resistor in the supply to the MAX6952, ensuring that the supply decoupling capacitors are still on the MAX6952 side of the resistor. For example, consider the requirement that the minimum supply voltage to a MAX6952 must be 3.0V, and the input supply range is 5V 5%. sity dims uniformly as supply voltage drops out of regulation and beyond. The MAX6952 operates down to 2.5V supply voltage (although most displays are very dim at this voltage), provided that the MAX6952 is powered up initially to at least 2.7V to trigger the device's internal reset. Maximum supply current is: 12mA + (40mA x 10) = 412mA N = number of segments driven (worst case is 10) VLED = LED forward voltage ISEG = segment current set by RSET Minimum input supply voltage is 4.75V. Maximum series resistor value is: (4.75V - 3.0V) / 0.412A = 4.25 We choose 3.3 5%. Worst-case resistor dissipation is at maximum toleranced resistance, i.e., (0.412A) 2 x (3.3 1.05) = 0.577W. We choose a 1W resistor rating. The maximum MAX6952 supply voltage is at maximum input supply voltage and minimum toleranced resistance, i.e., 5.25V - (0.412A x 3.3 0.95) = 3.97V. Low-Voltage Operation The MAX6952 works over the 2.7V to 5.5V supply range. The minimum useful supply voltage is determined by the forward voltage drop of the LEDs at the peak current ISEG, plus the 0.6V headroom required by the driver output stages. The MAX6952 correctly regulates ISEG with a supply voltage above this minimum voltage. If the supply drops below this minimum voltage, the driver output stages may brown out, and be unable to regulate the current correctly. As the supply voltage drops further, the LED segment drive current becomes effectively limited by the output driver's onresistance, and the LED drive current drops. The characteristics of each individual LED in a 5 7 matrix digit are well matched, so the result is that the display inten18 Computing Power Dissipation The upper limit for power dissipation (PD) for the MAX6952 is determined from the following equation: PD = (V+ 12mA) + (V+ - VLED) (DUTY x ISEG N) where: V+ = supply voltage Duty = duty cycle set by intensity register PD = power dissipation, in mW if currents are in mA Dissipation example: ISEG = 40mA, N = 10, Duty = 15 / 16, VLED = 2.4V at 40mA, V+ = 3.6V PD = 3.6V (12mA) + (3.6V - 2.4V)(15 / 16 40mA 10) = 0.493W Thus, for a 36-pin SSOP package (TJA = 1 / 0.0118 = +85C/W from operating ratings), the maximum allowed ambient temperature TA is given by: TJ(MAX) = TA + (PD TJA) = +150C = TA + (0.493 +85C/W) So, TA = +108C. Thus, the part can be operated safely at a maximum package temperature of +85C. Power Supplies The MAX6952 operates from a single 2.7V to 5.5V power supply. Bypass the power supply to GND with a 0.1F capacitor as close to the device as possible. Add a 47F capacitor if the MAX6952 is not close to the board's input bulk decoupling capacitor. ______________________________________________________________________________________ 4-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5 7 Matrix LED Display Driver MAX6952 START OF NEXT CYCLE ONE COMPLETE 1.4ms MULTIPLEX CYCLE AROUND 14 ROWS 100s COLUMN DRIVER PINS O14-O18 DIGIT 0 ROW 1 DIGIT 0 ROW 2 DIGIT 0 ROW 3 DIGIT 0 ROW 4 DIGIT 0 ROW 5 DIGIT 0 ROW 6 DIGIT 0 ROW 7 DIGIT 2 ROW 1 DIGIT 2 ROW 2 DIGIT 2 ROW 3 DIGIT 2 ROW 4 DIGIT 2 ROW 5 DIGIT 2 ROW 6 DIGIT 2 ROW 7 DIGIT 0 ROW 1 COLUMN DRIVER PINS O19-O23 DIGIT 1 ROW 1 DIGIT 1 ROW 2 DIGIT 1 ROW 3 DIGIT 1 ROW 4 DIGIT 1 ROW 5 DIGIT 1 ROW 6 DIGIT 1 ROW 7 DIGIT 3 ROW 1 DIGIT 3 ROW 2 DIGIT 3 ROW 3 DIGIT 3 ROW 4 DIGIT 3 ROW 5 DIGIT 3 ROW 6 DIGIT 3 ROW 7 DIGIT 1 ROW 1 DIGIT 1 COLUMN DRIVER OUTPUTS PINS O19-O23 CURRENT SOURCE 1/16TH (MIN ON) DIGIT 1 ROW 1's 100s MULTIPLEX TIMESLOT HIGH-Z CURRENT SOURCE 2/16TH HIGH-Z CURRENT SOURCE 3/16TH HIGH-Z CURRENT SOURCE 4/16TH HIGH-Z CURRENT SOURCE 5/16TH HIGH-Z CURRENT SOURCE 6/16TH HIGH-Z CURRENT SOURCE 7/16TH HIGH-Z CURRENT SOURCE 8/16TH HIGH-Z CURRENT SOURCE 9/16TH HIGH-Z CURRENT SOURCE 10/16TH HIGH-Z CURRENT SOURCE 11/16TH HIGH-Z CURRENT SOURCE 12/16TH HIGH-Z CURRENT SOURCE 13/16TH HIGH-Z CURRENT SOURCE 14/16TH HIGH-Z CURRENT SOURCE 15/16TH HIGH-Z CURRENT SOURCE 16/16TH HIGH-Z (MAX ON) DIGITS 0 & 1 ROW OUTPUTS PINS O0-O6 DIGITS 2 & 3 ROW OUTPUTS PINS O7-O13 MINIMUM 6.25s INTERDIGIT BLANKING INTERVAL HIGH-Z HIGH-Z LOW HIGH-Z HIGH-Z Figure 7. Multiplex Timing Diagram (OSC = 4MHz) ______________________________________________________________________________________ 19 MAX6952 4-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5 7 Matrix LED Display Driver Board Layout Chip Information When designing a board, use the following guidelines: 1) The RSET connection to the ISET pin is a high-impedance node, and sensitive to layout. Place RSET right next to the ISET pin and route RSET directly to these pins with very short tracks. 2) Ensure that the track from the ground end of RSET routes directly to GND pin 18 (PDIP package) or GND pin 16 (SSOP package), and that this track is not used as part of any other ground connection. TRANSISTOR COUNT: 43,086 PROCESS: CMOS Pin Configurations TOP VIEW O0 1 40 O23 O0 1 36 O23 O1 2 39 O22 O1 2 35 O22 O2 3 34 O21 O2 3 38 O21 GND 4 37 V+ GND 4 33 V+ 5 32 V+ GND 5 36 V+ GND GND 6 35 V+ O3 6 31 O20 O3 7 34 O20 O4 7 30 O19 8 29 O18 9 O4 8 33 O19 O5 O5 9 32 O18 O6 O6 10 31 O17 O7 10 27 O16 O8 11 26 O15 MAX6952 MAX6952 28 O17 O7 11 30 O16 O8 12 29 O15 O9 12 25 O14 24 O13 O9 13 28 O14 O10 13 O10 14 27 O13 O11 14 23 O12 O11 15 26 O12 ISET 15 22 OSC 21 CS N.C. 16 25 N.C. GND 16 17 24 OSC BLINK 17 ISET 23 CS 19 22 DOUT 20 21 CLK GND 18 BLINK DIN 20 DOUT DIN 18 19 CLK SSOP PDIP 20 ______________________________________________________________________________________ 4-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5 7 Matrix LED Display Driver SSOP.EPS 36 E DIM A A1 B C e E H L D H INCHES MILLIMETERS MAX MIN 0.096 0.104 0.004 0.011 0.012 0.017 0.009 0.013 0.0315 BSC 0.291 0.299 0.398 0.414 0.040 0.020 0.598 0.612 MAX MIN 2.65 2.44 0.29 0.10 0.44 0.30 0.23 0.32 0.80 BSC 7.40 7.60 10.11 10.51 0.51 15.20 1.02 15.55 1 TOP VIEW D A1 e A B C 0 -8 L FRONT VIEW SIDE VIEW PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE, 36L SSOP, 0.80 MM PITCH APPROVAL DOCUMENT CONTROL NO. 21-0040 REV. E 1 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 21 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX6952 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)