SEMICONDUCTOR TECHNICAL DATA The MC74VHCT00A is an advanced high speed CMOS 2-input NAND gate fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The VHCT inputs are compatible with TTL levels. This device can be used as a level converter for interfacing 3.3V to 5.0V, because it has full 5V CMOS level output swings. The VHCT00A input structures provide protection when voltages between 0V and 5.5V are applied, regardless of the supply voltage. The output structures also provide protection when VCC = 0V. These input and output structures help prevent device destruction caused by supply voltage - input/output voltage mismatch, battery backup, hot insertion, etc. * * * * * * * * * * * D SUFFIX 14-LEAD SOIC PACKAGE CASE 751A-03 High Speed: tPD = 5.0ns (Typ) at VCC = 5V Low Power Dissipation: ICC = 2A (Max) at TA = 25C TTL-Compatible Inputs: VIL = 0.8V; VIH = 2.0V Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Designed for 4.5V to 5.5V Operating Range Low Noise: VOLP = 0.8V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300mA ESD Performance: HBM > 2000V; Machine Model > 200V Chip Complexity: 48 FETs or 12 Equivalent Gates DT SUFFIX 14-LEAD TSSOP PACKAGE CASE 948G-01 M SUFFIX 14-LEAD SOIC EIAJ PACKAGE CASE 965-01 ORDERING INFORMATION MC74VHCTXXAD MC74VHCTXXADT MC74VHCTXXAM LOGIC DIAGRAM A1 B1 A2 B2 A3 B3 A4 B4 1 3 2 Y1 FUNCTION TABLE 4 6 5 Y2 Inputs Y = AB 9 8 10 Y3 12 11 13 Y4 Pinout: 14-Lead Packages (Top View) VCC B4 A4 Y4 B3 A3 Y3 14 13 12 11 10 9 8 1 2 3 4 5 6 7 A1 B1 Y1 A2 B2 Y2 GND 6/97 Motorola, Inc. 1997 SOIC TSSOP SOIC EIAJ 1 REV 0 Output A B Y L L H H L H L H H H H L MC74VHCT00A IIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIII IIIIII III IIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIII IIIIII III III IIIIIIIIIIIIII IIIIII III III IIIIIIIIIIIIII IIIIII III III IIIIIIIIIIIIII IIIIII III III IIIIIIIIIIIIII IIIIII III III IIIIIIIIIIIIII IIIIII III III IIIIIIIIIIIIII IIIIII III III IIIIIIIIIIIIII IIIIII III III IIIIIIIIIIIIII IIIIII III III IIIIIIIIIIIIII IIIIII III III IIIIIIIIIIIIII IIIIII III III IIIIIIIIIIIIII IIIIII III MAXIMUM RATINGS* Symbol Value Unit DC Supply Voltage - 0.5 to + 7.0 V Vin DC Input Voltage - 0.5 to + 7.0 V Vout DC Output Voltage - 0.5 to + 7.0 - 0.5 to VCC + 0.5 V IIK Input Diode Current - 20 mA IOK Output Diode Current (VOUT < GND; VOUT > VCC) 20 mA Iout DC Output Current, per Pin 25 mA ICC DC Supply Current, VCC and GND Pins 50 mA PD Power Dissipation in Still Air, 500 450 mW Tstg Storage Temperature - 65 to + 150 _C VCC Parameter VCC = 0 High or Low State SOIC Packages TSSOP Package This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open. v v * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Derating -- SOIC Packages: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C IIII IIIIIIIIIIIIII III III III IIII IIIIIIIIIIIIII III III III IIII IIIIIIIIIIIIII III III III IIII IIIIIIIIIIIIII III III III IIII IIIIIIIIIIIIII III III III IIII IIIIIIIIIIIIII III III III IIII IIIIIIIIIIIIII III III III IIII IIIIIIIIIIIIII III III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIII IIIIIII IIII IIIIIIII IIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III IIII III IIII IIII IIII IIIIIII IIIIIII IIII IIIIIIII IIIIIII II IIII IIIIIII IIIIIII IIII III IIII III IIII IIII II IIII IIIIIII IIIIIII IIII III IIII III IIII IIII II IIIIIIIIIIIIIIIIIIII IIII IIIIIII IIIIIII IIII II IIII IIIIIII IIIIIII IIII III IIII III IIII IIII IIII IIIIIII IIIIIII IIII III IIII III IIII IIII II IIII IIIIIII IIIIIII IIII III IIII III IIII IIII II IIII IIIIIII IIIIIII IIII III IIII III IIII IIII II IIII IIIIIII IIIIIII IIII III IIII III IIII IIII II II IIII IIIIIII IIIIIII IIII III IIII III IIII IIII IIII IIIIIII IIIIIII IIII III IIII III IIII IIII II III III IIII IIIIIII IIIIIII IIII IIII IIII IIII II II IIII IIIIIII IIIIIII IIII III IIII III IIII IIII III III IIII IIIIIII IIIIIII IIII IIII IIII IIIIII II IIII IIIIIII IIIIIII IIII III IIII III IIII IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Min Max Unit 4.5 5.5 V 0 5.5 V 0 0 5.5 VCC V - 40 + 85 _C 0 20 ns/V DC Supply Voltage Vin DC Input Voltage Vout DC Output Voltage TA Operating Temperature tr, tf Input Rise and Fall Time VCC = 0 High or Low State VCC =5.0V 0.5V DC ELECTRICAL CHARACTERISTICS S b l Symbol P Parameter T Test C Conditions di i VCC V TA = 25C Min VIH Minimum High-Level Input Voltage 4.5 to 5.5 VIL Maximum Low-Level Input Voltage 4.5 to 5.5 VOH Minimum High-Level Output Voltage Vin = VIH or VIL IOH = - 50A 4.5 4.4 IOH = - 8mA 4.5 3.94 Maximum Low-Level Output Voltage Vin = VIH or VIL IOL = 50A 4.5 IOL = 8mA VOL Typ TA = - 40 to 85C Max 2.0 Min Max 2.0 0.8 4.5 U i Unit V 0.8 4.4 V V 3.80 0.0 0.1 0.1 4.5 0.36 0.44 V Maximum Input Leakage Current Vin = 5.5 V or GND 0 to 5.5 0.1 1.0 A Maximum Quiescent Supply Current Vin = VCC or GND 5.5 2.0 20.0 A ICCT Quiescent Supply Current Per Input: VIN = 3.4V Other Input: VCC or GND 5.5 1.35 1.50 mA IOPD Output Leakage Current VOUT = 5.5V 0 0.5 5.0 A Iin ICC MOTOROLA 2 VHC Data - Advanced CMOS Logic DL203 -- Rev 1 MC74VHCT00A IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIII IIIIIIIII IIIIIIIII IIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIII IIIIIIIII IIII III IIII III IIII II IIIIIIIII IIIIII IIII IIIIIIII IIIIIIIII IIII III IIII III IIII II IIII IIIIIIII IIIIIIIII IIII III IIII III IIII II II IIII IIIIIIII IIIIIIIII IIII III IIII III IIII IIII IIIIIIII IIIIIIIII IIII III IIII III IIII II AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns) TA = 25C S b l Symbol P Parameter tPLH, tPHL Propagation Delay, A or B to Y Cin T Test C Conditions di i VCC = 5.0 0.5V CL = 15pF CL = 50pF Input Capacitance Min TA = - 40 to 85C Typ Max Min Max 5.0 5.5 6.9 7.9 1.0 1.0 8.0 9.0 4 10 10 U i Unit pF Typical @ 25C, VCC = 5.0V CPD P Power Dissipation Di i i Capacitance C i (N (Note NO TAG) pF F 17 1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 4 (per gate). CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC. NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V, Measured in SOIC Package) TA = 25C S b l Symbol Typ Max U i Unit VOLP Quiet Output Maximum Dynamic VOL Ch Characteristic i i 0.4 0.8 V VOLV Quiet Output Minimum Dynamic VOL - 0.4 - 0.8 V VIHD Minimum High Level Dynamic Input Voltage 2.0 V VILD Maximum Low Level Dynamic Input Voltage 0.8 V TEST POINT A or B 3V OUTPUT 1.5V DEVICE UNDER TEST GND tPLH tPHL CL* VOH Y 1.5V VOL * Includes all probe and jig capacitance Figure 1. Switching Waveforms VHC Data - Advanced CMOS Logic DL203 -- Rev 1 Figure 2. Test Circuit 3 MOTOROLA MC74VHCT00A OUTLINE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751A-03 ISSUE F NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. -A- 14 8 P 7 PL -B- 1 0.25 (0.010) 7 G D 0.25 (0.010) T M F J M K 14 PL M R X 45 C SEATING PLANE B M B S A S DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.75 8.55 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 BSC 0.25 0.19 0.25 0.10 7 0 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 7 0 0.228 0.244 0.010 0.019 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948G-01 ISSUE O 14X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. S S N 2X 14 L/2 0.25 (0.010) 8 M B -U- L PIN 1 IDENT. F 7 1 0.15 (0.006) T U N S DETAIL E K A -V- EEE CCC CCC EEE K1 J J1 SECTION N-N -W- C 0.10 (0.004) -T- SEATING PLANE MOTOROLA D G H DETAIL E 4 DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ VHC Data - Advanced CMOS Logic DL203 -- Rev 1 MC74VHCT00A OUTLINE DIMENSIONS M SUFFIX PLASTIC SOIC EIAJ PACKAGE CASE 965-01 ISSUE O 14 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). LE 8 Q1 E HE L 7 1 M_ DETAIL P Z D VIEW P A e c A1 b 0.13 (0.005) M 0.10 (0.004) DIM A A1 b c D E e HE 0.50 LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 1.42 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.056 Motorola reserves the right to make changes without further notice to any products herein. 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