OUT
IN
GND
LP38512-ADJ
VIN VOUT
EN
VEN
CIN
10 PF
Ceramic COUT
10 PF
Ceramic
GND GND
ON
OFF CFF
ADJ
R1
R2
LP38512-ADJ
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LP38512-ADJ 1.5A Fast-Transient Response Adjustable Low-Dropout Linear Voltage
Regulator
Check for Samples: LP38512-ADJ
1FEATURES APPLICATIONS
2• 2.25V to 5.5V Input Voltage Range • Digital Core ASICs, FPGAs, and DSPs
• Adjustable Output Voltage Range of 0.5V to • Servers
4.5V • Routers and Switches
• 1.5A Output Load Current • Base Stations
• ±2.0% Accuracy over Line, Load, and Full- • Storage Area Networks
Temperature Range from -40°C to +125°C • DDR2 Memory
• Stable with Tiny 10 µF Ceramic Capacitors DESCRIPTION
• Enable Pin The LP38512-ADJ Fast-Transient Response Low-
Dropout Voltage Regulator offers the highest-
• Typically Less than 1µA of Ground Pin Current performance in meeting AC and DC accuracy
in when Enable Pin is Low requirements for powering Digital Cores. The
• 25dB of PSRR at 100 kHz LP38512-ADJ uses a proprietary control loop that
• Over-Temperature and Over-Current enables extremely fast response to change in line
Protection conditions and load demands. Output Voltage DC
accuracy is specified at 2.5% over line, load and full
• 8-Pin SO PowerPad and 5-Pin PFM Surface temperature range from -40°C to +125°C. The
Mount Packages LP38512-ADJ is designed for inputs from the 2.5V,
3.3V, and 5.0V rail, is stable with 10 μF ceramic
capacitors, and has an adjustable output voltage. The
LP38512-ADJ provides excellent transient
performance to meet the demand of high
performance digital core ASICs, DSPs, and FPGAs
found in highly-intensive applications such as servers,
routers/switches, and base stations.
Typical Application Circuit
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2009–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
DAP
Connect to GND
IN
EN
IN
GND5
6
7
8
OUT
OUT
N/C
ADJ
1
2
3
4
Exposed
DAP
OUT
GND
EN 1
2
3
4
5
IN
LP38512TJ-ADJ
ADJ
LP38512-ADJ
SNVS546D –JANUARY 2009–REVISED APRIL 2013
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Connection Diagram
Figure 1. 5-Pin PFM, Top View Figure 2. 8-Pin SO PowerPad, Top View
See NDQ0005A Package See DDA0008A Package
PIN DESCRIPTIONS FOR PFM PACKAGE
Pin # Pin Name Function
Enable. Pull high to enable the output, low to disable the output. This pin has no internal bias and
1 EN must be tied to the input voltage, or actively driven.
2 IN Input Supply Pin
3 GND Ground
4 OUT Regulated Output Voltage Pin
5 ADJ The feedback to the internal Error Amplifier to set the output voltage
The PFM DAP is used as a thermal connection to remove heat from the device to an external heat-
sink in the form of the copper area on the printed circuit board. The DAP is physically connected to
DAP DAP backside of the die, but is not internally connected to device ground. The DAP should be soldered to
the Ground Plane copper.
PIN DESCRIPTIONS FOR SO PowerPad PACKAGE
Pin # Pin Name Function
1, 2 OUT Regulated Output Voltage Pin. Pins share current and must be connected together.
3 ADJ The feedback to the internal Error Amplifier to set the output voltage
4 N/C No internal connection.
5 GND Ground
Enable. Pull high to enable the output, low to disable the output. This pin has no internal bias and
6 EN must be tied to the input voltage, or actively driven.
7, 8 IN Input Supply Pin. Pins share current and must be connected together.
TheSO PowerPad DAP connection is used as a thermal connection to remove heat from the device
to an external heat-sink in the form of the copper area on the printed circuit board. The DAP is
DAP DAP physically connected to backside of the die, but is not internally connected to device ground. The
DAP should be soldered to the Ground Plane copper.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Absolute Maximum Ratings(1)
Storage Temperature Range −65°C to +150°C
PFM 260°C, 10s
Soldering Temperature(2) SO PowerPad 260°C, 10s
ESD Rating(3) ±2 kV
Power Dissipation(4) Internally Limited
Input Pin Voltage (Survival) -0.3V to +6.0V
Enable Pin Voltage (Survival) -0.3V to +6.0V
Output Pin Voltage (Survival) -0.3V to +6.0V
ADJ Pin Voltage (Survival) -0.3V to +6.0V
IOUT (Survival) Internally Limited
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but does not ensure specific performance limits. For ensured specifications and conditions,
see the Electrical Characteristics.
(2) Refer to JEDEC J-STD-020C for surface mount device (SMD) package reflow profiles and conditions. Unless otherwise stated, the
temperatures and times are for Sn-Pb (STD) only.
(3) The human body model is a 100 pF capacitor discharged through a 1.5 kΩresistor into each pin. Test method is per JESD22-A114.
(4) Device operation must be evaluated, and derated as needed, based on ambient temperature (TA), power dissipation (PD), maximum
allowable operating junction temperature (TJ(MAX)), and package thermal resistance (θJA).The typical θJA ratings given are worst case
based on minimum land area on two-layer PCB (EIA/JESD51-3). See POWER DISSIPATION/HEAT-SINKING for details.
Operating Ratings(1)
Input Supply Voltage, VIN 2.25V to 5.5V
Output Voltage, VOUT VADJ to 5V
Enable Input Voltage, VEN 0.0V to 5.5V
Output Current (DC) 1 mA to 1.5A
Junction Temperature(2) −40°C to +125°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but does not ensure specific performance limits. For ensured specifications and conditions,
see the Electrical Characteristics.
(2) Device operation must be evaluated, and derated as needed, based on ambient temperature (TA), power dissipation (PD), maximum
allowable operating junction temperature (TJ(MAX)), and package thermal resistance (θJA).The typical θJA ratings given are worst case
based on minimum land area on two-layer PCB (EIA/JESD51-3). See POWER DISSIPATION/HEAT-SINKING for details.
Electrical Characteristics
Unless otherwise specified: VIN= 2.50V, VOUT= VADJ, IOUT= 10 mA, CIN= 10 µF, COUT= 10 µF, VEN= 2.0V. Limits in standard
type are for TJ= 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C.
Minimum and Maximum limits are ensured through test, design, or statistical correlation. Typical values represent the most
likely parametric norm at TJ= 25°C, and are provided for reference purposes only.
Symbol Parameter Conditions Min Typ Max Units
2.25V ≤VIN ≤5.5V 495.0 505.0
VADJ VADJ Accuracy(1) 500. mV
10 mA ≤IOUT ≤1.5A 490.0 510.0
IADJ ADJ Pin Bias Current 2.25V ≤VIN ≤5.5V - 1 - nA
0.03
ΔVADJ/ΔVIN VADJ Line Regulation(2)(1) 2.25V ≤VIN ≤5.5V - - %/V
0.06
0.10
ΔVADJ/ΔIOUT VADJ Load Regulation(3)(1) 10 mA ≤IOUT ≤1.5A - - %/A
0.20
VDO Dropout Voltage(4) IOUT = 1.5A - - 300 mV
(1) The line and load regulation specification contains only the typical number. However, the limits for line and load regulation are included
in the output voltage tolerance specification.
(2) Line regulation is defined as the change in VADJ from the nominal value due to change in the voltage at the input.
(3) Load regulation is defined as the change in VADJ from the nominal value due to change in the load current at the output.
(4) Dropout voltage (VDO) is typically defined as the input to output voltage differential (VIN - VOUT) where the input voltage is low enough to
cause the output voltage to drop 2%. For the LP38512-ADJ, the minimum operating voltage of 2.25V is the limiting factor when the
programed output voltage is less than typically 1.80V.
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Electrical Characteristics (continued)
Unless otherwise specified: VIN= 2.50V, VOUT= VADJ, IOUT= 10 mA, CIN= 10 µF, COUT= 10 µF, VEN= 2.0V. Limits in standard
type are for TJ= 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C.
Minimum and Maximum limits are ensured through test, design, or statistical correlation. Typical values represent the most
likely parametric norm at TJ= 25°C, and are provided for reference purposes only.
Symbol Parameter Conditions Min Typ Max Units
12
IOUT = 10 mA - 10 15
Ground Pin Current, Output mA
Enabled 12
IGND IOUT = 1.5A - 10 14
Ground Pin Current, Output 100
VEN = 0.50V - 60 µA
Disabled 110
ISC Short Circuit Current VOUT = 0V - 2.8 - A
Enable Input
VEN rising from < VEN(OFF) until VOUT 0.90 1.50
VEN(ON) Enable ON Voltage Threshold 1.20 V
= ON 0.80 1.60
VEN falling from > VEN(ON) until VOUT 0.60 1.40
VEN(OFF) Enable OFF Voltage Threshold 1.00 V
= OFF 0.50 1.50
VEN(HYS) Enable Voltage Hysteresis VEN(ON) - VEN(OFF) - 200 - mV
VEN = VIN - 1 -
IEN Enable Pin Current nA
VEN = 0V - -1 -
Time from VEN < VEN(TH) to VOUT =
td(OFF) Turn-off delay - 5 -
OFF, ILOAD = 1.5A µs
Time from VEN >VEN(TH) to VOUT =
td(ON) Turn-on delay - 5 -
ON, ILOAD = 1.5A
AC Parameters
VIN = 2.5V - 73 -
f = 120Hz
PSRR Ripple Rejection dB
VIN = 2.5V - 70 -
f = 1 kHz
ρn(l/f) Output Noise Density f = 120Hz - 0.4 - µV/√Hz
enOutput Noise Voltage BW = 10Hz - 100kHz - 25 - µVRMS
Thermal Characteristics
TSD Thermal Shutdown TJrising - 165 - °C
ΔTSD Thermal Shutdown Hysteresis TJfalling from TSD - 10 -
SO PowerPad - 168 -
Thermal Resistance
θJ-A °C/W
Junction to Ambient(5) PFM - 67 -
SO PowerPad - 11 -
Thermal Resistance
θJ-C °C/W
Junction to Case PFM - 3 -
(5) Device operation must be evaluated, and derated as needed, based on ambient temperature (TA), power dissipation (PD), maximum
allowable operating junction temperature (TJ(MAX)), and package thermal resistance (θJA).The typical θJA ratings given are worst case
based on minimum land area on two-layer PCB (EIA/JESD51-3). See POWER DISSIPATION/HEAT-SINKING for details.
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Typical Performance Characteristics
Unless otherwise specified: TJ= 25°C, VIN = 2.50V, VOUT= VADJ, VEN = 2.0V, CIN = 10 µF, COUT = 10 µF, IOUT = 10 mA.
VADJ VOUT
vs vs
Temperature VIN
Figure 3. Figure 4.
Ground Pin Current (IGND) Ground Pin Current (IGND)
vs vs
VIN Temperature
Figure 5. Figure 6.
Ground Pin Current (IGND) Enable Threshold
vs vs
Temperature Temperature
Figure 7. Figure 8.
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Typical Performance Characteristics (continued)
Unless otherwise specified: TJ= 25°C, VIN = 2.50V, VOUT= VADJ, VEN = 2.0V, CIN = 10 µF, COUT = 10 µF, IOUT = 10 mA.
VOUT Load regulation
vs vs
VEN Temperature
Figure 9. Figure 10.
Line Regulation Current Limit
vs vs
Temperature Temperature
Figure 11. Figure 12.
Load Transient 10 mA to 1.5A Load Transient, 10 mA to 1.5A
VOUT = VADJ, COUT = 10 μF Ceramic VOUT = 1.20V, COUT = 10 μF Ceramic
Figure 13. Figure 14.
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Typical Performance Characteristics (continued)
Unless otherwise specified: TJ= 25°C, VIN = 2.50V, VOUT= VADJ, VEN = 2.0V, CIN = 10 µF, COUT = 10 µF, IOUT = 10 mA.
Load Transient, 500 mA to 1.5A Line Transient
VOUT = 1.20V, COUT = 10 μF Ceramic VOUT = VADJ, COUT = 10 μF Ceramic
Figure 15. Figure 16.
Line Transient PSRR, IOUT = 100 mA
VOUT = 1.20V, COUT = 10 μF Ceramic VOUT = VADJ, COUT = 10 μF Ceramic
Figure 17. Figure 18.
PSRR, IOUT = 1.5A Output Noise Density
VOUT = VADJ, COUT = 10 μF Ceramic VOUT = VADJ, COUT = 10 μF Ceramic
Figure 19. Figure 20.
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APPLICATION INFORMATION
EXTERNAL CAPACITORS
Like any low-dropout regulator, external capacitors are required to assure stability. These capacitors must be
correctly selected for proper performance.
Input Capacitor
A ceramic input capacitor of at least 10 µF is required. For general usage across all load currents and operating
conditions, a 10 µF ceramic input capacitor will provide satisfactory performance.
Output Capacitor
A ceramic capacitor with a minimum value of 10 µF is required at the output pin for loop stability. It must be
located less than 1 cm from the device and connected directly to the output and ground pin using traces which
have no other currents flowing through them. As long as the minimum of 10 µF ceramic is met, there is no
limitation on any additional capacitance.
X7R and X5R dielectric ceramic capacitors are strongly recommended, as they typically maintain a capacitance
range within ±20% of nominal over full operating ratings of temperature and voltage. Of course, they are typically
larger and more costly than Z5U/Y5U types for a given voltage and capacitance.
Z5U and Y5V dielectric ceramics are not recommended as the capacitance will drop severely with applied
voltage. A typical Z5U or Y5V capacitor can lose 60% of its rated capacitance with half of the rated voltage
applied to it. The Z5U and Y5V also exhibit a severe temperature effect, losing more than 50% of nominal
capacitance at high and low limits of the temperature range.
REVERSE VOLTAGE
A reverse voltage condition will exist when the voltage at the output pin is higher than the voltage at the input pin.
Typically this will happen when VIN is abruptly taken low and COUT continues to hold a sufficient charge such that
the input to output voltage becomes reversed. A less common condition is when an alternate voltage source is
connected to the output.
There are two possible paths for current to flow from the output pin back to the input during a reverse voltage
condition.
While VIN is high enough to keep the control circuity alive, and the Enable pin is above the VEN(ON) threshold, the
control circuitry will attempt to regulate the output voltage. Since the input voltage is less than the programmed
output voltage, the control circuit will drive the gate of the pass element to the full on condition when the output
voltage begins to fall. In this condition, reverse current will flow from the output pin to the input pin, limited only
by the RDS(ON) of the pass element and the output to input voltage differential. Discharging an output capacitor up
to 1000 µF in this manner will not damage the device as the current will rapidly decay. However, continuous
reverse current should be avoided. When the Enable is low this condition will be prevented.
The internal PFET pass element in the LP38512-ADJ has an inherent parasitic diode. During normal operation,
the input voltage is higher than the output voltage and the parasitic diode is reverse biased. However, if the
output voltage to input voltage differential is more than 500 mV (typical) the parasitic diode becomes forward
biased and current flows from the output pin to the input pin through the diode. The current in the parasitic diode
should be limited to less than 1A continuous and 5A peak.
If used in a dual-supply system where the regulator output load is returned to a negative supply, the output pin
must be diode clamped to ground. A Schottky diode is recommended for this protective clamp.
SHORT-CIRCUIT PROTECTION
The LP38512-ADJ is short circuit protected, and in the event of a peak over-current condition the short-circuit
control loop will rapidly drive the output PMOS pass element off. Once the power pass element shuts down, the
control loop will rapidly cycle the output on and off until the average power dissipation causes the thermal
shutdown circuit to respond to servo the on/off cycling to a lower frequency. Please refer to the POWER
DISSIPATION/HEAT-SINKING section for power dissipation calculations.
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SETTING THE OUTPUT VOLTAGE
The output voltage is set using the external resistive divider R1 and R2. The output voltage is given by the
formula:
VOUT = VADJ x (1 + (R1/R2)) (1)
The resistors used for R1 and R2 should be high quality, tight tolerance, and with matching temperature
coefficients. It is important to remember that, although the value of VADJ is specified, the final value of VOUT is
not. The use of low quality resistors for R1 and R2 can easily produce a VOUT value that is unacceptable.
It is recommended that the values selected for R1 and R2 are such that the parallel value is less than 1.00 kΩ.
This is to reduce the possibility of any internal parasitic capacitances on the ADJ pin from creating an
undesirable phase shift that may interfere with device stability.
( (R1 x R2) / (R1 + R2) ) ≤1.00 kΩ(2)
FEED FORWARD CAPACITOR, CFF
When using a ceramic capacitor for COUT, the typical ESR value will be too small to provide any meaningful
positive phase compensation, FZ, to offset the internal negative phase shifts in the gain loop.
FZ= 1 / (2 x πx COUT x ESR) (3)
A capacitor placed across the gain resistor R1 will provide additional phase margin to improve load transient
response of the device. This capacitor, CFF, in parallel with R1, will form a zero in the loop response given by the
formula:
FZ= 1 / (2 x πx CFF x R1) (4)
For optimum load transient response select CFF so the zero frequency, FZ, falls between 20 kHz and 40 kHz.
CFF = 1 / (2 x πx R1 x FZ) (5)
The phase lead provided by CFF diminishes as the DC gain approaches unity, or VOUT approaches VADJ. This is
because CFF also forms a pole with a frequency of:
FP= 1 / (2 x πx CFF x (R1 || R2) ) (6)
It's important to note that at higher output voltages, where R1 is much larger than R2, the pole and zero are far
apart in frequency. At lower output voltages the frequency of the pole and the zero mover closer together. The
phase lead provided from CFF diminishes quickly as the output voltage is reduced, and has no effect when VOUT
= VADJ. For this reason, relying on this compensation technique alone is adequate only for higher output
voltages.
Table 1 lists some suggested, best fit, standard ±1% resistor values for R1 and R2, and a standard ±10%
capacitor values for CFF, for a range of VOUT values. Other values of R1, R2, and CFF are available that will give
similar results.
Table 1.
VOUT R1R2CFF FZ
0.80V 1.07 kΩ1.78 kΩ4700 pF 31.6 kHz
1.00V 1.00 kΩ1.00 kΩ4700 pF 33.8 kHz
1.20V 1.40 kΩ1.00 kΩ3300 pF 34.4 kHz
1.50V 2.00 kΩ1.00 kΩ2700 pF 29.5 kHz
1.80V 2.94 kΩ1.13 kΩ1500 pF 36.1kHz
2.00V 1.02 kΩ340Ω4700 pF 33.2 kHz
2.50V 1.02 kΩ255Ω4700 pF 33.2 kHz
3.00V 1.00 kΩ200Ω4700 pF 33.8 kHz
3.30V 2.00 kΩ357Ω2700 pF 29.5 kHz
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Please refer to Application Note AN-1378 Method For Calculating Output Voltage Tolerances in Adjustable
Regulators (SNVA112) for additional information on how resistor tolerances affect the calculated VOUT value.
ENABLE OPERATION
The Enable ON threshold is typically 1.2V, and the OFF threshold is typically 1.0V. To ensure reliable operation
the Enable pin voltage must rise above the maximum VEN(ON) threshold and must fall below the minimum VEN(OFF)
threshold. The Enable threshold has typically 200mV of hysteresis to improve noise immunity.
The Enable pin (EN) has no internal pull-up or pull-down to establish a default condition and, as a result, this pin
must be terminated either actively or passively.
If the Enable pin is driven from a single ended device (such as the collector of a discrete transistor) a pull-up
resistor to VIN, or a pull-down resistor to ground, will be required for proper operation. A 1 kΩto 100 kΩresistor
can be used as the pull-up or pull-down resistor to establish default condition for the EN pin. The resistor value
selected should be appropriate to swamp out any leakage in the external single ended device, as well as any
stray capacitance.
If the Enable pin is driven from a source that actively pulls high and low (such as a CMOS rail to rail comparator
output), the pull-up, or pull-down, resistor is not required.
If the application does not require the Enable function, the pin should be connected directly to the adjacent VIN
pin.
POWER DISSIPATION/HEAT-SINKING
A heat-sink may be required depending on the maximum power dissipation (PD(MAX)), maximum ambient
temperature (TA(MAX))of the application, and the thermal resistance (θJA) of the package. Under all possible
conditions, the junction temperature (TJ) must be within the range specified in the Operating Ratings. The total
power dissipation of the device is given by:
PD= ( (VIN−VOUT) x IOUT) + ((VIN) x IGND) (7)
where IGND is the operating ground current of the device (specified under Electrical Characteristics).
The maximum allowable junction temperature rise (ΔTJ) depends on the maximum expected ambient
temperature (TA(MAX)) of the application, and the maximum allowable junction temperature (TJ(MAX)):
ΔTJ= TJ(MAX) −TA(MAX) (8)
The maximum allowable value for junction to ambient Thermal Resistance, θJA, can be calculated using the
formula:
θJA =ΔTJ/ PD(MAX) (9)
LP38512-ADJ is available in PFM and SO PowerPad surface mount packages. For a comparison of the PFM
package to the standard TO-263 package see Application Note AN-1797 PFM Package (SNVA328). The θJA
thermal resistance depends on amount of copper area, or heat sink, attached to the DAP, and on air flow. See
Application Note AN-1520 A Guide to Board Layout for Best Thermal Resistance for Exposed Packages
(SNVA183) for guidelines.
Heat-Sinking the PFM Package
The DAP of the PFM package is soldered to the copper plane for heat sinking. The PFM package has a θJA
rating of 67°C/W, and a θJC rating of 2°C/W. The θJA rating of 67°C/W includes the device DAP soldered to an
area of 0.055 square inches (0.22 in x 0.25 in) of 1 ounce copper on a two sided PCB, with no airflow. See
JEDEC standard EIA/JESD51-3 for more information.
Figure 21 shows a curve for the θJA of PFM package for different thermal via counts under the exposed DAP,
using a four layer PCB for heat sinking. The thermal vias connect the copper area directly under the exposed
DAP to the first internal copper plane only. See JEDEC standards EIA/JESD51-5 and EIA/JESD51-7 for more
information.
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Figure 21. θJA vs Thermal Via Count for the PFM Package on 4–Layer PCB
Figure 22 shows the thermal performance when the Thin TO-263 is mounted to a two layer PCB where the
copper area is predominately directly under the exposed DAP.As shown in the figure, increasing the copper area
beyond 1 square inch produces very little improvement.
Figure 22. θJA vs Copper Area for the PFM Package
Heat-Sinking The SO PowerPad Package
The DAP of the SO PowerPad package is soldered to the copper plane for heat sinking. The LP38512MR
package has a θJA rating of 168°C/W, and a θJC rating of 11°C/W. The θJA rating of 168°C/W includes the device
DAP soldered to an area of 0.008 square inches (0.09 in x 0.09 in) of 1 ounce copper on a two sided PCB, with
no airflow. See JEDEC standard EIA/JESD51-3 for more information.
Figure 23 shows a curve for different thermal via counts under the exposed DAP, using a four layer PCB for heat
sinking. The thermal vias connect the copper area directly under the exposed DAP to the first internal copper
plane only. See JEDEC standards EIA/JESD51-5 and EIA/JESD51-7 for more information.
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Figure 23. θJA vs Thermal Via Count for the SO PowerPad Package on 2–Layer PCB with Copper Area on
Bottom-Side
Figure 24 shows thermal performance for a two layer board using thermal vias to a copper area on the bottom of
the PCB. The copper area on the top of the PCB, which is soldered to the exposed DAP, is 0.10in x 0.20in,
which is approximately the same dimensions as the body of the SO PowerPad package. The copper area on the
bottom of the PCB is a square area and is centered directly under the SO PowerPad package.
Figure 24. θJA vs Thermal Via Count for the SO PowerPad Package on 2–Layer PCB with Copper Area on
Bottom-Side
Figure 25 shows thermal performance for a two layer board with the DAP soldered to copper area on the of the
PCB only. Increasing the copper area soldered to the DAP to 1 square inch of 1 ounce copper, using a dog-bone
type layout, will produce a typical θJA rating of 98°C/W.
Figure 25. θJA vs Copper Area for the SO PowerPad Package on 2–Layer PCB with Copper Area on Top-
Side
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REVISION HISTORY
Changes from Revision C (April 2013) to Revision D Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 13
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LP38512MR-ADJ/NOPB ACTIVE SO PowerPAD DDA 8 95 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 L38512
-ADJ
LP38512MRX-ADJ/NOPB ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 L38512
-ADJ
LP38512TJ-ADJ/NOPB ACTIVE TO-263 NDQ 5 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LP38512
TJ-ADJ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
www.ti.com 13-Sep-2014
Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LP38512MRX-ADJ/NOPB SO
Power
PAD
DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LP38512TJ-ADJ/NOPB TO-263 NDQ 5 1000 330.0 24.4 10.6 15.4 2.45 12.0 24.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 29-May-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LP38512MRX-ADJ/NOPB SO PowerPAD DDA 8 2500 367.0 367.0 35.0
LP38512TJ-ADJ/NOPB TO-263 NDQ 5 1000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 29-May-2013
Pack Materials-Page 2
MECHANICAL DATA
NDQ0005A
www.ti.com
TJ5A (Rev F)
www.ti.com
PACKAGE OUTLINE
C
TYP
6.2
5.8
1.7 MAX
6X 1.27
8X 0.51
0.31
2X
3.81
TYP
0.25
0.10
0 - 8
0.15
0.00
2.34
2.24
2.34
2.24
0.25
GAGE PLANE
1.27
0.40
A
NOTE 3
5.0
4.8
B4.0
3.8
4218825/A 05/2016
PowerPAD SOIC - 1.7 mm max heightDDA0008A
PLASTIC SMALL OUTLINE
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012.
PowerPAD is a trademark of Texas Instruments.
TM
18
0.25 C A B
5
4
PIN 1 ID
AREA
NOTE 4
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.400
EXPOSED
THERMAL PAD
4
1
5
8
www.ti.com
EXAMPLE BOARD LAYOUT
(5.4)
(1.3) TYP
( ) TYP
VIA
0.2
(R ) TYP0.05
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
8X (1.55)
8X (0.6)
6X (1.27)
(2.95)
NOTE 9
(4.9)
NOTE 9
(2.34)
(2.34)
SOLDER MASK
OPENING
(1.3)
TYP
4218825/A 05/2016
PowerPAD SOIC - 1.7 mm max heightDDA0008A
PLASTIC SMALL OUTLINE
SYMM
SYMM
SEE DETAILS
LAND PATTERN EXAMPLE
SCALE:10X
1
45
8
SOLDER MASK
OPENING
METAL COVERED
BY SOLDER MASK
SOLDER MASK
DEFINED PAD
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
TM
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
(R ) TYP0.05
8X (1.55)
8X (0.6)
6X (1.27)
(5.4)
(2.34)
(2.34)
BASED ON
0.125 THICK
STENCIL
4218825/A 05/2016
PowerPAD SOIC - 1.7 mm max heightDDA0008A
PLASTIC SMALL OUTLINE
1.98 X 1.980.175
2.14 X 2.140.150
2.34 X 2.34 (SHOWN)0.125
2.62 X 2.620.1
SOLDER STENCIL
OPENING
STENCIL
THICKNESS
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
TM
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
SYMM
SYMM
1
45
8
BASED ON
0.125 THICK
STENCIL
BY SOLDER MASK
METAL COVERED SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
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