IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
09/12/2015
1
512K x36 and 1024K x18 18Mb,
SYNCHRONOUS FLOW-THROUGH SRAM OCTOBER 2015
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Burst sequence control using MODE input
• Three chip enable option for simple depth
expansion and address pipelining
• Common data inputs and data outputs
• Auto Power-down during deselect
• Single cycle deselect
• Snooze MODE for reduced-power standby
• JEDEC 100-pin QFP, 165-ball BGA and 119-ball
BGA packages
• Power supply:
LF: VDD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%)
VF: VDD 2.5V (± 5%), VDDQ 2.5V (± 5%)
VVF: VDD 1.8V (± 5%), VDDQ 1.8V (± 5%)
• JTAG Boundary Scan for BGA packages
• Commercial, Industrial and Automotive
temperature support
• Lead-free available
• For leaded options, please contact ISSI
FAST ACCESS TIME
DESCRIPTION
The 18Mb product family features high-speed, low-
power synchronous static RAMs designed to provide
burstable, high-performance memory for
communication and networking applications. The
IS61(64)LF/VF/VVF51236(32)B organized as 524,288
words by 36(32)bits. The IS61(64)LF/VF/VVF102418B
are organized as 1,048,576 words by 18 bits.
Fabricated with ISSI's advanced CMOS technology,
the device integrates a 2-bit burst counter, high-speed
SRAM core, and high-drive capability outputs into a
single monolithic circuit. All synchronous inputs pass
through registers controlled by a positive-edge-
triggered single clock input.
Write cycles are internally self-timed and are initiated
by the rising edge of the clock input. Write cycles can
be one to four bytes wide as controlled by the write
control inputs.
Separate byte enables allow individual bytes to be
written. The byte write operation is performed by using
the byte write enable (/BWE) input combined with one
or more individual byte write signals (/BWx). In
addition, Global Write (/GW) is available for writing all
bytes at one time, regardless of the byte write controls.
Bursts can be initiated with either /ADSP (Address
Status Processor) or /ADSC (Address Status Cache
Controller) input pins. Subsequent burst addresses can
be generated internally and controlled by the /ADV
(burst address advance) input pin.
The mode pin is used to select the burst sequence
order. Linear burst is achieved when this pin is tied
LOW. Interleave burst is achieved when this pin is tied
HIGH or left floating
Copyright © 2015 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Symbol
Parameter
-6.5
-7.5
Units
tKQ
Clock Access
Time
6.5
7.5
ns
tKC
Cycle time
7.5
8.5
ns
Frequency
133
117
MHz
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
09/12/2015
2
BLOCK DIAGRAM
E
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
09/12/2015
3
PIN CONFIGURATION
512K x 36, 165-Ball BGA (Top View)
2
3
4
5
6
7
8
9
10
11
A
NC
A
/CE
/BWc
/BWb
/CE2
/BWE
/ADSC
/ADV
A
NC
B
NC
A
CE2
/BWd
/BWa
CLK
/GW
/OE
/ADSP
A
NC
C
DQPc
NC
VDDQ
VSS
VSS
VSS
VSS
VSS
VDDQ
NC
DQPb
D
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
E
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
F
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
G
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
H
NC
VSS
NC
VDD
VSS
VSS
VSS
VDD
NC
NC
ZZ
J
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
K
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
L
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
M
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
N
DQPd
NC
VDDQ
VSS
NC
A
NC
VSS
VDDQ
NC
DQPa
P
NC
NC
A
A
TDI
A1*
TDO
A
A
A
A
R
MODE
NC
A
A
TMS
A0*
TCK
A
A
A
A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
Bottom View
165-Ball, 13 mm x 15mm BGA
PIN DESCRIPTIONS
Symbol
Pin Name
CLK
Synchronous Clock
A0,A1
Synchronous Burst Address Inputs
A
Address Inputs
/ADV
Synchronous Burst Address Advance
/ADSP
Address Status Processor
/ADSC
Address Status Controller
MODE
Burst Sequence Selection
/CE,CE2,/CE2
Synchronous Chip Enable
/BWE
Byte Write Enable
/BWx (x=a-d)
Synchronous Byte Write Inputs
/GW
Global Write Enable
/OE
Output Enable
DQx
Data Inputs/Outputs
DQPx
Parity Data I/O
TCK,TDI,
TDO,TMS
JTAG Pins
ZZ
Power Sleep Mode
NC
No Connect
VDD
Power Supply
VDDQ
I/O Power Supply
VSS
Ground
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
09/12/2015
4
512K x 32, 165-Ball BGA (Top View)
1
2
3
4
5
6
7
8
9
10
11
A
NC
A
/CE
/BWc
/BWb
/CE2
/BWE
/ADSC
/ADV
A
NC
B
NC
A
CE2
/BWd
/BWa
CLK
/GW
/OE
/ADSP
A
NC
C
NC
NC
VDDQ
VSS
VSS
VSS
VSS
VSS
VDDQ
NC
NC
D
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
E
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
F
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
G
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
H
NC
VSS
NC
VDD
VSS
VSS
VSS
VDD
NC
NC
ZZ
J
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
K
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
L
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
M
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
N
NC
NC
VDDQ
VSS
NC
A
NC
VSS
VDDQ
NC
NC
P
NC
NC
A
A
TDI
A1*
TDO
A
A
A
A
R
MODE
NC
A
A
TMS
A0*
TCK
A
A
A
A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
Bottom View
165-Ball, 13 mm x 15mm BGA
PIN DESCRIPTIONS
Symbol
Pin Name
CLK
Synchronous Clock
A0,A1
Synchronous Burst Address Inputs
A
Address Inputs
/ADV
Synchronous Burst Address Advance
/ADSP
Address Status Processor
/ADSC
Address Status Controller
MODE
Burst Sequence Selection
/CE,CE2,/CE2
Synchronous Chip Enable
/BWE
Byte Write Enable
/BWx (x=a-d)
Synchronous Byte Write Inputs
/GW
Global Write Enable
/OE
Output Enable
DQx
Data Inputs/Outputs
DQPx
Parity Data I/O
TCK,TDI,
TDO,TMS
JTAG Pins
ZZ
Power Sleep Mode
NC
No Connect
VDD
Power Supply
VDDQ
I/O Power Supply
VSS
Ground
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
09/12/2015
5
1024K x 18, 165-Ball BGA (Top View)
2
3
4
5
6
7
8
9
10
11
A
NC
A
/CE
/BWb
NC
/CE2
/BWE
/ADSC
/ADV
A
A
B
NC
A
CE2
NC
/BWa
CLK
/GW
/OE
/ADSP
A
NC
C
NC
NC
VDDQ
VSS
VSS
VSS
VSS
VSS
VDDQ
NC
DQPa
D
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
E
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
F
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
G
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
H
NC
VSS
NC
VDD
VSS
VSS
VSS
VDD
NC
NC
ZZ
J
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
K
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
L
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
M
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
N
DQPb
NC
VDDQ
VSS
NC
A
NC
VSS
VDDQ
NC
NC
P
NC
NC
A
A
TDI
A1*
TDO
A
A
A
A
R
MODE
NC
A
A
TMS
A0*
TCK
A
A
A
A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
Bottom View
165-Ball, 13 mm x 15mm BGA
PIN DESCRIPTIONS
Symbol
Pin Name
CLK
Synchronous Clock
A0,A1
Synchronous Burst Address Inputs
A
Address Inputs
/ADV
Synchronous Burst Address
Advance
/ADSP
Address Status Processor
/ADSC
Address Status Controller
MODE
Burst Sequence Selection
/CE,CE2,/CE2
Synchronous Chip Enable
/BWE
Byte Write Enable
/BWx (x=a-b)
Synchronous Byte Write Inputs
/GW
Global Write Enable
/OE
Output Enable
DQx
Data Inputs/Outputs
DQPx
Parity Data I/O
TCK,TDI,
TDO,TMS
JTAG Pins
ZZ
Power Sleep Mode
NC
No Connect
VDD
Power Supply
VDDQ
I/O Power Supply
VSS
Ground
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
09/12/2015
6
512K x 36, 119-Ball BGA (Top View)
1
2
3
4
5
6
7
A
VDDQ
A
A
/ADSP
A
A
VDDQ
B
NC
A
A
/ADSC
A
A
NC
C
NC
A
A
VDD
A
A
NC
D
DQc
DQPc
VSS
NC
VSS
DQPb
DQb
E
DQc
DQc
VSS
/CE
VSS
DQb
DQb
F
VDDQ
DQc
VSS
/OE
VSS
DQb
VDDQ
G
DQc
DQc
/BWc
/ADV
/BWb
DQb
DQb
H
DQc
DQc
VSS
/GW
VSS
DQb
DQb
J
VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
K
DQd
DQd
VSS
CLK
VSS
DQa
DQa
L
DQd
DQd
/BWd
NC
/BWa
DQa
DQa
M
VDDQ
DQd
VSS
/BWE
VSS
DQa
VDDQ
N
DQd
DQd
VSS
A1*
VSS
DQa
DQa
P
DQd
DQPd
VSS
A0*
VSS
DQPa
DQa
R
NC
A
MODE
VDD
NC
A
NC
T
NC
NC
A
A
A
NC
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
Bottom View
119-Ball, 14 mm x 22 mm BGA
PIN DESCRIPTIONS
Symbol
Pin Name
CLK
Synchronous Clock
A0,A1
Synchronous Burst Address Inputs
A
Address Inputs
/ADV
Synchronous Burst Address
Advance
/ADSP
Address Status Processor
/ADSC
Address Status Controller
MODE
Burst Sequence Selection
/CE
Synchronous Chip Enable
/BWE
Byte Write Enable
/BWx (x=a-d)
Synchronous Byte Write Inputs
/GW
Global Write Enable
/OE
Output Enable
DQx
Data Inputs/Outputs
DQPx
Parity Data I/O
TCK,TDI,
TDO,TMS
JTAG Pins
ZZ
Power Sleep Mode
NC
No Connect
VDD
Power Supply
VDDQ
I/O Power Supply
VSS
Ground
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
09/12/2015
7
512K x 32, 119-Ball BGA (Top View)
1
2
3
4
5
6
7
A
VDDQ
A
A
/ADSP
A
A
VDDQ
B
NC
A
A
/ADSC
A
A
NC
C
NC
A
A
VDD
A
A
NC
D
DQc
NC
VSS
NC
VSS
NC
DQb
E
DQc
DQc
VSS
/CE
VSS
DQb
DQb
F
VDDQ
DQc
VSS
/OE
VSS
DQb
VDDQ
G
DQc
DQc
/BWc
/ADV
/BWb
DQb
DQb
H
DQc
DQc
VSS
/GW
VSS
DQb
DQb
J
VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
K
DQd
DQd
VSS
CLK
VSS
DQa
DQa
L
DQd
DQd
/BWd
NC
/BWa
DQa
DQa
M
VDDQ
DQd
VSS
/BWE
VSS
DQa
VDDQ
N
DQd
DQd
VSS
A1*
VSS
DQa
DQa
P
DQd
NC
VSS
A0*
VSS
NC
DQa
R
NC
A
MODE
VDD
NC
A
NC
T
NC
NC
A
A
A
NC
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
Bottom View
119-Ball, 14 mm x 22 mm BGA
PIN DESCRIPTIONS
Symbol
Pin Name
CLK
Synchronous Clock
A0,A1
Synchronous Burst Address Inputs
A
Address Inputs
/ADV
Synchronous Burst Address
Advance
/ADSP
Address Status Processor
/ADSC
Address Status Controller
MODE
Burst Sequence Selection
/CE
Synchronous Chip Enable
/BWE
Byte Write Enable
/BWx (x=a-d)
Synchronous Byte Write Inputs
/GW
Global Write Enable
/OE
Output Enable
DQx
Data Inputs/Outputs
TCK,TDI,
TDO,TMS
JTAG Pins
ZZ
Power Sleep Mode
NC
No Connect
VDD
Power Supply
VDDQ
I/O Power Supply
VSS
Ground
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
09/12/2015
8
1024K x 18, 119-Ball BGA (Top View)
1
2
3
4
5
6
7
A
VDDQ
A
A
/ADSP
A
A
VDDQ
B
NC
A
A
/ADSC
A
A
NC
C
NC
A
A
VDD
A
A
NC
D
DQb
NC
VSS
NC
VSS
DQPa
NC
E
NC
DQb
VSS
/CE
VSS
NC
DQa
F
VDDQ
NC
VSS
/OE
VSS
DQa
VDDQ
G
NC
DQb
/BWb
/ADV
VSS
NC
DQa
H
DQb
NC
VSS
/GW
VSS
DQa
NC
J
VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
K
NC
DQb
VSS
CLK
VSS
NC
DQa
L
DQb
NC
VSS
NC
/BWa
DQa
NC
M
VDDQ
DQb
VSS
/BWE
VSS
NC
VDDQ
N
DQb
NC
VSS
A1*
VSS
DQa
NC
P
NC
DQPb
VSS
A0*
VSS
NC
DQa
R
NC
A
MODE
VDD
NC
A
NC
T
NC
A
A
NC
A
A
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
Bottom View
119-Ball, 14 mm x 22 mm BGA
PIN DESCRIPTIONS
Symbol
Pin Name
CLK
Synchronous Clock
A0,A1
Synchronous Burst Address Inputs
A
Address Inputs
/ADV
Synchronous Burst Address
Advance
/ADSP
Address Status Processor
/ADSC
Address Status Controller
MODE
Burst Sequence Selection
/CE
Synchronous Chip Enable
/BWE
Byte Write Enable
/BWx (x=a-b)
Synchronous Byte Write Inputs
/GW
Global Write Enable
/OE
Output Enable
DQx
Data Inputs/Outputs
DQPx
Parity Data I/O
TCK,TDI,
TDO,TMS
JTAG Pins
ZZ
Power Sleep Mode
NC
No Connect
VDD
Power Supply
VDDQ
I/O Power Supply
VSS
Ground
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
09/12/2015
9
512K x 36, 100PIN QFP (Top View)
A
A
/CE
CE2
/BWd
/BWc
/BWb
/BWa
/CE2
VDD
VSS
CLK
/GW
/BWE
/OE
/ADSC
/ADSP
/ADV
A
A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
DQPc 1 80 DQPb
DQc 2 79 DQb
DQc 3 78 DQb
VDDQ 4 77 VDDQ
VSS 5 76 VSS
DQc 6 75 DQb
DQc 7 74 DQb
DQc 8 73 DQb
DQc 9 72 DQb
VSS 10 71 VSS
VDDQ 11 70 VDDQ
DQc 12 69 DQb
DQc 13 68 DQb
NC 14 67 VSS
VDD 15 66 NC
NC 16 65 VDD
VSS 17 64 ZZ
DQd 18 63 DQa
DQd 19 62 DQa
VDDQ 20 61 VDDQ
VSS 21 60 VSS
DQd 22 59 DQa
DQd 23 58 DQa
DQd 24 57 DQa
DQd 25 56 DQa
VSS 26 55 VSS
VDDQ 27 54 VDDQ
DQd 28 53 DQa
DQd 29 52 DQa
DQPd 30 51 DQPa
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VDD
A
A
A
A
A
A
A
A
A
512K x 36
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
Pin Name
Symbol
Pin Name
CLK
Synchronous Clock
/GW
Global Write Enable
A0,A1
Synchronous Burst Address Inputs
/OE
Output Enable
A
Address Inputs
DQx
Data Inputs/Outputs
/ADV
Synchronous Burst Address Advance
DQPx
Parity Data I/O
/ADSP
Address Status Processor
ZZ
Power Sleep Mode
/ADSC
Address Status Controller
NC
No Connect
MODE
Burst Sequence Selection
VDD
Power Supply
/CE,CE2,/CE2
Synchronous Chip Enable
VDDQ
I/O Power Supply
/BWE
Byte Write Enable
VSS
Ground
/BWx (x=a-d)
Synchronous Byte Write Inputs
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
09/12/2015
10
512K x 32, 100PIN QFP (Top View)
A
A
/CE
CE2
/BWd
/BWc
/BWb
/BWa
/CE2
VDD
VSS
CLK
/GW
/BWE
/OE
/ADSC
/ADSP
/ADV
A
A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
NC 180 NC
DQc 2 79 DQb
DQc 3 78 DQb
VDDQ 4 77 VDDQ
VSS 5 76 VSS
DQc 6 75 DQb
DQc 7 74 DQb
DQc 8 73 DQb
DQc 9 72 DQb
VSS 10 71 VSS
VDDQ 11 70 VDDQ
DQc 12 69 DQb
DQc 13 68 DQb
NC 14 67 VSS
VDD 15 66 NC
NC 16 65 VDD
VSS 17 64 ZZ
DQd 18 63 DQa
DQd 19 62 DQa
VDDQ 20 61 VDDQ
VSS 21 60 VSS
DQd 22 59 DQa
DQd 23 58 DQa
DQd 24 57 DQa
DQd 25 56 DQa
VSS 26 55 VSS
VDDQ 27 54 VDDQ
DQd 28 53 DQa
DQd 29 52 DQa
NC 30 51 NC
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VDD
A
A
A
A
A
A
A
A
A
512K x 32
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
Pin Name
Symbol
Pin Name
CLK
Synchronous Clock
/GW
Global Write Enable
A0,A1
Synchronous Burst Address Inputs
/OE
Output Enable
A
Address Inputs
DQx
Data Inputs/Outputs
/ADV
Synchronous Burst Address Advance
ZZ
Power Sleep Mode
/ADSP
Address Status Processor
NC
No Connect
/ADSC
Address Status Controller
VDD
Power Supply
MODE
Burst Sequence Selection
VDDQ
I/O Power Supply
/CE,CE2,/CE2
Synchronous Chip Enable
VSS
Ground
/BWE
Byte Write Enable
/BWx (x=a-d)
Synchronous Byte Write Inputs
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
09/12/2015
11
1024K x 18, 100PIN
QFP (Top View)
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
Pin Name
Symbol
Pin Name
CLK
Synchronous Clock
/GW
Global Write Enable
A0,A1
Synchronous Burst Address Inputs
/OE
Output Enable
A
Address Inputs
DQx
Data Inputs/Outputs
/ADV
Synchronous Burst Address Advance
DQPx
Parity Data I/O
/ADSP
Address Status Processor
ZZ
Power Sleep Mode
/ADSC
Address Status Controller
NC
No Connect
MODE
Burst Sequence Selection
VDD
Power Supply
/CE,CE2,/CE2
Synchronous Chip Enable
VDDQ
I/O Power Supply
/BWE
Byte Write Enable
VSS
Ground
/BWx (x=a-b)
Synchronous Byte Write Inputs
A
A
/CE
CE2
NC
NC
/BWb
/BWa
/CE2
VDD
VSS
CLK
/GW
/BWE
/OE
/ADSC
/ADSP
/ADV
A
A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
NC 180 A
NC 279 NC
NC 378 NC
VDDQ 4 77 VDDQ
VSS 5 76 VSS
NC 675 NC
NC 774 DQPa
DQb 8 73 DQa
DQb 9 72 DQa
VSS 10 71 VSS
VDDQ 11 70 VDDQ
DQb 12 69 DQa
DQb 13 68 DQa
NC 14 67 VSS
VDD 15 66 NC
NC 16 65 VDD
VSS 17 64 ZZ
DQb 18 63 DQa
DQb 19 62 DQa
VDDQ 20 61 VDDQ
VSS 21 60 VSS
DQb 22 59 DQa
DQb 23 58 DQa
DQPb 24 57 NC
NC 25 56 NC
VSS 26 55 VSS
VDDQ 27 54 VDDQ
NC 28 53 NC
NC 29 52 NC
NC 30 51 NC
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VDD
A
A
A
A
A
A
A
A
A
1024K x 18
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
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Rev. C
09/12/2015
12
TRUTH TABLE
SYNCHRONOUS TRUTH TABLE
OPERATION
ADDRESS
/CE
/CE2
CE2
ZZ
/ADSP
/ADSC
/ADV
/WRITE
/OE
CLK
DQ
Deselect Cycle, Power-Down
None
H
X
X
L
X
L
X
X
X
L-H
High-Z
Deselect Cycle, Power-Down
None
L
X
L
L
L
X
X
X
X
L-H
High-Z
Deselect Cycle, Power-Down
None
L
H
X
L
L
X
X
X
X
L-H
High-Z
Deselect Cycle, Power-Down
None
L
X
L
L
H
L
X
X
X
L-H
High-Z
Deselect Cycle, Power-Down
None
L
H
X
L
H
L
X
X
X
L-H
High-Z
Snooze Mode, Power-Down
None
X
X
X
H
X
X
X
X
X
X
High-Z
Read Cycle, Begin Burst
External
L
L
H
L
L
X
X
X
L
L-H
Q
Read Cycle, Begin Burst
External
L
L
H
L
L
X
X
X
H
L-H
High-Z
Write Cycle, Begin Burst
External
L
L
H
L
H
L
X
L
X
L-H
D
Read Cycle, Begin Burst
External
L
L
H
L
H
L
X
H
L
L-H
Q
Read Cycle, Begin Burst
External
L
L
H
L
H
L
X
H
H
L-H
High-Z
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
L
L-H
Q
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
H
L-H
High-Z
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
L
L-H
Q
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L-H
High-Z
Write Cycle, Continue Burst
Next
X
X
X
L
H
H
L
L
X
L-H
D
Write Cycle, Continue Burst
Next
H
X
X
L
X
H
L
L
X
L-H
D
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L-H
Q
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L-H
High-Z
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L-H
Q
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L-H
High-Z
Write Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
L
X
L-H
D
Write Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
L
X
L-H
D
NOTE:
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
2. For WRITE, L means one or more byte write enable signals (/BWa-d) and /BWE are LOW or /GW is LOW. /WRITE = H for all /BWx, /BWE, /GW HIGH.
3. /BWa enables WRITEs to DQa’s and DQPa. /BWb enables WRITEs to DQb’s and DQPb. /BWc enables WRITEs to DQc’s and DQPc. /BWd enables
WRITEs to DQd’s and DQPd. DQPa and DQPb are available on the x18 version. DQPa-DQPd are available on the x36 version.
4. All inputs except /OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, /OE must be HIGH before the input data setup time and held HIGH during the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. /ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and
/BWE LOW or /GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
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13
PARTIAL TRUTH TABLE
Operation
/GW
/BWE
/BWa
/BWb
/BWc
/BWd
READ
H
H
X
X
X
X
READ
H
L
H
H
H
H
WRITE BYTE a
H
L
L
H
H
H
WRITE BYTE b
H
L
H
L
H
H
WRITE BYTE c
H
L
H
H
L
H
WRITE BYTE d
H
L
H
H
H
L
WRITE ALL BYTEs
H
L
L
L
L
L
WRITE ALL BYTEs
L
X
X
X
X
X
Notes:
1. X means "Don't Care".
2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
ADDRESS SEQUENCE IN BURST MODE
INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or NC)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A1 A0
A1 A0
A1 A0
A1 A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
LINEAR BURST ADDRESS TABLE (MODE = Vss )
Power Up Sequence
VDDQ → VDD1 → I/O Pins2
Notes:
1. VDD can be applied at the same time as VDDQ
2. Applying I/O inputs is recommended after VDDQ is stable. The inputs of the I/O pins can be applied at the same time as VDDQ as long as Vih (level of I/O
pins) is lower than VDDQ.
A1', A0' = 1,1
0,0
1,0
0,1
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
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ABSOLUTE MAXIMUM RATINGS AND OPERATING RANGE
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
LPS Value
VPS/VVPS Value
Unit
TSTG
Storage Temperature
–65 to +150
–65 to +150
°C
PD
Power Dissipation
1.6
1.6
W
IOUT
Output Current (per I/O)
100
20
mA
VIN, VOUT
Voltage Relative to Vss for I/O Pins
–0.5 to VDDQ +0.5
–0.5 to VDDQ + 0.3
V
VIN
Voltage Relative to Vss for Address and
Control Inputs
–0.5 to VDD +0.5
–0.5 to VDD + 0.3
V
VDD
Voltage on VDD Supply Relative to Vss
–0.5 to VDD +0.5
–0.5 to VDD +0.3
V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to
avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
OPERATING RANGE (IS61LFx)
Range
Ambient Temperature
VDD
VDDQ
Commercial
0°C to +70°C
3.3V ± 5%
3.3V / 2.5V ± 5%
Industrial
-40°C to +85°C
3.3V ± 5%
3.3V / 2.5V ± 5%
Automotive
-40°C to +125°C
3.3V ± 5%
3.3V / 2.5V ± 5%
OPERATING RANGE (IS61VFx)
Range
Ambient Temperature
VDD
VDDQ
Commercial
0°C to +70°C
2.5V ± 5%
2.5V ± 5%
Industrial
-40°C to +85°C
2.5V ± 5%
2.5V ± 5%
Automotive
*Please contact ISSI
OPERATING RANGE (IS61VVFx)
Range
Ambient Temperature
VDD
VDDQ
Commercial
0°C to +70°C
1.8V ± 5%
1.8V ± 5%
Industrial
-40°C to +85°C
1.8V ± 5%
1.8V ± 5%
Automotive
*Please contact ISSI
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
09/12/2015
15
CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS (Over operating temperature range)
Symbol
Parameter
Test Conditions
3.3V
2.5V
1.8V
Unit
Min.
Max.
Min
.
Max.
Min.
Max.
VOH
Output HIGH
Voltage
IOH=-4.0 mA(3.3V)
2.4
—
2.0
—
VDDQ
-0.4
—
V
IOH=–1.0 mA(2.5V,1.8V)
VOL
Output LOW
Voltage
IOL=8.0 mA(3.3V)
—
0.4
—
0.4
—
0.4
V
IOL=1.0 mA(2.5V,1.8V)
VIH
Input HIGH
Voltage
2.0
VDD
+0.3
1.7
VDD
+0.3
0.7* VDD
VDD
+0.3
V
VIL
Input LOW
Voltage
–0.3
0.8
–
0.3
0.7
–0.3
0.3*
VDD
V
ILI
Input Leakage
Current
Vss≤VIN≤ VDD
–1
1
–1
1
–1
1
μA
ILO
Output Leakage
Current
Vss≤VOUT≤ VDD,/OE=VIH
–1
1
–1
1
–1
1
μA
Notes:
1. All voltages referenced to ground.
2. Overshoot:
3.3V and 2.5V: VIH (AC) ≤ VDD + 1.5V (Pulse width less than tKC /2)
1.8V: VIH (AC) ≤ VDD + 0.5V (Pulse width less than tKC /2)
3. Undershoot:
3.3V and 2.5V: VIL (AC) ≥ -1.5V (Pulse width less than tKC /2)
1.8V: VIL (AC) ≥ -0.5V (Pulse width less than tKC /2)
4. MODE pin has an internal pull-up and should be tied to VDD or Vss . It exhibits ±100μA maximum leakage current when tied to ≤Vss+0.2V or ≥ VDDQ–
0.2V.
5. ZZ pin has an internal pull-down and should be tied to VDD or Vss . It exhibits ±100μA maximum leakage current when tied to ≤Vss+0.2V or ≥ VDD–0.2V.
POWER SUPPLY CHARACTERISTICS (Over Operating Range)
Symbol
Parameter
Test Conditions
-6.5
-7.5
Unit
Max
Max
x18
x36
x18
x36
ICC
AC Operating,
Supply Current
Device Selected, /OE = VIH, ZZ ≤ VIL, All Inputs
≤ 0.2V or ≥ VDD – 0.2V,Cycle Time ≥ tKC min.
240
240
190
190
mA
260
260
210
210
-
-
230
230
ISB
Standby
Current TTL
Input
Device Deselected, VDD = Max.All Inputs ≤ VIL
or ≥ VIH, ZZ ≤ VIL, f = Max.
80
80
70
70
mA
90
90
80
80
-
-
90
90
ISB1
Standby
Current CMOS
Input
Device Deselected, VDD = Max.,VIN ≤ Vss +
0.2V or ≥ VDD – 0.2V,f = 0
60
60
60
60
mA
70
70
70
70
-
-
80
80
Note:
1. Power-up assumes a linear ramp from 0V to VDD (min) within 200ms. During this time Vih < VDD and VDDQ < VDD
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
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CAPACITANCE
Symbol
Parameter
Conditions
Max.
Unit
CIN
Input Capacitance
VIN = 0V
6
pF
COUT
Input/Output Capacitance
VOUT = 0V
8
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: Ta = 25°C, f = 1 MHz, VDD = 3.3V.
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
Symbol
Parameter
-6.5
-7.5
Unit
Min.
Max.
Min.
Max.
fMAX
Clock Frequency
—
133
—
117
MHz
tKC
Cycle Time
7.5
—
8.5
—
ns
tKH
Clock High Time
2.2
—
2.5
—
ns
tKL
Clock Low Time
2.2
—
2.5
—
ns
tKQ
Clock Access Time
—
6.5
—
7.5
ns
tKQX(2)
Clock High to Output Invalid
2.5
—
2.5
—
ns
tKQLZ(2,3)
Clock High to Output Low-Z
2.5
—
2.5
—
ns
tKQHZ(2,3)
Clock High to Output High-Z
—
3.8
—
4.0
ns
tOEQ
Output Enable to Output Valid
—
3.2
—
3.4
ns
tOELZ(2,3)
Output Enable to Output Low-Z
0
—
0
—
ns
tOEHZ(2,3)
Output Disable to Output High-Z
—
3.5
—
3.5
ns
tAS
Address Setup Time
1.5
—
1.5
—
ns
tSS
Address Status Setup Time
1.5
—
1.5
—
ns
tws
Read/Write Setup Time
1.5
—
1.5
—
ns
tCES
Chip Enable Setup Time
1.5
—
1.5
—
ns
tADVS
Address Advance Setup Time
1.5
—
1.5
—
ns
tDS
Data Setup Time
1.5
—
1.5
—
ns
tAH
Address Hold Time
0.5
—
0.5
—
ns
tSH
Address Status Hold Time
0.5
—
0.5
—
ns
tWH
Write Hold Time
0.5
—
0.5
—
ns
tCEH
Chip Enable Hold Time
0.5
—
0.5
—
ns
tADVH
Address Advance Hold Time
0.5
—
0.5
—
ns
tDH
Data Hold Time
0.5
—
0.5
—
ns
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
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3.3V I/O AC TEST CONDITIONS
Parameter
Unit
Input Pulse Level
0V to 3.0V
Input Rise and Fall Times
1.5 ns
Input and Output Timing and Reference Level
1.5V
VTT
1.5V
VLOAD
3.3V
R1, R2
317Ω, 351Ω
Output Load
See Figures 1 and 2
2.5V I/O AC TEST CONDITIONS
Parameter
Unit
Input Pulse Level
0V to 2.5V
Input Rise and Fall Times
1.5 ns
Input and Output Timing and Reference Level
1.25V
VTT
1.25V
VLOAD
2.5V
R1, R2
1667Ω, 1538Ω
Output Load
See Figures 1 and 2
1.8V I/O AC TEST CONDITIONS
Parameter
Unit
Input Pulse Level
0V to 1.8V
Input Rise and Fall Times
1.5 ns
Input and Output Timing and Reference Level
0.9V
VTT
0.9V
VLOAD
1.8V
R1, R2
1KΩ, 1KΩ
Output Load
See Figures 1 and 2
I/O OUTPUT LOAD EQUIVALENT
50
Ω
OUTPUT
Z
O
=50
Ω
VTT
VLOAD
OUTPUT
5 pF
Including
jig and
scope
R2
R1
Figure1
Figure2
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
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18
READ/WRITE CYCLE TIMING
tKC
CLK
/ADSP
/ADSC
/ADV
Address
RD3
/GW
/BWE
/BWd-/BWa
/CE Masks /ADSP
/CE
tCES
tCEH
CE2
Unselected with /CE2
/CE2
tOELZ
tOEHZ
tOEQ
/OE
tKQX
2d
1a
tKQLZ
tKQHZ
tKQX
tKQ
1a
High-Z
DATAIN
tDS
tDH
Single Write
Burst Read
Unselected
DATAOUT
/ADSP is blocked by /CE inactive
Single Read
Flow-through
CE2 and /CE2 only sampled with /ADSP or /ADSC
tSS
tSH
tKH
tKL
tSS
tSH
tAS
tAH
RD2
WR1
RD1
tWS
tWH
tWS
tWH
WR1
tWS
tWH
tCES
tCEH
tCEH
tCES
High-Z
High-Z
tKQLZ
tKQ
2c
2b
2a
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
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WRITE CYCLE TIMING
High-Z
DATAOUT
Address
DATAIN
/ADSC
/ADSP
/ADV
CLK
/BWE
/CE2
CE2
/BWx
/OE
/GW
/CE
High-Z
tSS
tAS
Single Write
tDS tDH
/ADV must be inactive for /ADSP Write
tWS
tKH
tKC
tKL
CE2 and /CE2 only sampled with /ADSP or/ ADSC
/CE Masks /ADSP
Burst Write
tAVS
/ADSP is blocked by /CE inactive
/ADSC initiates Write
Write
WR3
WR3
Unselected
Unselected with CE2
tSH
tAVH
WR2
WR1
tAH
tWH
tWH
tWS
WR2
WR1
tWS
tWH
tWH
tWS
tCES
tCEH
tCEH
tCES
tCEH
tCES
/BW1-/BW4 only are applied to first cycle of WR2
1a
2a
2b
2c
2d
3a
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20
SNOOZE MODE ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Conditions
Temperature Range
Min.
Max.
Unit
ISB2
Current during SNOOZE MODE
ZZ ≥ VIH
Com.
—
40
mA
Ind.
—
50
mA
Auto.
—
60
mA
tPDS
ZZ active to input ignored
—
—
2
cycle
tPUS
ZZ inactive to input sampled
—
2
—
cycle
tZZI
ZZ active to SNOOZE current
—
—
2
cycle
tRZZI
ZZ inactive to exit SNOOZE current
—
0
—
ns
SLEEP MODE TIMING
CLK
ZZ
Isupply
All Inputs
(except ZZ)
tPDS
tZZI
ISB2
tRZZI
Deselect or Read Only
Deselect or Read Only
ZZ setup cycle
Normal
operation
cycle
Outputs (Q)
Don't Care
High-Z
ZZ recovery cycle
tPUS
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IEEE 1149.1 TAP and Boundary Scan
The SRAM provides a limited set of JTAG functions to test the interconnection between SRAM I/Os and printed
circuit board traces or other components. There is no multiplexer in the path from I/O pins to the RAM core.
In conformance with IEEE Standard 1149.1, the SRAM contains a TAP controller, instruction register, boundary
scan register, bypass register, and ID register.
The TAP controller has a standard 16-state machine that resets internally on power-up. Therefore, a TRST signal
is not required
Disabling the JTAG feature
The SRAM can operate without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be left disconnected. They
may alternately be connected to VDD through a pull-up resistor. TDO should be left disconnected. On power-up, the
device will come up in a reset state, which will not interfere with device operation.
Test Access Port Signal List:
1. Test Clock (TCK)
This signal uses VDD as a power supply. The test clock is used only with the TAP controller. All inputs are captured
on the rising edge of TCK. All outputs are driven from the falling edge of TCK.
2. Test Mode Select (TMS)
This signal uses VDD as a power supply. The TMS input is used to send commands to the TAP controller and is
sampled on the rising edge of TCK.
3. Test Data-In (TDI)
This signal uses VDD as a power supply. The TDI input is used to serially input test instructions and information into
the registers and can be connected to the input of any of the registers. The register between TDI and TDO is
chosen by the instruction that is loaded into the TAP instruction register. TDI is connected to the most significant
bit (MSB) of any register. For more information regarding instruction register loading, please see the TAP
Controller State Diagram.
4. Test Data-Out (TDO)
This signal uses VDDQ as a power supply. The TDO output ball is used to serially clock test instructions and data
out from the registers. The TDO output driver is only active during the Shift-IR and Shift-DR TAP controller states.
In all other states, the TDO pin is in a High-Z state. The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register. For more information, please see the TAP Controller
State Diagram.
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TAP Controller State and Block Diagram
Bypass Register (1 bit)
Identification Register (32 bits)
Instruction Register (3 bits)
TAP Controller
TDO
TMS
TCK
TDI
Control Signals
Boundary Scan Register (75 bits)
...
TAP Controller State Machine
Test Logic
Reset
Select DR
Run Test
Idle
0
1 1
Capture
DR
0
1
0
0
1
0
1
1
0
Shift DR
Exit1 DR
Pause DR
Exit2 DR
1
1
Update
DR
0
Select IR 1
Capture
IR
0
1
0
0
1
0
1
Shift IR
Exit1 IR
Pause IR
Exit2 IR
1
1
Update IR
0
0 0
1 0 1 0
90
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Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. RESET may be performed while the
SRAM is operating and does not affect its operation. At power-up, the TAP is internally reset to ensure that TDO
comes up in a high-Z state.
TAP Registers
Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM
test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded
into the TDI pin on the rising edge of TCK and output on the TDO pin on the falling edge of TCK.
1. Instruction Register
This register is loaded during the update-IR state of the TAP controller. At power-up, the instruction register is
loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a
reset state as described in the previous section. When the TAP controller is in the capture-IR state, the two LSBs
are loaded with a binary “01” pattern to allow for fault isolation of the board-level serial test data path.
2. Bypass Register
The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to
be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS
instruction is executed.
3. Boundary Scan Register
The boundary scan register is connected to all the input and bidirectional balls on the SRAM. Several balls are
also included in the scan register to reserved balls. The boundary scan register is loaded with the contents of the
SRAM Input and Output ring when the TAP controller is in the capture-DR state and is then placed between the
TDI and TDO balls when the controller is moved to the shift-DR state. Each bit corresponds to one of the balls on
the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO.
4. Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code during the capture-DR state when the IDCODE
command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out
when the TAP controller is in the shift-DR state.
Scan Register Sizes
Register Name
Bit Size
Instruction
3
Bypass
1
ID
32
Boundary Scan
90
TAP Instruction Set
Many instructions are possible with an eight-bit instruction register and all valid combinations are listed in the TAP
Instruction Code Table. All other instruction codes that are not listed on this table are reserved and should not be
used. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is
placed between TDI and TDO. During this state, instructions are shifted from the instruction register through the
TDI and TDO pins. To execute an instruction once it is shifted in, the TAP controller must be moved into the
Update-IR state.
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1. EXTEST
The EXTEST instruction allows circuitry external to the component package to be tested. Boundary-scan register
cells at output balls are used to apply a test vector, while those at input balls capture test results. Typically, the first
test vector to be applied using the EXTEST instruction will be shifted into the boundary scan register using the
PRELOAD instruction. Thus, during the update-IR state of EXTEST, the output driver is turned on, and the
PRELOAD data is driven onto the output balls.
2. IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also
places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the
device when the TAP controller enters the shift-DR state. The IDCODE instruction is loaded into the instruction
register upon power-up or whenever the TAP controller is given a test logic reset state.
3. SAMPLE Z
If the SAMPLE-Z instruction is loaded in the instruction register, all SRAM outputs are forced to an inactive drive
state (high-Z), moving the TAP controller into the capture-DR state loads the data in the SRAMs input into the
boundary scan register, and the boundary scan register is connected between TDI and TDO when the TAP
controller is moved to the shift-DR state.
4. SAMPLE/PRELOAD
When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the
capture-DR state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register.
The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the
SRAM clock operates significantly faster. Because there is a large difference between the clock frequencies, it is
possible that during the capture-DR state, an input or output will undergo a transition. The TAP may then try to
capture a signal while in transition. This will not harm the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible. To ensure that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture
setup plus hold time. The SRAM clock input might not be captured correctly if there is no way in a design to stop
(or slow) the clock during a SAMPLE/ PRELOAD instruction. If this is an issue, it is still possible to capture all other
signals and simply ignore the value of the CLK captured in the boundary scan register. Once the data is captured,
it is possible to shift out the data by putting the TAP into the shift-DR state. This places the boundary scan register
between the TDI and TDO balls.
6. BYPASS
When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a shift-DR state, the
bypass register is placed between TDI and TDO. The advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected together on a board.
7. PRIVATE
Do not use these instructions. They are reserved for future use and engineering mode.
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JTAG DC Operating Characteristics
(Over the Operating Temperature Range, 2.5V and 3.3V Option)
Parameter
Symbol
Min
Max
Units
Notes
JTAG Input High Voltage
VIH1
2.0
VDD+0.3
V
JTAG Input Low Voltage
VIL1
–0.3
0.7
V
JTAG Output High Voltage
VOH1
1.7
-
V
|IOH1|=2mA
JTAG Output Low Voltage
VOL1
-
0.7
V
IOL1=2mA
JTAG Output High Voltage
VOH2
2.1
-
V
|IOH2|=100µA
JTAG Output Low Voltage
VOL2
-
0.2
V
IOL2=100µA
JTAG Input Leakage Current
ILIJTAG
-10
+10
µA
0 ≤ Vin ≤ VDD
JTAG Output Leakage Current
ILOJTAG
-10
+10
µA
0 ≤ Vout ≤ VDD
Notes:
1. All voltages referenced to VSS (GND); All JTAG inputs and outputs are LVTTL-compatible.
JTAG DC Operating Characteristics
(Over the Operating Temperature Range, 1.8V Option)
Parameter
Symbol
Min
Max
Units
Notes
JTAG Input High Voltage
VIH1
TBD
TBD
V
JTAG Input Low Voltage
VIL1
TBD
TBD
V
JTAG Output High Voltage
VOH1
TBD
TBD
V
JTAG Output Low Voltage
VOL1
TBD
TBD
V
JTAG Input Leakage Current
ILIJTAG
TBD
TBD
µA
JTAG Output Leakage Current
ILOJTAG
TBD
TBD
µA
Notes:
1. All voltages referenced to VSS (GND); All JTAG inputs and outputs are LVTTL-compatible.
JTAG AC Test Conditions
(Over the Operating Temperature Range)
Parameter
Symbol
1.8V Option
2.5V Option
3.3V Option
Units
Input Pulse High Level
VIH1
TBD
2.5
3.0
V
Input Pulse Low Level
VIL1
TBD
0
0
V
Input rise and fall time
TR1
TBD
1.5
1.5
ns
Test load termination supply voltage
VREF
TBD
1.25
1.5
V
Input and Output Timing Reference
Level
VREF
TBD
1.25
1.5
V
TAP Output Load Equivalent
VREF
Test Comparator
Output
50Ω
20pF
50Ω
VREF
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JTAG AC Characteristics
(Over the Operating Temperature Range)
Parameter
Symbol
Min
Max
Units
TCK cycle time
tTHTH
100
–
ns
TCK high pulse width
tTHTL
40
–
ns
TCK low pulse width
tTLTH
40
–
ns
TMS Setup
tMVTH
10
–
ns
TMS Hold
tTHMX
10
–
ns
TDI Setup
tDVTH
10
–
ns
TDI Hold
tTHDX
10
–
ns
TCK Low to Valid Data
tTLOV
–
20
ns
JTAG Timing Diagram
TCK
TMS
tTHTH
tTHTL tTLTH
tTHMX
tMVTH
TDI
TDO
tTLOV
tTHDX
tDVTH
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Instruction Set
Code
Instruction
TDO Output
Notes
000
EXTEST
Boundary Scan Register
2, 6
001
IDCODE
32-bit Identification Register
010
SAMPLE-Z
Boundary Scan Register
1, 2
011
PRIVATE
Do Not Use
5
100
SAMPLE(/PRELOAD)
Boundary Scan Register
4
101
PRIVATE
Do Not Use
5
110
PRIVATE
Do Not Use
5
111
BYPASS
Bypass Register
3
Notes:
1. Places DQs in high-Z in order to sample all input data, regardless of other SRAM inputs.
2. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data.
3. BYPASS register is initiated to VSS when BYPASS instruction is invoked. The BYPASS register also holds the last serially loaded TDI when exiting the
shift-DR state.
4. SAMPLE instruction does not place DQs in high-Z.
5. This instruction is reserved. Invoking this instruction will cause improper SRAM functionality.
6. This EXTEST is not IEEE 1149.1-compliant. By default, it places DQ in high-Z. If the internal register on the scan chain is set high, DQ will be updated
with information loaded via a previous SAMPLE instruction. The actual transfer occurs during the update IR state after EXTEST is loaded. The value of
the internal register can be changed during SAMPLE and EXTEST only.
ID Register Definition
Instruction Field
Description
512K x 36
1024K x 18
Revision Number (31:28)
Reserved for version number.
xxxx
xxxx
Device Depth (27:23)
Defines depth of SRAM. 512K or
1024K
00111
01000
Device Width (22:18)
Defines Width of the SRAM. x36 or
x18
00100
00011
ISSI Device ID (17:12)
Reserved for future use.
xxxxxx
xxxxxx
ISSI JEDEC ID (11:1)
Allows unique identification of
SRAM vendor.
00001010101
00001010101
ID Register Presence (0)
Indicate the presence of an ID
register.
1
1
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Boundary Scan Order
(TBA – 119 BGA)
165 BGA
X36
X18
Bit #
Bump ID
Signal
Bump ID
Signal
1
N6
A9
N6
A9
2
N7
NC
N7
NC
3
N10
NC
N10
NC
4
P11
A8
P11
A8
5
P8
A18
P8
A18
6
R8
A17
R8
A17
7
R9
A16
R9
A16
8
P9
A15
P9
A15
9
P10
A14
P10
A14
10
R10
A13
R10
A13
11
R11
A12
R11
A12
12
H11
ZZ
H11
ZZ
13
N11
DQa0
N11
NC
14
M11
DQa1
M11
NC
15
L11
DQa2
L11
NC
16
M10
DQa3
M10
DQa8
17
L10
DQa4
L10
DQa7
18
K11
DQa5
K11
NC
19
J11
DQa6
J11
NC
20
K10
DQa7
K10
DQa6
21
J10
DQa8
J10
DQa5
22
H9
NC
H9
NC
23
H10
NC
H10
NC
24
G11
DQb8
G11
DQa4
25
F11
DQb7
F11
DQa3
26
G10
DQb6
G10
NC
27
E11
DQb5
E11
DQa2
28
D11
DQb4
D11
DQa1
29
F10
DQb3
C11
DQa0
30
E10
DQb2
E10
NC
31
D10
DQb1
D10
NC
32
C11
DQb0
F10
NC
33
A11
NC
A11
A19
34
B11
NC
B11
NC
35
A10
A11
A10
A11
36
B10
A10
B10
A10
37
A9
/ADV
A9
/ADV
38
B9
/ADSP
B9
/ADSP
39
C10
NC
C10
NC
40
A8
/ADSC
A8
/ADSC
Continued on next page
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165 BGA
X36
X18
Bit #
Bump ID
Signal
Bump ID
Signal
41
B8
/OE
B8
/OE
42
A7
/BWE
A7
/BWE
43
B7
/GW
B7
/GW
44
B6
CLK
B6
CLK
45
A6
/CE2
A6
/CE2
46
B5
/Bwa
B5
/Bwa
47
A5
/Bwb
A5
NC
48
A4
/Bwc
A4
/Bwb
49
B4
/Bwd
B4
NC
50
B3
CE2
B3
CE2
51
A3
/CE1
A3
/CE1
52
A2
A7
A2
A7
53
B2
A6
B2
A6
54
C2
NC
C2
NC
55
B1
NC
B1
NC
56
A1
NC
A1
NC
57
C1
DQc0
C1
NC
58
D1
DQc1
D1
NC
59
E1
DQc2
E1
NC
60
D2
DQc3
D2
DQb8
61
E2
DQc4
E2
DQb7
62
F1
DQc5
F1
NC
63
G1
DQc6
G1
NC
64
F2
DQc7
F2
DQb6
65
G2
DQc8
G2
DQb5
66
H1
NC
H1
NC
67
H2
NC
H2
NC
68
H3
NC
H3
NC
69
J1
DQd8
J1
DQb4
70
K1
DQd7
K1
DQb3
71
J2
DQd6
J2
NC
72
L1
DQd5
L1
DQb2
73
M1
DQd4
M1
DQb1
74
K2
DQd3
N1
DQb0
75
L2
DQd2
L2
NC
76
M2
DQd1
M2
NC
77
N1
DQd0
K2
NC
78
N2
NC
N2
NC
79
P1
NC
P1
NC
80
R1
MODE
R1
MODE
Continue on next page
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165 BGA
X36
X18
Bit #
Bump ID
Signal
Bump ID
Signal
81
R2
NC
R2
NC
82
P3
A5
P3
A5
83
R3
A4
R3
A4
84
P2
NC
P2
NC
85
P4
A2
P4
A2
86
R4
A3
R4
A3
87
N5
NC
N5
NC
88
P6
A1
P6
A1
89
R6
A0
R6
A0
90
*
Int
*
Int
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ORDERING INFORMATION
Commercial Range: 0°C to +70°C
VDD
Speed
X36
X18
Package
VDD=3.3V, VDDQ=2.5V/3.3V
6.5ns
IS61LF51236B-6.5TQ
IS61LF102418B-6.5TQ
100 QFP
IS61LF51236B-6.5B3
IS61LF102418B-6.5B3
165 BGA
IS61LF51236B-6.5B2
IS61LF102418B-6.5B2
119 BGA
IS61LF51236B-6.5TQL
IS61LF102418B-6.5TQL
100 QFP, Lead-free
IS61LF51236B-6.5B3L
IS61LF102418B-6.5B3L
165 BGA, Lead-free
IS61LF51236B-6.5B2L
IS61LF102418B-6.5B2L
119 BGA, Lead-free
7.5ns
IS61LF51236B-7.5TQ
IS61LF102418B-7.5TQ
100 QFP
IS61LF51236B-7.5B3
IS61LF102418B-7.5B3
165 BGA
IS61LF51236B-7.5B2
IS61LF102418B-7.5B2
119 BGA
IS61LF51236B-7.5TQL
IS61LF102418B-7.5TQL
100 QFP, Lead-free
IS61LF51236B-7.5B3L
IS61LF102418B-7.5B3L
165 BGA, Lead-free
IS61LF51236B-7.5B2L
IS61LF102418B-7.5B2L
119 BGA, Lead-free
VDD =2.5V, VDDQ=2.5V
6.5ns
*Please contact ISSI Marketing
7.5ns
*Please contact ISSI Marketing
VDD=1.8V, VDDQ=1.8V
6.5ns
*Please contact ISSI Marketing
7.5ns
*Please contact ISSI Marketing
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ORDERING INFORMATION
Industrial Range: -40°C to +85°C
VDD
Speed
X36
X18
Package
VDDQ=3.3V, VDDQ=2.5V/3.3V
6.5ns
IS61LF51236B-6.5TQI
IS61LF102418B-6.5TQI
100 QFP
IS61LF51236B-6.5B3I
IS61LF102418B-6.5B3I
165 BGA
IS61LF51236B-6.5B2I
IS61LF102418B-6.5B2I
119 BGA
IS61LF51236B-6.5TQLI
IS61LF102418B-6.5TQLI
100 QFP, Lead-free
IS61LF51236B-6.5B3LI
IS61LF102418B-6.5B3LI
165 BGA, Lead-free
IS61LF51236B-6.5B2LI
IS61LF102418B-6.5B2LI
119 BGA, Lead-free
7.5ns
IS61LF51236B-7.5TQI
IS61LF102418B-7.5TQI
100 QFP
IS61LF51236B-7.5B3I
IS61LF102418B-7.5B3I
165 BGA
IS61LF51236B-7.5B2I
IS61LF102418B-7.5B2I
119 BGA
IS61LF51236B-7.5TQLI
IS61LF102418B-7.5TQLI
100 QFP, Lead-free
IS61LF51236B-7.5B3LI
IS61LF102418B-7.5B3LI
165 BGA, Lead-free
IS61LF51236B-7.5B2LI
IS61LF102418B-7.5B2LI
119 BGA, Lead-free
VDD=2.5V, VDDQ=2.5V
6.5ns
*Please contact ISSI Marketing
7.5ns
*Please contact ISSI Marketing
VDD=1.8V, VDDQ=1.8V
6.5ns
*Please contact ISSI Marketing
7.5ns
*Please contact ISSI Marketing
Automotive Range: -40°C to +125°C
VDD
Speed
X36
Package
VDDQ=3.3V, VDDQ=2.5V/3.3V
7.5ns
IS64LF51236B-7.5TQLA3
100 QFP, Lead-free
IS64LF51236B-7.5B3LA3
165 BGA, Lead-free
IS64LF51236B-7.5B2LA3
119 BGA, Lead-free
*For all other voltages and options in automotive grade, please contact ISSI.
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
09/12/2015
33
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
09/12/2015
34
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
09/12/2015
35