HYS72D128320GU-6-A - Infineon Technologies

INFINEON Technologies 1 2002-09-10 (rev.0.81)

HYS64/72D64000/128020GU-7/8-A

Unbuffered DDR-I SDRAM-Modules

2.5 V 184-pin Unbuffered DDR-I SDRAM Modules

512 MByte & 1024 MByte Modules

PC1600, PC2100 & PC2700

Preliminary datasheet rev. 0.81

The HYS64/72D64000GU and HYS64/72D128020GU are industry standard 184-pin 8-byte Dual

in-line Memory Modules (DIMMs) organized as 64M ×64 and 128M ×64 for non-parity and 64M x

72 and 128M x 72 forECC main memory applications. The memoryarray is designed with 512Mbit

Double Data Rate Synchronous DRAMs. A variety of decoupling capacitors are mounted on the PC

board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin

I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes

are available to the customer.

• 184-pin Unbuffered 8-Byte Dual-In-Line

DDR-I SDRAM non-parity and ECC-Modules

for PC and Server main memory applications

• One bank 64M x 64, 64M x 72 and two bank

128M x 64, 128M ×72 organization

• JEDEC standard Double Data Rate

Synchronous DRAMs (DDR-I SDRAM)

Single + 2.5 V (±0.2 V) power supply

• Builtwith512MbitDDR-I SDRAMs organized

as 64Mb x 8 in 66-Lead TSOPII package

• Programmable CAS Latency, Burst Length,

and Wrap Sequence (Sequential &

Interleave)

• Auto Refresh (CBR) and Self Refresh

• All inputs and outputs SSTL_2 compatible

• Serial Presence Detect with E2PROM

• Jedec standard MO-206 form factor:

133.35 mm ×31.75 mm ×4.00 mm max.

• Jedec standard reference layout

• Gold plated contacts

• Performance:

-6 -7 -8 Unit

Component Speed Grade DDR333B DDR266A DDR200

Module Speed Grade PC2700 PC2100 PC1600

fCK Clock Frequency (max.) @ CL = 2.5 166 143 125 MHz

fCK Clock Frequency (max.) @ CL = 2 133 133 100 MHz

HYS64/72D64000/128x20GU-7/8-A

Unbuffered DDR-I SDRAM-Modules

INFINEON Technologies 2 2002-09-10 (rev.0.81)

Ordering Information

Type Compliance Code Description SDRAM

Technology

PC2700 (CL=2.5):

HYS64D128320GU-6-A PC2700-25330-B1 two banks 1024 MB DIMM 512 MBit

HYS72D128320GU-6-A PC2700-25330-B1 two banks 1024 MB ECC-DIMM 512 MBit

PC2100 (CL=2):

HYS64D64000GU-7-A PC2100-20330-A1 one bank 512 MB DIMM 512 MBit

HYS72D64000GU-7-A PC2100-20330-A1 one bank 512 MB ECC-DIMM 512 Mbit

HYS64D128020GU-7-A PC2100-20330-B1 two banks 1024 MB DIMM 512 MBit

HYS72D128020GU-7-A PC2100-20330-B1 two banks 1024 MB ECC-DIMM 512 MBit

PC1600 (CL=2):

HYS64D64000GU-8-A PC1600-20220-A1 one bank 512 MB DIMM 512 MBit

HYS72D64000GU-8-A PC1600-20220-A1 one bank 512 MB ECC-DIMM 512 Mbit

HYS64D128020GU-8-A PC1600-20220-B1 two banks 1024 MB DIMM 512 MBit

HYS72D128020GU-8-A PC1600-20220-B1 two banks 1024 MB ECC-DIMM 512 MBit

Note: All part numbers end with a place code, designating the silicon-die revision. Reference information

available on request. Example: HYS 72D64000GU-8-A, indicating Rev.A dies are used for the SDRAM

components.

The Compliance Code is printed on the module labels and describes the speed sort fe. “PC2100”, the

latencies (f.e. “20330” means CAS latency = 2, trcd latency = 3 and trp latency =3 ) and the Raw Card

used for this module.

HYS64/72D64000/128020GU-7/8-A

Unbuffered DDR-I SDRAM-Modules

INFINEON Technologies 3 2002-09-10 (rev.0.81)

Pin Definitions and Functions

A0 - A12 Address Inputs S0, S1 Chip Selects

BA0, BA1 Bank Selects VDD Power (+ 2.5 V)

DQ0 - DQ63 Data Input/Output VSS Ground

CB0 - CB7 Check Bits (x72 organization only) VDDQ I/O Driver power supply

RAS Row Address Strobe VDDID VDD Indentification flag

CAS Column Address Strobe VREF I/O reference supply

WE Read/Write Input VDDSPD Serial EEPROM power supply

CKE0 - CKE1 Clock Enable SCL Serial bus clock

DQS0 - DQS8 SDRAM low data strobes SDA Serial bus data line

CLK0 - CLK2, SDRAM clock (positive lines) SA0 - SA2 slave address select

CLK0 -CLK2 SDRAM clock (negative lines) NC no connect

DM0 - DM8

DQS9 - DQS17 SDRAM low data mask/

high data strobes

note: S1and CKE1 are used on two bank modules only

Address Format

Density Organization Memory

Banks SDRAMs # of

SDRAMs # of row/bank/

columns bits Refresh Period Interval

512 MB 64M x 64 1 64M x 8 8 13/2/11 8k 64 ms 7.8 µs

512 MB 64M x 72 1 64M x 8 9 13/2/11 8k 64 ms 7.8 µs

1024 MB 128M ×64 2 64M x 8 16 13/2/11 8k 64 ms 7.8 µs

1024 MB 128M ×72 2 64M x 8 18 13/2/11 8k 64 ms 7.8 µs

HYS64/72D64000/128x20GU-7/8-A

Unbuffered DDR-I SDRAM-Modules

INFINEON Technologies 4 2002-09-10 (rev.0.81)

Pin Configuration

Frontside Frontside Backside Backside

PIN# Symbol PIN# Symbol PIN# Symbol PIN# Symbol

1 VREF 48 A0 93 VSS 140 NC / DM8/DQS17

2 DQ0 49 NC / CB2 94 DQ4 141 A10

3 VSS 50 VSS 95 DQ5 142 NC / CB6

4 DQ1 51 NC / CB3 96 VDDQ 143 VDDQ

5 DQS0 52 BA1 97 DM0/DQS9 144 NC / CB7

6DQ2 KEY 98 DQ6 KEY

7 VDD 53 DQ32 99 DQ7 145 VSS

8 DQ3 54 VDDQ 100 VSS 146 DQ36

9 NC 55 DQ33 101 NC 147 DQ37

10 NC 56 DQS4 102 NC 148 VDD

11 VSS 57 DQ34 103 NC 149 DM4/DQS13

12 DQ8 58 VSS 104 VDDQ 150 DQ38

13 DQ9 59 BA0 105 DQ12 151 DQ39

14 DQS1 60 DQ35 106 DQ13 152 VSS

15 VDDQ 61 DQ40 107 DM1/DQS10 153 DQ44

16 CLK1 62 VDDQ 108 VDD 154 RAS

17 CLK1 63 WE 109 DQ14 155 DQ45

18 VSS 64 DQ41 110 DQ15 156 VDDQ

19 DQ10 65 CAS 111 CKE1 157 S0

20 DQ11 66 VSS 112 VDDQ 158 S1

21 CKE0 67 DQS5 113 NC (BA2) 159 DM5/DQS14

22 VDDQ 68 DQ42 114 DQ20 160 VSS

23 DQ16 69 DQ43 115 NC / A12 161 DQ46

24 DQ17 70 VDD 116 VSS 162 DQ47

25 DQS2 71 NC 117 DQ21 163 NC

26 VSS 72 DQ48 118 A11 164 VDDQ

27 A9 73 DQ49 119 DM2/DQS11 165 DQ52

28 DQ18 74 VSS 120 VDD 166 DQ53

29 A7 75 CLK2 121 DQ22 167 NC (A13)

30 VDDQ 76 CLK2 122 A8 168 VDD

31 DQ19 77 VDDQ 123 DQ23 169 DM6/DQS15

32 A5 78 DQS6 124 VSS 170 DQ54

33 DQ24 79 DQ50 125 A6 171 DQ55

34 VSS 80 DQ51 126 DQ28 172 VDDQ

35 DQ25 81 VSS 127 DQ29 173 NC

36 DQS3 82 VDDID 128 VDDQ 174 DQ60

37 A4 83 DQ56 129 DM3/DQS12 175 DQ61

38 VDD 84 DQ57 130 A3 176 VSS

39 DQ26 85 VDD 131 DQ30 177 DM7/DQS16

40 DQ27 86 DQS7 132 VSS 178 DQ62

41 A2 87 DQ58 133 DQ31 179 DQ63

42 VSS 88 DQ59 134 NC / CB4 180 VDDQ

43 A1 89 VSS 135 NC / CB5 181 SA0

44 NC / CB0 90 NC 136 VDDQ 182 SA1

45 NC / CB1 91 SDA 137 CK0 183 SA2

46 VDD 92 SCL 138 CK0 184 VDDSPD

47 NC / DQS8 139 VSS

Note: Pins 44, 45, 47, 49, 51, 134, 135, 140 and 144 are NC (“no-connects”) on x64 organised non-ECC

modules.

HYS64/72D64000/128020GU-7/8-A

Unbuffered DDR-I SDRAM-Modules

INFINEON Technologies 5 2002-09-10 (rev.0.81)

Block Diagram: One Bank 64M x 64 DDR-I SDRAM DIMM Module

HYS64D64000GU using x8 organized SDRAMs

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

I/O 7

I/O 6

I/O 1

I/O 0

DM0/DQS9

I/O 5

I/O 4

I/O 3

I/O 2

DQ12

DQ13

DQ14

DQ8

DQ9

DQ10

DQ11

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

DM1/DQS10

DQ20

DQ21

DQ22

DQ23

DQ16

DQ17

DQ18

DQ19

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DM2/DQS11

DQ28

DQ29

DQ30

DQ31

DQ24

DQ25

DQ26

DQ27

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DM3/DQS12

DQ36

DQ37

DQ38

DQ39

DQ32

DQ33

DQ34

DQ35

I/O 7

I/O 6

I/O 1

I/O 0

DM4/DQS13

I/O 5

I/O 4

I/O 3

I/O 2

DQ44

DQ45

DQ46

DQ47

DQ40

DQ41

DQ42

DQ43

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DM5/DQS14

DQ52

DQ53

DQ54

DQ55

DQ48

DQ49

DQ50

DQ51

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQ60

DQ61

DQ62

DQ63

DQ56

DQ57

DQ58

DQ59

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DM7/DQS16

A0 -A11, A12 A0 - A11,A12: SDRAMs D0 - D7

Serial PD

A1 A2

SA0 SA1 SA2

SCL SDA

RAS RAS: SDRAMs D0 - D7

CAS CAS: SDRAMs D0 - D7

CKE0 CKE: SDRAMs D0 - D7

WE WE :SDRAMsD0-D7

BA0 - BA1 BA0, BA1: SDRAMs D0 - D7

DQS0

DQS

DQS4

DQS1 DQS5

DQS

DQS2

DQS

DQS3

DQS

DM6/DQS15

DQS6

DQS7

DQ15 I/O 2

DQS

Notes:

1. DQ-to-I/O wiring is shown as recom-

mended but may be changed.

2. DQ/DQS/DM/CKE/S relationships must

be maintained as shown.

3.DQ,DQS,DM/DQSresistors:22Ohms.

4. VDDID strap connections

(for memory device VDD, VDDQ):

STRAP OUT (OPEN): VDD = VDDQ

*ClockWiring

*CK0/CK0

Clock

Input SDRAMs

*CK1/CK1 2 SDRAMs

3 SDRAMs

* Wire per Clock Loading

Table/Wiring Diagrams

*CK2/CK2

DD,

DDQ

VREF

DDID

D0 - D7

CS CS

HYS64/72D64000/128x20GU-7/8-A

Unbuffered DDR-I SDRAM-Modules

INFINEON Technologies 6 2002-09-10 (rev.0.81)

Block Diagram: Two Bank 128M x 64 DDR-I SDRAM DIMM Modules

HYS64D128020GU using x8 Organized SDRAMs

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

I/O 7

I/O 6

I/O 1

I/O 0

DM0/DQS9

I/O 5

I/O 4

I/O 3

I/O 2

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DQ12

DQ13

DQ14

DQ8

DQ9

DQ10

DQ11

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

DM1/DQS10

DQ20

DQ21

DQ22

DQ23

DQ16

DQ17

DQ18

DQ19

I/O 7

I/O 6

I/O 1

I/O 0

D10

I/O 5

I/O 4

I/O 3

I/O 2

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DM2/DQS11

DQ28

DQ29

DQ30

DQ31

DQ24

DQ25

DQ26

DQ27

I/O 7

I/O 6

I/O 1

I/O 0

D11

I/O 5

I/O 4

I/O 3

I/O 2

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DM3/DQS12

DQ36

DQ37

DQ38

DQ39

DQ32

DQ33

DQ34

DQ35

I/O 7

I/O 6

I/O 1

I/O 0

DM4/DQS13

D12

I/O 5

I/O 4

I/O 3

I/O 2

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DQ44

DQ45

DQ46

DQ47

DQ40

DQ41

DQ42

DQ43

I/O 7

I/O 6

I/O 1

I/O 0

D13

I/O 5

I/O 4

I/O 3

I/O 2

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DM5/DQS14

DQ52

DQ53

DQ54

DQ55

DQ48

DQ49

DQ50

DQ51

I/O 7

I/O 6

I/O 1

I/O 0

D14

I/O 5

I/O 4

I/O 3

I/O 2

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DQ60

DQ61

DQ62

DQ63

DQ56

DQ57

DQ58

DQ59

I/O 7

I/O 6

I/O 1

I/O 0

D15

I/O 5

I/O 4

I/O 3

I/O 2

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DM7/DQS16

A0 - A12 A0 - A12: SDRAMs D0 - D15

Serial PD

A1 A2

SA0 SA1 SA2

SCL SDA

RAS RAS:SDRAMsD0-D15

CAS CAS:SDRAMsD0-D15

CKE0 CKE: SDRAMs D0 - D7

WE WE:SDRAMsD0-D15

S0 S1

CKE1 CKE: SDRAMs D8 - D15

BA0, BA1 BA0, BA1: SDRAMs D0, D15

DQS0

DQS

DQS4

DQS1 DQS5

DQS DQS

DQS2

DQS DQS

DQS3

DQS DQS

DM6/DQS15

DQS6

DQS7

DQ15 I/O 2 I/O 5

DQS DQS

DQS

DQSDQS

DQS

*ClockWiring

*CK0/CK0

Clock

Input SDRAMs

*CK1/CK1 4SDRAMs

6SDRAMs

* Wire per Clock Loading

Table/Wiring Diagrams

*CK2/CK2

Notes:

1. DQ-to-I/O wiring is shown as recom-

mended but may be changed.

2. DQ/DQS/DM/CKE/S relationships must

be maintained as shown.

3. DQ, DQS, DM/DQS resistors: 22 Ohms.

4. VDDID strap connections

(for memory device VDD, VDDQ):

STRAP OUT (OPEN): VDD = VDDQ

DD,

DDQ

VREF

DDID

D0 - D15

CS CS

CS CS CS CS

CS CS

HYS64/72D64000/128020GU-7/8-A

Unbuffered DDR-I SDRAM-Modules

INFINEON Technologies 7 2002-09-10 (rev.0.81)

Block Diagram: One Bank 64M x 72 DDR-I SDRAM DIMM Module

HYS72D64000GU using x8 organized SDRAMs

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

I/O 7

I/O 6

I/O 1

I/O 0

DM0/DQS9

I/O 5

I/O 4

I/O 3

I/O 2

DQ12

DQ13

DQ14

DQ8

DQ9

DQ10

DQ11

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

DM1/DQS10

DQ20

DQ21

DQ22

DQ23

DQ16

DQ17

DQ18

DQ19

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DM2/DQS11

DQ28

DQ29

DQ30

DQ31

DQ24

DQ25

DQ26

DQ27

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DM3/DQS12

DQ36

DQ37

DQ38

DQ39

DQ32

DQ33

DQ34

DQ35

I/O 7

I/O 6

I/O 1

I/O 0

DM4/DQS13

I/O 5

I/O 4

I/O 3

I/O 2

DQ44

DQ45

DQ46

DQ47

DQ40

DQ41

DQ42

DQ43

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DM5/DQS14

DQ52

DQ53

DQ54

DQ55

DQ48

DQ49

DQ50

DQ51

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQ60

DQ61

DQ62

DQ63

DQ56

DQ57

DQ58

DQ59

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DM7/DQS16

A0 - A11,A12 A0 - A11, A12: SDRAMs D0 - D8

Serial PD

A1 A2

SA0 SA1 SA2

SCL SDA

RAS RAS: SDRAMs D0 - D8

CAS CAS: SDRAMs D0 - D8

CKE0 CKE: SDRAMs D0 - D8

WE WE:SDRAMsD0 - D8

BA0, BA1 BA0, BA1: SDRAMs D0 - D8

DQS0

DQS

DQS4

DQS1 DQS5

DQS

DQS2

DQS

DQS3

DQS

DM6/DQS15

DQS6

DQS7

DQ15 I/O 2

DQS

Notes:

1. DQ-to-I/O wiring is shown as recom-

mended but may be changed.

2. DQ/DQS/DM/CKE/S relationships must

be maintained as shown.

3. DQ, DQS, DM/DQS resistors: 22 Ohms.

4. VDDID strap connections

(for memory device VDD, VDDQ):

STRAP OUT (OPEN): VDD = VDDQ

*ClockWiring

*CK0/CK0

Clock

Input SDRAMs

*CK1/CK1 3SDRAMs

3SDRAMs

* Wire per Clock Loading

Table/Wiring Diagrams

*CK2/CK2

CB4

CB5

CB6

CB7

CB0

CB1

CB2

CB3

DM8/DQS17

DQS8

DQS

DD,

DDQ

VREF

DDID

D0 - D8

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

CS CS

HYS64/72D64000/128x20GU-7/8-A

Unbuffered DDR-I SDRAM-Modules

INFINEON Technologies 8 2002-09-10 (rev.0.81)

Block Diagram: Two Bank 128M x 72 DDR-I SDRAM DIMM Modules

HYS72D128020GU using x8 Organized SDRAMs

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

I/O7

I/O 6

I/O 1

I/O 0

DM0/DQS9

I/O 5

I/O 4

I/O 3

I/O 2

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DQ12

DQ13

DQ14

DQ8

DQ9

DQ10

DQ11

I/O 7

I/O 6

I/O 1

I/O 0

D10

I/O 5

I/O 4

I/O 3

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

DM1/DQS10

DQ20

DQ21

DQ22

DQ23

DQ16

DQ17

DQ18

DQ19

I/O 7

I/O 6

I/O 1

I/O 0

D11

I/O 5

I/O 4

I/O 3

I/O 2

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DM2/DQS11

DQ28

DQ29

DQ30

DQ31

DQ24

DQ25

DQ26

DQ27

D12

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DM3/DQS12

DQ36

DQ37

DQ38

DQ39

DQ32

DQ33

DQ34

DQ35

I/O 7

I/O 6

I/O 1

I/O 0

DM4/DQS13

D13

I/O 5

I/O 4

I/O 3

I/O 2

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DQ44

DQ45

DQ46

DQ47

DQ40

DQ41

DQ42

DQ43

I/O 7

I/O 6

I/O 1

I/O 0

D14

I/O 5

I/O 4

I/O 3

I/O 2

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DM5/DQS14

DQ52

DQ53

DQ54

DQ55

DQ48

DQ49

DQ50

DQ51

I/O 7

I/O 6

I/O 1

I/O 0

D15

I/O 5

I/O 4

I/O 3

I/O 2

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DQ60

DQ61

DQ62

DQ63

DQ56

DQ57

DQ58

DQ59

I/O 7

I/O 6

I/O 1

I/O 0

D16

I/O 5

I/O 4

I/O 3

I/O 2

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DM7/DQS16

A0 - A12 A0 - A12: SDRAMs D0 - D17

Serial PD

A1 A2

SA0 SA1 SA2

SCL SDA

RAS RAS:SDRAMsD0-D17

CAS CAS:SDRAMsD0-D17

CKE0 CKE: SDRAMs D0 - D8

WE WE:SDRAMsD0-D17

S0 S1

CKE1 CKE: SDRAMs D9 - D17

BA0, BA1 BA0, BA1: SDRAMs D0 - D17

DQS0

DQS

DQS4

DQS1 DQS5

DQS DQS

DQS2

DQS DQS

DQS3

DQS DQS

DM6/DQS15

DQS6

DQS7

DQ15 I/O 2 I/O 5

DQS DQS

DQS

DQSDQS

DQS

*ClockWiring

*CK0/CK0

Clock

Input SDRAMs

*CK1/CK1 6 SDRAMs

6 SDRAMs

* Wire per Clock Loading

Table/Wiring Diagrams

*CK2/CK2

Notes:

1. DQ-to-I/O wiring is shown as recom-

mended but may be changed.

2. DQ/DQS/DM/CKE/S relationships must

be maintained as shown.

3.DQ,DQS,DM/DQSresistors:22Ohms.

4. VDDID strap connections

(for memory device VDD, VDDQ):

STRAP OUT (OPEN): VDD = VDDQ

CB4

CB5

CB6

CB7

CB0

CB1

CB2

CB3

DM8/DQS17

DQS8

DQS DQS

DD,

DDQ

VREF

DDID

D0 - D17

CS CS

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

D17

CS CS

HYS64/72D64000/128020GU-7/8-A

Unbuffered DDR-I SDRAM-Modules

INFINEON Technologies 9 2002-09-10 (rev.0.81)

Clock Net Wiring

Absolute Maximum Ratings

Parameter Symbol Limit Values Unit

min. max.

Input / Output voltage relative to VSS VIN, VOUT –0.5 3.6 V

Power supply voltage on VDD/VDDQ to VSS VDD, VDDQ –0.5 3.6 V

Storage temperature range TSTG -55 +150 oC

Power dissipation (per SDRAM component) PD–1W

Data out current (short circuit) IOS –50mA

Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded.

Functional operation should be restricted to recommended operation conditions.

Exposure to higher than recommended voltage for extended periods of time affect device reliability

4 DRAM Loads

DIMM

DRAM 1

DRAM2

DRAM4

DRAM5

DRAM6

DRAM 1

Cap.

DRAM3

DRAM5

Cap.

DRAM 1

Cap.

DRAM5

Cap.

DRAM 1

DRAM5

Cap.

DRAM3

DRAM2

DRAM6

Connector Connector

DIMM

R=120 R=

120

Connector

DIMM Connector

DIMM R=120

R=120

6 DRAM Loads

3 DRAM Loads 2 DRAM Loads

HYS64/72D64000/128x20GU-7/8-A

Unbuffered DDR-I SDRAM-Modules

INFINEON Technologies 10 2002-09-10 (rev.0.81)

Supply Voltage Levels

Parameter Symbol Limit Values Unit Notes

min. nom. max.

Device Supply Voltage VDD 2.3 2.5 2.7 V –

Output Supply Voltage VDDQ 2.3 2.5 2.7 V 1)

1) Under all conditions, VDDQ must be less than or equal to VDD.

Input Reference Voltage VREF 0.49 x VDDQ 0.5 x VDDQ 0.51 x VDDQ V2)

2) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC).VREF is also expected to track noise variations

in VDDQ.

Termination Voltage VTT VREF –0.04 VREF VREF +0.04 V 3)

3) VTT of the transmitting device must track VREF of the receiving device.

EEPROM supply voltage VDDSPD 2.3 2.5 3.6 V

DC Operating Conditions (SSTL_2 Inputs)

(VDDQ =2.5V,TA=70°C, Voltage Referenced to VSS)

Parameter Symbol Limit Values Unit Notes

min. max.

DC Input Logic High VIH (DC) VREF +0.15 VDDQ +0.3 V 1)

1) The relationship between the VDDQ of the driving device and the VREF of the receiving device is what determines

noise margins. However, in the case of VIH (max) (input overdrive), it is the VDDQ of the receiving device that is

referenced. In the case where a device is implemented such that it supports SSTL_2 inputs but has no SSTL_2

outputs (such as a translator), and therefore no VDDQ supply voltage connection, inputs must tolerate input

overdrive to 3.0 V (High corner VDDQ + 300 mV).

DC Input Logic Low VIL (DC) –0.30 VREF –0.15 V –

Input Leakage Current IIL –5 5 µA2)

2) For any pin under test input of 0 V ≤VIN ≤VDDQ + 0.3 V. Values are shown per DDR-SDRAM component.

Output Leakage Current IOL –5 5 µA2)

HYS64/72D64000/128020GU-7/8-A

Unbuffered DDR-I SDRAM-Modules

INFINEON Technologies 11 2002-09-10 (rev.0.81)

Operating, Standby and Refresh Currents (PC1600)

Notes

IDD2P mA 2

IDD2F mA 2

IDD2Q mA 2

IDD3P mA 2

IDD5 mA 1

mA 1

1.The moduleIDDvaluesare calculated from the component IDD datasheetvalues as:

n * IDDx[component] for single bankmodules (n: number ofcomponents permodule bank)

n * IDDx[component] +n * IDD3N[component] for two bank modules (n:number ofcomponents per module bank)

2.The moduleIDDvaluesare calculated from the component IDD datasheetvalues as:

n * IDDx[component] for single bankmodules (n: number ofcomponents permodule bank)

2 * n *IDDx[component] for two bankmodules (n:number ofcomponents permodule bank)

3.DQ I/O(IDDQ) currentsare notincluded into calculations:module IDD valueswill be measured differentlydepending on loadconditions

4.Test condition for maximum values:VDD = 2.7V ,Ta= 10°C

512MB

x64

1bank

-8

512MB

x72

1bank

-8

1GB

x64

2bank

-8

1GB

x72

2bank

-8

Precharge Power-Down Standby Current: all banks idle;power-down

mode;CKE <=VILMAX; tCK = tCK MIN

Precharge Floating Standby Current:/CS>= VIH MIN, all banks idle;

CKE >=VIHMIN;tCK = tCK MIN ,address and other control inputs

changing once perclockcycle, VIN = VREF for DQ, DQS and DM.

144

360

mA 1, 3

900 mA

256

800

640 720

225

1,3

mA 1

2610

1440

1485

450

Active Power-Down Standby Current: onebank active;power-down

mode;CKE<=VILMAX; tCK = tCK MIN;VIN = VREF for DQ, DQS and

DM.

Active Standby Current: one bank active;active / prechar

e;CS >=VIH

MIN;CKE>=VIHMIN;tRC = tRAS MAX; tCK = tCK MIN;DQ,DM,and

DQS inputs changing twice per clock cycle;address and control inputs

changing once perclockcycle

Operating Current:one bank active;Burst = 2;reads;continuous burst;

addressand control inputs changing once per clock cycle;50% of data

outputschanging on everyclock edge;CL = 2 for DDR200,and

DDR266A, CL=3 for DDR333;tCK = tCK MIN;IOUT = 0mA

Operating Current:one bank active;Burst = 2;writes;continuous burst;

addressand control inputs changing once per clock cycle;50% of data

outputschanging on everyclock edge;CL = 2 for DDR200,and

DDR266A, CL=3 for DDR333;tCK = tCK MIN

Precharge Quiet Standby Current:/CS>=VIH MIN, all banks idle;

CKE >=VIHMIN;tCK = tCK MIN ,address and other control inputs

stable at >=VIHMINor<=VILMAX; VIN = VREF for DQ,DQS and DM.

IDD0

Operating Current:one bank;active/read/precharge;Burst = 4;

Refer to the following page for detailed testconditions.

Operating Current:one bank;active / prechar

e;tRC=tRCMIN;tCK =

tCK MIN;DQ,DM,and DQS inputs changing once perclockcycle;

addressand control inputs changingonceeverytwo clockcycles

IDD1

108

1530

1440 1680

1760

192

1890

1935

288

450

216

1980

1890

Symbol UnitParameter/Condition

IDD4W

IDD4R

IDD3N

200

1720

1680

Auto-Refresh Current: tRC = tRFC MIN,distributed refresh 2320

1,336003150

45 80 90 mA

3200IDD7

IDD6

Operating Current:fourbank;four bank interleaving with BL=4;

Refer to the following page for detailed testconditions. 2800

Self-Refresh Current:CKE<=0.2V;external clockon;tCK=tCKMIN

320

128

400

1280

1320

400

2720 3060

MAXMAXMAXMAX

1280

1360

HYS64/72D64000/128x20GU-7/8-A

Unbuffered DDR-I SDRAM-Modules

INFINEON Technologies 12 2002-09-10 (rev.0.81)

Operating, Standby and Refresh Currents (PC2100 and PC2700)

Notes

IDD2P mA 2

IDD2F mA 2

IDD2Q mA 2

IDD3P mA 2

IDD5 mA 1

448

3040 3420

MAXMAXMAXMAX

1360

1440

112

400

144

560

1560

1600

IDD7

IDD6

Operating Current: four bank;four bank interleaving with BL=4;

Refer to the following page for detailed test conditions. 3040

Self-Refresh Current:CKE<=0.2V;external clock on;tCK=tCKMIN

Auto-Refresh Current: tRC = tRFC MIN, distributed refresh 2480

1,340503420

45 80 90 mA

3600 mA

Symbol UnitParameter/Condition

IDD4W

IDD4R

IDD3N

224

2160

2120 2385

2430

324

504

252

2250

2160

126

1620

1530 1920

2000

224

2200 2475

2320 2610

Precharge Quiet Standby Current:/CS>= VIH MIN, all banks idle;

CKE >=VIHMIN;tCK = tCK MIN ,address and other control inputs

stable at >=VIHMINor<=VILMAX; VIN = VREF for DQ, DQS and DM.

IDD0

Operating Current: one bank;active/read/precharge;Burst= 4;

Refer to the following page for detailed test conditions.

Operating Current: one bank;active /precharge;tRC = tRC MIN;tCK =

tCK MIN;DQ, DM,and DQS inputs changing once per clock cycle;

address and control inputs changing once every two clock cycles

IDD1

Active Power-Down Standby Current: one bank active;power-down

mode;CKE<=VILMAX; tCK = tCK MIN;VIN = VREF for DQ, DQS and

DM.

Active Standby Current: one bank active;active / precharge;CS >=VIH

MIN;CKE>=VIHMIN;tRC = tRAS MAX; tCK=tCKMIN;DQ,DM, and

DQS inputschanging twice per clock cycle;address and control inputs

changing once per clock cycle

Operating Current: one bankactive;Burst = 2;reads;continuous burst;

address and control inputs changing once per clock cycle;50% of data

outputs changing on every clock edge;CL =2 for DDR200,and

DDR266A, CL=3 for DDR333;tCK = tCK MIN;IOUT = 0mA

Operating Current:one bank active;Burst = 2;writes;continuous burst;

address and control inputs changing once per clock cycle;50% ofdata

outputs changing on every clock edge;CL =2 for DDR200,and

DDR266A, CL=3 for DDR333;tCK = tCK MIN

2790

1755

1800

630

1,3

mA 1

450

mA 1,3

1260 mA

288

1120

800 900

252

1.The moduleIDD values are calculated from the componentIDD datasheetvalues as:

n * IDDx[component] for single bank modules (n: number of components per module bank)

n * IDDx[component]+ n * IDD3N[component] for two bank modules (n:number of components per module bank)

2.The moduleIDD values are calculated from the componentIDD datasheetvalues as:

n * IDDx[component] for single bank modules (n: number of components per module bank)

2 * n * IDDx[component] for two bank modules (n: number of components per module bank)

3.DQI/O(IDDQ) currents arenotincluded into calculations:module IDD valueswill be measureddifferentlydepending on load conditions

4.Testcondition for maximum values: VDD = 2.7V,Ta = 10°C

mA 1

512MB

x64

1bank

-7

512MB

x72

1bank

-7

1GB

x64

2bank

-7

1GB

x72

2bank

-7

Precharge Power-Down Standby Current: all banks idle;power-down

mode;CKE <=VILMAX; tCK = tCK MIN

Precharge Floating Standby Current:/CS>= VIH MIN, all banks idle;

CKE >=VIHMIN;tCK = tCK MIN ,address and other control inputs

changing once per clock cycle, VIN = VREF for DQ,DQSand DM.

162

1GB

x64

2bank

-6

1GB

x72

2bank

-6

MAXMAX

288 324

960 1080

640 720

368 414

1200 1350

2560 2880

2480 2790

3280 3690

80 90

3840 4320

HYS64/72D64000/128020GU-7/8-A
Unbuffered DDR-I SDRAM-Modules
INFINEON Technologies 13 2002-09-10 (rev.0.81)
Electrical Characteristics & AC Timing for DDR-I components
(for reference only)
(0 °C≤ TA≤ 70 °C; VDDQ =2.5V± 0.2V;VDD =2.5V± 0.2V)
Symbol Parameter DDR333
-6 DDR266A
-7 DDR200
-8 Unit Notes
Min Max Min Max Min Max
tAC DQ output access time from CK/CK −0.7 +0.7 −0.75 +0.75 −0.8 +0.8 ns 1-4
tDQSCK DQS output access time from CK/CK −0.7 +0.7 −0.75 +0.75 −0.8 +0.8 ns 1-4
tCH CK high-level width 0.45 0.55 0.45 0.55 0.45 0.55 tCK 1-4
tCL CK low-level width 0.45 0.55 0.45 0.55 0.45 0.55 tCK 1-4
tHP Clock Half Period min (tCL, tCH) min (tCL,tCH) min (tCL, tCH) ns 1-4
tCK Clock cycle time CL=2.5 612712812ns1-4
tCK CL = 2.0 7.5 12 7.5 12 10 12 ns 1-4
tDH DQ and DM input hold time 0.45 – 0.5 0.6 ns 1-4
tDS DQ and DM input setup time 0.45 – 0.5 0.6 ns 1-4
tIPW Control and Addr. input pulse width (each
input) 2.2 2.2 2.5 ns 1, 10
tDIPW DQ and DM input pulse width (each input) 1.75 1.75 2 ns 1-4,
11
tHZData-out high-impedence time from CK/CK −0.7 +0.7 −0.75 +0.75 −0.8 +0.8 ns 1-4, 5
tLZData-out low-impedence time from CK/CK −0.7 +0.7 −0.75 +0.75 −0.8 +0.8 ns 1-4, 5
tDQSS Write command to 1st DQS latching transition 0.75 1.25 0.75 1.25 0.75 1.25 tCK 1-4
tDQSQ DQS-DQ skew
(for DQS & associated DQ signals) +0.4 +0.5 +0.6 ns 1-4
tQHS Data hold skew factor + 0.55 – + 0.75 + 1.0 ns 1-4
tQH Data Output hold time from DQS tHP-tQHS tHP-tQHS tHP-tQHS ns 1-4
tDQSL,H DQS input low (high) pulse width (write cycle) 0.35 0.35 0.35 tCK 1-4
tDSS DQS falling edge to CK setup time (write
cycle) 0.2 0.2 0.2 tCK 1-4
tDSH DQS falling edge hold time from CK(write
cycle) 0.2 0.2 0.2 tCK 1-4
tMRD Mode register set commandcycle time 12 14 16 ns 1-4
tWPRES Write preamble setup time 0 0 0 ns 1-4, 7
tWPST Write postamble 0.40 0.60 0.40 0.60 0.40 0.60 tCK 1-4, 6
tWPRE Write preamble 0.25 0.25 0.25 tCK 1-4
tIS Address and control
input setup time fast slew rate 0.75 0.9 1.1 ns
2-4,
10,11
slow slew rate 1.0 1.1 ns
tIH Address and control
input hold time fast slew rate 0.75 0.9 1.1 ns
slow slew rate 1.0 1.1 ns
tRPRE Read preamble 0.9 0.9 1.1 0.9 1.1 tCK 1-4
tRPST Read postamble 0.40 0.40 0.60 0.40 0.60 tCK 1-4
tRAS Active to Precharge command 42 45 120,000 50 120,000 ns 1-4
tRC Active to Active/Auto-refresh command period 60 65 70 ns 1-4

HYS64/72D64000/128020GU-7/8-A
Unbuffered DDR-I SDRAM-Modules
INFINEON Technologies 14 2002-09-10 (rev.0.81)
tRFC Auto-refresh to Active/Auto-refresh
command period 72 75 80 ns 1-4
tRCD Active to Read or Write delay 18 20 20 ns 1-4
tRP Precharge command period 18 20 20 ns 1-4
tRRD Active bank A to Active bank B command 12 15 15 ns 1-4
tWR Write recovery time 15 15 15 ns 1-4
tDAL Auto precharge write recovery
+ precharge time (twr/tck)
+(trp/
tck)
(twr/tck)
+(trp/
tck) tCK 1-4,9
tWTR Internal write to read command delay 1 1 1 tCK 1-4
tXSNR Exit self-refresh to non-read command 75 75 80 ns 1-4
tXSRD Exit self-refresh to read command 200 200 200 tCK 1-4
tREFI Average Periodic
Refresh Interval 512 Mbit based 7.8 7.8 7.8 µs1-4,8
1. Input slew rate >=1V/ns for DDR266 and = 1V/ns for DDR200.
2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK,isV
REF. CK/CK slew rate are >=1.0V/ns.
3. Inputs are not recognized as valid until VREF stabilizes.
4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT.
5. tHZand tLZtransitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
6. The maximumlimit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
7. The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Zto logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
9. For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock
cycle time.
10. These parameters guarantee device timing, but they are not necessarily tested on each device
11. Fast slew rate >=1.0V/ns,slowslewrate>= 0.5 V/ns and <1V/ns for command/address and CK & CK slew rate >1.0 V/
ns, measured between VOH(ac) and VOL(ac)
Electrical Characteristics & AC Timing for DDR-I components
(for reference only)
(0 °C≤ TA≤ 70 °C; VDDQ =2.5V± 0.2V;VDD =2.5V± 0.2V)
Symbol Parameter DDR333
-6 DDR266A
-7 DDR200
-8 Unit Notes
Min Max Min Max Min Max

HYS64/72D64000/128020GU-7/8-A

Unbuffered DDR-I SDRAM-Modules

INFINEON Technologies 15 2002-09-10 (rev.0.81)

SPD Codes for PC1600 Modules “-8”

512MB

x64

1bank

-8

512MB

x72

1bank

-8

1GB

x64

2bank

-8

1GB

x72

2bank

-8

HEXHEXHEXHEX

0 Number ofSPD Bytes 128 80 80 80 80

1 Total Bytesin Serial PD 256 08 08 08 08

2 MemoryType DDR-SDRAM07070707

3 Number of Row Addresses 13 0D 0D 0D 0D

4 Number ofColumn Addresses 11 0B 0B 0B 0B

5 Number of DIMMBanks 1 /2 01 01 02 02

6 ModuleData Width x64 /x72 40 48 40 48

7 Module Data Width (cont’d) 0 00 00 00 00

8 Module Interface Levels SSTL_2.5 04 04 04 04

9 SDRAMCycle Time atCL = 2.5 8 ns 80 80 80 80

10 Access Timefrom Clock atCL =2.5 0.8 ns 80 80 80 80

11 DIMM Config non-ECC /ECC 00 02 00 02

12 Refresh Rate/Type Self-Refresh, 7.8 ms 82 82 82 82

13 SDRAM Width, Primary x8 08 08 08 08

14 Error Checking SDRAM Data Width na /x8 00 08 00 08

15 Minimum Clock Delay forBack-to-Back

Random Column Address tccd=1CLK 01010101

16 BurstLength Supported 2,4 & 8 0E 0E 0E 0E

17 Numberof SDRAM Banks 4 04 04 04 04

18 Supported CAS Latencies CAS latency =2 & 2.5 0C 0C 0C 0C

19 CSLatencies CSlatency = 0 01 01 01 01

20 WELatencies Write latency= 1 02 02 02 02

21 SDRAMDIMMModule Attributes unbuffered 20 20 20 20

22 SDRAMDevice Attributes:General – C0 C0 C0 C0

23 Min.Clock Cycle Time atCAS Latency =2 10.0 ns A0 A0 A0 A0

24 Access Time from Clockfor CL = 2 0.8 ns 80 80 80 80

25 MinimumClock Cycle Time at CL = 1.5 notsupported 00 00 00 00

26 Access Timefrom Clock atCL =1.5 notsupported 00 00 00 00

27 Minimum Row Precharge Time 20 ns 50 50 50 50

28 Minimum Row Act.to Row Act.Delay tRRD 15 ns 3C 3C 3C 3C

29 MinimumRAS to CAS Delay tRCD 20 ns 50 50 50 50

30 Minimum RASPulse Width tRAS 50 ns 32 32 32 32

31 Module BankDensity (per bank) 512MByte 80 80 80 80

32 Addr.and Command Setup Time 1.1 ns B0 B0 B0 B0

33 Addr.and Command Hold Time 1.1 ns B0 B0 B0 B0

34 Data InputSetup Time 0.6 ns 60 60 60 60

35 Data InputHold Time 0.6 ns 60 60 60 60

36-40 SupersetInformation – 00 00 00 00

41 Minimum Core Cycle TimetRC 70 ns 46 46 46 46

42 Min.AutoRefreshCmdCycleTimetRFC 80ns 50 50 50 50

43 Maximum Clock Cycle Time tck 12 ns 30 30 30 30

44 Max.DQS-DQSkew tDQSQ 0.6 ns 3C 3C 3C 3C

45 X-Factor tQHS 1.0 ns A0 A0 A0 A0

46-61 SupersetInformation - 00 00 00 00

62 SPD Revision Revision 0.0 00 00 00 00

63 Checksum for Bytes 0 - 62 – E8 FA E9 FB

64 ManufacturersJEDECID Code – C1 C1 C1 C1

65-71 Manufacturer – INFINEON INFINEON INFINEON INFINEON

72 Module Assembly Location –

73-90 Module Part Number –

91-92 Module Revision Code –

93-94 Module Manufacturing Date –

95-98 Module Serial Number –

99-127 – –

128-255 open for Customer use –

Byte# Description

HYS64/72D64000/128020GU-7/8-A

Unbuffered DDR-I SDRAM-Modules

INFINEON Technologies 16 2002-09-10 (rev.0.81)

SPD Codes for PC2100 & PC2700 Modules “-7” & “-6”

512MB

x64

1bank

-7

512MB

x72

1bank

-7

1GB

x64

2bank

-7

1GB

x72

2bank

-7

1GB

x64

2bank

-6

1GB

x72

2bank

-6

HEXHEXHEXHEXHEXHEX

0 Number ofSPD Bytes 128 80 80 80 80 80 80

1 TotalBytes in Serial PD 256 08 08 08 08 08 08

2 MemoryType DDR-SDRAM 070707070707

3 Number of Row Addresses 13 0D 0D 0D 0D 0D 0D

4 Number of Column Addresses 11 0B 0B 0B 0B 0B 0B

5 Number of DIMMBanks 1 /2 01 01 02 02 02 02

6 ModuleDataWidth x64/x72 404840484048

7 Module Data Width (cont’d) 0 00 00 00 00 00 00

8 Module Interface Levels SSTL_2.5 04 04 04 04 04 04

9 SDRAMCycle Time atCL = 2.5 7 ns 70 70 70 70 60 60

10 AccessTimefromClockatCL=2.5 0.75ns 757575757070

11 DIMMConfig non-ECC/ECC 000200020002

12 Refresh Rate/Type Self-Refresh,7.8 ms 82 82 82 82 82 82

13 SDRAM Width, Primary x8 08 08 08 08 08 08

14 ErrorChecking SDRAMData Width na /x8 00 08 00 08 00 08

15 Minimum Clock Delay for Back-to-Back

Random Column Address tccd=1CLK 010101010101

16 BurstLength Supported 2,4 &8 0E 0E 0E 0E 0E 0E

17 NumberofSDRAM Banks 4 04 04 04 04 04 04

18 SupportedCAS Latencies CAS latency= 2 & 2.5 0C 0C 0C 0C 0C 0C

19 CSLatencies CSlatency = 0 01 01 01 01 01 01

20 WELatencies Write latency= 1 02 02 02 02 02 02

21 SDRAMDIMMModule Attributes unbuffered 20 20 20 20 20 20

22 SDRAMDevice Attributes:General – C0 C0 C0 C0 C0 C0

23 Min.Clock Cycle Time at CAS Latency = 2 7.5ns 75 75 75 75 75 75

24 Access Time from Clock forCL =2 0.75 ns 75 75 75 75 70 70

25 Minimum ClockCycle TimeatCL = 1.5 not supported 00 00 00 00 00 00

26 Access Time from Clock atCL = 1.5 notsupported 00 00 00 00 00 00

27 MinimumRowPrechargeTime 20ns 505050504848

28 Minimum Row Act. to Row Act. Delay tRRD 15 ns 3C 3C 3C 3C 30 30

29 MinimumRAS to CAS Delay tRCD 20 ns 50 50 50 50 48 48

30 Minimum RAS Pulse Width tRAS 45 ns 2D 2D 2D 2D 2A 2A

31 Module BankDensity (per bank) 512MByte 80 80 80 80 80 80

32 Addr.and Command SetupTime 0.9ns 90 90 90 90 75 75

33 Addr.and Command Hold Time 0.9ns 90 90 90 90 75 75

34 Data InputSetup Time 0.5 ns 50 50 50 50 45 45

35 Data InputHold Time 0.5 ns 50 50 50 50 45 45

36-40 Superset Information – 00 00 00 00 00 00

41 Minimum Core Cycle TimetRC 65 ns 41 41 41 41 3C 3C

42 Min.Auto Refresh Cmd Cycle Time tRFC 75 ns 4B 4B 4B 4B 48 48

43 Maximum ClockCycle Timetck 12 ns 30 30 30 30 30 30

44 Max.DQS-DQSkewtDQSQ 0.5ns 32 32 32 32 2D 2D

45 X-FactortQHS 0.75ns 757575755555

46-61 Superset Information – 00 00 00 00 00 00

62 SPDRevision Revision0.0 000000000000

63 Checksumfor Bytes0 - 62 – F3 05 F4 06 42 54

64 ManufacturersJEDECID Code – C1 C1 C1 C1 C1 C1

65-71 Manufacturer – INFI-

NEON INFI-

NEON

72 Module Assembly Location –

73-90 Module Part Number –

91-92 Module Revision Code –

93-94 Module Manufacturing Date –

95-98 Module Serial Number –

99-127 – –

128-255 open for Customer use –

Byte# Description

HYS64/72D64000/128020GU-7/8-A

Unbuffered DDR-I SDRAM-Modules

INFINEON Technologies 17 2002-09-10 (rev.0.81)

Package Outlines -Raw Card A1 (One Bank Modules)

DDR-SDRAM DIMM Module Package

L-DIM-184-

144 145 184

17.80

3*) on ECC modules only

10.0

Detail of Contacts A

2.5

1.27

0.20

+0.05

+0.20

+0.15

133.35

2.3 typ.

64.77 92

2.3 typ.

31.75

pin 1

+0.13

+0.15

6.62

49.53

4.0

1.27

4.0 max.

+0.1

pin 93

2.5D

Front View

Backside View

Detail of Contacts B

3.8 typ.

2.175

6.35

1.8

0.9R

HYS64/72D64000/128x20GU-7/8-A

Unbuffered DDR-I SDRAM-Modules

INFINEON Technologies 18 2002-09-10 (rev.0.81)

Package Outlines - Raw Card B1 (Two Bank Modules)

DDR-SDRAM DIMM Module Package

two bank modules

L-DIM-184-

144 145 184

17.80

3*) on ECC modules only

10.0

Detail of Contacts A

2.5

1.27

0.20

+0.05

+0.20

+0.15

133.35

2.3 typ.

64.77 92

2.3 typ.

31.75

pin 1

+0.13

+0.15

6.62

49.53

4.0

1.27

4.0 max.

+0.1

pin 93

2.5D

Front View

Backside View

Detail of Contacts B

3.8 typ.

2.175

6.35

1.8

0.9R