MRF49XA Data Sheet ISM Band Sub-GHz RF Transceiver (c) 2009-2011 Microchip Technology Inc. Preliminary DS70590C Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. 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Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2009-2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-61341-846-8 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS70590C-page 2 Preliminary (c) 2009-2011 Microchip Technology Inc. MRF49XA ISM Band Sub-GHz RF Transceiver Features Baseband Features * Fully Integrated Sub-GHz Transceiver * Supports Proprietary Sub-GHz Wireless Protocols * 4-Wire Serial Peripheral Interface (SPI) Compatible Interface * CMOS/TTL Compatible I/Os * Clock and Reset Signals for Microcontroller * Integrated 10 MHz Oscillator Circuitry * Integrated Low Battery Voltage Detector * Supports Power-Saving modes * Operating Voltage: 2.2V-3.8V * Low-Current Consumption, Typically: - 11 mA in RX mode - 15 mA in TX mode - 0.3 A in Sleep mode * Industrial Temperature Range * 16-Pin TSSOP Package * Supports Programmable TX Frequency Deviation and RX Baseband Bandwidth (BBBW) * Analog and Digital RSSI Outputs with Dynamic Range * RX Synchronous Pattern Recognition * 16-Bit RX Data FIFO * Two 8-Bit TX Data Registers * Low-Power Duty Cycle mode * Advanced Adjacent Channel Rejection/Blocking Capability * Internal Data and Clock Recovery * Supports Data Filtering * Data Quality Indicator (DQI) RF/Analog Features * Supports ISM Band Sub-GHz Frequency Ranges (433 MHz, 868 MHz and 915 MHz) * Modulation Technique: FSK with Frequency Hopping Spread Spectrum (FHSS) Capability * Supports High Data Rates: - Digital mode 115.2 kbps, max. - Analog mode 256 kbps, max. * Differential RF Input/Output: - -110 dBm Typical Sensitivity with 0 dBm Maximum Input Level - +7 dBm Typical Transmit Output Power * High-Resolution Programmable Phase-Locked Loop (PLL) Synthesizer * Integrated Power Amplifier * Integrated Low Phase Noise Voltage Controlled Oscillator (VCO) Frequency * Synthesizer and PLL Loop Filter * Automatic Frequency Control (AFC) (c) 2009-2011 Microchip Technology Inc. Typical Applications * * * * * * * * * * * * * Home/Industrial Automation Remote Control Wireless PC Peripherals Remote Keyless Entry Vehicle Sensor Monitoring Telemetry Data Logging Systems Remote Automatic Meter Reading Security Systems for Home/Industrial Environment Automobile Immobilizers Sports and Performance Monitoring Wireless Toy Controls Medical Applications Preliminary DS70590C-page 3 MRF49XA Pin Diagram: 16-Pin TSSOP DS70590C-page 4 SDI 1 16 INT/DIO SCK 2 15 RSSIO CS 3 14 VDD SDO 4 13 RFN MRF49XA IRQ 5 12 RFP FSK/DATA/FSEL 6 11 VSS RCLKOUT/FCAP/FINT 7 10 RESET CLKOUT 8 9 Preliminary RFXTL/EXTREF (c) 2009-2011 Microchip Technology Inc. MRF49XA Table of Contents 1.0 Introduction................................................................................................................................................................................... 7 2.0 Hardware Description................................................................................................................................................................... 9 3.0 Functional Description................................................................................................................................................................ 43 4.0 Application Details...................................................................................................................................................................... 73 5.0 Electrical Characteristics ............................................................................................................................................................ 79 6.0 Packaging Information................................................................................................................................................................ 89 Appendix A: Read Sequence and Packet Structures .......................................................................................................................... 93 Appendix B: Revision History............................................................................................................................................................... 95 The Microchip Web Site ....................................................................................................................................................................... 99 Customer Change Notification Service ................................................................................................................................................ 99 Customer Support ................................................................................................................................................................................ 99 Reader Response .............................................................................................................................................................................. 100 Product Identification System ............................................................................................................................................................ 101 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. (c) 2009-2011 Microchip Technology Inc. Preliminary DS70590C-page 5 MRF49XA NOTES: DS70590C-page 6 Preliminary (c) 2009-2011 Microchip Technology Inc. MRF49XA 1.0 INTRODUCTION Microchip's MRF49XA is a fully integrated Sub-GHz RF transceiver. This low-power single chip Frequency Shift Keying (FSK) baseband transceiver supports: * * * * * * * * Zero-IF architecture Multi-channel and multi-band Synthesizer with PLL Power Amplifier (PA) Low Noise Amplifier (LNA) I/Q down converter mixers I/Q demodulator Baseband filters (BBFs) and amplifiers * * * * * * PLL and I/Q VCO with Calibration Receiver Signal Strength Indicator Data Quality Indicator AFC Baseband Power Amplifier TX and RX Buffers The receiver's Baseband Bandwidth (BBBW) can be programmed to accommodate various deviations, data rates and crystal tolerance requirements. The high-resolution PLL allows: The simplified functional block diagram of MRF49XA is shown in Figure 1-1. The MRF49XA is an ideal choice for low-cost, high-volume, low data rate (<256 kbps), two-way and short range wireless applications. This transceiver can be used in the unlicensed 433 MHz, 868 MHz and 915 MHz frequency bands, and for applications looking for FCC, IC or ETSI certification in the ISM band. The MRF49XA has a low phase noise and provides an excellent adjacent channel interference, Bit Error Rate (BER) and larger communication coverage along with higher output power. The MRF49XA device's AFC feature allows for the use of a low-accuracy, low-cost crystal. In order to minimize the total system cost, a communication link in most of the applications can be created using a low-cost, generic 10 MHz crystal, a bypass filter and an affordable microcontroller. The MRF49XA provides a clock signal for the microcontroller and avoids the need for a second crystal on the circuit board. The transceiver can be interfaced with many popular Microchip PIC(R) microcontrollers through a 4-wire SPI, interrupt (IRO) and Reset. The interface between the microcontroller and MRF49XA is shown in Figure 1-2. (c) 2009-2011 Microchip Technology Inc. The MRF49XA supports the following digital data processing features: * The usage of multiple channels in any of the bands * The rapid settling time allows for faster frequency hopping, bypassing multipath fading and interference to achieve robust wireless links The transceiver is integrated with different Sleep modes and an internal wake-up timer to reduce the overall current consumption, and to extend the battery life. The device's small size with low-power consumption makes it ideal for various short range radio applications. Preliminary DS70590C-page 7 MRF49XA FIGURE 1-1: FUNCTIONAL NODE BLOCK DIAGRAM Antenna MRF49XA RF Block Matching Circuitry RFP PA/LNA and PLL/CLK Block RFN Baseband Amplifier/ Filter/ Limiter SPI Signals Data Processing Unit MCU Interface Other Handshaking Signals Power Management Memory 10 MHz FIGURE 1-2: MICROCONTROLLER TO MRF49XA INTERFACE PIC(R) MCU MRF49XA I/O/SS IRO __ CS SDO SDI SDI SDO SCK SCK INT I/O INT/DIO* I/O RESET* I/O FSK/DATA/FSEL* CLKOUT* OSC1 I/O RCLKOUT/FCAP/FINT* * Implies optional signals. DS70590C-page 8 Preliminary (c) 2009-2011 Microchip Technology Inc. MRF49XA 2.0 HARDWARE DESCRIPTION The MRF49XA is an integrated, single chip ISM Band Sub-GHz Transceiver. A simplified architectural block diagram of the MRF49XA is shown in Figure 2-1. The frequency synthesizer is clocked by an external 10 MHz crystal and generates the 433, 868 and 915 MHz radio frequency. The receiver with a Zero-IF architecture consists of the following components: * * * * * The quality of the data is checked or validated using the RSSI and DQI blocks built into the transceiver. Data is buffered in transmitter registers and receiver FIFOs. The AFC feature allows the use of a low-accuracy and low-cost crystal. The CLKOUT is used to clock the external controller. The transceiver is controlled through a 4-wire SPI, interrupt (INT/DIO and IRO), FSK/DATA/FSEL, RCLKOUT/FCAP/FINT and RESET pins. See Table 2-1 for pin details. The MRF49XA supports the following feature blocks: LNA Down Conversion Mixers Channel Filters Baseband Limiting Amplifiers Receiver Signal Strength Indicator The transmitter with a direct conversion architecture has a typical output power of +7 dBm. An internal transmit/receive switch combines the transmitter and receiver circuits into differential RFP and RFN pins. These pins are connected to the impedance matching circuitry (Balun) and to the external antenna connected to the device. * * * * * * Clock Generation Data Filtering and Amplification Data Pattern Recognition and Timing Data Processing and Storage Independent Transmit and Receiver FIFO Buffers Registers These features reduce the processing load, and hence, allows the use of low-cost 8-bit microcontrollers for data processing. The device operates in the low-voltage range of 2.2V- 3.8V, and in Sleep mode, it operates at a very low-current state, typically 0.3 A. (c) 2009-2011 Microchip Technology Inc. Preliminary DS70590C-page 9 MRF49XA ARCHITECTURAL BLOCK DIAGRAM MIX I Cal AMP Ckt LNA RFN 13 RFP 12 7 Self Calibration MIX Q Data Filtering and Clock Recovery Unit I/Q DEMOD CLK DATA 6 Cal AMP Ckt FIFO PA Preliminary PLL and I/Q VCO with Calibration PA/LNA and PLL/CLK Block CLK OSC (c) 2009-2011 Microchip Technology Inc. CLKOUT Comparator DQI AFC Baseband Amplifier/Filter/Limiter Block WUTM with calibration Data Processing Block LBDB Power Supply Block Microcontroller Interface Block Low-Power Block Clock Block 8 RSSI 9 RFXTL/ EXTREF 15 RSSIO 1 SDI 2 3 4 5 SCK __ CS SDO IRO 10 16 RESET INT/DIO RCLKOUT/ FCAP/FINT 11 VSS 14 VDD FSK/DATA/ ____ FSEL MRF49XA DS70590C-page 10 FIGURE 2-1: MRF49XA TABLE 2-1: Pin PIN DESCRIPTION Symbol Type 1 SDI Digital Input Serial data input interface to MRF49XA (SPI input signal). 2 SCK Digital Input Serial clock interface (SPI clock). 3 CS Digital Input Serial interface chip select (SPI chip/device select). 4 SDO Digital Output Serial data output interface from MRF49XA (SPI output signal). 5 IRO Digital Output Interrupt Request Output: Receiver generates an active-low interrupt request for the microcontroller on the following events: * The TXBREG (see Table 2-4) is ready to receive the next byte. * The RXFIFOREG (see Table 2-4) has received the preprogrammed amount of bits. * RXFIFOREG overflow/TXBREG underrun. * Negative pulse on interrupt input pin (INT). * Wake-up timer time-out. * Supply voltage below the preprogrammed value is detected. * Power-on Reset (POR). 6 FSK/DATA/FSEL Digital Input/Output Frequency Shift Keying: Transmit FSK data input (with internal pull-up resistor of 133 k). Data: When configured as DATA, this pin functions as follows: * Data In: Manually modulates the data from the external host microcontroller when the internal TXBREG is disabled. If the TXBREG is enabled, this pin can be tied "high" or left unconnected. When reading the internal RXFIFOREG, this pin must be pulled "low". * Data Out: Receives data in conjunction with RCLKOUT when the internal FIFO is not used. FIFO Select: Selects the FIFO and the first bit appears on the next clock when reading the RXFIFOREG. The FSEL pin has an internal pull-up resistor. This pin must be "high" when the TX register is enabled. In order to achieve minimum current consumption, keep this pin "high" in Sleep mode. 7 RCLKOUT/FCAP/ FINT Digital Input/Output Recovery Clock Output: Provides the clock recovered from the incoming data if: * FTYPE bit of BBFCREG (see Table 2-10) is configured as digital filter and * FIFO is disabled by configuring FIFOEN bit of GENCREG (see Table 2-10) Filter Capacitor: This pin is a raw baseband data if the FTYPE bit of BBFCREG is configured as a configuration filter. The pin can be used by the host microcontroller for data recovery. FIFO Interrupt: When the internal FIFO, FIFOEN bit of GENCREG is enabled, this pin acts as a FIFO full interrupt, indicating that the FIFO has been filled to its preprogrammed limit (see FFBC<3:0> bits in FIFORSTREG in Table 2-10). 8 CLKOUT Digital Output Clock Output: The transceiver's clock output can be used by the host microcontroller as a clock source. Refer Register 2 for more details. (c) 2009-2011 Microchip Technology Inc. Description Preliminary DS70590C-page 11 MRF49XA TABLE 2-1: PIN DESCRIPTION (CONTINUED) Pin Symbol Type Description 9 RFXTL/EXTREF Analog Input RF Crystal: This pin is connected to a 10 MHz series crystal or to an external oscillator reference. The crystal is used as a reference for the PLL which generates the local oscillator frequency. It is possible to "pull" the crystal to the accurate frequency by changing the load capacitor value. External Reference Input: An external reference input, such as an oscillator, can be connected as a reference source. Connect the oscillator through a 0.01 F capacitor. 10 RESET Digital Input/Output Active-low hardware pin. This pin has an open-drain Reset output with internal pull-up and input buffer. Refer to Section 3.1, Reset for more details. 11 Vss Ground 12 RFP RF Input/Output 13 RFN RF Input/Output 14 VDD Power 15 RSSIO Analog Input/Output Received Signal Strength Indicator Output: The analog RSSI output is used to determine the signal strength. The response and settling time depends on the external filter capacitor. Typically, a 4-10 nF capacitor provides optimum response time for most applications. 16 INT/DIO Digital Input/Output DS70590C-page 12 Ground reference. Differential RF input/output (+). Differential RF input/output (-). RF power supply. Bypass with a capacitor close to the pin. See Section 2.1, Power and Ground Pins for more details. Interrupt: This pin can be configured as an active-low external interrupt to the device. If a logic `0' is applied to this pin, it causes the IRO pin to toggle, signaling an interrupt to the external microcontroller. The source of interrupt can be determined by reading the first four bits of STSREG (see Table 2-4). This pin can be used to wake-up the device from Sleep. Data Indicator Output: This pin can be configured to indicate valid data based on the actual internal settings. Preliminary (c) 2009-2011 Microchip Technology Inc. MRF49XA 2.1 Power and Ground Pins The power supply bypassing is very essential for better handling of signal surges and noise in the power line. The large value decoupling capacitors should be placed at the PCB power input. The smaller value decoupling capacitors should be placed at every power point of the device and at bias points for the RF port. Poor bypassing leads to conducted interference which can cause noise and spurious signals to couple into the RF sections, thereby significantly reducing the performance. The VDD pin requires two bypass capacitors to ensure sufficient bypass and decoupling. However, based on the selected carrier frequency, the bypass capacitor values vary. The recommended bypass capacitor values are listed in Table 2-2 and the type of capacitor to be used is listed in Table 2-3. The bypass capacitors are connected to pin 14, as shown in Figure 4-1. The trace length (VDD pin to bypass capacitors) should be made as short as possible. TABLE 2-2: RECOMMENDED BYPASS CAPACITORS VALUE Band (MHz) C1(F) C2 (nF) C3 (pF) 433 2.2 10 220 868 2.2 10 47 915 2.2 10 33 TABLE 2-3: Property C2 Power-on Reset Power Glitch Reset Software Reset RESET Pin Software Reset can be issued by sending the appropriate control command to the device. The result of the command is similar to POR, but the duration of the Reset event is much less, typically 0.25 ms. The Software Reset works only when the Sensitive Reset mode is selected. See Section 3.1, Reset for details on Reset; for connection details, see Figure 4-1. 2.3 Power Amplifier The PA has an open-collector differential output and can directly drive different PCB antennas, like loop or dipole, with a programmable output power level during signal transmission. However, certain types of antennas, like monopole, need an additional matching circuitry. A built-in, automatic antenna tuning circuit is used to avoid the manual tuning and trimming procedures during production process; the so called "hand effect". Low Noise Amplifier The LNA has approximately 250 of differential input impedance which functions well with the proposed antenna (PCB/Monopole) during signal transmission. The LNA, when connected to the 50 device, needs an external matching circuit (Balun) for correct matching and to minimize the noise figure of the receiver. C3 SMD Size A 0603 0603 Dielectric Tantalum Ceramic Ceramic 2.2 * * * * 2.4 RECOMMENDED BYPASS CAPACITORS C1 The device enters the Reset mode if any of the following events take place: The LNA gain can be selected in four steps for different gain factors (between 0 dB and -20 dB relative to the highest gain) based on the required RF signal strength. This gain selection feature is useful in a noisy environment. RESET Pin An external hardware Reset of MRF49XA can be performed by asserting the RESET (pin 10) to low. After releasing the pin, it takes slightly more than 0.25 ms for the transceiver to be released from the Reset. The pin is driven with an open-drain output, and hence, it is pulled down while the device is in POR. The RESET pin has an internal, weak, on-chip, pull-up resistor. The device will not accept commands during the Reset period. (c) 2009-2011 Microchip Technology Inc. Preliminary DS70590C-page 13 MRF49XA 2.5 RFXTL/EXTREF and CLKOUT Pins The MRF49XA has an internal, integrated crystal oscillator circuit, and therefore, a single RFXTL/EXTREF pin is used as a crystal oscillator. The crystal oscillator circuit, with internal loading capacitors, provides a 10 MHz reference signal for the PLL. The PLL, in turn, generates the local oscillator frequency. It is possible to "pull" the crystal to the accurate frequency by changing the load capacitor value. This reduces the external component count and simplifies the design. The crystal load capacitor is programmable from 8.5 pF-16 pF in 0.5 pF steps. Thus, the crystal oscillator circuit can accept a wide range of crystals from different manufacturers with different load capacitance requirements. The ability to vary the load capacitance also helps in fine tuning the final carrier frequency as the crystal itself is the PLL reference for the carrier. An external reference input, such as an oscillator, can be connected as a reference source. The oscillator can be connected through a 0.01 F capacitor. Choosing better crystal results in a lesser TX to RX frequency offset and smaller deviation in BBBW. Hence, the recommended crystal accuracy should be 40 ppm. Deviation and BBBW are discussed in detail in Section 2.8, Baseband/Data Filters. The guidelines for selecting the appropriate crystal are explained in Section 3.6, Crystal Selection Guidelines. The transceiver can provide a clock signal through the Clock Output (CLKOUT) pin to the microcontroller for accurate timing, and thus, eliminating the need for a second crystal. This also results in reducing the component count. 2.6 Phase-Locked Loop The PLL circuitry determines the operating frequency of the device. This programmable PLL synthesizer requires only a single 10 MHz crystal reference source. The PLL maintains accuracy using the on-chip crystal controlled reference oscillator and provides maximum flexibility in performance to the designers. It is possible to change the crystal to the accurate frequency by changing the load capacitor value. The RF stability can be controlled by selecting a crystal with specifications which satisfy the application and by providing the functions required to generate the carriers, and by tuning each of the bands. For more details, see Section 3.6, Crystal Selection Guidelines. The PLL's high resolution allows the use of multiple channels in any of the bands. The on-chip PLL is able to perform manual and automatic calibration to compensate for the changes in temperature or operating voltage. DS70590C-page 14 2.7 Automatic Frequency Control The PLL in MRF49XA is capable of performing automatic fine adjustment for the carrier frequency by using an integrated AFC feature. The receiver uses the AFC feature to minimize the frequency offset between the TX/RX signals in discrete steps, which gives the advantage of: * Narrower receiver bandwidth for increased sensitivity can be achieved * Higher data rates can be achieved * Usability of any locally available, low-accuracy and inexpensive crystals can be used The MRF49XA can be programmed to automatically control the frequency or can be manually activated by a strobe signal. 2.8 Baseband/Data Filters The BBFs are user-programmable. The receiver bandwidth can be set by programming the bandwidth of the BBFs. The receiver, when programmed, is set up according to the characteristics of the signal to be received. The baseband receiver has several programming options to optimize the communication for a variety of applications. The programmable functions are as follows: * * * * * Baseband Analog Filter Baseband Digital Filter Receive Bandwidth Receive Data Rate Clock Recovery The output data filtering can be performed using either an external capacitor or a digital filter based on the user application. The RCLKOUT/FCAP/FINT pin in MRF49XA provides the raw baseband data if configured as a configuration filter. It can be used by the host microcontroller to perform the data recovery. 2.9 Clock Recovery Circuit The Clock Recovery Circuit (CLKRC) is used to render a synchronized clock source to recover the data using an external microcontroller. The CLKRC works by sampling the preamble on the received data. The preamble contains a sequence of 1 and 0 for the CLKRC to properly extract the data timing. In Slow mode, the CLKRC requires more sampling (12-16 bits), and hence, has a longer settling time before locking. In Fast mode, it uses less samples (6-8 bits) before locking, and thereby, the settling time is short which makes timing accuracy less critical. The RCLKOUT/FCAP/FINT pin provides the clock recovered from the incoming data if the baseband filter is configured as a digital filter. Preliminary (c) 2009-2011 Microchip Technology Inc. MRF49XA 2.10 2.10.1 Data Validity Blocks 2.10.2 RECEIVE SIGNAL STRENGTH INDICATOR The MRF49XA provides the RSSI signal to the host microcontroller, and hence, supports the monitoring of analog and digital signal strengths. A digital RSSI output is provided to monitor the input signal level through an internal STATUS register. The digital RSSI goes high, if the received signal strength exceeds a given preprogrammed RSSI threshold level. The digital RSSI can be monitored by reading the STSREG. Alternatively, an analog RSSI signal is also available at pin 15 (RSSIO) to determine the signal strength. The analog RSSI settling time depends on the external filter capacitor. Typically, a 4-10 nF capacitor provides optimum response time for most of the applications. See Section 4.0, Application Details and Section 5.0, Electrical Characteristics for details on filter capacitors for analog RSSI. The typical relationship between analog RSSI voltage and RF input power is graphically represented in Figure 2-2. DATA QUALITY INDICATOR The Data Quality Indicator (DQI) is a special function which indicates the quality of the received signal and the link. The unfiltered received data is sampled and the number of spikes are counted in the received data for a specified time. If the input signals are of high value, it indicates the operating FSK transmitter of the high output signal within the baseband filter bandwidth from the local oscillator. 2.10.3 DATA INDICATOR OUTPUT The Data Indicator Output (DIO) is an extension of DQI. The DIO pin can be configured to indicate valid data based on the actual internal settings. When an incoming signal is detected, the DIO uses the DQI clock recovery lock and digital RSSI signals to determine the validity of the incoming signal. The DIO searches for the valid data transitions at an expected data rate. The desired data rate and the acceptance criteria for valid data are user-programmable through the SPI port. The DIO signal is valid when using the internal receive FIFO or an external pin to capture baseband data. The DIO has three modes of operation: Slow, Medium and Fast. Each mode is dependent on the type of signals it uses to determine the valid data and the number of incoming preamble bits present at the beginning of the packet. The DIO can be multiplexed with the INT pin for external usage. ANALOG RSSI VOLTAGE VS. RF INPUT POWER Analog RSSI Voltage (mV) FIGURE 2-2: 1150 450 -100 -65 Input Power (dBm) (c) 2009-2011 Microchip Technology Inc. Preliminary DS70590C-page 15 MRF49XA 2.11 2.11.1 Power-Saving Blocks 2.12 LOW BATTERY VOLTAGE DETECTOR The integrated low-battery voltage detector circuit monitors the supply voltage against a preprogrammed value and generates an interrupt on the IRO pin if it falls below the programmed threshold level. The detector circuit has a built-in 50 mV hysteresis. 2.11.2 WAKE-UP TIMER The current consumption of the programmable wake-up timer is very low, typically 1.5 A. It is programmable from 1 ms to several days with an accuracy level of 10%. The calibration of the wake-up timer takes place at every start-up and every 30s thereafter, and is referenced with the crystal oscillator. The calibration is performed even in Sleep mode. The calibration process for the wake-up timer takes around 500 s, and for proper calibration, the crystal oscillator must be running before the wake-up timer is enabled. If any wake-up event occurs, including the wake-up timer, the wake-up logic generates an interrupt signal on the IRO pin which can be used to wake-up the microcontroller and this reduces the period that the microcontroller needs to be active. If the oscillator circuit is disabled, the calibration circuit turns it on for a brief period to perform the calibration in order to maintain accurate timing before returning to Sleep. 2.11.3 LOW DUTY CYCLE MODE The MRF49XA can be made to enter into a Low Duty Cycle mode operation to decrease the average power consumption in Receive mode. The Low Duty Cycle mode is normally used in conjunction with the wake-up timer for its operation. The DCSREG may be configured so that when the wake-up timer brings the device out of Sleep mode, the receiver is turned on for a short time to sample for a signal. Then, the device returns to Sleep and this process repeats. DS70590C-page 16 INT, IRO Pins and Interrupts The Interrupt pin (INT) can be configured as an active-low external interrupt to MRF49XA which is provided from the host microcontroller. The device generates an interrupt request for the host microcontroller by pulling the IRO pin low if the following events occur: * TX register is ready to receive the next byte * RX FIFO has received the preprogrammed amount of bits * FIFO overflow/TX register underrun (TXUROW overflow in Receive mode and underrun in Transmit mode) * Negative pulse on interrupt input pin, INT * Wake-up timer time-out * Supply voltage below the preprogrammed value is detected * Power-on Reset The Status bits should be read out to identify the source of interrupt. The interrupts are cleared by reading the STATUS register. See Section 3.9, Interrupts for functional description of interrupts. 2.13 Transmit Register The Transmit register in MRF49XA is configured as two, 8-bit shift registers connected in series to form a single 16-bit shift register. When the transmitter is enabled, it starts sending out data from the first register with respect to the set bit rate. After power-up and with the Transmit registers enabled, the transmitter preloads the TX latch with 0xAAAA. This can be used to generate a preamble before sending actual data. In hardware, the FSK/DATA/FSEL has two functions: * As Frequency Shift Keying pin, it basically takes care of transmitting the FSK data input. The pin has an internal pull-up resistor of 133 k. This pin must be "high" when the TX register is enabled to take care of the transmission. * As DATA (Data Out), this pin receives the data in conjunction with RCLKOUT when the internal FIFO is not used. When reading the internal RXFIFOREG, this pin must be pulled "low". Preliminary (c) 2009-2011 Microchip Technology Inc. MRF49XA 2.14 Receive FIFO The received data in MRF49XA is filled into a 16-bit First In First Out (FIFO) register. The FIFO is configured to generate an interrupt after receiving a defined number of bits. When the internal FIFO is enabled, the FIFO interrupt pin (RCLKOUT/FCAP/FINT) acts as a FIFO full interrupt, indicating that the FIFO has been filled to its preprogrammed limit. The receiver starts filling FIFO with data when it identifies the synchronous pattern through the synchronous pattern recognition circuit. During this process, the FINTDIO bit changes its state. The FIFO interrupt level is programmable from 1 to 16 bits. It is recommended to set the threshold to at least half the length of the register (8 bits) to ensure that the external host microcontroller has time to set up. The synchronous pattern recognition circuit prevents the FIFO from being filled up with noise, and hence, avoids overloading the external host microcontroller. Note: The synchronous word is not accessible in the RX FIFO. The SYNBREG provides this information to the host microcontroller. The FIFO read clock (SCK) must be < fXTAL/4 or < 2.5 MHz for 10 MHz on RFXTAL. The FSK/DATA/FSEL as the FIFO select pin, selects the FIFO and the first bit appears on the next clock when reading the RXFIFOREG. In hardware, the FSK/DATA/FSEL pin is configured as DATA (Data In) and with internal TXBREG disabled; this manually modulates the data from the external host microcontroller. If the TXBREG is enabled, this pin can be tied "high" or can be left unconnected. The internal synchronous pattern and the pattern length are user-programmable. If the Chip Select (CS) pin is low, the data bits on the SDI pin are shifted into the device on the rising edge of the clock on the SCK pin.The serial interface is initialized if the CS signal is high. 2.15 Table 5-8. Data is received by the transceiver through the SDI pin and is clocked on the rising edge of SCK. The timing diagram is shown in Figure 5-1. MRF49XA sends out the data through the SDO pin and is clocked out on the falling edge of SCK. The Most Significant bit (MSb) is sent first (e.g., bit 15 for a 16-bit command) in any data. The POR circuit sets default values in all control and command registers. Note: Special care must be taken when the microcontroller's built-in hardware serial port is used. If the port cannot be switched to a 16-bit mode, then a separate I/O line should be used to control the CS pin to ensure a low level during the complete duration of the communication (command) or a software serial control interface should be implemented. The SDO pin defaults to a low state when the CS pin is high (the MRF49XA is not selected). This pin has a tri-state buffer and uses a bus hold logic. For the SPI interface, see Figure 4-1. The following parameters can be programmed and set through SPI: * * * * * * Frequency band Center frequency of the synthesizer Division ratio for the microcontroller clock Wake-up timer period Bandwidth of the baseband signal path Low supply voltage detector threshold Any of these auxiliary functions can be disabled when not required. After power-on, all parameters are set to default values. The programmed values are retained during Sleep mode. The interface supports the read out of a status register which provides detailed information about the status of the transceiver and the received data. Note: Serial Peripheral Interface The MRF49XA communicates with the host microcontroller through a 4-wire SPI port as a slave device. An SPI compatible serial interface lets the user select, command and monitor the status of the MRF49XA through the host microcontroller. All registers consist of a command code, followed by a varying number of parameter or data bits. As the device uses word writes, the CS pin should be pulled low for 16 bits. Data bits on the SDI pin are shifted into the device upon the rising edge of the clock on the SCK pin whenever the CS pin is low. To test the SPI interface lines, set the LBD (Low Battery Detector) threshold below the actual VDD and the device must generate an interrupt. The maximum clock frequency for the SPI bus is 20 MHz. The MRF49XA supports SPI mode 0,0 which requires the SCK to remain Idle in a low state. The CS pin must be held low to enable communication between the host microcontroller and the MRF49XA. The device's timing specification details are given in (c) 2009-2011 Microchip Technology Inc. Preliminary DS70590C-page 17 MRF49XA 2.16 Memory Organization The memory in MRF49XA is implemented as static RAM and is accessible through the SPI port. Each memory location functionally addresses a register, control, status or data/FIFO fields, as shown in Table 2-10. The command/control registers provide control, status and device address for transceiver operations. The FIFOs serve as temporary buffers for data transmission and reception. code, followed by control, data, status or parameter bits. The MSb is sent first in all of the commands (e.g., bit 15 for a 16-bit command). The POR circuit sets the default values in all control and command registers. In general, MRF49XA registers are read only. Hence the chip status can only be read by the Status Read Register. During write, only appropriate byte is written to the desired register. It is not desired to read/write all registers and there is no way to read back the register. The commands to the device are sent serially. All 17 commands basically address the 17 registers affiliated to it. The registers consist of a command TABLE 2-4: CONTROL (COMMAND) REGISTER DESCRIPTION SI. No. Register Name 1 STSREG 2 Register Description Related Control Functions Status Read Register Receive register/FIFO, transmit register, interrupt, frequency control and signal strength, POR, wake-up timer, low battery detect, data quality, clock recovery GENCREG General Configuration Register Frequency band select, enables TX and RX registers, crystal load capacitor bank value 3 AFCCREG AFC Configuration Register AFC locking range, mode, accuracy and enable 4 TXCREG Transmit Configuration Register Modulation polarity, modulation bandwidth, transmit power and deviation 5 TXBREG Transmit Byte Register Transmit data byte 6 CFSREG Center Frequency Value Set Register Transmit or receive frequency 7 RXCREG Receive Control Register Function of pin 16, DIO mode, RX BBBW, LNA gain, digital RSSI threshold 8 BBFCREG Baseband Filter Configuration Register Clock Recovery mode, data indicator parameter value and filter type 9 RXFIFOREG 10 FIFORSTREG 11 SYNBREG Receiver FIFO Read Register Receive data byte FIFO and Reset mode Configuration Register FIFO interrupt level, FIFO start control and FIFO enable, POR Sensitivity mode, synchronous character length Synchronous Byte Configuration Register Synchronous character pattern 12 DRSREG Data Rate Value Set Register Data rate prescalar set 13 PMCREG Power Management Configuration Register Enables receive and transmit chain, baseband circuit, synthesizer circuit, oscillator, wake-up timer, low battery detect and clock out 14 WTSREG Wake-up Timer Value Set Register Wake-up timer values for time interval 15 DCSREG Duty Cycle Value Set Register Duty Cycle mode and value 16 BCSREG Battery Threshold Detect and Clock Output Value Set Register Low battery detect threshold values and clock output frequency 17 PLLCREG PLL Configuration Register Clock out buffer speed, PLL bandwidth, dithering and delay DS70590C-page 18 Preliminary (c) 2009-2011 Microchip Technology Inc. MRF49XA 2.17 Control (Command) Register Details STSREG: STATUS READ REGISTER (POR: 0x0000)(1) REGISTER 2-1: R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 TXRXFIFO POR TXOWRXOF WUTINT LCEXINT LBTD FIFOEM ATRSSI bit 15 bit 8 R-0 R-0 R-0 R-0 DQDO CLKRL AFCCT OFFSV R-0 R-0 R-0 R-0 OFFSB<3:0> bit 7 bit 0 Legend: r = reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15 TXRXFIFO: Transmit Register or Receive FIFO bit Transmit mode: Transmit Register Ready bit(2) Indicates whether the transmit register is ready to receive the next byte for transmission. 1 = Ready(5) 0 = Not ready Receive mode: Receive FIFO Fill (Interrupt) bit(2,3) Indicates whether the RX FIFO has reached the preprogrammed limit. 1 = Reached the preprogrammed limit(5) 0 = Programming limit has not been reached bit 14 POR: Power-on Reset bit 1 = POR has occurred(5) 0 = POR has not occured bit 13 TXOWRXOF: Transmit Overwrite Receive Overflow bit Transmit mode: Transmit Register Underrun or Overwrite bit 1 = Underrun or overwrite(5) 0 = Operating normally Receive mode: Receive FIFO Overflow bit 1 = FIFO overflow(5) 0 = Operating normally bit 12 WUTINT: Wake-up Timer (Interrupt) Overflow bit 1 = Timer overflow has occurred(5) 0 = Operating normally bit 11 LCEXINT: Logic Change on External Interrupt bit Indicates a high-to-low logic level change on external interrupt pin (INT/DIO)(5). 1 = High-to-low transition has occurred 0 = High-to-low transition has not occured Note 1: 2: 3: 4: 5: All register commands begin with logic `1' and only the STATUS register read command begins with logic `0'. This bit is multiplexed for Transmit or Receive mode. See the FFBC bits (FIFORSTREG<3:0>) in Register 2-10. To get accurate values, the AFC should be disabled during the read by clearing the FOFEN bit (AFCCREG<0>). The AFC offset value (OFFSB bits in the status word) is represented as a two's complement number. The actual frequency offset can be calculated as the AFC offset value multiplied by the current PLL frequency step from CFSREG (FREQB<11:0>). This bit is cleared after STSREG is read. (c) 2009-2011 Microchip Technology Inc. Preliminary DS70590C-page 19 MRF49XA REGISTER 2-1: STSREG: STATUS READ REGISTER (POR: 0x0000)(1) (CONTINUED) bit 10 LBTD: Low Battery Threshold Detect bit Indicates whether the battery or supply voltage is below the preprogrammed threshold limit. 1 = Supply voltage is below threshold 0 = Normal supply voltage feed bit 9 FIFOEM: FIFO Empty bit Indicates whether the receive FIFO is empty or filled. 1 = FIFO is empty 0 = FIFO is filled bit 8 ATRSSI: Antenna Tuning and Received Signal Strength Indicator bit Transmit mode: The bit indicates that the antenna tuning circuit has detected a strong RF signal. 1 = Strong RF signal present 0 = Weak or absence of RF signal Receive mode: The bit indicates that the incoming RF signal is above the preprogrammed digital RSSI limit. 1 = RF signal is above the threshold value set 0 = RF signal is less than the threshold value set bit 7 DQDO: Data Quality Detect/Indicate Output bit Indicates good data quality output. 1 = Quality data is detected 0 = Quality data is unavailable bit 6 CLKRL: Clock Recovery Lock bit Indicates clock recovery is locked. 1 = Clock recovery locked 0 = Clock recovery unlocked bit 5 AFCCT: Automatic Frequency Control Cycle Toggle bit For each AFC cycle run, this bit toggles between logic `1' and logic `0'. 1 = AFC cycle has occurred 0 = No AFC in this cycle bit 4 OFFSV: Offset Sign Value bit Indicates the measured difference or frequency offset of any AFC cycle (sign of the offset value). 1 = Higher than the chip frequency 0 = Lower than the chip frequency bit 3-0 OFFSB<3:0>: Offset bits The offset value to be added to the frequency control parameter (internal PLL)(4). 1 = Result is negative 0 = Result is positive Note 1: 2: 3: 4: 5: Note: All register commands begin with logic `1' and only the STATUS register read command begins with logic `0'. This bit is multiplexed for Transmit or Receive mode. See the FFBC bits (FIFORSTREG<3:0>) in Register 2-10. To get accurate values, the AFC should be disabled during the read by clearing the FOFEN bit (AFCCREG<0>). The AFC offset value (OFFSB bits in the status word) is represented as a two's complement number. The actual frequency offset can be calculated as the AFC offset value multiplied by the current PLL frequency step from CFSREG (FREQB<11:0>). This bit is cleared after STSREG is read. See Appendix A: "Read Sequence and Packet Structures" for the STSREG read sequence. DS70590C-page 20 Preliminary (c) 2009-2011 Microchip Technology Inc. MRF49XA REGISTER 2-2: GENCREG: GENERAL CONFIGURATION REGISTER (POR: 0x8008) W-1 W-0 W-0 W-0 W-0 W-0 W-0 W-0 CCB<15:8> bit 15 bit 8 W-0 W-0 TXDEN FIFOEN W-0 W-0 W-1 W-0 FBS<1:0> W-0 W-0 LCS<3:0> bit 7 bit 0 Legend: r = reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-8 CCB<15:8>: Command Code bits The command code bits (10000000b) are serially sent to the microcontroller to identify the bits to be written in the GENCREG. bit 7 TXDEN: TX Data Register Enable bit 1 = Internal TX Data register enabled(1) 0 = Internal TX Data register disabled; no transmit bit 6 FIFOEN: FIFO Enable bit 1 = Internal data FIFO enabled; the FIFO is used to store data during receive(2) 0 = FIFO disabled; FSK/DATA/FSEL and RCLKOUT/FCAP/FINT are used to receive data bit 5-4 FBS<1:0>: Frequency Band Select bits These bits set the frequency band to be used in Sub-GHz range. 11 = 915 MHz 10 = 868 MHz 01 = 433 MHz 00 = Reserved bit 3-0 LCS<3:0>: Load Capacitance Select bits These bits set and vary the internal load capacitance for the crystal reference. 1111 = 16.0 pF 1110 = 15.5 pF 1101 = 15.0 pF 1100 = 14.5 pF 1011 = 14.0 pF 1010 = 13.5 pF 1001 = 13.0 pF 1000 = 12.5 pF 0111 = 12.0 pF 0110 = 11.5 pF 0101 = 11.0 pF 0100 = 10.5 pF 0011 = 10.0 pF 0010 = 9.5 pF 0001 = 9.0 pF 0000 = 8.5 pF Note 1: 2: If the internal TX data register is used, the DATA/FSK/FSEL pin must be pulled "high". If the data FIFO is used, the DATA/FSK/FSEL pin must be pulled "low". (c) 2009-2011 Microchip Technology Inc. Preliminary DS70590C-page 21 MRF49XA REGISTER 2-3: W-1 AFCCREG: AUTOMATIC FREQUENCY CONTROL CONFIGURATION REGISTER (POR: 0xC4F7) W-1 W-0 W-0 W-0 W-1 W-0 W-0 CCB<15:8> bit 15 bit 8 W-1 W-1 AUTOMS<1:0> W-1 W-1 ARFO<1:0> W-0 W-1 W-1 W-1 MFCS HAM FOREN FOFEN bit 7 bit 0 Legend: r = reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-8 CCB<15:8>: Command Code bits The command code bits (11000100b) are serially sent to the microcontroller to identify the bits to be written in the AFCCREG. bit 7-6 AUTOMS<1:0>: Automatic mode Selection bits (for AFC) These bits select the operation type (automatic/manual) for performing AFC based on the status of the MFCS bit. 11 = Keeps offset independent for the state of the DIO signal 10 = Keeps offset only while receiving (DIO = High) 01 = Runs and measures only once after each power-up cycle 00 = Auto mode off (controlled by microcontroller) bit 5-4 ARFO<1:0>: Allowable Range for Frequency Offset bits These bits select the offset range allowable between transmitter and receiver frequencies. 11 = +3 FRES to -4 FRES(1) 10 = +7 FRES to -8 FRES 01 = +15 FRES to -16 FRES 00 = No restriction bit 3 MFCS: Manual Frequency Control Strobe bit This bit is the strobe signal which initiates the manual frequency control sample to calculate the offset error. 1 = A sample of a received signal is compared with a receiver Local Oscillator (LO) signal and an offset error is calculated. If bit 1 is enabled, the value is stored in the Offset register of the AFC block.(2) 0 = Ready for the next sample bit 2 HAM: High-Accuracy (Fine) mode bit(3) 1 = Switches the Frequency Control mode to High-Accuracy mode 0 = Frequency Control mode works in regular mode bit 1 FOREN: Frequency Offset Register Enable bit 1 = Enables the offset value calculated by the offset sample. The offset value is added to the frequency control word of the PLL which tunes the desired carrier frequency. 0 = Denies the addition of the offset value to the frequency control word of the PLL bit 0 FOFEN: Frequency Offset Enable bit 1 = Enables the frequency offset calculation using the AFC circuit 0 = Disables the frequency offset calculation using the AFC circuit Note 1: 2: 3: The FRES is the frequency tuning resolution for each band. The FRES for each band is as follows: 433 MHz = 2.5 kHz 868 MHz = 5 kHz 915 MHz = 7.5 kHz The offset error value is stored in the Offset register (FOREN bit should be enabled) in the AFC block and is added to the frequency control word of the PLL. Reset this bit before initiating another sample. In High-Accuracy (Fine) mode, the processing time is twice the regular mode, but the uncertainty of the measurement is significantly reduced. DS70590C-page 22 Preliminary (c) 2009-2011 Microchip Technology Inc. MRF49XA REGISTER 2-4: W-1 TXCREG: TRANSMIT CONFIGURATION REGISTER (POR: 0x9800) W-0 W-0 W-1 W-1 W-0 W-0 W-0 CCB<15:9> MODPLY bit 15 bit 8 W-0 W-0 W-0 MODBW<3:0> W-0 W-0 r W-0 W-0 W-0 OTXPWR<2:0> bit 7 bit 0 Legend: r = reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-9 CCB<15:9>: Command Code bits The command code bits (1001100b) are serially sent to the microcontroller to identify the bits to be written in the TXCREG. bit 8 MODPLY: Modulation Polarity bit (for FSK) When MODPLY is configured as high/low: 1 = Logic `0' is the higher channel frequency and logic `1' is the lower channel frequency (negative deviation) 0 = Logic `0' is the lower channel frequency and logic `1' is the higher channel frequency (positive deviation) bit 7-4 MODBW<3:0>: Modulation Bandwidth bits These bits set the FSK frequency deviation for transmitting the logic `1' and logic `0'(1). 1111 = 240 kHz 1110 = 225 kHz 1101 = 210 kHz 1100 = 195 kHz 1011 = 180 kHz 1010 = 165 kHz 1001 = 150 kHz 1000 = 135 kHz 0111 = 120 kHz 0110 = 105 kHz 0101 = 90 kHz 0100 = 75 kHz 0011 = 60 kHz 0010 = 45 kHz 0001 = 30 kHz 0000 = 15 kHz bit 3 Reserved: Write as `0' Note 1: 2: The transmitter FSK modulation parameters are used for calculating the resulting output frequency, as shown in Equation 2-1. The output transmit power range is relative to the maximum available power, which depends on the actual antenna impedance. (c) 2009-2011 Microchip Technology Inc. Preliminary DS70590C-page 23 MRF49XA REGISTER 2-4: TXCREG: TRANSMIT CONFIGURATION REGISTER (POR: 0x9800) (CONTINUED) OTXPWR<2:0>: Output Transmit Power Range bits(2) These bits set the transmit output power range. The output power is programmable from 0 dB (Max.) to -17.5 dB in -2.5 dB steps. 111 = -17.5 dB 110 = -15.0 dB 101 = -12.5 dB 100 = -10.5 dB 011 = -7.5 dB 010 = -5.0 dB 001 = -2.5 dB 000 = 0 dB bit 2-0 Note 1: 2: The transmitter FSK modulation parameters are used for calculating the resulting output frequency, as shown in Equation 2-1. The output transmit power range is relative to the maximum available power, which depends on the actual antenna impedance. EQUATION 2-1: fFSKOUT = f0 +[(- 1)SIGN x (MB + 1) x (15 kHz)] where: f0 is the Channel Center Frequency (see Register 2-6 for f0 Calculation) MB is the 4-bit Binary Number (MODBW<3:0>) SIGN = MODPLY XOR FSK DS70590C-page 24 Preliminary (c) 2009-2011 Microchip Technology Inc. MRF49XA REGISTER 2-5: W-1 TXBREG: TRANSMIT BYTE REGISTER (POR: 0xB8AA) W-0 W-1 W-1 W-1 W-0 W-0 W-0 CCB<15:8> bit 15 bit 8 W-1 W-0 W-1 W-0 W-1 W-0 W-1 W-0 TXDB<7:0> bit 7 bit 0 Legend: r = reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-8 CCB<15:8>: Command Code bits The command code bits (10111000b) are serially sent to the microcontroller to identify the bits to be written in the TXBREG. bit 7-0 TXDB<7:0>: Transmit Data Byte bits The transmit data bits hold the 8 bits that are to be transmitted. To use this register, set the bit, TXDEN = 1 (GENCREG<7>). If TXDEN is not set, use the FSK/DATA/FSEL pin to manually modulate the data. (c) 2009-2011 Microchip Technology Inc. Preliminary DS70590C-page 25 MRF49XA REGISTER 2-6: CFSREG: CENTER FREQUENCY VALUE SET REGISTER (POR: 0xA680) W-1 W-0 W-1 W-0 W-0 W-1 CCB<15:12> W-1 W-0 FREQB<11:8> bit 15 bit 8 W-1 W-0 W-0 W-0 W-0 W-0 W-0 W-0 FREQB<7:0> bit 7 bit 0 Legend: r = reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-12 CCB<15:12>: Command Code bits The command code bits (1010b) are serially sent to the microcontroller to identify the bits to be written in the CFSREG. bit 11-0 FREQB<11:0>: Center Frequency Set bits These bits set the center frequency to be used during transmit or receive. The 12-bit value (FVAL) must be in a decimal range of 96 to 3903. The value outside this range results in the previous value being retained and used such that no frequency change occurs(1). Note 1: To calculate the center frequency (F0), use Equation 2-2 and the values from Table 2-5. The CFSREG sets the frequency within the selected band for transmit or receive. Each band has a range of frequencies available for changing channels or frequency hopping. The selectable frequencies for each band are given in Table 2-6. EQUATION 2-2: F0 = 10 x FA1 x (FA0 + FVAL/4000) MHz where: FVAL = Decimal Value of FREQB<11:0> = 96 < FVAL < 3903 Where FA0 and FA1 are constant values as given in Table 2-5 to calculate the Center Frequency. TABLE 2-5: CENTER FREQUENCY VALUE Range FA1 FA0 433 MHz 1 43 868 MHz 2 43 915 MHz 3 30 TABLE 2-6: FREQUENCY BAND TUNING RESOLUTION Frequency Band (MHz) Min. (MHz) Max. (MHz) Tuning Resolution (kHz) 400 430.2400 439.7575 2.5 800 860.4800 879.5150 5.0 900 900.7200 929.2725 7.5 DS70590C-page 26 Preliminary (c) 2009-2011 Microchip Technology Inc. MRF49XA REGISTER 2-7: W-1 RXCREG: RECEIVE CONTROL REGISTER (POR: 0x9080) W-0 W-0 W-1 W-0 CCB<15:11> W-0 W-0 FINTDIO W-0 DIORT<1:0> bit 15 bit 8 W-1 W-0 W-0 RXBW<2:0> W-0 W-0 RXLNA<1:0> W-0 W-0 W-0 DRSSIT<2:0> bit 7 bit 0 Legend: r = reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-11 CCB<15:11>: Command Code bits The command code bits (10010b) are serially sent to the microcontroller to identify the bits to be written in the RXCREG. bit 10 FINTDIO: Function Interrupt/Data Indicator Output bit Sets the pin 16 function as the DIO or interrupt. 1 = DIO output 0 = INT input bit 9-8 DIORT<1:0>: Data Indicator Output Response Time bits If pin 16 is selected as DIO, these bits set the response time within which the transceiver detects and indicates the incoming synchronous bit pattern, and issues an interrupt to the host microcontroller. 11 = Continuous 10 = Slow 01 = Medium 00 = Fast bit 7-5 RXBW<2:0>: Receiver Baseband Bandwidth bits These bits set the bandwidth of demodulated data. The bandwidth can accommodate different data rates and deviations during frequency keying. 111 = Reserved 110 = 67 kHz 101 = 134 kHz 100 = 200 kHz 011 = 270 kHz 010 = 340 kHz 001 = 400 kHz 000 = Reserved bit 4-3 RXLNA<1:0>: Receiver LNA Gain bits These bits, when set to different values, can accommodate environments with high interferences. The LNA gain also affects the true RSSI value. 11 = -20 dB 10 = -14 dB 01 = -6 dB 00 = 0 dB (c) 2009-2011 Microchip Technology Inc. Preliminary DS70590C-page 27 MRF49XA REGISTER 2-7: bit 2-0 RXCREG: RECEIVE CONTROL REGISTER (POR: 0x9080) (CONTINUED) DRSSIT<2:0>: Digital RSSI Threshold bits These bits can be set to indicate the incoming signal strength above a preset limit. The result enables or disables the DQDO bit (STSREG<7>). 111 = Reserved 110 = Reserved 101 = -73 dB 100 = -79 dB 011 = -85 dB 010 = -91 dB 001 = -97 dB 000 = -103 dB DS70590C-page 28 Preliminary (c) 2009-2011 Microchip Technology Inc. MRF49XA REGISTER 2-8: W-1 BBFCREG: BASEBAND FILTER CONFIGURATION REGISTER (POR: 0xC22C) W-1 W-0 W-0 W-0 W-0 W-1 W-0 CCB<15:8> bit 15 bit 8 W-0 W-0 W-1 W-0 W-1 ACRLC MCRLC r FTYPE r W-1 W-0 W-0 DQTI<2:0> bit 7 bit 0 Legend: r = reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-8 CCB<15:8>: Command Code bits The command code bits (11000010b) are serially sent to the microcontroller to identify the bits to be written in the BBFCREG. bit 7 ACRLC: Automatic Clock Recovery Lock Control bit 1 = Configures the clock recovery lock control as automatic. In this setting, the clock recovery starts in Fast mode and automatically switches to Slow mode after locking 0 = Clock recovery lock is controlled in Manual mode bit 6 MCRLC: Manual Clock Recovery Lock Control bit 1 = Configures the clock recovery lock control to Fast mode. Fast mode requires a preamble of at least 6-8 bits to determine the clock rate and then it locks. 0 = Configures the clock recovery lock control to Slow mode. Slow mode takes a bit longer period and requires a preamble of at least 12-16 bits to determine the clock rate and then it locks. Slow mode requires more accurate bit timing. See Register 2-12 for the relationship between data rate and clock recovery. bit 5 Reserved: Write as `1' bit 4 FTYPE: Filter Type bit 1 = Configures the baseband filter as an analog RC low-pass filter 0 = Configures the baseband filter as a digital filter(1) bit 3 Reserved: Write as `1' bit 2-0 DQTI<2:0>: Data Quality Threshold Indicator bits The threshold parameter for the DQI should be set to less than four to report good signal quality if the bit rate is close to the deviation. Usually, if the data rate falls less than the deviation, a higher threshold parameter is permitted and might report a good signal quality(2). Note 1: 2: The digital filter is a digital version of a simple RC low-pass filter followed by a comparator with hysteresis. The time constant for the digital filter is automatically calculated based on the bit rate set in the DRSREG. The bit rate in this mode should not exceed 115 kbps. In analog RC filter, the demodulator output is fed to the RCLKOUT/FCAP/FINT pin over a 10 k resistor. The filter cutoff frequency is set by the external capacitor connected to this pin and VSS. Table 2-6 shows the optimum filter capacitor values for different data rates. The DQI parameter is calculated using Equation 2-3. The DQI parameter in BBFCREG should be chosen according to the following rules: - The parameter should be > 4, otherwise, noise might be treated as a valid FSK signal. - The maximum value is 7. (c) 2009-2011 Microchip Technology Inc. Preliminary DS70590C-page 29 MRF49XA EQUATION 2-3: TABLE 2-7: DQIpar = 4 x (Deviation - TX/RXoffset)/Bit Rate DS70590C-page 30 DATA RATE VS. FILTER CAPACITOR VALUE Data Rate Preliminary Filter Capacitor Value 1.2 kbps 12 nF 2.4 kbps 8.2 nF 4.8 kbps 6.8 nF 9.6 kbps 3.3 nF 19.2 kbps 1.5 nF 38.4 kbps 680 pF 57.6 kbps 270 pF 115.2 kbps 150 pF 256 kbps 100 pF (c) 2009-2011 Microchip Technology Inc. MRF49XA REGISTER 2-9: W-1 RXFIFOREG: RECEIVER FIFO READ REGISTER (POR: 0xB000) W-0 W-1 W-1 W-0 W-0 W-0 W-0 CCB<15:8> bit 15 bit 8 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 RXDB<7:0> bit 7 bit 0 Legend: r = reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-8 CCB<15:8>: Command Code bits The command code bits (10110000b) are serially sent to the microcontroller to identify the bits to be written in the RXFIFOREG. bit 7-0 RXDB<7:0>: Receiver Data Byte bits These are the recovered data bits stored in the FIFO. The controller can read 8 bits from the receiver FIFO over the SPI bus. The FIFOEN bit (GENCREG<6>) should be set to receive these bits. (c) 2009-2011 Microchip Technology Inc. Preliminary DS70590C-page 31 MRF49XA REGISTER 2-10: W-1 FIFORSTREG: FIFO AND RESET MODE CONFIGURATION REGISTER (POR: 0xCA80) W-1 W-0 W-0 W-1 W-0 W-1 W-0 CCB<15:8> bit 15 bit 8 W-1 W-0 W-0 FFBC<3:0> W-0 W-0 W-0 W-0 W-0 SYCHLEN FFSC FSCF DRSTM bit 7 bit 0 Legend: r = reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-8 CCB<15:8>: Command Code bits The command code bits (11001010b) are serially sent to the microcontroller to identify the bits to be written in the FIFORSTREG. bit 7-4 FFBC<3:0>: FIFO Fill Bit Count bits Sets the received bits before generating an external interrupt to the host microcontroller to indicate the receive FIFO is ready to be read. The maximum fill level is 15(1). bit 3 SYCHLEN: Synchronous Character Length bit This bit sets the synchronous character length to byte or word long.(2) 1 = Byte long. User-programmable SCL0 byte is used. 0 = Word long. The character is composed of the SCL1 and SCL0 bytes. The SCL1 byte value is fixed and is not configurable. The SCL0 byte value is user-programmable through the SYNBREG. bit 2 FFSC: FIFO Fill Start Condition bit This bit sets the condition at which the FIFO starts filling with data. 1 = The FIFO will continuously fill irrespective of noise or good data 0 = The FIFO will fill when it recognizes the synchronous character pattern as defined internally bit 1 FSCF: FIFO Synchronous Character Fill bit 1 = The FIFO starts filling with data when it detects the synchronous character pattern as defined in the FFSC bit 0 = The FIFO fill stops To restart the synchronous character pattern recognition, just clear and set this bit(2). bit 0 DRSTM: Disable (Sensitive) Reset mode bit 1 = Disables(3) 0 = Enables System Reset for any glitches above 0.2V in the power supply Note 1: 2: 3: On register overrun, the data will be lost. Therefore, the developer must take into account the processing time required to read-out data before a register overrun. It is recommended to set the fill value to half of the desired number of bits to be read to ensure sufficient time for additional processing. See Register 2-1 for the description of the TXRXFIFO and TXUROW bits, and Register 2-9 for details on polling and interrupt driven FIFO reads from the SPI bus. For synchronous character length selection, see Table 2-8. For Reset mode selection, see Table 2-9. DS70590C-page 32 Preliminary (c) 2009-2011 Microchip Technology Inc. MRF49XA TABLE 2-8: SYNCHRONOUS CHARACTER SELECTION SYCHLEN SCL0 Synchronous Character 1 NA 0xD4 0xD4 (byte long) 0 0x2D 0xD4 0x2DD4 (word long) TABLE 2-9: RESET MODE SELECTION DRSTM Note: SCL1 Reset mode 1 Normal Reset 0 Sensitive Reset Condition Reset is triggered when VDD is below 250 mV Reset is triggered when VDD is below 1.6V and VDD glitch is greater than 600 mV See Appendix A: "Read Sequence and Packet Structures" for FIFO packet structures. (c) 2009-2011 Microchip Technology Inc. Preliminary DS70590C-page 33 MRF49XA REGISTER 2-11: W-1 SYNBREG: SYNCHRONOUS BYTE CONFIGURATION REGISTER (POR: 0xCED4) W-1 W-0 W-0 W-1 W-1 W-1 W-0 CCB<15:8> bit 15 bit 8 W-1 W-1 W-0 W-1 W-0 W-1 W-0 W-0 SYNCB<7:0> bit 7 bit 0 Legend: r = reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-8 CCB<15:8>: Command Code bits The command code bits (11001110b) are serially sent to the microcontroller to identify the bits to be written in the SYNBREG. bit 7-0 SYNCB<7:0>: Synch Byte Configuration bits The SYNBREG assigns the value to SCL0 of the synchronous character in the FIFORSTREG. The value is valid for a byte or word long synchronous character. DS70590C-page 34 Preliminary (c) 2009-2011 Microchip Technology Inc. MRF49XA REGISTER 2-12: W-1 DRSREG: DATA RATE VALUE SET REGISTER (POR: 0xC623) W-1 W-0 W-0 W-0 W-1 W-1 W-0 CCB<15:8> bit 15 bit 8 W-0 W-0 W-1 W-0 W-0 W-0 W-1 W-1 DRPV<6:0>(1) DRPE bit 7 bit 0 Legend: r = reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-8 CCB<15:8>: Command Code bits The command code bits (11000110b) are serially sent to the microcontroller to identify the bits to be written in the DRSREG. bit 7 DRPE: Date Rate Prescaler Enable bit 1 = Enables the prescaler to obtain smaller values of expected data rates. The prescaler value when enabled is approximately 1/8 of the actual data rate. 0 = Disables the prescaler bit 6-0 DRPV<6:0>: Data Rate Parameter Value bits(1) These bits represent the decimal value of the 7-bit parameter which is used to calculate the expected data rate. Note 1: To calculate the expected data rate, use Equation 2-4. To calculate the DRPV<6:0> decimal value for a given bit rate, use Equation 2-5. If the prescaler is not used, the data rates range from 2.694 kbps-344.828 kbps. With the prescaler enabled, the data rates range from 337 bps to 43.103 kbps. The Slow Clock Recovery mode requires more accurate bit timing when setting the data rate. Equation 2-6 is used to calculate the data rate accuracy for Fast and Slow modes. EQUATION 2-4: DREx (kbps) = 10000/[29 x (DRPV<6:0> + 1) x (1 + DRPE x 7)] where: DRPV<6:0> is the Decimal Value from 0 to 127 and the Prescaler (DRPE) is `1' (if ON) or `0' (if OFF). EQUATION 2-5: DRPV<6:0> = 10000/[29 x (1 + DRPE x 7) x DREx] - 1 where: DREx is the Expected Data Rate. EQUATION 2-6: * Slow mode Accuracy (SMA) = DR/DR < 1/(29 x LN) * Fast mode Accuracy (FMA) = DR/DR < 3/(29 x LN) where: LN is the longest number of expected 1's or 0's in the data stream. DR is the difference in the actual data rate versus the set data rate in the transmitter. DR is the expected data rate set using DRPV<6:0>. (c) 2009-2011 Microchip Technology Inc. Preliminary DS70590C-page 35 MRF49XA REGISTER 2-13: W-1 PMCREG: POWER MANAGEMENT CONFIGURATION REGISTER (POR: 0x8208) W-0 W-0 W-0 W-0 W-0 W-1 W-0 CCB<15:8> bit 15 bit 8 W-0 W-0 RXCEN BBCEN(1) W-0 TXCEN W-0 SYNEN W-1 OSCEN W-0 LBDEN W-0 W-0 (3) WUTEN CLKOEN bit 7 bit 0 Legend: r = reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-8 CCB<15:8>: Command Code bits The command code bits (10000010b) are serially sent to the microcontroller to identify the bits to be written in the PMCREG. bit 7 RXCEN: Receiver Chain Enable bit The receiver chain consists of a baseband circuit, synthesizer and crystal oscillator. 1 = Enables receiver chain 0 = Disables receiver chain bit 6 BBCEN: Baseband Circuit Enable bit(1) The baseband circuit, synthesizer and oscillator work together to demodulate and recover the data transmitted to the synthesizer (SYNEN bit). The OSCEN bit must be enabled along with the baseband circuits in order to receive data. 1 = Enables baseband circuit 0 = Disables baseband circuit bit 5 TXCEN: Transmit Chain Enable bit The transmit chain consists of power amplifier, synthesizer, oscillator and transmit register. 1 = Enables the transmitter chain and starts transmission (if the TX register is enabled) 0 = Disables transmitter chain bit 4 SYNEN: Synthesizer Enable bit The synthesizer consists of a PLL, oscillator and VCO for controlling the channel frequency. 1 = Enables the synthesizer 0 = Disables the synthesizer bit 3 OSCEN: Crystal Oscillator Enable bit 1 = Enables the crystal oscillator 0 = Disables the crystal oscillator bit 2 LBDEN: Low Battery Detector Enable bit The battery detector can be programmed to 32 different threshold levels(2). 1 = Enables the battery voltage detector circuit 0 = Disables the battery voltage detector circuit bit 1 WUTEN: Wake-up Timer Enable bit(3) 1 = Enables the wake-up timer circuit 0 = Disables the wake-up timer circuit Note 1: 2: 3: 4: This bit can be disabled to reduce current consumption. See BCSREG (Register 2-16) for programming details. See WTSREG (Register 2-14) for details on programming the wake-up timer value. If the CLKOEN bit is cleared by enabling the clock output, the oscillator continues to run even if the OSCEN bit is cleared. The device will not fully enter into the Sleep mode. DS70590C-page 36 Preliminary (c) 2009-2011 Microchip Technology Inc. MRF49XA REGISTER 2-13: bit 0 Note 1: 2: 3: 4: PMCREG: POWER MANAGEMENT CONFIGURATION REGISTER (POR: 0x8208) (CONTINUED) CLKOEN: Clock Output Enable bit On-chip Reset or power-up clock output is enabled so that a processor can execute any special setup sequences as required by the designer(2). 1 = Disables the clock output 0 = Enables the clock output(4) This bit can be disabled to reduce current consumption. See BCSREG (Register 2-16) for programming details. See WTSREG (Register 2-14) for details on programming the wake-up timer value. If the CLKOEN bit is cleared by enabling the clock output, the oscillator continues to run even if the OSCEN bit is cleared. The device will not fully enter into the Sleep mode. (c) 2009-2011 Microchip Technology Inc. Preliminary DS70590C-page 37 MRF49XA REGISTER 2-14: W-1 WTSREG: WAKE-UP TIMER VALUE SET REGISTER (POR: 0xE196) W-1 W-1 W-0 W-0 CCB<15:13> W-0 W-0 W-1 WTEV<4:0> bit 15 bit 8 W-1 W-0 W-0 W-1 W-0 W-1 W-1 W-0 WTMV<7:0> bit 7 bit 0 Legend: r = reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-13 CCB<15:13>: Command Code bits The command code bits (111b) are serially sent to the microcontroller to identify the bits to be written in the WTSREG. bit 12-8 WTEV<4:0>: Wake-up Timer Exponential Value bits These bits define the exponential value to be used to set up the time interval. The value must be a decimal equivalent between 0 and 29(1). bit 7-0 WTMV<7:0>: Wake-up Timer Multiplier Exponential Value bits These bits define the multiplier value to be used to set up the time interval. The value must be a decimal equivalent between 0 and 255(1). Note 1: The WTSREG sets the wake-up interval for the device. After setting the wake-up time, the WUTEN bit (PMCREG<1>) must be cleared and set at the end of every wake-up cycle. The wake-up duration can be calculated using Equation 2-7. EQUATION 2-7: WUTIME (ms) =[1.03 x WTMV<7:0> x 2WTEV<4:0>] + 0.5 ms where: WTMV<7:0> = Decimal Value between 0 to 255 WTEV<4:0> = Decimal Value between 0 to 29 DS70590C-page 38 Preliminary (c) 2009-2011 Microchip Technology Inc. MRF49XA REGISTER 2-15: W-1 DCSREG: DUTY CYCLE VALUE SET REGISTER (POR: 0xC80E) W-1 W-0 W-0 W-1 W-0 W-0 W-0 CCB<15:8> bit 15 bit 8 W-0 W-0 W-0 W-0 W-1 W-1 W-1 DCMV<6:0> W-0 DCMEN bit 7 bit 0 Legend: r = reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-8 CCB<15:8>: Command Code bits The command code bits (11001000b) are serially sent to the microcontroller to identify the bits to be written in the DCSREG. bit 7-1 DCMV<6:0>: Duty Cycle Multiplier Value bits These bits are used to calculate the duty cycle or on time of the receiver after the wake-up timer has brought the MRF49XA out of Sleep mode(1). bit 0 DCMEN: Duty Cycle mode Enable bit 1 = Enables the Duty Cycle mode 0 = Disables the Duty Cycle mode Note 1: For operation in Duty Cycle mode, the receiver must be disabled (RXCEN = 0) and the wake-up timer must be enabled (WUTEN = 1) in PMCREG. The registers, DCSREG and WTSREG, can be used to reduce the current consumption of the receiver. The DCSREG can be set up so that when the wake-up timer brings the MRF49XA out of Sleep mode, the receiver is turned on for a short period to sample the signal presence before returning to Sleep. The process in the Duty Cycle mode starts over. The duty cycle uses the multiplier value of the wake-up timer, in parts for its calculation, as shown in Equation 2-8. EQUATION 2-8: DC = [(DCMV<7:1> x 2 + 1)]/[WTMV<7:0> x 100%] where: WTMV is WTMV<7:0> bits of the WTSREG. (c) 2009-2011 Microchip Technology Inc. Preliminary DS70590C-page 39 MRF49XA REGISTER 2-16: W-1 BCSREG: BATTERY THRESHOLD DETECT AND CLOCK OUTPUT VALUE SET REGISTER (POR: 0xC000) W-1 W-0 W-0 W-0 W-0 W-0 W-0 CCB<15:8> bit 15 bit 8 W-0 W-0 W-0 COFSB<2:0> W-0 W-0 r W-0 W-0 W-0 LBDVB<3:0> bit 7 bit 0 Legend: r = reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-8 CCB<15:8>: Command Code bits The command code bits (11000000b) are serially sent to the microcontroller to identify the bits to be written in the BCSREG. bit 7-5 COFSB<2:0>: Clock Output Frequency Set bits These bits set the output clock frequency which can be used to run an external host microcontroller. 111 = 10 MHz 110 = 5 MHz 101 = 3.33 MHz 100 = 2.5 MHz 011 = 2 MHz 010 = 1.66 MHz 001 = 1.25 MHz 000 = 1 MHz bit 4 Reserved: Write as `0' bit 3-0 LBDVB<3:0>: Low Battery Detect Value bits These bits set the decimal value to calculate the battery detect threshold voltage level(1,2). Note 1: 2: When the battery level goes down by 50 mV below this value, the LBTD bit (STSREG<10>) is set, indicating that the battery level is below the programmed threshold. This is useful in monitoring discharge-sensitive batteries, such as Lithium cells. The low battery detect can be enabled by setting the LBDEN bit (PMCREG<2>) and can be disabled by clearing the bit. The low battery threshold value is programmable from 2.2V - 3.8V by using Equation 2-9. EQUATION 2-9: Threshold Voltage Value = 2.25 +[0.1 x (LBDVB<3:0>)] where: LBDVB<3:0> is the Decimal Value from 0 to 15. DS70590C-page 40 Preliminary (c) 2009-2011 Microchip Technology Inc. MRF49XA REGISTER 2-17: W-1 PLLCREG: PLL CONFIGURATION REGISTER (POR: 0xCC77) W-1 W-0 W-0 W-1 W-1 W-0 W-0 CCB<15:8> bit 15 bit 8 W-0 W-1 -- W-1 W-1 W-0 W-1 W-1 W-1 r PDDS PLLDD r PLLBWB CBTC<1:0> bit 7 bit 0 Legend: r = reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-8 CCB<15:8>: Command Code bits The command code bits (11001100b) are serially sent to the microcontroller to identify the bits to be written in the PLLCREG. bit 7 Unimplemented: Write as `0' bit 6-5 CBTC<1:0>: Clock Buffer Time Control bits These bits control the rise and fall time for the clock buffer which is dependant on the output clock frequency from the BCSREG. 11 = 5 MHz - 10 MHz 10 = 3.3 MHz 01 = 2.5 MHz or less 00 = 2.5 MHz or less bit 4 Reserved: Masked to `1' bit 3 PDDS: Phase Detector Delay Switch bit 1 = Enables the phase detector delay function 0 = Disables the phase detector delay function bit 2 PLLDD: PLL Dithering Disable bit 1 = Disables PLL dithering 0 = Enables PLL dithering bit 1 Reserved: Write as `1' bit 0 PLLBWB: PLL Bandwidth bit Enabling the bit configures higher data rates, faster settling and reduced phase noise; thus, resulting in a better RF performance. 1 = -102 dBc/Hz, > 90 kbps (max 256 kbps) 0 = -107 dBc/Hz, < 90 kbps (max 86.2 kbps) (c) 2009-2011 Microchip Technology Inc. Preliminary DS70590C-page 41 Reg. Name STSREG CONTROL/COMMAND REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 TXOWRXOF WUTINT LCEXINT Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 AFCCT OFFSV Preliminary TXRXFIFO POR LBTD FIFOEM ATRSSI DQDO CLKRL GENCREG 1 0 0 0 0 0 0 0 TXDEN FIFOEN AFCCREG 1 1 0 0 0 1 0 0 TXCREG 1 0 0 1 1 0 0 MODPLY TXBREG 1 0 1 1 1 0 0 0 CFSREG 1 0 1 0 RXCREG 1 0 0 1 0 FINTDIO BBFCREG 1 1 0 0 0 0 1 0 RXFIFOREG 1 0 1 1 0 0 0 0 FIFORSTREG 1 1 0 0 1 0 1 0 SYNBREG 1 1 0 0 1 1 1 0 DRSREG 1 1 0 0 0 1 1 0 DRPE PMCREG 1 0 0 0 0 0 1 0 RXCEN WTSREG 1 1 1 DCSREG 1 1 0 0 1 0 0 0 BCSREG 1 1 0 0 0 0 0 0 PLLCREG 1 1 0 0 1 1 0 0 Bit 3 Bit 2 Bit 0 OFFSB<3:0> FBS<1:0> AUTOMS<1:0> Bit 1 0x0000 LCS<3:0> ARFO<1:0> MFCS MODBW<3:0> HAM -- 0x8008 FOREN FOFEN OTXPWR<2:0> TXDB<7:0> RXBW<2:0> ACRLC 0xB8AA 0xA680 RXLNA<1:0> MCRLC -- FTYPE -- DRSSIT<2:0> 0x9080 DQTI<2:0> 0xC22C RXDB<7:0> FFBC<3:0> 0xB000 SYCHLEN FFSC FSCF DRSTM SYNCB<7:0> TXCEN SYNEN WTEV<4:0> OSCEN 0xC623 LBDEN WUTEN CLKOEN WTMV<7:0> -- CBTC<1:0> -- 1 DCMEN LBDVB<3:0> PDDS 0x8208 0xE196 DCMV<6:0> COFSB<2:0> 0xCA80 0xCED4 DRPV<6:0> BBCEN 0xC4F7 0x9800 FREQB<11:0> DIORT<1:0> Value on POR PLLDD -- 0xC80E 0xC000 PLLBWB 0xCC77 MRF49XA DS70590C-page 42 TABLE 2-10: (c) 2009-2011 Microchip Technology Inc. MRF49XA 3.0 FUNCTIONAL DESCRIPTION 3.1 Reset The MRF49XA is a low-power, Zero-IF, multi-channel FSK transceiver which operates in the 433, 868 and 915 MHz frequency bands. All the RF and baseband functions and processes are integrated in the MRF49XA. The device for its operation requires only a single, 10 MHz crystal as a reference source and an external, low-cost host microcontroller. The MRF49XA supports the following functions: The MRF49XA supports four types of Reset: * * * * * * * * * The MRF49XA has a built-in Power-on Reset circuitry which automatically resets all control registers when power is applied. A delay of 100 ms is recommended after a power-up sequence in order to allow the VDD to reach the correct voltage level and to get stabilized to recognize an active-low Reset. In Reset mode, the device does not accept the control commands through the SPI. Reset PA and LNA Synthesizer (PLL, VCO and Oscillator) I/Q Mixers and Demodulators BBFs and Amplifiers Received Signal Strength Indicator Low Battery Detector Wake-up Timer/Low Duty Cycle mode DQI The MRF49XA is the best option for FHSS applications requiring frequency agility to meet Federal Communications Commission (FCC), Industry Canada (IC) or European Telecommunications Standards Institute (ETSI) requirements. The communication link can be created by just using the MRF49XA along with a low-cost microcontroller. The device uses the different power-saving modes to reduce the overall current consumption, and thereby, extends the battery life of the system or application. FIGURE 3-1: * * * * Power-on Reset Power Glitch Reset Software Reset Reset Pin 3.1.1 POWER-ON RESET After power-up, the supply voltage starts to rise above 0V. The Reset block has an internal ramping voltage reference level (Reset ramp signal) which rises at a 100 mV/ms (typical) rate. The device remains in the Reset state until the voltage difference between the actual VDD and the internal Reset ramp signal is higher than the Reset threshold voltage level (typically 600 mV). The device remains in Reset mode as long as the VDD voltage level is less than 1.6V (typical), irrespective of the voltage difference between the VDD and the internal ramp signal. Figure 3-1 graphically shows the POR example for VDD with respect to time conditions. POWER-ON RESET EXAMPLE VDD Reset Threshold Voltage (600 mV) 1.6V Reset Ramp Line (100 mV/ms) Time RESET Output (Pin 10) H L (c) 2009-2011 Microchip Technology Inc. The device stays in Reset when VDD < 1.6V (even if the voltage difference is smaller than the Reset threshold). Preliminary DS70590C-page 43 MRF49XA 3.1.2 POWER GLITCH RESET Spikes or glitches are found on the VDD line if the power supply filtering is not satisfactory, or the internal resistance of the power supply is very high. So, in this case, the Sensitive Reset mode needs to be enabled. Here, the device Reset occurs due to the transients present on the VDD line. The internal Reset block has two basic modes of operation: The Sensitive Reset mode is the default mode which can be changed using the DRSTM bit (FIFORSTREG<0>). Figure 3-2 shows the Sensitive Reset mode. Normal Reset mode: The device enters this mode, when the power glitch detection circuit is disabled. Figure 3-3 shows the Normal Reset mode. Note: * Sensitive Reset mode * Normal Reset mode Sensitive Reset mode: Enabling the Sensitive Reset, a Reset is generated if: * the positive going edge of the VDD has a rising rate greater than 100 mV/ms, and * the voltage difference between the internal ramp signal and the VDD reaches the Reset threshold voltage (600 mV). FIGURE 3-2: Negative change in the supply voltage does not cause a Reset event unless the VDD level reaches the Reset threshold voltage (i.e., 250 mV in Normal Reset mode, 1.6V in Sensitive Reset mode). If the Sensitive mode is disabled and the power supply is turned off, the VDD requires 250 mV to trigger a Power-on Reset when the supply voltage is reapplied. If the decoupling capacitors retain their charges for a longer duration, there might be no Reset after power-up as the power glitch detector is disabled. Note: The Reset event reinitializes the internal registers, and thus, the Sensitive mode is enabled again. SENSITIVE RESET ENABLED V DD Reset Threshold Voltage (600 m V) Reset Ram p Line (100 m V/m s) 1.6V Tim e RESET Output (Pin 10) H L DS70590C-page 44 Preliminary (c) 2009-2011 Microchip Technology Inc. MRF49XA FIGURE 3-3: SENSITIVE RESET DISABLED V DD Reset Threshold Voltage (600 mV) Reset Ramp Line (100 mV/ms) 250 mV Time RESET Output (Pin 10) 3.1.3 H L SOFTWARE RESET The registers associated with Reset are: The Software Reset is initiated using the host microcontroller. The 0xFE00 command triggers this Reset only if the Sensitive Reset mode is enabled. The hardware automatically clears the bit(s) to their power-on state. The Software Reset command is the same as POR, but the duration of the Reset event is much less than the actual POR (0.25 ms, typical). 3.1.4 * STSREG (see Register 2-1) * FIFORSTREG (see Register 2-10) * WTSREG (see Register 2-14) RESET PIN The MRF49XA has an open-drain Reset output with an internal pull-up and input buffer (active-low). The host microcontroller resets the MRF49XA by asserting the RESET pin to low (see Figure 3-4). All control registers are reset to their POR values. The RESET pin consists of an internal weak pull-up resistor. In order to allow the RF circuitry to start-up and get stabilized, a delay of around 0.25 ms is recommended for accessing the MRF49XA after a hardware Reset. FIGURE 3-4: RESET PIN INTERNAL CONNECTION V DD To M CU Reset (Input/Output*) 100k To Internal Reset Logic RESET Pin N 10k From POR Circuit V SS * These pins can be left floating. (c) 2009-2011 Microchip Technology Inc. Preliminary DS70590C-page 45 MRF49XA 3.2 VDD Line Filtering During the Reset event (caused by power-on, glitch on the supply line or Software Reset), the VDD line should be kept clean. Noise or a periodic disturbing signal superimposed on the supply voltage may prevent the device from getting out of the Reset state. To avoid this, adequate filters should be made available on the power supply lines to keep the distorting signal level below 100 mVp-p, in the DC-50 kHz range for 200 ms, from VDD ramp start. The usage of regulators or SMPS may sometimes introduce switching noise on the VDD line, so follow the power supply manufacturer's recommendations on how to decrease the ripple of regulator IC and/or how to shift the switching frequency while using SMPS. The registers associated with power line filtering are: * STSREG (see Register 2-1) * FIFORSTREG (see Register 2-10) * WTSREG (see Register 2-14) DS70590C-page 46 Preliminary (c) 2009-2011 Microchip Technology Inc. MRF49XA 3.3 Power and Low Noise Amplifiers The PA is an open-collector, differential output with programmable output power which can directly drive a loop or dipole antenna, and with proper matching, can also drive a monopole antenna. An automatic antenna tuning circuit configured in the PA avoids the manual tuning during production and this offsets "hand effects". TABLE 3-1: PROGRAMMABLE LOAD CAPACITANCE VALUE CAP3 CAP2 CAP1 CAP0 Load Capacitance 0 0 0 0 8.5 0 0 0 1 9 The registers associated with the PA are: 0 0 1 0 9.5 * TXCREG (see Register 2-4) * PMCREG (see Register 2-13) 0 0 1 1 10 0 1 0 0 10.5 0 1 0 1 11 0 1 1 0 11.5 0 1 1 1 12 1 0 0 0 12.5 1 0 0 1 13 1 0 1 0 13.5 1 0 1 1 14 1 1 0 0 14.5 1 1 0 1 15 1 1 1 0 15.5 1 1 1 1 16 The input LNA has selectable gain (0 dB, -6 dB, -14 dB and -20 dB) which is useful in environments with strong interferers. The LNA has 250 of differential input impedance, which requires a matching circuit when connected to 50 devices. The registers associated with the LNA are: * RXCREG (see Register 2-7) * PMCREG (see Register 2-13) 3.4 Crystal Oscillator and Clock Output The MRF49XA has a single pin crystal oscillator circuit, which provides a 10 MHz reference signal for the on-chip PLL. The clock frequency is programmable from eight predefined frequencies, each being a prescaled value of a 10 MHz crystal reference. A programmable crystal load capacitor has been internally configured to reduce the external component count and to have a much simplified design. The internal load capacitor is programmable from 8.5 pF - 16 pF in 0.5 pF steps as defined GENCREG. This provides the advantage of accepting a wide range of crystals from different manufacturers with different load capacitance requirements. For load capacitance values, see Table 3-1. These values are programmable through the BCSREG (see Register 2-16). The crystal oscillator circuit is sensitive to parasitic capacitance for start-up. A small amount of parasitic capacitance is needed to facilitate oscillation. To achieve this, create a ground plane around the crystal and widen the connection to the MRF49XA. This is to adjust the reference frequency and to compensate for stray capacitance that might be introduced due to PCB layout. If the layout is not possible, a 0.5 pF - 1 pF capacitor, soldered across the crystal, will initiate the start-up. Also, see Section 3.6, Crystal Selection Guidelines for selecting the right crystal. The crystal oscillator provides a reference signal to the RF synthesizer, baseband circuits and digital signal processing parts. If receiver or transmitter blocks are used frequently, it is recommended to leave the oscillator running because the crystal might need a few milliseconds to start and stabilize. The stabilization time mainly depends on the crystal parameters. The CLKOEN bit (PMCREG<0>) is used to enable or disable the clock output. 3.4.1 CLOCK TAIL FEATURE The MRF49XA provides the clock signal for the microcontroller for accurate timing, and thus, removes the need for a second crystal for any board design. When the microcontroller turns off the crystal oscillator by clearing the OSCEN bit (PMCREG<3>), the MRF49XA provides a fixed number (192) of further clock pulses for the microcontroller to switch itself to Idle or Sleep mode (Low-Power Consumption modes). To use this feature, STSREG must be read before the OSCEN bit is set to `0'. If STSREG is not read, then the clock output will not shut down. If the CLKOUT pin is not used, it is suggested to turn off the output buffer from PMCREG. Note: Leaving blocks needlessly turned on increases the current consumption, and thus, reduces the battery life. The microcontroller clock source (if the clock is not supplied by the MRF49XA) should be stable enough over temperature and voltage ranges to ensure a minimum of 16 bits time delay under all operating circumstances. (c) 2009-2011 Microchip Technology Inc. Preliminary DS70590C-page 47 MRF49XA 3.4.2 AUTO CRYSTAL OSCILLATOR When an interrupt occurs, irrespective of the OSCEN bit setting, the crystal oscillator automatically turns on to supply a clock signal to the microcontroller. After clearing all interrupts and reading the STSREG, the crystal oscillator is automatically turned off. The clock tail feature provides enough clock pulses for the microcontroller to enter the Low-Power mode. Due to this automatic feature, it is not possible to turn off the crystal by clearing the OSCEN bit if any interrupt is active. For example, after power-on, the POR interrupt must be cleared by reading STSREG and then writing `0' to the OSCEN bit puts the part in Sleep mode. It is necessary to clear all interrupts before turning the OSCEN bit off as the extra current required for running the crystal oscillator can shorten the battery life significantly. On disabling the clock output (CLKOEN = 1), both the clock tail and auto crystal oscillator usage features are turned off. Only the OSCEN bit controls the crystal oscillator (considering that both RXCEN and TXCEN bits are cleared); the interrupts have no effect on it. The registers associated with the crystal oscillator and clock are: * * * * * STSREG (see Register 2-1) AFCCREG (see Register 2-3) PMCREG (see Register 2-13) BCSREG (see Register 2-16) PLLCREG (see Register 2-17) 3.5 Phase-Locked Loop The synthesizer consists of a PLL, oscillator and VCO for controlling the channel frequency. The synthesizer must be enabled when either the transmitter or the receiver is enabled. For faster RX/TX switching, the synthesizer block must be kept on. Enabling the transmitter using the TXCEN bit (PMCREG<5>) will turn on the PA, and since the synthesizer is already up and running, the PA immediately produces the TX signal at the output. The oscillator must also be enabled to provide the reference frequency for the PLL. On power-up, the synthesizer performs the calibration automatically. The synthesizer also has an internal start-up calibration procedure. If there are significant changes in voltage or temperature, recalibration should be performed by simply disabling the synthesizer and re-enabling it. When set, the SYNEN bit (PMCREG<4>) enables the synthesizer. DS70590C-page 48 The PLL circuit automatically performs the fine adjustment of carrier frequency. This way, the receiver can minimize the offset between a transmit and receive frequency. The frequency control function can be enabled or disabled through AFCCREG. The range of offset can be programmed and the offset value is calculated and added to the frequency control word within the PLL to incrementally change the carrier frequency. The MRF49XA can be programmed to automatically change and control the carrier frequency. The carrier frequency can also be manually activated by a strobe signal. The oscillator provides the reference signal to the RF synthesizer to set up the transmit or receive frequency. The crystal oscillator also provides a reference signal to the RF, baseband circuits and microcontroller interface. The PLL following: * * * * * Configuration register configures the Output clock buffer slew rate Crystal start-up time Phase detector delay PLL dithering PLL bandwidth The dithering reduces the noise error when calculating the fractional-N synthesizer code. When the PLLDD bit (PLLCREG<2>) is cleared, dithering is enabled and the settling time is slightly increased. The PLL bandwidth can accommodate higher data rates above 90 kbps. The reduced PLL bandwidth allows faster settling time and reduced phase noise, and thus, results in a better RX performance. See Register 2-17 for details on PLL setting and configuration. The registers associated with the PLL are: * * * * * STSREG (see Register 2-1) AFCCREG (see Register 2-3) PMCREG (see Register 2-13) BCSREG (see Register 2-16) PLLCREG (see Register 2-17) Preliminary (c) 2009-2011 Microchip Technology Inc. MRF49XA 3.6 Crystal Selection Guidelines The crystal oscillator of MRF49XA requires a 10 MHz Parallel mode crystal. The circuit contains an integrated load capacitor in order to minimize the external component count. The internal load capacitance value is programmable from 8.5 pF - 16 pF in 0.5 pF steps. With appropriate PCB layout, the total load capacitance value can be 10 pF - 20 pF, so a variety of crystal types can be used. When the total load capacitance is not more than 20 pF, and a worst case 7 pF Shunt Capacitance (CS) value is expected for the crystal, the oscillator is able to start-up with any crystal having less than 100 Equivalent Series Loss Resistance (ESR). However, the low CS and ESR values ensure the faster oscillator start-up. FIGURE 3-5: The Crystal Frequency (fref) is used as the reference of the PLL, which generates the Local Oscillator Frequency (fLO). Therefore, fLO is directly proportional to fref. The accuracy requirements for production tolerance, temperature drift and aging can thus be determined from the maximum allowable local oscillator frequency error. Whenever a low-frequency error is essential for the application, it is possible to "pull" the crystal to the accurate frequency by changing the load capacitor value. The widest pulling range can be achieved if the nominal required load capacitance of the crystal is in the "midrange"; for example, 16 pF. The "pull-ability" of the crystal is defined by its Motional Capacitance (Cm) and shunt capacitance. MAXIMUM CRYSTAL TOLERANCES INCLUDING TEMPERATURE AND AGING (ppm) Bit Rate: 2.4 kbps 433 MHz 868 MHz 915 MHz 30 20 10 10 45 30 20 15 Deviation [ kHz] 60 75 50 70 25 30 25 30 90 90 40 40 105 100 50 50 120 100 60 50 45 30 15 15 Deviation [ kHz] 60 75 50 70 25 30 25 30 90 80 40 40 105 100 50 50 120 100 60 50 45 5 3 3 Deviation [ kHz] 60 75 20 30 10 20 10 15 90 50 25 25 105 75 30 30 120 75 40 40 Deviation [ kHz] 135 150 20 30 10 20 10 15 165 50 25 25 Bit Rate: 9.6 kbps 433 MHz 868 MHz 915 MHz 30 15 8 8 Bit Rate: 38.4 kbps 433 MHz 868 MHz 915 MHz 30 Do Not Use Do Not Use Do Not Use Bit Rate: 115.2 kbps 433 MHz 868 MHz 915 MHz 105 Do Not Use Do Not Use Do Not Use (c) 2009-2011 Microchip Technology Inc. 120 3 Do Not Use Do Not Use Preliminary 180 70 35 30 195 80 45 40 DS70590C-page 49 MRF49XA 3.7 Automatic Frequency Control The AFC block operates in two modes and these modes depend on the strobe signals which are governed by the MFCS bit (AFCCREG<3>). The two operating modes are as follows: caused by the crystal tolerances. This method allows the use of a low-cost quartz crystal in the application and provides protection against interference. (AUTOMS1 = 1, AUTOMS0 = 0): The frequency offset is automatically calculated and the center frequency is corrected when the DIO is high. When DIO goes low, the calculated value is dropped. 3. * Manual mode * Automatic mode Manual mode: In this mode, the microcontroller provides the manual frequency control strobe signal. See Register 2-3 (AFCCREG) for more details. One measurement cycle can compensate for around 50% - 60% of the actual frequency offset. Two measurement cycles can compensate for 80% and three measurement cycles can compensate for 92% of the actual frequency offset. The AFCCT bit (STSREG<5>) is used to determine when the actual measurement cycle has been completed. Automatic mode: In this mode, the strobe signal from the microcontroller is not required to update the Frequency Offset register block, as shown in Figure 3-6. The AFC circuit is automatically enabled when the DIO indicates the potential incoming signal during the entire measurement cycle and measures the same result in two subsequent cycles. Without AFC, the transmitter and the receiver need to be tuned precisely to the same frequency. The RX/TX frequency offset can lower the range. The units must be adjusted carefully during the production. To avoid drift, a stable and efficient crystal must be used or the output power needs to be increased to compensate for yield loss. The two methods recommended for improving the accuracy of the AFC calculation are as follows: * The transmit package should start with a low effective baud rate pattern (i.e., 00110011b) as it is easier to receive. The circuit automatically measures the frequency offset during this initial pattern and changes the receiving frequency accordingly. The remaining part of the package will be received by the corrected frequency settings. * The transmitter sends the first part of the packet with a higher deviation step than required during normal operation to help reception. After the frequency shift correction, the deviation can be reduced. In both methods, when the DIO indicates poor receiving conditions (i.e., when DIO goes low), the output register is automatically cleared. This mode (Drop Offset mode) is used when the receiver communicates with more than one transmitter. 4. (AUTOMS1 = 1, AUTOMS0 = 1): This mode (Keep Offset mode) is similar to Drop Offset mode, but is recommended for use when the receiver communicates with only one transmitter. After a complete measuring cycle, the measured value is kept independent of the state of the DIO signal. In this mode, the DRSSI limit should be carefully selected to minimize the range hysteresis. The AFC block calculates the TX/RX offset using the OFFSB bits (STSREG<3:0>). This value is used to pull the RX synthesizer close to the transmitter frequency. The benefits of the AFC feature are: * Low-cost crystal can be used * Temperature or aging drift will not cause range loss * Production alignment is not needed Figure 3-6 depicts the AFC circuit for frequency offset correction. The Automatic mode Selection bits, AUTOMS<1:0> (AFCCREG<7:6>), select the type of operation (automatic or manual) for performing the AFC based on the status of the MFCS bit (AFCCREG<3>). There are four types of operation modes for controlling the frequency: 1. 2. (AUTOMS1 = 0, AUTOMS0 = 0): Automatic operation of AFC is off. The MFCS bit is controlled by the microcontroller. (AUTOMS1 = 0, AUTOMS0 = 1): The circuit measures the frequency offset only once after power-up. Hence, extended TX to RX distance can be achieved. In the actual application, when the user applies a battery, the circuit measures and compensates for the frequency offset DS70590C-page 50 The AFC Offset Value (OFFSB<3:0> bits in the status word) is represented as a two's complement number. The actual frequency offset is calculated as the AFC offset value multiplied by the current PLL frequency step (see Register 2-6 for more details). The actual RX/TX offset can be monitored by using the AFC status report (i.e., AFCCT bit) included in the status word of the receiver. By reading out the status word, the actual measured offset frequency can be derived. To get accurate values, the AFC has to be disabled during read by clearing the FOFEN bit (AFCCREG<0>). The registers associated with AFC are: * * * * * STSREG (see Register 2-1) AFCCREG (see Register 2-3) CFSREG (see Register 2-6) RXCREG (see Register 2-7) PLLCREG (see Register 2-17) Preliminary (c) 2009-2011 Microchip Technology Inc. (c) 2009-2011 Microchip Technology Inc. FIGURE 3-6: AFC CIRCUIT FOR FREQUENCY OFFSET CORRECTION Baseband Signal IN AFCCT STSIG HAM FINE SEL 10 Y 10 MHz CLK /4 11 MUX FIFOEN Enable Calculation CLK Digital AFC Core Logic OFFSB <6:0> 7-Bit Digital Limiter If IN > MaxDEV then, OUT = MaxDEV 7 7 If IN < MinDEV then, OUT = MinDEV Frequency Offset Register DIO AUTOMS<1:0> Auto Operation Signals for Auto Operation modes ADDER FCOR<11:0> Corrected Frequency Parameter to Synthesizer ELSE, OUT = IN Preliminary CLK POR ARFO<1:0> 12-Bit CLR Range Limit Strobe MFCS Strobe Output Enable FOREN Output Enable FREQB<11:0> DS70590C-page 51 MRF49XA Parameter from Frequency Control Word MRF49XA 3.8 Initialization 3.9 Certain control register values must be initialized for the basic operations of MRF49XA. These values differ from the Power-on Reset values and provide improved operational parameters. These settings are normally made once after a Reset. After initialization, the MRF49XA device features can be configured for the application. Here, accessing a register is implied as a command to the MRF49XA device through the SPI port. The steps to be followed for the initialization of MRF49XA using the control registers are as follows: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. Set FIFORSTREG. Enable synchronous latch from FIFORSTREG. Program frequency band and crystal load capacitance from GENCREG. Enable AFC function from AFCCREG. Set center frequency through CFSREG for transmit or receive frequency. Set data rate through DRSREG. Enable required functions (transmit, receive, etc.) from PMCREG. Configure RXCREG. Configure TXCREG. Tune in the antenna. Turn off the transmitter and turn on the receiver. Enable FIFO for data reception. Set FIFORSTREG. Enable synchronous latch from FIFORSTREG. Read STSREG. Interrupts The advanced interrupt handler circuit is implemented in the MRF49XA to reduce the power consumption. As mentioned, the Sleep mode is the lowest power consumption mode in which the mode clock and all functional blocks of the chip are disabled. However, the WUT and LBD circuits can be active if enabled. In case of any interrupt, the device wakes up, switches to the Active mode and an interrupt signal generated on the IRO pin of the device indicates the change in state or occurrence of an interrupt to the host microcontroller. The source of the interrupt is determined by reading the status word of the device (see Register 2-1). The receiver generates an active-low interrupt request for the microcontroller at the following events: * TXBREG is ready to receive the next byte * RXFIFOREG has received the preprogrammed amount of bits * RXFIFOREG overflow/TXBREG underrun * Negative pulse on Interrupt Input pin (INT) * Wake-up Timer Time-out (WUTINT) * Supply voltage below the preprogrammed value is detected * Power-on Reset The following steps should be followed to tune in the antenna section: 1. 2. Turn on the transmitter section from PMCREG. Wait for 5 ms for the oscillator to get stabilized. The registers associated with initialization are: * * * * * * * * * STSREG (see Register 2-1) GENCREG (see Register 2-2) AFCCREG (see Register 2-3) TXCREG (see Register 2-4) CFSREG (see Register 2-6) RXCREG (see Register 2-7) FIFORSTREG (see Register 2-10) DRSREG (see Register 2-12) PMCREG (see Register 2-13) DS70590C-page 52 Preliminary (c) 2009-2011 Microchip Technology Inc. MRF49XA 3.9.1 SETTING INTERRUPTS 3.9.1.4 The device's interrupt pin (IRO) signals one of eight interrupt events to the host microcontroller. The interrupt source in the microcontroller is read out from the transceiver through the SDO pin. The interrupt sources that are available are briefly described in the following subsections. 3.9.1.1 1. TXRXFIFO: Transmit Register or Receive FIFO bit Transmit mode: Transmit Register Ready bit This interrupt is generated when the Transmit register is empty. It is valid only when the TXDEN bit (GENCREG<7>) is set and the TXCEN bit (PMCREG<5>) is enabled. 2. Receive mode: Receive FIFO Empty bit This interrupt is generated when the bit level in the RXFIFOREG has reached the preprogrammed level. An interrupt is triggered when the number of received data bits in the receiver FIFO reaches the threshold set by the FFBC bits (FIFORSTREG<7:4>). This is valid only when the FIFOEN bit (GENCREG<6>) is set and the RXCEN bit (PMCREG<7>) is enabled. 3.9.1.2 POR: Power-on Reset Interrupt The POR interrupt is generated when a change on the VDD line triggers an internal Reset circuit or a Software Reset was issued. For details, see Section 3.1, Reset. 3.9.1.3 1. 2. TXOWRXOF: Transmit Overwrite Receive Overflow bit WUTINT: Wake-up Timer Interrupt This interrupt occurs when the time specified by the wake-up timer has elapsed. It is valid only when the WUTEN bit (PMCREG<1>) is set. The device periodically wakes up and switches to Receive mode. If valid FSK data is received, the device sends an interrupt to the microcontroller and continues filling the RXFIFO. After the completion of transmission, the FIFO is read out completely and all other interrupts are cleared. The device returns to the Low-Power Consumption mode. 3.9.1.5 LCEXINT: Logic Low-Level Change on External Interrupt Follows the level of the INT pin if configured as an external interrupt by clearing the FINTDIO bit (RXCREG<10>). 3.9.1.6 LBTD: Low Battery Threshold Detect This interrupt occurs when VDD goes below the programmable low battery detector threshold level configured by the LBDVB bits (BCSREG<3:0>). It is valid only when the LBDEN bit (PMCREG<2>) is set. 3.9.2 CLEARING INTERRUPTS If any of the interrupt sources gets active, the IRO changes to logic low level and the corresponding interrupt bit in the status byte goes high. Clearing an interrupt implies: * releasing the IRO pin to return to logic high, and * clearing the corresponding interrupt bit in the STSREG Transmit mode: Transmit Register Underrun or Overwrite bit The clearing of each of the interrupts is briefly described in the following subsections. This interrupt is generated when the automatic Baud Rate Generator (BRG) has completed the transmission of a byte in TXBREG before the register write. It is valid only when the TXDEN bit (GENCREG<7>) is set and the TXCEN bit (PMCREG<5>) is enabled. 3.9.2.1 1. Transmit mode The IRO pin and its status bit remain active until the register is written (if underrun does not occur until the register write) or the transmitter and the TX latch are switched off. Receive mode: Receive FIFO Overflow bit This interrupt is generated when the bits received are more than the FIFO capacity (16 bits). This is valid only when the FIFOEN bit (GENCREG<6>) is set and the RXCEN bit (PMCREG<7>) is enabled. TXRXFIFO 2. Receive mode The IRO pin and its status bit remain active until the FIFO is read (receive FIFO interrupt threshold number of bits have been read). The receiver is switched off or the RXFIFO is switched off. 3.9.2.2 POR The IRO pin and its status bit are cleared by reading the Status Read register. (c) 2009-2011 Microchip Technology Inc. Preliminary DS70590C-page 53 MRF49XA 3.9.2.3 1. TXOWRXOF Transmit mode In this mode, the TXOWRXOF and TXRXFIFO bits are always set together. The IRO pin and its status bit remain active until the transmitter and the TX latch are switched off. 2. Receive mode In this mode, the TXOWRXOF and TXRXFIFO bits are always set together and can be cleared by reading the STSREG. The IRO pin and its status bit remain active until the FIFO is read (a FIFO interrupt threshold number of bits have been read), the receiver is switched off or the RX FIFO is switched off. 3.9.2.4 WUTINT The IRO pin and its status bit are cleared by reading the STSREG. 3.9.2.5 LCEXINT feature provides sufficient clock pulses for the microcontroller to enter the Low-Power Consumption mode. Due to this automatic feature, it is not possible to turn off the crystal by clearing the OSCEN bit if any interrupt is active. For example, after power-on, the POR interrupt must be cleared by a status read, and then by writing `0' in the OSCEN bit, puts the device into Sleep mode. Note: Before turning the OSCEN bit off, clear all the interrupts, because the additional current required for running the crystal oscillator can shorten the battery life significantly. The registers associated with interrupts are: * * * * * STSREG (see Register 2-1) GENCREG (see Register 2-2) RXCREG (see Register 2-7) PMCREG (see Register 2-13) BCSREG (see Register 2-16) The IRO pin and its status bit follow the level of the INT pin. 3.9.2.6 LBTD The IRO pin is released by reading the status bit of STSREG, but the status bit remains active until the VDD is below the threshold value. The MRF49XA interrupt generation logic is shown in Figure 3-7. A better way of interrupt handling is to first read the STSREG on an interrupt and then decide the action based on the status byte/word. It is important to note that any of the interrupt sources can wake-up the MRF49XA from Sleep mode. This means that the crystal oscillator starts to supply a clock signal to the microcontroller even if the microcontroller has its own clock source. The MRF49XA will not enter Sleep mode if any of the interrupt remains active, irrespective of the state of the OSCEN bit in PMCREG. This way, the microcontroller can always have a clock signal to process the interrupt. To prevent high-current consumption, which results in short battery life, it is highly recommended to process and clear interrupts before entering Sleep mode. The functions which are not necessary should be turned off to avoid unwanted interrupts. Before finalizing the microcontroller (application) code, a thorough testing must be conducted to make sure that all interrupt sources are handled before putting the transceiver in Sleep mode. The OSCEN bit controls the crystal oscillator (considering that the RXCEN and TXCEN bits are cleared) if the CLKOEN bit (PMCREG<0>) is set. The interrupts have no effect on it. On interrupt, the crystal oscillator turns on automatically to supply a clock signal to the microcontroller, irrespective of the OSCEN bit setting. The clock tail DS70590C-page 54 Preliminary (c) 2009-2011 Microchip Technology Inc. MRF49XA FIGURE 3-7: MRF49XA INTERRUPT GENERATION LOGIC TXRXFIFO TXCEN TXRXFIFO RXCEN RESET (Ext./Int.) TXOWRXOF TXCEN IRO TXOWRXOF RXCEN WUTINT WUTEN LCEXINT (INT) FINTDIO LBTD LBDEN (c) 2009-2011 Microchip Technology Inc. Preliminary DS70590C-page 55 MRF49XA 3.10 Baseband/Data Filtering A suitable bandwidth should be used to achieve various FSK deviation, data rate and crystal tolerance requirements. The filter structure is a 7th order, Butterworth low-pass with 40 dB suppression at twice the bandwidth frequency. Offset cancellation is done by using a high-pass filter, with a cutoff frequency below 7 kHz, in order to achieve the best possible frequency response in baseband and a good flat response in the pass band. Figure 3-8 shows the full baseband amplifier transfer function. This optimizes the chip area, cost and channel separation. The baseband receiver has several programming options to optimize the communication for a wide range of applications. The programmable functions are as follows: * * * * * Baseband Analog Filter Baseband Digital Filter Receive Bandwidth Receive Data Rate Clock Recovery FIGURE 3-8: FULL BASEBAND AMPLIFIER TRANSFER FUNCTION (BW = 67 kHz) 40 Output Power Level (dB) 20 0 -20 -40 -60 -80 -100 -120 -140 1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06 Frequency (Hz) The receive bandwidth is programmable from 67 kHz to 400 kHz to accommodate various FSK modulation deviations. If the deviation is known for a given transmitter, good results are obtained with a bandwidth of at least twice the transmitter FSK deviation. EXAMPLE 3-1: * * * * Example 3-1 shows the method to calculate the recommended frequency deviation and BBBW for the given specifications. FREQUENCY DEVIATION AND BBBW CALCULATION Data Rate - 9.6 kbps Crystal Accuracy - 40 ppm Frequency Band - 915 MHz fxerror by the Crystal: 40 x (915000/1000000) = 36.6 kHz Deviation = Data Rate + 2 x fxerror + 10 = 9.6 + 2 x 36.6 + 10 = 92.8 kHz The closest possible deviation is 90 kHz. BBBW = Deviation x 2 - 10 kHz = 90 x 2 - 10 = 170 kHz The closest possible BBBW is 200 kHz. The FSK modulated deviation for this example is shown in Figure 3-9. DS70590C-page 56 Preliminary (c) 2009-2011 Microchip Technology Inc. MRF49XA FIGURE 3-9: FSK MODULATED DEVIATION - MAXIMUM TX TO RX OFFSET 2 x deviation Amplitude 10 kHz + Data Rate Baseband Filter Characteristic Data Rate TX-RX Offset Frequency BBBW Programmable The baseband filtering type can also be selected between an analog filter and a digital filter. 3.10.1 ANALOG FILTERING MODE For analog filtering, a simple RC low-pass filter is used, along with a Schmitt Trigger circuit. The demodulator output is fed to the RCLKOUT/FCAP/FINT pin over a 10 k resistor. The filter cut-off frequency is set by the external capacitor connected to this pin and VSS. A 10 k resistor and the Schmitt Trigger are integrated on the chip. An external capacitor for the RC filter has to be chosen in accordance with the required bit rate. The receiver can handle up to 256 kbps of data rate in analog operation. The receive data rate is programmable from 337 bps to 256 kbps. An internal prescaler can be used to give better resolution when setting up the receive data rate. The prescaler is optional and can be disabled through DRSREG. The analog filtering does not use the FIFO and the clock. The clock is not provided for the demodulated data, and hence, there is no need for setting the correct bit rate. (c) 2009-2011 Microchip Technology Inc. RX Center Freq. 10 kHz 3.10.2 TX Center Freq. DIGITAL FILTERING MODE A digital filter is used with a clock frequency at 29 times the data rate. For digital filtering, the synchronized clock to the data is provided by the CLKRC. By using this clock, the received data can fill the FIFO. If the FIFO is not used, the recovered clock can be accessed through RCLKOUT/FCAP/ FINT pin. The CLKRC operates in three modes: Automatic mode, Slow mode and Fast mode. All three modes are configurable through BBFCREG. Each mode is dependent on the type of signals it uses to determine the valid data and also the number of incoming preamble bits present at the beginning of the packet. In Automatic mode, the CR CLKRC automatically switches between the Fast and Slow mode. The noise immunity of the CLKRC is very high in Slow mode; however, it has slower settling time and requires more accurate data timing than in Fast mode. The registers associated with baseband filtering are: * * * * STSREG (see Register 2-1) RXCREG (see Register 2-7) BBFCREG (see Register 2-8) PMCREG (see Register 2-13) Preliminary DS70590C-page 57 MRF49XA 3.11 Data Quality Indicator can prevent the crystal oscillator from starting, or the DQI signal will not go high, even when the quality of the received signal is good. The DQI is the digital processing part of the radio connected to the demodulator and functions when the receiver is on. This reports the reception of an FSK modulated RF signal. The DQI parameter setting defines how clean the incoming data stream would be stated as good data (valid FSK signal). The DIO signal goes high if the internally calculated data quality value exceeds the DIO threshold parameter, for five consecutive data bits, for both high and low periods. The DIO is an extension of the DQI. When incoming data is detected, it uses the DQI signal, the clock recovery lock signal and the digital RSSI signal to determine if the incoming data is valid. The desired data rate and the acceptance criteria for valid data are user-programmable through the SPI port. The DIO has three modes of operation: Slow, Medium and Fast. Each mode is dependent on the signals it uses to determine the valid data and also on the number of incoming preamble bits present at the beginning of the packet. The DQI parameter (i.e., Data Quality Threshold Indicator (DQTI) bit) value is calculated using the formula given in Equation 3-1. EQUATION 3-1: The DIO can be disabled by the user so that only raw data from the comparator comes out, or it can be set to accept only a preset range of data rates and data quality. The DIO saves the battery power and the time for a host microcontroller because it will not wake-up the microcontroller unless there is valid data present. See Register 2-7 (RXCREG) for setup details. DQIpar = 4 x (Deviation - TX/RXoffset)/Bit Rate The DQI parameter in BBFCREG should be chosen according to the following rules: * The parameter should be > 4; otherwise, noise might be treated as a valid FSK signal * The maximum value is 7 The DIO signal is valid when using the internal receive FIFO or an external pin to capture baseband data. DIO can be multiplexed to pin 16 for external usage. Figure 3-10 depicts the DIO logic block diagram. Even during the on-time calculation in the Low Duty Cycle mode, depending on the data quality threshold indicator, the device needs to receive a few valid data bits before the DQI signal indicates good signal condition (see Register 2-8). Selecting a short on-time FIGURE 3-10: DIO LOGIC BLOCK DIAGRAM MUX DQI DIORT0 SEL0 DIORT1 CR_LOCK SEL1 FAST IN0 MEDIUM DRSSI IN1 SLOW DQI IN2 LOGIC HIGH DRSSI DQI CR_LOCK SET Y DIO IN3 CLR Q RXCEN R/S FLIP/FLOP CLR DS70590C-page 58 Preliminary (c) 2009-2011 Microchip Technology Inc. MRF49XA The DIO signal response time setting is configured through RXCREG and has the following modes of operation: * Default mode: The DIO is permanently connected to logic high. It always stays high independent of the receiving parameters. * Slow mode: The DIO signal goes high if the digital RSSI, DQI and Clock Recovery Lock (CR_LOCK) signals are present. It stays high until any of these signals are present and goes low when all three input signals are low. * Medium mode: The DIO signal is active when the CR_LOCK and the DRSSI or the DQI signals are high. It goes low when either the CR_LOCK becomes inactive or the DRSSI or DQI signals goes low. * Fast mode: The DIO signal follows the level of the DQI signal. The registers associated with DQI are: * STSREG (see Register 2-1) * RXCREG (see Register 2-7) * BBFCREG (see Register 2-8) 3.12 Programmable Synchronous Byte The internal synchronous pattern and the pattern length are user-programmable. The MRF49XA is configured to use a synchronous character to indicate the valid incoming data. The synchronous character selection is done through the FIFORSTREG. The character is divided into two bytes: SCL1 and SCL0. The SCL0 byte is user-configurable, whereas SCL1 is fixed to 2Dh and is non-programmable. The synchronous character can also be configured as a byte character or a word character. A byte character uses only SCL0, whereas the word character uses both SCL1 and SCL0. Since SCL0 is user-configurable, it is advantageous while operating under interferences and also while identifying the related transmitters. The registers associated with the programmable synchronous byte are: * FIFORSTREG (see Register 2-10) * PMCREG (see Register 2-13) (c) 2009-2011 Microchip Technology Inc. 3.13 Received Signal Strength Indicator The Received Signal Strength Indicator (RSSI) estimates the received signal power within the bandwidth of ISM channels. The MRF49XA provides both analog RSSI and digital RSSI. A digital RSSI output is provided to monitor the input signal level. The signal goes high if the received signal strength exceeds a given preprogrammed level. The digital RSSI threshold is programmable through RXCREG, and is read and monitored only through STSREG. When an incoming signal is stronger than the preprogrammed threshold, the digital RSSI bit in the STSREG is set. The settling time of digital RSSI depends on the external filter capacitor. The DRSSIT value is a 3-bit binary value ranging from 0 to 8. Table 3-2 shows the mapping between the DRSSIT value versus the received power level. The number of symbols to average can be changed by programming the DRSSIT bits (RXCREG<2:0>). The digital RSSI is basically a sensitive comparator behind an analog RSSI block. The comparator threshold can be set using the three bits and the comparator output can be read out through the Status Read register. The curve in Figure 3-11 shows the analog RSSI output voltage versus signal strength. The analog RSSI level is linear with input signal levels between -103 dBm and -73 dBm. The RSSIO pin in MRF49XA is used as an analog RSSI output and better results can be achieved by using this pin with a sensitive comparator. These bits can be set to indicate the incoming signal strength above a preset limit. The result enables or disables the DQDO bit (STSREG<7>). The RSSI threshold depends on the LNA gain and the real RSSI threshold can be calculated by using the formula as given in Equation 3-2. EQUATION 3-2: RSSIth = RSSIsetth + GLNA In Transmit mode, the ATRSSI bit (STSREG<8>) indicates that the antenna tuning circuit has detected a relatively strong RF signal. In Receive mode, the ATRSSI bit indicates that the incoming RF signal is above the preprogrammed digital RSSI threshold. Preliminary DS70590C-page 59 MRF49XA TABLE 3-2: DIGITAL RSSI THRESHOLD LEVELS RSSI Threshold DRSSIT2 DRSSIT1 DRSSIT0 Reserved 1 1 1 Reserved 1 1 0 -73 1 0 1 -79 1 0 0 -85 0 1 1 -91 0 1 0 -97 0 0 1 -103 0 0 0 FIGURE 3-11: INPUT POWER VS. ANALOG RSSI VOLTAGE 1.2 1 0.6 RSSI (V) 0.8 0.4 0.2 0 -112 -102 -92 -82 -72 -62 -52 -42 Input Power (dBm) 3.13.1 RELATIONSHIP BETWEEN RSSI AND CLOCK RECOVERY 3.13.2 The DIO signal response time setting is configured through RXCREG and has the following modes of operation: * * * * Normal mode Slow mode Medium mode Fast mode These operation modes are configurable through BBFCREG. In Medium mode, the DIO signal is active when the CR_LOCK and the DRSSI or the DQI signals are high. The DIO goes low when either the CR_LOCK turns inactive, or the DRSSI or DQI signals go low. For more details on DQI, see Section 3.11, Data Quality Indicator. DS70590C-page 60 RELATIONSHIP BETWEEN RSSI AND AFC The Keep Offset mode of automatic configuration of AFC (i.e., AUTOMS1 = 1, AUTOMS0 = 1) is recommended to be used when a receiver operates with only one transmitter. After a complete measuring cycle, the measured value is kept independent from the state of the DIO signal. In this mode, the DRSSI limit should be carefully selected to minimize the range hysteresis. The registers associated with RSSI are: * * * * STSREG (see Register 2-1) GENCREG (see Register 2-2) RXCREG (see Register 2-7) PMCREG (see Register 2-13) Preliminary (c) 2009-2011 Microchip Technology Inc. MRF49XA 3.14 Power Management The Power Management Configuration enables/disables the following functions: * * * * * * * * register Receiver Transmitter Baseband Circuit Synthesizer Crystal Oscillator Low Battery Detect Circuit Wake-up Timer Clock Output Clock Output: The CLKOEN bit, when set, disables the oscillator clock output. On device Reset or power-up, the clock output is enabled so that a processor can begin execution of any special setup sequences as required by the designer. See Register 2-16 (BCSREG) for programming details. Note: Figure 3-12 shows the functions that are enabled using PMCREG. Receiver: The RXCEN bit, when set, enables the entire receiver chain. The receiver chain consists of a baseband circuit, synthesizer and crystal oscillator. Transmitter: The TXCEN bit, when set, enables the entire transmit chain. The transmit chain consists of a power amplifier, synthesizer, oscillator and transmit register. When the transmit chain and Transmit register are enabled, any data in the Transmit register is shifted out and a transmission is started. Baseband Circuit: The BBCEN bit, when set, enables the baseband circuit. The baseband circuit, synthesizer and oscillator work together to demodulate and recover the data transmitted to the synthesizer (SYNEN bit). If baseband circuits are enabled, then the oscillator (OSCEN bit) must be enabled in order to receive data. The BBCEN bit can be disabled to reduce current consumption. Synthesizer: The SYNEN bit, when set, enables the synthesizer. The synthesizer is comprised of a PLL, oscillator and VCO for controlling the channel frequency. This bit must be enabled when either the transmitter or the receiver is enabled. The oscillator must also be enabled to provide the reference frequency for the PLL. On power-up, the synthesizer automatically performs the calibration. If there are significant changes in voltage or temperature, recalibration can be performed by disabling and re-enabling the synthesizer. If bit 0 is cleared, and with the clock output enabled, the oscillator continues to run even if the OSCEN bit is cleared. The device will not fully enter Sleep mode. The RF front end is comprised of the LNA and the mixer. The synthesizer block has two main components: the VCO and the PLL. The baseband section consists of a baseband amplifier, low-pass filter, limiter and I/Q demodulator. The synthesizer also has an internal start-up calibration procedure. If quick RX/TX switching is needed, leave this block on. Enabling the transmitter using the TXCEN bit (PMCREG<5>) will turn on the PA, and since the synthesizer is already up and running, the PA immediately produces the TX signal at the output. To decrease the TX/RX turnaround time, keep the baseband section on. Switching to Receive mode means disabling the PA and enabling the RF front end. Since the baseband block is already on, the internal start-up calibration is skipped, and thus, the turnaround time is shorter. The BBCEN, SYNEN and OSCEN bits are provided to optimize the TX to RX or RX to TX turnaround time. The crystal oscillator provides a reference signal to the RF synthesizer, baseband circuit and digital signal processor. If the receiver or the transmitter is frequently used, it is recommended to leave the oscillator running as the crystal might need a few milliseconds to start. The start timing mainly depends on the crystal parameters. Note: Leaving blocks unnecessarily turned on increases the current consumption, and thus, decreases the battery life. Crystal Oscillator: The OSCEN bit, when set, enables the oscillator circuit. The oscillator provides the reference signal to the synthesizer when setting the transmit or receive frequency of use. Low Battery Detect Circuit: The LBDEN bit, when set, enables the battery voltage detect circuit. The battery detector can be programmed to 32 different threshold levels. See Register 2-16 (BCSREG) for programming details. Wake-up Timer: The WUTEN bit, when set, enables the wake-up timer. See Register 2-14 (WTSREG) for details on programming the wake-up timer interval. (c) 2009-2011 Microchip Technology Inc. Preliminary DS70590C-page 61 MRF49XA From PMCREG, the following points are applicable when using the bit functionalities: * The chip enters Receive mode if both the TXCEN and RXCEN bits are set. * FSK/DATA/FSEL input is equipped with an internal pull-up resistor. To achieve minimum current consumption, do not pull this input to logic low in Sleep mode. * To enable the RF synthesizer, the crystal oscillator must be turned on. * To turn on the baseband circuits, the RF synthesizer and the crystal oscillator must be enabled. * Setting the RXCEN bit automatically turns on the crystal oscillator, synthesizer, baseband circuits and RF front end. * Setting the TXCEN bit automatically turns on the crystal oscillator, synthesizer and RF power amplifier. DS70590C-page 62 The clock tail and automatic crystal enable/disable features help in reducing the power consumption and are discussed in detail in Section 3.4, Crystal Oscillator and Clock Output. The registers associated with power management are: * * * * STSREG (see Register 2-1) GENCREG (see Register 2-2) RXCREG (see Register 2-7) PMCREG (see Register 2-13) Preliminary (c) 2009-2011 Microchip Technology Inc. (c) 2009-2011 Microchip Technology Inc. FIGURE 3-12: LOGIC CONNECTIONS BETWEEN POWER CONTROL BITS Enable Power Amplifier TXCEN Start TX Enable Power Amplifier Edge Detector LNA PA Enable RF Front End Clear TX Latch (If TX latch is used) Enable RF Synthesizer VCO and PLL Preliminary SYNEN Enable RF Synthesizer (Crystal Synthesizer must be ON) Start TX Clear TX Latch RXCEN TX Latch Enable RF Front End Enable Baseband Circuits Enable Crystal Oscillator Crystal Oscillator I/Q Demod. Enable Baseband Circuits BBCEN Digital Signal Processing DS70590C-page 63 Enable Crystal Oscillator OSCEN MRF49XA (RF Synthesizer must be ON) MRF49XA 3.15 Low Duty Cycle Mode In Low Duty Cycle mode, the receiver periodically wakes up for a short period and checks for the valid FSK transmission in progress. The FSK transmission is detected in the frequency range determined by CFSREG and the baseband filter bandwidth is determined by the RXCREG. The on time is automatically extended until the DQI indicates a good received signal condition. completely and all other interrupts are cleared. The device then returns to the Low-Power Consumption mode. Figure 3-13 depicts the Low-Power Duty Cycle mode sequence. The low duty cycle is calculated by using the DCMV (DCSREG<7:1>) and WTMV (WTSREG<7:0>) bits, as shown in Equation 3-3. The time cycle is determined by the WTSREG. EQUATION 3-3: The following facts need to be considered while calculating the duty cycle on-time: * The crystal oscillator, the synthesizer and the PLL need time to start (see Table 5-7). * Depending on the DQTI, the device needs to receive few valid data bits before the DQI signal indicates a good signal condition (see Register 2-8). Selecting a short on-time can prevent the crystal oscillator from starting, or the DQI signal will not go high even when the received signal has a good quality. The MRF49XA is normally configured to work in FIFO mode. However, when the device periodically wakes up from Sleep mode, it switches to the Receive mode. If valid FSK data is received, the device sends an interrupt to the microcontroller and continues filling the RXFIFO. On completion of transmission, the FIFO is read out FIGURE 3-13: DC = (DCMV<7:1> x 2 + 1)/WTMV<7:0> x 100% Note: The registers associated with Low Duty Cycle mode are: * * * * * * STSREG (see Register 2-1) GENCREG (see Register 2-2) RCXREG (see Register 2-7) BBFCREG (see Register 2-8) PMCREG (see Register 2-13) WTSREG (see Register 2-14) LOW-POWER DUTY CYCLE MODE SEQUENCE Start/Send Start/Send Packet A Transmitter In Duty Cycle mode, the RXCEN bit must be cleared and the WUTEN bit must be set in PMCREG. Packet A Packet A Packet B. B. B. B. Receiver TWAKE-up Receiving Packet A Packet A Packet B. DQI IRO Microcontroller Operation DS70590C-page 64 FIFO Read FIFO Read Preliminary (c) 2009-2011 Microchip Technology Inc. MRF49XA 3.16 Sleep, Wake-up and Battery Operations The advanced interrupt handler circuit is configured in the transmitter to reduce the power consumption. As mentioned, the Sleep mode is the lowest power consumption mode in which the clock and all functional blocks of the device are disabled. In case of any interrupt, the device wakes up, switches to Active mode and an interrupt signal generated on the IRO pin indicates the change in state to the host microcontroller. The source of the interrupt can be determined by reading the status word of the device (see Register 2-1). To reduce current consumption, the MRF49XA should be placed in the low-power consuming Sleep mode. In Sleep mode, the 10 MHz main oscillator is turned off, disabling the RF and baseband circuitry. Data is retained in the control and FIFO registers and the transceiver is accessible through the SPI port. The MRF49XA will not enter Sleep mode if any of the interrupt remains active, irrespective of the state of the OSCEN bit in the PMCREG. This way, the microcontroller can always have a clock signal to process the interrupt. To prevent high-current consumption, which results in shorter battery life, it is highly recommended to process and clear interrupts before entering Sleep mode. The functions which are not necessary should be turned off to avoid unwanted interrupts. The device has the ability to wake itself up from Sleep mode through a wake-up timer. The WTSREG sets the wake-up interval for the MRF49XA. After setting the wake-up interval, the WUTEN bit (PMCREG<1>) should be cleared and set at the end of every wake-up cycle. The Wake-up Duration Time (WUTIME) is calculated as shown in Equation 3-4. EQUATION 3-4: WUTIME = 1.03 x WTMV<7:0> x 2WTEV<4:0> + 0.5 ms where: WTMV<7:0> = Decimal Value between 0 to 255 WTEV<4:0> = Decimal Value between 0 to 29 Note: WUTIME is measured in ms. The Battery Threshold Detect feature is useful in monitoring the discharge-sensitive batteries, such as Lithium cells. The LBDEN bit (PMCREG<2>) is used to enable or disable the low battery detect feature. The BCSREG configures the following: * Output clock frequency * Low battery detect threshold The low battery threshold value is programmable from 2.2V to 3.8V and is calculated by using Equation 3-5. EQUATION 3-5: Threshold Voltage Value = 2.25 + 0.1 x (LBDVB<3:0>) To minimize the current consumption, the MRF49XA supports different power-saving modes, along with an integrated wake-up timer. Active mode can be reinitiated by the following ways: * By applying the wake-up events' negative logical pulse on INT pin * Wake-up timer time-out * Low supply voltage detection * On-chip FIFO filled up * On receiving a request through the serial interface To make the MRF49XA device enter into Sleep mode, certain control register values must be initialized. The sequence to program the control registers for entering into Sleep and Wake-up modes is as follows: For Sleep mode: 1. 2. 3. 4. Check the IRO bit status Read STSREG Configure GENCREG Configure PMCREG for oscillator and clock buffering where: LBDVB<3:0> is the Decimal Value from 0-15 When the battery level falls 50 mV below this value, the LBTD bit (STSREG<10>) is set, indicating that the battery level is below the programmed threshold. The registers associated with power-saving modes are: * * * * * * * STSREG (see Register 2-1) GENCREG (see Register 2-2) TXCREG (see Register 2-4) RXCREG (see Register 2-7) PMCREG (see Register 2-13) WTSREG (see Register 2-14) BCSREG (see Register 2-16) For Wake-up mode: 1. 2. 3. Enter in TX/RX mode or Enable crystal or Set the INT pin (c) 2009-2011 Microchip Technology Inc. Preliminary DS70590C-page 65 MRF49XA 3.17 TX Register Buffered Data Transmission In Data Transmission mode (enabled by the TXDEN bit (GENCREG<7>)), the TX data is clocked into one of the two 8-bit data registers. The transmitter starts to send the data from the first register (with the given bit rate) when the TXCEN bit (PMCREG<5>) is set. The initial value of the data registers (0xAA) can be used to generate preamble. During this mode, the SDO pin is monitored to check whether the register is ready (SDO is high) to receive the next byte from the microcontroller. The block diagrams of the Transmit register, before and during transmit, are shown in Figure 3-14 and Figure 3-15, respectively. FIGURE 3-14: The transmitter FSK modulation parameters are used for calculating the resulting output frequency, as shown in Equation 3-6. EQUATION 3-6: fFSKOUT = f0 + (-1)SIGN x (MB + 1) x (15 kHz) where: f0 is the Channel Center Frequency (see Register 2-6 for f0 calculation) MB is the 4-bit Binary Number (MODBW<3:0>) SIGN = MODPLY XOR FSK TX REGISTER BLOCK DIAGRAM (BEFORE TRANSMIT) TXCEN = 0 (Register Initial Fill-up) SDI 8-Bit Shift Register (Default: AAh) SDO 8-Bit Shift Register (Default: AAh) SDO TX_DATA CLK Serial Bus Data SCLK DS70590C-page 66 SDI CLK Preliminary (c) 2009-2011 Microchip Technology Inc. MRF49XA FIGURE 3-15: TX REGISTER BLOCK DIAGRAM (DURING TRANSMIT) TXCEN = 1 (During TX) SDI 8-Bit Shift Register SEL 10 Y Bit Rate SDO CLK 11 MUX SEL 1:8 Divider 10 SEL 8-Bit Shift Register 10 SCLK Y TX_DATA SDI Y CLK SDO 11 MUX 11 MUX Serial Bus Data (c) 2009-2011 Microchip Technology Inc. Note: The data registers' content is initialized by clearing the TXCEN bit. Preliminary DS70590C-page 67 MRF49XA The device transmit sequence should be performed as follows: 1. 2. Enable the TX register by setting TXDEN = 1. The TX register is automatically filled with 0xAAAA, which can be used to generate preamble. 3. Enable the transmitter by setting TXCEN = 1. 4. The synthesizer and the PLL turns on, calibrates itself and the PA is automatically enabled. 5. The TX data transmission starts. 6. On completion of byte transmission, the IRO pin goes high and the SDO pin goes low simultaneously. The IRO pulse shows that the first 8 bits (the first byte by default, 0xAA) have been transmitted. There are still 8 bits in the transmit register. 7. The microcontroller recognizes the interrupt and writes a data byte to the TXBREG. 8. Repeat steps 6 and 7 until the last data byte is reached. 9. Using the same method, transmit a dummy byte. The value of this dummy byte can be anything. 10. The next high-to-low transition on the IRO line (or low-to-high on the SDO pin) shows that the transmission of the data bytes has ended. The dummy byte is still in the TX latch. 11. Turn off the transmitter by setting the bit, TXCEN = 0. This event probably happens while the dummy byte is being transmitted. Since the dummy byte contains no useful information, this corruption will not cause any problem. 12. Clearing the TXDEN bit clears the register underrun interrupt. The IRO pin goes high and the SDO pin goes low. TABLE 3-3: Mode Transmit The transmit sequence is illustrated in Figure 3-16. For details on transmit pin function configuration, see Table 3-3. The TXDEN bit is in the GENCREG register and enables the Transmit Data register. The transmit sequence can be performed without sending a dummy byte (step 1), but after loading the last data byte to the transmit register, the PA turn off should be delayed for at least 16 bits time. The microcontroller clock source (if the clock is not supplied by the transceiver) should be stable enough over temperature and voltage ranges to ensure this minimum delay under all operating circumstances. When the dummy byte is used, the whole process is driven by interrupts. Changing the TX data rate has no effect on the algorithm and no accurate delay measurement is needed. Figure 3-17 shows the multi-byte transmit write sequence. The registers associated with transmission are: * * * * * STSREG (see Register 2-1) GENCREG (see Register 2-2) TXCREG (see Register 2-4) TXBREG (see Register 2-5) PMCREG (see Register 2-13) TRANSMIT PIN FUNCTION VS. OPERATION MODE Bit Setting Function Pin 6 Pin 7 TXDEN = 0 Internal TX Data register disabled TX data input Not used TXDEN = 1 Internal TX Data register enabled FSEL input (TX Data register can be accessed) DS70590C-page 68 Preliminary (c) 2009-2011 Microchip Technology Inc. MRF49XA FIGURE 3-16: TX REGISTER USAGE Do not switch the TXCEN off here, because the TX Byte 1 is not transmitted out, it is only stored in the internal register Enabling the transmitter preloads the TX latch with 0xAAAA SPI Commands GENCREG (CS, SCK, SDI) TXDEN = 1 TX Latch TX Latch TX Byte 1 Dummy TX Byte PMCREG TXCEN = 1 PMCREG TXCEN = 0 GENCREG TXDEN = 0 TXCEN Enable Synthesizer/PA Synt. PA Ttx_xtal_on(1) 0xAA TX Data 0xAA TX Byte1 Fraction of the dummy byte IRO SDO(2) Note 1: Ttx_xtal_on is the start-up time of PLL + PA with a running crystal oscillator. 2: SDO is a tri-state of CS. FIGURE 3-17: MULTIPLE BYTE WRITE WITH TRANSMIT REGISTER CS SCK TX BYTE 2 TX BYTE 1 SDI TX BYTE n Transmit Register Write SDO (Register interrupt in TX mode*) * The device is in Transmit (TX) mode when the RXCEN bit is cleared using the PMCREG. (c) 2009-2011 Microchip Technology Inc. Preliminary DS70590C-page 69 MRF49XA 3.18 RX FIFO Buffered Data Read the device on the rising edge of the clock on the SCK pin. The serial interface is initialized every time if the CS signal is high. Figure 3-18 shows a simple receiver FIFO read over SPI lines. In the Receive Operating mode, the incoming data is clocked into a 16-bit FIFO buffer. The receive pin function configuration required for the FIFO operation is given in Table 3-4. The FIFOEN bit is in the GENCREG register and enables the receive FIFO. The receiver starts to fill the FIFO when the FINTDIO bit and the synchronous pattern recognition circuit indicates the potential real incoming data. This prevents the FIFO from being filled with noise and avoids the overloading on the external microcontroller. In general, MRF49XA registers are read only. The RXFIFO and the chip status can be read. During write only appropriate byte is written to the desired register. Hence it is not desired to read/write all registers and there is no way reading back any of the other registers. To test the SPI interface lines, the best is to set the LBD (Low Battery Detector) threshold below the actual VDD and the device must generate an interrupt. The internal synchronous pattern and the pattern length are user-programmable. If the Chip Select (CS) pin is low, the data bits on the SDI pin are shifted into FIGURE 3-18: RECEIVER FIFO READ CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK SDI Received Bits Out SDO TXRXFIFO MSB LSB (TX/RX mode) Note: The transceiver is in Receive (RX) mode when the RXCEN bit is set using the PMCREG . DS70590C-page 70 Preliminary (c) 2009-2011 Microchip Technology Inc. MRF49XA 3.18.1 INTERRUPT MODE 3.18.2 The user can define the FIFO interrupt level (the number of received bits) which generates the FINT when the level is exceeded. In this case, the Status bits report the changed FIFO status. POLLING MODE When the FSEL signal is low, the FIFO output is connected directly to the SDO pin and its contents are clocked out by the SCK pin. Set the FIFO interrupt level to 1. In this case, as long as FINT indicates received bits in the FIFO, the microcontroller continues to take the bits away. When FINT goes low, no more bits need to be taken. An SPI read command (Receiver FIFO Read Command) is also available to read out the contents of the FIFO. See Figure 3-19 for a simple receiver FIFO read, in Polling mode, on SPI lines. TABLE 3-4: Mode Receive FIGURE 3-19: RECEIVE PIN FUNCTION VS. OPERATION MODE Bit Setting Function Pin 6 Pin 7 FIFOEN = 0 Receiver FIFO Disabled RX Data Output RX Data Clock Output FIFOEN = 1 Receiver FIFO Enabled FSEL Input (RX data FIFO can be accessed) FINT Output FIFO READ EXAMPLE WITH FINT POLLING CS 0 1 2 3 4 SCK FSEL FIFO Read Out SDO FIFO OUT FO + 1 FO + 2 FO + 3 FO + 4 FINT The registers associated with reception are: Note: During FIFO access, fSCK cannot be higher than fref/4, where fref is the crystal oscillator frequency. If the duty cycle of the clock signal is not 50%, the shorter period of the clock pulse should be at least 2/fref. (c) 2009-2011 Microchip Technology Inc. * * * * * STSREG (see Register 2-1) GENCREG (see Register 2-2) RXCREG (see Register 2-7) FIFORSTREG (see Register 2-10) PMCREG (see Register 2-13) Preliminary DS70590C-page 71 MRF49XA 3.19 RX-TX Frequency Alignment Method The RX-TX frequency offset occurs due to the differences in the actual reference frequency. To minimize this error, the same crystal type and the same PCB layout should be used for the crystal placement on the RX and TX PCBs. Also, see Section 3.6, Crystal Selection Guidelines. To verify the possible RX-TX offset, it is recommended to measure the CLK output of both transceivers with a high level of accuracy. Do not measure the output at the RFXTL pin as the measurement process itself might change the reference frequency. As the carrier frequencies are derived from the reference frequency, having identical reference frequencies, and nominal frequency settings at the TX and RX side, there should be no offset if the CLK signals have identical frequencies. The actual RX-TX offset can be monitored by using the AFC status data included in the STSREG of the receiver. By reading out the STSREG, the actual measured offset frequency can be reported. In order to get accurate values, the AFC has to be disabled during the read by clearing the FOFEN bit in AFCCREG. The registers associated with RX-TX alignment procedures are: * * * * STSREG (see Register 2-1) AFCCREG (see Register 2-3) RXCREG (see Register 2-7) PMCREG (see Register 2-13) The crystal oscillator load capacitor bank value is to fine-tune the oscillator and minimize the offset. So the process is to measure the clock output and parallel change the value to minimize the offset. DS70590C-page 72 Preliminary (c) 2009-2011 Microchip Technology Inc. MRF49XA 4.0 APPLICATION DETAILS The application circuit of MRF49XA with a balun circuit is shown in Figure 4-1. FIGURE 4-1: APPLICATION CIRCUIT VDD C1 2 .2 u F IN T /D IO * RC7 SDI RC6 SCK RC5 CS RC4 RC3 IR O RC2 F S K /D A T A /F S E L * RC1 R C L K O U T /F C A P /F IN T * RC0 C LK O U T* OSC1 _____ M C LR 1 16 2 15 3 14 4 5 MRF49XA P IC (R) M C U SDO C3 0 .0 1 u F C2 (see Table 2-2) C4* 2 .2 n F 13 B a lu n 12 6 11 7 10 8 9 50 O hm Loop A n te n n a RESET* X1 10 M H z * C o n n e c tio n s a re o p tio n a l. 4.1 Antenna/Balun A balun circuit for a 50 antenna is shown in Figure 4-2. If low tolerance components (i.e., 5%) are used with an appropriate ground, the impedance remains close to the 50 measurement. FIGURE 4-2: BALUN CIRCUIT +3.3V L1 C5 C6 J1 50 ANT RFN L2 L3 RFP C7 (c) 2009-2011 Microchip Technology Inc. Freq. L1 868 MHz 390 nH 33 nH 47 nH 2.7 pF 68 pF 5.1 pF 433 MHz 100 nH 8.2 nH 22 nH 1.2 pF 27 pF 2.7 pF 915 MHz 100 nH 8.2 nH 22 nH 1.2 pF 27 pF 2.7 pF Preliminary L2 L3 C5 C6 C7 DS70590C-page 73 MRF49XA 4.2 Antenna Design Considerations The MRF49XA is designed to drive a differential output, such as a dipole antenna or a loop antenna. The loop antenna is ideally suited for applications where compact size is required. The dipole is typically not a good option for compact designs due to its inherent size at resonance, and its space requirements around the ground plane, to be an efficient antenna. A monopole antenna can be used, along with a balun, or by using the matching circuit. TABLE 4-1: RF Transmitter Matching The RF pins are of high impedance and differential value. The optimum differential load for the RF port at a given frequency band is shown in Table 4-1. These load values in the table are expected by the RF port pins to have as an antenna load for maximum power transfer. Antennas that are suited for such values would be a Loop, Dipole and Folded Dipole. For all antenna applications, either a bias, choke inductor or coils must be included during transmission since the RF outputs are of open-collector type. FREQUENCY BAND - ANTENNA ADMITTANCE/IMPEDANCE MRF49XA 4.4 4.3 Admittance (ms) Impedance () 433 MHz 2-j5.9 52+j152 62 868 MHz 1.2-j11.9 7.8+j83 15.4 915 MHz 1.49-j12.8 9+j77 13.6 General PCB Layout Design The guidelines in this section help the users in high-frequency PCB layout design. The printed circuit board is usually comprised of two or four basic FR4 layers. The two-layer printed circuit board has mixed signal/power/RF and common ground routed in both the layers. FIGURE 4-3: Inductance (nH) The four-layer printed circuit board is comprised of the following layers: * * * * Signal layout RF ground Power line routing Common ground The four-layer PCB is shown in Figure 4-4. TWO BASIC COPPER FR4 LAYERS Signal/Power/RF and Common Ground Dielectric Constant = 4.5 Signal/Power/RF and Common Ground FIGURE 4-4: FOUR BASIC COPPER FR4 LAYERS Signal Layout Dielectric Constant = 4.5 RF Ground Dielectric Constant = 4.5 Power Line Routing Dielectric Constant = 4.5 Ground DS70590C-page 74 Preliminary (c) 2009-2011 Microchip Technology Inc. MRF49XA The following guidelines explain the requirements of the above mentioned layers. * It is important to keep the original PCB thickness, since any change will affect antenna performance (see total thickness of dielectric) or microstrip lines' characteristic impedance. * For good transmit and receive performance, the trace lengths at RF pins must be kept as short as possible. Using small, surface mount components (in 0402/0603 package) yields good performance and keeps the RF circuit small. RF connections should be short and direct. * Except for the antenna layout, avoid sharp corners since they can act as an antenna. Round corners will eliminate possible future EMI problems. * Digital lines are prone to be very noisy when handling periodic waveforms and fast clock/switching rates. Avoid RF signal layout close to any of the digital lines. * A VIA filled ground patch underneath the IC transceiver is mandatory. * Power supply must be distributed to each pin in a star topology and low-ESR capacitors must be placed at each pin for proper decoupling noise. * Thorough decoupling on each power pin is beneficial for reducing in-band transceiver noise, particularly when this noise degrades performance. Usually, low value caps (27 pF - 47 pF) combined with large value caps (100 nF) will cover a large spectrum of frequency. * Passive component (inductors) should be in the high-frequency category and the Self Resonant Frequency (SRF) should be at least two times higher than the operating frequency. (c) 2009-2011 Microchip Technology Inc. * The additional trace length affects the crystal oscillator by adding parasitic capacitance to the overall load of the crystal. To minimize this, place the crystal as close as possible to the RF device. * Setting short and direct connections between the components on board minimizes the effects of "frequency pulling" that might be introduced by stray capacitance. It even allows the internal load capacitance of the chip to be more effective in properly loading the crystal oscillator circuit. * Long run tracks of clock signal may radiate and cause interference. This can degrade receiver performance and add harmonics or unwanted modulation to the transmitter. * Keep clock connections as short as possible and surround the clock trace with an adjacent ground plane pour. Pouring helps in reducing any radiation or crosstalk due to long run traces of the clock signal. * Low value decoupling capacitors, typically 0.01 F - 0.1 F, should be placed for VDD of the chip and for bias points of the RF circuit. * High value decoupling capacitors, typically 2.2 F - 10 F, should be placed at the point where power is applied to the PCB. * Power supply bypassing is necessary. Poor bypassing contributes to conducted interference which can cause noise and spurious signals to couple into the RF sections, significantly reducing performance. Preliminary DS70590C-page 75 MRF49XA 4.5 MRF49XA Schematic and Bill of Materials 4.5.1 SCHEMATIC FIGURE 4-5: MRF49XA SCHEMATIC +3.3V C1 RSSIO C2 0.01 uF C3 2.2 uF 6.3V C4 1000 pF +3.3V INT/DIO L1 U1 MRF49XA SDI SCK __ CS SDO __ IRO __ FSEL FINT TP1 CLK TP2 GND 1 2 3 4 5 6 7 89 C5 C6 J1 50 ANT __ 16 SDI INT/DIO 15 SCK RSSIO __ 14 VDD CS 13 SDO RFN __ 12 IRO RFP ___ 11 FSK/DATA/FSEL VSS ____ 10 RCLK OUT/FCAP/FINT RESET CLKOUT RFXTL/EXTREF L2 L3 C7 X1 10 MHz ___ RESET Freq. DS70590C-page 76 C1 L1 L2 390 nH 33 nH L3 C5 C6 47 nH 2.7 pF 68 pF C7 433 MHz 220 pF 868 MHz 47 pF 100 nH 8.2 nH 22 nH 1.2 pF 27 pF 2.7 pF 915 MHz 33 pF 100 nH 8.2 nH 22 nH 1.2 pF 27 pF 2.7 pF Preliminary 5.1 pF (c) 2009-2011 Microchip Technology Inc. MRF49XA 4.5.2 BILL OF MATERIALS TABLE 4-2: MRF49XA: 433 MHz BILL OF MATERIALS Designator Value C1 200 pF Capacitor, Ceramic, 50V, C0G, SMT 0603 Murata GRM1885C1H201JA01D C5 2.7 pF Capacitor, Ceramic, 50V, C0G, SMT 0603 Murata GRM1885C1H2R7CZ01D C6 68 pF Capacitor, Ceramic, 50V, C0G, SMT 0603 Murata GRM1885C1H680JA01D C7 5.1 pF Capacitor, Ceramic, 50V, C0G, SMT 0603 Murata GRM1885C1H5R1DZ01D L1 390 nH Inductor, Ceramic, 5%, SMT 0603 Murata LQW18ANR39J00D L2 33 nH Inductor, Multilayer, 5%, SMT 0603 TDK Corporation MLG1608B33NJ L3 47 nH Inductor, Multilayer, 5%, SMT 0603 TDK Corporation MLG1608B47NJ C4 1000 pF Capacitor, Ceramic, 50V, 10%, SMT 0603, X7R Murata GRM188R71H102KA01D C2 10000 pF Capacitor, Ceramic, 50V, 10%, SMT 0603, X7R Murata GRM188R71H103KA01D Kemet T491A225K010AT C3 Description 2.2 F, 10V Capacitor, Tantalum, 10%, SMT 3216-18 (A) U1 -- X1 10 MHz Manufacturer Manufacturer PN MRF49XA Transceiver Microchip MRF49XA-I/ST Crystal, 10 ppm, 10 pF, SMT 5 x 3.2 mm Abracon ABM3B-10.000MHZ-12-R8 0-B-1-U-T (c) 2009-2011 Microchip Technology Inc. Preliminary DS70590C-page 77 MRF49XA TABLE 4-3: MRF49XA: 868/915 MHz BILL OF MATERIALS Designator Value C1 33 pF Capacitor, Ceramic, 50V, C0G, SMT 0603 Murata GRM1885C1H330JA01D C5 1.2 pF Capacitor, Ceramic, 50V, C0G, SMT 0603 Murata GRM1885C1H1R2CZ01D C6 27 pF Capacitor, Ceramic, 50V, C0G, SMT 0603 Murata GRM1885C1H270JA01D C7 2.7 pF Capacitor, Ceramic, 50V, C0G, SMT 0603 Murata GRM1885C1H2R7CZ01D L1 100 nH Inductor, Multilayer, 5%, SMT 0603 L2 8.2 nH Inductor, Multilayer, 5%, SMT 0603 TDK Corporation MLG1608B8N2D L3 22 nH Inductor, Multilayer, 5%, SMT 0603 TDK Corporation MLG1608B22NJ C4 1000 pF Capacitor, Ceramic, 50V, 10%, SMT 0603, X7R Murata GRM188R71H102KA01D C2 10000 pF Capacitor, Ceramic, 50V, 10%, SMT 0603, X7R Murata GRM188R71H103KA01D Kemet T491A225K010AT C3 2.2 F, 10V Capacitor, Tantalum, 10%, SMT 3216-18 (A) U1 -- X1 10 MHz DS70590C-page 78 Description Manufacturer Manufacturer PN TDK Corporation MLG1608BR10J MRF49XA Transceiver Microchip MRF49XA-I/ST Crystal, 10 ppm, 10 pF, SMT 5 x 3.2 mm Abracon ABM3B-10.000MHZ-12-R80B-1-U-T Preliminary (c) 2009-2011 Microchip Technology Inc. MRF49XA 5.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings() Temperature under bias ........................................................................................................................... -40C to +85C Storage temperature .............................................................................................................................. -55C to +125C Lead temperature (soldering, max 10s) ............................................................................................................... +260C Voltage on VDD with respect to VSS ............................................................................................................... -0.3V to 6V Voltage on any combined digital and analog pin with respect to VSS (except RFP, RFN and VDD) ........................................................................................................... -0.3V to (VDD + 0.3V) Voltage on open-collector outputs (RFP, RFN)(1) ........................................................................... -0.5V to (VDD + 1.5V) Input current into pin (except VDD and VSS).......................................................................................... -25 mA to 25 mA Electrostatic discharge with human body model .................................................................................................... 1000V Note: At maximum, voltage on RFP and RFN cannot be higher than 7V. NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. (c) 2009-2011 Microchip Technology Inc. Preliminary DS70590C-page 79 MRF49XA TABLE 5-1: RECOMMENDED OPERATING CONDITIONS Parameters Min Typ Max Unit Operating Temperature -40 -- +85 C Supply Voltage for RF, Analog and Digital Circuits 2.2 -- 3.8 V Supply Voltage for Digital I/O 2.2 3.3 3.8 V DC Voltage on Open-Collector Outputs (RFP, RFN)(1,2) VDD-1.5 -- VDD+1.5 V AC Peak Voltage on Open-Collector Outputs (RFP, RFN)(1) VDD-1.5 -- VDD+1.5 V Note 1: 2: At minimum, VDD - 1.5V cannot be lower than 1.2V. At maximum, VDD + 1.5V cannot be higher than 5.5V. CURRENT CONSUMPTION(1) TABLE 5-2: Chip mode Condition Min Typ Max Unit Sleep Sleep clock disabled, all blocks disabled -- 0.3 1 A Idle Oscillator and baseband enabled, clock output disabled -- 0.6 1.2 mA TX TX RX Power output - 0 dBm, 50 load, 433 MHz -- 15 -- mA 868 MHz -- 16 -- mA 915 MHz -- 17 -- mA At maximum output power, 433 MHz -- 22 26 mA 868 MHz -- 23 27 mA 915 MHz -- 24 28 mA 433 MHz -- 11 13 mA 868 MHz -- 12 14 mA -- 13 15 mA Low Battery Voltage Detector Current Consumption 915 MHz -- -- 0.5 1.7 A Wake-up Timer Current Consumption -- -- 1.5 3.5 A Note 1: Typical Values: TA = 25C, VDD = 3.3V. I/O PIN INPUT SPECIFICATIONS(1) TABLE 5-3: Symbol Characteristic VIL Input Low Voltage VIH Input High Voltage (2) Condition Min Typ Max Unit -- -- -- 0.3xVDD V -- 0.7xVDD -- -- V IIL Input Low Leakage Current VIL = 0V -1 -- 1 A IIH Input High Leakage Current VIH = VDD, VDD = 3.8V -1 -- 1 A VOL Digital Low Output Voltage lOL = 2 mA -- -- 0.4 V VOH Digital Low Output IOH = -2 mA VDD-0.4 -- -- V VLBTD Low Battery Threshold Detect Programmable in 0.1V steps 2.25 -- 3.75 V Note 1: 2: Typical Values: TA = 25C, VDD = 3.3V. Negative current is defined as the current sourced by the pin. DS70590C-page 80 Preliminary (c) 2009-2011 Microchip Technology Inc. MRF49XA TABLE 5-4: RECEIVER AC CHARACTERISTICS(1) Parameters Receiver Sensitivity Condition Min Typ Max Unit (2) -- -112 -- dBm (2) -- -110 -- dBm (2) 915 MHz band -- -109 -- dBm LNA: High Gain 0 -- -- dBm 433 MHz band 868 MHz band Maximum RF Input Power RF Input Capacitance -- -- 1 -- pF Receiver Spurious Emission -- -- -- -60 dBm mode 0 -- 67 -- kHz Mode 1 -- 134 -- kHz Mode 2 -- 200 -- kHz Mode 3 -- 270 -- kHz Mode 4 -- 340 -- kHz Receiver BW Mode 5 RSSI Range RSSI Error -- 400 -- kHz -- -- 46 -- dB -- -- 6 -- dB RSSI Power Supply Dependency When input signal level is lower than -54 dBm and greater than -100 dBm -- +35 -- mV/V Filter Capacitor for Analog RSSI -- 1 -- -- nF RSSI Programmable Level Steps -- -- 6 -- dB Digital RSSI Response Time Until the RSSI signal goes high after the input signal exceeds the preprogrammed limit, CARRSI = 4.7 nF -- 500 -- s Input IP3 In band interferers in high bands (868 MHz, 915 MHz) -- -21 -- dBm IIP3 (LNA - 6 dB gain) In band interferers in low band (433 MHz) -- -15 -- dBm IIP3 (LNA - 6 dB gain) Out of band interferers, l f-fO l > 4 MHz -- -12 -- dBm FSK Bit Rate With internal digital filters supported by design 0.6 -- 115.2 kbps FSK Bit Rate With internal analog filters supported by design -- -- 256 kbps AFC Locking Range ffsk: FSK deviation in the received signal -- 0.8 - ffsk -- -- Note 1: 2: Typical Values: TA = 25C, VDD = 3.3V. BER = 10E - 3, BW = 67 kHz, f = 30 kHz, Baud Rate = 1.2 kbps, digital filter with AFC disabled. (c) 2009-2011 Microchip Technology Inc. Preliminary DS70590C-page 81 MRF49XA TABLE 5-5: TRANSMITTER AC CHARACTERISTICS(1) Parameters RF Carrier Frequency Maximum RF Output Power Condition Min Typ Max Unit 433 MHz band, 2.5 kHz resolution 430.24 -- 439.75 MHz 868 MHz band, 5.0 kHz resolution 860.48 -- 879.51 MHz 915 MHz band, 7.5 kHz resolution 900.72 -- 929.27 MHz 433 MHz @ 50 load -- 7 -- dBm 868 MHz @ 50 load -- 5 -- dBm 915 MHz @ 50 load -- 5 -- dBm RF Output Power Control Range In steps of 8 Pmax - 17.5 -- Pmax dBm TX Gain Control Resolution Programmed in 8 steps -- 2.5 -- dB Harmonic Suppression At maximum power, 50 load -- -- -35 dBc Open-Collector Output DC Current Programmable 0.5 -- 6 mA Spurious Emission | f-fsp | > 1 MHz At maximum power, 50 load -- -- -55 dBc Output Capacitance (Set by the Automatic Antenna Tuning Circuit) 433 MHz band 2 2.6 3.2 pF 868 MHz band 2.1 2.7 3.3 pF 915 MHz band 2.1 2.7 3.3 pF Quality Factor of the Output Capacitance 433 MHz band 13 15 17 -- 868 MHz band 8 10 12 -- 915 MHz band 8 10 12 -- 100 kHz from carrier -- -80 -- dBc/Hz 1 MHz from carrier -- -103 -- dBc/Hz Output Phase Noise FSK Bit Rate Internal TX Data register -- -- 172 kbps FSK Bit Rate TX data connected to the FSK input -- -- 256 kbps FSK Frequency Deviation Programmable in 15 kHz steps 15 -- 240 kHz Note 1: Typical Values: TA = 25C, VDD = 3.3V. TABLE 5-6: PLL PARAMETERS AC CHARACTERISTICS(1) Parameters Condition/Note Min Typ Max Unit PLL Reference Frequency Crystal related timing and frequency parameters change according to the PLL reference frequency 9 10 11 MHz PLL Lock Time Frequency error <1 kHz after 10 MHz step -- 30 -- s PLL Start-up Time With a running crystal oscillator and based on the design -- 200 300 s Note 1: Typical Values: TA = 25C, VDD = 3.3V. DS70590C-page 82 Preliminary (c) 2009-2011 Microchip Technology Inc. MRF49XA TABLE 5-7: OTHER TIMING PARAMETERS AC CHARACTERISTICS(1) Parameters Condition Min Typ Max Unit Transmitter Switch On Time Synthesizer off, crystal oscillator on with 10 MHz step -- 250 -- s Receiver Switch On Time Synthesizer off, crystal oscillator on with 10 MHz step -- 250 -- s Transmitter to Receiver Switch Time Synthesizer and crystal oscillator on during TX/RX change with 10 MHz step -- 150 -- s Receiver to Transmitter Switch Time Synthesizer and crystal oscillator on during RX/TX change with 10 MHz step -- 150 -- s Crystal Load Capacitance (See Crystal Selection Guide) Programmable in 0.5 pF steps, tolerance 10% 8.5 -- 16 pF Crystal Oscillator Start-up Time Default capacitance bank setting, crystal ESR <50. Crystal load capacitance = 16 pF.(2) -- 2 7 ms Internal POR Time-out After VDD has reached 90% of the final value(3) -- -- 100 ms Wake-up Timer Clock Accuracy Crystal oscillator must be enabled to ensure proper calibration at the start-up(2) -- 10 -- % -- -- -- 2 pF -- -- 10 ns Digital Input Capacitance Digital Output Rise/Fall Time Note 1: 2: 3: 15 pF pure capacitive load Typical Values: TA = 25C, VDD = 3.3V. The crystal oscillator start-up time depends on the capacitance seen by the oscillator. Low capacitance and low-ESR crystal are recommended with low parasitic PCB layout design. During the Power-on Reset period, commands are not accepted by the chip. In case of Software Reset (see WTSREG (Register 2-14)), the Reset time-out is typically 0.25 ms. (c) 2009-2011 Microchip Technology Inc. Preliminary DS70590C-page 83 MRF49XA 5.1 Timing Specification and Diagram TABLE 5-8: SPI TIMING SPECIFICATION Symbol Parameter Minimum Value (ns) tCH Clock High Time 25 tCL Clock Low Time 25 tSS Select Setup Time (CS falling edge to SCK rising edge) 10 tSH Select Hold Time (SCK falling edge to CS rising edge) 10 tSHI Select High Time 25 tDS Data Setup Time (SDI transition to SCK rising edge) 5 tDH Data Hold Time (SCK rising edge to SDI transition) 5 tOD Data Delay Time 10 FIGURE 5-1: SPI TIMING DIAGRAM tSS tSHI CS tCD tCH tSH tCL SCK tDS SDI SDO tDH BIT 15 TXRXFIFO BIT 14 POR BIT 13 BIT 8 TXOWRXOF BIT 7 BIT 1 DQDO OFFSB(0) BIT 0 FIFO OUT ATRSSI DS70590C-page 84 Preliminary (c) 2009-2011 Microchip Technology Inc. MRF49XA 5.2 Typical Performance Characteristics CHANNEL SELECTIVITY AND BLOCKING(1,2) FIGURE 5-2: 80 70 Suppression (dB) 60 50 40 30 20 434 MHz 10 868 MHz ETSI 0 0 1 2 3 4 5 6 7 8 9 10 11 12 CW Interferer Offset with respect to Carrier (MHz) Note 1: 2: LNA gain maximum, filter bandwidth 67 kHz, data rate 9.6 kbps, AFC switched off, FSK deviation 45 kHz, VDD = 2.7V. The ETSI limit given in the figure is drawn by taking -106 dBm at 9.6 kbps typical sensitivity into account and corresponds to receiver class 2 requirements. (c) 2009-2011 Microchip Technology Inc. Preliminary DS70590C-page 85 MRF49XA FIGURE 5-3: BER CURVES IN 433 MHz BAND BER Curves in 433 MHz Band 1.0E+00 1.0E-01 BER 1.0E-02 1.0E-03 1.0E-04 1.2k 9.6k 19.2k 115.2k 1.0E-05 1.0E-06 -120 -115 -110 -105 -100 -95 -90 Input Power (dBm) FIGURE 5-4: BER CURVES IN 868 MHz BAND BER Curves in 868 MHz Band 1.0E+00 1.0E-01 BER 1.0E-02 1.0E-03 1.0E-04 1.2k 9.6k 19.2k 115.2k 1.0E-05 1.0E-06 -115 -110 -105 -100 -95 -90 -85 Input Power (dBm) DS70590C-page 86 Preliminary (c) 2009-2011 Microchip Technology Inc. MRF49XA Table 5-9 shows the optimal receiver BBBW and transmitter deviation frequency (fFSK) settings for different data rates, considering no TX/RX offset frequency. If the TX/RX offset (for example, due to crystal tolerances) has to be taken into account, increase the BW accordingly. TABLE 5-9: Baud Rate RX BW AND TX DEVIATION FREQUENCY FOR DIFFERENT BAUD RATES 1.2 kbps 2.4 kbps 4.8 kbps 9.6 kbps 19.2 kbps 38.4 kbps 57.6 kbps 115.2 kbps BW in kHz BW - 67 BW - 67 BW - 67 BW - 67 BW - 67 BW - 134 BW - 134 BW - 200 TX in kHz fFSK - 45 fFSK - 45 fFSK - 45 fFSK - 45 fFSK - 45 fFSK - 90 fFSK - 90 fFSK - 120 (c) 2009-2011 Microchip Technology Inc. Preliminary DS70590C-page 87 MRF49XA FIGURE 5-5: RECEIVER SENSITIVITY OVER AMBIENT TEMPERATURE (433 MHz, 2.4 kbps, fFSK: 45 kHz, BW: 67 kHz) Receiver Sensitivity over Ambient Temperature for 433 MHz -100 Power Level (dBm) -103 2.2V -106 2.7V 3.3V -109 3.8V -112 -115 -50 -25 0 25 50 75 100 Temperature (C) FIGURE 5-6: RECEIVER SENSITIVITY OVER AMBIENT TEMPERATURE (868 MHz, 2.4 kbps, fFSK: 45 kHz, BW: 67 kHz) Receiver Sensitivity over Ambient Temperature for 868 MHz -100 Power Level (dBm) -103 2.2V -106 2.7V 3.3V -109 3.8V -112 -115 -50 -25 0 25 50 75 100 Temperature (C) DS70590C-page 88 Preliminary (c) 2009-2011 Microchip Technology Inc. MRF49XA 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 16-Lead TSSOP Example XXXXXXXX YYWW NNN Legend: XX...X Y YY WW NNN e3 * Note: 49XA/ST e3 0910 017 Product-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event, the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. (c) 2009-2011 Microchip Technology Inc. Preliminary DS70590C-page 89 MRF49XA 6.2 Package Details This section provides the technical details of the packages. 16-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm Body [TSSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70590C-page 90 Preliminary (c) 2009-2011 Microchip Technology Inc. MRF49XA 16-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm Body [TSSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging (c) 2009-2011 Microchip Technology Inc. Preliminary DS70590C-page 91 MRF49XA 16-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm Body [TSSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70590C-page 92 Preliminary (c) 2009-2011 Microchip Technology Inc. MRF49XA APPENDIX A: READ SEQUENCE AND PACKET STRUCTURES Figure 1 shows the STSREG read sequence with FIFO read as an example. FIGURE A-1: STSREG READ SEQUENCE CS 1 0 2 3 4 5 6 7 8 9 11 10 12 14 13 15 17 16 SCK Command SDI Interrupt Bits Out (1)(2)(3) SDO Status Bits Out (1,2,3) POR TXRXFIFO TXOWR XOF FIFO Out (1,2,3) WUTI NT LCE XINT LBTD FIFO EM ATRS SI DQDO CLKRL AFCCT OFFSV OFFSB <3> OFFSB <2> OFFSB <1> OFFSB <0> FO FO+1 FO+2 (Sign) (Latched) (Latched) (Latched) (Latched) (Latched) Note: 1. Applicable when the RXCEN bit is set using the PMCREG. 2. Applicable when the RXCEN bit is cleared using the PMCREG. 3. These bits are internally latched and the other bits are only multiplexed out. TABLE A-1: Length Minimum Length RECOMMENDED FIFO PACKET STRUCTURES Preamble Synchronous Word/Network ID Payload CRC 4-8 bits (0x0A or 0x05) 0xD4 (programmable) -- 4-bit-1 byte 0x2DD4 (D4 is programmable) -- 2 bytes Recommended Length 8-12 bits (e.g., 0xAA or 0x55) (c) 2009-2011 Microchip Technology Inc. Preliminary DS70590C-page 93 MRF49XA NOTES: DS70590C-page 94 Preliminary (c) 2009-2011 Microchip Technology Inc. MRF49XA APPENDIX B: REVISION HISTORY Revision A (March 2009) This is the initial released version of this document. Revision B (June 2009) Major updates are done throughout the document. Revision C (November 2011) Minor corrections such as figures, language and formatting updates are incorporated throughout the document. (c) 2009-2011 Microchip Technology Inc. Preliminary DS70590C-page 95 MRF49XA NOTES: DS70590C-page 96 Preliminary (c) 2009-2011 Microchip Technology Inc. MRF49XA INDEX F A Absolute Maximum Ratings ................................................ 79 AC Characteristics Other Timing Parameters............................................ 83 PLL Parameters .......................................................... 82 Receiver...................................................................... 81 Transmitter.................................................................. 82 Antenna Design Considerations ......................................... 74 Antenna/Balun .................................................................... 73 Automatic Frequency Control (AFC) ............................. 14, 50 FIFO Interrupt ..................................................................... 11 Frequency Shift Keying Data ............................................................................ 11 FIFO Select ................................................................ 11 Functional Description ........................................................ 43 G General PCB Layout Deign ................................................ 74 H Hardware Description ........................................................... 9 B I Baseband Features............................................................... 3 Baseband/Data Filtering ..................................................... 56 Bill of Materials.................................................................... 77 Block Diagrams AFC Circuit for Frequency Offset Correction .............. 51 Analog RSSI Voltage vs. RF Input Power................... 15 Application Circuit ....................................................... 73 Balun Circuit................................................................ 73 DIO Logic .................................................................... 58 Four Basic Copper FR4 Layers .................................. 74 Functional Node............................................................ 8 Logic Connection Between Power Control Bits .......... 63 MCU to MRF49XA Interface ......................................... 8 MRF49XA Architectural .............................................. 10 MRF49XA Interrupt Generation Logic......................... 55 RESET Pin Internal Connection.................................. 45 Two Basic Copper FR4 Layers ................................... 74 TX Register Before Transmit ...................................... 66 TX Register During Transmit ...................................... 67 I/O Pin Input Specifications................................................. 80 Initialization ......................................................................... 52 Internet Address ................................................................. 99 Interrupt .............................................................................. 12 Interrupt Request Output .................................................... 11 Interrupts ............................................................................ 52 Clearing ...................................................................... 53 LBTD .......................................................................... 53 LCEXINT .................................................................... 53 POR............................................................................ 53 Setting ........................................................................ 53 TXOWRXOF............................................................... 53 TXRXFIFO.................................................................. 53 WUTINT...................................................................... 53 C M Clock Output ....................................................................... 11 Clock Recovery Circuit (CLKRC) ........................................ 14 Crystal Oscillator ................................................................. 14 Crystal Oscillator and Clock Output .................................... 47 Crystal Selection Guidelines ............................................... 49 Current Consumption .......................................................... 80 Customer Change Notification Service ............................... 99 Customer Notification Service............................................. 99 Customer Support ............................................................... 99 Memory Organization ......................................................... 18 Microchip Internet Web Site................................................ 99 D Data Data In ........................................................................ 11 Data Out...................................................................... 11 Data Filtering and Clock Recovery ..................................... 14 Analog Operation ........................................................ 57 Digital Operation ......................................................... 57 Data Indicator Output (DIO) ................................................ 15 Data Quality Indicator (DQI).......................................... 15, 58 Data Validity Blocks Data Indicator Output.................................................. 15 Data Quality Indicator ................................................. 15 Receive Signal Strength Indicator............................... 15 E Electrical Characteristics..................................................... 79 Errata .................................................................................... 5 Examples Frequency Deviation and BBBW Calculation.............. 56 External Reference Input .................................................... 12 (c) 2009-2011 Microchip Technology Inc. L Low Duty Cycle Mode................................................... 16, 64 Low Noise Amplifier (LNA).................................................. 13 Low-Battery Voltage Detector............................................. 16 O Output Filter Capacitor ........................................................... 11 P Packaging Details......................................................................... 90 Marking....................................................................... 89 Packaging Information ........................................................ 89 Performance Characteristics BER Curves In 433 MHz Band................................................ 86 In 868 MHz Band................................................ 86 Channel Selectivity and Blocking ............................... 85 Receiver Sensitivity Over Ambient Temperature At 433 MHz......................................................... 88 At 868 MHz......................................................... 88 Phase Locked Loop (PLL) ............................................ 14, 48 Pin Description.................................................................... 11 Pin Diagram .......................................................................... 4 Pins CLKOUT ..................................................................... 11 CS............................................................................... 11 DATA .......................................................................... 11 FSK/DATA/FSEL ........................................................ 11 INT/DIO ...................................................................... 12 IRO ............................................................................. 11 RCLKOUT/FCAP/FINT............................................... 11 Preliminary DS70590C-page 97 MRF49XA RESET ........................................................................ 12 RFN............................................................................. 12 RFP ............................................................................. 12 RFXTL/EXTREF ......................................................... 12 RSSIO......................................................................... 12 SCK............................................................................. 11 SDI .............................................................................. 11 SDO ............................................................................ 11 VDD.............................................................................. 12 VSS .............................................................................. 12 Power and Low Noise Amplifiers ........................................ 47 Power Management ............................................................ 61 Power-Saving Modes Low Battery Voltage Detector ..................................... 16 Low Duty Cycle Mode ................................................. 16 Wake-up Timer ........................................................... 16 Programmable Synchronous Byte ...................................... 59 R Reader Response ............................................................. 100 Receive FIFO ...................................................................... 17 Receive Signal Strength Indicator (RSSI) ........................... 15 Received Signal Strength Indicator (RSSI) ......................... 59 Recommended Operating Conditions ................................. 80 Recovery Clock Output ....................................................... 11 Register Map....................................................................... 42 Registers AFCCREG (Automatic Frequency Control Configuration) 22 BBFCREG (Baseband Filter Configuration)................ 29 BCSREG (Battery Threshold Detect and Clock Output Value Set) ........................................................... 40 CFSREG (Center Frequency Value Set) .................... 26 DCSREG (Duty Cycle Value Set) ............................... 39 DRSREG (Data Rate Value Set) ................................ 35 FIFORSTREG (FIFO and Reset Mode Configuration) 32 GENCREG (General Configuration) ........................... 21 PLLCREG (PLL Configuration) ................................... 41 PMCREG (Power Management Configuration) .......... 36 RXCREG (Receive Control)........................................ 27 RXFIFOREG (Receiver FIFO Read)........................... 31 STSREG (STATUS Read) .......................................... 19 SYNBREG (Synchronous Byte Configuration) ........... 34 TXBREG (Transmit Byte)............................................ 25 TXCREG (Transmit Configuration) ............................. 23 WTSREG (Wake-up Timer Value Set)........................ 38 Reset Power Glitch Reset ..................................................... 44 Power-on Reset .......................................................... 43 RESET Pin.................................................................. 45 Software Reset ........................................................... 45 Reset Mode Selection ......................................................... 33 RESET Pin .......................................................................... 13 Revision History .................................................................. 95 RF Crystal ........................................................................... 12 RF Transmitter Matching..................................................... 74 RF/Analog Features .............................................................. 3 RX FIFO Buffered Data Read ............................................. 70 RX-TX Frequency Alignment Method ................................. 72 Timing Specification.................................................... 84 Synchronous Character Selection ...................................... 33 T Timing Diagrams FIFO Read with FINT Polling...................................... 71 FSK Modulated Deviation (Max. TX to RX Offset)...... 57 Low-Power Duty Cycle Mode Sequence .................... 64 Multiple Byte Write with Transmit Register ................. 69 Power-on Reset Example ........................................... 43 Receiver FIFO Read................................................... 70 Sensitive Reset Disabled............................................ 45 Sensitive Reset Enabled............................................. 44 SPI .............................................................................. 84 STSREG Read Sequence .......................................... 93 TX Register Usage ..................................................... 69 Transmit Register ............................................................... 16 TX Register Buffered Data Transmission ........................... 66 Typical Applications .............................................................. 3 V VDD Line Filtering................................................................ 46 W Wake-up Timer ................................................................... 16 WWW Address ................................................................... 99 WWW, On-Line Support ....................................................... 5 S Schematics MRF49XA ................................................................... 76 Serial Peripheral Interface (SPI) ......................................... 17 Sleep, Wake-up and Battery Operations............................. 65 SPI DS70590C-page 98 Preliminary (c) 2009-2011 Microchip Technology Inc. MRF49XA THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support through our web site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: Users of Microchip products can receive assistance through several channels: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQs), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives * * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://microchip.com/support CUSTOMER CHANGE NOTIFICATION SERVICE Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under "Support", click on "Customer Change Notification" and follow the registration instructions. (c) 2009-2011 Microchip Technology Inc. Preliminary DS70590C-page 99 MRF49XA READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: Technical Publications Manager RE: Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: MRF49XA Literature Number: DS70590C Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS70590C-page 100 Preliminary (c) 2009-2011 Microchip Technology Inc. MRF49XA PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Example: a) b) Device MRF49XA: Sub-GHz RF Transceiver Temperature Range I Package ST = TSSOP (Lead Plastic Thin Shrink Small Outline, No Lead) T = Tape and Reel MRF49XA-I/ST: Industrial temperature, TSSOP package. MRF49XAT-I/ST: Industrial temperature, TSSOP package, tape and reel. = -40 C to +85 C (Industrial) (c) 2009-2011 Microchip Technology Inc. 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