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FEATURES
DB, DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)
INT
A1
A2
P00
P01
P02
P03
P04
P05
P06
P07
GND
VCC
SDA
SCL
A0
P17
P16
P15
P14
P13
P12
P11
P10
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
24 23 22 21 20
7 8 9 10 11
1
2
3
4
5
6
18
17
16
15
14
13
RGE PACKAGE
(TOP VIEW)
A2
A1
INT
P10
P11 SDA
P06
P07
GND VCC
19
SCL
12
P12
P00
P01
P02
P03
P04
P05
A0
P17
P16
P15
P14
P13
DESCRIPTION/ORDERING INFORMATION
PCA9555REMOTE 16-BIT I
2
C AND SMBus I/O EXPANDERWITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
SCPS131C – AUGUST 2005 – REVISED JUNE 2006
•Latched Outputs With High-Current DriveCapability for Directly Driving LEDs•Low Standby-Current Consumption of1µA Max •Latch-Up Performance Exceeds 100 mA PerJESD 78, Class II•I
2
C to Parallel Port Expander
•ESD Protection Exceeds JESD 22•Open-Drain Active-Low Interrupt Output
– 2000-V Human-Body Model (A114-A)•5-V Tolerant I/O Ports
– 200-V Machine Model (A115-A)•Compatible With Most Microcontrollers
– 1000-V Charged-Device Model (C101)•400-kHz Fast I
2
C Bus•Address by Three Hardware Address Pins forUse of up to Eight Devices•Polarity Inversion Register
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING
Reel of 2000 PCA9555DBRSSOP – DB PD9555Reel of 250 PCA9555DBTQSOP – DBQ Reel of 2500 PCA9555DBQR PCA9555TVSOP – DGV Reel of 2000 PCA9555DGVR PD9555–40 °C to 85 °C Tube of 25 PCA9555DWSOIC – DW PCA9555Reel of 2000 PCA9555DWRTube of 60 PCA9555PWTSSOP – PW PD9555Reel of 1200 PCA9555PWRQFN – RGE Reel of 3000 PCA9555RGER PD9555
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available atwww.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005–2006, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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DESCRIPTION/ORDERING INFORMATION (CONTINUED)
PCA9555
REMOTE 16-BIT I
2
C AND SMBus I/O EXPANDERWITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
SCPS131C – AUGUST 2005 – REVISED JUNE 2006
This 16-bit I/O expander for the two-line bidirectional bus (I
2
C) is designed for 2.3-V to 5.5-V V
CC
operation. Itprovides general-purpose remote I/O expansion for most microcontroller families via the I
2
C interface [serialclock (SCL), serial data (SDA)].
The PCA9555 consists of two 8-bit Configuration (input or output selection), Input Port, Output Port, and PolarityInversion (active high or active low operation) registers. At power on, the I/Os are configured as inputs. Thesystem master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The datafor each input or output is kept in the corresponding Input or Output register. The polarity of the Input Portregister can be inverted with the Polarity Inversion register. All registers can be read by the system master.
The system master can reset the PCA9555 in the event of a timeout or other improper operation by utilizing thepower-on reset feature, which puts the registers in their default state and initializes the I
2
C/SMBus statemachine.
The PCA9555 open-drain interrupt ( INT) output is activated when any input state differs from its correspondingInput Port register state and is used to indicate to the system master that an input state has changed.
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, theremote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate viathe I
2
C bus. Thus, the PCA9555 can remain a simple slave device.
The device outputs (latched) have high-current drive capability for directly driving LEDs.
Although pin-to-pin and I
2
C-address is compatible with the PCF8575, software changes are required due to theenhancements.
The PCA9555 is identical to the PCA9535, except for the inclusion of the internal I/O pullup resistor, which pullsthe I/O to a default high when configured as an input and undriven.
Three hardware pins (A0, A1, and A2) are used to program and vary the fixed I
2
C address and allow up to eightdevices to share the same I
2
C bus or SMBus. The fixed I
2
C address of the PCA9555 is the same as thePCF8575, PCF8575C, and PCF8574, allowing up to eight of these devices in any combination to share thesame I
2
C bus or SMBus.
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PCA9555REMOTE 16-BIT I
2
C AND SMBus I/O EXPANDERWITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
SCPS131C – AUGUST 2005 – REVISED JUNE 2006
TERMINAL FUNCTIONS
NO.
SOIC (D),SSOP (DB),
NAME DESCRIPTIONQSOP (DBQ), QFN (RGE)TSSOP (PW), ANDTVSOP (DGV)
1 22 INT Interrupt output. Connect to V
CC
through a pullup resistor.2 23 A1 Address input. Connect directly to V
CC
or ground.3 24 A2 Address input. Connect directly to V
CC
or ground.4 1 P00 P-port input/output5 2 P01 P-port input/output6 3 P02 P-port input/output7 4 P03 P-port input/output8 5 P04 P-port input/output9 6 P05 P-port input/output10 7 P06 P-port input/output11 8 P07 P-port input/output12 9 GND Ground13 10 P10 P-port input/output14 11 P11 P-port input/output15 12 P12 P-port input/output16 13 P13 P-port input/output17 14 P14 P-port input/output18 15 P15 P-port input/output19 16 P16 P-port input/output20 17 P17 P-port input/output21 18 A0 Address input. Connect directly to V
CC
or ground.22 19 SCL Serial clock bus. Connect to V
CC
through a pullup resistor.23 20 SDA Serial data bus. Connect to V
CC
through a pullup resistor.24 21 V
CC
Supply voltage
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22
I/O
Port P17−P10
Shift
Register 16 Bits
LP Filter
Interrupt
Logic
Input
Filter
23
Power-On
Reset
Read Pulse
Write Pulse
PCA9555
3
2
21
1
24
12
GND
VCC
SDA
SCL
A2
A1
A0
INT
I2C Bus
Control
P07−P00
PCA9555
REMOTE 16-BIT I
2
C AND SMBus I/O EXPANDERWITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
SCPS131C – AUGUST 2005 – REVISED JUNE 2006
LOGIC DIAGRAM (POSITIVE LOGIC)
A. Pin numbers shown are for DB, DBQ, DGV, DW, and PW packages.B. All I/Os are set to inputs at reset.
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VCC
CLK
D Q
FF
Configuration
Register
Data From
Shift Register
Data From
Shift Register
Q
Write Configuration
Pulse
CLK
D Q
FF
Q
Write Pulse
Output Port
Register
100 kW
Q1
Q2
GND
I/O Pin
Output Port
Register Data
CLK
D Q
FF
Q
Input Port
Register
Read Pulse
CLK
D Q
FF
Q
Polarity Inversion
Register
Write Polarity
Pulse
Input Port
Register Data
Polarity
Register Data
To INT
Data From
Shift Register
I/O Port
PCA9555REMOTE 16-BIT I
2
C AND SMBus I/O EXPANDERWITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
SCPS131C – AUGUST 2005 – REVISED JUNE 2006
SIMPLIFIED SCHEMATIC OF P-PORT I/Os
(1)
(1) At power-on reset, all registers return to default values.
When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input. The inputvoltage may be raised above V
CC
to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the Output Port register. Inthis case, there are low-impedance paths between the I/O pin and either V
CC
or GND. The external voltageapplied to this I/O pin should not exceed the recommended levels for proper operation.
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I
2
C Interface
SDA
SCL
Start Condition
S
Stop Condition
P
SDA
SCL
Data Line
Stable;
Data Valid
Change
of Data
Allowed
PCA9555
REMOTE 16-BIT I
2
C AND SMBus I/O EXPANDERWITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
SCPS131C – AUGUST 2005 – REVISED JUNE 2006
The bidirectional I
2
C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must beconnected to a positive supply via a pullup resistor when connected to the output stages of a device. Datatransfer may be initiated only when the bus is not busy.
I
2
C communication with this device is initiated by a master sending a Start condition, a high-to-low transition onthe SDA input/output while the SCL input is high (see Figure 1 ). After the Start condition, the device addressbyte is sent, MSB first, including the data direction bit (R/W). This device does not respond to the general calladdress.
After receiving the valid address byte, this device responds with an ACK, a low on the SDA input/output duringthe high of the ACK-related clock pulse. The address inputs (A0–A2) of the slave device must not be changedbetween the Start and Stop conditions.
On the I
2
C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remainstable during the high pulse of the clock period, as changes in the data line at this time are interpreted as controlcommands (Start or Stop) (see Figure 2 ).
A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by themaster (see Figure 1 ).
Any number of data bytes can be transferred from the transmitter to the receiver between the Start and the Stopconditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line beforethe receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACKclock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (seeFigure 3 ). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly,the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and holdtimes must be met to ensure proper operation.
A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK)after the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA linehigh. In this event, the transmitter must release the data line to enable the master to generate a Stop condition.
Figure 1. Definition of Start and Stop Conditions
Figure 2. Bit Transfer
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Data Output
by Transmitter
SCL From
Master
Start
Condition
S
1 2 8 9
Data Output
by Receiver
Clock Pulse for
Acknowledgment
NACK
ACK
PCA9555REMOTE 16-BIT I
2
C AND SMBus I/O EXPANDERWITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
SCPS131C – AUGUST 2005 – REVISED JUNE 2006
Figure 3. Acknowledgment on I
2
C Bus
Interface Definition
BITBYTE
7 (MSB) 6 5 4 3 2 1 0 (LSB)
I
2
C slave address L H L L A2 A1 A0 R/ WP0x I/O data bus P07 P06 P05 P04 P03 P02 P01 P00P1x I/O data bus P17 P16 P15 P14 P13 P12 P11 P10
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Device Address
0 1 0 0 A1A2 A0
Slave Address
R/W
Fixed Programmable
Control Register and Command Byte
0 0 0 B2 B1 B000
PCA9555
REMOTE 16-BIT I
2
C AND SMBus I/O EXPANDERWITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
SCPS131C – AUGUST 2005 – REVISED JUNE 2006
Figure 4 shows the address byte of the PCA9555.
Figure 4. PCA9555 Address
Address Reference
INPUTS
I
2
C BUS SLAVE ADDRESSA2 A1 A0
L L L 32 (decimal), 20 (hexadecimal)L L H 33 (decimal), 21 (hexadecimal)L H L 34 (decimal), 22 (hexadecimal)L H H 35 (decimal), 23 (hexadecimal)H L L 36 (decimal), 24 (hexadecimal)H L H 37 (decimal), 25 (hexadecimal)H H L 38 (decimal), 26 (hexadecimal)H H H 39 (decimal), 27 (hexadecimal)
The last bit of the slave address defines the operation (read or write) to be performed. A high (1) selects a readoperation, while a low (0) selects a write operation.
Following the successful acknowledgment of the address byte, the bus master sends a command byte that isstored in the control register in the PCA9555. Three bits of this data byte state the operation (read or write) andthe internal register (input, output, polarity inversion or configuration) that will be affected. This register can bewritten or read through the I
2
C bus. The command byte is sent only during a write transmission.
Once a command byte has been sent, the register that was addressed continues to be accessed by reads untila new command byte has been sent.
Figure 5. Control Register Bits
Command Byte
CONTROL REGISTER BITS
COMMAND POWER-UPREGISTER PROTOCOLBYTE (HEX) DEFAULTB2 B1 B0
0 0 0 0x00 Input Port 0 Read byte xxxx xxxx0 0 1 0x01 Input Port 1 Read byte xxxx xxxx0 1 0 0x02 Output Port 0 Read/write byte 1111 11110 1 1 0x03 Output Port 1 Read/write byte 1111 11111 0 0 0x04 Polarity Inversion Port 0 Read/write byte 0000 00001 0 1 0x05 Polarity Inversion Port 1 Read/write byte 0000 00001 1 0 0x06 Configuration Port 0 Read/write byte 1111 11111 1 1 0x07 Configuration Port 1 Read/write byte 1111 1111
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Register Descriptions
Power-On Reset
PCA9555REMOTE 16-BIT I
2
C AND SMBus I/O EXPANDERWITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
SCPS131C – AUGUST 2005 – REVISED JUNE 2006
The Input Port registers (registers 0 and 1) reflect the incoming logic levels of the pins, regardless of whether thepin is defined as an input or an output by the Configuration register. It only acts on read operation. Writes tothese registers have no effect. The default value, X, is determined by the externally applied logic level.
Before a read operation, a write transmission is sent with the command byte to indicate to the the I
2
C device thatthe Input Port register will be accessed next.
Registers 0 and 1 (Input Port Registers)
Bit I0.7 I0.6 I0.5 I0.4 I0.3 I0.2 I0.1 I0.0
Default XXXXXXXX
Bit I1.7 I1.6 I1.5 I1.4 I1.3 I1.2 I1.1 I1.0
Default XXXXXXXX
The Output Port registers (registers 2 and 3) show the outgoing logic levels of the pins defined as outputs by theConfiguration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from thisregister reflect the value that is in the flip-flop controlling the output selection, not the actual pin value.
Registers 2 and 3 (Output Port Registers)
Bit O0.7 O0.6 O0.5 O0.4 O0.3 O0.2 O0.1 O0.0
Default 11111111
Bit O1.7 O1.6 O1.5 O1.4 O1.3 O1.2 O1.1 O1.0
Default 11111111
The Polarity Inversion registers (registers 4 and 5) allow polarity inversion of pins defined as inputs by theConfiguration register. If a bit in this register is set (written with 1), the corresponding port pin's polarity isinverted. If a bit in this register is cleared (written with a 0), the corresponding port pin's original polarity isretained.
Registers 4 and 5 (Polarity Inversion Registers)
Bit N0.7 N0.6 N0.5 N0.4 N0.3 N0.2 N0.1 N0.0
Default 00000000
Bit N1.7 N1.6 N1.5 N1.4 N1.3 N1.2 N1.1 N1.0
Default 00000000
The Configuration registers (registers 6 and 7) configure the directions of the I/O pins. If a bit in this register isset to 1, the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in thisregister is cleared to 0, the corresponding port pin is enabled as an output.
Registers 6 and 7 (Configuration Registers)
Bit C0.7 C0.6 C0.5 C0.4 C0.3 C0.2 C0.1 C0.0
Default 11111111
Bit C1.7 C1.6 C1.5 C1.4 C1.3 C1.2 C1.1 C1.0
Default 11111111
When power (from 0 V) is applied to V
CC
, an internal power-on reset holds the PCA9555 in a reset conditionuntil V
CC
has reached V
POR
. At that point, the reset condition is released and the PCA9555 registers andI
2
C/SMBus state machine initialize to their default states. After that, V
CC
must be lowered to below 0.2 V andthen back up to the operating voltage for a power-reset cycle.
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Interrupt ( INT) Output
Bus Transactions
Writes
1 2
SCL 3 4 5 6 7 8
SDA A A A
Data 0
R/W
tpv
9
00 0 0 0 0 0 1 0.7 0.0 Data 1
1.7 1.0 A
S 0 1 0 0 A2 A1 A0 0
tpv
P
Slave Address Command Byte Data to Port 0 Data to Port 1
Start Condition Acknowledge
From Slave
Write to Port
Data Out from Port 1
Data Out from Port 0
Data Valid
Acknowledge
From Slave Acknowledge
From Slave
1 2
SCL 3 4 5 6 7 8
SDA A A A
Data 0
Data to Register
R/W
9
00 0 0 0 0 1 1 MSB LSB Data1MSB LSB A
Data to Register
S 0 1 0 0 A2 A1 A0 0
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5
P
Acknowledge
From Slave
Acknowledge
From Slave
Start Condition
Command ByteSlave Address
Acknowledge
From Slave
PCA9555
REMOTE 16-BIT I
2
C AND SMBus I/O EXPANDERWITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
SCPS131C – AUGUST 2005 – REVISED JUNE 2006
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, t
iv
, thesignal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the originalsetting, data is read from the port that generated the interrupt or in a Stop event. Resetting occurs in the readmode at the acknowledge (ACK) bit or not acknowledge (NACK) bit after the falling edge of the SCL signal. In aStop event, INT is cleared after the rising edge of SDA. Interrupts that occur during the ACK or NACK clockpulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of theI/Os after resetting is detected and is transmitted as INT.
Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an outputcannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur if thestate of the pin does not match the contents of the Input Port register. Because each 8-bit port is readindependently, the interrupt caused by port 0 is not cleared by a read of port 1, or vice versa.
INT has an open-drain structure and requires a pullup resistor to V
CC
.
Data is exchanged between the master and the PCA9555 through write and read commands.
Data is transmitted to the PCA9555 by sending the device address and setting the least-significant bit to a logic0 (see Figure 4 for device address). The command byte is sent after the address and determines which registerreceives the data that follows the command byte.
The eight registers within the PCA9555 are configured to operate as four register pairs. The four pairs are inputports, output ports, polarity inversion ports, and configuration ports. After sending data to one register, the nextdata byte is sent to the other register in the pair (see Figure 6 and Figure 7 ). For example, if the first byte is sentto output port (register 3), the next byte is stored in Output Port 0 (register 2).
There is no limitation on the number of data bytes sent in one write transmission. In this way, each 8-bit registermay be updated independently of the other registers.
Figure 6. Write to Output Port Registers
Figure 7. Write to Configuration Registers
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Reads
0 0 A2 A1 A00 10 0 A2 A1 A00 1S 0 A A A
R/W
A
PNA
S
R/W
1MSB LSB
MSB LSB
Slave Address Acknowledge
From Slave
Command Byte
Data From Upper
or Lower Byte
of Register
Last Byte
Data
Acknowledge
From Slave Acknowledge
From Slave
Slave Address
Data From Lower
or Upper Byte
of Register
First Byte
Data
No Acknowledge
From Master
Acknowledge
From Master
At this moment, master transmitter
becomes master receiver, and
slave-receiver becomes
slave-transmitter.
123456789
S0100A2 A1 A0 1 A 7 6 5 4 3 2 1 0 A
I0.x
7 6 5 4 3 2 1 0 A
I1.x
7 6 5 4 3 2 1 0 A
I0.x
765432101
I1.x
P
R/W
SCL
SDA
INT
Read From Port 0
Data Into Port 0
Read From Port 1
Data Into Port 1
Acknowledge
From Master
Acknowledge
From Slave Acknowledge
From Master
Acknowledge
From Master No Acknowledge
From Master
tiv tir
PCA9555REMOTE 16-BIT I
2
C AND SMBus I/O EXPANDERWITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
SCPS131C – AUGUST 2005 – REVISED JUNE 2006
The bus master first must send the PCA9555 address with the least-significant bit set to a logic 0 (see Figure 4for device address). The command byte is sent after the address and determines which register is accessed.After a restart, the device address is sent again, but this time, the least-significant bit is set to a logic 1. Datafrom the register defined by the command byte then is sent by the PCA9555 (see Figure 8 through Figure 10 ).
After a restart, the value of the register defined by the command byte matches the register being accessed whenthe restart occurred. For example, if the command byte references Input Port 1 before the restart, and the restartoccurs when Input Port 0 is being read, the stored command byte changes to reference Input Port 0. Theoriginal command byte is forgotten. If a subsequent restart occurs, Input Port 0 is read first. Data is clocked intothe register on the rising edge of the ACK clock pulse. After the first byte is read, additional bytes may be read,but the data now reflect the information in the other register in the pair. For example, if Input Port 1 is read, thenext byte read is Input Port 0.
Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the numberof data bytes received in one read transmission, but when the final byte is received, the bus master must notacknowledge the data.
Figure 8. Read From Register
A. Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latestacknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (readInput Port register).B. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave addresscall and actual data transfer from the P port (see Figure 8 for these details).
Figure 9. Read Input Port Register, Scenario 1
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123456789
S 0 1 0 0 A2 A1 A0 1 A A
I0.x
A
I1.x
A
I0.x
1
I1.x
P
R/W
SCL
SDA
INT
tph
00 10 03 12
tps
tph tps
11 12
Read From Port 0
Data Into Port 0
Read From Port 1
Data Into Port 1
Data 02Data 01Data 00 Data 03
DataDataData 10
Acknowledge
From Slave Acknowledge
From Master
Acknowledge
From Master Acknowledge
From Master
No Acknowledge
From Master
tiv tir
PCA9555
REMOTE 16-BIT I
2
C AND SMBus I/O EXPANDERWITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
SCPS131C – AUGUST 2005 – REVISED JUNE 2006
A. Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latestacknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (readInput Port register).B. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave addresscall and actual data transfer from the P port (see Figure 8 for these details).
Figure 10. Read Input Port Register, Scenario 2
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Absolute Maximum Ratings
(1)
Recommended Operating Conditions
PCA9555REMOTE 16-BIT I
2
C AND SMBus I/O EXPANDERWITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
SCPS131C – AUGUST 2005 – REVISED JUNE 2006
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage range –0.5 6 VV
I
Input voltage range
(2)
–0.5 6 VV
O
Output voltage range
(2)
–0.5 6 VI
IK
Input clamp current V
I
< 0 –20 mAI
OK
Output clamp current V
O
< 0 –20 mAI
IOK
Input/output clamp current V
O
< 0 or V
O
> V
CC
±20 mAI
OL
Continuous output low current V
O
= 0 to V
CC
50 mAI
OH
Continuous output high current V
O
= 0 to V
CC
–50 mAContinuous current through GND –200I
CC
mAContinuous current through V
CC
160DB package 63DBQ package 61DGV package 86θ
JA
Package thermal impedance, junction to free air
(3)
°C/WDW package 46PW package 88RGE package 45θ
JP
Package thermal impedance, junction to pad RGE package 1.5 °C/WT
stg
Storage temperature range –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under Recommended OperatingConditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.(3) The package thermal impedance is calculated in accordance with JESD 51-7.
MIN MAX UNIT
V
CC
Supply voltage 2.3 5.5 VSCL, SDA 0.7 ×V
CC
5.5V
IH
High-level input voltage VA2–A0, P07–P00, P17–P10 0.7 ×V
CC
5.5SCL, SDA –0.5 0.3 ×V
CCV
IL
Low-level input voltage VA2–A0, P07–P00, P17–P10 –0.5 0.3 ×V
CC
I
OH
High-level output current P07–P00, P17–P10 –10 mAI
OL
Low-level output current P07–P00, P17–P10 25 mAT
A
Operating free-air temperature –40 85 °C
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Electrical Characteristics
PCA9555
REMOTE 16-BIT I
2
C AND SMBus I/O EXPANDERWITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
SCPS131C – AUGUST 2005 – REVISED JUNE 2006
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP
(1)
MAX UNIT
V
IK
Input diode clamp voltage I
I
= –18 mA 2.3 V to 5.5 V –1.2 VV
POR
Power-on reset voltage V
I
= V
CC
or GND, I
O
= 0 V
POR
1.5 1.65 V2.3 V 1.8I
OH
= –8 mA 3 V 2.64.75 V 4.1V
OH
P-port high-level output voltage
(2)
V2.3 V 1.7I
OH
= –10 mA 3 V 2.54.75 V 4SDA V
OL
= 0.4 V 2.3 V to 5.5 V 3V
OL
= 0.5 V 2.3 V to 5.5 V 8 20I
OL
P port
(3)
mAV
OL
= 0.7 V 2.3 V to 5.5 V 10 24INT V
OL
= 0.4 V 2.3 V to 5.5 V 3SCL, SDA ±1I
I
V
I
= V
CC
or GND 2.3 V to 5.5 V µAA2–A0 ±1I
IH
P port V
I
= V
CC
2.3 V to 5.5 V 1 µAI
IL
P port V
I
= GND 2.3 V to 5.5 V –100 µA5.5 V 100 200V
I
= V
CC
or GND, I
O
= 0,Operating mode 3.6 V 30 75 µAI/O = inputs, f
SCL
= 400 kHz, No load
2.7 V 20 505.5 V 1.1 1.5V
I
= GND, I
O
= 0, I/O = inputs,I
CC
Low inputs 3.6 V 0.7 1.3 mAf
SCL
= 0 kHz, No load
2.7 V 0.5 1Standby mode
5.5 V 0.5 1V
I
= V
CC
, I
O
= 0, I/O = inputs,High inputs 3.6 V 0.4 0.9 µAf
SCL
= 0 kHz, No load
2.7 V 0.25 0.8Additional current in standby One input at V
CC
– 0.6 V,∆I
CC
2.3 V to 5.5 V 1.5 mAmode Other inputs at V
CC
or GNDC
I
SCL V
I
= V
CC
or GND 2.3 V to 5.5 V 3 7 pFSDA 3 7C
io
V
IO
= V
CC
or GND 2.3 V to 5.5 V pFP port 3.7 9.5
(1) All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V V
CC
) and T
A
= 25 °C.(2) Each I/O must be externally limited to a maximum of 25 mA, and each octal (P07–P00 and P17–P10) must be limited to a maximumcurrent of 100 mA, for a device total of 200 mA.(3) The total current sourced by all I/Os must be limited to 160 mA (80 mA for P07–P00 and 80 mA for P17–P10).
14
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I
2
C Interface Timing Requirements
Switching Characteristics
PCA9555REMOTE 16-BIT I
2
C AND SMBus I/O EXPANDERWITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
SCPS131C – AUGUST 2005 – REVISED JUNE 2006
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 11 )
MIN MAX UNIT
f
scl
I
2
C clock frequency 0 400 kHzt
sch
I
2
C clock high time 0.6 µst
scl
I
2
C clock low time 1.3 µst
sp
I
2
C spike time 50 nst
sds
I
2
C serial-data setup time 100 nst
sdh
I
2
C serial-data hold time 0 nst
icr
I
2
C input rise time 20 + 0.1C
b
(1)
300 nst
icf
I
2
C input fall time 20 + 0.1C
b
(1)
300 nst
ocf
I
2
C output fall time 10-pF to 400-pF bus 20 + 0.1C
b
(1)
300 nst
buf
I
2
C bus free time between Stop and Start 1.3 µst
sts
I
2
C Start or repeated Start condition setup 0.6 µst
sth
I
2
C Start or repeated Start condition hold 0.6 µst
sps
I
2
C Stop condition setup 0.6 µst
vd(Data)
Valid-data time SCL low to SDA output valid 50 nst
vd(ack)
Valid-data time of ACK condition ACK signal from SCL low to SDA (out) low 0.1 0.9 µsC
b
I
2
C bus capacitive load 400 pF
(1) C
b
= total capacitance of one bus line in pF
over recommended operating free-air temperature range, C
L
≤100 pF (unless otherwise noted) (see Figure 12 andFigure 13 )
FROM TOPARAMETER MIN MAX UNIT(INPUT) (OUTPUT)
t
iv
Interrupt valid time P port INT 4 µst
ir
Interrupt reset delay time SCL INT 4 µst
pv
Output data valid SCL P port 200 nst
ps
Input data setup time P port SCL 150 nst
ph
Input data hold time P port SCL 1 µs
15Submit Documentation Feedback
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TYPICAL CHARACTERISTICS
0
5
10
15
20
25
30
35
40
45
50
55
-50 -25 0 25 50 75 100
TA– Free-Air Tem perature – °C
ICC – Supply Current – µA
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
fSCL = 400 kHz
I/Os Unloaded
0
10
20
30
40
50
60
70
2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
VCC – Supply Voltage – V
ICC – Supply Current – µA
fSCL = 400 kHz
I/Os Unloaded
0
5
10
15
20
25
30
-50 -25 0 25 50 75 100
TA– Free-Air Tem perature – °C
ICC – Supply Current – nA
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
SCL = VCC
0
5
10
15
20
25
30
0.0 0.1 0.2 0.3 0.4 0.5 0.6
VOL – Output Low Voltage – V
ISINK – I/O Sink Current – mA
TA= –40°C
VCC = 2.5 V
TA= 25°C
TA= 125°C
0
5
10
15
20
25
30
35
40
0.0 0.1 0.2 0.3 0.4 0.5 0.6
VOL – Output Low Voltage – V
ISINK – I/O Sink Current – mA
TA= –40°C
VCC = 3.3 V
TA= 25°C
TA= 125°C
0
5
10
15
20
25
30
35
40
45
50
0.0 0.1 0.2 0.3 0.4 0.5 0.6
VOL – Output Low Voltage – V
ISINK – I/O Sink Current – mA
TA= –40°C
VCC = 5 V
TA= 25°C
TA= 125°C
0
5
10
15
20
25
30
35
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
(VCC – VOH) – V
ISOURCE – I/O Source Current – mA
TA= –40°C
VCC = 2.5 V
TA= 25°C
TA= 125°C
0
5
10
15
20
25
30
35
40
45
50
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
(VCC – VOH) – V
ISOURCE – I/O Source Current – mA
TA= –40°C
VCC = 3.3 V
TA= 25°C
TA= 125°C
0
25
50
75
100
125
150
175
200
225
250
275
300
-50 -25 0 25 50 75 100
TA– Free-Air Te m perature – °C
VOL – Output Low Voltage – mV
VCC = 5 V, ISINK = 10 mA
VCC = 2.5 V, ISINK = 10 mA
VCC = 2.5 V, ISINK = 1 mA
VCC = 5 V, ISINK = 1 mA
PCA9555
REMOTE 16-BIT I
2
C AND SMBus I/O EXPANDERWITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
SCPS131C – AUGUST 2005 – REVISED JUNE 2006
T
A
= 25 °C (unless otherwise noted)
SUPPLY CURRENT STANDBY SUPPLY CURRENT SUPPLY CURRENTvs vs vsTEMPERATURE TEMPERATURE SUPPLY VOLTAGE
I/O SINK CURRENT I/O SINK CURRENT I/O SINK CURRENTvs vs vsOUTPUT LOW VOLTAGE OUTPUT LOW VOLTAGE OUTPUT LOW VOLTAGE
I/O OUTPUT LOW VOLTAGE I/O SOURCE CURRENT I/O SOURCE CURRENTvs vs vsTEMPERATURE OUTPUT HIGH VOLTAGE OUTPUT HIGH VOLTAGE
16
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0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
(VCC – VOH) – V
ISOURCE – I/O Source Current – mA
TA= –40°C
VCC = 5 V
TA= 25°C
TA= 125°C
0
25
50
75
100
125
150
175
200
225
250
275
300
-50 -25 0 25 50 75 100
TA– Free-Air Te m perature – °C
VOH – Output High Voltage – mV
VCC = 5 V, IOL = 10 mA
VCC = 2.5 V, IOL = 10 mA
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Num ber of I/Os Held Low
ICC – Supply Current – µA
TA= –40°C
VCC = 5 V
TA= 25°C
TA= 125°C
0
1
2
3
4
5
6
2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
VCC – Supply Voltage – V
VOH – Output High Voltage – V
IOH = –10 m A
IOH = –8 m A
TA= 25°C
PCA9555REMOTE 16-BIT I
2
C AND SMBus I/O EXPANDERWITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
SCPS131C – AUGUST 2005 – REVISED JUNE 2006
TYPICAL CHARACTERISTICS (continued)T
A
= 25 °C (unless otherwise noted)
I/O SOURCE CURRENT I/O HIGH VOLTAGE SUPPLY CURRENTvs vs vsOUTPUT HIGH VOLTAGE TEMPERATURE NUMBER OF I/Os HELD LOW
OUTPUT HIGH VOLTAGE
vsSUPPLY VOLTAGE
17Submit Documentation Feedback
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PARAMETER MEASUREMENT INFORMATION
RL = 1 kΩ
VCC
CL = 50 pF
tbuf
ticr
tsth tsds
tsdh
ticf
ticr
tscl tsch
tsts
tPHL
tPLH
0.3 × VCC
Stop
Condition
tsps
Repeat
Start
Condition
Start or
Repeat
Start
Condition
SCL
SDA
Start
Condition
(S)
Address
Bit 7
(MSB)
Data
Bit 10
(LSB)
Stop
Condition
(P)
Three Bytes for Complete
Device Programming
SDA LOAD CONFIGURATION
VOLTAGE WAVEFORMS
ticf
Stop
Condition
(P)
tsp
DUT SDA
0.7 × VCC
0.3 × VCC
0.7 × VCC
R/W
Bit 0
(LSB)
ACK
(A)
Data
Bit 07
(MSB)
Address
Bit 1
Address
Bit 6
BYTE DESCRIPTION
1 I2C address
2, 3 P-port data
PCA9555
REMOTE 16-BIT I
2
C AND SMBus I/O EXPANDERWITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
SCPS131C – AUGUST 2005 – REVISED JUNE 2006
A. C
L
includes probe and jig capacitance.B. All inputs are supplied by generators having the following characteristics: PRR ≤10 MHz, Z
O
= 50 Ω, t
r
/t
f
≤30 ns.C. All parameters and waveforms are not applicable to all devices.
Figure 11. I
2
C Interface Load Circuit and Voltage Waveforms
18
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A
A
A
A
S 0 1 0 0 A1A2 A0 1Data 1 1 PData 3
Start
Condition 16 Bits
(Two Data Bytes)
From Port Data From PortSlave Address (PCA9555)
R/W
87654321
tir
tir
tsps
tiv
Address Data 1 Data 3
INT
Data
Into
Port
B
B
A
A
Pn INT
R/W A
tir
0.7 × VCC
0.3 × VCC
0.7 × VCC
0.3 × VCC
0.7 × VCC
0.3 × VCC
0.7 × VCC
0.3 × VCC
INT SCL
View B−BView A−A
tiv
RL = 4.7 kΩ
VCC
CL = 100 pF
INTERRUPT LOAD CONFIGURATION
DUT INT
ACK
From Slave ACK
From Slave
Data 2
Data 2
PCA9555REMOTE 16-BIT I
2
C AND SMBus I/O EXPANDERWITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
SCPS131C – AUGUST 2005 – REVISED JUNE 2006
PARAMETER MEASUREMENT INFORMATION (continued)
A. C
L
includes probe and jig capacitance.B. All inputs are supplied by generators having the following characteristics: PRR ≤10 MHz, Z
O
= 50 Ω, t
r
/t
f
≤30 ns.C. All parameters and waveforms are not applicable to all devices.
Figure 12. Interrupt Load Circuit and Voltage Waveforms
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P00 A 0.7 × VCC
0.3 × VCC
SCL P17
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
tpv
(see Note A)
Slave
ACK
Unstable
Data
Last Stable Bit
SDA
Pn
Pn
WRITE MODE (R/W = 0)
P00 A 0.7 × VCC
0.3 × VCC
SCL P17
0.7 × VCC
0.3 × VCC
tps tph
READ MODE (R/W = 1)
DUT
GND
CL = 100 pF
P-PORT LOAD CONFIGURATION
Pn
PCA9555
REMOTE 16-BIT I
2
C AND SMBus I/O EXPANDERWITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
SCPS131C – AUGUST 2005 – REVISED JUNE 2006
PARAMETER MEASUREMENT INFORMATION (continued)
A. C
L
includes probe and jig capacitance.B. t
pv
is measured from 0.7 ×V
CC
on SCL to 50% I/O (Pn) output.C. All inputs are supplied by generators having the following characteristics: PRR ≤10 MHz, Z
O
= 50 Ω, t
r
/t
f
≤30 ns.D. The outputs are measured one at a time, with one transition per measurement.E. All parameters and waveforms are not applicable to all devices.
Figure 13. P-Port Load Circuit and Voltage Waveforms
20
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SDA
SCL
Start
ACK or Read Cycle
tw
tREC
RESET
tREC
0.3 y VCC
VCC/2
tRESET
Pn
RL = 1 kΩ
VCC
CL = 50 pF
SDA LOAD CONFIGURATION
DUT SDA DUT
P-PORT LOAD CONFIGURATION
Pn
CL = 100 pF
VCC/2
PCA9555REMOTE 16-BIT I
2
C AND SMBus I/O EXPANDERWITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
SCPS131C – AUGUST 2005 – REVISED JUNE 2006
PARAMETER MEASUREMENT INFORMATION (continued)
A. C
L
includes probe and jig capacitance.B. All inputs are supplied by generators having the following characteristics: PRR ≤10 MHz, Z
O
= 50 Ω, t
r
/t
f
≤30 ns.C. The outputs are measured one at a time, with one transition per measurement.D. I/Os are configured as inputs.E. All parameters and waveforms are not applicable to all devices.
Figure 14. Reset Load Circuits and Voltage Waveforms
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APPLICATION INFORMATION
P00
P01
P02
P03
P04
P05
A2
A1
A0
A
B
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
VCC
VCC
VCC
(5 V)
Controlled Switch
(e.g., CBT Device)
GND INT
SDA
SCL
10 kW10 kW10 kW10 kW2 kW
INT
Subsystem 1
(e.g., Temperature
Sensor)
Subsystem 2
(e.g., Counter)
PCA9555
SDA
SCL
INT
GND
Keypad ALARM
RESET
ENABLE
Subsystem 3
(e.g., Alarm)
Master
Controller
4
5
6
7
8
9
10
11
13
14
15
16
17
18
19
20
22
23
1
3
2
21
12
24
VCC
PCA9555
REMOTE 16-BIT I
2
C AND SMBus I/O EXPANDERWITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
SCPS131C – AUGUST 2005 – REVISED JUNE 2006
Figure 15 shows an application in which the PCA9555 can be used.
A. Device address is configured as 0100100 for this example.B. P00, P02, and P03 are configured as outputs.C. P01, P04–P07, and P10–P17 are configured as inputs.D. Pin numbers shown are for DB, DBQ, DGV, DW, and PW packages.
Figure 15. Typical Application
22
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Minimizing I
CC
When I/O Is Used to Control LED
VCC
VCC
LED
Pn
100 kW
VCC
3.3 V 5 V
LED
Pn
PCA9555REMOTE 16-BIT I
2
C AND SMBus I/O EXPANDERWITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
SCPS131C – AUGUST 2005 – REVISED JUNE 2006
APPLICATION INFORMATION (continued)
When an I/O is used to control an LED, normally it is connected to V
CC
through a resistor as shown in Figure 15 .Because the LED acts as a diode, when the LED is off, the I/O V
IN
is about 1.2 V less than V
CC
. The ∆I
CCparameter in Electrical Characteristics shows how I
CC
increases as V
IN
becomes lower than V
CC
. Forbattery-powered applications, it is essential that the voltage of I/O pins is greater than or equal to V
CC
when theLED is off to minimize current consumption.
Figure 16 shows a high-value resistor in parallel with the LED. Figure 17 shows V
CC
less than the LED supplyvoltage by at least 1.2 V. Both of these methods maintain the I/O V
IN
at or above V
CC
and prevent additionalsupply current consumption when the LED is off.
Figure 16. High-Value Resistor in Parallel With LED
Figure 17. Device Supplied by Lower Voltage
23Submit Documentation Feedback
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
PCA9555DB ACTIVE SSOP DB 24 60 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9555DBQR ACTIVE SSOP/
QSOP DBQ 24 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1YEAR
PCA9555DBQRG4 ACTIVE SSOP/
QSOP DBQ 24 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1YEAR
PCA9555DBR ACTIVE SSOP DB 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9555DGVR ACTIVE TVSOP DGV 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9555DW ACTIVE SOIC DW 24 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9555DWR ACTIVE SOIC DW 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9555PW ACTIVE TSSOP PW 24 60 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9555PWE4 ACTIVE TSSOP PW 24 60 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9555PWR ACTIVE TSSOP PW 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9555PWRE4 ACTIVE TSSOP PW 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9555RGER ACTIVE QFN RGE 24 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1YEAR
PCA9555RHLR PREVIEW QFN RHL 24 1000 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
PACKAGE OPTION ADDENDUM
www.ti.com 19-Jun-2006
Addendum-Page 1
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 19-Jun-2006
Addendum-Page 2
MECHANICAL DATA
MPDS006C – FEBRUAR Y 1996 – REVISED AUGUST 2000
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50 4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
112
24 13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
382416
4,90
5,103,70
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
M
0,07
0,40
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65 M
0,10
0,10
0,25
0,50
0,75
0,15 NOM
Gage Plane
28
9,80
9,60
24
7,90
7,70
2016
6,60
6,40
4040064/F 01/97
0,30
6,60
6,20
80,19
4,30
4,50
7
0,15
14
A
1
1,20 MAX
14
5,10
4,90
8
3,10
2,90
A MAX
A MIN
DIM PINS **
0,05
4,90
5,10
Seating Plane
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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