0 QPro Virtex 2.5V Radiation-Hardened FPGAs R DS028 (v2.0) January 4, 2010 0 2 Product Specification Features * Supported by FPGA FoundationTM and Alliance Development Systems * 0.22 m 5-layer epitaxial process * QML certified * Radiation-hardened FPGAs for space and satellite applications - Complete support for Unified Libraries, Relationally Placed Macros, and Design Manager * Guaranteed total ionizing dose to 100K Rad(si) - Wide selection of PC and workstation platforms * Latch-up immune to LET = 125 MeV cm2/mg * SEU immunity achievable with recommended redundancy implementation * - Unlimited reprogrammability - Four programming modes * Guaranteed over the full military temperature range (-55 C to +125 C) * Fast, high-density Field-Programmable Gate Arrays Available to Standard Microcircuit Drawings. Contact Defense Supply Center Columbus (DSCC) for more information at http://www.dscc.dla.mil - Densities from 100k to 1M system gates - 5962-99572 for XQVR300 - System performance up to 200 MHz - 5962-99573 for XQVR600 - Hot-swappable for Compact PCI - 5962-99574 for XQVR1000 * * * * Multi-standard SelectIOTM interfaces - 16 high-performance interface standards - Connects directly to ZBTRAM devices * SRAM-based in-system configuration Description Built-in clock-management circuitry - Four dedicated delay-locked loops (DLLs) for advanced clock control - Four primary low-skew global clock distribution nets, plus 24 secondary global nets Hierarchical memory system - LUTs configurable as 16-bit RAM, 32-bit RAM, 16-bit dual-ported RAM, or 16-bit Shift Register - Configurable synchronous dual-ported 4k-bit RAMs - Fast interfaces to external high-performance RAMs Flexible architecture that balances speed and density - Dedicated carry logic for high-speed arithmetic - Dedicated multiplier support - Cascade chain for wide-input functions - Abundant registers/latches with clock enable, and dual synchronous/asynchronous set and reset - Internal 3-state bussing - IEEE 1149.1 boundary-scan logic - Die-temperature sensing device The QProTM Virtex(R) family delivers high-performance, high-capacity programmable logic solutions. Dramatic increases in silicon efficiency result from optimizing the new architecture for place-and-route efficiency and exploiting an aggressive 5-layer-metal 0.22 m CMOS process. These advances make QPro Virtex FPGAs powerful and flexible alternatives to mask-programmed gate arrays. The Virtex radiation-hardened family comprises the three members shown in Table 1. Building on experience gained from previous generations of FPGAs, the Virtex family represents a revolutionary step forward in programmable logic design. Combining a wide variety of programmable system features, a rich hierarchy of fast, flexible interconnect resources, and advanced process technology, the QPro Virtex family delivers a high-speed and high-capacity programmable logic solution that enhances design flexibility while reducing time-to-market. Refer to the Virtex 2.5V FPGA commercial data sheet at http://www.xilinx.com/support/documentation/virtex.htm for more information on device architecture and timing specifications. (c) Copyright 2001-2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. DS028 (v2.0) January 4, 2010 Product Specification www.xilinx.com 1 R QPro Virtex 2.5V Radiation-Hardened FPGAs Table 1: QPro Virtex FPGA Radiation-Hardened FPGA Family Members Device System Gates CLB Array Logic Cells Maximum Available I/O Block RAM Bits Max Select RAM Bits XQVR300 322,970 32x48 6,912 162 65,536 98,304 XQVR600 661,111 48x72 15,552 162 98,304 221,184 XQVR1000 1,124,022 64x96 27,648 404 131,072 393,216 Radiation Specifications(1) Symbol Description Min Max Units TID Total Ionizing Dose 100 - krad(Si) - 0 (cm2/Device) - 6.5E - 8 (cm2/Bit) - 8.0E - 8 (cm2/Bit) - 2.2E - 14 (cm2/Bit) - 1.6E - 7 (cm2/Bit) Method 1019, Dose Rate ~9.0 rad(Si)/sec SEL Single Event Latch-up Immunity Heavy Ion Saturation Cross Section LET > 125 MeV cm2/mg SEUFH Single Event Upset CLB Flip-flop Heavy Ion Saturation Cross Section SEUCH Single Event Upset Configuration Latch Heavy Ion Saturation Cross Section SEUCP Single Event Upset Configuration Latch Proton (63 MeV) Saturation Cross Section SEUBH Single Event Upset Block RAM Bit Heavy Ion Saturation Cross Section Notes: 1. For more information, refer to "Radiation Test Results of the Virtex FPGA for Space Based Reconfigurable Computing" and "SEU Mitigation Techniques for Virtex FPGAs in Space Applications" at http://www.xilinx.com/esp/aero_def/aero_def_app.htm. 2 www.xilinx.com DS028 (v2.0) January 4, 2010 Product Specification R QPro Virtex 2.5V Radiation-Hardened FPGAs Virtex FPGA Electrical Characteristics Based on preliminary characterization. Further changes are not expected. All specifications are representative of worst-case supply voltage and junction temperature conditions. The parameters included are common to popular designs and typical applications. Contact the factory for design considerations requiring more detailed information. Virtex FPGA DC Characteristics Absolute Maximum Ratings Symbol Description Min/Max Units VCCINT Supply voltage relative to GND -0.5 to 3.0 V VCCO Supply voltage relative to GND -0.5 to 4.0 V VREF Input reference voltage VIN(3) Input voltage relative to GND VTS Voltage applied to 3-state output VCC Longest supply voltage rise time from 1V to 2.375V TSTG Storage temperature (ambient) TJ -0.5 to 3.6 V Using VREF -0.5 to 3.6 V Internal threshold -0.5 to 5.5 V -0.5 to 5.5 V 50 ms -65 to +150 C +150 C Junction temperature Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability. 2. Power supplies can turn on in any order. 3. For protracted periods (e.g., longer than a day), VIN should not exceed VCCO by more that 3.6V. Recommended Operating Conditions Symbol VCCINT VCCO Description Supply voltage relative to GND Supply voltage relative to GND TIN Input signal transition time TIC Initialization temperature range(4) TOC ICCINTQ ICCCCOQ Device Operational temperature range(5) Quiescent VCCINT supply current Quiescent VCCO supply current Min 2.5 - 5% Max 2.5 + 5% Units V 1.2 3.6 V - 250 ns XQVR300 -55 +125 C XQVR600 -55 +125 C XQVR1000 -40 +125 C XQVR300 -55 +125 C XQVR600 -55 +125 C XQVR1000 -55 +125 C XQVR300 - 150 mA XQVR600 - 200 mA XQVR1000 - 200 mA XQVR300 - 4.0 mA XQVR600 - 4.0 mA XQVR1000 - 4.0 mA Notes: 1. Correct operation is guaranteed with a minimum VCCINT of 2.25V (Nominal VCCINT - 10%). Below the minimum value stated above, all delay parameters increase by 3% for each 50 mV reduction in VCCINT below the specified range. 2. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per C. 3. Input and output measurement threshold is ~50% of VCC. 4. Initialization occurs from the moment of VCC ramp-up to the rising transition of the INIT pin. 5. The device is operational after the INIT pin has transitioned High. DS028 (v2.0) January 4, 2010 Product Specification www.xilinx.com 3 R QPro Virtex 2.5V Radiation-Hardened FPGAs QPro Virtex FPGA Pinouts Device/Package Combinations and Maximum User I/O Maximum User I/O (Excluding Dedicated Clock Pins) Package XQVR300 XQVR600 XQVR1000 CB228 162 162 - CG560(1) - - 404 Notes: 1. Obsolete package. CG560 is no longer available. It is listed for information purposes only. Pinout Tables Table 2 and Table 3 list the locations of special-purpose and power-supply pins. Pins not listed are user I/Os. Table 2: Virtex FPGA Ceramic Column Grid (CG560) Pinout (Continued) Table 2: Virtex FPGA Ceramic Column Grid (CG560) Pinout 4 Pin Name Device CG560(1) GCK0 XQVR1000 AL17 GCK1 AJ17 GCK2 D17 GCK3 A17 M0 AJ29 M1 AK30 M2 AN32 CCLK C4 PROGRAM AM1 DONE AJ5 INIT AH5 BUSY/DOUT D4 D0/DIN E4 D1 K3 D2 L4 D3 P3 D4 W4 D5 AB5 D6 AC4 D7 AJ4 WRITE D6 CS A2 TDI D5 Pin Name Device CG560(1) TDO XQVR1000 E6 TMS B33 TCK E29 DXN AK29 DXP AJ28 VCCINT (VCCINT pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) A21, B12, B14, B18, B28, C22, C24, E9, E12, F2, H30, J1, K32, M3, N1, N29, N33, U5, U30, Y2, Y31, AB2, AB32, AD2, AD32, AG3, AG31, AJ13, AK8, AK11, AK17, AK20, AL14, AL22, AL27, AN25 VCCO, Bank 0 A22, A26, A30, B19, B32 VCCO, Bank 1 A10, A16, B13, C3, E5 VCCO, Bank 2 B2, D1, H1, M1, R2 www.xilinx.com DS028 (v2.0) January 4, 2010 Product Specification R QPro Virtex 2.5V Radiation-Hardened FPGAs Table 2: Virtex FPGA Ceramic Column Grid (CG560) Pinout (Continued) Pin Name VCCO, Bank 3 Device CG560(1) XQVR1000 V1, AA2, AD1, AK1, AL2 VCCO, Bank 4 AM2, AM15, AN4, AN8, AN12 VCCO, Bank 5 AL31, AM21, AN18, AN24, AN30 VCCO, Bank 6 W32, AB33, AF33, AK33, AM32 VCCO, Bank 7 C32, D33, K33, N32, T33 VREF, Bank 0 A19, D20, D26, D29, E21, E23, E24, E27, Within each bank, if input reference voltage is not required, all VREF pins are general I/O. VREF, Bank 1 Within each bank, if input reference voltage is not required, all VREF pins are general I/O. VREF, Bank 2 Within each bank, if input reference voltage is not required, all VREF pins are general I/O. VREF, Bank 3 Within each bank, if input reference voltage is not required, all VREF pins are general I/O. VREF, Bank 4 Within each bank, if input reference voltage is not required, all VREF pins are general I/O. VREF, Bank 5 Within each bank, if input reference voltage is not required, all VREF pins are general I/O. DS028 (v2.0) January 4, 2010 Product Specification Table 2: Virtex FPGA Ceramic Column Grid (CG560) Pinout (Continued) Pin Name VREF, Bank 6 Device XQVR1000 Within each bank, if input reference voltage is not required, all VREF pins are general I/O. V29, Y32, AA30,AD31, AE29, AK32, AE31, AH30 VREF, Bank 7 Within each bank, if input reference voltage is not required, all VREF pins are general I/O. D31, E31, G31, H32, K31, P31, T31, L33 GND A1, A7, A12, A14, A18, A20, A24, A29, A32, A33, B1, B6, B9, B15, B23, B27, B31, C2, E1, F32, G2, G33, J32, K1, L2, M33, P1, P33, R32, T1, V33, W2, Y1, Y33, AB1, AC32, AD33, AE2, AG1, AG32, AH2, AJ33, AL32, AM3, AM7, AM11, AM19, AM25, AM28, AM33, AN1, AN2, AN5, AN10, AN14, AN16, AN20, AN22, AN27, AN33 A6, D7, D10, D11, D13, D16, E7, E15 B3, G5, H4, K5, L5, N5, P4, R1 V4, W5, AA4, AD3, AE5, AF1, AH4, AK2 No Connect AK13, AL7, AL9, AL10, AL16, AM4, AM14,AN3 CG560(1) XQVR1000 C31, AC2, AK4, AL3 Notes: 1. Obsolete package. CG560 is no longer available. It is listed for information purposes only. AJ18, AJ25, AK28, AL20, AL24, AL29, AM26, AN23 www.xilinx.com 5 R QPro Virtex 2.5V Radiation-Hardened FPGAs Table 3: CQFP Package (CB228) (Continued) Table 3: CQFP Package (CB228) 6 Function Pin # Bank # Function Pin # Bank # GND 1 7 VCCO 28 6 TMS 2 IO_TRDY 29 IO 3 VCCINT 30 IO 4 IO 31 IO_VREF_7 5 IO 32 IO 6 IO 33 IO 7 IO_VREF_6 34 GND 8 IO 35 IO 9 IO 36 IO 10 VCCO 37 IO 11 IO 38 IO_VREF_7 12 IO 39 IO 13 IO 40 GND 14 VCCINT 41 VCCINT 15 GND 42 IO 16 IO 43 IO 17 IO_VREF_6 44 VCCO 18 IO 45 IO 19 IO 46 IO 20 IO_VREF_6 47 IO_VREF_7 21 GND 48 IO 22 IO 49 IO 23 IO 50 IO 24 IO_VREF_6 51 IO 25 IO 52 IO_IRDY 26 IO 53 GND 27 IO 54 M1 55 GND 56 M0 57 www.xilinx.com DS028 (v2.0) January 4, 2010 Product Specification R QPro Virtex 2.5V Radiation-Hardened FPGAs Table 3: CQFP Package (CB228) (Continued) Table 3: CQFP Package (CB228) (Continued) Function Pin # Bank # Function Pin # Bank # VCCO 58 5 VCCINT 83 4 M2 59 GCK1 84 IO 60 VCCO 85 IO 61 GND 86 IO 62 GCKO 87 IO_VREF_5 63 IO 88 IO 64 IO 89 IO 65 IO 90 GND 66 IO 91 IO_VREF_5 67 IO_VREF_4 92 IO 68 IO 93 IO 69 IO 94 IO_VREF5 70 VCCO 95 IO 71 IO 96 GND 72 IO 97 VCCINT 73 IO 98 IO 74 VCCINT 99 IO 75 GND 100 VCCO 76 IO 101 IO 77 IO_VREF_4 102 IO 78 IO 103 IO_VREF_5 79 IO 104 IO 80 IO_VREF_4 105 IO 81 GND 106 IO 82 IO 107 IO 108 IO_VREF_4 109 IO 110 IO 111 IO 112 GND 113 DONE 114 VCCO 115 DS028 (v2.0) January 4, 2010 Product Specification www.xilinx.com 7 R QPro Virtex 2.5V Radiation-Hardened FPGAs Table 3: CQFP Package (CB228) (Continued) Table 3: CQFP Package (CB228) (Continued) 8 Function Pin # Bank # Function Pin # Bank # PROGRAM 116 3 GND 143 2 IO_INIT 117 IO_IRDY 144 IO_D7 118 IO 145 IO 119 IO 146 IO_VREF_3 120 IO 147 IO 121 IO_D3 148 IO 122 IO_VREF_2 149 GND 123 IO 150 IO_VREF_3 124 IO 151 IO 125 VCCO 152 IO 126 IO 153 IO_VREF_3 127 IO 154 IO_D6 128 IO_D2 155 GND 129 VCCINT 156 VCCINT 130 GND 157 IO_D5 131 IO_D1 158 IO 132 IO_VREF_2 159 VCCO 133 IO 160 IO 134 IO 161 IO 135 IO_VREF_2 162 IO_VREF_3 136 GND 163 IO_D4 137 IO 164 IO 138 IO 165 IO 139 IO_VREF_2 166 VCCINT 140 IO 167 IO_TRDY 141 IO_DIN_D0 168 VCCO 142 IO_DOUT_BUSY 169 CCLK 170 VCCO 171 www.xilinx.com DS028 (v2.0) January 4, 2010 Product Specification R QPro Virtex 2.5V Radiation-Hardened FPGAs Table 3: CQFP Package (CB228) (Continued) Table 3: CQFP Package (CB228) (Continued) Function Pin # Bank # Function Pin # Bank # TDO 172 1 GCK3 202 0 GND 173 VCCINT 203 TDI 174 IO 204 IO_CS 175 IO 205 IO_WRITE 176 IO 206 IO 177 IO_VREF_0 207 IO_VREF_1 178 IO 208 IO 179 IO 209 GND 180 VCCO 210 IO_VREF_1 181 IO 211 IO 182 IO 212 IO 183 IO 213 IO_VREF_1 184 VCCINT 214 IO 185 GND 215 GND 186 IO 216 VCCINT 187 IO_VREF_0 217 IO 188 IO 218 IO 189 IO 219 IO 190 IO_VREF_0 220 VCCO 191 GND 221 IO 192 IO 222 IO 193 IO 223 IO_VREF_1 194 IO_VREF_0 224 IO 195 IO 225 IO 196 IO 226 IO 197 TCK 227 IO 198 VCCO 228 GCK2 199 GND 200 VCCO 201 DS028 (v2.0) January 4, 2010 Product Specification www.xilinx.com 9 R QPro Virtex 2.5V Radiation-Hardened FPGAs Table 4: Pinout Diagram Symbols (Continued) Table 3: CQFP Package (CB228) (Continued) Function Pin # Bank # Symbol GND 1, 8, 14, 27, 42, 48, 56, 66, 72, 86, 100, 106, 113, 123, 129, 143, 157, 163, 173, 180, 186, 200, 215, 221 - v Device-dependent VCCINT, n/c on smaller devices O VCCO R VREF r Device-dependent VREF, remains I/O on smaller devices 15, 30, 41, 73, 83, 99, 130, 140, 156, 187, 203, 214 - G Ground 18, 28, 37, 58, 76, 85, 95, 115, 133, 142, 152, 171, 191, 201, 210, 228 - VCCINT VCCO O, 1, 2, 3 , , , , , , Pin Function Global Clocks M0, M1, M2 D0/DIN, D1, D2, D3, D4, D5, D6, D7 , , , B DOUT/BUSY D DONE Pinout Diagrams P PROGRAM The following diagrams illustrate the locations of specialpurpose pins on Virtex FPGAs. Table 4 lists the symbols used in these diagrams. The diagrams also show I/O-bank boundaries. I INIT K CCLK W WRITE Table 4: Pinout Diagram Symbols S CS T Boundary-scan test access port Symbol 10 Pin Function S General I/O + Temperature diode, anode d Device-dependent general I/O, n/c on smaller devices - Temperature diode, cathode n No connect V VCCINT www.xilinx.com DS028 (v2.0) January 4, 2010 Product Specification R QPro Virtex 2.5V Radiation-Hardened FPGAs CG560 Pin Function Diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Note: CG560 is an obsolete package and is no longer available. It is listed for information purposes only. G G O G O V G O V G R G O G G O r G O P G S O G V G G O G V O v n V G G R O O G R G O r G G OK B T W R r R O T r V Bank 1 R R r Bank 2 R v r R V R R r Bank 3 R R V Bank 4 r I D n V V n R r R G R G G r O G O G G v V O r G V G R O R 3 2 G V R O G R V r O v G G V R r Bank 0 O R G R V Bank 7 CG560 (Top View) Bank 6 Bank 5 O v r V R G O R G 1 V O R O G V R G O v G r R O R G V r V G + r G G r T v R R - R O V V r r O G n r R R R R R V R r V O G O O G r G V O G O R v G V G R G O G T O G O r G V G O G G O G O G O G G A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN DS028 (v2.0) January 4, 2010 Product Specification www.xilinx.com 11 R QPro Virtex 2.5V Radiation-Hardened FPGAs Package Drawing CG560 Ceramic Column Grid Note: CG560 is an obsolete package and is no longer available. It is listed for information purposes only. DS028_01_011900 12 www.xilinx.com DS028 (v2.0) January 4, 2010 Product Specification R QPro Virtex 2.5V Radiation-Hardened FPGAs Device/Package Combinations and Maximum User I/O Maximum User I/O (Excluding Dedicated Clock Pins) Package XQVR300 XQVR600 XQVR1000 CB228 162 162 - CG560(1) - - 404 Notes: 1. Obsolete package. CG560 is no longer available. It is listed for information purposes only. Ordering Information Example: XQVR600 -4 CB 228 V Device Type Manufacturing Grade Number of Pins Speed Grade(1) Package Type Device Ordering Options Device Type Package XQVR300 CB228 XQVR600 CG560(2) Grade 228-pin Ceramic Quad Flat Package M Military Ceramic TC = -55 C to +125 C 560-column Ceramic Column Grid Package V QPro Plus TC = -55 C to +125 C Q MIL-PRF-38535(3) TC = -55 C to +125 C XQVR1000 Notes: 1. -4 is the only supported speed grade. 2. Obsolete package. CG560 is no longer available. It is listed for information purposes only. 3. Class Q must be ordered with the SMD number. Device Ordering Combinations M Grade V Grade XQVR300-4CB228M XQVR300-4CB228V XQVR600-4CB228M XQVR600-4CB228V XQVR1000-4CG560M(1) XQVR1000-4CG560V(1) Notes: 1. Obsolete package. CG560 is no longer available. It is listed for information purposes only. DS028 (v2.0) January 4, 2010 Product Specification www.xilinx.com 13 R QPro Virtex 2.5V Radiation-Hardened FPGAs SMD (Class Q) Ordering Options 5962 R 9957201 Q Y C Generic Standard Microcircuit Drawing (SMD) Lead Finish Package Type Radiation Hardened QML Certified MIL-PRF-38535 Device Type Valid SMD Combinations SMD Number Device Package Markings Lead Finish 5962R9957201QYC XQVR300-4CB228B Lid Gold Plate 5962R9957201QZC XQVR300-4CB228B Base Gold Plate 5962R9957301QYC XQVR600-4CB228B Lid Gold Plate 5962R9957301QZC XQVR600-4CB228B Base Gold Plate 5962R9957401QXA XQVR1000-4CG560B(1) - Solder Column Notes: 1. Obsolete package. CG560 is no longer available. It is listed for information purposes only. 14 www.xilinx.com DS028 (v2.0) January 4, 2010 Product Specification R QPro Virtex 2.5V Radiation-Hardened FPGAs Revision History The following table shows the revision history for this document. Date Version Revision 04/25/00 1.0 Initial Xilinx release. 02/13/01 1.1 Updated Temperature Specifications. 11/05/01 1.2 Updated Temperature Specifications for V600. Added Class V option and SMD. Updated format. 01/04/10 2.0 Changed document classification from Preliminary Product Specification to Product Specification. Added notes indicating that CG560 is obsolete. In Table 1, changed the Maximum Available I/O values to 162 for XQVR300 and XQVR600. Changed the example in Ordering Information. In the Valid SMD Combinations table, changed the last digit of the device numbers to B in the Device column and changed 5962R9957401QXC to 5962R9957401QXA in the SMD Number column. Notice of Disclaimer THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN ("PRODUCTS") ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS. CRITICAL APPLICATIONS DISCLAIMER XILINX PRODUCTS (INCLUDING HARDWARE, SOFTWARE AND/OR IP CORES) ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS IN LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, CLASS III MEDICAL DEVICES, NUCLEAR FACILITIES, APPLICATIONS RELATED TO THE DEPLOYMENT OF AIRBAGS, OR ANY OTHER APPLICATIONS THAT COULD LEAD TO DEATH, PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (INDIVIDUALLY AND COLLECTIVELY, "CRITICAL APPLICATIONS"). FURTHERMORE, XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN ANY APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE OR AIRCRAFT, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR. CUSTOMER AGREES, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE XILINX PRODUCTS, TO THOROUGHLY TEST THE SAME FOR SAFETY PURPOSES. TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW, CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN CRITICAL APPLICATIONS. DS028 (v2.0) January 4, 2010 Product Specification www.xilinx.com 15