935280966151 - NXP SEMICONDUCTORS

1. General description

The LPC2101/02/03 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S CPU with

real-time emulation that combines the microcontroller with 8 kB, 16 kB or 32 kB of

embedded high-speed ﬂash memory. A 128-bit wide memory interface and a unique

accelerator architecture enable 32-bit code execution at the maximum clock rate. For

critical performance in interrupt service routines and DSP algorithms, this increases

performance up to 30 % over Thumb mode. For critical code size applications, the

alternative 16-bit Thumb mode reduces code by more than 30 % with minimal

performance penalty.

Due to their tiny size and low power consumption, the LPC2101/02/03 are ideal for

applications where miniaturization is a key requirement. A blend of serial communications

interfaces ranging from multiple UARTs, SPI to SSP and two I2C-buses, combined with

on-chip SRAM of 2 kB/4 kB/8 kB, make these devices very well suited for communication

gateways and protocol converters. The superior performance also makes these devices

suitable for use as math coprocessors. Various 32-bit and 16-bit timers, an improved

10-bit ADC, PWM features through output match on all timers, and 32 fast GPIO lines with

up to nine edge or level sensitive external interrupt pins make these microcontrollers

particularly suitable for industrial control and medical systems.

2. Features

2.1 Enhanced features

Enhanced features are available in parts LPC2101/02/03 labelled Revision A and higher:

nDeep power-down mode with option to retain SRAM memory and/or RTC.

nThree levels of ﬂash Code Read Protection (CRP) implemented.

2.2 Key features

n16-bit/32-bit ARM7TDMI-S microcontroller in tiny LQFP48 and HVQFN48 packages.

n2 kB/4 kB/8 kB of on-chip static RAM and 8 kB/16 kB/32 kB of on-chip ﬂash program

memory. 128-bit wide interface/accelerator enables high-speed 70 MHz operation.

nISP/IAP via on-chip bootloader software. Single ﬂash sector or full chip erase in

100 ms and programming of 256 bytes in 1 ms.

nEmbeddedICE-RT offers real-time debugging with the on-chip RealMonitor software.

nThe 10-bit ADC provides eight analog inputs, with conversion times as low as 2.44 µs

per channel and dedicated result registers to minimize interrupt overhead.

nTwo 32-bit timers/external event counters with combined seven capture and seven

compare channels.

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers; 8 kB/16 kB/32 kB

ﬂash with ISP/IAP, fast ports and 10-bit ADC

Rev. 04 — 2 June 2009 Product data sheet

Product data sheet Rev. 04 — 2 June 2009 2 of 37

NXP Semiconductors LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

nTwo 16-bit timers/external event counters with combined three capture and seven

compare channels.

nLow power Real-Time Clock (RTC) with independent power and dedicated 32 kHz

clock input.

nMultiple serial interfaces including two UARTs (16C550), two Fast I2C-buses

(400 kbit/s), SPI and SSP with buffering and variable data length capabilities.

nVectored interrupt controller with conﬁgurable priorities and vector addresses.

nUp to thirty-two, 5 V tolerant fast general purpose I/O pins.

nUp to 13 edge or level sensitive external interrupt pins available.

n70 MHz maximum CPU clock available from programmable on-chip PLL with a

possible input frequency of 10 MHz to 25 MHz and a settling time of 100 µs.

nOn-chip integrated oscillator operates with an external crystal in the range from 1 MHz

to 25 MHz.

nPower saving modes include Idle mode, Power-down mode with RTC active, and

Power-down mode.

nIndividual enable/disable of peripheral functions as well as peripheral clock scaling for

additional power optimization.

nProcessor wake-up from Power-down and Deep power-down (Revision A and higher)

mode via external interrupt or RTC.

3. Ordering information

3.1 Ordering options

Table 1. Ordering information

Type number Package

Name Description Version

LPC2101FBD48 LQFP48 plastic low proﬁle quad ﬂat package; 48 leads; body 7 ×7×1.4 mm SOT313-2

LPC2102FBD48 LQFP48 plastic low proﬁle quad ﬂat package; 48 leads; body 7 ×7×1.4 mm SOT313-2

LPC2103FBD48 LQFP48 plastic low proﬁle quad ﬂat package; 48 leads; body 7 ×7×1.4 mm SOT313-2

LPC2102FHN48 HVQFN48 plastic thermal enhanced very thin quad ﬂat package; no leads;

48 terminals; body 7 ×7×0.85 mm SOT619-7

LPC2103FHN48 HVQFN48 plastic thermal enhanced very thin quad ﬂat package; no leads;

48 terminals; body 7 ×7×0.85 mm SOT619-7

LPC2103FHN48H HVQFN48 plastic thermal enhanced very thin quad ﬂat package; no leads;

48 terminals; body 6 × 6 × 0.85 mm SOT778-3

Table 2. Ordering options

Type number Flash memory RAM ADC Temperature

range (°C)

LPC2101FBD48 8 kB 2 kB 8 inputs −40 to +85

LPC2102FBD48 16 kB 4 kB 8 inputs −40 to +85

LPC2103FBD48 32 kB 8 kB 8 inputs −40 to +85

LPC2102FHN48 16 kB 4 kB 8 inputs −40 to +85

LPC2103FHN48 32 kB 8 kB 8 inputs −40 to +85

LPC2103FHN48H 32 kB 8 kB 8 inputs −40 to +85

Product data sheet Rev. 04 — 2 June 2009 3 of 37

NXP Semiconductors LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

4. Block diagram

(1) Pins shared with GPIO.

Fig 1. Block diagram

002aab814

system

clock

TRST

TMS

TCK

TDI

TDO

XTAL2 VDD(3V3)

XTAL1

AMBA AHB

(Advanced High-performance Bus)

MEMORY

ACCELERATOR

AHB BRIDGE

TEST/DEBUG

INTERFACE

AHB TO APB

BRIDGE

VECTORED

INTERRUPT

CONTROLLER

SYSTEM

FUNCTIONS

PLL

8 kB/16 kB/

32 kB FLASH

ARM7TDMI-S

LPC2101/2102/2103

INTERNAL

SRAM

CONTROLLER

2 kB/4 kB/

8 kB SRAM

ARM7 local bus

APB (ARM

peripheral bus) SCL0, SCL1(1)

SDA0, SDA1(1)

3 × CAP0(1)

4 × CAP1(1)

3 × CAP2(1)

3 × MAT0(1)

4 × MAT1(1)

3 × MAT2(1)

4 × MAT3(1)

AD0[7:0]

I2C-BUS SERIAL

INTERFACES 0 AND 1

CAPTURE/COMPARE

EXTERNAL COUNTER

TIMER 0/TIMER 1/

TIMER 2/TIMER 3

EINT2 to

EINT0(1) EXTERNAL

INTERRUPTS

SCK0, SCK1(1)

MOSI0, MOSI1(1)

MISO0, MISO1(1)

SSEL0, SSEL1(1)

SPI AND SSP

SERIAL INTERFACES

ADC

TXD0, TXD1(1)

RXD0, RXD1(1)

UART0/UART1

RTCX2

RTCX1

VBAT

REAL-TIME CLOCK

WATCHDOG

TIMER SYSTEM CONTROL

P0[31:0]

GENERAL

PURPOSE I/O

HIGH SPEED

GENERAL

PURPOSE I/O

RST VSS

8 kB

BOOT ROM

VDD(1V8)

DSR1, CTS1,

RTS1, DTR1

DCD1, RI1

Product data sheet Rev. 04 — 2 June 2009 4 of 37

NXP Semiconductors LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

5. Pinning information

5.1 Pinning

Fig 2. Pin conﬁguration (LQFP48)

LPC2101FBD48

LPC2102FBD48

LPC2103FBD48

P0.19/MAT1.2/MISO1 P0.11/CTS1/CAP1.1/AD0.4

P0.20/MAT1.3/MOSI1 P0.10/RTS1/CAP1.0/AD0.3

P0.21/SSEL1/MAT3.0 P0.24/AD0.2

VBAT P0.23/AD0.1

VDD(1V8) P0.22/AD0.0

RST VSSA

VSS P0.9/RXD1/MAT2.2

P0.27/TRST/CAP2.0 P0.8/TXD1/MAT2.1

P0.28/TMS/CAP2.1 P0.7/SSEL0/MAT2.0

P0.29/TCK/CAP2.2 DBGSEL

XTAL1 RTCK

XTAL2 RTCX2

P0.0/TXD0/MAT3.1 P0.18/CAP1.3/SDA1

P0.1/RXD0/MAT3.2 P0.17/CAP1.2/SCL1

P0.30/TDI/MAT3.3 P0.16/EINT0/MAT0.2

P0.31/TDO P0.15/RI1/EINT2

VDD(3V3) P0.14/DCD1/SCK1/EINT1

P0.2/SCL0/CAP0.0 VSS

VSS VDDA

RTCX1 P0.13/DTR1/MAT1.1

P0.3/SDA0/MAT0.0 VDD(3V3)

P0.4/SCK0/CAP0.1 P0.26/AD0.7

P0.5/MISO0/MAT0.1

P0.6/MOSI0/CAP0.2

P0.25/AD0.6

P0.12/DSR1/MAT1.0/AD0.5

002aab821

Product data sheet Rev. 04 — 2 June 2009 5 of 37

NXP Semiconductors LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

Fig 3. Pin conﬁguration (HVQFN48)

002aad918

LPC2102FHN48

LPC2103FHN48

LPC2103FHN48H

Transparent top view

12 25

11 26

10 27

9 28

8 29

7 30

6 31

5 32

4 33

3 34

2 35

1 36

terminal 1

index area

P0.19/MAT1.2/MISO1

P0.20/MAT1.3/MOSI1

P0.21/SSEL1/MAT3.0

VBAT

VDD(1V8)

RST

VSS

P0.27/TRST/CAP2.0

P0.28/TMS/CAP2.1

P0.29/TCK/CAP2.2

XTAL1

XTAL2

P0.18/CAP1.3/SDA1

P0.17/CAP1.2/SCL1

P0.16/EINT0/MAT0.2

P0.15/RI1/EINT2

P0.14/DCD1/SCK1/EINT1

VSS

VDDA

P0.13/DTR1/MAT1.1

VDD(3V3)

P0.26/AD0.7

P0.25/AD0.6

P0.12/DSR1/MAT1.0/AD0.5

P0.11/CTS1/CAP1.1/AD0.4

P0.10/RTS1/CAP1.0/AD0.3

P0.24/AD0.2

P0.23/AD0.1

P0.22/AD0.0

VSSA

P0.9/RXD1/MAT2.2

P0.8/TXD1/MAT2.1

P0.7/SSEL0/MAT2.0

DBGSEL

RTCK

RTCX2

P0.0/TXD0/MAT3.1

P0.1/RXD0/MAT3.2

P0.30/TDI/MAT3.3

P0.31/TDO

VDD(3V3)

P0.2/SCL0/CAP0.0

VSS

RTCX1

P0.3/SDA0/MAT0.0

P0.4/SCK0/CAP0.1

P0.5/MISO0/MAT0.1

P0.6/MOSI0/CAP0.2

Product data sheet Rev. 04 — 2 June 2009 6 of 37

NXP Semiconductors LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

5.2 Pin description

Table 3. Pin description

Symbol Pin Type Description

P0.0 to P0.31 I/O Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit.

A total of 31 pins of the Port 0 can be used as general purpose bidirectional

digital I/Os while P0.31 is an output only pin. The operation of port 0 pins

depends upon the pin function selected via the pin connect block.

P0.0/TXD0/

MAT3.1 13[1] I/O P0.0 — General purpose input/output digital pin.

OTXD0 — Transmitter output for UART0.

OMAT3.1 — PWM output 1 for Timer 3.

P0.1/RXD0/

MAT3.2 14[1] I/O P0.1 — General purpose input/output digital pin.

IRXD0 — Receiver input for UART0.

OMAT3.2 — PWM output 2 for Timer 3.

P0.2/SCL0/

CAP0.0 18[2] I/O P0.2 — General purpose input/output digital pin. Output is open-drain.

I/O SCL0 — I2C0 clock Input/output. Open-drain output (for I2C-bus compliance).

ICAP0.0 — Capture input for Timer 0, channel 0.

P0.3/SDA0/

MAT0.0 21[2] I/O P0.3 — General purpose input/output digital pin. Output is open-drain.

I/O SDA0 — I2C0 data input/output. Open-drain output (for I2C-bus compliance).

OMAT0.0 — PWM output for Timer 0, channel 0. Output is open-drain.

P0.4/SCK0/

CAP0.1 22[1] I/O P0.4 — General purpose input/output digital pin.

I/O SCK0 — Serial clock for SPI0. SPI clock output from master or input to slave.

ICAP0.1 — Capture input for Timer 0, channel 1.

P0.5/MISO0/

MAT0.1 23[1] I/O P0.5 — General purpose input/output digital pin.

I/O MISO0 — Master In Slave Out for SPI0. Data input to SPI master or data

output from SPI slave.

OMAT0.1 — PWM output for Timer 0, channel 1.

P0.6/MOSI0/

CAP0.2 24[1] I/O P0.6 — General purpose input/output digital pin.

I/O MOSI0 — Master Out Slave In for SPI0. Data output from SPI master or data

input to SPI slave.

ICAP0.2 — Capture input for Timer 0, channel 2.

P0.7/SSEL0/

MAT2.0 28[1] I/O P0.7 — General purpose input/output digital pin.

ISSEL0 — Slave Select for SPI0. Selects the SPI interface as a slave.

OMAT2.0 — PWM output for Timer 2, channel 0.

P0.8/TXD1/

MAT2.1 29[1] I/O P0.8 — General purpose input/output digital pin.

OTXD1 — Transmitter output for UART1.

OMAT2.1 — PWM output for Timer 2, channel 1.

P0.9/RXD1/

MAT2.2 30[1] I/O P0.9 — General purpose input/output digital pin.

IRXD1 — Receiver input for UART1.

OMAT2.2 — PWM output for Timer 2, channel 2.

P0.10/RTS1/

CAP1.0/AD0.3 35[3] I/O P0.10 — General purpose input/output digital pin.

ORTS1 — Request to Send output for UART1.

ICAP1.0 — Capture input for Timer 1, channel 0.

IAD0.3 — ADC 0, input 3.

Product data sheet Rev. 04 — 2 June 2009 7 of 37

NXP Semiconductors LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

P0.11/CTS1/

CAP1.1/AD0.4 36[3] I/O P0.11 — General purpose input/output digital pin.

ICTS1 — Clear to Send input for UART1.

ICAP1.1 — Capture input for Timer 1, channel 1.

IAD0.4 — ADC 0, input 4.

P0.12/DSR1/

MAT1.0/AD0.5 37[3] I/O P0.12 — General purpose input/output digital pin.

IDSR1 — Data Set Ready input for UART1.

OMAT1.0 — PWM output for Timer 1, channel 0.

IAD0.5 — ADC 0, input 5.

P0.13/DTR1/

MAT1.1 41[1] I/O P0.13 — General purpose input/output digital pin.

ODTR1 — Data Terminal Ready output for UART1.

OMAT1.1 — PWM output for Timer 1, channel 1.

P0.14/DCD1/

SCK1/EINT1 44[4][5] I/O P0.14 — General purpose input/output digital pin.

IDCD1 — Data Carrier Detect input for UART1.

I/O SCK1 — Serial Clock for SPI1. SPI clock output from master or input to slave.

IEINT1 — External interrupt 1 input.

P0.15/RI1/

EINT2 45[4] I/O P0.15 — General purpose input/output digital pin.

IRI1 — Ring Indicator input for UART1.

IEINT2 — External interrupt 2 input.

P0.16/EINT0/

MAT0.2 46[4] I/O P0.16 — General purpose input/output digital pin.

IEINT0 — External interrupt 0 input.

OMAT0.2 — PWM output for Timer 0, channel 2.

P0.17/CAP1.2/

SCL1 47[6] I/O P0.17 — General purpose input/output digital pin. The output is not

open-drain.

ICAP1.2 — Capture input for Timer 1, channel 2.

I/O SCL1 — I2C1 clock Input/output. This pin is an open-drain output if I2C1

function is selected in the pin connect block.

P0.18/CAP1.3/

SDA1 48[6] I/O P0.18 — General purpose input/output digital pin. The output is not

open-drain.

ICAP1.3 — Capture input for Timer 1, channel 3.

I/O SDA1 — I2C1 data Input/output. This pin is an open-drain output if I2C1

function is selected in the pin connect block.

P0.19/MAT1.2/

MISO1 1[1] I/O P0.19 — General purpose input/output digital pin.

OMAT1.2 — PWM output for Timer 1, channel 2.

I/O MISO1 — Master In Slave Out for SSP. Data input to SSP master or data

output from SSP slave.

P0.20/MAT1.3/

MOSI1 2[1] I/O P0.20 — General purpose input/output digital pin.

OMAT1.3 — PWM output for Timer 1, channel 3.

I/O MOSI1 — Master Out Slave for SSP. Data output from SSP master or data

input to SSP slave.

P0.21/SSEL1/

MAT3.0 3[1] I/O P0.21 — General purpose input/output digital pin.

ISSEL1 — Slave Select for SPI1. Selects the SPI interface as a slave.

OMAT3.0 — PWM output for Timer 3, channel 0.

Table 3. Pin description

…continued

Symbol Pin Type Description

Product data sheet Rev. 04 — 2 June 2009 8 of 37

NXP Semiconductors LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

P0.22/AD0.0 32[3] I/O P0.22 — General purpose input/output digital pin.

IAD0.0 — ADC 0, input 0.

P0.23/AD0.1 33[3] I/O P0.23 — General purpose input/output digital pin.

IAD0.1 — ADC 0, input 1.

P0.24/AD0.2 34[3] I/O P0.24 — General purpose input/output digital pin.

IAD0.2 — ADC 0, input 2.

P0.25/AD0.6 38[3] I/O P0.25 — General purpose input/output digital pin.

IAD0.6 — ADC 0, input 6.

P0.26/AD0.7 39[3] I/O P0.26 — General purpose input/output digital pin.

IAD0.7 — ADC 0, input 7.

P0.27/TRST/

CAP2.0 8[1] I/O P0.27 — General purpose input/output digital pin.

ITRST — Test Reset for JTAG interface. If DBGSEL is HIGH, this pin is

automatically conﬁgured for use with EmbeddedICE (Debug mode).

ICAP2.0 — Capture input for Timer 2, channel 0.

P0.28/TMS/

CAP2.1 9[1] I/O P0.28 — General purpose input/output digital pin.

ITMS — Test Mode Select for JTAG interface. If DBGSEL is HIGH, this pin is

automatically conﬁgured for use with EmbeddedICE (Debug mode).

ICAP2.1 — Capture input for Timer 2, channel 1.

P0.29/TCK/

CAP2.2 10[1] I/O P0.29 — General purpose input/output digital pin.

ITCK — Test Clock for JTAG interface. This clock must be slower than 1⁄6of the

CPU clock (CCLK) for the JTAG interface to operate. If DBGSEL is HIGH, this

pin is automatically conﬁgured for use with EmbeddedICE (Debug mode).

ICAP2.2 — Capture input for Timer 2, channel 2.

P0.30/TDI/

MAT3.3 15[1] I/O P0.30 — General purpose input/output digital pin.

ITDI — Test Data In for JTAG interface. If DBGSEL is HIGH, this pin is

automatically conﬁgured for use with EmbeddedICE (Debug mode).

OMAT3.3 — PWM output 3 for Timer 3.

P0.31/TDO 16[1] OP0.31 — General purpose output only digital pin.

OTDO — Test Data Out for JTAG interface. If DBGSEL is HIGH, this pin is

automatically conﬁgured for use with EmbeddedICE (Debug mode).

RTCX1 20[7][8] I Input to the RTC oscillator circuit. Input voltage must not exceed 1.8 V.

RTCX2 25[7][8] O Output from the RTC oscillator circuit.

RTCK 26[7] I/O Returned test clock output: Extra signal added to the JTAG port. Assists

debugger synchronization when processor frequency varies. Bidirectional pin

with internal pull-up.

XTAL1 11 I Input to the oscillator circuit and internal clock generator circuits. Input voltage

must not exceed 1.8 V.

XTAL2 12 O Output from the oscillator ampliﬁer.

DBGSEL 27 I Debug select: When LOW, the part operates normally. When externally

pulled HIGH at reset, P0.27 to P0.31 are conﬁgured as JTAG port, and the

part is in Debug mode[9]. Input with internal pull-down.

RST 6 I External reset input: A LOW on this pin resets the device, causing I/O ports

and peripherals to take on their default states and processor execution to

begin at address 0. TTL with hysteresis, 5 V tolerant.

Table 3. Pin description

…continued

Symbol Pin Type Description

Product data sheet Rev. 04 — 2 June 2009 9 of 37

NXP Semiconductors LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

[1] 5 V tolerant (if VDD(3V3) and VDDA ≥ 3.0 V) pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.

[2] Open-drain 5 V tolerant (if VDD(3V3) and VDDA ≥ 3.0 V) digital I/O I2C-bus 400 kHz speciﬁcation compatible pad. It requires external

pull-up to provide an output functionality. Open-drain conﬁguration applies to ALL functions on that pin.

[3] 5 V tolerant (if VDD(3V3) and VDDA ≥ 3.0 V) pad providing digital I/O (with TTL levels and hysteresis and 10 ns slew rate control) and

analog input function. If conﬁgured for an input function, this pad utilizes built-in glitch ﬁlter that blocks pulses shorter than 3 ns. When

conﬁgured as an ADC input, digital section of the pad is disabled.

[4] 5 V tolerant (if VDD(3V3) and VDDA ≥3.0 V) pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.

If conﬁgured for an input function, this pad utilizes built-in glitch ﬁlter that blocks pulses shorter than 3 ns.

[5] A LOW level during reset on pin P0.14 is considered as an external hardware request to start the ISP command handler.

[6] Open-drain 5 V tolerant (if VDD(3V3) and VDDA ≥ 3.0 V) digital I/O I2C-bus 400 kHz speciﬁcation compatible pad. It requires external

pull-up to provide an output functionality. Open-drain conﬁguration applies only to I2C function on that pin.

[7] Pad provides special analog functionality.

[8] For lowest power consumption, pin should be left ﬂoating when the RTC is not used.

[9] See

LPC2101/02/03 User manual UM10161

for details.

VSS 7, 19, 43 I Ground: 0 V reference.

VSSA 31 I Analog ground: 0 V reference. This should be nominally the same voltage as

VSS but should be isolated to minimize noise and error.

VDDA 42 I Analog 3.3 V power supply: This should be nominally the same voltage as

VDD(3V3) but should be isolated to minimize noise and error. The level on this

pin also provides a voltage reference level for the ADC.

VDD(1V8) 5I1.8 V core power supply: This is the power supply voltage for internal

circuitry and the on-chip PLL.

VDD(3V3) 17, 40 I 3.3 V pad power supply: This is the power supply voltage for the I/O ports.

VBAT 4 I RTC power supply: 3.3 V on this pin supplies the power to the RTC.

Table 3. Pin description

…continued

Symbol Pin Type Description

Product data sheet Rev. 04 — 2 June 2009 10 of 37

NXP Semiconductors LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

6. Functional description

6.1 Architectural overview

The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high

performance and very low power consumption. The ARM architecture is based on

Reduced Instruction Set Computer (RISC) principles, and the instruction set and related

decode mechanism are much simpler than those of microprogrammed Complex

Instruction Set Computers (CISC). This simplicity results in a high instruction throughput

and impressive real-time interrupt response from a small and cost-effective processor

core.

Pipeline techniques are employed so that all parts of the processing and memory systems

can operate continuously. Typically, while one instruction is being executed, its successor

is being decoded, and a third instruction is being fetched from memory.

The ARM7TDMI-S processor also employs a unique architectural strategy known as

Thumb, which makes it ideally suited to high-volume applications with memory

restrictions, or applications where code density is an issue.

The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the

ARM7TDMI-S processor has two instruction sets:

•The standard 32-bit ARM set.

•A 16-bit Thumb set.

The Thumb set’s 16-bit instruction length allows it to approach twice the density of

standard ARM code while retaining most of the ARM’s performance advantage over a

traditional 16-bit processor using 16-bit registers. This is possible because Thumb code

operates on the same 32-bit register set as ARM code.

Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the

performance of an equivalent ARM processor connected to a 16-bit memory system.

The particular ﬂash implementation in the LPC2101/02/03 allows for full speed execution

also in ARM mode. It is recommended to program performance critical and short code

sections in ARM mode. The impact on the overall code size will be minimal but the speed

can be increased by 30 % over Thumb mode.

6.2 On-chip ﬂash program memory

The LPC2101/02/03 incorporate a 8 kB, 16 kB or 32 kB ﬂash memory system

respectively. This memory may be used for both code and data storage. Programming of

the ﬂash memory may be accomplished in several ways. It may be programmed in system

via the serial port. The application program may also erase and/or program the ﬂash while

the application is running, allowing a great degree of ﬂexibility for data storage ﬁeld

ﬁrmware upgrades, etc. The entire ﬂash memory is available for user code as the

bootloader resides in a separate memory.

The LPC2101/02/03 ﬂash memory provides a minimum of 100,000 erase/write cycles and

20 years of data-retention memory.

Product data sheet Rev. 04 — 2 June 2009 11 of 37

NXP Semiconductors LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

6.3 On-chip static RAM

On-chip static RAM may be used for code and/or data storage. The SRAM may be

accessed as 8-bits, 16-bits, and 32-bits. The LPC2101/02/03 provide 2 kB, 4 kB or 8 kB of

static RAM.

6.4 Memory map

The LPC2101/02/03 memory map incorporates several distinct regions, as shown in

Figure 4.

In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in either

ﬂash memory (the default) or on-chip static RAM. This is described in Section 6.17

“System control”.

Fig 4. LPC2101/02/03 memory map

AHB PERIPHERALS

APB PERIPHERALS

RESERVED ADDRESS SPACE

BOOT BLOCK

RESERVED ADDRESS SPACE

8 kB ON-CHIP STATIC RAM (LPC2103)

2 kB ON-CHIP STATIC RAM (LPC2101)

32 kB ON-CHIP NON-VOLATILE MEMORY

(LPC2103)

0xFFFF FFFF

0xF000 0000

0xE000 0000

0xC000 0000

0x8000 0000

0x7FFF FFFF

0x4000 1000

0x4000 07FF

0x4000 2000

0x4000 1FFF

4 kB ON-CHIP STATIC RAM (LPC2102) 0x4000 0800

0x4000 0FFF

0x7FFF E000

0x7FFF DFFF

0x4000 0000

0x0000 8000

0x0000 7FFF

0x0000 4000

4.0 GB

3.75 GB

3.5 GB

3.0 GB

2.0 GB

1.0 GB

16 kB ON-CHIP NON-VOLATILE MEMORY

(LPC2102) 0x0000 3FFF

0x0000 2000

8 kB ON-CHIP NON-VOLATILE MEMORY

(LPC2101) 0x0000 1FFF

0x0000 0000

0.0 GB

002aab822

Product data sheet Rev. 04 — 2 June 2009 12 of 37

NXP Semiconductors LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

6.5 Interrupt controller

The VIC accepts all of the interrupt request inputs and categorizes them as FIQ, vectored

IRQ, and non-vectored IRQ as deﬁned by programmable settings. The programmable

assignment scheme means that priorities of interrupts from the various peripherals can be

dynamically assigned and adjusted.

FIQ has the highest priority. If more than one request is assigned to FIQ, the VIC

combines the requests to produce the FIQ signal to the ARM processor. The fastest

possible FIQ latency is achieved when only one request is classiﬁed as FIQ, because then

the FIQ service routine does not need to branch into the interrupt service routine but can

run from the interrupt vector location. If more than one request is assigned to the FIQ

class, the FIQ service routine will read a word from the VIC that identiﬁes which FIQ

source(s) is (are) requesting an interrupt.

Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned

to this category. Any of the interrupt requests can be assigned to any of the 16 vectored

IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest.

Non-vectored IRQs have the lowest priority.

The VIC combines the requests from all the vectored and non-vectored IRQs to produce

the IRQ signal to the ARM processor. The IRQ service routine can start by reading a

provides the address of the highest-priority requesting IRQs service routine, otherwise it

provides the address of a default routine that is shared by all the non-vectored IRQs. The

default routine can read another VIC register to see what IRQs are active.

6.5.1 Interrupt sources

Each peripheral device has one interrupt line connected to the Vectored Interrupt

Controller, but may have several internal interrupt ﬂags. Individual interrupt ﬂags may also

represent more than one interrupt source.

6.6 Pin connect block

The pin connect block allows selected pins of the microcontroller to have more than one

function. Conﬁguration registers control the multiplexers to allow connection between the

pin and the on chip peripherals. Peripherals should be connected to the appropriate pins

prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any

enabled peripheral function that is not mapped to a related pin should be considered

undeﬁned.

The pin control module with its pin select registers deﬁnes the functionality of the

microcontroller in a given hardware environment.

After reset all pins of Port 0 are conﬁgured as input with the following exceptions: If the

DBGSEL pin is HIGH (Debug mode enabled), the JTAG pins will assume their JTAG

functionality for use with EmbeddedICE and cannot be conﬁgured via the pin connect

block.

Product data sheet Rev. 04 — 2 June 2009 13 of 37

NXP Semiconductors LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

6.7 Fast general purpose parallel I/O

Device pins that are not connected to a speciﬁc peripheral function are controlled by the

GPIO registers. Pins may be dynamically conﬁgured as inputs or outputs. Separate

registers allow setting or clearing any number of outputs simultaneously. The value of the

output register may be read back, as well as the current state of the port pins.

LPC2101/02/03 introduce accelerated GPIO functions over prior LPC2000 devices:

•GPIO registers are relocated to the ARM local bus for the fastest possible I/O timing.

•Mask registers allow treating sets of port bits as a group, leaving other bits

unchanged.

•All GPIO registers are byte addressable.

•Entire port value can be written in one instruction.

6.7.1 Features

•Bit-level set and clear registers allow a single instruction set or clear of any number of

bits in one port.

•Direction control of individual bits.

•Separate control of output set and clear.

•All I/O default to inputs after reset.

6.8 10-bit ADC

The LPC2101/02/03 contain one ADC. It is a single 10-bit successive approximation ADC

with eight channels.

6.8.1 Features

•Measurement range of 0 V to 3.3 V.

•Each converter capable of performing more than 400,000 10-bit samples per second.

•Burst conversion mode for single or multiple inputs.

•Optional conversion on transition on input pin or Timer Match signal.

•Every analog input has a dedicated result register to reduce interrupt overhead.

6.9 UARTs

The LPC2101/02/03 each contain two UARTs. In addition to standard transmit and

receive data lines, UART1 also provides a full modem control handshake interface.

Compared to previous LPC2000 microcontrollers, UARTs in LPC2101/02/03 include a

fractional baud rate generator for both UARTs. Standard baud rates such as 115200 can

be achieved with any crystal frequency above 2 MHz.

6.9.1 Features

•16 byte Receive and Transmit FIFOs.

•Register locations conform to 16C550 industry standard.

•Receiver FIFO trigger points at 1, 4, 8, and 14 bytes

Product data sheet Rev. 04 — 2 June 2009 14 of 37

NXP Semiconductors LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

•Built-in fractional baud rate generator covering wide range of baud rates without a

need for external crystals of particular values.

•Transmission FIFO control enables implementation of software (XON/XOFF) ﬂow

control on both UARTs.

•UART1 is equipped with standard modem interface signals. This module also

provides full support for hardware ﬂow control (auto-CTS/RTS).

6.10 I2C-bus serial I/O controllers

The LPC2101/02/03 each contain two I2C-bus controllers.

The I2C-bus is bidirectional, for inter-IC control using only two wires: a Serial Clock Line

(SCL), and a Serial Data Line (SDA). Each device is recognized by a unique address and

can operate as either a receiver-only device (e.g., LCD driver) or a transmitter with the

capability to both receive and send information such as serial memory. Transmitters

and/or receivers can operate in either master or slave mode, depending on whether the

chip has to initiate a data transfer or is only addressed. The I2C-bus is a multi-master bus,

it can be controlled by more than one bus master connected to it.

The I2C-bus implemented in LPC2101/02/03 supports bit rates up to 400 kbit/s (Fast

I2C-bus).

6.10.1 Features

•Compliant with standard I2C-bus interface.

•Easy to conﬁgure as Master, Slave, or Master/Slave.

•Programmable clocks allow versatile rate control.

•Bidirectional data transfer between masters and slaves.

•Multi-master bus (no central master).

•Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

•Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

•Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer.

•The I2C-bus can also be used for test and diagnostic purposes.

6.11 SPI serial I/O controller

The LPC2101/02/03 each contain one SPI controller. The SPI is a full duplex serial

interface, designed to handle multiple masters and slaves connected to a given bus. Only

a single master and a single slave can communicate on the interface during a given data

transfer. During a data transfer the master always sends 8 bits to 16 bits of data to the

slave, and the slave always sends 8 bits to 16 bits of data to the master.

6.11.1 Features

•Compliant with SPI speciﬁcation.

•Synchronous, Serial, Full Duplex, Communication.

Product data sheet Rev. 04 — 2 June 2009 15 of 37

NXP Semiconductors LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

•Combined SPI master and slave.

•Maximum data bit rate of one eighth of the input clock rate.

6.12 SSP serial I/O controller

The LPC2101/02/03 each contain one SSP. The SSP controller is capable of operation on

a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the

bus. However, only a single master and a single slave can communicate on the bus during

a given data transfer. The SSP supports full duplex transfers, with data frames of 4 bits to

16 bits ﬂowing from the master to the slave and from the slave to the master. Often only

one of these data streams carries meaningful data.

6.12.1 Features

•Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National

Semiconductor’s Microwire buses

•Synchronous serial communication

•Master or slave operation

•8-frame FIFOs for both transmit and receive

•Four bits to 16 bits per frame

6.13 General purpose 32-bit timers/external event counters

The Timer/Counter is designed to count cycles of the Peripheral Clock (PCLK) or an

externally supplied clock and optionally generate interrupts or perform other actions at

speciﬁed timer values, based on four match registers. It also includes four capture inputs

to trap the timer value when an input signal transitions, optionally generating an interrupt.

Multiple pins can be selected to perform a single capture or match function, providing an

application with ‘or’ and ‘and’, as well as ‘broadcast’ functions among them.

The LPC2101/02/03 can count external events on one of the capture inputs if the

minimum external pulse is equal or longer than a period of the PCLK. In this conﬁguration,

unused capture lines can be selected as regular timer capture inputs or used as external

interrupts.

6.13.1 Features

•A 32-bit timer/counter with a programmable 32-bit prescaler.

•External event counter or timer operation.

•Four 32-bit capture channels per timer/counter that can take a snapshot of the timer

value when an input signal transitions. A capture event may also optionally generate

an interrupt.

•Four 32-bit match registers that allow:

–Continuous operation with optional interrupt generation on match.

–Stop timer on match with optional interrupt generation.

–Reset timer on match with optional interrupt generation.

•Four external outputs per timer/counter corresponding to match registers, with the

following capabilities:

–Set LOW on match.

Product data sheet Rev. 04 — 2 June 2009 16 of 37

NXP Semiconductors LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

–Set HIGH on match.

–Toggle on match.

–Do nothing on match.

6.14 General purpose 16-bit timers/external event counters

The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an

externally supplied clock and optionally generate interrupts or perform other actions at

speciﬁed timer values, based on four match registers. It also includes three capture inputs

to trap the timer value when an input signal transitions, optionally generating an interrupt.

Multiple pins can be selected to perform a single capture or match function, providing an

application with ‘or’ and ‘and’, as well as ‘broadcast’ functions among them.

The LPC2101/02/03 can count external events on one of the capture inputs if the

minimum external pulse is equal or longer than a period of the PCLK. In this conﬁguration,

unused capture lines can be selected as regular timer capture inputs or used as external

interrupts.

6.14.1 Features

•Two 16-bit timer/counters with a programmable 16-bit prescaler.

•External event counter or timer operation.

•Three 16-bit capture channels that can take a snapshot of the timer value when an

input signal transitions. A capture event may also optionally generate an interrupt.

•Four 16-bit match registers that allow:

–Continuous operation with optional interrupt generation on match.

–Stop timer on match with optional interrupt generation.

–Reset timer on match with optional interrupt generation.

•Four external outputs per timer/counter corresponding to match registers, with the

following capabilities:

–Set LOW on match.

–Set HIGH on match.

–Toggle on match.

–Do nothing on match.

6.15 Watchdog timer

The purpose of the watchdog is to reset the microcontroller within a reasonable amount of

time if it enters an erroneous state. When enabled, the watchdog will generate a system

reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined

amount of time.

6.15.1 Features

•Internally resets chip if not periodically reloaded.

•Debug mode.

•Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be

disabled.

Product data sheet Rev. 04 — 2 June 2009 17 of 37

NXP Semiconductors LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

•Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.

•Flag to indicate watchdog reset.

•Programmable 32-bit timer with internal pre-scaler.

•Selectable time period from (TPCLK × 256 × 4) to (TPCLK × 232 × 4) in multiples of

TPCLK ×4.

6.16 Real-time clock

The Real-Time Clock (RTC) is designed to provide a set of counters to measure time

when normal or idle operating mode is selected. The RTC has been designed to use little

power, making it suitable for battery powered systems where the CPU is not running

continuously (Idle mode).

6.16.1 Features

•Measures the passage of time to maintain a calendar and clock.

•Ultra-low power design to support battery powered systems.

•Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day

of Year.

•Can use either the RTC dedicated 32 kHz oscillator input or clock derived from the

external crystal/oscillator input at XTAL1. The programmable reference clock divider

allows ﬁne adjustment of the RTC.

•Dedicated power supply pin can be connected to a battery or the main 3.3 V.

6.17 System control

6.17.1 Crystal oscillator

The on-chip integrated oscillator operates with external crystal in range of 1 MHz to

25 MHz. The oscillator output frequency is called fosc and the ARM processor clock

frequency is referred to as CCLK for purposes of rate equations, etc. fosc and CCLK are

the same value unless the PLL is running and connected. Refer to Section 6.17.2 “PLL”

and Section 10.1 “XTAL1 input” for additional information.

6.17.2 PLL

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input

frequency is multiplied up into the range of 10 MHz to 70 MHz with a Current Controlled

Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the

multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper

frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so

there is an additional divider in the loop to keep the CCO within its frequency range while

the PLL is providing the desired output frequency. The output divider may be set to divide

by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2,

it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and

bypassed following a chip reset and may be enabled by software. The program must

conﬁgure and activate the PLL, wait for the PLL to lock, and then connect to the PLL as a

clock source. The PLL settling time is 100 µs.

Product data sheet Rev. 04 — 2 June 2009 18 of 37

NXP Semiconductors LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

6.17.3 Reset and wake-up timer

Reset has two sources on the LPC2101/02/03: the RST pin and watchdog reset. The RST

pin is a Schmitt trigger input pin with an additional glitch ﬁlter. Assertion of chip reset by

any source starts the wake-up timer (see wake-up timer description below), causing the

internal chip reset to remain asserted until the external reset is de-asserted, the oscillator

is running, a ﬁxed number of clocks have passed, and the on-chip ﬂash controller has

completed its initialization.

When the internal reset is removed, the processor begins executing at address 0, which is

the reset vector. At that point, all of the processor and peripheral registers have been

initialized to predetermined reset values.

The wake-up timer ensures that the oscillator and other analog functions required for chip

operation are fully functional before the processor is allowed to execute instructions. This

is important at power on, all types of reset, and whenever any of the aforementioned

functions are turned off for any reason. Since the oscillator and other functions are turned

off during Power-down and Deep power-down mode, any wake-up of the processor from

the Power-down modes makes use of the wake-up timer.

The wake-up timer monitors the crystal oscillator as the means of checking whether it is

safe to begin code execution. When power is applied to the chip, or some event caused

the chip to exit Power-down mode, some time is required for the oscillator to produce a

signal of sufﬁcient amplitude to drive the clock logic. The amount of time depends on

many factors, including the rate of VDD ramp (in the case of power on), the type of crystal

and its electrical characteristics (if a quartz crystal is used), as well as any other external

circuitry (e.g., capacitors), and the characteristics of the oscillator itself under the existing

ambient conditions.

Product data sheet Rev. 04 — 2 June 2009 19 of 37

NXP Semiconductors LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

6.17.4 Code security (Code Read Protection - CRP)

This feature of the LPC2101/02/03 allows user to enable different levels of security in the

system so that access to the on-chip ﬂash and use of the JTAG and ISP can be restricted.

When needed, CRP is invoked by programming a speciﬁc pattern into a dedicated ﬂash

location. IAP commands are not affected by the CRP.

Implemented in bootloader code version 2.21 are three levels of the Code Read

Protection:

1. CRP1 disables access to chip via the JTAG and allows partial ﬂash update (excluding

ﬂash sector 0) using a limited set of the ISP commands. This mode is useful when

CRP is required and ﬂash ﬁeld updates are needed but all sectors cannot be erased.

2. CRP2 disables access to chip via the JTAG and only allows full ﬂash erase and

update using a reduced set of the ISP commands.

3. Running an application with level CRP3 selected fully disables any access to chip via

the JTAG pins and the ISP. This mode effectively disables ISP override using P0.14

pin, too. It is up to the user’s application to provide (if needed) ﬂash update

mechanism using IAP calls or call reinvoke ISP command to enable ﬂash update via

UART0.

Remark: Parts LPC2101/02/03 Revision ‘-’ have CRP2 enabled only (bootloader code

version 2.2).

6.17.5 External interrupt inputs

The LPC2101/02/03 include up to three edge or level sensitive external interrupt inputs as

selectable pin functions. When the pins are combined, external events can be processed

as three independent interrupt signals. The external interrupt inputs can optionally be

used to wake-up the processor from Power-down mode and Deep power-down mode.

Additionally all 10 capture input pins can also be used as external interrupts without the

option to wake the device up from Power-down mode.

6.17.6 Memory mapping control

The memory mapping control alters the mapping of the interrupt vectors that appear

beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip

ﬂash memory, or to the on-chip static RAM. This allows code running in different memory

spaces to have control of the interrupts.

6.17.7 Power control

The LPC2101/02/03 supports three reduced power modes: Idle mode, Power-down

mode, and Deep power-down mode.

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.

Product data sheet Rev. 04 — 2 June 2009 20 of 37

NXP Semiconductors LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

In Idle mode, execution of instructions is suspended until either a reset or interrupt occurs.

Peripheral functions continue operation during Idle mode and may generate interrupts to

cause the processor to resume execution. Idle mode eliminates power used by the

processor itself, memory systems and related controllers, and internal buses.

In Power-down mode, the oscillator is shut down and the chip receives no internal clocks.

The processor state and registers, peripheral registers, and internal SRAM values are

preserved throughout Power-down mode and the logic levels of chip output pins remain

static. The Power-down mode can be terminated and normal operation resumed by either

a reset or certain speciﬁc interrupts that are able to function without clocks. Since all

dynamic operation of the chip is suspended, Power-down mode reduces chip power

consumption to nearly zero.

Selecting an external 32 kHz clock instead of the PCLK as a clock-source for the on-chip

RTC will enable the microcontroller to have the RTC active during Power-down mode.

Power-down current is increased with RTC active. However, it is signiﬁcantly lower than in

Idle mode.

In Deep-power down mode all power is removed from the internal chip logic except for the

RTC module, the I/O ports, the SRAM, and the 32 kHz external oscillator. For additional

power savings, SRAM and the 32 kHz oscillator can be powered down individually. The

Deep power-down mode produces the lowest possible power consumption without

actually removing power from the entire chip. In Deep power-down mode, the contents of

registers and memory are not preserved except for SRAM, if selected, and three general

purpose registers. Therefore, to resume operations, a full chip reset process is required.

A power selector module switches the RTC power supply from VBAT to VDD(1V8) whenever

the core voltage is present on pin VDD(1V8) to conserve battery power.

A power control for peripherals feature allows individual peripherals to be turned off if they

are not needed in the application, resulting in additional power savings during Active and

Idle mode.

6.17.8 APB

The APB divider determines the relationship between the processor clock (CCLK) and the

clock used by peripheral devices (PCLK). The APB divider serves two purposes. The ﬁrst

is to provide peripherals with the desired PCLK via APB so that they can operate at the

speed chosen for the ARM processor. In order to achieve this, the APB may be slowed

down to 1⁄2 to 1⁄4 of the processor clock rate. Because the APB must work properly at

power-up (and its timing cannot be altered if it does not work since the APB divider control

registers reside on the APB), the default condition at reset is for the APB to run at 1⁄4of the

processor clock rate. The second purpose of the APB divider is to allow power savings

when an application does not require any peripherals to run at the full processor rate.

Because the APB divider is connected to the PLL output, the PLL remains active (if it was

running) during Idle mode.

6.18 Emulation and debugging

The LPC2101/02/03 support emulation and debugging via a JTAG serial port.

Product data sheet Rev. 04 — 2 June 2009 21 of 37

NXP Semiconductors LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

6.18.1 EmbeddedICE

Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of

the target system requires a host computer running the debugger software and an

EmbeddedICE protocol converter. The EmbeddedICE protocol converter converts the

remote debug protocol commands to the JTAG data needed to access the ARM core.

The ARM core has a debug communication channel function built-in. The debug

communication channel allows a program running on the target to communicate with the

host debugger or another separate host without stopping the program ﬂow or even

entering the debug state. The debug communication channel is accessed as a

coprocessor 14 by the program running on the ARM7TDMI-S core. The debug

communication channel allows the JTAG port to be used for sending and receiving data

without affecting the normal program ﬂow. The debug communication channel data and

control registers are mapped in to addresses in the EmbeddedICE logic. The JTAG clock

(TCK) must be slower than 1⁄6 of the CPU clock (CCLK) for the JTAG interface to operate.

6.18.2 RealMonitor

RealMonitor is a conﬁgurable software module, developed by ARM Inc., which enables

real time debug. It is a lightweight debug monitor that runs in the background while users

debug their foreground application. It communicates with the host using the DCC, which is

present in the EmbeddedICE logic. The LPC2101/02/03 contain a speciﬁc conﬁguration of

RealMonitor software programmed into the on-chip boot ROM memory.

Product data sheet Rev. 04 — 2 June 2009 22 of 37

NXP Semiconductors LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

7. Limiting values

[1] The following applies to the limiting values:

a) This product includes circuitry speciﬁcally designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

b) Parameters are valid over operating temperature range unless otherwise speciﬁed. All voltages are with respect to VSS unless

otherwise noted.

[2] Core and internal rail.

[3] External rail.

[4] On ADC related pins.

[5] Including voltage on outputs in 3-state mode.

[6] Only valid when the VDD(3V3) supply voltage is present.

[7] Not to exceed 4.6 V.

[8] Per supply pin.

[9] The peak current is limited to 25 times the corresponding maximum current.

[10] Per ground pin.

[11] Dependent on package type.

[12] Performed per AEC-Q100-002.

[13] Performed per AEC-Q100-003.

[14] Performed per AEC-Q100-011.

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

[1]

Symbol Parameter Conditions Min Max Unit

VDD(1V8) supply voltage (1.8 V) [2] −0.5 +2.5 V

VDD(3V3) supply voltage (3.3 V) [3] −0.5 +4.6 V

VDDA analog 3.3 V pad supply voltage −0.5 +4.6 V

Vi(VBAT) input voltage on pin VBAT for the RTC −0.5 +4.6 V

VIA analog input voltage [4] −0.5 +5.1 V

VIinput voltage 5 V tolerant I/O

pins [5][6] −0.5 +6.0 V

other I/O pins [5] −0.5 VDD + 0.5[7] V

IDD supply current [8] - 100[9] mA

ISS ground current [10] - 100[9] mA

Tstg storage temperature [11] −65 +150 °C

Ptot(pack) total power dissipation (per package) based on package

heat transfer, not

device power

consumption

- 1.5 W

VESD electrostatic discharge voltage Human Body

Model (HBM) −4000 +4000 V[12]

Machine Model

(MM) −200 +200 V[13]

Charged Device

Model (CDM) −800 +800 V[14]

Product data sheet Rev. 04 — 2 June 2009 23 of 37

NXP Semiconductors LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

8. Static characteristics

Table 5. Static characteristics

amb

−

C to +85

C for commercial applications, unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ[1] Max Unit

VDD(1V8) supply voltage

(1.8 V) [2] 1.65 1.8 1.95 V

VDD(3V3) supply voltage

(3.3 V) [3] 2.6[4] 3.3 3.6 V

VDDA analog 3.3 V pad

supply voltage 2.6[5] 3.3 3.6 V

Vi(VBAT) input voltage on pin

VBAT 2.0[6] 3.3 3.6 V

Standard port pins, RST, RTCK

IIL LOW-level input

current VI= 0 V; no pull-up - - 3 µA

IIH HIGH-level input

current VI=V

DD(3V3); no pull-down - - 3 µA

IOZ OFF-state output

current VO=0V, V

O=V

DD(3V3); no

pull-up/down --3µA

Ilatch I/O latch-up current −(0.5VDD(3V3)) < VI < (1.5VDD(3V3));

Tj < 125 °C- - 100 mA

VIinput voltage pin conﬁgured to provide a digital

function; VDD(3V3) and VDDA ≥ 3.0 V [7][8]

[9] 0 - 5.5 V

pin conﬁgured to provide a digital

function; VDD(3V3) and VDDA < 3.0 V [7][8]

[9] 0V

DD(3V3) V

VOoutput voltage output active 0 - VDD(3V3) V

VIH HIGH-level input

voltage 2.0 - - V

VIL LOW-level input

voltage - - 0.8 V

Vhys hysteresis voltage 0.4 - - V

VOH HIGH-level output

voltage IOH =−4mA [10] VDD(3V3) − 0.4 - - V

VOL LOW-level output

voltage IOL =−4mA [10] - - 0.4 V

IOH HIGH-level output

current VOH =V

DD(3V3) −0.4 V [10] −4--mA

IOL LOW-level output

current VOL = 0.4 V [10] 4--mA

IOHS HIGH-level

short-circuit output

current

VOH =0V [11] --−45 mA

IOLS LOW-level

short-circuit output

current

VOL =V

DDA [11] - - 50 mA

Ipd pull-down current VI=5V

[12] 10 50 150 µA

Product data sheet Rev. 04 — 2 June 2009 24 of 37

NXP Semiconductors LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

Ipu pull-up current VI=0V [13] −15 −50 −85 µA

VDD(3V3) <V

I<5V

[12] 000µA

IDD(CORE) core supply current Active mode;

code

while(1){}

executed from ﬂash; all peripherals

enabled via PCONP register but not

conﬁgured to run; CCLK = 70 MHz

VDD(1V8) = 1.8 V; Tamb =25°C - 41 70 mA

Power-down mode;

VDD(1V8) = 1.8 V; Tamb =25°C - 2.5 25 µA

VDD(1V8) = 1.8 V; Tamb =85°C - 35 105 µA

Deep power-down mode;

RTC off; SRAM off; Tamb =25°C

Vi(VBAT) = 3.3 V; VDD(1V8) = 1.8 V - 0.7 - µA

IBAT battery supply

current Active mode; CCLK = 70 MHz;

PCLK = 17.5 MHz;

PCLK enabled to RTCK;

RTC clock = 32 kHz (from RTCX

pins); Tamb =25°C[14]

VDD(1V8) = 1.8 V; Vi(VBAT) = 3.0 V - 10 15 µA

Power-down mode;

RTC clock = 32 kHz

(from RTCX pins); Tamb =25°C

VDD(1V8) = 1.8 V; Vi(VBAT) = 2.5 V - 7 12 µA

VDD(1V8) = 1.8 V; Vi(VBAT) = 3.0 V - 8 12 µA

Deep power-down mode;

RTC off; SRAM off; Tamb =25°C

VDD(1V8) = 1.8 V; Vi(VBAT) = 3.0 V - 8 - µA

I2C-bus pins

VIH HIGH-level input

voltage 0.7VDD(3V3) --V

VIL LOW-level input

voltage - - 0.3VDD(3V3) V

Vhys hysteresis voltage - 0.5VDD(3V3) -V

VOL LOW-level output

voltage IOLS =3mA [10] - - 0.4 V

ILI input leakage

current VI=V

DD(3V3) -24µA

VI=5V [15] -1022µA

Oscillator pins

Vi(XTAL1) input voltage on pin

XTAL1 0 - 1.8 V

Table 5. Static characteristics

…continued

amb

−

C to +85

C for commercial applications, unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ[1] Max Unit

Product data sheet Rev. 04 — 2 June 2009 25 of 37

NXP Semiconductors LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.

[2] Core and internal rail.

[3] External rail.

[4] If VDD(3V3) < 3.0 V, the I/O pins are not 5 V tolerant, and the ADC input voltage is limited to VDDA = 3.0 V.

[5] If VDDA < 3.0 V, the I/O pins are not 5 V tolerant.

[6] The RTC typically fails when Vi(VBAT) drops below 1.6 V.

[7] Including voltage on outputs in 3-state mode.

[8] VDD(3V3) supply voltages must be present.

[9] 3-state outputs go into 3-state mode when VDD(3V3) is grounded.

[10] Accounts for 100 mV voltage drop in all supply lines.

[11] Allowed as long as the current limit does not exceed the maximum current allowed by the device.

[12] Minimum condition for VI= 4.5 V, maximum condition for VI= 5.5 V. VDDA ≥ 3.0 V and VDD(3V3) ≥ 3.0 V.

[13] Applies to P0.25:16.

[14] Battery supply current on pin VBAT.

[15] Input leakage current to VSS.

[1] Conditions: VSSA =0V, V

DDA = 3.3 V and VDD(3V3) = 3.3 V for 10-bit resolution at full speed; VDDA = 2.6 V, VDD(3V3) = 2.6 V for 8-bit

resolution at full speed.

[2] The ADC is monotonic, there are no missing codes.

[3] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 5.

[4] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after

appropriate adjustment of gain and offset errors. See Figure 5.

[5] The offset error (EO) is the absolute difference between the straight line which ﬁts the actual curve and the straight line which ﬁts the

ideal curve. See Figure 5.

[6] The gain error (EG) is the relative difference in percent between the straight line ﬁtting the actual transfer curve after removing offset

error, and the straight line which ﬁts the ideal transfer curve. See Figure 5.

[7] The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC

and the ideal transfer curve. See Figure 5.

Vo(XTAL2) output voltage on

pin XTAL2 0 - 1.8 V

Vi(RTCX1) input voltage on pin

RTCX1 0 - 1.8 V

Vo(RTCX2) output voltage on

pin RTCX2 0 - 1.8 V

Table 5. Static characteristics

…continued

amb

−

C to +85

C for commercial applications, unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ[1] Max Unit

Table 6. ADC static characteristics

DDA

= 2.5 V to 3.6 V; T

amb

−

C to +85

C unless otherwise speciﬁed. ADC frequency 4.5 MHz.

Symbol Parameter Conditions Min Typ Max Unit

VIA analog input voltage 0 - VDDA V

Cia analog input capacitance - - 1 pF

EDdifferential linearity error [1][2][3] --±1 LSB

EL(adj) integral non-linearity [1][4] --±2 LSB

EOoffset error [1][5] --±3 LSB

EGgain error [1][6] --±0.5 %

ETabsolute error [1][7] --±4 LSB

Product data sheet Rev. 04 — 2 June 2009 26 of 37

NXP Semiconductors LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

(1) Example of an actual transfer curve.

(2) The ideal transfer curve.

(3) Differential linearity error (ED).

(4) Integral non-linearity (EL(adj)).

(5) Center of a step of the actual transfer curve.

Fig 5. ADC conversion characteristics

002aac046

1023

1022

1021

1020

1019

(2)

(1)

10241018 1019 1020 1021 1022 1023

7123456

1018

(5)

(4)

(3)

1 LSB

(ideal)

code

out

VDDA − VSSA

1024

offset

error

gain

error

offset error

VIA (LSBideal)

1 LSB =

Product data sheet Rev. 04 — 2 June 2009 27 of 37

NXP Semiconductors LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

8.1 Power consumption in Deep power-down mode

Test conditions: Deep power-down mode entered; RTC off; SRAM off;

Vi(VBAT) = VDD(3V3) = VDDA = 3.3 V.

Fig 6. Core supply current IDD(CORE) measured at different temperatures and supply

voltages

Test conditions: Deep power-down mode entered; Vi(BAT) = 3.3 V; VDD(1V8) = 1.8 V;

VDD(3V3) =V

DDA = 3.3 V.

Fig 7. Battery supply current IBAT measured at different temperatures and conditions

002aae680

Temperature (°C)

−40 853510 60−15

0.75

1.25

1.5

IDD(CORE)

(µA)

0.5

1.7 V

1.65 V

VDD(1V8) =1.8 V

002aae681

Temperature (°C)

−40 853510 60−15

7.5

12.5

IBAT

(µA)

RTC off; SRAM on

RTC off; SRAM off

RTC on; SRAM on

RTC on; SRAM off

Product data sheet Rev. 04 — 2 June 2009 28 of 37

NXP Semiconductors LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

Test conditions: Deep power-down mode entered; RTC off; SRAM off; VDD(3V3) = 3.3 V;

VDD(1V8) = 1.8 V; Vi(BAT) =V

DDA = 3.3 V.

Fig 8. I/O supply current IDD(IO) measured at different temperatures

002aae682

Temperature (°C)

−40 853510 60−15

0.05

0.15

0.10

0.20

IDD(IO)

(µA)

Product data sheet Rev. 04 — 2 June 2009 29 of 37

NXP Semiconductors LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

9. Dynamic characteristics

[1] Parameters are valid over operating temperature range unless otherwise speciﬁed.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.

[3] Bus capacitance Cb in pF, from 10 pF to 400 pF.

10. Application information

10.1 XTAL1 input

The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a

clock in slave mode, it is recommended that the input be coupled through a capacitor with

Ci = 100 pF. To limit the input voltage to the speciﬁed range, choose an additional

capacitor to ground Cgwhich attenuates the input voltage by a factor Ci/(Ci+C

g). In slave

mode, a minimum of 200 mV (RMS) is needed. For more details see the

LPC2101/02/03

User manual UM10161

Table 7. Dynamic characteristics

amb

Cto70

C for commercial applications,

−

C to +85

C for industrial applications, V

DD(1V8)

, V

DD(3V3)

over

speciﬁed ranges

[1]

Symbol Parameter Conditions Min Typ[2] Max Unit

External clock

fosc oscillator frequency 10 - 25 MHz

Tcy(clk) clock cycle time 40 - 100 ns

tCHCX clock HIGH time Tcy(clk) × 0.4 - - ns

tCLCX clock LOW time Tcy(clk) × 0.4 - - ns

tCLCH clock rise time - - 5 ns

tCHCL clock fall time - - 5 ns

Port pins (except P0.2 and P0.3)

tr(o) output rise time - 10 - ns

tf(o) output fall time - 10 - ns

I2C-bus pins (P0.2 and P0.3)

tf(o) output fall time VIH to VIL 20 + 0.1 × Cb[3] --ns

Fig 9. Slave mode operation of the on-chip oscillator

LPC2xxx

XTAL1

100 pF Cg

002aae718

Product data sheet Rev. 04 — 2 June 2009 30 of 37

NXP Semiconductors LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

10.2 XTAL and RTC Printed Circuit Board (PCB) layout guidelines

The crystal should be connected on the PCB as close as possible to the oscillator input

and output pins of the chip. Take care that the load capacitors Cx1 and Cx2, and Cx3 in

case of third overtone crystal usage, have a common ground plane. The external

components must also be connected to the ground plain. Loops must be made as small

as possible, in order to keep the noise coupled in via the PCB as small as possible. Also

parasitics should stay as small as possible. Values of Cx1 and Cx2 should be chosen

smaller accordingly to the increase in parasitics of the PCB layout.

Product data sheet Rev. 04 — 2 June 2009 31 of 37

NXP Semiconductors LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

11. Package outline

Fig 10. Package outline SOT313-2 (LQFP48)

UNIT A

max. A1A2A3bpcE

(1) eH

ELL

pZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 1.6 0.20

0.05 1.45

1.35 0.25 0.27

0.17 0.18

0.12 7.1

6.9 0.5 9.15

8.85 0.95

0.55 7

0.12 0.10.21

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.75

0.45

SOT313-2 MS-026136E05 00-01-19

03-02-25

D(1) (1)(1)

7.1

6.9

9.15

8.85

0.95

0.55

vMB

vMA

36 25

detail X

(A )

0 2.5 5 mm

scale

pin 1 index

LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2

Product data sheet Rev. 04 — 2 June 2009 32 of 37

NXP Semiconductors LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

Fig 11. Package outline SOT619-7 (HVQFN48)

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT619-7 - - -

MO-220

- - -

SOT619-7

05-10-24

05-10-25

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included

HVQFN48: plastic thermal enhanced very thin quad flat package; no leads;

48 terminals; body 7 x 7 x 0.85 mm

0 2.5 5 mm

scale

DIMENSIONS (mm are the original dimensions)

UNIT

mm 0.05

0.00 0.30

0.18 7.1

6.9 7.1

6.9 3.45

3.15 0.5

0.3

A1b

A(1)

max D(1) E(1) Eh

3.45

3.15

Dhee

1L v

0.15.5

5.50.5

0.2

0.05

0.1

detail X

A1c

terminal 1

index area Dh

1/2 e

AC B

vMCw M

13 24

48 37

terminal 1

index area

Product data sheet Rev. 04 — 2 June 2009 33 of 37

NXP Semiconductors LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

Fig 12. Package outline SOT778-3 (HVQFN48)

terminal 1

index area

terminal 1

index area

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT778-3 - - -

- - -

SOT778-3

04-06-16

04-06-23

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included

DIMENSIONS (mm are the original dimensions)

HVQFN48: plastic thermal enhanced very thin quad flat package; no leads;

48 terminals; body 6 x 6 x 0.85 mm

detail X

13 24

48 37

1/2 e

AC B

vMCw My

0 2.5 5 mm

scale

UNIT

mm 0.05

0.00 0.25

0.15 6.1

5.9 6.1

5.9 3.95

3.65 0.5

0.3

A1b

A(1)

max D(1) E(1) Eh

3.95

3.65

Dhee

1L v

0.14.4

4.40.4

0.2

0.05

0.1

Product data sheet Rev. 04 — 2 June 2009 34 of 37

NXP Semiconductors LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

12. Abbreviations

Table 8. Acronym list

Acronym Description

ADC Analog-to-Digital Converter

AMBA Advanced Microcontroller Bus Architecture

APB Advanced Peripheral Bus

DCC Debug Communications Channel

DSP Digital Signal Processor

FIFO First In, First Out

FIQ Fast Interrupt reQuest

GPIO General Purpose Input/Output

IAP In-Application Programming

IRQ Interrupt Request

ISP In-System Programming

PLL Phase-Locked Loop

PWM Pulse Width Modulator

SPI Serial Peripheral Interface

SRAM Static Random Access Memory

SSI Synchronous Serial Interface

SSP Synchronous Serial Port

TTL Transistor-Transistor Logic

UART Universal Asynchronous Receiver/Transmitter

VIC Vectored Interrupt Controller

Product data sheet Rev. 04 — 2 June 2009 35 of 37

NXP Semiconductors LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

13. Revision history

Table 9. Revision history

Document ID Release date Data sheet status Change

notice Supersedes

LPC2101_02_03_4 20090602 Product data sheet LPC2101_02_03_3

Modiﬁcations: •Section 6.17.4 “Code security (Code Read Protection - CRP)”: added description of three

CRP levels (applicable to Revision A and higher).

•Section 6.17.7 “Power control”: added description of Deep power-down mode (applicable to

Revision A and higher).

•Section 10.1 “XTAL1 input” added.

•Section 10.2 “XTAL and RTC Printed Circuit Board (PCB) layout guidelines” added.

•Figure 6,Figure 7,Figure 8: added power consumption data for Deep power-down mode

(applicable to Revision A and higher).

•Table 3: added table note 7.

•Table 3: modiﬁed description of P0.14, RTCX1, RTCX2, XTAL1, XTAL2, JTAG, and DBGSEL

pins.

•Table 4: modiﬁed value for VDD(3V3).

•Table 5: added and modiﬁed values for Vhys.

•Table 5: Voltage range for pins VDD(3V3) and VDDA extended to 2.6 V.

LPC2101_02_03_3 20081007 Product data sheet - LPC2101_02_03_2

Modiﬁcations: •Updated data sheet status to Product data sheet.

•Table 1 and Table 2: added LPC2102FHN48 and LPC2103FHN48.

•Table 1, Table 2, Table 3 and related ﬁgures: removed LPC2103FA44.

•Table 3: updated pad descriptions.

•Table 3: updated description of pin 47, SCL1.

•Table 3: updated description of pins VDDA and VDD(1V8).

•Table 4: changed storage temperature range from −40 °C/125 °C to −65 °C/150 °C.

•Table 5: added or modiﬁed values for IDD(act), IDD(pd), IBATpd, IBATact.

•Table 5: removed “CCLK = 10 MHz” and associated values for IDD(act).

•Section 5: added Figure 3.

•Section 11: added Figure 11.

LPC2101_02_03_2 20071218 Preliminary data sheet - LPC2101_02_03_1

LPC2101_02_03_1 20060118 Preliminary data sheet - -

Product data sheet Rev. 04 — 2 June 2009 36 of 37

NXP Semiconductors LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

14. Legal information

14.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Deﬁnitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

14.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

14.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

14.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I2C-bus — logo is a trademark of NXP B.V.

15. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Deﬁnition

Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development.

Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation.

Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 2 June 2009

Document identifier: LPC2101_02_03_4

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

16. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2.1 Enhanced features . . . . . . . . . . . . . . . . . . . . . . 1

2.2 Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

3.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

6 Functional description . . . . . . . . . . . . . . . . . . 10

6.1 Architectural overview. . . . . . . . . . . . . . . . . . . 10

6.2 On-chip ﬂash program memory . . . . . . . . . . . 10

6.3 On-chip static RAM. . . . . . . . . . . . . . . . . . . . . 11

6.4 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 11

6.5 Interrupt controller . . . . . . . . . . . . . . . . . . . . . 12

6.5.1 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 12

6.6 Pin connect block . . . . . . . . . . . . . . . . . . . . . . 12

6.7 Fast general purpose parallel I/O . . . . . . . . . . 13

6.7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6.8 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6.8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6.9 UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6.9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6.10 I2C-bus serial I/O controllers. . . . . . . . . . . . . . 14

6.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.11 SPI serial I/O controller. . . . . . . . . . . . . . . . . . 14

6.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.12 SSP serial I/O controller . . . . . . . . . . . . . . . . . 15

6.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.13 General purpose 32-bit timers/external

event counters . . . . . . . . . . . . . . . . . . . . . . . . 15

6.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.14 General purpose 16-bit timers/external

event counters . . . . . . . . . . . . . . . . . . . . . . . . 16

6.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.15 Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 16

6.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.16 Real-time clock. . . . . . . . . . . . . . . . . . . . . . . . 17

6.16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.17 System control . . . . . . . . . . . . . . . . . . . . . . . . 17

6.17.1 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . 17

6.17.2 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.17.3 Reset and wake-up timer . . . . . . . . . . . . . . . . 18

6.17.4 Code security (Code Read Protection - CRP) 19

6.17.5 External interrupt inputs . . . . . . . . . . . . . . . . . 19

6.17.6 Memory mapping control . . . . . . . . . . . . . . . . 19

6.17.7 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.17.8 APB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.18 Emulation and debugging. . . . . . . . . . . . . . . . 20

6.18.1 EmbeddedICE . . . . . . . . . . . . . . . . . . . . . . . . 21

6.18.2 RealMonitor . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 22

8 Static characteristics . . . . . . . . . . . . . . . . . . . 23

8.1 Power consumption in Deep power-down

mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

9 Dynamic characteristics. . . . . . . . . . . . . . . . . 29

10 Application information . . . . . . . . . . . . . . . . . 29

10.1 XTAL1 input . . . . . . . . . . . . . . . . . . . . . . . . . . 29

10.2 XTAL and RTC Printed Circuit Board (PCB)

layout guidelines. . . . . . . . . . . . . . . . . . . . . . . 30

11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 31

12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 34

13 Revision history . . . . . . . . . . . . . . . . . . . . . . . 35

14 Legal information . . . . . . . . . . . . . . . . . . . . . . 36

14.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 36

14.2 Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

14.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 36

14.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 36

15 Contact information . . . . . . . . . . . . . . . . . . . . 36

16 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37