MM74HC273MTCX - Fairchild Semiconductor

September 1983

Revised May 2005

MM74HC273 Octal D-Type Flip-Flops with Clear

MM74HC273

Octal D-Type Flip-Flops with Clear

General Descript ion

The MM74HC273 edge triggered flip-flops utilize advanced

silicon-gate CMOS technology to implement D-type flip-

flops. They possess high noise immunity, low power, and

speeds comparable to low power Schottky TTL circuits.

This device contains 8 master-slave flip-flops with a com-

mon clock and common clear. Data on the D input having

the specified setup and hold times is transferred to the Q

output on the LOW-to-HIG H tra nsi tio n of t he CL OC K i np ut.

The CLEAR input when LOW, sets all outputs to a low

state.

Each out put can dr ive 10 lo w power Schottky TT L equiv a-

lent loads. The MM74HC273 is functionally as well as pin

compatible to the 74LS273. All inputs are protected from

damage due to static discharge by diodes to VCC and

ground.

Features

■Typical propagation delay: 18 ns

■Wide operating voltage ran ge

■Low input current: 1

A maximum

■Low quiescent current: 80

A (74 Series)

■Output drive: 10 LS-TTL loads

Ordering Code:

Devices also available in Tape and Reel. Specify by ap pending th e s uffix let t er “X” to the or dering code.

Connection Diagram

Top View

Order Number Package Number Package Description

MM74HC273WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

MM74HC273SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

MM74HC273MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

MM74HC273N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

www.fairchildsemi.com 2

MM74HC273

Truth Table

(Each Flip-Flop)

HIGH Level (Steady State)

LOW Level (Steady State )

Don’t Care

Transition from LOW-to-HIGH level

The level of Q be fore the indica ted ste ad y state input cond ition s were

established

Logic Diagram

Inputs Outputs

Clear Clock D Q

LXXL

HLXQ

3 www.fairchildsemi.com

MM74HC273

Absolute Maximum Ratings(Note 1)

(Note 2) Recommended Operating

Conditions

Note 1: Absolute Maximum Ratings are those values beyond which dam-

age to the device may occur.

Note 2: Unl es s ot herwise s pecified all v olt ages are ref erenced t o ground.

Note 3: Power Dis sipation tem perature d erating — plastic “N” pa ckage:



12 mW/

C from 65

C to 85

DC Electrical Characteristics (Note 4)

Note 4: For a power supply of 5V

10% the worst case output voltages (VOH, and V OL) occ ur for HC at 4.5V. Th us the 4. 5V valu es shoul d be use d when

designi ng with t his s upply. Worst c as e VIH and VIL occur at VCC

5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage cur-

rent (IIN, ICC, and IOZ) occur fo r C M OS at the h i gher voltag e and so the 6 .0 V v alues sho uld be used.

Supply Voltage (VCC)



0.5 to



7.0V

DC Input Voltage (VIN)



1.5 to VCC



1.5V

DC Output Voltage (VOUT)



0.5 to VCC



0.5V

Clamp Diode Current (IIK, IOK)

20 mA

DC Output Current, per pin (IOUT)

25 mA

DC VCC or GND Current, per pin (ICC)

50 mA

Storage Temperature Range (TSTG)



C to



150

Power Dissipation (PD)

(Note 3) 600 mW

S.O. Package only 500 mW

Lead Temperature (TL)

(Soldering 10 seconds) 260

Min Max Units

Supply Voltage (VCC)26V

DC Input or Output Voltage

(VIN, VOUT)0V

CC V

Operati ng Temperatu re Ran ge (TA)





Input Rise or Fall Times

(tr, tf) VCC

2.0V 1000 ns

VCC

4.5V 500 ns

VCC

6.0V 400 ns

Symbol Parameter Conditions VCC TA



40 to 85



55 to 125

CUnits

Typ Guaranteed Limits

VIH Minimum HIGH Level 2.0V 1.5 1.5 1.5 V

Input Voltage 4.5V 3.15 3.15 3.15 V

6.0V 4.2 4.2 4.2 V

VIL Maximum LOW Level 2.0V 0.5 0.5 0.5 V

Input Voltage 4.5V 1.35 1.35 1.35 V

6.0V 1.8 1.8 1.8 V

VOH Minimum HIGH Level VIN

VIH or VIL

Output Voltage |IOUT|

A 2.0V 2.0 1.9 1.9 1.9 V

4.5V 4.5 4.4 4.4 4.4 V

6.0V 6.0 5.9 5.9 5.9 V

VIN

VIH or VIL

|IOUT|

4.0 mA 4.5V 4.2 3.98 3.84 3.7 V

|IOUT|

5.2 mA 6.0V 5.7 5.48 5.34 5.2 V

VOL Maximum LOW Lev el VIN

VIH or VIL

Output Voltage |IOUT|

A 2.0V 0 0.1 0.1 0.1 V

4.5V 0 0.1 0.1 0.1 V

6.0V 0 0.1 0.1 0.1 V

VIN

VIH or VIL

|IOUT|

4 mA 4.5V 0.2 0.26 0.33 0.4 V

|IOUT|

5.2 mA 6.0V 0.2 0.26 0.33 0.4 V

IIN Maxim um In put VIN

VCC or GND 6.0V

0.1

1.0

Current

ICC Maximum Quiescent VIN

VCC or GND 6.0V 8 80 160

Supply Current IOUT

www.fairchildsemi.com 4

MM74HC273

AC Electrical Characteristics

VCC

5V, TA

C, CL

15 pF, tr

6 ns

AC Electrical Characteristics

50 pF, t r

6 ns (unless otherwise specified)

Note 5: CPD determines the no load dynam ic pow er cons um ption, PD

CPD VCC2f



ICC VCC, and the no load dynamic current consumption,

CPD VCC f



ICC.

Symbol Parameter Conditions Typ Guaranteed Units

Limit

fMAX Maximum Operating Frequency 50 30 MHz

tPHL, tPLH Maximum Propagation 18 27 ns

Delay, Clock to Output

tPHL Maximum Propagation 18 27 ns

Delay, Clear to Output

tREM Minimum Re mova l Time, 10 20 ns

Clear to Clock

tsMinimum Setu p T im e 10 20 ns

Data to Clock

tHMinimum Ho ld T ime



20ns

Clock to Data

tWMinimum Pulse Width 10 16 ns

Clock or Clear

Symbol Parameter Conditions VCC TA



40 to 85



55 to 125

CUnits

Typ Guaranteed Limits

fMAX Maximum Operating 2.0V 16 5 4 3 MHz

Frequency 4.5V 74 27 21 18 MHz

6.0V 78 31 24 20 MHz

tPHL, tPLH Maximum Propagation 2.0V 38 135 170 205 ns

Delay, Clock to Output 4.5V 14 27 34 41 ns

6.0V 12 23 29 35 ns

tPHL Maximum Propagation 2.0V 42 135 170 205 ns

Delay, Clear to Output 4.5V 19 27 34 41 ns

6.0V 18 23 29 35 ns

tREM Minimum Removal Time 2.0V 0 25 32 37 ns

Clear to Clock 4.5V 0 5 6 7 ns

6.0V 0 4 5 6 ns

tsMinimum Setup Time 2.0V 26 100 125 150 ns

Data to Clock 4.5V 7 20 25 30 ns

6.0V 5 17 21 25 ns

tHMinimum Hold Time 2.0V



15 0 0 0 ns

Clock to Data 4.5V



60 0 0 ns

6.0V



40 0 0 ns

tWMinimum Pulse Width 2.0V 34 80 100 120 ns

Clock or Clear 4.5V 11 16 20 24 ns

6.0V 10 14 18 20 ns

tr, tfMaximum Input Rise and 2.0V 1000 1000 1000 ns

Fall Time, Clock 4.5V 500 500 500 ns

6.0V 400 400 400 ns

tTHL, tTLH Maximum Output Rise 2.0V 28 75 95 110 ns

and Fall Time 4.5V 11 15 19 22 ns

6.0V 9 13 16 19 ns

CPD Power Dissipation (per flip-flop) 45 pF

Capacitance (Note 5)

CIN Maximum Input 7 10 10 10 pF

Capacitance

5 www.fairchildsemi.com

MM74HC273

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

Package Number M20B

www.fairchildsemi.com 6

MM74HC273

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Small Outline Package (SOP), EIAJ T YPE II, 5.3mm Wide

Package Number M20D

7 www.fairchildsemi.com

MM74HC273

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lea d Th in S hri nk Sm all Ou tlin e Pack age (TSSOP ), JED EC MO-1 53, 4.4mm Wide

Package Number MTC20

www.fairchildsemi.com 8

MM74HC273 Octal D-Type Flip-Flops with Clear

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N20A

Fairchild does no t assume any responsibility for use of any circui try described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r systems a re devices or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical compon ent in any componen t of a life support

device or system whose failure to perform can be rea-

sonabl y ex pect ed to cause the fa ilu re of the li fe su pp ort

device or system, or to affect its safety or effectiveness.