SiI1160CTU - Silicon Image, Inc.

Technology

SiI 1160

PanelLink Transmitter

Data Sheet

Document # SiI-DS-0126-B

SiI 1160 PanelLink Transmitter

Data Sheet

Silicon Image, Inc.

SiI-DS-0126-B

March 2005

Application Information

To obtain the most updated Application Notes and other useful information for your design, please visit the Silicon

Image web site at www.siliconimage.com or contact your local Silicon Image sales office.

This manual is copyrighted by Silicon Image, Inc. Do not reproduce, transform to any other format, or

send/transmit any part of this documentation without the expressed written permission of Silicon Image, Inc.

T rademark Acknowledgment

Silicon Image, the Silicon Image logo, PanelLink® and the PanelLink® Digital logo are registered trademarks of

Silicon Image, Inc. TMDSTM is a trademark of Silicon Image, Inc. I2C is a trademark of Philips Semiconductor. All

other trademarks are the property of their respective holders.

Disclaimer

This document provides technical information for the user. Silicon Image, Inc. reserves the right to modify the

information in this document as necessary. The customer should make sure that they have the most recent data

sheet version. Silicon Image, Inc. holds no responsibility for any errors that may appear in this document.

Customers should take appropriate action to ensure their use of the products does not infringe upon any patents.

Silicon Image, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to

infringe upon such rights.

All information cont ained herein is subject to change without notice.

Revision History

Revision Date Comment

A 07/07/04 Data Sheet – 1st release

B 03/01/05 Data Sheet – 2nd release – added I2C registers and pins, added

dual zone PLL information, corrected recommended REXT_SWING

value from 380Ω to 510Ω, corrected package JEDEC code, added

reset description.

SiI-DS-0126-B ii

SiI 1160 PanelLink Transmitter

Data Sheet

TABLE OF CONTENTS

General Description........................................................................................................................................ 1

Features ...................................................................................................................................................... 1

Functional Description .................................................................................................................................... 3

Electrical Specifications.................................................................................................................................. 4

Absolute Maximum Conditions ................................................................................................................... 4

Normal Operating Conditions ..................................................................................................................... 4

Digital I/O Specifications ............................................................................................................................. 4

DC Specifications........................................................................................................................................ 5

AC Specifications ........................................................................................................................................ 5

Input Timing Diagrams ................................................................................................................................6

Pin Descriptions.............................................................................................................................................. 8

Input Pins .................................................................................................................................................... 8

Control and Configuration Pins................................................................................................................... 8

Power Management Pins............................................................................................................................ 9

Differential Signal Data Pins ....................................................................................................................... 9

Local Control (I2C) Interface ....................................................................................................................... 9

Reserved Pins........................................................................................................................................... 10

Power and Ground Pins............................................................................................................................ 10

Feature Information ...................................................................................................................................... 11

I2C Interface .............................................................................................................................................. 11

I2C Register Mapping................................................................................................................................12

Dual Zone PLL .......................................................................................................................................... 13

Manual Zone Control............................................................................................................................. 13

Automatic Zone Control......................................................................................................................... 14

Reset Description...................................................................................................................................... 14

TFT Panel Data Mapping.......................................................................................................................... 15

Design Recommendations ........................................................................................................................... 20

Differences Between SiI 160 and SiI 1160 ............................................................................................... 20

EXT_SWING Selection ............................................................................................................................. 20

PCB Ground Planes.................................................................................................................................. 20

Voltage Ripple Regulation......................................................................................................................... 20

Spread Spectrum Support......................................................................................................................... 21

Reset Circuit for I2C Application................................................................................................................ 22

Power Control ........................................................................................................................................... 22

Decoupling Capacitors.............................................................................................................................. 23

Series Damping Resistors on Outputs...................................................................................................... 24

Source Termination Resistors on Differential Outputs.............................................................................. 24

Differential Trace Routing ......................................................................................................................... 25

Package Dimensions.................................................................................................................................... 28

Package .................................................................................................................................................... 28

Ordering Information ................................................................................................................................. 28

iii SiI-DS-0126-B

SiI 1160 PanelLink Transmitter

Data Sheet

LIST OF TABLES

Table 1. General I2C Register Bits................................................................................................................ 13

Table 2. Dual Zone PLL I2C Control Register Bits........................................................................................ 14

Table 3. One Pixel/Clock Input/Output TFT Mode........................................................................................ 15

Table 4. Two Pixels/Clock Input/Output TFT Mode ...................................................................................... 16

Table 5. 24-bit One Pixel/Clock Input with 24-bit Two Pixels/Clock Output TFT Mode................................ 17

Table 6. 18-bit One Pixel/Clock Input with 18-bit Two Pixels/Clock Output TFT Mode................................ 18

Table 7. Two Pixels/Clock Input with One Pixel/Clock Output TFT Mode .................................................... 19

Table 8. New Pin Functions for SiI 1160 Tx.................................................................................................. 20

Table 9. Power Consumption Characteristics .............................................................................................. 22

Table 10. Recommended Components for Bypass and Decoupling Circuits............................................... 23

Table 11. Routing Guidelines for DVI Traces................................................................................................ 27

LIST OF FIGURES

Figure 1. System Block Diagram – Typical Application .................................................................................. 1

Figure 2. Pin Diagram for SiI 1160 ................................................................................................................. 2

Figure 3. Functional Block Diagram ............................................................................................................... 3

Figure 4. Clock Cycle High/Low Times........................................................................................................... 6

Figure 5. Input Data Setup/Hold Time to IDCK .............................................................................................. 6

Figure 6. VSYNC, HSYNC and CTL[3:1] Delay Time from DE ...................................................................... 6

Figure 7. DE High and Low Times.................................................................................................................. 6

Figure 8. Reset Timing at Power-Up or Prior to First I2C Access................................................................... 7

Figure 9. I2C Byte Read................................................................................................................................11

Figure 10. I2C Byte Write .............................................................................................................................. 11

Figure 11. Voltage Regulation using LM317EMP......................................................................................... 20

Figure 12. Planned Spread Spectrum Support Circuit ................................................................................. 21

Figure 13. Typical Reset Circuit.................................................................................................................... 22

Figure 14. Decoupling and Bypass Capacitor Placement............................................................................ 23

Figure 15. Decoupling and Bypass Schematic............................................................................................. 23

Figure 16. Series Input Damping Resistors for Driving Source ................................................................... 24

Figure 17. Differential Output Source Terminations .................................................................................... 24

Figure 18. Source Termination Layout Illustration........................................................................................ 25

Figure 19. Example of Incorrect Differential Signal Routing ........................................................................ 26

Figure 20. Example of Correct Differential Signal Routing........................................................................... 26

Figure 21. Differential Trace Routing to DVI Connector (Top Side View) .................................................... 26

Figure 22. 100-pin TQFP Package Dimensions (JEDEC code MS-026-AED) ............................................ 28

SiI-DS-0126-B iv

SiI 1160 PanelLink Transmitter

Data Sheet

General Description

The SiI 1160 transmitter uses PanelLink Digital

technology to support displays up to UXGA resolution.

It supports up to true-color panels (24 bits per pixel,

16.7M colors) in 1 or 2 pixels-per-clock mode.

All PanelLink products are designed on scaleable

CMOS architecture to support future performance

requirements while maintaining the same logical

interface. The SiI 1160 transmitter follows this strategy

by offering a pin-compatible upgrade to the SiI 160

transmitter that also brings longer cable support.

PanelLink Digital technology simplifies the PC &

display interface by resolving many of the system

level issues associated with high-speed digital design,

providing the system designer with a digital solution

that is quicker to market and lower in cost.

Features

• Scaleable Bandwidth: 25-165 MHz (VGA to

UXGA)

• Backwards compatible replacement for the SiI 160

transmitter

• High Skew Inter pair Tolerance: 1 full input clock

cycle (6ns at 165 MHz)

• Flexible interface: single or dual pixel input at up

to 48 bits

• Cable Distance Support: over 20m DVI cable

• Fully DVI 1.0 compliant

• Advanced on-chip input clock jitter filter to ensure

clean output to receiver

• Available in Universal package for both standard

and Pb-Free (environmentally-friendly)

applications.

SiI 1160

TMDS Tx

even pixel data

odd pixel data

control

clock

TMDS over

DVI cable or

flat cable

Video

Processor

SiI 1161

TMDS Rx

Panel

Controller

even pixel data

odd pixel data

control

clock

Figure 1. System Block Diagram – Typical Application

1 SiI-DS-0126-B

SiI 1160 PanelLink Transmitter

Data Sheet

Figure 2. Pin Diagram for SiI 1160

DIE13

SiI 1160

100-Pin TQ FP

(Top View )

DIE12

DIE11

DIE10

DIE9

DIE8

GND

VCC

DIE7

DIE6

DIE5

DIE4

DIE3

DIE2

DIE1

DIE0

IVCC

PVCC1

PGND1

SCL

MSEN

RSVD

SDA

EDGE

PIXS

RSVD

VCC

GND

EXT_SWING

AGND

TXC-

TXC+

AVCC

AGND

RSVD

TX0-

TX0+

AGND

TX1-

TX1+

AVCC

TX2-

TX2+

AGND

DIO23

DIO22

DIO21

DIO1 74

DIO2 73

DIO3 72

DIO4 71

DIO5 70

DIO6 69

DIO7 68

GND 67

IVCC 66

DIO8 65

DIO9 64

DIO10 63

DIO11 62

DIO12 61

DIO13 60

DIO14 59

DIO15 58

GND 57

VCC 56

DIO16 55

DIO17 54

DIO18 53

DIO19 52

DIO20 51

DIO0

DIE14 100

DIE15 99

IVC C 98

DIE16 97

DIE17 96

DIE18 95

DIE19 94

DIE20 93

DIE21 92

DIE22 91

DIE23 90

GND 89

VCC 88

ISEL/RST 87

PGND2 86

PVCC2 85

CTL1 84

CTL2 83

CTL3 82

IVC C 81

IDCK 80

GND 79

DE 78

VSYNC 77

HSYNC 76

DIFFERENTIAL SIGNALS

ODD 8-bits RED

EVEN 8-bits RED

ODD 8-bits GREEN

EVEN 8-bits GREEN

ODD 8-bits BLUE

EVEN 8-bits BLUE CONFIGURATION PINS

PLL

CONTROLS

INPUT

CLOCK

GPI

CONTROL

SiI-DS-0126-B 2

SiI 1160 PanelLink Transmitter

Data Sheet

3 SiI-DS-0126-B

Functional Description

The SiI 1160 Tx is a DVI 1.0 compliant PanelLink transmitter in a compact package. It provides 48 bits for data

input to allow for panel support up to UXGA. Figure 3 shows the functional blocks of the chip.

Data

Capture

Logic

HSYNC

VSYNC

CTL3

CTL2

CTL1

IDCK

EXT_SWING

Tx0

DATA

DIE[23:0]

DIO[23:0] Encoder

HSYNC

VSYNC

Encoder

CTL1

DATA

CTL2

CTL3

Jitter

Filter

Main

PLL

Swing

Control

Tx1

Tx2

TxC

Tx0+

Tx0-

Tx1+

Tx1-

Tx2+

Tx2-

TxC+

TxC-

SDA

SCL

EDGE

PIXS

I2C Registers

-----------

Configuration

Logic

-----------

Message

Encoder Logic

CTL0

config

info

Figure 3. Functional Block Diagram

SiI 1160 PanelLink Transmitter

Data Sheet

SiI-DS-0126-B 4

Electrical Specifications

Absolute Maximum Conditions

Symbol Parameter Min Typ Max Units

VCC

1Supply Voltage 3.3V -0.3 4.0 V

VIInput Voltage -0.3 VCC+ 0.3 V

2Input Voltage -0.3 VCC+ 0.3 V

TjJunction Temperature (with power applied) 125 °C

TSTG Storage Temperature -65 150 °C

Note

1. Permanent device damage may occur if absolute maximum conditions are exceeded.

2. Functional operation should be restricted to the conditions described under normal operating conditions.

Normal Operating Conditions

Symbol Parameter Min Typ Max Units

VCC Supply Voltage 3.0 3.3 3.6 V

VCCN Supply Voltage Noise 100 mVP-P

TAAmbient Temperature (with power applied) 0 25 70 °C

θJA Thermal Resistance (junction to ambient)1 53

°C/W

Note

1. Airflow at 0m/s.

Digital I/O Specifications

Under normal operating conditions unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Units

VIH High-level Input Voltage 2 V

VIL Low-level Input Voltage 0.8 V

VOH High-level Input Voltage 2.4 V

VOL Low-level Input Voltage 0.4 V

VCINL Input Clamp Voltage1ICL = -18mA GND -0.8 V

VCIPL Input Clamp Voltage1ICL = 18mA IVCC + 0.8 V

VCONL Input Clamp Voltage1ICL = -18mA GND -0.8 V

VCOPL Input Clamp Voltage1ICL = 18mA OVCC + 0.8 V

IOL Input Leakage Current High Impedance -10 10 µA

Note

1. Guaranteed by design. Voltage undershoot or overshoot cannot exceed absolute maximum conditions for a pulse of

greater than 3 ns or one third of the clock cycle.

SiI 1160 PanelLink Transmitter

Data Sheet

5 SiI-DS-0126-B

DC Specifications

Under normal operating conditions, with REXT_SWING = 510Ω and using source termination, unless otherwise

specified.

Symbol Parameter Conditions Min Typ Max Units

VOD Differential Voltage

Single ended peak to peak

amplitude

RLOAD = 50Ω

510

550

590

VDOH Differential High-level Output

Voltage1 AVCC V

IDOS Differential Output Short

Circuit Current1VOUT = 0 V 5 µA

IPD Power-down Current2

5 mA

ICCT Transmitter Supply Current IDCK= 165 MHz, two pixel per

clock mode

IVCC = VCC, Worst Case Pattern3

140

200

Notes

1. Guaranteed by design.

2. Assumes all inputs to the transmitter are not toggling.

3. The Worst Case Pattern consists of a black and white checkerboard pattern, each checker one pixel wide.

AC Specifications

Under normal operating conditions with source termination and the recommended REXT_SWING value unless

otherwise specified.

Symbol Parameter Conditions Min Max Units

TCIP IDCK Period, 1 Pixel/Clock 6 40 ns

FCIP IDCK Frequency, 1 Pixel/Clock 25 165 MHz

TCIP IDCK Period, 2 Pixels/Clock 12 80 ns

FCIP IDCK Frequency, 2 Pixels/Clock 12 81 MHz

TCIH IDCK High Time at 165MHz 2 ns

TCIL IDCK Low Time at 165MHz 2 ns

TSIDF Data, DE, VSYNC, HSYNC, and CTL[3:1]

Setup Time to IDCK falling edge

EDGE = 0 1.5 ns

THIDF Data, DE, VSYNC, HSYNC, and CTL[3:1]

Hold Time from IDCK falling edge

EDGE = 0 1.5 ns

TSIDR Data, DE, VSYNC, HSYNC, and CTL[3:1]

Setup Time to IDCK rising edge

EDGE = 1 1.5 ns

THIDR Data, DE, VSYNC, HSYNC, and CTL[3:1]

Hold Time from IDCK rising edge

EDGE = 1 1.5 ns

TDDF VSYNC, HSYNC, and CTL[3:1] Delay from DE falling

edge1 T

CIP ns

TDDR VSYNC, HSYNC, and CTL[3:1] Delay to DE rising edge1 T

CIP ns

THDE DE high time1 8191TCIP ns

TLDE DE low time1 128TCIP ns

TI2CDVD SDA Data Valid Delay from SCL high to low transition CL = 400pf 1000 ns

TRESET ISEL/RST Signal High Time required for valid I2C reset 50 µs

Notes

1. Guaranteed by design.

2. All TMDS signaling is guaranteed to meet the DVI 1.0 specifications.

3. All Standard mode I2C (100kHz and 400kHz) timing requirements are guaranteed by design.

SiI 1160 PanelLink Transmitter

Data Sheet

SiI-DS-0126-B 6

Input Timing Diagrams

CIH

CIL

CIP

80% VCC

20% VCC

80% VCC 80% VCC

Figure 4. Clock Cycle High/Low Times

D[23:0], DE,

HSYNC,VSYNC

IDCK

SIDF

HIDF

SIDR

HIDR

50 %

50 % 50 %

50 %

Figure 5. Input Data Setup/Hold Time to IDCK

TDDR

TDDF

VSYNC, HSYNC,

CTL[3:1]

20% VCC

20% VCC 20% VCC

20% VCC

VSYNC, HSYNC,

CTL[3:1]

Figure 6. VSYNC, HSYNC and CTL[3:1] Delay Time from DE

LDE

HDE

20% VCC

80% VCC

20% VCC

80% VCC

Figure 7. DE High and Low Times

SiI 1160 PanelLink Transmitter

Data Sheet

7 SiI-DS-0126-B

max

RESET

min

ISEL/RST TRESET

Figure 8. Reset Timing at Power-Up or Prior to First I2C Access

SiI 1160 PanelLink Transmitter

Data Sheet

SiI-DS-0126-B 8

Pin Descriptions

Input Pins

Pin Name Pin # Type Description

DIE23-

DIE0

See

SiI 1160

Diagram

In Input Even Data[23:0] corresponds to 24-bit pixel data for 1-pixel/clock input mode and to

the first 24-bit pixel data for 2-pixels/clock mode.

Input data is synchronized with Input data clock (IDCK).

Data can be latched on the rising of the falling edge of IDCK depending on whether

EDGE is high or low, respectively.

Refer to TFT Panel Data Mapping in this document and DSTN Panel Data Mapping

application note (SiI-AN-0007-A), which tabulates the relationship between the input data

to the transmitter and output data from the Receiver

DIO23-

DIO0

See

SiI 1160

Diagram

In Input Odd Data[23:0] corresponds to the second 24-bit pixel data for 2-pixels/clock mode.

Tie all pins to low when not in use.

Input data is synchronized with Input data clock (IDCK).

Data can be latched on the rising of the falling edge of IDCK depending on whether

EDGE is high or low, respectively.

Dual Link is not supported.

IDCK 80 In Input Data Clock. Input data and control signals can be valid either on the falling or the

rising edge of IDCK as selected by the EDGE pin.

DE 78 In Input Data Enable. This signal qualifies the active data area. DE is always required by the

transmitter and must be high during active display time and low during blanking time.

HSYNC

VSYNC

Horizontal Sync input control signal.

Vertical Sync input control signal.

Control and Configuration Pins

Pin Name Pin # Type Description

EDGE 24 In Data/Control Latching Edge. A LOW level indicates that all input signals(DIE/DIO[23:0],

HSYNC, VSYNC, DE and CTL[3:1] are latched on the falling edge of IDCK, while a HIGH

level(3.3V) indicates that all input signals are latched on the rising edge of IDCK. When

the I2C interface is enabled (ISEL/RST=LOW), this pin is ignored and the EDGE register

bit is used instead.

PIXS 25 In Pixel Select. A LOW level indicates one pixel (up to 24-bits) per clock mode using

DIE[23:0]. A HIGH level (3.3V) indicates two pixels (up to 48-bits) per clock mode using

DIE[23:0] for the first pixel and DIO[23:0] for the second pixel.

CTL1 84 In General Input control signal 1.

SS_CLK_IN Spread Spectrum Clock Input (future). A planned future variation of this device will allow

a spread spectrum version of SS_CLK_OUT to be driven into this pin, at which time pin

29 will become CTL1.

CTL2 83 In General Input control signal 2.

SS_CLK_OUT Out Spread Spectrum Clock Output (future). A planned future variation of this device will

allow a clock to be driven out of this pin for conditioning by a spread spectrum device, at

which time pin 28 will become CTL2.

CTL3 82 In General Input control signal 3.

RSVD 27 In

Reserved. Must be tied HIGH for normal operation.

SS_EN# Spread Spectrum Enable. A planned future variation of this device will use this pin to

enable pins 83 and 84 to handle spread spectrum clock.

Low = Spread Spectrum feature enabled on pins 83 and 84

High = Pins 83 and 84 are CTL2 and CTL1 outputs (default)

SiI 1160 PanelLink Transmitter

Data Sheet

9 SiI-DS-0126-B

Power Management Pins

Pin Name Pin # Type Description

PD 26 In Power Down (active LOW). A HIGH level indicates normal operation. A LOW level

indicates power down mode. During power down mode, all data (DIE/DIO[23:0]), data

enable (DE), clock (IDCK) and control signals (HSYNC, VSYNC, CTL[3:1]), input buffers

are disabled, all output buffers are tri-stated and all internal circuitry is powered down.

When the I2C interface is enabled (ISEL/RST=LOW), this pin is ignored and the PD

Differential Signal Data Pins

Pin Name Pin # Type Description

TX0+

TX0-

TX1+

TX1-

TX2+

TX2-

Analog

TMDS Low Voltage Differential Signal input data pairs.

These pins are tri-stated when PD is asserted.

TXC+

TXC-

Analog

TMDS Low Voltage Differential Signal input clock pair.

These pins are tri-stated when PD is asserted.

EXT_SWING 32 Analog Voltage Swing Adjust. A resistor should tie this pin to AVCC. This resistor determines

the amplitude of the voltage swing. A smaller resistor value sets a larger voltage swing

and vice versa. For remote display applications with source termination, a 510Ω resistor

is recommended (see page 24). Without the source termination, use a 560Ω resistor.

Local Control (I2C) Interface

The transmitter can operate with or without an I2C interface connection. Refer to the Feature Information section

for details on using the I2C registers.

Pin Name Pin # Type Description

ISEL/RST 87 In I2C Interface Select. If LOW, then the I2C interface is active. If HIGH, the interface is

inactive and chip configuration is taken from strap and default settings. This pin also acts

as an asynchronous reset to the I2C interface controller. Switching this input from HIGH to

LOW after a minimum TRESET high time resets the I2C logic.

MSEN 21 Out Monitor Sense. The behavior of this output depends on whether the I2C interface is

enabled or disabled.

No I2C (ISEL = HIGH)

MSEN=HIGH: a powered on receiver is detected at the TMDS outputs.

MSEN=LOW: a powered on receiver is not detected.

This Receiver Sense function can only be used in DC-coupled systems.

I2C enabled (ISEL = LOW)

The output is programmable through the I2C interface and can indicate the Hot

Plug or Receiver Sense signal state, or can instead generate a status change interrupt for

those signals.

This pin is an open collector output. An external pull-up resistor (5KΩ recommended) is

required on this pin if the MSEN signal will be used. Otherwise the signal should be tied

low.

SCL 20 In I2C Clock. When the I2C interface is enabled (ISEL=LOW), this pin acts as the I2C clock

input. This pin is an open collector output. It must be pulled high to VCC through a

resistor; a value of 2.2KΩ is recommended for I2C applications, 2-5KΩ otherwise. This pin

is not 5V-tolerant.

SDA 23 In/Out I2C Data. When the I2C interface is enabled (ISEL=LOW), this pin acts as the I2C data

input and output. This pin is an open collector output. It must be pulled high to VCC

through a resistor; a value of 2.2KΩ is recommended for I2C applications, 2-5KΩ

otherwise. This pin is not 5V-tolerant.

SiI 1160 PanelLink Transmitter

Data Sheet

SiI-DS-0126-B 10

Reserved Pins

It is preferable to tie indicated pins HIGH through a 2-5KΩ resistor; direct connection to VCC is not

recommended.

Pin Name Pin # Type Description

RSVD 22 In

Reserved. Must be tied HIGH for normal operation.

RSVD 28 In

Reserved. Must be tied HIGH for normal operation.

RSVD 29 In

Reserved. Must be tied HIGH for normal operation.

RSVD 38 -- Reserved. Should be left unconnected (but can be tied to AVCC for existing

SiI 160 designs).

Power and Ground Pins

Pin Name Pin # Type Description

VCC 8,30,56,88 Power Digital Core VCC, must be set to 3.3V.

GND 7,31,57,67,79,89 Ground Digital Core GND.

IVCC 17,66,81,98 Power Input VCC, must be set to 3.3V.

AVCC 36,44 Power Analog VCC must be set to 3.3V.

AGND 33,37,41,47 Ground Analog GND.

PVCC1 18 Power Primary PLL Analog VCC must be set to 3.3V.

PVCC2 85 Power Filter PLL Analog VCC must be set to 3.3V.

PGND1 19 Ground PLL Analog GND. PGND1 should not be directly

connected to PGND2 before being connected to the

GROUND plane. They should be connected individually

to the GROUND plane.

PGND2 86 Ground PLL Analog GND. PGND2 should not be directly

connected to PGND1 before being connected to the

GROUND plane. They should be connected individually

to the GROUND plane.

SiI 1160 PanelLink Transmitter

Data Sheet

11 SiI-DS-0126-B

Feature Information

I2C Interface

The SiI 1160 Tx provides an I2C slave interface for more precise control of the chip features. Use of this interface

is optional and is selected by the ISEL/RST pin. If not used, the chip register settings return to a default state; the

EDGE and PD features then come under the control of the respective strap pins instead.

The I2C slave state machine operates from an internal clock derived from the incoming SCL signal. No video

clock and input is required to read and write to the I2C registers from address 0x00 to 0x0F. These accesses can

also take place using only the SCL clock in power down mode.

The transmitter responds to the seven-bit binary I2C address of 0x70. A read or write transaction is determined by

bit 0 of the I2C address. Setting this bit to 0 will enable a write transaction and setting this bit to 1 will enable a

read transaction.

The I2C read operation is shown in Figure 9, and the write operation in Figure 10. Page mode is not supported.

Slave Address Register Address Slave Address

Data

Stop

Start

Bus Activity :

Master

SDA

Figure 9. I2C Byte Read

Slave Address Register Address Data

Stop

Start

Bus Activity :

Master

SDA

Figure 10. I2C Byte Write

SiI 1160 PanelLink Transmitter

Data Sheet

SiI-DS-0126-B 12

I2C Register Mapping

Addr. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default

Value Notes

0x0 VND_IDL 0x01

0x1 VND_IDH 0x00

0x2 DEV_IDL 0x06

0x3 DEV_IDH 0x00

0x4 DEV_REV 0x00

0x5 RSVD 4

0x6 FRQ_LOW 0x19

0x7 FRQ_HIGH 0x64

0x8 RSVD

write to 00

VEN HEN RSVD

write to 01

EDGE PD 00110100 3, 5,

0x9 RSVD

RSEN RSVD

read only

0xA RSVD

write to 1000000

CTL0 10000001 5, 6

0xB-

0xD RSVD 4

0xE RSVD

write to 00

EZONE ZONEF ZONEO RSVD

write to 001

00000001

0xF RSVD 4

Notes:

1. Hexadecimal values use a prefix of ‘0x’. All values use bit 7 as most significant, bit 0 as least significant.

2. Read-only or read/write capabilities are noted on the next page.

3. On any reset assertion event, registers that have default values lose their previously programmed value and are set back

to the default values listed.

4. Registers listed as RSVD and shaded gray are reserved for factory use and should not be accessed.

5. Write RSVD bits to the values indicated when writing other bits in the register.

6. Write PD to 1 for normal operation; write CTL0 to 0 for HDMI applications.

SiI 1160 PanelLink Transmitter

Data Sheet

13 SiI-DS-0126-B

Table 1. General I2C Register Bits

VND_IDL RO Vendor ID Low byte (0x01)

VND_IDH RO Vendor ID High byte (0x00)

DEV_IDL RO Device ID Low byte (0x06)

DEV_IDH RO Device ID High byte (0x00)

DEV_REV RO Device Revision (0x00)

FRQ_LOW RO IDCK. Low frequency limit is 25MHz. (0x19)

FRQ_HIGH RO IDCK High frequency limit is 165MHz. Value is offset over 65MHz. (0x64)

HEN RW Horizontal Sync Enable

0 – HSYNC input is transmitted as fixed LOW

1 – HSYNC input is transmitted as input. → Default

VEN RW Vertical Sync Enable

0 – VSYNC input is transmitted as fixed LOW

1 – VSYNC input is transmitted as input. → Default

EDGE RW Edge Select (same function as EDGE pin)

0 – Input data low order bits latched first → Default

1 – Input data high order bits latched first

PD RW Power Down mode (same function as PD# pin)

0 – Power Down. → Default after RESET

1 – Normal operation

RSEN RO Receiver Sense. This bit is HIGH if a powered on receiver is connected to the transmitter

outputs, LOW otherwise. This function is only available for use in DC-coupled systems.

CTL0 RW Control 0. CTL0, CTL1, CTL2, CTL3 are sent over TMDS interface when DE is LOW.

CTL1-3 are driven in from external pins, but CTL0 is not available externally and therefore

must be set through this register. Set to 0 for HDMI applications.

0 – Transmit CTL0 as LOW

1 – Transmit CTL0 as HIGH

Note that when not in I2C mode, CTL0 is always transmitted as HIGH.

Notes:

1. RO = Read Only Registers

2. RW = Read/Write Registers

3. ‘Default’ indicates value set after a reset event. Not all bits default to a defined state after reset.

Dual Zone PLL

The SiI 1160 Tx offers a dual-zone PLL that changes its operational parameters depending on the frequency zone

selected. In the low zone, operation is ideal in the low frequency range, from 20MHz to around 120MHz. High

zone operation is optimized in the high frequency range, above 100MHz. In the overlapping range, either low

zone or high zone operation can be used.

Operating zone optimization contributes to robust operation over long cables. For example, optimized PLL

characteristics account for the ability of the transmitter to send video at UXGA over 20m cables.

PLL zone selection is controlled either manually or automatically. Manual zone control is the preferred mode of

operation.

Manual Zone Control

Whenever the application allows it, PLL zone selection should be made manually. The I2C register bits ZONEF

and EZONE allow the host graphics controller to set the optimal zone for the current video resolution being

transmitted. For frequencies over 100MHz, the controller should select high zone PLL operation. Table 2

describes the relevant register bits.

SiI 1160 PanelLink Transmitter

Data Sheet

SiI-DS-0126-B 14

Automatic Zone Control

For applications that are not able to program the I2C registers, the chip incorporates an automatic zone control

circuit. This circuit determines whether the input pixel clock is operating in the low frequency range or the high

frequency range, and sets the PLL zone selection accordingly. The chip defaults to the automatic mode of zone

selection after reset.

The zone determination depends primarily on input frequency, but is also affected by operating voltage and chip

temperature. Therefore, it is possible for an automatic zone switch to occur while video input is stable, causing

momentary (~1µs) unevenness in the video output clock and data streams. This could occur, for example, while

the chip is still warming up to its normal operating temperature. However, the automatic selection circuit provides

wide hysteresis to ensure that there will not be any oscillation around the zone switch point.

Table 2. Dual Zone PLL I2C Control Register Bits

ZONEF RW Zone Force. Enable external selection of main PLL operating zone. When ZONEF=1, the

main PLL zone is selected by EZONE.

0 – Automatic zone selection – EZONE bit disabled (default)

1 – Manual zone selection – EZONE bit enabled

EZONE RW External Zone Select. Selects operating zone of main PLL, but only when ZONEF=1

(disabled by default).

0 – Low zone (recommended for 20-120MHz)

1 – High zone (recommended for > 100MHz)

ZONEO RO Zone Output – indicates current operating zone.

When ZONEF=0 (automatic), ZONEO indicates that PLL is operating in zone optimized for:

0 = Lower frequencies

1 = Higher frequencies.

When ZONEF=1 (manual), ZONEO information is not used.

Reset Description

The input pin ISEL/RST serves as an asynchronous reset for the I2C slave controller in I2C mode. The

programming registers, which are accessible over the I2C bus, lose their previously programmed values as soon

as ISEL/RST is switched from HIGH to LOW. I2C registers whose default values are not correct for normal

operation must then be manually set to their appropriate value.

ISEL/RST serves only to set the registers to their default values, and to restore the interface to a known initial

state. Without an initial reset, the I2C interface may not respond properly. The minimum ISEL/RST high time for

proper reset, after nominal VCC values have been reached, is TRESET.

state of this bit is set during the reset period according to the following rule: After a reset, the chip is turned off; the

power down control bit, PD, is forced to 0. When the chip comes out of reset (ISEL/RST goes LOW), the TMDS

outputs will be disabled and the transmitter will be turned off. To turn the transmitter back on, the PD bit must be

set to 1 over the I2C bus.

SiI 1160 PanelLink Transmitter

Data Sheet

15 SiI-DS-0126-B

TFT Panel Data Mapping

The following TFT data mapping tables are strictly listed for single link TFT applications only. For DSTN mapping

please refer to Application Note SiI-AN-0007-A. SiI 1151 and SiI 1161 have the same pinout.

Table 3. One Pixel/Clock Input/Output TFT Mode

TFT VGA Output Tx Input Data Rx Output Data TFT Panel Input

24-bpp 18-bpp 1160 164 1161 141B 24-bpp 18-bpp

B0 DIE0 D0 QE0 Q0 B0

B1 DIE1 D1 QE1 Q1 B1

B2 B0 DIE2 D2 QE2 Q2 B2 B0

B3 B1 DIE3 D3 QE3 Q3 B3 B1

B4 B2 DIE4 D4 QE4 Q4 B4 B2

B5 B3 DIE5 D5 QE5 Q5 B5 B3

B6 B4 DIE6 D6 QE6 Q6 B6 B4

B7 B5 DIE7 D7 QE7 Q7 B7 B5

G0 DIE8 D8 QE8 Q8 G0

G1 DIE9 D9 QE9 Q9 G1

G2 G0 DIE10 D10 QE10 Q10 G2 G0

G3 G1 DIE11 D11 QE11 Q11 G3 G1

G4 G2 DIE12 D12 QE12 Q12 G4 G2

G5 G3 DIE13 D13 QE13 Q13 G5 G3

G6 G4 DIE14 D14 QE14 Q14 G6 G4

G7 G5 DIE15 D15 QE15 Q15 G7 G5

R0 DIE16 D16 QE16 Q16 R0

R1 DIE17 D17 QE17 Q17 R1

R2 R0 DIE18 D18 QE18 Q18 R2 R0

R3 R1 DIE19 D19 QE19 Q19 R3 R1

R4 R2 DIE20 D20 QE20 Q20 R4 R2

R5 R3 DIE21 D21 QE21 Q21 R5 R3

R6 R4 DIE22 D22 QE22 Q22 R6 R4

R7 R5 DIE23 D23 QE23 Q23 R7 R5

Shift

CLK

Shift

CLK

IDCK IDCK ODCK ODCK Shift CLK Shift CLK

VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC

HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC

DE DE DE DE DE DE DE DE

For 18-bit mode, the Flat Panel Graphics Controller interfaces to the transmitter exactly the same as in the 24-bit

mode; however, 6 bits per channel (color) are used instead of 8. It is recommended that unused data bits be tied

low. As can be seen from the above table, the data mapping for less than 24-bit per pixel interfaces are MSB

justified. The data is sent during active display time while the control signals are sent during blank time. Note that

the three data channels (CH0, CH1, CH2) are mapped to Blue, Green and Red data respectively.

SiI 1160 PanelLink Transmitter

Data Sheet

SiI-DS-0126-B 16

Table 4. Two Pixels/Clock Input/Output TFT Mode

TFT VGA Output Tx Input Data Rx Output Data TFT Panel Input

24-bpp 18-bpp 1160 1161 24-bpp 18-bpp

B0 - 0 DIE0 QE0 B0 - 0

B1 - 0 DIE1 QE1 B1 - 0

B2 - 0 B0 - 0 DIE2 QE2 B2 - 0 B0 - 0

B3 - 0 B1 - 0 DIE3 QE3 B3 - 0 B1 - 0

B4 - 0 B2 - 0 DIE4 QE4 B4 - 0 B2 - 0

B5 - 0 B3 - 0 DIE5 QE5 B5 - 0 B3 - 0

B6 - 0 B4 - 0 DIE6 QE6 B6 - 0 B4 - 0

B7 - 0 B5 - 0 DIE7 QE7 B7 - 0 B5 - 0

G0 - 0 DIE8 QE8 G0 - 0

G1 - 0 DIE9 QE9 G1 - 0

G2 - 0 G0 - 0 DIE10 QE10 G2 - 0 G0 - 0

G3 - 0 G1 - 0 DIE11 QE11 G3 - 0 G1 - 0

G4 - 0 G2 - 0 DIE12 QE12 G4 - 0 G2 - 0

G5 - 0 G3 - 0 DIE13 QE13 G5 - 0 G3 - 0

G6 - 0 G4 - 0 DIE14 QE14 G6 - 0 G4 - 0

G7 - 0 G5 - 0 DIE15 QE15 G7 - 0 G5 - 0

R0 - 0 DIE16 QE16 R0 - 0

R1 - 0 DIE17 QE17 R1 - 0

R2 - 0 R0 - 0 DIE18 QE18 R2 - 0 R0 - 0

R3 - 0 R1 - 0 DIE19 QE19 R3 - 0 R1 - 0

R4 - 0 R2 - 0 DIE20 QE20 R4 - 0 R2 - 0

R5 - 0 R3 - 0 DIE21 QE21 R5 - 0 R3 - 0

R6 - 0 R4 - 0 DIE22 QE22 R6 - 0 R4 - 0

R7 - 0 R5 - 0 DIE23 QE23 R7 - 0 R5 - 0

B0 - 1 DIO0 QO0 B0 - 1

B1 - 1 DIO1 QO1 B1 - 1

B2 - 1 B0 - 1 DIO2 QO2 B2 - 1 B0 - 1

B3 - 1 B1 - 1 DIO3 QO3 B3 - 1 B1 - 1

B4 - 1 B2 - 1 DIO4 QO4 B4 - 1 B2 - 1

B5 - 1 B3 - 1 DIO5 QO5 B5 - 1 B3 - 1

B6 - 1 B4 - 1 DIO6 QO6 B6 - 1 B4 - 1

B7 - 1 B5 - 1 DIO7 QO7 B7 - 1 B5 - 1

G0 - 1 DIO8 QO8 G0 - 1

G1 - 1 DIO9 QO9 G1 - 1

G2 - 1 G0 - 1 DIO10 QO10 G2 - 1 G0 - 1

G3 - 1 G1 - 1 DIO11 QO11 G3 - 1 G1 - 1

G4 - 1 G2 - 1 DIO12 QO12 G4 - 1 G2 - 1

G5 - 1 G3 - 1 DIO13 QO13 G5 - 1 G3 - 1

G6 - 1 G4 - 1 DIO14 QO14 G6 - 1 G4 - 1

G7 - 1 G5 - 1 DIO15 QO15 G7 - 1 G5 - 1

R0 - 1 DIO16 QO16 R0 - 1

R1 - 1 DIO17 QO17 R1 - 1

R2 - 1 R0 - 1 DIO18 QO18 R2 - 1 R0 - 1

R3 - 1 R1 - 1 DIO19 QO19 R3 - 1 R1 - 1

R4 - 1 R2 - 1 DIO20 QO20 R4 - 1 R2 - 1

R5 - 1 R3 - 1 DIO21 QO21 R5 - 1 R3 - 1

R6 - 1 R4 - 1 DIO22 QO22 R6 - 1 R4 - 1

R7 - 1 R5 - 1 DIO23 QO23 R7 - 1 R5 - 1

ShiftClk/2 ShiftClk/2 IDCK ODCK Shift CLK Shift CLK

VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC

HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC

DE DE DE DE DE DE