PEX 8111AA PR EL IM IN AR Y PCI Express-to-PCI Bridge Data Book Version 0.82 June 2005 Website www.plxtech.com Technical Support www.plxtech.com/support/ Phone 408 774-9060 800 759-3735 FAX 408 774-2169 Copyright (c) 2005 by PLX Technology Inc. All Rights Reserved - Version 0.82 June, 2005 June, 2005 PLX Technology, Inc. Revision History Revision Date Description of Changes 0.01 March 14, 2004 Initial spec. 0.02 May 25, 2004 Add pinouts and preliminary electrical specs. Part name change to PEX 8111. 0.03 June 2, 2004 Remove Theory of Operation Chapters. 0.04 September 28, 2004 Update pinouts, registers. 0.05 October 26, 2004 0.06 November 15, 2004 Miscellaneous changes. 0.80 December 2, 2004 Blue Book Initial Release. Miscellaneous changes; change EERDDATA from pull-down to pull-up. December 28, 2004 Update to Mechanical Drawing in Chapter 23. "Preliminary" removed from drawing, and critical dimensions now appear in table form. Miscellaneous changes. June 3, 2005 Silicon Revision AA update. Clock speed changed from 33 to 66 MHz. Changed non-connected pin NC2 to 66 MHz Enable, M66EN. Added new "Testability and Debug" (JTAG) chapter. Added new General Information" appendix, which includes Product Ordering Information. 0.82 PR EL IM IN AR Y 0.81 Add 144 pin package. Copyright Information Copyright (c) 2003, 2004, and 2005 PLX Technology, Inc. All rights reserved. The information in this document is proprietary to PLX Technology. No part of this document may be reproduced in any form or by any means or used to make any derivative work (such as translation, transformation, or adaptation) without written permission from PLX Technology. PLX Technology provides this documentation without warranty, term or condition of any kind, either express or implied, including, but not limited to, express and implied warranties of merchantability, fitness for a particular purpose, and non-infringement. While the information contained herein is believed to be accurate, such information is preliminary, and no representations or warranties of accuracy or completeness are made. In no event will PLX Technology be liable for damages arising directly or indirectly from any use of or reliance upon the information contained in this document. PLX Technology may make improvements or changes in the product(s) and/or the program(s) described in this documentation at any time. PLX Technology retains the right to make changes to this product at any time, without notice. Products may have minor variations to this publication, known as errata. PLX Technology assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX Technology products. PLX Technology, the PLX logo, and Data Pipe Architecture are registered trademarks of PLX Technology, Inc. PCI Express is a trademark of the PCI Special Interest Group. All product names are trademarks, registered trademarks, or servicemarks of their respective owners. ii PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 Preface Preface The information contained in this document is subject to change without notice. This PLX Document to be updated periodically as new information is made available. Scope This document describes the PEX 8111 bridge operation and provides operational data for customer use. Intended Audience This data book provides the functional details of PLX Technology PEX 8111 for both hardware designers and software/firmware engineers. This data book assumes that the reader has access to and is familiar with the documents referenced below. Supplemental Documentation This data book assumes that the reader is familiar with the documents referenced below. * PCI Special Interest Group (PCI-SIG) PR EL IM IN AR Y 5440 SW Westgate Drive #217, Portland, OR 97221 USA Tel: 503 291-2569, Fax: 503 297-1090, http://www.pcisig.com - PCI Local Bus Specification, Revision 2.3 - PCI Local Bus Specification, Revision 3.0 - PCI to PCI Bridge Architecture Specification, Revision 1.1 - PCI Express Base Specification 1.0a - PCI Bus Power Management Interface Specification, Revision 1.1 - PCI Express to PCI/PCI-X Bridge Specification 1.0 * The Institute of Electrical and Electronics Engineers, Inc. 445 Hoes Lane, PO Box 1331, Piscataway, NJ 08855-1331, USA Tel: 800 678-4333 (domestic only) or 732 981-0060, Fax: 732 981-1721, http://www.ieee.org - IEEE Standard 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture, 1990 - IEEE 1149.1a-1993, IEEE Standard Test Access Port and Boundary-Scan Architecture - IEEE Standard 1149.1b-1994, Specifications for Vendor-Specific Extensions PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 iii Data Book PLX Technology, Inc. Supplemental Documentation Abbreviations Note: In this data book, shortened titles are provided to the previously listed documents. The following table lists these abbreviations. Abbreviation PCI r3.0 P-to-P Bridge r1.1 PCI Power Management r1.1 PICMG 2.1 R2.0 PICMG 2.1 PCI Express Bridge IEEE Standard 1149.1-1990 Document PCI Local Bus Specification, Revision 3.0 PCI to PCI Bridge Architecture Specification, Revision 1.1 PCI Bus Power Management Interface Specification, Revision 1.1 R2.0 CompactPCI Hot Swap Specification PCI Express to PCI/PCI-X Bridge Specification 1.0 IEEE Standard Test Access Port and Boundary-Scan Architecture PR EL IM IN AR Y Data Assignment Conventions Data Width 1 byte (8 bits) 2 bytes (16 bits) 4 bytes (32-bits) 8 bytes (64-bits) iv PEX 8111 Convention Byte Word DWORD/DWord/Dword QWORD/QWord/Qword PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 General Definitions General Definitions The root complex denotes the device that connects the CPU and memory subsystem to the PCI-E fabric. It may support 1 or more PCI-E ports. A port is the interface between a PCI-E component and the link and consists of transmitters and receivers. An ingress port receives a packet. An egress port transmits a packet. A link is a physical connection between two devices that consists of xN lanes. An x1 link consists of 1 transmit and 1 receive signal where each signal is a differential pair. This is one lane. There are four lines or signals in an x1 link. PR EL IM IN AR Y * * * * ! $IFFERENTIAL 0AIR ! $IFFERENTIAL 0AIR IN EACH DIRECTION ONE ,ANE 4HIS IS AN X ,INK 4HERE ARE FOUR SIGNALS A lane is a differential signal pair in each direction. A switch appears to software as two or more logical PCI-to-PCI bridges. Endpoints are devices, other than the root complex and switches, that are requesters or completers of PCI-E transactions. * Endpoints may be PCI-E endpoints or legacy endpoints. * Legacy endpoints may support I/O and locked transaction semantics. PCI-E endpoints do not. A requester is a device that originates a transaction or puts a transaction sequence into the PCI-E fabric. A completer is a device addressed by a requester. A non-posted request packet sent by a requester has a completion packet returned by the associated completer. A posted request packet sent by a requester has no completion packet returned by the completer. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 v Data Book PLX Technology, Inc. PCI Express defines three layers: * Transaction Layer - The primary function of the Transaction Layer is assembly and disassembly of TLPs. The major components of a TLP are: Header, Data Payload, and an optional Digest Field. * Data Link Layer - The primary task of the link layer is to provide link management and data integrity, including error detection and correction. It defines the data control for PCI Express. * Physical Layer - The primary value to end users is that this layer appears to the upper layers to be PCI. It connects the lower protocols to the upper layers. There are three packet types: * TLP, Transaction Layer Packet * DLLP, Data Link Layer Packet * PLP, Physical Layer Packet PR EL IM IN AR Y A Transparent bridge provides connectivity from the conventional PCI or PCI-X bus system to the PCI Express hierarchy or subsystem. The bridge not only converts the physical bus to PCI Express point-topoint signaling; but it also translates the PCI or PCI-X bus protocol to PCI Express protocol. The Transparent bridge allows the address domain on one side of the bridge to be mapped into the CPU system hierarchy on the primary side of the bridge. vi PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 General Definitions PCI-PCI Express Specific Acronyms Acronym # ACK ADB ADQ Clock cycle CRS CSR DAC Destination Bus DLLP DMA Downstream DWORD FCP Forward Bridge Mode host HwInit PR EL IM IN AR Y BAR Byte CA CIS I I/O LVDSRn LVDSRp LVDSTn LVDSTp MAM MSI MWI NAK Non-Posted Transaction NS O OD Originating Bus PCI PCI PCI-E Definition Indicates an Active-Low signal Acknowledge Control Packet. A control packet used by a destination to acknowledge the receipt of a data packet. A signal that acknowledges the receipt of a signal. Allowable Disconnect Boundary Allowable Disconnect Quantity. In PCI Express, the ADQ is a buffer size. It is used to indicate memory requirements or reserves. Base Address Register 8-bit quantity of data. Completion with Completer Abort status. Card Information Structure. Describes resource requirements and other characteristics of a PC card. The operating system uses this information to configure the device in Plug and Play operations. One period of the PCI bus clock. Configuration Retry Status. Configuration Status Register; Control and status register; Command and status register Dual address cycle. A PCI transaction where a 64-bit address is transferred across a 32-bit data path in two clock cycles. The target of a transaction that crosses a bridge is said to reside on the destination bus. Data Link Layer Packet (originate at the Data Link Layer); can have Flow Control (FCx DLLPs) acknowledge packets (ACK and NAK DLLPs); and power management (PMx DLLPs). Direct Memory Access. Method of transferring data between a device and main memory without intervention by the CPU. Transactions that are forwarded from the primary bus to the secondary bus of a bridge are said to be flowing downstream. 32-bit quantity of data. Flow Control Packet Devices on each link exchange FCPs, which carry header and data payload credit information for one of three packet types: posted requests, non-posted requests and completions. The primary bus is closest to the PCI Express Root Complex. A host computer provides services to computers that connect to it on a network. It is considered to be in charge over the rest of the devices connected on the bus. Hardware initialized register or register bit: The register bits are initialized by either PEX 8111 hardware initialization mechanism or PEX 8111 EEPROM register initialization feature. The register bits are read-only after initialization and can only be reset with "Power Good Reset" CMOS Input CMOS Bi-Directional Input Output Differential low-voltage, high-speed, LVDS negative Receiver Inputs Differential low-voltage, high-speed, LVDS positive Receiver Inputs Differential low-voltage, high-speed, LVDS negative Transmitter Outputs Differential low-voltage, high-speed, LVDS positive Transmitter Outputs Master Abort Mode Message Signaled Interrupt Memory Write and Invalidate Negative Acknowledge A Memory Read, I/O Read or Write, or Configuration Read or Write that returns a completion to the master. No Snoop CMOS Output Open Drain The master of a transaction that crosses a bridge is said to reside on the originating bus. Peripheral Component Interconnect. A PCI bus is a high-performance bus that is 32-bit or 64-bit. It is designed to be used with devices that contain high-bandwidth requirements-- for example the display subsystem. It is an I/O bus that can be configured dynamically. PCI/PCI-X Compliant PCI Express PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 vii Data Book PLX Technology, Inc. PCI-PCI Express Specific Acronyms PCI Target PCI Transaction PCI Transfer Posted Transaction Primary Bus PU QoS RCB Reverse Bridge Mode R/W R/W1C R/W1CS R/WS RC RO RO RX SC Secondary Bus STRAP STS TC TLP TP TS TX Upstream UR VC Word Definition Drives the address phase and transaction boundary (FRAME#). Initiates a transaction and drives data handshaking (IRDY#) with the target. Claims the transaction by asserting DEVSEL# and handshakes the transaction (TRDY#) with the initiator. A read, write, read burst, or write burst operation on the PCI bus. It includes an address phase followed by one or more data phases. During a transfer, data is moved from the source to the destination on the PCI bus. The assertion of TRDY# and IRDY# indicates a data transfer. A memory write that does not return a completion to the master. The bus closest to the PCI Express Root Complex (Forward Bridge mode) or the PCI host CPU (Reverse Bridge mode). Signal is internally pulled up Quality of Service Read Boundary Completion The primary bus is closest to the PCI host CPU. Read-write register or register bit: The register bits are read-write and may be either set or cleared by software to the desired state. Read-only status - write 1b to clear status register or register bit. The register bits indicate status when read. A status bit set by the system to 1b to indicate status may be cleared by writing a 1b to that bit. Read-only status - write 1b to clear status register or register bit: The register bits indicate status when read. A status bit set by the system to 1b to indicate status may be cleared by writing a 1b to that bit. Writing 0b does not have any effect. Bits are not initialized or modified by reset. Devices that consume AUX power preserve register values when AUX power consumption is enabled (either by way of AUX power or PME Enable). Read-Write register or bit: The register bits are read-write and may be either set or cleared by software to the desired state. Bits are not initialized or modified by reset. Devices that consume AUX power preserve register values when AUX power consumption is enabled (either by way of AUX power or PME Enable). Root Complex Relaxed Ordering Read only register or register bit: The register bits are read-only and cannot be altered by software. The register bits may be initialized by either PEX 8111 hardware initialization mechanism or PEX 8111 EEPROM register initialization feature Received Packet Successful Completion. The bus farthest from the PCI Express Root Complex (Forward Bridge mode) or the PCI host CPU (Reverse Bridge mode). Strapping pads must be connected to H or L on the board PCIX Sustained Three-State Output, Driven High for One CLK before Float PR EL IM IN AR Y Acronym PCI Master (Initiator) Traffic Class Translation Layer Packet. Totem Pole Three-State Bi-Directional Transmitted Packet Transactions that are forwarded from the secondary bus to the primary bus of a bridge are said to be flowing upstream. Unsupported Request. Virtual Channel 16-bit quantity of data. This document contains material that is proprietary to PLX. Reproduction without the express written consent of PLX is prohibited. All reasonable attempts were made to ensure the contents of this document are accurate; however no liability, expressed or implied is guaranteed. PLX reserves the right to modify this document, without notification, at any time. viii PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 PLX Technology, Inc. Contents Chapter 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PEX 8111 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PEX 8111 Typical Forward Bridge Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . PEX 8111 Typical Reverse Bridge Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 2 1 1 2 3 3 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Chapter 3 PR EL IM IN AR Y Pin Description Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin Description (144 Pin PBGA Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Tables (144 Pin PBGA Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Physical Pin Assignment (144 Pin PBGA) -- Bottom View . . . . . . . . . . . . . . . . . . . 15 Pin Description (161 Pin FBGA Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Pin Tables (161 Pin FBGA Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Physical Pin Assignment (161 Pin FBGA Package) -- Bottom View . . . . . . . . . . . 25 Reset Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Forward Bridge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Reverse Bridge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Initialization Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Chapter 4 EEPROM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM Random Read/Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM Low-Level Access Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM Read Status Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM Write Data Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM Read Data Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 5 29 29 30 31 31 31 32 32 32 Address Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enable Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Base and Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGA Palette Snooping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory-Mapped I/O Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enable Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory-Mapped I/O Base and Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Prefetchable Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enable Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Prefetchable Base and Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 33 33 33 34 35 36 37 37 38 38 39 40 40 40 xi Contents PLX Technology, Inc. 64-Bit Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Forward Bridge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reverse Bridge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 6 Configuration Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 PR EL IM IN AR Y Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Type 0 Configuration Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Type 1 Configuration Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Type 1 to Type 0 Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Forward Bridge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reverse Bridge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Type 1 to Type 1 Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Forward Bridge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reverse Bridge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Type 1 to Special Cycle Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Express Enhanced Configuration Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory-Mapped Indirect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Retry Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Forward Bridge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reverse Bridge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 7 45 46 46 46 47 47 48 48 48 49 49 49 50 50 51 Error Handling (Forward Bridge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Express Originating Interface (Primary to Secondary) . . . . . . . . . . . . . . . . . . . . . . Received Poisoned TLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Uncorrectable Data Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Immediate Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Non-Posted Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Posted Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Address Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Master Abort on Posted Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Master Abort on Non-Posted Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Target Abort on Posted Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Target Abort on Non-Posted Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Retry Abort on Posted Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Retry Abort on Non-Posted Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Originating Interface (Secondary to Primary) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Received PCI Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Uncorrectable Data Error on Non-Posted Write . . . . . . . . . . . . . . . . . . . . . . . . Uncorrectable Data Error on Posted Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . Uncorrectable Data Error on PCI Delayed Read Completions . . . . . . . . . . . . . Uncorrectable Address Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unsupported Request (UR) Completion Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Abort Mode Bit Cleared . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Abort Mode Bit Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Completer Abort (CA) Completion Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timeout Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Express Completion Timeout Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Delayed Transaction Timeout Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Other Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii 42 42 43 44 53 53 54 54 54 54 55 55 55 55 56 56 56 56 57 57 57 58 58 58 58 58 59 59 59 59 59 60 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 Chapter 8 PLX Technology, Inc. Error Handling (Reverse Bridge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Chapter 9 PR EL IM IN AR Y Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Express Originating Interface (Secondary to Primary) . . . . . . . . . . . . . . . . . . . . . . Received Poisoned TLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Uncorrectable Data Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Immediate Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Non-Posted Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Posted Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Address Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Master Abort on Posted Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Master Abort on Non-Posted Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Target Abort on Posted Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Target Abort on Non-Posted Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Retry Abort on Posted Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Retry Abort on Non-Posted Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Originating Interface (Primary to Secondary) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Received PCI Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Uncorrectable Data Error on Non-Posted Write . . . . . . . . . . . . . . . . . . . . . . . . Uncorrectable Data Error on Posted Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . Uncorrectable Data Error on PCI Delayed Read Completions . . . . . . . . . . . . . Uncorrectable Address Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unsupported Request (UR) Completion Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Abort Mode Bit Cleared . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Abort Mode Bit Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Completer Abort (CA) Completion Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timeout Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Express Completion Timeout Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Delayed Transaction Timeout Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Other Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Express Error Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 61 61 62 62 62 62 62 62 63 63 63 63 63 63 64 64 64 65 65 65 65 65 65 66 66 66 66 66 Exclusive (Locked) Access (Forward Bridge) . . . . . . . . . . . . . . . . . . . . . . . . 67 Exclusive Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lock Sequence across PEX 8111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Master Rules for supporting LOCK# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Acquiring Exclusive Access across PEX 8111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Non-Posted Transactions and Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuing Exclusive Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Completing Exclusive Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Invalid PCI Express Requests while Locked . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Locked Transaction Originating on PCI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Bus Errors while Locked . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Master Abort during Non-Posted Transaction . . . . . . . . . . . . . . . . . . . . . . . . . PCI Master Abort during Posted Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Target Abort during Non-Posted Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Target Abort during Posted Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 67 67 67 68 68 68 68 68 68 69 69 69 69 69 xiii Contents Chapter 10 PLX Technology, Inc. Exclusive (Locked) Access (Reverse Bridge) . . . . . . . . . . . . . . . . . . . . . . . . .71 Exclusive Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Target Rules for Supporting LOCK# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Acquiring Exclusive Access across PEX 8111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Completing Exclusive Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Express Locked Read Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 11 Power Management (Forward Bridge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 PR EL IM IN AR Y Link State Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Link Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Link State Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set Slot Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 12 83 83 83 83 83 83 83 PCI Express Messages (Reverse Bridge) . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 INTx# Interrupt Message Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management Message Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PME Handling Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Error Signaling Message Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Locked Transaction Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiv 81 81 81 81 PCI Express Messages (Forward Bridge) . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INTx# Interrupt Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Error Signaling Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Locked Transactions Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slot Power Limit Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hot Plug Signaling Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 16 79 79 79 79 Interrupts (Reverse Bridge). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 PCI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally Generated Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INTx# Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Message Signaled Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 15 77 77 77 78 78 Interrupts (Forward Bridge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 PCI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally Generated Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Virtual Wire Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Message Signaled Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 14 73 73 74 75 75 75 76 76 Power Management (Reverse Bridge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Power Management States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PME# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set Slot Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 13 71 71 71 71 72 72 85 85 85 85 85 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 Chapter 17 PLX Technology, Inc. Initialization (Forward Bridge). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fundamental Reset (Cold/Warm Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Primary Reset Due to Physical Layer Mechanism (Hot Reset) . . . . . . . . . . . . . . . . Primary Reset Due to Data Link Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Secondary Bus Reset by way of Bridge Control Register . . . . . . . . . . . . . . . . . . . . Bus Parking during Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 18 87 87 87 87 88 88 88 Initialization (Reverse Bridge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Secondary Bus Reset by way of Bridge Control Register . . . . . . . . . . . . . . . . . . . . . . . 89 Chapter 19 PCI Arbiter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Chapter 20 PR EL IM IN AR Y Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Arbiter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single-Level Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multi-Level Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Arbiter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Arbitration Parking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shared Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Express Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 21 91 91 91 91 92 92 93 93 93 93 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Configuration Access Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Register Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 PCI-Compatible Configuration Registers (Type 1) . . . . . . . . . . . . . . . . . . . . . . . . . 97 PCI-Compatible Extended Capability Registers for PCI Express Bus . . . . . . . . . . . 97 PCI Express Extended Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Main Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 PCI-Compatible Configuration Registers (Type 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 PCI-Compatible Extended Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 PCI Express Extended Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 PCI Express Power Budgeting Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 PCI Express Serial Number Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Main Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Chapter 22 Testability and Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IEEE Standard 1149.1 Test Access Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Boundary Scan Boundary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Reset Input TRST# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 153 153 153 154 154 xv Contents Chapter 23 PLX Technology, Inc. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Bus DC Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Bus 33-MHz AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Bus 66-MHz AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 24 155 156 157 157 158 158 159 Mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161 PBGA (144 Pin Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 FBGA (161 Pin Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Appendix A General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 PR EL IM IN AR Y Product Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 United States and International Representatives and Distributors . . . . . . . . . . . . . . . . 165 Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 xvi PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 Chapter 1 Features * * * * * * * * * * * * * * 1.2 PCI Express Specification Revision 1.0a Compliant PCI Specification Revision 3.0 Compliant Forward and reverse transparent bridging between PCI Express and the PCI bus PCI Express 1 Lane Port (1 virtual channel) PCI Express 2.5 GBps per direction PCI Express full split completion protocol PCI 32-bit 66 MHz Bus Internal PCI Arbiter supporting up to 4 external PCI Masters PR EL IM IN AR Y 1.1 Introduction PCI Bus Power Management Interface 1.1 Compliant SPI EEPROM Port Internal 8 KByte shared RAM available to PCI Express and PCI buses Four GPIO pins Low power CMOS in 144 Pin PBGA or161 Pin FBGA Package 1.5V core operating voltage, 3.3V I/O, 5V Tolerant PCI Overview The PEX 8111 PCI Express to PCI Bridge allows for the use of ubiquitous PCI silicon with the high performance PCI Express Network. As PCI Express systems proliferate, there remain many applications that do not need the extensive bandwidth or performance features of PCI Express. With the PEX 8111, many existing chips and entire subsystems can be used with PCI Express motherboards without modification. PCI Express Endpoint Interface * * * * * * * * * * Full 2.5 Gbps per direction Single lane and Single virtual channel operation Compatible with multi lane and multi virtual channel PCI Express chips Packetized serial traffic with PCI Express split completion protocol Data link layer CRC generator and checker. Automatic retry of bad packets Integrated low voltage differential drivers 8b/10b signal encoding In-band interrupts and messages Support of message signaled interrupts PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 1 Introduction PLX Technology, Inc. PCI Bus Interface * * * * * * * PCI Revision 3.0-compliant 32-bit, 66 MHz PCI interface PCI master controller allows PCI Express access to PCI target devices PCI target controller allows full transparent access to PCI Express resources PCI target controller allows memory-mapped access to shared RAM and configuration registers PCI arbiter supports up to four external PCI bus masters Support of power management registers and PME# pin Support of message signaled interrupts Configuration Registers All internal registers are accessible from the PCI Express or PCI buses All internal registers can be set up through an external EEPROM Internal registers allow write and read to an external EEPROM Internal registers allow control of GPIO pins PR EL IM IN AR Y * * * * Data Transfer Pathways * * * * * * * * 1.3 PCI transparent bridge access to PCI Express PCI memory-mapped single access to internal configuration registers PCI memory-mapped single/burst access to internal shared RAM PCI configuration access to PCI configuration registers (Reverse Bridge mode only) PCI Express transparent bridge access to PCI bus targets PCI Express memory-mapped single access to internal configuration registers PCI Express memory-mapped single/burst access to internal shared RAM PCI Express configuration access to PCI configuration registers (Forward Bridge mode only) PEX 8111 Block Diagram PC I Express Interface Fully Transparent P C I E xpress to PC I B ridge PC I Interface PCI Bus PCI Express C onfiguration R egisters 8 K B S hared M em ory 2 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 1.3.1 PEX 8111 Typical Forward Bridge Block Diagram PEX 8111 Typical Forward Bridge Block Diagram EEPROM Legacy PCI Chip PCI Based CPU PCI Bus PR EL IM IN AR Y PEX 8111 Proprietary PCI ASIC PCI Express 1.3.2 PEX 8111 Typical Reverse Bridge Block Diagram EEPROM PEX 8111 PCI Express Bus PCI Express I/O Device PCI Bus PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 3 PLX Technology, Inc. PR EL IM IN AR Y Introduction 4 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 Chapter 2 2.1 Pin Descriptions Pin Description Abbreviations Table 2-1. Pin Description Abbreviations (PBGA and FBGA Packages) Abbreviation Description I Input O Output I/O Bi-Directional PCI PCI-Compatible buffer, 26mA drive S TS STS TP OD PD PU # PCI Express Differential buffer PR EL IM IN AR Y DIFF Schmitt Trigger Tri-State Sustained Tri-State, driven inactive one clock cycle before float Totem-Pole Open-Drain 50K Pull-Down 50K Pull-Up Active low PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 5 Pin Descriptions 2.2 PLX Technology, Inc. Pin Description (144 Pin PBGA Package) Table 2-2. Signal 6 Power and Ground (46 pins) (144 Pin PBGA Package) Type Pins Power E7 AVSS Ground C7 GND Ground VDD_P Power A12, B4, C3, C11, D9, E6, F12, G5, H4, H7, J4, J8, K2, K10 D5 VDD_R Power A7 VDD_T Power VDD1.5 Power VDD3.3 Power VDD5 Power VDDQ Power VSS_C Ground VSS_P0 Ground VSS_P1 Ground VSS_R Ground VSS_RE Ground F7 VSS_T Ground C5 Analog Supply Voltage. Connect to the +1.5V supply. Analog Ground. Connect to ground. Ground. Connect to ground PLL Supply Voltage. Connect to the +1.5V filtered PLL supply. Receiver Supply Voltage. Connect to the +1.5V supply. Transmitter Supply Voltage. Connect to the +1.5V supply. Core Supply Voltage. Connect to the +1.5V supply. I/O Supply Voltage. Connect to the +3.3V supply. PCI I/O Clamp Voltage. Connect to the +5.0V supply for PCI buffers. In a 3.3V PCI environment, these pins can be connected to the 3.3V supply. I/O Supply Voltage. Connect to the +3.3V supply for PCI buffers. Common Ground. Connect to ground. PLL Ground. Connect to ground. PLL Ground. Connect to ground. Receiver Ground. Connect to ground. Receiver Ground. Connect to ground. Transmitter Ground. Connect to ground. PR EL IM IN AR Y AVDD Description A5 C10, D4, F6, F8, G6, G7, J9, K3 B3, B11, L2, M10 F5, G8, H6 E5, F9, G4, H5, H8, J7 D7 D6 C6 B8 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 Pin Description (144 Pin PBGA Package) Table 2-3. PERn0 PERp0 PERST# PETn0 PETp0 REFCLK- REFCLK+ WAKEIN# WAKEOUT# Type I DIFF I DIFF I/O 6mA 3.3V O DIFF O DIFF I DIFF Pins B7 A8 B12 A4 B5 B6 Description Receive Minus. PCI Express Differential Receive Signal Receive Plus. PCI Express Differential Receive Signal PCI Express Reset. In Forward Bridge mode, this bit is an input. It resets the entire chip when asserted. In Reverse Bridge mode, this bit is an output. It is asserted when a PCI reset is detected. Transmit Minus. PCI Express Differential Transmit Signal Transmit Plus. PCI Express Differential Transmit Signal PCI Express Clock Input Minus. PCI Express differential, 100 MHz spread spectrum reference clock. This signal is connected to the PCI Express bus REFCLK- pin in Forward Bridge mode, and to an external differential clock driver in Reverse Bridge mode. PCI Express Clock Input Plus. PCI Express differential, 100 MHz spread spectrum reference clock. This signal is connected to the PCI Express bus REFCLK+ pin in Forward Bridge mode, and to an external differential clock driver in Reverse Bridge mode. Wake In Signal. In Reverse Bridge mode, this signal is an input, and indicates that the PCI Express Device has requested a wakeup while the link is in the L2 state. Wake Out Signal. In Forward Bridge mode, this signal is an output, and is asserted when the PME# pin is asserted and the link is in the L2 state. PR EL IM IN AR Y Signal Name PCI Express Pins (9 pins) (144 Pin PBGA Package) I DIFF A6 I 3.3V C12 OD 6mA 3.3V A9 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 7 Pin Descriptions PLX Technology, Inc. Table 2-4. Signal 8 PCI Pins (63 pins) (144 Pin PBGA Package) Type Pins Description I/O TS PCI J10, J12, J11, K12, L9, M9, K8, L8, K7, L7, M7, J6, K6, M6, L6, J5, H2, H1, G3, G2, G1, F4, F3, F2, E4, E3, E2, E1, D2, D1, C1, D3 M8, K5, H3, F1 CBE[3:0]# I/O TS PCI DEVSEL# I/O STS PCI FRAME# I/O STS PCI GNT[3:0]# I/O TS PCI E11, F11, G9, G10 IDSEL I PCI K9 Address/Data Bus. The PCI address and data are multiplexed onto the same bus. During the address phase, AD[31:0] contain the physical address of the transfer. During the data phase, AD[31:0] contain the data. AD31 is the most significant bit. Write data is stable when IRDY# is asserted, and read data is stable when TRDY# is asserted. Data is transferred when both IRDY# and TRDY# are asserted. Command/Byte Enable Bus. The bus command and byte enables are multiplexed onto the same bus. During the address phase, CBE[3:0]# contain the bus command. During the data phase, CBE[3:0]# contain the byte enables. CBE0# corresponds to byte 0 (AD[7:0]), and CBE3# corresponds to byte 3 (AD[31:24]). CBE[3:0]# Command 0000 Interrupt Acknowledge 0001 Special Cycle 0010 I/O Read 0011 I/O Write 0100 Reserved 0101 Reserved 0110 Memory Read 0111 Memory Write 1000 Reserved 1001 Reserved 1010 Configuration Read 1011 Configuration Write 1100 Memory Read Multiple 1101 Dual Address Cycle 1110 Memory Read Line 1111 Memory Write and Invalidate Device Select. This signal indicates that the target (bus slave) has decoded its address during the current bus transaction. As an input, DEVSEL# indicates whether any device on the bus has been selected. Frame. This signal is driven by the initiator, and indicates the beginning and duration of an access. When FRAME# is first asserted, the address phase is indicated. When FRAME# is negated, the transaction is in the last data phase. Bus Grant. These signals indicate that the central arbiter has granted the bus to an agent. If the internal PCI arbiter is enabled, these pins are outputs used to grant the bus to external devices. If the internal PCI arbiter is disabled, GNT0# is an input used to grant the bus to the PEX 8111. Initialization Device Select. This signal is used as a chip select during Configuration Read and Write cycles. Each PCI slot or device typically has its IDSEL connected to a signal address line, allowing the PCI host to select individual sets of configuration registers. This pin is only used in Reverse Bridge mode. In Forward Bridge mode, it can either be grounded or pulled up to 3.3V. PR EL IM IN AR Y AD[31:0] K4 M5 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 Pin Description (144 Pin PBGA Package) Table 2-4. Signal PCI Pins (63 pins) (144 Pin PBGA Package) (Cont.) Type Pins INTA#, INTB#, INTC#, INTD# I/O OD PCI E12, E9, D11, E10 IRDY# I/O STS PCI I/O STS PCI L5 M66EN I PCI M3 D10 J1 PAR I/O TS PCI PCIRST# I/O OD PCI PCLKI I PCI D12 PERR# I/O STS PCI I S PCI OD 24mA 3.3V J3 PMEIN# PMEOUT# Interrupt. These signals are asserted to request an interrupt. Once asserted, it must remain asserted until the device driver clears it. INTx# is level sensitive and is asynchronous to the CLK. In Forward Bridge mode, INTx# is an input from PCI devices. All INTx# signals are mapped into Assert_INTx and Deassert_INTx messages on the PCI Express side. In Reverse Bridge mode, INTx# is an output to the PCI Central Resource Function. All Assert_INTx and Deassert_INTx PCI Express messages are translated to INTx# transitions on the PCI side. Initiator Ready. This signal indicates that the initiator (bus master) is ready to transfer data. A data phase is completed when both IRDY# and TRDY# are asserted. Lock an Atomic Operation. Indicates an atomic operation to a bridge that may require multiple transactions to complete. It is an output in Forward Bridge mode and an input in Reverse Bridge mode. 66 MHz Enable. Indicates whether the PCI bus is operating at 33 or 66 MHz. When low, and the PCLKO divider is 3, then the PCLKO pin oscillates at 33 MHz with a 50 percent duty cycle. When high, and the PCLKO divider is 3, then the PCLKO pin oscillates at 66 MHz with a 33 percent duty cycle. This pin can be read using the PCICTL register, bit 7. In 33-MHz systems, this pin should be grounded. PR EL IM IN AR Y LOCK# Description F10 H12 L12 Parity. Even parity is generated across AD[31:0], and C/BE[3:0]#. This means that the number of `1's on AD[31:0], C/BE[3:0]#, and PAR is an even number. PAR is valid one clock after the address phase. For data phases, PAR is valid one clock after IRDY# is asserted on write cycles, and one clock after TRDY# is asserted on read cycles. PAR has the same timing as AD[31:0], except delayed by one clock cycle. The bus initiator drives PAR for address and write data phases, and the target drives PAR for read data phases. PCI Reset. In Forward Bridge mode, this pin is driven when either a PCI Express reset is detected, or when the Secondary Bus Reset bit in the Bridge Control register is set. In Reverse Bridge mode, this is an input pin that resets the entire chip. Reset is asserted and negated asynchronously to CLK, and is used to bring a PCI device to an initial state. All PCI signals are asynchronously tri-stated during reset. PCI Clock Input. All PCI signals, except RST# and interrupts, are sampled on the rising edge of this clock. The frequency can vary from 0 to 66 MHz. This clock needs to be oscillating during the EEPROM initialization sequence. Parity Error. This signal indicates that a data parity error has occurred. It is driven active by the receiving agent two clocks following the data that had bad parity. Power Management Event In. This pin as an input used to monitor requests to change the system's power state. This pin is only valid in Forward Bridge mode. Power Management Event Out. This pin is an open-drain output used to request a change in the power state. This pin is only valid in Reverse Bridge mode. This pin is not 5V tolerant. If it is used in a system with a 5V pull-up resistor on the PME# signal, then an external voltage translation circuit is required. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 9 Pin Descriptions PLX Technology, Inc. Table 2-4. Signal PCI Pins (63 pins) (144 Pin PBGA Package) (Cont.) Type Pins Description I/O TS PCI H11, G12, H9, G11 SERR# I/O OD PCI J2 STOP# I/O STS PCI L4 TRDY# I/O STS PCI 10 Bus Request. These signals indicate that an agent desires use of the bus. If the internal PCI arbiter is enabled, these pins are inputs used to service external bus requests. If the internal PCI arbiter is disabled, REQ0# is an output used to request control of the bus. System Error. This signal indicates that an address parity error, data parity error on the Special Cycle command, or other catastrophic error has occurred. It is driven active for one PCI clock period, and is synchronous to the CLK. This signal is only driven in Reverse Bridge mode. Stop. This signal indicates that the target (bus slave) is requesting that the master stop the current transaction. Once STOP# is asserted, it must remain asserted until FRAME# is negated, whereupon STOP# must be negated. Also, DEVSEL# and TRDY# cannot be changed until the current data phase completes. STOP# must be negated in the clock following the completion of the last data phase, and must be tri-stated in the next clock. Data is transferred when IRDY# and TRDY# are asserted, independent of STOP#. Target Ready. This signal indicates that the target (bus slave) is ready to transfer data. A data phase is completed when both IRDY# and TRDY# are asserted. PR EL IM IN AR Y REQ[3:0]# M4 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 Pin Description (144 Pin PBGA Package) Table 2-5. Signal Type Pins O 3mA TP 3.3V O 3mA TP 3.3V I 3.3V B2 O 3mA TP 3.3V I 3.3V A2 FORWARD I 3.3V L11 GPIO[3:0] I/O 12mA 3.3V A11, B10, A10, C9 NC1, NC3 -- C2, E8 PCLKO O 26mA TP PCI O 6mA 3.3V EECS# EERDDATA EEWRDATA EXTARB PWR_OK C4 A1 Description EEPROM Clock. This pin provides the clock to the EEPROM. The frequency of this pin is determined by the EECLKFREQ register, and can vary from 2 MHz to 25 MHz. EEPROM Chip Select. Active low chip select. EEPROM Read Data. This pin is used to read data from the device. A 47K pull-up resistor is required on this pin. EEPROM Write Data. This pin is used to write data to the device. PR EL IM IN AR Y EECLK Clocks, Reset, Miscellaneous (14 pins) (144 Pin PBGA Package) K11 H10 B9 External Arbiter Enable. When low, the internal PCI arbiter services requests from an external PCI device. When high, the PEX 8111 requests the PCI bus from an external arbiter. Bridge Select. When low, the chip acts as a PCI to PCI Express Bridge (reverse bridge). When this bit is high, the chip acts as a PCI Express to PCI Bridge (forward bridge). General Purpose I/O. Each of these bits can be programmed as either an input or output generalpurpose pin. Interrupts can be generated on each of the pins that are programmed as inputs. No Connect. These pins must be left open. PCI Clock Output. This pin is a buffered clock output from the internal 100 MHz reference clock, with the frequency depending on the PCLKO Clock Frequency field of the DEVINIT register. Power OK. When the available power indicated in the Set Slot Power Limit message is greater than or equal to the power requirement indicated in the POWER register, this pin is asserted. It is only valid in Forward Bridge mode. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 11 Pin Descriptions PLX Technology, Inc. Table 2-6. Type Pins Description BUNRI I D8 TEST I A3 SMC I K1 TMC I C8 TMC1 I B1 TMC2 I M1 BTON PR EL IM IN AR Y Signal Test Pins (12 pins) (144 Pin PBGA Package) I M11 I PU L3 O 12mA TS 3.3V L1 I M2 TMS I PU M12 TRST# I PU L10 TDI TDO TCK 12 Test Mode Select. Connect to ground for normal operation. Test Mode Select. Connect to ground for normal operation. Scan Path Mode Control. Connect to ground for normal operation. Test Mode Control. Connect to ground for normal operation. IDDQ Test Control Input. Connect to ground for normal operation. I/O Buffer Control. Connect to ground for normal operation. Test Enable. Connect to ground for normal operation. Test Data Input. This pin is the serial data input to all JTAG instruction and data registers. The state of the TAP (Test Access Port) controller as well as the particular instruction held in the instruction register determines which register is fed by TDI for a specific operation. TDI is sampled into the JTAG registers on the rising edge of TCK. This pin should be left open if JTAG is not used. Test Data Output. This pin is the serial data output for all JTAG instruction and data registers. The state of the TAP controller as well as the particular instruction held in the instruction register determines which register feeds TDO for a specific operation. Only one register (instruction or data) is allowed to be the active connection between TDI and TDO for any given operation. TDO changes state on the falling edge of TCK and is only active during the shifting of data through the device. This pin is three-stated at all other times. This pin should be left open if JTAG is not used. Test Clock. This pin is the JTAG test clock. It sequences the TAP controller as well as all of the JTAG registers provided in the PEX 8111. This pin should be left open if JTAG is not used. Test Mode Select. This pin is the mode input signal to the TAP Controller. The TAP controller is a 16-state FSM that provides the control logic for JTAG. The state of TMS at the rising edge of TCK determines the sequence of states for the TAP controller. This pin should be left open if JTAG is not used. Test Reset. This pin resets the JTAG TAP controller when driven to ground. This pin should be left open if JTAG is not used. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 2.2.1 Pin Tables (144 Pin PBGA Package) Pin Tables (144 Pin PBGA Package) Table 2-7. Signal EERDDATA EEWRDATA TEST PETn0 VDD_T REFCLK+ VDD_R PERp0 WAKEOUT# GPIO1 GPIO3 GND TMC1 EECLK VDD3.3 GND PETp0 REFCLKPERn0 VSS_R PWR_OK GPIO2 VDD3.3 PERST# AD1 NC1 GND EECS# VSS_T VSS_P1 AVSS TMC GPIO0 VDD1.5 GND WAKEIN# Grid D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 Signal AD2 AD3 AD0 VDD1.5 VDD_P VSS_P0 VSS_C BUNRI GND M66EN INTC# PCLKI AD4 AD5 AD6 AD7 VDDQ GND AVDD NC3 INTB# INTD# GNT3# INTA# CBE0# AD8 AD9 AD10 VDD5 VDD1.5 VSS_RE VDD1.5 VDDQ PCIRST# GNT2# GND Grid G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 Signal AD11 AD12 AD13 VDDQ GND VDD1.5 VDD5 GNT1# GNT0# REQ0# REQ2# AD14 AD15 CBE1# GND VDDQ VDD5 GND VDDQ REQ1# PCLKO REQ3# PMEIN# PAR SERR# PERR# GND AD16 AD20 VDDQ GND VDD1.5 AD31 AD29 AD30 PR EL IM IN AR Y Grid A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 Grid Order (144 Pin PBGA Package) PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 Grid K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 Signal SMC GND VDD1.5 DEVSEL# CBE2# AD19 AD23 AD25 IDSEL GND EXTARB AD28 TDO VDD3.3 TDI STOP# IRDY# AD17 AD22 AD24 AD27 TRST# FORWARD PMEOUT# TMC2 TCK LOCK# TRDY# FRAME# AD18 AD21 CBE3# AD26 VDD3.3 BTON TMS 13 Pin Descriptions PLX Technology, Inc. Table 2-8. D3 C1 D1 D2 E1 E2 E3 E4 F2 F3 F4 G1 G2 G3 H1 H2 J5 L6 M6 K6 J6 M7 L7 K7 L8 K8 M9 L9 K12 J11 J12 J10 E7 C7 M11 D8 14 Signal AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 AVDD AVSS BTON BUNRI Grid F1 H3 K5 M8 K4 B2 C4 A1 A2 K11 L11 M5 A12 B4 C3 C11 D9 E6 F12 G5 H4 H7 J4 J8 K2 K10 G10 G9 F11 E11 C9 A10 B10 A11 K9 E12 Signal CBE0# CBE1# CBE2# CBE3# DEVSEL# EECLK EECS# EERDDATA EEWRDATA EXTARB FORWARD FRAME# Grid E9 D11 E10 L5 M3 C2 D10 E8 J1 F10 D12 H10 B7 A8 J3 B12 A4 B5 H12 L12 B9 B6 A6 G11 H9 G12 H11 J2 K1 L4 M2 L3 L1 A3 C8 B1 Signal INTB# INTC# INTD# IRDY# LOCK# NC1 M66EN NC3 PAR PCIRST# PCLKI PCLKO PERn0 PERp0 PERR# PERST# PETn0 PETp0 PMEIN# PMEOUT# PWR_OK REFCLKREFCLK+ REQ0# REQ1# REQ2# REQ3# SERR# SMC STOP# TCK TDI TDO TEST TMC TMC1 PR EL IM IN AR Y Grid Signal Order (144 Pin PBGA Package) GND GNT0# GNT1# GNT2# GNT3# GPIO0 GPIO1 GPIO2 GPIO3 IDSEL INTA# Grid M1 M12 M4 L10 D5 A7 A5 C10 D4 F6 F8 G6 G7 J9 K3 B3 B11 L2 M10 F5 G8 H6 E5 F9 G4 H5 H8 J7 D7 D6 C6 B8 F7 C5 C12 A9 Signal TMC2 TMS TRDY# TRST# VDD_P VDD_R VDD_T VDD1.5 VDD3.3 VDD5 VDDQ VSS_C VSS_P0 VSS_P1 VSS_R VSS_RE VSS_T WAKEIN# WAKEOUT# PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 2.2.2 Physical Pin Assignment (144 Pin PBGA) -- Bottom View Physical Pin Assignment (144 Pin PBGA) -- Bottom View L K J H G F E D C B A TMS PMEOUT# AD28 AD30 PMEIN# REQ2# GND INTA# PCLKI WAKEIN# PERST# GND 12 BTON FORWARD EXTARB AD29 REQ3# REQ0# GNT2# GNT3# INTC# GND VDD3.3 GPIO3 11 VDD3.3 TRST# GND AD31 PCLKO GNT0# PCIRST# INTD# M66EN VDD1.5 GPIO2 GPIO1 10 AD26 AD27 IDSEL VDD1.5 REQ1# GNT1# VDDQ INTB# GND GPIO0 PWR_OK WAKEOUT# 9 CBE3# AD24 AD25 GND VDDQ VDD5 VDD1.5 NC3 BUNRI TMC VSS_R PERp0 8 AD21 AD22 AD23 VDDQ GND VDD1.5 VSS_RE AVDD VSS_C AVSS PERn0 VDD_R 7 AD18 AD17 AD19 AD20 VDD5 VDD1.5 VDD1.5 GND VSS_P0 VSS_P1 REFCLK- REFCLK+ 6 FRAME# IRDY# CBE2# AD16 VDDQ GND VDD5 VDDQ VDD_P VSS_T PETp0 VDD_T 5 TRDY# STOP# DEVSEL# GND GND VDDQ AD10 AD7 VDD1.5 EECS# GND PETn0 4 LOCK# TDI VDD1.5 PERR# CBE1# AD13 AD9 AD6 AD0 GND VDD3.3 TEST 3 TCK VDD3.3 GND SERR# AD15 AD12 AD8 AD5 AD3 NC1 EECLK EEWRDATA 2 TMC2 TDO SMC PAR AD14 AD11 CBE0# AD4 AD2 AD1 TMC1 EERDDATA 1 PR EL IM IN AR Y M PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 15 Pin Descriptions 2.3 PLX Technology, Inc. Pin Description (161 Pin FBGA Package) Table 2-9. Signal Power and Ground (46 pins) (161 Pin FBGA Package) Type Pins AVDD Power C8 AVSS Ground C6 GND Ground VDD_P Power A4, C13, D5, D12, E4, E11, F11, J2, K4, K11, L4, M6, N9, P12 B6 VDD_R Power VDD_T Power VDD1.5 Power VDD3.3 Power VDD5 Power VDDQ Power VSS_C Ground VSS_P0 Ground VSS_P1 Ground VSS_R Ground VSS_RE Ground VSS_T Ground 16 Description Analog Supply Voltage. Connect to the +1.5V supply. Analog Ground. Connect to ground. Ground. Connect to ground. PR EL IM IN AR Y PLL Supply Voltage. Connect to the +1.5V filtered PLL supply. C7 Receiver Supply Voltage. Connect to the +1.5V supply. D6 Transmitter Supply Voltage. Connect to the +1.5V supply. B10, C1, C14, G2, G13, Core Supply Voltage. L3, L11, N7 Connect to the +1.5V supply. B4, C11, L10, N3 I/O Supply Voltage. Connect to the +3.3V supply. G3, H13, L7 PCI I/O Clamp Voltage. Connect to the +5.0V supply for PCI buffers. In a 3.3V PCI environment, these pins can be connected to the 3.3V supply. F4, G12, H4, J12, L8, N5 I/O Supply Voltage. Connect to the +3.3V supply for PCI buffers. D9 Common Ground. Connect to ground. D7 PLL Ground. Connect to ground. D8 PLL Ground. Connect to ground. A9 Receiver Ground. Connect to ground. B8 Receiver Ground. Connect to ground. A5 Transmitter Ground. Connect to ground. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 Pin Description (161 Pin FBGA Package) Table 2-10. PERn0 PERp0 PERST# PETn0 PETp0 REFCLK- REFCLK+ WAKEIN# WAKEOUT# Type Pins I DIFF I DIFF I/O 6mA 3.3V B9 O DIFF O DIFF I DIFF B5 I DIFF B7 I 3.3V D14 OD 6mA 3.3V A11 A8 C12 A6 A7 Description Receive Minus. PCI Express Differential Receive Signal Receive Plus. PCI Express Differential Receive Signal PCI Express Reset. In Forward Bridge mode, this bit is an input. It resets the entire chip when asserted. In Reverse Bridge mode, this bit is an output. It is asserted when a PCI reset is detected. Transmit Minus. PCI Express Differential Transmit Signal Transmit Plus. PCI Express Differential Transmit Signal PCI Express Clock Input minus. PCI Express differential, 100 MHz spread spectrum reference clock. This signal is connected to the PCI Express bus REFCLK- pin in Forward Bridge mode, and to an external differential clock driver in Reverse Bridge mode. PCI Express Clock Input plus. PCI Express differential, 100 MHz spread spectrum reference clock. This signal is connected to the PCI Express bus REFCLK+ pin in Forward Bridge mode, and to an external differential clock driver in Reverse Bridge mode. Wake In Signal. In Reverse Bridge mode, this signal is an input, and indicates that the PCI Express Device has requested a wakeup while the link is in the L2 state. Wake Out Signal. In Forward Bridge mode, this signal is an output, and is asserted when the PME# pin is asserted and the link is in the L2 state. PR EL IM IN AR Y Signal Name PCI Express Pins (9 pins) (161 Pin FBGA Package) PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 17 Pin Descriptions PLX Technology, Inc. Table 2-11. Signal PCI Pins (62 pins) (162 Pin FBGA Package) Type Pins Description Address/Data Bus. The PCI address and data are multiplexed onto the same bus. During the address phase, AD[31:0] contain the physical address of the transfer. During the data phase, AD[31:0] contain the data. AD31 is the most significant bit. Write data is stable when IRDY# is asserted, and read data is stable when TRDY# is asserted. Data is transferred when both IRDY# and TRDY# are asserted. Command/Byte Enable Bus. The bus command and byte enables are multiplexed onto the same bus. During the address phase, CBE[3:0]# contain the bus command. During the data phase, CBE[3:0]# contain the byte enables. CBE0# corresponds to byte 0 (AD[7:0]), and CBE3# corresponds to byte 3 (AD[31:24]). I/O TS PCI CBE[3:0]# I/O TS PCI M9, P6, K1, G1 PR EL IM IN AR Y AD[31:0] L13, J11, K12, L12, M10, P11, P10, P9, L9, N8, P8, M8, M7, L6, N6, P7, K2, J3, J1, H2, H3, H1, G4, F3, F2, F1, E2, E3, E1, D3, D1, D2 M4 DEVSEL# I/O STS PCI FRAME# I/O STS PCI L5 GNT[3:0]# I/O TS PCI F12, G11, J13, J14 IDSEL I PCI N10 18 CBE[3:0]# Command 0000 Interrupt Acknowledge 0001 Special Cycle 0010 I/O Read 0011 I/O Write 0100 Reserved 0101 Reserved 0110 Memory Read 0111 Memory Write 1000 Reserved 1001 Reserved 1010 Configuration Read 1011 Configuration Write 1100 Memory Read Multiple 1101 Dual Address Cycle 1110 Memory Read Line 1111 Memory Write and Invalidate Device Select. This signal indicates that the target (bus slave) has decoded its address during the current bus transaction. As an input, DEVSEL# indicates whether any device on the bus has been selected. Frame. This signal is driven by the initiator, and indicates the beginning and duration of an access. When FRAME# is first asserted, the address phase is indicated. When FRAME# is negated, the transaction is in the last data phase. Bus Grant. These signals indicate that the central arbiter has granted the bus to an agent. If the internal PCI arbiter is enabled, these pins are outputs used to grant the bus to external devices. If the internal PCI arbiter is disabled, GNT0# is an input used to grant the bus to the PEX 8111. Initialization Device Select. This signal is used as a chip select during Configuration Read and Write cycles. Each PCI slot or device typically has its IDSEL connected to a signal address line, allowing the PCI host to select individual sets of configuration registers. This pin is only used in Reverse Bridge mode. In Forward Bridge mode, it can either be grounded or pulled up to 3.3V. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 Pin Description (161 Pin FBGA Package) Table 2-11. Signal PCI Pins (62 pins) (162 Pin FBGA Package) (Cont.) Type Pins INTA#, INTB#, INTC#, INTD# I/O OD PCI F14, F13, E14, E13 IRDY# I/O STS PCI I/O STS PCI P5 M66EN I PCI P4 D13 J4 PAR I/O TS PCI PCIRST# I/O OD PCI PCLKI I PCI E12 PERR# I/O STS PCI I S PCI OD 24mA 3.3V L2 PMEIN# PMEOUT# Interrupt. These signals are asserted to request an interrupt. Once asserted, it must remain asserted until the device driver clears it. INTx# is level sensitive and is asynchronous to the CLK. In Forward Bridge mode, INTx# is an input from PCI devices. All INTx# signals are mapped into Assert_INTx and Deassert_INTx messages on the PCI Express side. In Reverse Bridge mode, INTx# is an output to the PCI Central Resource Function. All Assert_INTx and Deassert_INTx PCI Express messages are translated to INTx# transitions on the PCI side. Initiator Ready. This signal indicates that the initiator (bus master) is ready to transfer data. A data phase is completed when both IRDY# and TRDY# are asserted. Lock an Atomic Operation. Indicates an atomic operation to a bridge that may require multiple transactions to complete. It is an output in Forward Bridge mode and an input in Reverse Bridge mode. 66 MHz Enable. Indicates whether the PCI bus is operating at 33 or 66 MHz. When low, and the PCLKO divider is 3, then the PCLKO pin oscillates at 33 MHz with a 50 percent duty cycle. When high, and the PCLKO divider is 3, then the PCLKO pin oscillates at 66 MHz with a 33 percent duty cycle. This pin can be read using the PCICTL register, bit 7. In 33-MHz systems, this pin should be grounded. PR EL IM IN AR Y LOCK# Description G14 L14 M14 Parity. Even parity is generated across AD[31:0], and C/BE[3:0]#. This means that the number of `1's on AD[31:0], C/BE[3:0]#, and PAR is an even number. PAR is valid one clock after the address phase. For data phases, PAR is valid one clock after IRDY# is asserted on write cycles, and one clock after TRDY# is asserted on read cycles. PAR has the same timing as AD[31:0], except delayed by one clock cycle. The bus initiator drives PAR for address and write data phases, and the target drives PAR for read data phases. PCI Reset. In Forward Bridge mode, this pin is driven when either a PCI Express reset is detected, or when the Secondary Bus Reset bit in the Bridge Control register is set. In Reverse Bridge mode, this is an input pin that resets the entire chip. Reset is asserted and negated asynchronously to CLK, and is used to bring a PCI device to an initial state. All PCI signals are asynchronously tri-stated during reset PCI Clock Input. All PCI signals, except RST# and interrupts, are sampled on the rising edge of this clock. The frequency can vary from 0 to 66 MHz. This clock needs to be oscillating during the EEPROM initialization sequence. Parity Error. This signal indicates that a data parity error has occurred. It is driven active by the receiving agent two clocks following the data that had bad parity. Power Management Event In. This pin as an input used to monitor requests to change the power state of the system.This pin is only valid in Forward Bridge mode. Power Management Event Out. This pin is an open-drain output used to request a change in the power state. This pin is only valid in Reverse Bridge mode. This pin is not 5V tolerant. If it is used in a system with a 5V pull-up resistor on the PME# signal, then an external voltage translation circuit is required. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 19 Pin Descriptions PLX Technology, Inc. Table 2-11. Signal Type PCI Pins (62 pins) (162 Pin FBGA Package) (Cont.) Pins I/O TS PCI SERR# I/O OD PCI L1 STOP# I/O STS PCI N4 TRDY# I/O STS PCI 20 Description Bus Request. These signals indicate that an agent desires use of the bus. If the internal PCI arbiter is enabled, these pins are inputs used to service external bus requests. If the internal PCI arbiter is disabled, REQ0# is an output used to request control of the bus. System Error. This signal indicates that an address parity error, data parity error on the Special Cycle command, or other catastrophic error has occurred. It is driven active for one PCI clock period, and is synchronous to the CLK. This signal is only driven in Reverse Bridge mode. Stop. This signal indicates that the target (bus slave) is requesting that the master stop the current transaction. Once STOP# is asserted, it must remain asserted until FRAME# is negated, whereupon STOP# must be negated. Also, DEVSEL# and TRDY# cannot be changed until the current data phase completes. STOP# must be negated in the clock following the completion of the last data phase, and must be tri-stated in the next clock. Data is transferred when IRDY# and TRDY# are asserted, independent of STOP#. Target Ready. This signal indicates that the target (bus slave) is ready to transfer data. A data phase is completed when both IRDY# and TRDY# are asserted. PR EL IM IN AR Y REQ[3:0]# H11, H12, K13, K14 M5 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 Pin Description (161 Pin FBGA Package) Table 2-12. EECLK EECS# EERDDATA EEWRDATA EXTARB Type O 3mA TP 3.3V O 3mA TP 3.3V I 3.3V C2 O 3mA TP 3.3V I 3.3V A3 FORWARD I 3.3V GPIO[3:0] I/O 12mA 3.3V NA -- NC1, NC3 -- PCLKO O 26mA TP PCI O 6mA 3.3V PWR_OK Pins C5 B3 Description EEPROM Clock. This pin provides the clock to the EEPROM. The frequency of this pin is determined by the EECLKFREQ register, and can vary from 2 MHz to 25 MHz. EEPROM Chip Select. Active low chip select. EEPROM Read Data. This pin is used to read data from the device. A 47K pull-up resistor is required on this pin. EEPROM Write Data. This pin is used to write data to the device. PR EL IM IN AR Y Signal Clocks, Reset, Misc. (31 pins) (161 Pin FBGA Package) M12 External Arbiter Enable. When low, the internal PCI arbiter services requests from an external PCI device. When high, the PEX 8111 requests the PCI bus from an external arbiter. M13 Bridge Select. When low, the chip acts as a PCI to PCI Express Bridge (reverse bridge). When this bit is high, the chip acts as a PCI Express to PCI Bridge (forward bridge). B12, D11, A12, C10 General Purpose I/O. Each of these bits can be programmed as either an input or output generalpurpose pin. Interrupts can be generated on each of the pins that are programmed as inputs. A1, A2, A13, A14, Not Available. These pins are never used, and should be left open. B1, B2, B13, B14, E5, N1, N2, N13, N14, P1, P2, P13, P14 C3, A10 No Connect. These pins must be left open. H14 PCI Clock Output. This pin is a buffered clock output from the internal 100 MHz reference clock, with the frequency depending on the PCLKO Clock Frequency field of the DEVINIT register. B11 Power OK. When the available power indicated in the Set Slot Power Limit message is greater than or equal to the power requirement indicated in the POWER register, this pin is asserted. It is only valid in Forward Bridge mode. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 21 Pin Descriptions PLX Technology, Inc. Table 2-13. Signal Test Pins (12 pins) (161 Pin FBGA Package) Type Pins I M11 BUNRI I C9 SMC I K3 TCK I M2 TDI I PU P3 O 12mA TS 3.3V M3 I C4 I D10 I D4 I M1 TMS I PU N12 TRST# I PU N11 TDO TEST TMC TMC1 TMC2 22 Test Enable. Connect to ground for normal operation. Test Mode Select. Connect to ground for normal operation. Scan Path Mode Control. Connect to ground for normal operation. Test Clock. This pin is the JTAG test clock. It sequences the TAP controller as well as all of the JTAG registers provided in the PEX 8111. This pin should be left open if JTAG is not used. Test Data Input. This pin is the serial data input to all JTAG instruction and data registers. The state of the TAP (Test Access Port) controller as well as the particular instruction held in the instruction register determines which register is fed by TDI for a specific operation. TDI is sampled into the JTAG registers on the rising edge of TCK. This pin should be left open if JTAG is not used. Test Data Output. This pin is the serial data output for all JTAG instruction and data registers. The state of the TAP controller as well as the particular instruction held in the instruction register determines which register feeds TDO for a specific operation. Only one register (instruction or data) is allowed to be the active connection between TDI and TDO for any given operation. TDO changes state on the falling edge of TCK and is only active during the shifting of data through the device. This pin is three-stated at all other times. This pin should be left open if JTAG is not used. Test Mode Select. Connect to ground for normal operation. Test Mode Control. Connect to ground for normal operation. IDDQ Test Control Input. Connect to ground for normal operation. I/O Buffer Control. Connect to ground for normal operation. Test Mode Select. This pin is the mode input signal to the TAP Controller. The TAP controller is a 16-state FSM that provides the control logic for JTAG. The state of TMS at the rising edge of TCK determines the sequence of states for the TAP controller. This pin should be left open if JTAG is not used. Test Reset. This pin resets the JTAG TAP controller when driven to ground. This pin should be left open if JTAG is not used. PR EL IM IN AR Y BTON Description PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 2.3.1 Pin Tables (161 Pin FBGA Package) Pin Tables (161 Pin FBGA Package) Table 2-14. Grid A1 A2 Grid Order (161 Pin FBGA Package) Signal Grid C14 NA Signal VDD1.5 Grid H2 Signal AD12 Grid M5 Signal TRDY# D1 AD1 H3 AD11 M6 GND A3 EEWRDATA D2 AD0 H4 VDDQ M7 AD19 A4 GND D3 AD2 H11 REQ3# M8 AD20 A5 VSS_T D4 TMC1 H12 REQ2# M9 CBE3# A6 PETp0 D5 GND H13 VDD5 M10 AD27 A7 REFCLK- D6 VDD_T H14 PCLKO M11 BTON A8 PERp0 D7 VSS_P0 J1 AD13 M12 EXTARB A9 VSS_R D8 VSS_P1 J2 GND M13 FORWARD A10 NC3 M14 PMEOUT# A11 WAKEOUT# D10 TMC J4 PAR N1 A12 GPIO1 D11 GPIO2 J11 AD30 N2 D12 GND J12 VDDQ N3 VDD3.3 D13 M66EN J13 GNT1# N4 STOP# A14 B1 NA B2 VSS_C J3 AD14 PR EL IM IN AR Y A13 D9 NA D14 WAKEIN# J14 GNT0# N5 VDDQ E1 AD3 K1 CBE1# N6 AD17 B3 EERDDATA E2 AD5 K2 AD15 N7 VDD1.5 B4 VDD3.3 E3 AD4 K3 SMC N8 AD22 B5 PETn0 E4 GND K4 N9 GND B6 VDD_P E5 NA K11 N10 IDSEL B7 REFCLK+ E11 GND K12 AD29 N11 TRST# TMS GND B8 VSS_RE E12 PCLKI K13 REQ1# N12 B9 PERn0 E13 INTD# K14 REQ0# N13 B10 VDD1.5 E14 INTC# L1 SERR# N14 B11 PWR_OK F1 AD6 L2 PERR# P1 B12 GPIO3 F2 AD7 L3 VDD1.5 P2 F3 AD8 L4 GND P3 TDI F4 VDDQ L5 FRAME# P4 LOCK# VDD1.5 F11 GND L6 AD18 P5 IRDY# C2 EECLK F12 GNT3# L7 VDD5 P6 CBE2# C3 NC1 F13 INTB# L8 VDDQ P7 AD16 C4 TEST F14 INTA# L9 AD23 P8 AD21 C5 EECS# G1 CBE0# L10 VDD3.3 P9 AD24 C6 AVSS G2 VDD1.5 L11 VDD1.5 P10 AD25 C7 VDD_R G3 VDD5 L12 AD28 P11 AD26 C8 AVDD G4 AD9 L13 AD31 P12 GND C9 BUNRI G11 GNT2# L14 PMEIN# P13 C10 GPIO0 G12 VDDQ M1 TMC2 P14 C11 VDD3.3 G13 VDD1.5 M2 TCK C12 PERST# G14 PCIRST# M3 TDO C13 GND H1 AD10 M4 DEVSEL# B13 B14 C1 NA PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 NA NA 23 Pin Descriptions PLX Technology, Inc. Table 2-15. D2 D1 D3 E1 E3 E2 F1 F2 F3 G4 H1 H3 H2 J1 J3 K2 P7 N6 L6 M7 M8 P8 N8 L9 P9 P10 P11 M10 L12 K12 J11 L13 C8 C6 M11 C9 G1 K1 P6 M9 M4 24 Signal AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 AVDD AVSS BTON BUNRI CBE0# CBE1# CBE2# CBE3# DEVSEL# Grid C2 C5 B3 A3 M12 M13 L5 A4 C13 D5 D12 E4 E11 F11 J2 K4 K11 L4 M6 N9 P12 J14 J13 G11 F12 C10 A12 D11 B12 N10 F14 F13 E14 E13 P5 P4 A1 A2 A13 A14 Signal EECLK EECS# EERDDATA EEWRDATA EXTARB FORWARD FRAME# Grid B1 B2 B13 B14 E5 N1 N2 N13 N14 P1 P2 P13 P14 C3 D13 A10 J4 G14 E12 H14 B9 A8 L2 C12 B5 A6 L14 M14 B11 A7 B7 K14 K13 H12 H11 L1 K3 N4 M2 P3 Signal NA PR EL IM IN AR Y Grid Signal Order (161 Pin FBGA Package) GND GNT0# GNT1# GNT2# GNT3# GPIO0 GPIO1 GPIO2 GPIO3 IDSEL INTA# INTB# INTC# INTD# IRDY# LOCK# NA NC1 M66EN NC3 PAR PCIRST# PCLKI PCLKO PERn0 PERp0 PERR# PERST# PETn0 PETp0 PMEIN# PMEOUT# PWR_OK REFCLKREFCLK+ REQ0# REQ1# REQ2# REQ3# SERR# SMC STOP# TCK TDI Grid M3 C4 D10 D4 M1 N12 M5 N11 B6 C7 D6 B10 C1 C14 G2 G13 L3 L11 N7 B4 C11 L10 N3 G3 H13 L7 F4 G12 H4 J12 L8 N5 D9 D7 D8 A9 B8 A5 D14 A11 Signal TDO TEST TMC TMC1 TMC2 TMS TRDY# TRST# VDD_P VDD_R VDD_T VDD1.5 VDD3.3 VDD5 VDDQ VSS_C VSS_P0 VSS_P1 VSS_R VSS_RE VSS_T WAKEIN# WAKEOUT# PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 2.3.2 Physical Pin Assignment (161 Pin FBGA Package) -- Bottom View Physical Pin Assignment (161 Pin FBGA Package) -- Bottom View N M L K J H G F E D C B A NC NC PMEOUT# PMEIN# REQ0# GNT0# PCLKO PCIRST# INTA# INTC# WAKEIN# VDD1.5 NC NC 14 NC NC FORWARD AD31 REQ1# GNT1# VDD5 VDD1.5 INTB# INTD# M66EN GND NC NC 13 GND TMS EXTARB AD28 AD29 VDDQ REQ2# VDDQ GNT3# PCLKI GND PERST# GPIO3 GPIO1 12 AD26 TRST# BTON VDD1.5 GND AD30 REQ3# GNT2# GND GND GPIO2 VDD3.3 PWR_OK WAKEOUT# 11 AD25 IDSEL AD27 VDD3.3 TMC GPIO0 VDD1.5 NC3 10 AD24 GND CBE3# AD23 VSS_C BUNRI PERn0 VSS_R 9 AD21 AD22 AD20 VSS_P1 AVDD VSS_RE PERp0 8 VDD5 VSS_P0 VDD_R REFCLK+ REFCLK- 7 AD18 VDD_T AVSS VDD_P PETp0 6 NC GND EECS# PETn0 VSS_T 5 PR EL IM IN AR Y P VDDQ Bottom View (PEX 8111) AD16 VDD1.5 AD19 CBE2# AD17 GND IRDY# VDDQ TRDY# LOCK# STOP# DEVSEL# TDI VDD3.3 NC NC FRAME# GND GND PAR VDDQ AD9 VDDQ GND TMC1 TEST VDD3.3 GND 4 TDO VDD1.5 SMC AD14 AD11 VDD5 AD8 AD4 AD2 NC1 EERDDATA EEWRDATA 3 NC TCK PERR# AD15 GND AD12 VDD1.5 AD7 AD5 AD0 EECLK NC NC 2 NC TMC2 SERR# CBE1# AD13 AD10 CBE0# AD6 AD3 AD1 VDD1.5 NC NC 1 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 25 PLX Technology, Inc. PR EL IM IN AR Y Pin Descriptions 26 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 Chapter 3 3.1 Reset Summary Forward Bridge Mode Table 3-1 shows which device resources are reset when each of the forward bridge reset sources are asserted. Table 3-1. Device Resources Forward Bridge Reset PCI Express Interface Logic PCI Interface Logic PCI RST# Pin Configuration Registers PCI Express PERST# pin X X X X PCI Express Link Down X X X PCI Express Hot Reset Secondary Bus Reset bit X D3 to D0 Power Management Reset 3.2 X X X X X X X X X PR EL IM IN AR Y Reset Sources X Reverse Bridge Mode Table 3-2 shows which device resources are reset when each of the reverse bridge reset sources are asserted. Table 3-2. Reverse Bridge Reset Device Resources Reset Sources PCI RST# pin PCI Express Interface Logic PCI Interface Logic PCI PERST# Pin PCI Express Hot Reset Configuration Registers X X X X X Secondary Bus Reset bit X D3 to D0 Power Management Reset X 3.3 X X X X Initialization Summary Various initialization sequences of the PEX 8111 are described below: * No EEPROM, blank EEPROM, or invalid EEPROM - If the EERDDATA pin is always high, then an invalid EEPROM is detected. In this case, the default PCI product ID (8111h) is selected. A 47K pull-up resistor ensures that EERDDATA is high if no EEPROM is installed. - Enable the PCI Express and PCI interfaces using default register values. * Valid EEPROM with configuration register data. - Enable the PCI Express and PCI interfaces using register values loaded from the EEPROM. The interface enable bits in the DEVINIT register should be the last ones set by the EEPROM. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 27 PLX Technology, Inc. PR EL IM IN AR Y Reset Summary 28 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 Chapter 4 4.1 EEPROM Controller Overview The PEX 8111 provides an interface to SPI (Serial Peripheral Interface) compatible serial EEPROMs. This interface consists of a chip select, clock, write data, and read data pins, and operates at up to 25 MHz. Some 128 byte EEPROMs compatible with this interface are the Atmel AT25010A, Catalyst CAT25C01, or ST Microelectronics M95010W. The PEX 8111 supports up to a 16 MB EEPROM, utilizing 1, 2, or 3 byte addressing. The appropriate addressing mode is determined automatically by the PEX 8111. 4.2 EEPROM Data Format PR EL IM IN AR Y The data in the EEPROM is stored in the following format. Table 4-1. Location EEPROM Data Value 5A See Table 4-2 REG BYTE COUNT (LSB) REG BYTE COUNT (MSB) REGADDR (LSB) Description Validation Signature EEPROM Format Byte Configuration register byte count (LSB) Configuration register byte count (MSB) REGADDR (MSB) 1st Configuration Register Address (MSB) REGDATA (Byte 0) 1st Configuration Register Data (Byte 0) REGDATA (Byte 1) 1st Configuration Register Data (Byte 1) REGDATA (Byte 2) 1st Configuration Register Data (Byte 2) REGDATA (Byte 3) 1st Configuration Register Data (Byte 3) REGADDR (LSB) 2nd Configuration Register Address (LSB) REGADDR (MSB) 2nd Configuration Register Address (MSB) 12 REGDATA (Byte 0) 2nd Configuration Register Data (Byte 0) 13 REGDATA (Byte 1) 2nd Configuration Register Data (Byte 1) 14 REGDATA (Byte 2) 2nd Configuration Register Data (Byte 2) 15 REGDATA (Byte 3) 2nd Configuration Register Data (Byte 3) ...... REG BYTE COUNT + 4 REG BYTE COUNT + 5 REG BYTE COUNT + 6 MEM BYTE COUNT (LSB) MEM BYTE COUNT (MSB) SHARED MEM (byte 0) Shared memory byte count (LSB) Shared memory byte count (MSB) REG BYTE COUNT + 7 SHARED MEM (byte 1) 2nd byte of shared memory ...... FFFF SHARED MEM (byte n) Last byte of shared memory 0 1 2 3 4 5 6 7 8 9 10 11 1st Configuration Register Address (LSB) 1st byte Shared memory PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 29 EEPROM Controller PLX Technology, Inc. The EEPROM Format Byte is organized as follows. Table 4-2. 1 7:2 4.3 Description Configuration Register Load. When set, configuration registers are loaded from the EEPROM. The address of the first configuration register is located at bytes 3 and 4 in the EEPROM. If this bit is clear but REG BYTE COUNT is non-zero, the configuration data is read from the EEPROM and discarded. Shared Memory Load. When set, the shared memory is loaded from the EEPROM starting at location REG BYTE COUNT + 6. The number of bytes to load is determined by the value in EEPROM locations REG BYTE COUNT + 4 and REG BYTE COUNT + 5. Reserved PR EL IM IN AR Y Bits 0 EEPROM Format Byte Initialization After the device reset is de-asserted, the EEPROM internal status register is read to determine whether an EEPROM is installed. A pull-up resistor on the EERDDATA pin produces a value of 0xFF if there is no EEPROM installed. If an EEPROM is detected, the first byte is read. If a value of 'h5A is read, it is assumed that the EEPROM is programmed for the PEX 8111. If the first byte is not 'h5A, then the EEPROM is blank, or programmed with invalid data. In this case, the PCI Express and PCI interfaces are enabled for a default enumeration. If the EEPROM has valid data, then the second byte (EEPROM Format Byte) is read to determine which sections of the EEPROM should be loaded into the PEX 8111 configuration registers and memory. Bytes 2 and 3 determine how many EEPROM locations contain configuration register addresses and data. Each configuration register entry consists of two bytes of register address (bit 12 low selects the PCI configuration registers, and bit 12 high selects the memory-mapped configuration registers) and four bytes of register write data. If bit 1 of the EEPROM Format Byte is set, locations REG BYTE COUNT + 4 and REG BYTE COUNT + 5 are read to determine how many bytes to transfer from the EEPROM into the shared memory. The REG BYTE COUNT must be a multiple of 6 and MEM BYTE COUNT must be a multiple of 4. The EECLK pin frequency is determined by the EE Clock Frequency field of the EECLKFREQ register. The default clock frequency is 2 MHz. At this clock rate, it takes about 24 s per DWORD during configuration register or shared memory initialization. For faster loading of large EEPROMs that support a faster clock, the first configuration register load from the EEPROM could be to the EECLKFREQ register. Note: 30 If operating in Reverse Bridge mode, be sure to have the EEPROM set the PCI Enable bit in the DEVINIT register. If operating in Forward Bridge mode, be sure to have the EEPROM set the PCI Express Enable bit in the DEVINIT register. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 4.4 EEPROM Random Read/Write Access EEPROM Random Read/Write Access Either a PCI Express or PCI bus master can use the EECTL register to access the EEPROM. This register contains 8-bit read and write data fields, read and write start signals, and related status bits. The following "C" routines demonstrate the firmware protocol required to access the EEPROM through the EECTL register. An interrupt can be generated whenever the EEPROM BUSY bit of the EECTL register goes from true to false. 4.4.1 EEPROM Opcodes READ_STATUS_EE_OPCODE = 5 WREN_EE_OPCODE = 6 WRITE_EE_OPCODE = 2 READ_EE_OPCODE = 3 EEPROM Low-Level Access Routines PR EL IM IN AR Y 4.4.2 int EE_WaitIdle() { int eeCtl, ii; for (ii = 0; ii < 100; ii++) { PEX 8111Read(EECTL, eeCtl); /* read current value in EECTL */ if ((eeCtl & (1 << EEPROM_BUSY)) == 0) /* loop until idle */ return(eeCtl); } PANIC("EEPROM Busy timeout!\n"); } void EE_Off() { EE_WaitIdle(); /* make sure EEPROM is idle */ PEX 8111Write(EECTL, 0);/* turn off everything (especially EEPROM_CS_ENABLE)*/ } int EE_ReadByte() { int eeCtl = EE_WaitIdle(); /* make sure EEPROM is idle */ eeCtl |= (1 << EEPROM_CS_ENABLE) | (1 << EEPROM_BYTE_READ_START); PEX 8111Write(EECTL, eeCtl);/* start reading */ eeCtl = EE_WaitIdle(); /* wait until read is done */ return((eeCtl >> EEPROM_READ_DATA) & 0xff); /* extract read data from EECTL */ } void EE_WriteByte(int val) { int eeCtl = EE_WaitIdle(); /* make sure EEPROM is idle */ eeCtl &= ~(0xff << EEPROM_WRITE_DATA); /* clear current WRITE value */ eeCtl |= (1 << EEPROM_CS_ENABLE) | (1 << EEPROM_BYTE_WRITE_START) | ((val & 0xff) << EEPROM_WRITE_DATA); PEX 8111Write(EECTL, eeCtl); } PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 31 EEPROM Controller 4.4.3 PLX Technology, Inc. EEPROM Read Status Routine ... EE_WriteByte(READ_STATUS_EE_OPCODE); /* read status opcode */ status = EE_ReadByte(); /* get EEPROM status */ EE_Off(); /* turn off EEPROM */ ... 4.4.4 EEPROM Write Data Routine 4.4.5 /* must first write-enable */ /* turn off EEPROM */ /* opcode to write bytes */ /* three-byte addressing EEPROM? */ /* send high byte of address */ /* send next byte of address */ /* send low byte of address */ PR EL IM IN AR Y ... EE_WriteByte(WREN_EE_OPCODE); EE_Off(); EE_WriteByte(WRITE_EE_OPCODE); #ifdef THREE_BYTE_ADDRESS_EEPROM EE_WriteByte(addr >> 16); #endif EE_WriteByte(addr >> 8); EE_WriteByte(addr); for (ii = 0; ii < n; ii++) { EE_WriteByte(buffer[ii]); } EE_Off(); ... /* send data to be written */ /* turn off EEPROM */ EEPROM Read Data Routine ... EE_WriteByte(READ_EE_OPCODE); /* opcode to write bytes */ #ifdef THREE_BYTE_ADDRESS_EEPROM /* three-byte addressing EEPROM? */ EE_WriteByte(addr >> 16); /* send high byte of address */ #endif EE_WriteByte(addr >> 8); /* send next byte of address */ EE_WriteByte(addr); /* send low byte of address */ for (ii = 0; ii < n; ii++) { buffer[ii] = EE_ReadByte(buffer[ii]); /* store read data in buffer */ } EE_Off(); /* turn off EEPROM */ 32 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 Chapter 5 5.1 Address Spaces Introduction The PEX 8111 supports the following address spaces: * * * * * PCI-compatible configuration (00h to FFh; 256 bytes) PCI Express Extended configuration (100h to FFFh) I/O (32-bit) Memory-mapped I/O (32-bit non-prefetchable) Prefetchable memory (64-bit) PR EL IM IN AR Y The first two spaces are used for accessing configuration registers, and is described in chapter on Configuration Transactions. The PCI Express Extended configuration space (100h - FFFh) is only supported in Forward Bridge mode. Table 5-1 lists which bus is primary or secondary for the two bridge modes of the PEX 8111. Table 5-1. Primary and Secondary Bus Definitions for Forward or Reverse Mode Bridge Mode Primary Bus Secondary Bus Forward Bridge PCI Express PCI Reverse Bridge PCI PCI Express The other three address spaces determine which transactions are forwarded from the primary bus to the secondary bus and from the secondary bus to the primary bus. The memory and I/O ranges are defined by a set of base and limit registers in the configuration header. Transactions falling within the ranges defined by the base and limit registers are forwarded from the primary to secondary bus. Transactions falling outside these ranges are forwarded from the secondary bus to the primary bus. The PEX 8111 does not perform any address translation (flat address space) as transactions cross the bridge. 5.2 I/O Space The I/O addressing space determines whether to forward I/O Read or I/O Write transactions across the bridge. PCI Express uses the 32-bit Short Address Format (DWORD-aligned) for I/O transactions. 5.2.1 Enable Bits The response of the bridge to I/O transactions is controlled by the following configuration register bits: * * * * * I/O Space Enable bit in the PCI Command register Bus Master Enable bit in the PCI Command register ISA Enable bit in the Bridge Control register VGA Enable bit in the Bridge Control register VGA 16-bit Decode bit in the Bridge Control register PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 33 Address Spaces PLX Technology, Inc. The I/O Enable bit must be set for any I/O transaction to be forwarded downstream. If this bit is not set, all I/O transactions on the secondary bus are forwarded to the primary bus. If this bit is not set in Forward Bridge mode, all primary interface I/O requests are completed with Unsupported Request status. If this bit is not set in Reverse Bridge mode, all I/O transactions are ignored (no DEVSEL# assertion) on the primary (PCI) bus. The Bus Master Enable bit must be set for any I/O transaction to be forwarded upstream. * If this bit is not set in Forward Bridge mode, all I/O transactions on the secondary (PCI) bus are ignored. * If this bit is not set in Reverse Bridge mode, all I/O requests on the secondary (PCI Express) bus are completed with Unsupported Request status. The ISA Enable and VGA Enable bits are discussed in the ISA and VGA mode sections. 5.2.2 I/O Base and Limit Registers * * * * PR EL IM IN AR Y The following I/O Base and Limit configuration registers are used to determine whether to forward I/O transactions across the bridge. I/O Base (upper 4 bits of 8-bit register correspond to address bits 15:12) I/O Base Upper (16-bit register corresponds to address bits 31:16) I/O Limit (upper 4 bits of 8-bit register correspond to address bits 15:12) I/O Limit Upper (16-bit register correspond to address bits 31:16) The I/O base consists of one 8-bit register and one 16-bit register. The upper four bits of the 8-bit register define bits 15:12 of the I/O base address. The lower four bits of the 8-bit register determine the I/O address capability of this device. The 16 bits of the I/O Base Upper register define bits 31:16 of the I/O base address. The I/O limit consists of one 8-bit register and one 16-bit register. The upper four bits of the 8-bit register define bits 15:12 of the I/O limit. The lower four bits of the 8-bit register determine the I/O address capability of this device, and reflect the value of the same field in the I/O Base register. The 16 bits of the I/O Limit Upper register define bits 31:16 of the I/O limit. Since address bits 11:0 are not included in the address space decoding, the I/O address range has a granularity of 4 KB, and is always aligned to a 4 KB boundary. The maximum I/O range is 4 GB. I/O transactions on the primary bus that fall within the range defined by the base and limit are forwarded downstream to the secondary bus, and I/O transactions on the secondary bus that are within the range are ignored. I/O transactions on the primary bus that do not fall within the range defined by the base and limit are ignored, and I/O transactions on the secondary bus that do not fall within the range are forwarded upstream to the primary bus. Figure 5-1 illustrates I/O forwarding. 34 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 ISA Mode Figure 5-1. I/O Forwarding Downstream Upstream Primary Bus Secondary Bus I/O Limit PR EL IM IN AR Y 4 KB Multiple I/O Base I/O Address Space For 16-bit I/O addressing, if the I/O Base has a value greater than the I/O Limit, then the I/O range is disabled. For 32-bit I/O addressing, if the I/O base specified by the I/O Base and I/O Base Upper registers has a value greater than the I/O limit specified by the I/O Limit and I/O Limit Upper registers, then the I/O range is disabled. In these cases, all I/O transactions are forwarded upstream, and no I/O transactions are forwarded downstream. 5.2.3 ISA Mode The ISA Enable bit in the Bridge Control register supports I/O forwarding in a system that has an ISA bus. The ISA Enable bit only affects I/O addresses that are within the range defined by the I/O base and limits registers, and are in the first 64 KB of the I/O addressing space. If the ISA Enable bit is set, the bridge does not forward downstream any I/O transactions on the primary bus that are in the top 768 bytes of each 1 KB block within the first 64 KB of address space. Only transactions in the bottom 256 bytes of each 1 KB block are forwarded downstream. If the ISA Enable bit is clear, then all addresses within the range defined by the I/O base and limit registers are forwarded downstream. I/O transactions with addresses above 64 KB are forwarded according to the range defined by the I/O base and limit registers. If the ISA Enable bit is set, the bridge forwards upstream any I/O transactions on the secondary bus that are in the top 768 bytes of each 1 KB block within the first 64 KB of address space, even if the address is within the I/O base and limit. All other transactions on the secondary bus are forwarded upstream if they fall outside the range defined by the I/O base and limit registers. If the ISA Enable bit is clear, then all secondary bus I/O addresses outside the range defined by the I/O base and limit registers are forwarded upstream. As with all upstream I/O transactions, the Master Enable bit in the PCI Command register must be set to enable upstream forwarding. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 35 Address Spaces PLX Technology, Inc. Figure 5-2 illustrates I/O forwarding with the ISA Enable bit set. Figure 5-2. I/O Forwarding with the ISA Enable Bit Set Downstream Primary Bus Upstream Secondary Bus 0x900h - 0xBFFh 0x800h - 0x8FFh PR EL IM IN AR Y 0x500h - 0x7FFh 0x400h - 0x4FFh 0x100h - 0x3FFh 0x000h - 0x0FFh ISA I/O Address Space Example 5.2.4 VGA Mode The VGA Enable bit in the Bridge Control register enables VGA register accesses to be forwarded downstream from the primary to secondary bus, independent of the I/O base and limit registers. The VGA 16-bit Decode bit selects between 10-bit and 16-bit VGA I/O address decoding, and is applicable when the VGA Enable bit is set. The following VGA I/O addresses are controlled by the VGA Enable and VGA 16-bit Decode bits: * Address bits 9:0 = 3B0h through 3BBh, and 3C0h through 3DFh (10-bit addressing) * Address bits 15:0 = 3B0h through 3BBh, and 3C0h through 3DFh (16-bit addressing) These ranges only apply to the first 64K of I/O address space. 36 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 5.2.4.1 Memory-Mapped I/O Space VGA Palette Snooping Separate VGA palette snooping is not supported by PCI Express to PCI bridges, but the PEX 8111 supports palette snooping in Reverse Bridge mode. In Forward Bridge mode, the VGA Enable bit determines whether the VGA palette accesses are forwarded from PCI Express to PCI. The VGA Snoop Enable bit is forced to 0 in Forward Bridge mode. The following I/O addresses are used by VGA graphic devices to control the palette: * Address bits 9:0 = 3C6h, 3C8h, and 3C9h The PEX 8111 supports the following three modes of palette snooping: * Ignore VGA palette accesses if there are no graphics agents downstream that need to snoop or respond to VGA palette access cycles (reads or writes). * Positively decode and forward VGA palette writes if there are graphics agents downstream of the PEX 8111 that need to snoop palette writes (reads are ignored). PR EL IM IN AR Y * Positively decode and forward VGA palette reads and writes if there are graphics agents downstream that need to snoop or respond to VGA palette access cycles (reads or writes). The VGA Enable bit in the Bridge Control register and the VGA Snoop Enable bit in the PCI Command register select the bridge response to palette accesses as listed in Table 5-2. Table 5-2. VGA Enable 5.3 Bridge Response to Palette Access 0 VGA Snoop Enable 0 Response to Palette Accesses 0 1 Positively decode palette writes (ignore reads) 1 x Positively decode palette reads and writes Ignore all palette accesses Memory-Mapped I/O Space The memory-mapped I/O addressing space determines whether to forward non-prefetchable memory read or write transactions across the bridge. Devices that have side-effects during reads, such as FIFOs, should be mapped into this space. For PCI to PCI Express reads, prefetching occurs in this space only if the Memory Read Line or Memory Read Multiple commands are issued on the PCI bus. For PCI Express to PCI reads, the number of bytes to read is determined by the Memory Read Request TLP. Transactions that are forwarded using this address space are limited to a 32-bit range. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 37 Address Spaces 5.3.1 PLX Technology, Inc. Enable Bits The response of the bridge to memory-mapped I/O transactions is controlled by the following configuration register bits: * Memory Space Enable bit in the PCI Command register * Bus Master Enable bit in the PCI Command register * VGA Enable bit in the Bridge Control register The Memory Space Enable bit must be set for any memory transaction to be forwarded downstream. If this bit is not set, all memory transactions on the secondary bus are forwarded to the primary bus. * If this bit is not set in Forward Bridge mode, all non-posted memory requests are completed with an Unsupported Request status. Posted write data is discarded. * If this bit is not set in Reverse Bridge mode, all memory transactions are ignored on the primary (PCI) bus. PR EL IM IN AR Y The Bus Master Enable bit must be set for any memory transaction to be forwarded upstream. * If this bit is not set in Forward Bridge mode, all memory transactions on the secondary (PCI) bus are ignored. * If this bit is not set in Reverse Bridge mode, all non-posted memory requests on the secondary (PCI Express) bus are completed with an Unsupported Request status. Posted write data is discarded. The VGA Enable bit is discussed in the section on VGA Mode (6.3.3). 5.3.2 Memory-Mapped I/O Base and Limit Registers The following Memory Base and Limit configuration registers are used to determine whether to forward memory-mapped I/O transactions across the bridge. * Memory Base (bits 15:4 of 16-bit register correspond to address bits 31:20) * Memory Limit (bits 15:4 of 16-bit register correspond to address bits 31:20) Bits 15:4 of the Memory Base register define bits 31:20 of the memory-mapped I/O base address. Bits 15:4 of the Memory Limit register define bits 31:20 of the memory-mapped I/O limit. Bits 3:0 of each register are hardwired to 0. Since address bits 19:0 are not included in the address space decoding, the memory-mapped I/O address range has a granularity of 1 MB, and is always aligned to a 1 MB boundary. The maximum memorymapped I/O range is 4 GB. Memory transactions that fall within the range defined by the base and limit are forwarded downstream from the primary to secondary bus, and memory transactions on the secondary bus that are within the range are ignored. Memory transactions that do not fall within the range defined by the base and limit are ignored on the primary bus and are forwarded upstream from the secondary bus (provided they are not in the address range defined by the set of prefetchable memory address registers or are not forwarded downstream by the VGA mechanism). Figure 5-3 illustrates memory-mapped I/O forwarding. 38 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 VGA Mode Figure 5-3. Memory-Mapped I/O Forwarding Downstream Upstream Primary Bus Secondary Bus Memory Limit PR EL IM IN AR Y 1 MB Multiple Memory Base Memory-Mapped I/O Address Space If the Memory Base is programmed to have a value greater than the Memory Limit, then the Memorymapped I/O range is disabled. In this case, all memory transaction forwarding is determined by the prefetchable base and limit registers and the VGA enable bit. 5.3.3 VGA Mode The VGA Enable bit in the Bridge Control register enables VGA frame buffer accesses to be forwarded downstream from the primary to secondary bus, independent of the memory-mapped I/O base and limit registers. The following VGA memory addresses are controlled by the VGA Enable bit: * 0A0000h - 0BFFFFh PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 39 Address Spaces 5.4 PLX Technology, Inc. Prefetchable Space The prefetchable addressing space determines whether to forward prefetchable memory read or write transactions across the bridge. Devices that do not have side-effects during reads should be mapped into this space. * For PCI to PCI Express reads, prefetching occurs in this space for all memory read commands (MemRd, MemRdLine, MemRdMult).issued on the PCI bus. * For MemRd commands, the Blind Prefetch Enable bit in the DEVSPECCTL register must be set for prefetching to occur. * For PCI Express to PCI reads, the number of bytes to read is determined by the Memory Read Request, so prefetching does not actually occur. 5.4.1 Enable Bits 5.4.2 PR EL IM IN AR Y The prefetchable space responds to the enable bits as described in the earlier section on Enable Bits. Prefetchable Base and Limit Registers The following Prefetchable Memory Base and Limit configuration registers are used to determine whether to forward prefetchable memory transactions across the bridge. * * * * Prefetchable Memory Base (bits 15:4 of 16-bit register correspond to address bits 31:20) Prefetchable Memory Base Upper (32-bit register corresponds to address bits 63:32) Prefetchable Memory Limit (bits 15:4 of 16-bit register correspond to address bits 31:20) Prefetchable Memory Limit Upper (32-bit register corresponds to address bits 63:32) Bits 15:4 of the Prefetchable Memory Base register define bits 31:20 of the prefetchable memory base address. Bits 15:4 of the Prefetchable Memory Limit register define bits 31:20 of the prefetchable memory limit. Bits 3:0 of each register are hardwired to 0. For 64-bit addressing, the Prefetchable Memory Base Upper and Prefetchable Memory Limit Upper registers are also used to define the space. Since address bits 19:0 are not included in the address space decoding, the prefetchable memory address range has a granularity of 1 MB, and is always aligned to a 1 MB boundary. The maximum prefetchable memory range is 4 GB with 32-bit addressing, and 264 with 64-bit addressing. Memory transactions that fall within the range defined by the base and limit are forwarded downstream from the primary to secondary bus, and memory transactions on the secondary bus that are within the range are ignored. Memory transactions that do not fall within the range defined by the base and limit are ignored on the primary bus and are forwarded upstream from the secondary bus (provided they are not in the address range defined by the set of memory-mapped I/O address registers or are not forwarded downstream by the VGA mechanism). Figure 5-4 illustrates both memory-mapped I/O and prefetchable memory forwarding. 40 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 Prefetchable Base and Limit Registers Figure 5-4. Memory-Mapped I/O and Prefetchable Memory Forwarding Downstream Primary Bus Upstream Secondary Bus DAC DAC Prefetchable Memory Limit 1 MB Multiple DAC PR EL IM IN AR Y DAC SAC 4 GB Boundary SAC Prefetchable Memory Base SAC SAC Memory-Mapped I/O Limit SAC 1 MB Multiple SAC Memory-Mapped I/O Base SAC SAC Prefetchable and Memory-Mapped I/O Memory Space SAC = single address cycle DAC = dual address cycle If the Prefetchable Memory Base is programmed to have a value greater than the Prefetchable Memory Limit, then the prefetchable memory range is disabled. In this case, all memory transaction forwarding is determined by the memory-mapped I/O base and limit registers and the VGA Enable bit. All four prefetchable base and limit registers must be considered when disabling the prefetchable range. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 41 Address Spaces 5.4.3 PLX Technology, Inc. 64-Bit Addressing Unlike memory-mapped I/O memory that must be below the 4 GB boundary, prefetchable memory may be located below, above, or span the 4 GB boundary. Memory locations above the 4 GB boundary must be accessed using 64-bit addressing. PCI Express memory transactions that use the Short Address (32bit) format may target the non-prefetchable memory space, or a prefetchable memory window that is below the 4 GB boundary. PCI Express memory transactions that use the Long Address (64-bit) format may target locations anywhere in the 64-bit memory space. PCI memory transactions that use single address cycles may only target locations below the 4 GB boundary. PCI memory transactions that use dual address cycles may target locations anywhere in the 64-bit memory space. The first address phase of a dual-address transaction contains the lower 32-bits of the address, and the second address phase contains the upper 32 bits of the address. If the upper 32 bits of the address are 0, a single-address transaction is always performed. 5.4.3.1 Forward Bridge Mode PR EL IM IN AR Y If both the Prefetchable Memory Base Upper and Prefetchable Memory Limit Upper registers are set to 0, then addresses above 4 GB are not supported. In Forward Bridge mode, if a PCI Express memory transaction is detected with an address above 4 GB, the transaction is completed with Unsupported Request status. All dual-address transactions on the PCI bus are forwarded upstream to the PCI Express bus. If the prefetchable memory is located entirely above the 4 GB boundary, both the Prefetchable Memory Base Upper and Prefetchable Memory Limit Upper registers are both set to non-zero values. If a PCI Express memory transaction is detected with an address below 4 GB, the transaction is completed with Unsupported Request status, and all single-address transactions on the PCI bus are forwarded upstream to the PCI Express bus (unless they fall within the memory-mapped I/O or VGA memory range). A PCI Express memory transaction above 4 GB that falls within the range defined by the Prefetchable Base, Prefetchable Memory Base Upper, Prefetchable Memory Limit, and Prefetchable Memory Limit Upper registers is forwarded downstream and becomes a dual address cycle on the PCI bus. If a dual address cycle is detected on the PCI bus that is outside the range defined by these registers, it is forwarded upstream to the PCI Express bus. If a PCI Express memory transaction above 4 GB does not fall into the range defined by these registers, it is completed with Unsupported Request status. If a PCI dual address cycle falls into the range determined by these registers, it is ignored. If the prefetchable memory spans the 4 GB boundary, the Prefetchable Memory Base Upper is set to 0, and the Prefetchable Memory Limit Upper registers is set to a non-zero value. If a PCI Express memory transaction is detected with an address below 4 GB, and is greater than or equal to the prefetchable memory base address, then the transaction is forwarded downstream. A singleaddress transaction on the PCI bus is forwarded upstream to the PCI Express bus if the address is less than the prefetchable memory base address. If a PCI Express memory transaction above 4 GB is less than or equal to the prefetchable memory limit register, it is forwarded downstream to the PCI bus as a dual-address cycle. If a dual-address cycle on the PCI bus is less than or equal to the Prefetchable Memory Limit register, it is ignored. 42 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 64-Bit Addressing If a PCI Express memory transaction above 4 GB is greater than the Prefetchable Memory Limit register, it is completed with Unsupported Request status. If a dual-address cycle on the PCI bus is greater than the Prefetchable Memory Limit register, it is forwarded upstream to the PCI Express bus. 5.4.3.2 Reverse Bridge Mode If both the Prefetchable Memory Base Upper and Prefetchable Memory Limit Upper registers are set to 0, then addresses above 4 GB are not supported. In Reverse Bridge mode, if a dual address transaction on the PCI is detected, the transaction is ignored. If a PCI Express memory transaction is detected with an address above 4 GB, it is forwarded upstream to the PCI bus as a dual-address cycle. PR EL IM IN AR Y If the prefetchable memory is located entirely above the 4 GB boundary, both the Prefetchable Memory Base Upper and Prefetchable Memory Limit Upper registers are set to non-zero values. The PEX 8111 ignores all single address memory transactions on the PCI bus, and forwards all PCI Express memory transactions with addresses below 4 GB upstream to the PCI bus (unless they fall within the memory-mapped I/O or VGA memory range). A dual address transaction on the PCI bus that falls within the range defined by the Prefetchable Base, Prefetchable Memory Base Upper, Prefetchable Memory Limit, and Prefetchable Memory Limit Upper registers is forwarded downstream to the PCI Express bus. If a PCI Express memory transaction is above the 4 GB boundary and falls outside the range defined by these registers, it is forwarded upstream to the PCI bus as a dual-address cycle. If a dual address transaction on the PCI bus does not fall into the range defined by these registers, it is ignored. If a PCI Express memory transaction above 4 GB falls into the range defined by these registers, it is completed with Unsupported Request status. If the prefetchable memory spans the 4 GB boundary, the Prefetchable Memory Base Upper is set to 0, and the Prefetchable Memory Limit Upper registers is set to a non-zero value. If a PCI single address cycle is greater than or equal to the prefetchable memory base address, then the transaction is forwarded downstream to the PCI Express bus. If a PCI Express memory transaction is detected with an address below 4 GB, and is less than the prefetchable memory base address, then the transaction is forwarded upstream to the PCI bus. If a dualaddress PCI transaction is less than or equal to the prefetchable memory limit register, it is forwarded downstream to the PCI Express bus. If a PCI Express memory transaction above 4 GB is less than or equal to the prefetchable memory limit register, it is completed with Unsupported Request status. If a dual-address PCI transaction is greater than the prefetchable memory limit register, it is ignored. If a PCI Express memory transaction above 4 GB is greater than the prefetchable memory limit register, it is forwarded upstream to the PCI bus as a dual-address cycle. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 43 Address Spaces 5.4.4 PLX Technology, Inc. VGA Mode The VGA Enable bit in the Bridge Control register enables VGA frame buffer accesses to be forwarded downstream from the primary to secondary bus, independent of the prefetchable memory base and limit registers. The following VGA memory address are controlled by the VGA Enable bit: PR EL IM IN AR Y * 0A0000h - 0BFFFFh 44 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 Chapter 6 6.1 Configuration Transactions Introduction Configuration requests are only initiated by the Root Complex in a PCI Express-based system or by the Central Resource Function in a PCI-based system. Every device in a PCI Express or PCI system has a configuration space that is accessed using configuration transactions. * A Type 0 configuration transaction is used to access the internal PEX 8111 configuration registers. * A Type 1 configuration transaction is used to access a device that resides downstream of the PEX 8111. PR EL IM IN AR Y The configuration address is formatted as follows. Table 6-1. 31 24 Bus Number 23 19 Device Number Table 6-2. 31 PCI Express 18 16 Function Number Rsvd Rsvd 8 Extended Register Address 15 11 10 8 2 1 0 Rsvd Rsvd 7 2 Register Number 1 0 0 0 PCI Type 0 (at Target) 10 8 Function Number 24 7 Register Address Function Number 11 Table 6-4. 31 11 PCI Type 0 (at Initiator) Single bit decoding of device number 31 12 Rsvd 16 Table 6-3. 15 7 2 Register Number 1 0 0 0 PCI Type 1 23 Bus Number 16 15 11 Device Number 10 Function Number PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 8 7 Register Number 2 1 0 0 1 45 Configuration Transactions 6.2 PLX Technology, Inc. Type 0 Configuration Transactions The PEX 8111 only responds to Type 0 configuration transactions on its primary bus that address the PEX 8111 configuration space. A Type 0 configuration transaction is used to configure the PEX 8111, and is not forwarded downstream to the secondary bus. The PEX 8111 ignores Type 0 configuration transactions on its secondary bus. Type 0 configuration transactions always result in the transfer of one DWORD. If Configuration Write data is poisoned, the data is discarded and a Non-Fatal Error message is generated, if enabled. 6.3 Type 1 Configuration Transactions PR EL IM IN AR Y Type 1 configuration transactions are used for device configuration in a hierarchical bus system. Bridges and switches are the only types of devices that respond to a Type 1 configuration transaction. Type 1 configuration transactions are used when the transaction is intended for a device residing on a bus other than the one where the Type 1 request is issued. The Bus Number field in a configuration transaction request specifies a unique bus in the hierarchy on which the target of the transaction resides. The bridge compares the specified bus number with two PEX 8111 configuration registers to determine whether to forward a Type 1 configuration transaction across the bridge. The two configuration registers are the Secondary Bus Number and the Subordinate Bus Number. If a Type 1 configuration transaction is received on the primary interface, the following tests are applied, in sequence, to the Bus Number field to determine how the transaction must be handled: * If the Bus Number field is equal to the Secondary Bus Number register value, and the conditions for converting the transaction into a Special Cycle transaction are met, the PEX 8111 forwards the configuration request to the secondary bus as a Special Cycle transaction. If the conditions are not met, the PEX 8111 forwards the configuration request to the secondary bus as a Type 0 configuration transaction. * If the Bus Number field is not equal to the Secondary Bus Number register value but is in the range of the Secondary Bus Number and Subordinate Bus Number (inclusive) registers, the Type 1 configuration request is specifying a bus that is located behind the bridge. In this case, the PEX 8111 forwards the configuration request to the secondary bus as a Type 1 configuration transaction. * If the Bus Number field does not satisfy the above criteria, the Type 1 configuration request is specifying a bus that is not located behind the bridge. In this case, the configuration request is invalid. - If the primary interface is PCI Express, a completion with Unsupported Request status is returned. - If the primary interface is PCI, the configuration request is ignored, resulting in a Master Abort. 6.4 Type 1 to Type 0 Conversion The PEX 8111 performs a Type 1 to Type 0 conversion when the Type 1 transaction is generated on the primary bus and is intended for a device attached directly to the secondary bus. The PEX 8111 must convert the Type 1 configuration transaction to Type 0 so that the device can respond to it. Type 1 to Type 0 conversions are only performed in the downstream direction. The PEX 8111 only generates Type 0 configuration transactions on the secondary interface, never on the primary interface. 46 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 6.4.1 Forward Bridge Mode Forward Bridge Mode The PEX 8111 forwards a Type 1 transaction on the PCI Express bus to a Type 0 transaction on the PCI bus if the following are true: * The Type 1 Bus Number field of the configuration request is equal to the Secondary Bus Number register value. * The conditions for conversion to a Special Cycle transaction are not met. The PEX 8111 then performs the following on the secondary interface: * Set address bits AD[1:0] to 0. * Derive address bits AD[7:2] directly from the Register Address field of the configuration request. * Derive address bits AD[10:8] directly from the Function Number field of the configuration request. PR EL IM IN AR Y * Set address bits AD[15:11] to 0. * Decode the Device Number field and assert a single address bit in the range AD[31:16] during the address phase. * Verify that the Extended Register Address field in the configuration request is zero. If the value is non-zero, the PEX 8111 does not forward the transaction, and treats it as an Unsupported Request on the PCI Express bus, and a received Master Abort on the PCI bus. Type 1 to Type 0 transactions are performed as non-posted transactions. 6.4.2 Reverse Bridge Mode The PEX 8111 forwards a Type 1 transaction on the PCI bus to a Type 0 transaction on the PCI Express bus if the following are true during the PCI address phase: * Address bits AD[1:0] are 01b. * The Type 1 configuration request Bus Number field (AD[23:16]) is equal to the Secondary Bus Number register value. * The bus command on CBE[3:0]# is a Configuration Read or Write. * The Type 1 configuration request Device Number field (AD[15:11]) is zero. If it is non-zero, the transaction is ignored, resulting in a Master Abort. The PEX 8111 then creates a PCI Express configuration request according to the following: * Set the request Type field to Configuration Type 0. * Set the Register Address field [7:2] directly from the Register Address field of the configuration request * Set the Extended Register Address field [11:8] to 0. * Set the Function Number field [18:16] directly from the Function Number field of the configuration request. * Set the Device Number field [23:19] directly from the Device Number field (forced to zero) of the configuration request. * Set the Bus Number field [31:24] directly from the Bus Number field of the configuration request. Type 1 to Type 0 transactions are performed as non-posted (delayed) transactions. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 47 Configuration Transactions 6.5 PLX Technology, Inc. Type 1 to Type 1 Forwarding Type 1 to Type 1 transaction forwarding provides a hierarchical configuration mechanism when two or more levels of bridges are used. When the PEX 8111 detects a Type 1 configuration transaction intended for a PCI bus downstream from the secondary bus, it forwards the transaction unchanged to the secondary bus. In this case, the target of the transaction does not reside on the secondary interface of the PEX 8111, but is located on a bus segment further downstream. Ultimately, this transaction is converted to a Type 0 or Special Cycle transaction by a downstream bridge. 6.5.1 Forward Bridge Mode The PEX 8111 forwards a Type 1 transaction on the PCI Express bus to a Type 1 transaction on the PCI bus if the following are true: PR EL IM IN AR Y * A Type 1 configuration transaction is detected on the PCI Express. * The value specified by the Bus Number field is within the range of bus numbers between the Secondary Bus Number (exclusive) and the Subordinate Bus Number (inclusive). The PEX 8111 then performs the following on the secondary interface: * Generate address bits AD[1:0] as 01b. * Generate PCI Register Number, Function Number, Device Number, and Bus Number directly from the Register Address, Function Number, Device Number, and Bus Number fields, respectively, of the PCI Express Configuration Request. * Generate address bits AD[31:24] as 0. * Verify that the Extended Register Address field in the configuration request is zero. If the value is non-zero, the PEX 8111 does not forward the transaction, and returns a completion with Unsupported Request status on the PCI Express bus, and a received Master Abort on the PCI bus. Type 1 to Type 1 forwarding transactions are performed as non-posted transactions. 6.5.2 Reverse Bridge Mode The PEX 8111 forwards a Type 1 transaction on the PCI bus to a Type 1 transaction on the PCI Express bus if the following are true during the PCI address phase: * Address bits AD[1:0] are 01b. * The value specified by the Bus Number field is within the range of bus numbers between the Secondary Bus Number (exclusive) and the Subordinate Bus Number (inclusive). * The bus command on CBE[3:0]# is a Configuration Read or Write. The PEX 8111 then creates a PCI Express configuration request according to the following: * Set the request Type field to Configuration Type 1. * Set the Register Address field [7:2] directly from the Register Address field of the configuration request. * Set the Extended Register Address field [11:8] to 0. * Set the Function Number field [18:16] directly from the Function Number field of the configuration request. * Set the Device Number field [23:19] directly from the Device Number field of the configuration request. * Set the Bus Number field [31:24] directly from the Bus Number field of the configuration request. Type 1 to Type 1 forwarding transactions are performed as non-posted (delayed) transactions. 48 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 6.6 Type 1 to Special Cycle Forwarding Type 1 to Special Cycle Forwarding The Type 1 configuration mechanism is used to generate Special Cycle transactions in hierarchical systems. Special Cycle transactions are ignored by the PEX 8111 acting as a target, and are not forwarded across the bridge. In Forward Bridge mode, Special Cycle transactions can only be generated in the downstream direction (PCI Express to PCI). In Reverse Bridge mode, Special Cycle transactions are also generated in the downstream direction (PCI to PCI Express). A Type 1 Configuration Write Request on the PCI Express bus is converted to a Special Cycle on the PCI bus when all of the following conditions are met: * The Type 1 configuration request Bus Number field is equal to the Secondary Bus Number register value. The Device Number field is all ones. PR EL IM IN AR Y * * * * The Function Number field is all ones. The Register Address field is all zeroes The Extended Register Address field is all zeros. When the PEX 8111 initiates the transaction on the PCI bus, the bus command is converted from a Configuration Write to a Special Cycle. The address and data fields are forwarded unchanged from the PCI Express to the PCI. Target devices that recognize the Special Cycle ignore the address, and the message is passed in the data word. The transaction is performed as a non-posted transaction, but the PCI target response (always Master Abort in this case) is not returned back to the PCI Express. Once the Master Abort has been detected on the PCI bus, the successful completion TLP is returned to the PCI Express. 6.7 PCI Express Enhanced Configuration Mechanisms The PCI Express Enhanced Configuration Mechanism adds four extra bits to the Register Address field to expand the space to 4096 bytes. The PEX 8111 only forwards configuration transactions if the Extended Register Address bits are all zero. This prevents address aliasing on the PCI bus which does not support Extended Register Addressing. If a configuration transaction targets the PCI bus and has a non-zero value in the Extended Register Address, the PEX 8111 treats the transaction as if it received a Master Abort on the PCI bus. The PEX 8111 then does the following: * Sets the appropriate status bits for the destination bus as if the transaction had actually executed and received a Master Abort. * Generates a PCI Express completion with Unsupported Request status. 6.7.1 Memory-Mapped Indirect In Reverse Bridge mode, the PEX 8111 provides the capability for a PCI host to access all of the downstream PCI Express configuration registers using PCI memory transactions. The 4 KByte region of the memory range defined by the PCIBASE0 register is used for this mechanism. Memory reads and writes to PCIBASE0 offsets 'h2000 to 'h2FFF result in a PCI Express configuration transaction. The address of the transaction is determined by the ECFGADDR register. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 49 Configuration Transactions PLX Technology, Inc. The format of this address register is as follows. Table 6-5. 31 Enhanced Enable 30 Rsvd 29 Address Register Format 27 20 Bus Number 19 15 Device Number 14 12 Function Number 11 0 Rsvd Once the ECFGADDR has been programmed to point to a particular device, the entire 4 KByte configuration space of a PCI Express endpoint can be accessed directly using memory read and write transactions. Only single DWORDs are transferred during Enhanced Configuration transactions. Configuration Retry Mechanism 6.8.1 Forward Bridge Mode PR EL IM IN AR Y 6.8 Bridges are required to return a completion for all configuration requests that traverse the bridge from PCI Express to PCI prior to expiration of the Completion Timeout timer in the Root Complex. This requires that bridges take ownership of all configuration requests forwarded across the bridge. If the configuration request to PCI completes successfully prior to the bridge timer expiration, the bridge returns a completion with Successful Status to PCI Express. If the configuration request to PCI encounters an error condition prior to the bridge timer expiration, the bridge returns an appropriate error completion to PCI Express. If the configuration request to PCI does not complete either successfully or with an error, prior to timer expiration, then the bridge returns a completion with Configuration Retry Status (CRS) to PCI Express. Even after the PEX 8111 has returned a completion with CRS to PCI Express, the PEX 8111 continues to keep the configuration transaction alive on the PCI bus. The PCI Specification states that once a PCI master detects a target retry, it must continue to retry the transaction until at least one DWORD is transferred. The PEX 8111 keeps retrying the transaction until it completes on the PCI bus or until the PCI Express to PCI Retry timer expires. If another PCI Express to PCI configuration transaction is detected while the previous one is being retried, a completion with CRS is returned immediately. When the configuration transaction completes on the PCI bus after the return of a completion with CRS on PCI Express, the PEX 8111 discards the completion information. Bridges that implement this option are also required to implement bit 15 of the Device Control register as the Bridge Configuration Retry Enable bit. If this bit is cleared, the bridge does not return a completion with CRS on behalf of configuration requests forwarded across the bridge. The lack of a completion should result in eventual Completion Timeout at the Root Complex. Bridges, by default, do not return CRS for Configuration Requests to a PCI device behind the bridge. This may result in lengthy completion delays that must be comprehended by the Completion Timeout value in the Root Complex. 50 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 6.8.2 Reverse Bridge Mode Reverse Bridge Mode In Reverse Bridge mode, the PEX 8111 may detect a completion with CRS status from a downstream PCI Express device. The CRS Retry Control field of the DEVSPECCTL register determines the response of the PEX 8111 in Reverse Bridge Mode when a PCI to PCI Express configuration transaction is terminated with a Configuration Request Retry Status. Table 6-6. CRS Retry Control CRS Retry Control Response Retry once after 1 second. If another CRS is received, Target Abort on the PCI bus. 01 Retry 8 times, once per second. If another CRS is received, Target Abort on the PCI bus. 10 Retry once per second until successful completion. 11 Reserved PR EL IM IN AR Y 00 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 51 PLX Technology, Inc. PR EL IM IN AR Y Configuration Transactions 52 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 Chapter 7 7.1 Error Handling (Forward Bridge) Introduction For all errors detected by the bridge, the bridge sets the appropriate error status bit (both legacy PCI error bit(s) and PCI Express error status bit(s)), and optionally generates an error message on PCI Express. Each error condition has a default error severity level, and has a corresponding error message generated on PCI Express. Error message generation on the PCI Express bus is controlled by three control bits: The SERR Enable bit in the PCI Command register. The Fatal Error Reporting Enable bit in the PCI Express Device Control register. The Non-Fatal Error Reporting Enable bit in the PCI Express Device Control register. PR EL IM IN AR Y * * * * The Correctable Error Reporting Enable bit in the PCI Express Device Control register. ERR_FATAL PCI Express messages are enabled for transmission if either the SERR Enable bit or the Fatal Error Reporting Enable bit is set. ERR_NONFATAL Messages are enabled for transmission if either the SERR Enable bit or the Non-Fatal Error Reporting Enable bit is set. ERR_COR Messages are enabled for transmission if the Correctable Error Reporting Enable bit is set. The Fatal Error Detected, Non-Fatal Error Detected, and Correctable Error Detected status bits in the DEVSTAT register are set for the corresponding errors on the PCI Express, regardless of the error reporting enable bits. 7.2 PCI Express Originating Interface (Primary to Secondary) This section describes error support for transactions that cross the bridge if the originating side is the PCI Express interface, and the destination side is the PCI bus. If a Write Request or Read Completion is received with a poisoned TLP, the entire data payload of the PCI Express transaction must be considered as corrupt. Invert the parity for every data when completing the transaction on the PCI bus. Table 7-1 provides the translation a bridge has to perform when it forwards a non-posted PCI Express request (read or write) to the PCI bus, and the request is completed immediately on the PCI bus either normally or with an error condition. Table 7-1. Translation Performed when Bridge Forwards a Non-Posted PCI Express Request Immediate PCI Termination PCI Express Completion Status Data Transfer with parity error (reads) Successful (poisoned TLP) Completion with parity error (non-posted writes) Unsupported Request Master Abort Unsupported Request Target Abort Completer Abort PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 53 Error Handling (Forward Bridge) 7.2.1 PLX Technology, Inc. Received Poisoned TLP When a write request or read completion is received by the PCI Express interface, and the data is poisoned, the following occur: * The Detected Parity Error bit in the PCI Status register is set. * The Master Data Parity Error bit in the PCI Status register is set if the poisoned TLP is a read completion and the Parity Error Response Enable bit in the PCI Command register is set. * An ERR_NONFATAL Message is generated on PCI Express, if the following conditions are met: o The SERR Enable bit in the PCI Command register is set OR o The Non-Fatal Error Reporting Enable bit in the PCI Express Device Control register is set. * The Signaled System Error in the PCI Status register is set if the SERR Enable bit is set. * The parity bit associated with each DWORD of data is inverted. * For a poisoned write request, the Secondary Master Data Parity Error bit in the Secondary 7.2.2 PR EL IM IN AR Y Status register is set if the Secondary Parity Error Response Enable bit in the Bridge Control register is set, and the bridge sees PERR# asserted when the inverted parity is detected by the PCI target device. PCI Uncorrectable Data Errors The following sections describe how errors are handled when forwarding non-poisoned PCI Express transactions to the PCI bus, and an uncorrectable PCI error is detected. 7.2.2.1 Immediate Reads When the PEX 8111 forwards a read request (I/O, Memory, or Configuration) from the PCI Express and detects an uncorrectable data error on the secondary bus while receiving an immediate response from the completer, the following occur: * The Secondary Master Data Parity Error bit in the Secondary Status register is set if the Secondary Parity Error Response Enable bit is set in the Bridge Control register. * The Secondary Detected Parity Error bit in the Secondary Status register is set. * PERR# is asserted on the secondary interface if the Secondary Parity Error Response Enable bit in the Bridge Control register is set. After detecting an uncorrectable data error on the destination bus for an immediate read transaction, the PEX 8111 continues to fetch data until the byte count is satisfied or the target ends the transaction. When the bridge creates the PCI Express completion, it forwards it with Successful Completion and poisons the TLP. 7.2.2.2 Non-Posted Writes When the PEX 8111 detects PERR# asserted on the PCI secondary interface while forwarding a non-poisoned non-posted write transaction from PCI Express, the following occur: * The Secondary Master Data Parity Error bit in the Secondary Status register is set if the Secondary Parity Error Response Enable bit in the Bridge Control register is set. * A PCI Express completion with Unsupported Request status is generated. * An ERR_NONFATAL Message is generated on PCI Express, if the following conditions are met: o The SERR Enable bit in the PCI Command register is set OR o The Non-Fatal Error Reporting Enable bit in the PCI Express Device Control register is set * The Signaled System Error in the PCI Status register is set if the SERR Enable bit is set. 54 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 7.2.2.3 PCI Address Errors Posted Writes When the PEX 8111 detects PERR# asserted on the PCI secondary interface while forwarding a non-poisoned posted write transaction from PCI Express, the following occur: * The Secondary Master Data Parity Error bit in the Secondary Status register is set if the Secondary Parity Error Response Enable bit in the Bridge Control register is set. * An ERR_NONFATAL Message is generated on PCI Express, if the following conditions are met: o The SERR Enable bit in the PCI Command register is set OR o The Non-Fatal Error Reporting Enable bit in the PCI Express Device Control register is set. * The Signaled System Error in the PCI Status register is set if the SERR Enable bit is set. * After the error is detected, the remainder of the data is forwarded. 7.2.3 PCI Address Errors PR EL IM IN AR Y When the PEX 8111 forwards transactions from PCI Express to PCI, PCI address errors are reported by the assertion of the SERR# pin. When the PEX 8111 detects SERR# asserted, the following occur: * The Secondary Received System Error bit in the Secondary Status register is set. * An ERR_FATAL message is generated on PCI Express, if the following conditions are met: o The Secondary SERR Enable bit in the Bridge Control register is set. o The SERR Enable bit in the PCI Command register or the Fatal Error Reporting Enable bit in the PCI Express Device Control register is set. * The Signaled System Error in the PCI Status register is set if the Secondary SERR Enable and SERR Enable bits are set. 7.2.4 PCI Master Abort on Posted Transaction When a posted write transaction forwarded from PCI Express to PCI results in a Master Abort on the PCI bus, the following occur: * The entire transaction is discarded. * The Secondary Received Master Abort bit in the Secondary Status register is set. * An ERR_NONFATAL Message is generated on PCI Express if the following conditions are met: o The Master Abort Mode bit in the Bridge Control register is set. o The SERR Enable bit in the PCI Command register or the Non-Fatal Error Reporting Enable bit in the PCI Express Device Control register is set. * The Signaled System Error in the PCI Status register is set if the Master Abort Mode and SERR Enable bits are set. 7.2.5 PCI Master Abort on Non-Posted Transaction When a non-posted transaction forwarded from PCI Express to PCI results in a Master Abort on the PCI bus, the following occur: * A completion with Unsupported Request status is returned on the PCI Express. * The Secondary Received Master Abort bit in the Secondary Status register is set. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 55 Error Handling (Forward Bridge) 7.2.6 PLX Technology, Inc. PCI Target Abort on Posted Transaction When a transaction forwarded from PCI Express to PCI results in a Target Abort on the PCI bus, the following occur: * The entire transaction is discarded. * The Secondary Received Target Abort bit in the Secondary Status register is set. * An ERR_NONFATAL Message is generated on PCI Express if the following conditions are met: o The SERR Enable bit in the PCI Command register is set OR o The Non-Fatal Error Reporting Enable bit in the PCI Express Device Control register is set. * The Signaled System Error in the PCI Status register is set if the SERR Enable bit is set. 7.2.7 PCI Target Abort on Non-Posted Transaction * * * * PR EL IM IN AR Y When a transaction forwarded from PCI Express to PCI results in a Target Abort on the PCI bus, the following occur: A completion with Completer Abort status is returned on the PCI Express. The Secondary Received Target Abort bit in the Secondary Status register is set. The Signaled Target Abort bit in the PCI Status register is set. An ERR_NONFATAL Message is generated on PCI Express if the following conditions are met: o The SERR Enable bit in the PCI Command register is set OR o The Non-Fatal Error Reporting Enable bit in the PCI Express Device Control register is set. * The Signaled System Error in the PCI Status register is set if the SERR Enable bit is set. 7.2.8 PCI Retry Abort on Posted Transaction When a transaction forwarded from PCI Express to PCI results in the maximum number of PCI retries (selectable in PCICTL register), the following occur: * The remaining data is discarded. * The PCI Express to PCI Retry Interrupt bit in the IRQSTAT register is set. 7.2.9 PCI Retry Abort on Non-Posted Transaction When a transaction forwarded from PCI Express to PCI results in the maximum number of PCI retries (selectable in PCICTL register), the following occur: * A completion with the status of Completer Abort is returned on the PCI Express. * The PCI Express to PCI Retry Interrupt bit in the IRQSTAT register is set. * The Signaled Target Abort bit in the PCI Status register is set. 56 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 7.3 PCI Originating Interface (Secondary to Primary) PCI Originating Interface (Secondary to Primary) This section describes error support for transactions that cross the bridge if the originating side is the PCI bus, and the destination side is the PCI Express. The PEX 8111 supports TLP poisoning as a transmitter to permit proper forwarding of parity errors that occur on the PCI interface. Posted write data received on the PCI interface with bad parity are forwarded to PCI Express as Poisoned TLPs. Table 7-2 provides the error forwarding requirements for Uncorrectable data errors detected by the PEX 8111 when a transaction targets the PCI Express interface. Table 7-2. Error Forwarding Requirements Received PCI Error Forwarded PCI Express Error Write request with poisoned TLP Read Completion with parity error in data phase Read completion with poisoned TLP PR EL IM IN AR Y Write with parity error Configuration or I/O Completion with parity error in data phase Read/Write completion with Completer Abort Status Table 7-3 describes the bridge behavior on a PCI delayed transaction that is forwarded by a bridge to PCI Express as a Memory Read request or an I/O Read/Write request, and the PCI Express interface returns a completion with UR or CA status for the request. Table 7-3. Bridge Behavior on a PCI Delayed Transaction PCI Express Completion Status PCI Immediate Response Master Abort Mode = 1 Master Abort Mode = 0 Unsupported Request (on Memory Read or I/O Read) Target Abort Normal completion, return FFFFFFFFh Unsupported Request (on I/O Write) Target Abort Normal completion Completer Abort Target Abort 7.3.1 Received PCI Errors 7.3.1.1 Uncorrectable Data Error on Non-Posted Write When a non-posted write is addressed such that it crosses the bridge, and the PEX 8111 detects an uncorrectable data error on the PCI interface, the following occur: * The Secondary Detected Parity Error status bit in the Secondary Status register is set. * If the Secondary Parity Error Response Enable bit in the Bridge Control register is set, the transaction is discarded and is not forwarded to PCI Express. The PERR# pin is asserted on the PCI bus. * If the Secondary Parity Error Response Enable bit in the Bridge Control register is not set, the data is forwarded to PCI Express as a poisoned TLP. Also, set the Master Data Parity Error bit in the PCI Status register if the Parity Error Response Enable bit in the PCI Command register is set. The PERR# pin is not asserted on the PCI bus. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 57 Error Handling (Forward Bridge) 7.3.1.2 PLX Technology, Inc. Uncorrectable Data Error on Posted Write When the PEX 8111 detects an uncorrectable data error on the PCI secondary interface for a posted write transaction that crosses the bridge, the following occur: * The PCI PERR# signal is asserted if the Secondary Parity Error Response Enable bit in the Bridge Control register is set. * The Secondary Detected Parity Error status bit in the Secondary Status register is set. * The posted write transaction is forwarded to PCI Express as a poisoned TLP. * The Master Data Parity Error bit in the PCI Status register is set if the Parity Error Response Enable bit in the PCI Command register is set. 7.3.1.3 Uncorrectable Data Error on PCI Delayed Read Completions When the PEX 8111 forwards a non-poisoned read completion from PCI Express to PCI, and it detects PERR# asserted by the PCI master, the remainder of the completion is forwarded. 7.3.1.4 PR EL IM IN AR Y When the PEX 8111 forwards a poisoned read completion from PCI Express to PCI, the PEX 8111 proceeds with the above mentioned actions when it detects the PERR# pin asserted by the PCI master, but no error message is generated on PCI Express. Uncorrectable Address Error When an uncorrectable address error is detected by the PEX 8111, and parity error detection is enabled via the Secondary Parity Error Response Enable bit in the Bridge Control register, the following occur: * The transaction is terminated with a Target Abort. * The Secondary Detected Parity Error bit in the Secondary Status register is set, independent of the setting of the Secondary Parity Error Response Enable bit in the Bridge Control register. * The Secondary Signaled Target Abort bit in the Secondary Status register is set. * An ERR_FATAL message is generated on PCI Express if the following conditions are met: o The SERR Enable bit in the PCI Command register is set OR o The Fatal Error Reporting Enable bit in the PCI Express Device Control register is set. * The Signaled System Error in the PCI Status register is set if the SERR Enable bit is set. 7.3.2 Unsupported Request (UR) Completion Status The PEX 8111 provides two methods for handling a PCI Express completion received with Unsupported Request (UR) status in response to a request originated by the PCI interface. The response is controlled by the Master Abort Mode bit in the Bridge Control register. In either case, the Received Master Abort bit in the PCI Status register is set. 7.3.2.1 Master Abort Mode Bit Cleared This is the default PCI compatibility mode, and an Unsupported Request is not considered to be an error. When a read transaction initiated on the PCI results in the return of a completion with Unsupported Request status, the PEX 8111 returns FFFFFFFFh to the originating master and terminates the read transaction on the originating interface normally (by asserting TRDY#). When a non-posted write transaction results in a completion with Unsupported Request status, the PEX 8111 completes the write transaction on the originating bus normally (by asserting TRDY#) and discards the write data. 58 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 7.3.2.2 Completer Abort (CA) Completion Status Master Abort Mode Bit Set When the Master Abort Mode bit is set, the PEX 8111 signals a Target Abort to the originating master of an upstream read or non-posted write transaction when the corresponding request on the PCI Express interface results in a completion with UR Status. In addition, the Secondary Signaled Target Abort bit in the Secondary Status register is set. 7.3.3 Completer Abort (CA) Completion Status PR EL IM IN AR Y If the PEX 8111 receives a completion with Completer Abort status on the PCI Express primary interface in response to any forwarded non-posted PCI transaction, the Received Target Abort bit is set in the PCI Status register. A CA response results in a Delayed Transaction Target Abort on the PCI bus. The PEX 8111 provides data to the requesting PCI agent up to the point where data was successfully returned from the PCI Express interface and then signals Target Abort. The Secondary Signaled Target Abort status bit in the Secondary Status register is set when signaling Target Abort to a PCI agent. 7.4 Timeout Errors 7.4.1 PCI Express Completion Timeout Errors The PCI Express Completion Timeout Mechanism allows requesters to abort a non-posted request if a completion does not arrive within a reasonable time. Bridges, when acting as initiators on PCI Express on behalf of internally-generated requests or when forwarding requests from a secondary interface, behave as endpoints for requests that they take ownership of. If a completion timeout is detected and the link is up, the PEX 8111 responds as if a completion with Unsupported Request status has been received. The following action is taken: * An ERR_NONFATAL Message is generated on PCI Express if the following conditions are met: o The SERR Enable bit in the PCI Command register is set OR o The Non-Fatal Error Reporting Enable bit in the PCI Express Device Control register is set. * The Signaled System Error in the PCI Status register is set if the SERR Enable bit is set. If the link is down, the P2PE_RETRY_COUNT field in the PCICTL register determines how many PCI retries occur before a Master Abort is returned to the PCI bus. 7.4.2 PCI Delayed Transaction Timeout Errors The PEX 8111 has Delayed Transaction Timers for each queued delayed transaction. If a delayed transaction timeout is detected, the following occur: * An ERR_NONFATAL Message is generated on PCI Express if the following conditions are met: o The Discard Timer SERR# Enable bit in the Bridge Control register is set. o The SERR Enable bit in the PCI Command register or the Non-Fatal Error Reporting Enable bit in the PCI Express Device Control register is set. * The Signaled System Error in the PCI Status register is set if the SERR Enable bit is set. * The Discard Timer Status in the Bridge Control register is set. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 59 Error Handling (Forward Bridge) 7.5 PLX Technology, Inc. Other Errors PCI devices can assert SERR# when detecting errors that compromise system integrity. When the PEX 8111 detects SERR# asserted on the secondary PCI bus, the following occur: * The Secondary Received System Error bit in the Secondary Status register is set. * An ERR_FATAL message is generated on PCI Express, if the following conditions are met: o The Secondary SERR Enable bit in the Bridge Control register is set. o The SERR Enable bit in the PCI Command register or the Fatal Error Reporting Enable bit in the PCI Express Device Control register is set. * The Signaled System Error in the PCI Status register is set if the Secondary SERR Enable and PR EL IM IN AR Y SERR Enable bits are set. 60 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 Chapter 8 8.1 Error Handling (Reverse Bridge) Introduction For all errors detected by the bridge, the bridge sets the appropriate error status bit (both legacy PCI error bit(s) and PCI Express error status bit(s)). No PCI Express error messages are generated in Reverse Bridge mode. 8.2 PCI Express Originating Interface (Secondary to Primary) PR EL IM IN AR Y This section describes error support for transactions that cross the bridge if the originating side is the PCI Express (secondary) interface, and the destination side is the PCI (primary) interface. If a Write Request or Read Completion is received with a poisoned TLP, the entire data payload of the PCI Express transaction is considered corrupt. The PEX 8111 inverts the parity for every data when completing the transaction on the PCI bus. Table 8-1 provides the translation the PEX 8111 performs when it forwards a non-posted PCI Express request (read or write) to the PCI bus, and the request is completed immediately on the PCI bus either normally or with an error condition. Table 8-1. PEX 8111 Translation - Non-Posted PCI Request Immediate PCI Termination 8.2.1 PCI Express Completion Status Data Transfer with parity error (reads) Successful (poisoned TLP) Completion with parity error (non-posted writes) Unsupported Request Master Abort Unsupported Request Target Abort Completer Abort Received Poisoned TLP When a write request or read completion is received by the PCI Express interface, and the data is poisoned, the following occur: * The Secondary Detected Parity Error bit is set in the Secondary Status register. * The Secondary Master Data Parity Error bit is set in the Secondary Status register if the poisoned TLP is a read completion and the Secondary Parity Error Response Enable bit in the Bridge Control register is set. * The parity bit associated with each DWORD of data is inverted. * For a poisoned write request, the Master Data Parity Error bit in the PCI Status register is set if the Parity Error Response Enable bit in the PCI Command register is set, and the bridge sees PERR# asserted when the inverted parity is detected by the PCI target device. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 61 Error Handling (Reverse Bridge) 8.2.2 PLX Technology, Inc. PCI Uncorrectable Data Errors The following sections describe how errors are handled when forwarding non-poisoned PCI Express transactions to the PCI bus, and an uncorrectable PCI error is detected. 8.2.2.1 Immediate Reads When the PEX 8111 forwards a read request (I/O or Memory) from the PCI Express secondary interface and detects an uncorrectable data error on the PCI primary bus while receiving an immediate response from the completer, the following occur: * The Master Data Parity Error bit in the PCI Status register is set if the Parity Error Response Enable bit is set in the PCI Command register. * The Detected Parity Error bit in the PCI Status register is set. * PERR# is asserted on the PCI interface if the Parity Error Response Enable bit in the PCI Command register is set. PR EL IM IN AR Y After detecting an uncorrectable data error on the destination bus for an immediate read transaction, the PEX 8111 continues to fetch data until the byte count is satisfied or the target ends the transaction. When the bridge creates the PCI Express completion, it forwards it with Successful Completion status and poisons the TLP. 8.2.2.2 Non-Posted Writes When the PEX 8111 detects PERR# asserted on the PCI primary interface while forwarding a non-poisoned non-posted write transaction from PCI Express, the following occur: * The Master Data Parity Error bit in the PCI Status register is set if the Parity Error Response Enable bit is set in the PCI Command register. * A PCI Express completion with Unsupported Request status is returned. 8.2.2.3 Posted Writes When the PEX 8111 detects PERR# asserted on the PCI primary interface while forwarding a non-poisoned posted write transaction from PCI Express, the following occur: * The Master Data Parity Error bit in the PCI Status register is set if the Parity Error Response Enable bit is set in the PCI Command register. * After the error is detected, the remainder of the data is forwarded. 8.2.3 PCI Address Errors When the PEX 8111 forwards transactions from PCI Express to PCI, PCI Address errors are reported by the assertion of the SERR# pin by the PCI target. The PEX 8111 ignores the assertion of SERR#, and lets the PCI Central Resource service the error. 8.2.4 PCI Master Abort on Posted Transaction When a transaction forwarded from PCI Express to PCI results in a Master Abort on the PCI bus, the following occur: * The entire transaction is discarded. * The Received Master Abort bit in the PCI Status register is set. 62 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 8.2.5 PCI Master Abort on Non-Posted Transaction PCI Master Abort on Non-Posted Transaction When a non-posted transaction forwarded from PCI Express to PCI results in a Master Abort on the PCI bus, the following occur: * A PCI Express completion with Unsupported Request status is returned. * Set the Received Master Abort bit in the PCI Status register. 8.2.6 PCI Target Abort on Posted Transaction When a posted transaction forwarded from PCI Express to PCI results in a Target Abort on the PCI bus, the following occur: * The entire transaction is discarded. * The Received Target Abort bit in the PCI Status register is set. PCI Target Abort on Non-Posted Transaction PR EL IM IN AR Y 8.2.7 When a non-posted transaction forwarded from PCI Express to PCI results in a Target Abort on the PCI bus, the following occur: * A PCI Express completion with Completer Abort status is returned. * The Received Target Abort bit in the PCI Status register is set. 8.2.8 PCI Retry Abort on Posted Transaction When a posted transaction forwarded from PCI Express to PCI results in a Retry Abort on the PCI bus, the following occur: * The entire transaction is discarded. * The PCI Express to PCI Retry Interrupt bit in the IRQSTAT register is set. 8.2.9 PCI Retry Abort on Non-Posted Transaction When a non-posted transaction forwarded from PCI Express to PCI results in a Retry Abort on the PCI bus, the following occur: * A PCI Express completion with Completer Abort status is returned. * The PCI Express to PCI Retry Interrupt bit in the IRQSTAT register is set. * The Secondary Signaled Target Abort bit in the Secondary Status register is set. 8.3 PCI Originating Interface (Primary to Secondary) This section describes error support for transactions that cross the bridge if the originating side is the PCI bus, and the destination side is the PCI Express. The PEX 8111 supports TLP poisoning as a transmitter to permit proper forwarding of parity errors that occur on the PCI interface. Posted write data received on the PCI interface with bad parity are forwarded to PCI Express as Poisoned TLPs. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 63 Error Handling (Reverse Bridge) PLX Technology, Inc. Table 8-2 provides the error forwarding requirements for Uncorrectable data errors detected by the PEX 8111 when a transaction targets the PCI Express interface. Table 8-2. Error Forwarding Requirements Received PCI Error Forwarded PCI Express Error Write with parity error Write request with poisoned TLP Read Completion with parity error in data phase Read completion with poisoned TLP Configuration or I/O Completion with parity error in data phase Read/Write completion with Completer Abort Status. PR EL IM IN AR Y Table 8-3 describes the bridge behavior on a PCI delayed transaction that is forwarded to PCI Express as a Memory Read request or an I/O Read/Write request, and the PCI Express interface returns a completion with UR or CA status for the request. Table 8-3. Bridge Behavior on a PCI Delayed Transaction PCI Express Completion Status PCI Immediate Response Master Abort Mode = 1 Unsupported Request (on Memory Read or I/O Read) Unsupported Request (on I/O Write) Completer Abort Target Abort Target Abort Master Abort Mode = 0 Normal completion, return FFFFFFFFh Normal completion Target Abort 8.3.1 Received PCI Errors 8.3.1.1 Uncorrectable Data Error on Non-Posted Write When a non-posted write is addressed such that it crosses the bridge, and the PEX 8111 detects an uncorrectable data error on the PCI interface, the following occur: * The Detected Parity Error status bit in the PCI Status register is set. * If the Parity Error Response Enable bit in the PCI Command register is set, the transaction is discarded and is not forwarded to PCI Express. The PCI PERR# signal is asserted. * If the Parity Error Response Enable bit in the PCI Command register is not set, the data is forwarded to PCI Express as a poisoned TLP. The Secondary Master Data Parity Error bit in the Secondary Status register is set if the Secondary Parity Error Response Enable bit in the Bridge Control register is set. The PCI PERR# signal is not asserted. 8.3.1.2 Uncorrectable Data Error on Posted Write When the PEX 8111 detects an uncorrectable data error on the PCI interface for a posted write transaction that crosses the bridge, the following occur: * The PCI PERR# signal is asserted if the Parity Error Response Enable bit in the PCI Command register is set. * The Detected Parity Error status bit in the PCI Status register is set. * The posted write transaction is forwarded to PCI Express as a poisoned TLP. * The Secondary Master Data Parity Error bit in the Secondary Status register is set if the Secondary Parity Error Response Enable bit in the Bridge Control register is set. 64 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 8.3.1.3 Unsupported Request (UR) Completion Status Uncorrectable Data Error on PCI Delayed Read Completions When the PEX 8111 forwards a non-poisoned or poisoned read completion from PCI Express to PCI, and PERR# is asserted by the PCI master, the following occur: * The remainder of the completion is forwarded. * The PCI Central Resource Function services the PERR# assertion. 8.3.1.4 Uncorrectable Address Error When an uncorrectable address error is detected by the PEX 8111 and parity error detection is enabled via the Parity Error Response Enable bit in the PCI Command register, the following occur: * The transaction is terminated with a Target Abort. * The Signaled Target Abort bit in the PCI Status register is set. * The Detected Parity Error bit in the PCI Status register is set, independent of the setting of the Parity Error Response Enable bit in the PCI Command register. 8.3.2 PR EL IM IN AR Y * SERR# is asserted if enabled via the SERR Enable bit in the PCI Command register. * The Signaled System Error bit in the PCI Status register is set if SERR# is asserted. Unsupported Request (UR) Completion Status The PEX 8111 provides two methods for handling a PCI Express completion received with Unsupported Request (UR) status in response to a request originated by the PCI interface. The response is controlled by the Master Abort Mode bit in the Bridge Control register. In either case, the Secondary Received Master Abort bit in the Secondary Status register is set. 8.3.2.1 Master Abort Mode Bit Cleared This is the default PCI compatibility mode, and an Unsupported Request is not considered to be an error. When a read transaction initiated on the PCI results in the return of a completion with UR status, the PEX 8111 returns FFFFFFFFh to the originating master and terminates the read transaction on the originating interface normally (by asserting TRDY#). When a non-posted write transaction results in a completion with UR status, the PEX 8111 completes the write transaction on the originating bus normally (by asserting TRDY#) and discards the write data. 8.3.2.2 Master Abort Mode Bit Set When the Master Abort Mode bit is set, the PEX 8111 signals a Target Abort to the originating master of a downstream read or non-posted write transaction when the corresponding request on the PCI Express interface results in a completion with UR status. Additionally, the Signaled Target Abort bit in the PCI Status register is set. 8.3.3 Completer Abort (CA) Completion Status If the PEX 8111 receives a completion with Completer Abort status on the PCI Express interface in response to any forwarded non-posted PCI transaction, the Secondary Received Target Abort bit in the Secondary Status register is set. A completion with CA status results in a Delayed Transaction Target Abort on the PCI bus. The PEX 8111 provides data to the requesting PCI agent up to the point where data was successfully returned from the PCI Express interface and then signals Target Abort. The Signaled Target Abort status bit in the PCI Status register is set when signaling Target Abort to a PCI agent. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 65 Error Handling (Reverse Bridge) PLX Technology, Inc. 8.4 Timeout Errors 8.4.1 PCI Express Completion Timeout Errors The PCI Express Completion Timeout Mechanism allows requesters to abort a non-posted request if a completion does not arrive within a reasonable time. Bridges, when acting as initiators on PCI Express on behalf of internally-generated requests and requests forwarded from a secondary interface, behave as endpoints for requests that they take ownership of. If a completion timeout is detected and the link is up, the PEX 8111 responds as if an unsupported request completion has been received. If the link is down, the P2PE_RETRY_COUNT field in the PCICTL register determines how many PCI retries occur before a Master Abort is returned to the PCI bus. 8.4.2 PCI Delayed Transaction Timeout Errors PR EL IM IN AR Y The PEX 8111 has Delayed Transaction Timers for each queued delayed transaction. If a delayed transaction timeout is detected, the following occur: * The Discard Timer Status bit in the Bridge Control Register is set. * The delayed request is removed from the Non-Posted Transaction Queue. * SERR# is asserted if the SERR Enable bit in the PCI Command register is set. 8.5 Other Errors PCI devices can assert SERR# when detecting errors that compromise system integrity. The PEX 8111 never monitors the SERR# pin in Reverse Bridge mode, but instead lets the PCI Central Resource Function service the SERR# interrupt. 8.6 PCI Express Error Messages When the PEX 8111 detects an ERR_FATAL, ERR_NONFATAL, or ERR_COR error, or receives an ERR_FATAL, ERR_NONFATAL, or ERR_COR message, the PCI SERR# signal is asserted if the corresponding reporting enable bit in the ROOTCTL register is set. When an ERR_FATAL or ERR_NONFATAL message is received, the Secondary Received System Error bit in the Secondary Status register is set, independent of the reporting enable bits in the ROOTCTL register. If an Unsupported Request is received by the PEX 8111, an interrupt status bit is set in the IRQSTAT register. This status bit can be enabled to generate an INTx# or MSI interrupt. 66 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 Chapter 9 9.1 Exclusive (Locked) Access (Forward Bridge) Exclusive Accesses The exclusive access mechanism allows non-exclusive accesses to proceed in the face of exclusive accesses. This allows a master to hold a hardware lock across several accesses without interfering with non-exclusive data transfers. Masters and targets not involved in the exclusive accesses are allowed to proceed with non-exclusive accesses while another master retains a bus lock. Exclusive access support in the PEX 8111 is enabled by the Lock Enable bit in the PCICTL register. If this bit is clear, PCI Express Memory Read Locked requests are terminated with a completion with UR status. Lock Sequence across PEX 8111 PR EL IM IN AR Y 9.2 Locked transaction sequences are generated by the Host CPU as one or more reads followed by a number of writes to the same locations. In Forward Bridge mode, the PEX 8111 only supports locked transaction in the downstream direction (PCI Express to PCI). Upstream locked transactions are not allowed. The initiation of a locked transaction sequence through the PEX 8111 is as follows: * A locked transaction begins with a MRdLk Request. * Any successive reads for the locked transaction also use MRdLk Requests. * The completions for any successful MRdLk Request use the CplDLk Completion type, or the CplLk Completion type for unsuccessful Requests. * When the Locked Completion for the first Locked Read Request is returned, the PEX 8111 does not accept new requests from the PCI bus. * All writes for the locked sequence use MWr Requests. * The PEX 8111 remains locked until it is unlocked by the PCI Express. The unlock is then propagated to the PCI bus by terminating the locked sequence. * The PCI Express Unlock Message is used to indicate the end of a locked sequence. Upon receiving an Unlock Message, the PEX 8111 unlocks itself. If the PEX 8111 is not locked, it ignores the unlock message. When the locked read request is queued in the PE2P Non-Posted Transaction Queue, subsequent nonposted non-locked requests from the PCI Express are completed with Unsupported Request status. Any requests that were queued before the locked read request are allowed to complete. 9.3 PCI Master Rules for supporting LOCK# The PEX 8111 must obey the following rules when performing locked sequences on the PCI bus: * A master can access only a single resource during a lock operation. * The first transaction of a lock operation must be a Memory Read transaction. * LOCK# must be asserted during the clock cycle following the address phase and kept asserted to maintain control. * LOCK# must be released if the initial transaction of the lock request is terminated with Retry (Lock was not established). * LOCK# must be released whenever an access is terminated by Target Abort or Master Abort. * LOCK# must be de-asserted between consecutive lock operations for a minimum of one clock cycle while the bus is in the Idle state. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 67 Exclusive (Locked) Access (Forward Bridge) 9.4 PLX Technology, Inc. Acquiring Exclusive Access across PEX 8111 When a PCI Express Locked Memory Read request appears at the output of the non-posted request queue, the locked request is performed on the PCI bus. The PEX 8111 monitors the state of the PCI LOCK# pin when attempting to establish lock. If it is asserted, the PEX 8111 does not request the PCI bus to start the transaction. Once LOCK# is de-asserted and the PCI bus is idle, REQ# is asserted. While waiting for GNT#, the PEX 8111 continues to monitor LOCK#. If LOCK# is ever busy, the PEX 8111 de-asserts REQ# because another agent has gained control of LOCK#. When the PEX 8111 is granted the bus and LOCK# is not asserted, ownership of LOCK# has been obtained. The PEX 8111 is free to perform an exclusive operation when the current transaction completes. LOCK# is de-asserted during the first address phase, and then is asserted one clock cycle later. A locked transaction is not established on the bus until completion of the first data phase of the first transaction (IRDY# and TRDY# asserted). 9.5 PR EL IM IN AR Y If the target terminates the first transaction with Retry, the PEX 8111 terminates the transaction and releases LOCK#. Once the first data phase completes, the PEX 8111 keeps LOCK# asserted until either the lock operation completes or a Master Abort or Target Abort causes an early termination. Non-Posted Transactions and Lock The PEX 8111 must consider itself locked when a locked memory read request is detected on the output of the non-posted request queue, even though no data has transferred. This condition is referred to as a target-lock. While in target-lock, the PEX 8111 does not process any new requests on the PCI Express. The bridge locks the PCI bus when lock sequence on the PCI bus has completed. A target-lock becomes a full-lock when the locked request is completed on the PCI Express. At this point, the PCI Express master has established the lock. 9.6 Continuing Exclusive Access When the PEX 8111 performs another transaction to a locked target, LOCK# is de-asserted during the address phase. The locked target accepts and responds to the request. LOCK# is asserted one clock cycle after the address phase to keep the target in the locked state and allow the PEX 8111 to retain ownership of LOCK# beyond the end of the current transaction. 9.7 Completing Exclusive Access When the PEX 8111 receives an Unlock Message from the PCI Express, it de-asserts LOCK# on the PCI bus. 9.8 Invalid PCI Express Requests while Locked When the PEX 8111 is locked, it only accepts PCI Express MRdLk or MWr transactions that are being forwarded to the PCI bus. Any other type of transaction is terminated with a completion with Unsupported Request status, including non-posted accesses to internal configuration registers and shared memory. 9.9 Locked Transaction Originating on PCI Bus Locked transactions originating on the secondary bus are not allowed to propagate to the primary bus. If a locked transaction is performed on the PCI bus and is intended for the PEX 8111, the PEX 8111 ignores the transaction. 68 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 PCI Bus Errors while Locked 9.10 PCI Bus Errors while Locked 9.10.1 PCI Master Abort during Non-Posted Transaction If a PCI Master Abort occurs during a PCI Express to PCI locked read transaction, the PEX 8111 de-asserts LOCK#, thus releasing the PCI bus from the locked state. Also, the PCI Express bus is released from the locked state, even though no Unlock Message has been received. A CplLk with Unsupported Request status is returned to the PCI Express bus. Refer to Section 7.2.5 "PCI Master Abort on Non-Posted Transaction," for additional details describing the action taken if a Master Abort is detected during a non-posted transaction. 9.10.2 PCI Master Abort during Posted Transaction PR EL IM IN AR Y If a PCI Master Abort occurs during a PCI Express to PCI locked write transaction, the PEX 8111 de-asserts LOCK#, thus releasing the PCI bus from the locked state. Also, the PCI Express bus is released from the locked state, even though no Unlock Message has been received. The write data is discarded. See section PCI Master Abort during Posted Transaction for additional details describing the action taken if a Master Abort is detected during a posted transaction. 9.10.3 PCI Target Abort during Non-Posted Transaction If a PCI Target Abort occurs during a PCI Express to PCI locked read transaction, the PEX 8111 de-asserts LOCK#, thus releasing the PCI bus from the locked state. Also, the PCI Express bus is released from the locked state, even though no Unlock Message has been received. A CplLk with Completer Abort status is returned to the PCI Express bus. See section PCI Target Abort during Non- Posted Transaction for additional details describing the action taken if a Target Abort is detected during a non-posted transaction. 9.10.4 PCI Target Abort during Posted Transaction If a PCI Target Abort occurs during a PCI Express to PCI locked write transaction, the PEX 8111 de-asserts LOCK#, thus releasing the PCI bus from the locked state. Also, the PCI Express bus is released from the locked state, even though no Unlock Message has been received. The write data is discarded. See section PCI Master Abort on Posted Transaction for additional details describing the action taken if a Target Abort is detected during a posted transaction. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 69 PLX Technology, Inc. PR EL IM IN AR Y Exclusive (Locked) Access (Forward Bridge) 70 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 Chapter 10 10.1 Exclusive (Locked) Access (Reverse Bridge) Exclusive Accesses A reverse bridge is allowed to pass locked transactions from the primary interface (PCI) to the secondary interface (PCI Express). If a locked request (LOCK# asserted) is initiated on the PCI bus, then a Memory Read Locked Request is issued to the PCI Express bus. All subsequent locked read transactions targeting the PEX 8111 use the Memory Read Locked Request on the PCI Express bus. All subsequent locked write transactions use the Memory Write Request on the PCI Express bus. The PEX 8111 must send the Unlock message when PCI Lock sequence is complete. 10.2 PR EL IM IN AR Y Exclusive access support in the PEX 8111 is enabled by the Lock Enable bit in the PCICTL register. If this bit is clear, the PCI LOCK# pin is ignored, and locked transactions are treated as unlocked transactions. PCI Target Rules for Supporting LOCK# * The PEX 8111, acting as a target of an access, locks itself when LOCK# is de-asserted during the address phase and is asserted during the following clock cycle. * Lock is established when LOCK# is de-asserted during the address phase, asserted during the following clock cycle, and data is transferred during the current transaction. * Once lock is established, the PEX 8111 remains locked until both FRAME# and LOCK# are sampled de-asserted, regardless of how the transaction is terminated. * The PEX 8111 is not allowed to accept any new requests (from either PCI or PCI Express) while it is in a locked condition except from the owner of LOCK#. 10.3 Acquiring Exclusive Access across PEX 8111 A PCI master attempts to forward a locked memory read transaction to the PCI Express bus. The transaction is terminated by the PEX 8111 with a Retry, and the locked request is written to the P2PE Non-Posted Transaction Queue. When this locked request reaches the top of the queue, the locked request is performed on the PCI Express bus as a MRdLk Request. When the PCI Express responds with a locked completion, the locked request is updated with completion status. When the PCI master retries the locked memory read request, the PEX 8111 responds with TRDY#, thus completing the lock sequence. When the PEX 8111 is locked, it only accepts PCI locked transactions that are being forwarded to the PCI Express bus. Other bus transactions are terminated with a Retry, including accesses to internal configuration registers and shared memory. All PCI Express requests are terminated with a completion with Unsupported Request status. 10.4 Completing Exclusive Access When the PEX 8111 detects LOCK# and FRAME# de-asserted, it sends an Unlock message to the PCI Express. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 71 Exclusive (Locked) Access (Reverse Bridge) 10.5 PLX Technology, Inc. PCI Express Locked Read Request If a locked read request is performed on the PCI Express bus, the PEX 8111 responds with a completion with Unsupported Request status. 10.6 Limitations PR EL IM IN AR Y In a system with multiple PCI masters that perform exclusive transactions to the PCI Express bus, the Lock Enable bit in the PCICTL register must be set. 72 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 Chapter 11 11.1 Power Management (Forward Bridge) Link State Power Management PCI Express defines Link power management states, replacing the bus power management states that were defined by the PCI Power Management (PCI-PM) specification. Link states are not visible to PCIPM legacy compatible software, and are either derived from the power management D-states or by Active State power management protocols. 11.1.1 Link Power States The following link power states are supported by the PEX 8111. PR EL IM IN AR Y * L0 - Active state. All PCI Express operations are enabled. * L0s - A low resume latency, energy saving "standby" state * L1 - Higher latency, lower power "standby" state. L1 support is required for PCI-PM compatible power management. L1 is optional for Active State Link power management. All platform provided main power supplies and component reference clocks must remain active at all times in L1. The internal PLLs of the component may be shut off in L1, enabling greater energy savings at a cost of increased exit latency. The L1 state is entered whenever all functions of a downstream component on a given PCI Express Link are either programmed to a D-state other than D0, or if the downstream component requests L1 entry (Active State Link PM) and receives positive acknowledgement for the request. Exit from L1 is initiated by an upstream initiated transaction targeting the downstream component, or by the desire of the downstream component to initiate a transaction heading upstream. Transition from L1 to L0 is typically a few microseconds. TLP and DLLP communication over a Link that is in the L1 state is prohibited. * L2/L3 Ready - Staging point for removal of main power. L2/L3 Ready transition protocol support is required. The L2/L3 Ready state is related to PCI-PM D-state transitions. L2/L3 Ready is the state that a given Link enters into when the platform is preparing to enter its system sleep state. Following the completion of the L2/L3 Ready state transition protocol for that Link, the Link is then ready for either L2 or L3, but not actually in either of those states until main power has been removed. Depending upon the implementation choices of the platform with respect to providing a Vaux supply, after main power has been removed, the Link either settles into L2 (i.e., Vaux is provided), or it settles into a zero power "off" state (see L3). The PEX 8111 does not support L2, so it settles into the L3 state. The L2/L3 Ready state entry transition process must begin as soon as possible following the PME_TO_Ack TLP acknowledgment of a PM_TURN_OFF message. The downstream component initiates L2/L3 Ready entry by injecting a PM_Enter_L23 DLLP onto its transmit Port. TLP and DLLP communication over a Link that is in L2/L3 Ready is prohibited. Exit from L2/L3 Ready back to L0 may only be initiated by an upstream initiated transaction targeting the downstream component in the same manner that an upstream initiated transaction would trigger the transition from L1 back to L0. The case where an upstream initiated exit from L2/L3 Ready would occur corresponds to the scenario where, sometime following the transition of the Link to L2/L3 Ready but before main power is removed, and the platform power manager decides not to enter the system sleep state. A Link transition into the L2/L3 Ready state is one of the final stages involving PCI Express protocol leading up to the platform entering into in a system sleep state wherein main power has been shut off (e.g., ACPI S3 or S4 sleep state). * L2 - Auxiliary powered link deep energy saving state. Not supported by PEX 8111. * L3 - Link off state. Power off state. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 73 Power Management (Forward Bridge) 11.1.2 PLX Technology, Inc. Link State Transitions The following figure highlights the L-state transitions that may occur during the course of Link operation. L0s L0 L2 L3 L2/L3 Ready L1 PR EL IM IN AR Y See note in text The arc noted in the above figure indicates the case where the platform does not provide Vaux, as in the case of the PEX 8111. In this case, the L2/L3 Ready state transition protocol results in a state of readiness for loss of main power, and once removed the Link settles into the L3 state. Link PM Transitions from any L-state to any other L-state pass through the L0 state during the transition process with the exception of the L2/L3 Ready to L2 or L3 transitions. In this case, the Link transitions from L2/ L3 Ready directly to either L2 or L3 when main power to the component is removed. (This follows along with a D-state transition from D3 for the corresponding component.) The following sequence, leading up to entering a system sleep state, illustrates the multi-step Link state transition process: 1. System Software directs all functions of a downstream component to D3hot. 2. The downstream component then initiates the transition of the Link to L1 as required. 3. System Software then causes the Root Complex to broadcast the PME_Turn_Off message in preparation for removing the main power source. 4. This message causes the subject Link to transition back to L0 to send it, and to enable the downstream component to respond with PME_TO_Ack. 5. After the PME_TO_Ack is sent, the downstream component then initiates the L2/L3 Ready transition protocol. In summary: * L0 --> L1 --> L0 --> L2/L3 Ready * The L2/L3 Ready entry sequence is initiated at the completion of the PME_Turn_Off/ PME_TO_Ack protocol handshake. It is also possible to remove power without first placing all devices into D3hot: 1. System Software causes the Root Complex to broadcast the PME_Turn_Off Message in preparation for removing the main power source. 2. The Downstream components respond with PME_TO_Ack. 3. After the PME_TO_Ack is sent, the Downstream component then initiates the L2/L3 Ready transition protocol. In summary: 1. L0 --> L2/L3 Ready 74 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 11.2 Power Management States Power Management States The PEX 8111 provides the configuration registers and support hardware required by the PCI Power Management Specification. The PCICAPPTR register points to the base address of the power management registers (40h in the PEX 8111). The PEX 8111 also supports the PCI Express Active State Link power management protocol as described in the previous section. 11.2.1 Power States The following power states are supported by the PEX 8111, and are selected by the Power State field in the PWRMNGCSR register: * D0uninitialized - Power-on default state. This state is entered when power is initially applied. The Memory Space Enable, I/O Space Enable, and Bus Master Enable bits in the PCICMD register are all clear. PR EL IM IN AR Y * D0active - Fully operational. At lease one of the following PCICMD bits must be set: Memory Space Enable, I/O Space Enable, Bus Master Enable. * D1 - Light sleep. Only PCI Express configuration transactions are accepted. Other types of transactions are terminated with an Unsupported Request. All PCI Express requests generated by the PEX 8111 are disabled except for PME Messages. * D2 - Heavy sleep. Same restrictions as D1. * D3hot - Function context not maintained. Only PCI Express configuration transactions are accepted. Other types of transactions are terminated with an Unsupported Request. All PCI Express requests generated by the PEX 8111 are disabled except for PME Messages. From this state, the next power state can be either D3cold or D0uninitialized. When transitioning from D3hot to D0, the entire chip is reset. * D3cold - Device is powered-off. A power-on sequence transitions a function from the D3cold state to the D0uninitialized state. At this point software must perform a full initialization of the function to re-establish all functional context, completing the restoration of the function to its D0active state. When transitioning from D0 to any other state, the PCI Express link transitions to link state L1. System software must allow a minimum recovery time following a D3hot to D0 transition of at least 10 ms, prior to accessing the function. This recovery time may, for example, be used by the D3hot to D0 transitioning component to bootstrap any of its component interfaces (e.g., from serial ROM) prior to being accessible. Attempts to target the function during the recovery time (including configuration request packets) results in undefined behavior. 11.3 Power Management Signaling PCI devices assert the PME# pin to signal a power management event. The PEX 8111 converts the PME# signal to PCI Express PME Messages. There are no internal events that cause a PME message to be sent upstream. Power Management Messages are used to support Power Management Events signaled by devices downstream of the PEX 8111. System software needs to identify the source of a PCI Power Management Event that is reported by a PM_PME message. When the PME comes from an agent on a PCI bus, then the PM_PME Message Requester ID reports the Bus Number from which the PME was collected, and the Device Number and Function Number reported must both be zero. When the PME message is sent to the host, the PME Status bit in the PWRMNGCSR register is set and a 100 ms timer is started. If the status bit is not cleared within 100 ms, another PME message is sent. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 75 Power Management (Forward Bridge) PLX Technology, Inc. When the upstream device is powering down the downstream devices, it first places all devices into the D3hot state. It then sends a PCI Express PME_Turn_Off message. Once the PEX 8111 has received this message, it does not send any more PME messages upstream. The PEX 8111 then sends a PME_TO_Ack message to the upstream device and puts its link into the L2/L3 Ready state. It is now ready to be powered-down. If the upstream device changes the power state of the PEX 8111 back to D0, PME messages are re-enabled. The PCI Express PME_Turn_Off message terminates at the PEX 8111, and is not communicated to the PCI devices. The PEX 8111 does not issue a PM_PME message on behalf of a downstream PCI device while its upstream Link is in the L2/L3 non-communicating state. To avoid loss of PME# assertions in the conversion of the level-sensitive PME# signal to the edge triggered PCI Express PM_PME message, the PCI PME# signal is polled every 256 ms by the PEX 8111 and a PCI Express PM_PME message is generated if PME# is asserted. 11.3.1 Wakeup PR EL IM IN AR Y If the link is in the L2 state, a device on the secondary PCI bus can signal the root complex to wake up the link. The PEX 8111 asserts the WAKEOUT# pin or sends a PCI Express beacon for the following: * PCI PME# pin is asserted while link is in L2 state * PCI Express beacon is received while link is in L2 state. * PCI Express PM_PME Message is received. A beacon is transmitted if the following are true: * PCI PME# pin is asserted while link is in L2 state * Beacon Generate Enable bit in the DEVSPECCTL register is set. * PME Enable bit in the PWRMNGCSR register is set. 11.4 Set Slot Power When a PCI Express link first comes up, or the Slot Power Limit Value or Slot Power Limit Scale fields in the Root Complex SLOTCAP register are changed, the Root Complex sends a Set Slot Power Message. When the PEX 8111 receives this message, it updates its Captured Slot Power Limit Value and Captured Slot Power Limit Scale fields in the DEVCAP register. When the available power indicated by the Slot Power Limit Value and Captured Slot Power Limit Scale fields in the DEVCAP register is greater than or equal to the power requirement indicated in the POWER register, the PWR_OK pin is asserted 76 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 Chapter 12 12.1 Power Management (Reverse Bridge) Power Management States The PEX 8111 provides the configuration registers and support hardware required by the PCI Power Management Specification. The PCICAPPTR register points to the base address of the power management registers (40h in the PEX 8111). 12.1.1 Power States The following power states are supported by the PEX 8111, and are selected by the Power State field in the PWRMNGCSR register: * D0uninitialized - Power-on default state. This state is entered when power is initially applied. The PR EL IM IN AR Y Memory Space Enable, I/O Space Enable, and Bus Master Enable bits in the PCICMD register are all clear. * D0active - fully operational. At lease one of the following PCICMD bits must be set: Memory Space Enable, I/O Space Enable, Bus Master Enable. * D1 - Light sleep. Only PCI configuration transactions are accepted. No master cycles are allowed, and the INTx# interrupts are disabled. The PMEOUT# pin can be asserted by the PEX 8111. The PCI clock continues to run in this state. * D2 - Heavy sleep. Same as D1, except that the PCI host can stop the PCI clock. * D3hot - Function context not maintained. Only PCI configuration transactions are accepted. From this state, the next power state can be either D3cold or D0uninitialized. When transitioning from D3hot to D0, the entire chip is reset. * D3cold - Device is powered-off. A power-on sequence transitions a function from the D3cold state to the D0uninitialized state. At this point software must perform a full initialization of the function to re-establish all functional context, completing the restoration of the function to its D0active state. An interrupt, indicated by the Power State Change Interrupt bit in the IRQSTAT register, can be generated when the power state is changed. 12.2 Power Down Sequence During a link power-down, the following sequence occurs: * * * * * PCI host puts downstream PCI Express device in power state D3. * * * * * Downstream device responds with a PME_TO_Ack message. Downstream device initiates a transition to link state L1. PCI host puts PEX 8111 in power state D3. PEX 8111 initiates a transition to L0 on the link. PEX 8111 generates a PCI Express PME_Turn_Off message to the PCI Express downstream device. Downstream device sends a DLLP to request transition to L2/L3 Ready state (L2.Idle Link state). PEX 8111 acknowledges the request, completing the transition to the L2.Idle Link State. PME# pin is asserted to the PCI host. PCI host can now remove power from the PEX 8111. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 77 Power Management (Reverse Bridge) 12.3 PLX Technology, Inc. PME# Signal PME messages from the PCI Express interface are translated to the PME# signal on the PCI bus. The PME Status bit in the PWRMNGCSR register is set when a PCI Express PME Message is received, the WAKEIN# pin is asserted, a beacon is detected, or the link transitions to the L2/L3 Ready state. The PME# pin is asserted whenever the PME Status bit is set and PME is enabled. 12.4 Set Slot Power When a PCI Express link first comes up, or the Slot Power Limit Value or Slot Power Limit Scale fields in the PEX 8111 SLOTCAP register are changed, the PEX 8111 sends a Set Slot Power Message to the downstream PCI Express device. PR EL IM IN AR Y When the downstream device receives this message, it updates its Captured Slot Power Limit Value and Captured Slot Power Limit Scale fields in the DEVCAP register. 78 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 Chapter 13 13.1 Interrupts (Forward Bridge) PCI Interrupts In Forward Bridge mode, the PCI INTx# signals are inputs to the PEX 8111. The interrupt is routed to the PCI Express bus using virtual wire interrupt messages. The PCI Express supports the INTx virtual wire interrupt feature for legacy systems that still support the PCI INTx# interrupt signals. PCI INTx# interrupts are "virtualized" in PCI Express using Assert_INTx and Deassert_INTx messages, where x is A, B, C, or D for the respective PCI INTx# interrupt signals defined in PCI Specification 3.0. This message pairing provides a mechanism to preserve the level-sensitive semantics of the PCI interrupts. The Assert_INTx and Deassert_INTx messages transmitted on the PCI Express link capture the asserting/de-asserting edge of the respective PCI INTx# signal. 13.2 PR EL IM IN AR Y The Requester ID used in the PCI Express Assert_INTx and Deassert_INTx messages transmitted by the PEX 8111 (irrespective of whether the source is internal or external to the bridge) equals the bridge primary interface Bus Number and Device Number. The Function Number sub-field is set to zero. Internally Generated Interrupts The following internal events can be programmed to generate an interrupt: * EEPROM transaction done * GPIO bit change * Mailbox register written When one of these interrupts occurs, the interrupt can be produced using one of two methods: 13.2.1 Virtual Wire Interrupts If MSI is disabled, virtual wire interrupts can be used to support internal interrupt events. Internal interrupt sources are masked by the Interrupt Disable bit in the PCI Command register and are routed to one of the virtual interrupts using the PCI Interrupt Pin register. PCI Express Assert_INTx and Deassert_INTx messages are not masked by the Bus Master Enable bit located in the PCI Command register. The internal interrupt is processed the same as the corresponding PCI interrupt signal. 13.2.2 Message Signaled Interrupts The PCI Express bus supports interrupts using Message Signaled Interrupts (MSI). With this mechanism, a device signals an interrupt by writing to a specific memory location. The PEX 8111 uses the 64-bit Message Address version of the MSI capability structure and clears the No Snoop and Relaxed Ordering bits in the Requester Attributes. There are address and data configuration registers associated with the MSI feature (MSIADDR, MSIUPPERADDR, MSIDATA). When an internal interrupt event occurs, the value in the MSI Data configuration register is written to the PCI Express address specified by the MSI Address configuration registers. The MSI feature is enabled by the MSI Enable bit in the MSICTL register. If MSI is enabled, the virtual wire interrupt feature is disabled. MSI interrupts are generated independently of the Interrupt Disable bit in the PCI Command register. MSI interrupts are gated by the Bus Master Enable bit in the PCI Command register. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 79 PLX Technology, Inc. PR EL IM IN AR Y Interrupts (Forward Bridge) 80 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 Chapter 14 14.1 Interrupts (Reverse Bridge) PCI Interrupts In Reverse Bridge mode, the PCI INTx# signals are outputs from the PEX 8111. Each INTx# signal is asserted or de-asserted when the corresponding PCI Express Assert_INTx or Deassert_INTx message is received. The INTx# signals are asserted independently of the Interrupt Disable bit in the PCI Command register. The INTx# signals are only asserted when the PEX 8111 is in power state D0. 14.2 Internally Generated Interrupts The following internal events can be programmed to generate an interrupt: PR EL IM IN AR Y * EEPROM transaction done * GPIO bit change * Mailbox register written When one of these interrupts occurs, the interrupt can be produced using one of two methods: 14.2.1 INTx# Signals When an internal interrupt event occurs, it can cause one of the PCI INTx# signals to be asserted. Internal interrupt sources are masked by the Interrupt Disable bit in the PCI Command register and are routed to one of the INTx# signals using the PCI Interrupt Pin register. The INTx# signals are only asserted when Message Signaled Interrupts are disabled. 14.2.2 Message Signaled Interrupts The PCI bus supports interrupts using Message Signaled Interrupts (MSI). With this mechanism, a device signals an interrupt by writing to a specific memory location. The PEX 8111 uses the 64-bit Message Address version of the MSI capability structure. There are address and data configuration registers associated with the MSI feature (MSIADDR, MSIUPPERADDR, MSIDATA). When an internal interrupt event occurs, the value in the MSI Data configuration register is written to the PCI Express address specified by the MSI Address configuration registers. The MSI feature is enabled by the MSI Enable bit in the MSICTL register. If MSI is enabled, the INTx# interrupt signals for internally generated interrupts are disabled. MSI interrupts are generated independently of the Interrupt Disable bit in the PCI Command register. MSI interrupts are gated by the Bus Master Enable bit in the PCI Command register. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 81 PLX Technology, Inc. PR EL IM IN AR Y Interrupts (Reverse Bridge) 82 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 Chapter 15 15.1 PCI Express Messages (Forward Bridge) Introduction PCI Express defines a set of messages that are used as a method for in-band communication of events (e.g., interrupts), generally replacing the need for sideband signals. These messages may also be used for general purpose messaging. PCI Express to PCI bridge support requirements for these messages are described in the sections below. PCI Express messages are routed either explicitly or implicitly depending on specific bit field encodings in the message request header. An explicitly routed message is routed based either on a specific address or on an ID field contained within the message header. The destination of an implicitly routed message is inferred from the message Type field. INTx# Interrupt Signaling PR EL IM IN AR Y 15.2 INTx# Interrupt Signaling messages are used for in-band communication of the state of the PCI line based interrupts INTA#, INTB#, INTC#, and INTD# for devices downstream of the bridge. Refer to Chapter 13, "Interrupts (Forward Bridge)," for details. 15.3 Power Management Messages Power Management Messages are used to support Power Management Events signaled by sources integrated into the bridge and for devices downstream of the bridge. Refer to Chapter 11, "Power Management (Forward Bridge)," for details. 15.4 Error Signaling Messages Error Signaling Messages are transmitted by the bridge on its PCI Express primary interface to signal an error for a particular transaction, for the link interface, for errors internal to the bridge, or for PCI related errors detected on the secondary interface. The message types include ERR_COR, ERR_NONFATAL, and ERR_FATAL and the relevant mask bits are located in the PCI Express Capability Structure. Refer to Chapter 7, "Error Handling (Forward Bridge)," for details. 15.5 Locked Transactions Support The PCI Express Unlock Message is used to support Locked Transaction sequences in the downstream direction. Refer to Chapter 9, "Exclusive (Locked) Access (Forward Bridge)," for details. 15.6 Slot Power Limit Support The Set_Slot_Power_Limit Message is transmitted to endpoints, including bridges, by the Root Complex or a Switch. The PEX 8111 supports and complies with these messages. These messages are particularly relevant to bridges implemented on add-in cards. Refer to Chapter 11, "Power Management (Forward Bridge)," and Chapter 12, "Power Management (Reverse Bridge)," for details. 15.7 Hot Plug Signaling Messages The PEX 8111 does not support Hot Plug Signaling, and ignores the associated messages. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 83 PLX Technology, Inc. PR EL IM IN AR Y PCI Express Messages (Forward Bridge) 84 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 Chapter 16 16.1 PCI Express Messages (Reverse Bridge) INTx# Interrupt Message Support The PEX 8111 controls the state of the corresponding PCI interrupt pins based on the Assert_INTx and Deassert_INTx messages received. 16.2 Power Management Message Support The PEX 8111 generates a PME_Turn_Off message when placed into power state D3. The PEX 8111 then waits for the PME_TO_Ack message from the downstream device before proceeding with the power-down sequence. PME Handling Requirements PR EL IM IN AR Y 16.2.1 The PEX 8111 translates PME messages from the PCI Express interface to the PME# signal on the PCI bus. The PEX 8111 converts the edge triggered PME events on the PCI Express interface to the level triggered PME# signal on PCI. The PEX 8111 signals PME# on the PCI bus for the following: * PCI Express WAKEIN# signal is asserted while link is in L2 state. * PCI Express beacon is received while link is in L2 state. * PCI Express PM_PME Message is received. For compatibility with existing software, the PEX 8111 does not signal PME# unless the PME signaling is enabled by the PME Enable bit in the PWRMSGCSR register. The PEX 8111 sets its PME Status bit when PME# is signaled and clears PME# when the PME Status bit or the PME Enable bit is cleared. All PME messages received while the PME Enable bit is cleared are ignored and the PME Status bit is not set during this time. 16.3 Error Signaling Message Support The PEX 8111 converts all ERR_COR, ERR_FATAL and ERR_NONFATAL Messages to SERR# on the PCI interface. 16.4 Locked Transaction Support The PEX 8111 is allowed to pass locked transactions from the primary interface to the secondary interface. The PEX 8111 uses the Memory Read Locked request to initiate a locked sequence when a locked request is sent on the PCI bus. All subsequent locked read transactions targeting the bridge use the Memory Read Locked request on PCI Express. All subsequent locked write transactions use the Memory Write request on PCI Express. The PEX 8111 sends the Unlock Message when PCI Lock sequence is complete. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 85 PLX Technology, Inc. PR EL IM IN AR Y PCI Express Messages (Reverse Bridge) 86 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 Chapter 17 17.1 Initialization (Forward Bridge) Introduction The actions that the PEX 8111 takes upon receipt of various reset events and interface initialization requirements are described in the following sections. 17.2 Reset Behavior There are three types of reset that the PEX 8111 receives over the PCI Express primary interface: * Physical layer resets that are platform specific and referred to as "Fundamental Resets" (cold/ warm reset) PR EL IM IN AR Y * PCI Express Physical Layer mechanism (Hot Reset) * PCI Express Data Link transitioning to the Down state of primary interface. These three primary interface reset sources are each described in sections that follow. All primary interface reset events initiate a Secondary Bus Reset which resets the PCI bus. In addition to primary interface reset sources, the PEX 8111 supports a PCI bus reset by way of the Bridge Control Register. When attempting a Configuration access to devices on the PCI bus behind the PEX 8111, the timing parameter Trhfa (225 PCI Clocks) must be respected after reset. 17.2.1 Fundamental Reset (Cold/Warm Reset) The PEX 8111 uses the PCI Express PERST# signal as a fundamental reset input. When the assertion of PERST# follows the power-on event, it is referred to as a cold reset. The PCI Express system may also generate this signal without removing power; this is referred to as a warm reset. The PEX 8111 treats cold and warm resets without distinction. The PEX 8111 state machines are asynchronously reset, and the configuration registers are initialized to their default values when this signal is asserted. The PEX 8111 also tri-states its PCI outputs unless it is configured as the PCI bus parking agent. The PEX 8111 propagates the warm/cold reset from its primary interface to PCI reset on the secondary interface. The PCI RST# signal is asserted while PERST# is asserted. During a cold reset, the PCI RST# is asserted for at least 100 ms after the power levels are valid. During any other types of PCI resets, PCI RST# is asserted for at least 1 ms. 17.2.2 Primary Reset Due to Physical Layer Mechanism (Hot Reset) PCI Express supports the Link Training Control Reset (a training sequence with the reset bit asserted), or hot reset, for propagating reset requests downstream. When the PEX 8111 receives a hot reset on its PCI Express primary interface, it propagates that reset to the PCI RST# signal. In addition, the PEX 8111 discards all transactions being processed and returns all registers, state machines and externally observable state internal logic to the state specified default or initial conditions. Software is responsible for ensuring that the Link Reset assertion and de-assertion messages are timed such that the bridge adheres to proper reset assertion and de-assertion durations on the PCI RST# signal. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 87 Initialization (Forward Bridge) 17.2.3 PLX Technology, Inc. Primary Reset Due to Data Link Down When the PCI Express primary interface of the PEX 8111 is in normal operation and, for whatever reason, the Link goes down, the Transaction and Data Link Layers enter the DL_Down state. The PEX 8111 discards all transactions being processed and returns all registers, state machines and externally observable state internal logic to the state specified default or initial conditions. In addition, the entry of the primary interface of the PEX 8111 into DL_Down status initiates a reset of the PCI bus using the PCI RST# signal. 17.2.4 Secondary Bus Reset by way of Bridge Control Register PR EL IM IN AR Y A reset of the PCI secondary interface may be initiated by software through assertion of the Secondary Bus Reset bit in the Bridge Control Register. This targeted reset may be used for various reasons, including recovery from error conditions on the secondary bus, or to initiate re-enumeration. A write to the Secondary Bus Reset bit forces the assertion of the secondary interface PCI reset (RST#) signal without affecting the primary interface or any configuration space registers. Additionally, the logic associated with the secondary interface is re-initialized and any transaction buffers associated with the secondary interface are cleared. RST# is asserted as long as the Secondary Bus Reset bit is asserted, so software must take care to observe proper PCI reset timing requirements. Software is responsible for ensuring that the PEX 8111 does not receive transactions that require forwarding to the secondary interface while Secondary Bus Reset is asserted. 17.2.5 Bus Parking during Reset The PEX 8111 drives the secondary PCI bus AD[31:0], C/BE[3:0]#, and PAR signals to a logic low level (zero) when the secondary interface RST# is asserted. 88 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 Chapter 18 18.1 Initialization (Reverse Bridge) Reset Behavior A PCI Express hot reset (PCI Express Link Training Sequence) is generated for the following cases: * Secondary Bus Reset bit is set in the Bridge Control register. * Power management state transitions from D3 to D0. Assertion of the PCI RST# pin causes the PCI Express sideband reset signal (PERST#) to be asserted. Secondary Bus Reset by way of Bridge Control Register PR EL IM IN AR Y 18.2 A reset of the PCI Express secondary interface may be initiated by software through assertion of the Secondary Bus Reset bit in the Bridge Control register. This targeted reset may be used for various reasons, including recovery from error conditions on the secondary bus, or to initiate re-enumeration. A write to the Secondary Bus Reset bit causes a PCI Express Link Reset Training Sequence to be transmitted without affecting the primary interface or any configuration space registers. Additionally, the logic associated with the secondary interface is re-initialized and any transaction buffers associated with the secondary interface are cleared. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 89 PLX Technology, Inc. PR EL IM IN AR Y Initialization (Reverse Bridge) 90 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 Chapter 19 19.1 PCI Arbiter Overview A PCI system using the PEX 8111 can either utilize an external bus arbiter, or use the PEX 8111 internal arbiter. This internal arbiter can accept bus requests from up to four external PCI devices. The PCI Express to PCI bridge controller logic can also request control of the PCI bus. 19.2 Internal Arbiter Mode 19.2.1 PR EL IM IN AR Y When the EXTARB pin is de-asserted, the PEX 8111 accepts and arbitrates PCI requests from up to four external devices. The PEX 8111 supports single and multi-level arbiter modes, selected by the PCI Multi-Level Arbiter bit in the PCICTL register. Single-Level Mode The four external requests and the PCI Express to PCI Bridge Controller request are all placed into a single-level arbiter. After a device is granted the bus, it becomes the lowest level requester. All devices have the same priority. For example, if all internal and external agents are requesting the bus, then the order of the agents granted the bus would be: * * * * * * PEX 8111 PCI Initiator External Requester 0 External Requester 1 External Requester 2 External Requester 3 Bridge and so forth. 19.2.2 Multi-Level Mode The four external requests are placed into a two-level round robin arbiter with the PCI Express to PCI Bridge Controller. Level 0 alternates between the PCI Express to PCI Bridge controller and level 1, guaranteeing that the PCI Express to PCI Bridge is granted up to 50% of the accesses. Level 1 consists of the four external PCI requesters. For example, if all internal and external agents are requesting the bus, then the order of the agents that are granted the bus would be: * * * * * * * * PEX 8111 PCI Initiator External Requester 0 PEX 8111 PCI Initiator External Requester 1 PEX 8111 PCI Initiator External Requester 2 PEX 8111 PCI Initiator External Requester 3 and so forth. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 91 PCI Arbiter 19.3 PLX Technology, Inc. External Arbiter Mode When the EXTARB pin is asserted, the PEX 8111 PCI request inputs to the internal arbiter are disabled. The PEX 8111 generates a PCI request (REQ0#) to an external arbiter when it needs to use the PCI bus. The PCI grant input (GNT0#) to the PEX 8111 allows it to become the PCI bus master. 19.4 Arbitration Parking The PCI bus is not allowed to float for more than 8 clock cycles. When there are no requests for the bus, the arbiter selects a device to drive the bus to a known state by driving its GNT# pin active. When the EXTARB pin is de-asserted (internal arbiter mode), the PEX 8111 selects a PCI master to be parked on the bus during idle periods. The PCI Arbiter Park Select field of the PCICTL register determines which master is parked on the bus. When parked (GNT# driven during idle bus), the device drives AD[31:0], C/BE[3:0]#, and PAR to a known state. PR EL IM IN AR Y In Forward Bridge mode, the PEX 8111 parks on the PCI bus during reset, independent of the EXTARB signal. 92 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 Chapter 20 20.1 Shared Memory Overview The PEX 8111 has a 2Kx32 bit (8 KByte) memory block that can be accessed from the EEPROM, PCI Express bus, or PCI bus. 20.2 EEPROM Accesses When the Shared Memory Load bit in the EEPROM format byte is set, the shared memory is loaded from 20.3 PR EL IM IN AR Y the EEPROM starting at location REG BYTE COUNT + 6. The number of bytes to load is determined by the value in EEPROM locations REG BYTE COUNT + 4 and REG BYTE COUNT + 5. The EEPROM data is always loaded into the shared memory starting at address 0. Data is transferred from the EEPROM to the shared memory in units of DWORDs. Refer to Chapter 4, "EEPROM Controller," for details. PCI Express Accesses The shared memory is accessed using the 64 KByte address space defined by the Base Address Register 0 register. The shared memory is located at address offset 'h8000 in this space. PCI Express posted writes are used to write data to the shared memory. Either single or burst writes are accepted, and PCI Express first and last byte enables are supported. If shared memory write data is poisoned, the data is discarded and an ERR_NONFATAL Message is generated if enabled. PCI Express non-posted reads are used to read data from the shared memory. Either single or burst reads are accepted. If the 8K boundary of the shared memory is reached during a burst write or read, the address wraps around to the beginning of the memory. 20.4 PCI Accesses The shared memory is accessed using the 64 KByte address space defined by the Base Address Register 0 register. The shared memory is located at address offset 'h8000 in this space. PCI single or burst writes are used to write data to the shared memory. PCI byte enables are supported for each DWORD transferred. PCI single or burst reads are used to read data from the shared memory. If the 8K boundary of the shared memory is reached during a burst write or read, a PCI Disconnect is generated. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 93 PLX Technology, Inc. PR EL IM IN AR Y Shared Memory 94 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 Chapter 21 21.1 Configuration Registers Register Description The PCI-Compatible Configuration Registers are accessed by the PCI Express host (Forward Bridge mode) or by the PCI host (Reverse Bridge mode) using the PCI configuration address space. All configuration registers can be accessed from the PCI Express or PCI bus using the 64 KByte memory space defined by PCI Base Address 0. Any register that can be written by the EEPROM controller can also be written using memory writes through PCI Base Address 0. In Reverse Bridge mode, a PCI master cannot access any of the PCI Express Extended Capability Registers using PCI Configuration transactions. PR EL IM IN AR Y When the configuration registers are accessed using memory transactions to Base Address Register 0, the following address mapping is used. Table 21-1. Base Address Register 0 Address Mapping A15 0 0 A13 0 0 A12 0 1 0 1 x x x 1 Register Space PCI-Compatible Configuration Registers Memory-Mapped Configuration Registers Memory-Mapped PCI Express Endpoint Registers (Reverse Bridge mode only) 8 KB Internal shared memory The EEPROM controller can write to any of the configuration registers. An upper address bit is used to select one of the two register spaces. Table 21-2. Selecting Register Space A12 0 1 Register Space PCI-Compatible Configuration Registers Memory-Mapped Configuration registers Each register is 32 bits wide, and can be accessed a byte, word, or DWORD at a time. These registers utilize little endian byte ordering which is consistent with the PCI Local Bus Specification. The least significant byte in a DWORD is accessed at address 0. The least significant bit in a DWORD is 0, and the most significant bit is 31. After the PEX 8111 is powered-up or reset, the registers are set to their default values. Writes to unused registers are ignored, and reads from unused registers return a value of 0. 21.2 Configuration Access Types CFG - These are accesses initiated by PCI Configuration transactions on the primary bus. MM - These are accesses initiated by PCI Memory transactions on either the primary or secondary bus using the address range defined by PCI Base Address 0. EE - These are accesses initiated by the EEPROM controller during initialization. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 95 Configuration Registers 21.3 PLX Technology, Inc. Register Attributes The following register attributes are used to indicate the type of access provided by each register bit. Table 21-3. Access Provided by Each Register Bit HwInit RO RW RW1C WO RsvdP RsvdZ 21.4 Description Hardware Initialized. Register bits are initialized by firmware or hardware mechanisms such as pin strapping or serial EEPROM. Bits are read-only after initialization and can only be reset with "Fundamental Reset." Read-only register. Register bits are read-only and cannot be altered by software. Register bits may be initialized by hardware mechanisms such as pin strapping or serial EEPROM. Read-Write register. Register bits are read-write and may be either set or cleared by software to the desired state. Read-only status, Write-1-to-clear status register. Register bits indicate status when read; a set bit indicating a status event may be cleared by writing a 1. Writing a 0 to RW1C bits has no effect. Write-only. This attribute is used to indicate that a register can be written by the EEPROM controller. Reserved and Preserved. Reserved for future RW implementations. Registers are read-only and must return 0 when read. Software must preserved value read for writes to bits. Reserved and Zero. Reserved for future RW1C implementations. Registers are read-only and must return 0 when read. Software must use 0 for writes to bits. PR EL IM IN AR Y Register Attribute Register Summary Table 21-4. Register Summary Register Group PCI-Compatible Configuration Registers PCI Express Extended Capability Configuration Registers Main Control Registers PCI Express Configuration Registers using Enhanced Configuration Access 8 KBytes General Purpose Memory 96 PCI Space PCI Express Configuration (Forward Bridge mode); PCI Configuration (Reverse Bridge mode) Memory-Mapped, BAR0 PCI Express Configuration (Forward Bridge mode) Memory-Mapped, BAR0 Memory-Mapped, BAR0 Address Range 000-0FFh 100-1FFh 100-1FFh 1000-10FFh Memory-Mapped, BAR0 2000-2FFFh Memory-Mapped, BAR0 8000-9FFFh 000-0FFh PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 Register Mapping 21.5 Register Mapping 21.5.1 PCI-Compatible Configuration Registers (Type 1) Table 21-5. PCI-Compatible Configuration Registers (Type 1) PCI Configuration Register Address 00h 04h 08h 0Ch 10h 14h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch 21.5.2 24 23 Device ID Status 16 15 8 7 Vendor ID Command 0 Class Code Revision ID Primary Latency BIST Header Type Cache Line Size Timer PCI Base Address 0 for Memory-Mapped Configuration Registers PCI Base Address 1 (Not used) Secondary Subordinate Bus Secondary Bus Primary Bus Latency Timer Number Number Number Secondary Status I/O Limit I/O Base Memory Limit Memory Base Prefetchable Memory Limit Prefetchable Memory Base Prefetchable Base Upper 32 Bits Prefetchable Limit Upper 32 Bits I/O Limit Upper 16 Bits I/O Base Upper 16 Bits Capabilities Reserved Pointer PCI Base Address for Expansion ROM (Not Supported) Bridge Control Interrupt Pin Interrupt Line PR EL IM IN AR Y 18h 31 PCI-Compatible Extended Capability Registers for PCI Express Bus Table 21-6. PCI-Compatible Extended Capability Registers for PCI Express Bus PCI Configuration Register Address 40h 44h 48h 4C-4Fh 50h 54h 58h 5Ch 60h 64h 68h 6Ch 70h 74h 78h 7Ch 80h 31 24 23 16 15 8 7 0 Power Management Capabilities Next Item Pointer Capability ID Data Bridge Extensions Power Management CSR Device Specific Control Reserved Message Control Next Item Pointer Capability ID Message Address Message Upper Address Reserved Message Data PCI Express Capabilities Next Item Pointer Capability ID Device Capabilities Device Status Device Control Link Capabilities Link Status Link Control Slot Capabilities Slot Status Slot Control Reserved Root Control Root Status PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 97 Configuration Registers 21.5.3 PLX Technology, Inc. PCI Express Extended Capability Registers Table 21-7. Power Budgeting Capability and Device Serial Number Registers PCI Express Configuration Register Address 100h 31 24 Next Capability Offset 104h 23 16 Capability Version 15 0 Data Select Register Data Register Power Budget Capability Register 10Ch Reserved Next Capability Offset 110h Capability Version PCI Express Extended Capability ID 114h Serial Number Register (Lower DW) 118h Serial Number Register (Upper DW) PR EL IM IN AR Y 21.5.4 7 PCI Express Extended Capability ID Reserved 108h 8 Main Control Registers Table 21-8. Main Control Registers Register DEVINIT EECTL EECLKFREQ PCICTL PCIEIRQENB PCIIRQENB IRQSTAT POWER GPIOCTL GPIOSTAT MAILBOX0 MAILBOX1 MAILBOX2 MAILBOX3 CHIPREV DIAG TLPCFG0 TLPCFG1 TLPCFG2 TLPTAG TLPTIMELIMIT0 TLPTIMELIMIT1 CRSTIMER ECFGADDR 98 Address 1000h 1004h 1008h 100Ch 1010h 1014h 1018h 101Ch 1020h 1024h 1030h 1034h 1038h 103Ch 1040h 1044h 1048h 104Ch 1050h 1054h 1058h 105Ch 1060h 1064h Description Device Initialization EEPROM Control EEPROM Clock Frequency PCI Control PCI Express Interrupt Enable PCI Interrupt Enable Interrupt Status Power Required General-Purpose I/O Control General-Purpose I/O Status Mailbox 0 Mailbox 1 Mailbox 2 Mailbox 3 Chip Silicon Revision Diagnostics TLP Controller Configuration 0 TLP Controller Configuration 1 TLP Controller Configuration 2 TLP Controller Tag TLP Controller Time Limit 0 TLP Controller Time Limit 1 CRS Retry Timer Enhanced Configuration Address Page 142 143 143 144 145 145 146 146 147 148 148 148 148 148 149 149 150 150 150 151 151 151 152 152 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 21.6 PCI-Compatible Configuration Registers (Type 1) PCI-Compatible Configuration Registers (Type 1) Table 21-9. (Address 00h; PCIVENDID) PCI Vendor ID Bits 15:0 Description PCI Vendor ID. This field identifies the manufacturer of the device. Table 21-10. Bits MM EE Default RO RW WO 10B5h CFG MM EE Default RW WO (Address 02h; PCIDEVID) PCI Device ID Description PCI Device ID. This field identifies the particular device, as specified by the Vendor. RO 8111h PR EL IM IN AR Y 15:0 CFG PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 99 Configuration Registers Table 21-11. 0 1 2 3 4 5 6 7 8 9 10 15:11 100 (Address 04h; PCICMD) PCI Command (Forward Bridge Mode) Description I/O Space Enable. This bit enables the device to respond to I/O space accesses on the primary interface (PCI Express). These accesses must be directed to a target on the PCI bus, because the PEX 8111 does not have any internal I/O mapped resources. Memory Space Enable. This bit enables the device to respond to Memory space accesses on the primary interface (PCI Express). These accesses may be directed to either a target on the PCI bus, or to internal memory-mapped registers. When this bit is clear, respond to all Memory Requests on the primary interface with an Unsupported Request completion. Bus Master Enable. This bit enables the PEX 8111 to issue memory and I/O read/write requests on the primary interface (PCI Express). Requests other than memory or I/O requests are not controlled by this bit. If this bit is clear, the bridge must disable response as a target to all memory or I/O transactions on the secondary interface (PCI bus) (they cannot be forwarded to the primary interface). Special Cycle Enable. Does not apply to PCI Express, so this bit is forced to 0. Memory Write and Invalidate. When set, this bit enables the PEX 8111 PCI bus master logic to use the Memory Write-and-Invalidate command. When clear, the Memory Write command is used instead. VGA Palette Snoop. This bit does not apply to PCI Express, so it is forced to 0. Parity Error Response Enable. This bit controls the response to data parity errors forwarded from the primary interface (e.g., a poisoned TLP). If clear, the bridge must ignore (but may record status such as setting the Detected Parity Error bit) any data parity errors that it detects and continue normal operation. If set, the bridge must take its normal action when a data parity error is detected. Address Stepping Enable. The PEX 8111 performs address stepping for PCI Configuration cycles, so this bit is read/write with an initial value of 1. SERR Enable. This bit enables reporting of non-fatal and fatal errors to the Root Complex. CFG Note: Errors are reported if enabled either through this bit or through the PCI-Express specific bits in the Device Control Register. Fast Back-to-Back Enable. This bit does not apply to PCI Express, so it is forced to 0. Interrupt Disable. When set, the PEX 8111 is prevented from generating INTx# interrupt messages on behalf of functions integrated into the bridge. This bit has no effect on INTx# messages generated on behalf of INTx# inputs associated with the PCI secondary interface. Any INTx# emulation interrupts already asserted must be de-asserted when this bit is set. Reserved MM EE Default RW RW WO 0 RW RW WO 0 RW RW WO 0 RO RO -- 0 RW RW WO 0 RO RO -- 0 RW RW WO 0 RW RW WO 1 RW RW WO 0 RO RO -- 0 RW RW WO 0 RsvdP RsvdP -- 0 PR EL IM IN AR Y Bits PLX Technology, Inc. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 Table 21-12. 0 1 2 3 4 5 6 7 8 9 10 15:11 (Address 04h; PCICMD) PCI Command (Reverse Bridge Mode) Description I/O Space Enable. This bit enables the PEX 8111 to respond to I/O space accesses on the primary interface (PCI). These accesses would be directed to a target on the PCI Express bus, because the PEX 8111 does not have any internal I/O mapped devices. When this bit is clear, PCI I/O accesses to the PEX 8111 result in a Master Abort. Memory Space Enable. This bit enables the PEX 8111 to respond to Memory space accesses on the primary interface (PCI). These accesses may be directed to either a target on the PCI Express bus, or to internal memory-mapped registers. When this bit is clear, PCI memory accesses to the PEX 8111 result in a Master Abort. Bus Master Enable. When set, this bit enables the PEX 8111 to perform memory or I/O transactions on the PCI bus. Configuration transactions can be forwarded from the PCI Express bus and performed on the PCI bus independent of this bit. When clear, the bridge must disable response as a target to all memory or I/ O transactions on the secondary interface (PCI Express bus) (they cannot be forwarded to the primary interface). In this case, all Memory and I/O requests are terminated with an Unsupported Request completion. Special Cycle Enable. A bridge does not respond to Special Cycle transactions, so this bit is forced to 0. Memory Write and Invalidate. When set, this bit enables the PEX 8111 PCI bus master logic to use the Memory Write-and-Invalidate command. When clear, the Memory Write command is used instead. VGA Palette Snoop. If set, I/O Writes in the first 64 KB of the I/O address space with address bits 9:0 equal to 3C6h, 3C8h, and 3C9h (inclusive of ISA aliases - AD[15:10] are not decoded and may be any value) must be positively decoded on the PCI interface and forwarded to the secondary interface (PCI Express). Parity Error Response Enable. This bit enables PCI parity checking. Reserved SERR Enable. When asserted, this bit enables the SERR# pin to be asserted. Fast Back to Back Enable. The PEX 8111 PCI master interface does not perform fast back-to-back transactions, so this bit is forced to 0. Interrupt Disable. When set, the PEX 8111 is prevented from asserting INTx# signals on behalf of functions integrated into the bridge. This bit has no effect on INTx# signals asserted on behalf of INTx# messages associated with the PCI Express secondary interface. Reserved CFG PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 MM EE Default RW RW WO 0 RW RW WO 0 RW RW WO 0 RO RO -- 0 RW RW WO 0 RW RW WO 0 RW RW WO 0 RsvdP RsvdP -- 0 RW RW WO 0 RO RO -- 0 RW RW WO 0 RsvdP RsvdP -- 0 PR EL IM IN AR Y Bits PCI-Compatible Configuration Registers (Type 1) 101 Configuration Registers Table 21-13. 3 4 5 6 7 8 10:9 11 12 13 14 15 102 (Address 06h; PCISTAT) PCI Status (Forward Bridge Mode) Description Reserved Interrupt Status. When set, indicates that an INTx# interrupt message is pending on behalf of functions integrated into the bridge. This bit does not reflect the status of INTx# inputs associated with the secondary interface. Capabilities List. This bit indicates if the New Capabilities Pointer at address 34h is valid. Since all PCI Express devices are required to implement the PCI Express capability structure, this bit is hardwired to 1. 66MHz Capable. This optional read-only bit indicates whether the PEX 8111 is capable of running at 66 MHz. A value of 0 indicates 33 MHz. A value of 1 indicates that the PEX 8111 is 66 MHz capable. Reserved Fast Back-To-Back Transactions Capable. Does not apply to PCI Express, so this bit is forced to 0. Master Data Parity Error. This bit is used to report the detection of a data parity error by the bridge. This bit is set if the Parity Error Response Enable bit in the PCI Command register is set and either of the following two conditions occur: * The bridge receives a completion marked poisoned on the primary interface * The bridge poisons a write request or read completion on the primary interface. Writing a 1 clears this bit. Devsel Timing. Does not apply to PCI Express, so this field is forced to 0. Signaled Target Abort. This bit is set when the bridge completes a request as a target of a transaction on its primary interface using Completer Abort completion status. Writing a 1 clears this bit. Received Target Abort. This bit is set when the bridge receives a completion with Completer Abort completion status on its primary interface. Writing a 1 clears this bit. Received Master Abort. This bit is set when the bridge receives a completion with Unsupported Request completion status on its primary interface. Writing a 1 clears this bit. Signaled System Error. This bit is set when the bridge sends an ERR_FATAL or ERR_NONFATAL Message to the Root Complex, and the SERR Enable bit in the PCI Command register is set. Writing a 1 clears this bit. Detected Parity Error. This bit is set by the bridge whenever it receives a poisoned TLP on the primary interface, regardless of the state of the Parity Error Response Enable bit in the PCI Command register. Writing a 1 clears this bit. CFG RsvdZ MM RsvdZ EE -- Default 0 RO RO -- 0 RO RO -- 1 RO RO -- 0 RsvdZ RsvdZ -- 0 RO RO -- 0 RW1C RW1C -- 0 RO RO -- 0 RW1C RW1C -- 0 RW1C RW1C -- 0 RW1C RW1C -- 0 RW1C RW1C -- 0 RW1C RW1C -- 0 PR EL IM IN AR Y Bits 2:0 PLX Technology, Inc. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 Table 21-14. 3 4 5 6 7 8 10:9 11 12 13 14 15 (Address 06h; PCISTAT) PCI Status (Reverse Bridge Mode) Description Reserved Interrupt Status. This bit reflects the state of the PEX 8111 internal PCI interrupt status. One of the INTx# signals is asserted when this bit is high, the Interrupt Disable bit in the PCI Command register is low, and the Power State is D0. Capabilities List. This bit indicates if the New Capabilities Pointer at address 34h is valid. Since all PCI Express devices are required to implement the PCI Express capability structure, this bit is hardwired to 1. 66MHz Capable. The PEX 8111 does not support 66 MHz, so this bit is forced to 0. Reserved Fast Back-To-Back Transactions Capable. The PEX 8111 does not accept fast back-to-back transactions, so this bit is forced to 0. Master Data Parity Error. This bit indicates that a data parity error has occurred when this device was the PCI bus master. The Parity Error Response Enable bit in the PCI Command register must be set for this bit to be set. Writing a 1 clears this bit. Devsel Timing. This field determines how quickly this device responds to a transaction with DEVSEL#. A value of 1 indicates a medium response. Signaled Target Abort. This bit is set whenever the device is acting as a PCI bus target, and terminates its transaction with a Target-Abort. A Target-Abort occurs when a target detects a fatal error and is unable to complete the transaction. This never occurs in the PEX 8111, so a zero is always returned. Received Target Abort. This bit is set whenever the device is acting as a PCI bus master, and has its transaction terminated with a Target-Abort. A Target-Abort occurs when a target detects a fatal error and is unable to complete the transaction. It deasserts DEVSEL# and asserts STOP# to signal the Target Abort. Writing a 1 clears this bit. Received Master Abort. This bit is set whenever the device is acting as a PCI bus master, and has its transaction terminated with a Master-Abort. A Master-Abort occurs when no target responds with a DEVSEL. Writing a 1 clears this bit. Signaled System Error. This bit is set whenever the device asserts the SERR# pin. Writing a 1 clears this bit. Detected Parity Error. This bit is set whenever the device detects a parity error on incoming addresses or data from the PCI bus, regardless of the state of the Parity Error Response Enable bit in the PCI Command register. Writing a 1 clears this bit. CFG RsvdZ MM RsvdZ EE -- Default 0 RO RO -- 0 RO RO -- 1 RO RO -- 0 RsvdZ RsvdZ -- 0 RO RO -- 0 RW1C RW1C -- 0 RO RO -- 1 RsvdZ RsvdZ -- 0 RW1C RW1C -- 0 RW1C RW1C -- 0 RW1C RW1C -- 0 RW1C RW1C -- 0 PR EL IM IN AR Y Bits 2:0 PCI-Compatible Configuration Registers (Type 1) PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 103 Configuration Registers Table 21-15. 7:0 Description PCI Device Revision ID. This field identifies the silicon revision of the device. Bits 3:0 represent the minor revision number and bits 7:4 represent the major revision number. Table 21-16. Bits 7:0 15:8 23:16 7:0 Description Bits 7:0 Bits 7:0 Bits 7:0 104 Default 'h10 RO RO -- CFG RO RO RO MM RW RW RW EE WO WO WO Default 0 4 6 MM EE Default CFG RW CFG MM RO (F) RW (R) RO (F) RW (R) RW WO 0 EE Default -- (F) WO (R) 0 (Address 0Eh; PCIHEADER) PCI Header Type Description PCI Header Type. This field specifies the format of the second part of the predefined configuration header starting at address 10h. For PCI Bridges, this bit is forced to 1. Table 21-20. EE (Address 0Dh; PCILATENCY) PCI Bus Latency Timer Description PCI Bus Latency Timer. This register is also referred to as primary latency timer for Type 1 Configuration Space Header devices. The primary/master latency timer does not apply to PCI Express (Forward Bridge mode). In Reverse Bridge mode, this field specifies, in units of PCI clocks, the value of the Latency Timer during bus master bursts. When the Latency Timer expires, the device must terminate its tenure on the bus. Table 21-19. MM (Address 0Ch; PCICACHESIZE) PCI Cache Line Size Description PCI Cache Line Size. This register specifies the system cache line size in units of DWORDs. The value in this register is used by PCI master devices to determine whether to use Read, Memory Read Line, Memory Read Multiple or Memory Write Invalidate commands for accessing memory. This device only supports cache line sizes of 8, 16, or 32 DWORDs. Writes of values other than these are ignored. Table 21-18. CFG (Address 09h; PCICLASS) PCI Class Code Interface Sub Class Base Class Table 21-17. Bits (Address 08h; PCIDEVREV) PCI Device Revision ID PR EL IM IN AR Y Bits PLX Technology, Inc. CFG MM RO RO EE -- Default 1 (Address 0Fh; PCIBIST) PCI Built-In Self Test Description PCI Built-In Self Test. The built-in self-test function is not supported, and always returns a value of 0. CFG MM RO RO EE -- Default 0 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 Table 21-21. 0 2:1 3 15:4 31:16 Description Space Type. When low, this space is accessed as memory. When high, this space is accessed as I/O. Note: Hardcoded to 0. Address Type. This field indicates the type of addressing for this space. 00 = Locate anywhere in 32-bit address space (default) 01 = Locate below 1 Meg 10 = Locate anywhere in 64-bit address space 11 = Reserved Note: Hardcoded to 0. Prefetch Enable. When set, indicates that pre-fetching has no side effects on reads. Base Address. This part of the base address is ignored for a 64 KByte space. Note: Hardcoded to 0. Base Address. Specifies the upper 16 bits of the 32-bit starting base address of the 64 KByte addressing space for the PEX 8111 Configuration registers and shared memory. Table 21-22. Bits 31:0 (Address 10h; PCIBASE0) PCI Base Address 0 PR EL IM IN AR Y Bits PCI-Compatible Configuration Registers (Type 1) CFG MM EE Default RO RO -- 0 RO RO -- 0 RO RW WO 1 RO RO -- 0 RW RW WO 0 CFG Rsvd P MM Rsvd P EE Default (Address 14h; PCIBASE1) PCI Base Address 1 Description Base Address 1. This base address register is unused. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 -- 0 105 Configuration Registers Table 21-23. 7:0 Description Primary Bus Number. This field is used to record the bus number of the PCI bus segment to which the primary interface of the bridge is connected. Table 21-24. Bits 7:0 7:0 Bits 7:0 106 MM RW RW EE WO CFG MM RW RW WO Default 0 EE CFG MM EE RW RW Default 0 (Address 1Ah; SUBBUSNUM) Subordinate Bus Number Description Subordinate Bus Number. This field is used to record the bus number of the highest numbered PCI bus segment which is behind (or subordinate to) the bridge. Table 21-26. CFG (Address 19h; SECBUSNUM) Secondary Bus Number Description Secondary Bus Number. This field is used to record the bus number of the PCI bus segment to which the secondary interface of the bridge is connected. Table 21-25. Bits (Address 18h; PRIMBUSNUM) Primary Bus Number PR EL IM IN AR Y Bits PLX Technology, Inc. WO Default 0 (Address 1Bh; SECLATTIMER) Secondary Latency Timer Description Secondary Latency Timer. This field specifies, in units of PCI clocks, the value of the Latency Timer during secondary PCI bus master bursts. When the Latency Timer expires, the device must terminate its tenure on the bus. This field is only valid in Forward Bridge mode. CFG MM RW RW EE WO Default 0 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 Table 21-27. 3:0 7:4 Description I/O Base Address Capability. This field indicates the type of addressing for this space. 00 = 16-bit I/O addressing 01 = 32-bit I/O addressing Others = Reserved I/O Base. This field defines the starting address at which I/O transactions on the primary interface are forwarded to the secondary interface. The upper 4 bits of this register correspond to address bits AD[15:12]. For purposes of address decoding, the bridge assumes that the lower 12 address bits, AD[11:0], of the I/O base address are zero. Thus, the bottom of the defined I/O address range is aligned to a 4 KByte boundary, and the top is one less than a 4 KByte boundary. Table 21-28. Bits 3:0 7:4 (Address 1Ch; IOBASE) I/O Base CFG MM EE Default RO RW WO 0 RW RW WO 0 (Address 1Dh; IOLIMIT) I/O Limit PR EL IM IN AR Y Bits PCI-Compatible Configuration Registers (Type 1) Description I/O Limit Address Capability. This field indicates the type of addressing for this space. 00 = 16-bit I/O addressing 01 = 32-bit I/O addressing Others = Reserved The value returned in this field is derived from the I/O Base Address Capability field of the IOBASE register. I/O Limit. This field determines the range of the I/O space that is forwarded from the primary interface to the secondary interface. The upper 4 bits of this register correspond to address bits AD[15:12]. For purposes of address decoding, the bridge assumes that the lower 12 address bits, AD[11:0], of the I/O limit address are FFFh. If there are no I/O addresses on the secondary side of the bridge, the I/O Limit field can be programmed to a smaller value than the I/O Base field. In this case, the bridge does not forward any I/O transactions from the primary bus to the secondary, and does forward all I/O transactions from the secondary bus to the primary bus. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 CFG MM EE Default RO RO -- 0 RW RW WO 0 107 Configuration Registers Table 21-29. 6 7 8 10:9 11 12 13 14 15 108 (Address 1Eh; SECSTAT) Secondary Status (Forward Bridge Mode) Description Reserved Secondary 66MHz Capable. This bit indicates whether or not the secondary interface of the bridge is capable of operating at 66 MHz. The PEX 8111 only supports 66 MHz, so this bit is hardwired to 0. Reserved Secondary Fast Back-To-Back Transactions Capable. This bit indicates whether or not the secondary interface of the bridge is capable of decoding fast back-to-back transactions when the transactions are from the same master but to different targets. (A bridge is required to support fast back-to-back transactions from the same master.) The PEX 8111 does not support fast back-to-back decoding. Secondary Master Data Parity Error. This bit is used to report the detection of a data parity error by the bridge when it is the master of the transaction on the secondary interface. This bit is set if the following three conditions are true: * The bridge is the bus master of the transaction on the secondary interface. * The bridge asserted PERR# (read transaction) or detected PERR# asserted (write transaction). * The Secondary Parity Error Response Enable bit in the Bridge Control register is set. Writing a 1 clears this bit. Secondary Devsel Timing. This field encodes the timing of the secondary interface DEVSEL#. The encoding must indicate the slowest response time that the bridge uses to assert DEVSEL# on its secondary interface when it is responding as a target to any transaction except a Configuration Read or Configuration Write. This field is hardwired to a value of 1, indicating medium DEVSEL# timing. Secondary Signaled Target Abort. This bit reports the signaling of a Target-Abort termination by the bridge when it responds as the target of a transaction on its secondary interface. Writing a 1 clears this bit. Secondary Received Target Abort. This bit reports the detection of a Target-Abort termination by the bridge when it is the master of a transaction on its secondary interface. Writing a 1 clears this bit. Secondary Received Master Abort. This bit reports the detection of a Master-Abort termination by the bridge when it is the master of a transaction on its secondary interface. This bit is also set for a PCI Express to PCI configuration transaction with an extended address not equal to 0. Writing a 1 clears this bit. Secondary Received System Error. This bit reports the detection of an SERR# assertion on the secondary interface of the bridge. Writing a 1 clears this bit. Secondary Detected Parity Error. This bit reports the detection of an address or data parity error by the bridge on its secondary interface. This bit is set when any of the following three conditions are true: * Bridge detects an address parity error as a potential target * Bridge detects a data parity error when the target of a write transaction * Bridge detects a data parity error when the master of a read transaction This bit is set irrespective of the state of the Secondary Parity Error Response Enable bit in the Bridge Control register. Writing a 1 clears this bit. CFG RsvdZ RO MM RsvdZ RO EE -- -- Default 0 0 RsvdZ RsvdZ -- 0 RO RO -- 0 RW1C RW1C -- 0 RO RO -- 1 RW1C RW1C -- 0 RW1C RW1C -- 0 RW1C RW1C -- 0 RW1C RW1C -- 0 RW1C RW1C -- 0 PR EL IM IN AR Y Bits 4:0 5 PLX Technology, Inc. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 Table 21-30. 5 6 7 8 10:9 11 12 13 14 15 (Address 1Eh; SECSTAT) Secondary Status (Reverse Bridge Mode) Description Reserved Secondary 66MHz Capable. This bit indicates whether or not the secondary interface of the bridge is capable of operating at 66 MHz. This bit is not valid for the PCI Express and is forced to 0. Reserved Secondary Fast Back-To-Back Transactions Capable. This bit indicates whether or not the secondary interface of the bridge is capable of decoding fast back-to-back transactions when the transactions are from the same master but to different targets. This bit is not valid for the PCI Express and is forced to 0. Secondary Master Data Parity Error. This bit is used to report the detection of a data parity error by the bridge. This bit is set if the Secondary Parity Error Response Enable bit in the Bridge Control register is set and either of the following two conditions occur: * The bridge receives a completion marked poisoned on the secondary interface * The bridge poisons a write request or read completion on the secondary interface. Writing a 1 clears this bit. Secondary Devsel Timing. This field encodes the timing of the secondary interface DEVSEL#. This field is not valid for the PCI Express and is forced to 0. Secondary Signaled Target Abort. This bit is set when the bridge completes a request as a target of a transaction on its secondary interface using Completer Abort completion status. Writing a 1 clears this bit. Secondary Received Target Abort. This bit is set when the bridge receives a completion with Completer Abort completion status on its secondary interface. Writing a 1 clears this bit. Secondary Received Master Abort. This bit is set when the bridge receives a completion with Unsupported Request completion status on its secondary interface. Writing a 1 clears this bit. Secondary Received System Error. This bit is set when the PEX 8111 receives an ERR_FATAL or ERR_NONFATAL message from the downstream PCI Express device. Writing a 1 clears this bit. Secondary Detected Parity Error. This bit is set by the bridge whenever it receives a poisoned TLP on the secondary interface, regardless of the state of the Secondary Parity Error Response Enable bit in the Bridge Control register. Writing a 1 clears this bit. CFG RsvdZ MM RsvdZ EE -- Default 0 RO RO -- 0 RsvdZ RsvdZ -- 0 RO RO -- 0 RW1C RW1C -- 0 RO RO -- 0 RW1C RW1C -- 0 RW1C RW1C -- 0 RW1C RW1C -- 0 RW1C RW1C -- 0 RW1C RW1C -- 0 PR EL IM IN AR Y Bits 4:0 PCI-Compatible Configuration Registers (Type 1) PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 109 Configuration Registers Table 21-31. 15:4 Description Reserved Memory Base. This field defines the starting address at which Memory transactions on the primary interface are forwarded to the secondary interface. The upper 12 bits of this register correspond to address bits AD[31:20]. For purposes of address decoding, the bridge assumes that the lower 20 address bits, AD[19:0], of the memory base address are zero. The bottom of the defined memory address range is aligned to a 1 Mbyte boundary, and the top is one less than a 1 MByte boundary. Table 21-32. Bits 3:0 15:4 110 (Address 20h; MEMBASE) Memory Base CFG RsvdP MM RsvdP EE -- Default 0 RW RW WO -- CFG RsvdP MM RsvdP EE -- Default 0 RW RW WO -- (Address 22h; MEMLIMIT) Memory Limit Description Reserved Memory Limit. This field determines the range of the Memory space that is forwarded from the primary interface to the secondary interface. The upper 12 bits of this register correspond to address bits AD[31:20]. For purposes of address decoding, the bridge assumes that the lower 20 address bits, AD[19:0], of the memory limit address are FFFFFh. If there are no memory-mapped I/O addresses on the secondary side of the bridge, the Memory Limit field must be programmed to a smaller value than the Memory Base field. If there is no prefetchable memory, and there is no memory-mapped I/O on the secondary side of the bridge, then the bridge does not forward any memory transactions from the primary bus to the secondary, and does forward all memory transactions from the secondary bus to the primary bus. PR EL IM IN AR Y Bits 3:0 PLX Technology, Inc. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 Table 21-33. 3:0 15:4 Description Prefetchable Base Address Capability. This field indicates the type of addressing for this space. 00 = 32-bit I/O addressing 01 = 64-bit I/O addressing Others = Reserved Prefetchable Memory Base. This field defines the starting address at which Prefetchable Memory transactions on the primary interface are forwarded to the secondary interface. The upper 12 bits of this register correspond to address bits AD[31:20]. For purposes of address decoding, the bridge assumes that the lower 20 address bits, AD[19:0], of the prefetchable memory base address are zero. The bottom of the defined prefetchable memory address range is aligned to a 1 Mbyte boundary, and the top is one less than a 1 Mbyte boundary. Table 21-34. Bits 3:0 15:4 (Address 24h; PREBASE) Prefetchable Memory Base PR EL IM IN AR Y Bits PCI-Compatible Configuration Registers (Type 1) CFG MM EE Default RO RW WO 0 RW RW WO -- CFG MM RO RO -- 0 RW RW WO -- (Address 26h; PRELIMIT) Prefetchable Memory Limit Description Prefetchable Limit Address Capability. This field indicates the type of addressing for this space. 00 = 32-bit addressing 01 = 64-bit addressing Others = Reserved The value returned in this field is derived from the Prefetchable Base Address Capability field of the PREBASE register. Prefetchable Memory Limit. This field determines the range of the Prefetchable Memory space that is forwarded from the primary interface to the secondary interface. The upper 12 bits of this register correspond to address bits AD[31:20]. For purposes of address decoding, the bridge assumes that the lower 20 address bits, AD[19:0], of the prefetchable memory limit address are FFFFFh. If there is no prefetchable memory on the secondary side of the bridge, the Prefetchable Memory Limit field must be programmed to a smaller value than the Prefetchable Memory Base field. If there is no prefetchable memory, and there is no memory-mapped I/O on the secondary side of the bridge, then the bridge does not forward any memory transactions from the primary bus to the secondary, and does forward all memory transactions from the secondary bus to the primary bus. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 EE Default 111 Configuration Registers Table 21-35. 31:0 Description Prefetchable Memory Base Upper 32 Bits. If the Prefetchable Base Address Capability field indicates 32-bit addressing, this register is read-only and returns a 0. If the Prefetchable Base Address Capability field indicates 64-bit addressing, this register provides the upper 32 bits of the starting address at which Prefetchable Memory transactions on the primary interface are forwarded to the secondary interface. Table 21-36. Bits 31:0 15:0 Bits 15:0 112 MM RW RW EE WO Default 0 CFG MM RW RW EE WO Default 0 (Address 30h; IOBASEUPPER) I/O Base Upper 16 Bits Description I/O Base Upper 16 Bits. If the I/O Base Address Capability field indicates 16-bit addressing, this register is read-only and returns a 0. If the I/O Base Address Capability field indicates 32-bit addressing, this register provides the upper 16 bits of the starting address at which I/O transactions on the primary interface are forwarded to the secondary interface. Table 21-38. CFG (Address 2Ch; PRELIMITUPPER) Prefetchable Memory Limit Upper 32 Bits Description Prefetchable Memory Limit Upper 32 Bits. If the Prefetchable Base Address Capability field indicates 32-bit addressing, this register is read-only and returns a 0. If the Prefetchable Base Address Capability field indicates 64-bit addressing, this register determines the upper 32 bits of the range of the Prefetchable Memory transactions on the primary interface are forwarded to the secondary interface. Table 21-37. Bits Address 28h; PREBASEUPPER) Prefetchable Memory Base Upper 32 Bits PR EL IM IN AR Y Bits PLX Technology, Inc. CFG MM RW RW CFG MM RW RW EE WO Default -- (Address 32h; IOLIMITUPPER) I/O Limit Upper 16 Bits Description I/O Limit Upper 16 Bits. If the I/O Base Address Capability field indicates 16-bit addressing, this register is read-only and returns a 0. If the I/O Base Address Capability field indicates 32-bit addressing, this register determines the upper 16 bits of the range of the I/O transactions on the primary interface are forwarded to the secondary interface. EE WO Default -- PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 Table 21-39. 7:0 31:8 Description PCI Capabilities Pointer. This field provides the configuration address of the first New Capabilities register. Reserved Table 21-40. Bits 7:0 7:0 CFG MM EE Default RO RW WO 'h40 RsvdP RsvdP -- 0 CFG MM EE Default RW RW WO CFG MM EE RO RW (Address 3Ch; PCIINTLINE) PCI Interrupt Line Description PCI Interrupt Line. This field indicates which input of the system interrupt controller the interrupt pin of the device is connected to. Device drivers and operating systems use this field. Table 21-41. Bits (Address 34h; PCICAPPTR) PCI Capabilities Pointer 0 (Address 3Dh; PCIINTPIN) PCI Interrupt Pin PR EL IM IN AR Y Bits PCI-Compatible Configuration Registers (Type 1) Description PCI Interrupt Pin. For Forward Bridge mode, this register identifies the legacy interrupt message(s) the device uses. Valid values are 1, 2, 3, and 4 that map to legacy interrupt messages for INTA#, INTB#, INTC#, and INTD#. A value of 0 indicates that the device uses no legacy interrupt message(s). For Reverse Bridge mode, this register selects which interrupt pin the device uses. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 WO Default 1 113 Configuration Registers Table 21-42. 0 1 2 3 114 (Address 3Eh; BRIDGECTL) Bridge Control (Forward Bridge Mode) Description Secondary Parity Error Response Enable. This bit controls the response of the bridge to address and data parity errors on the secondary interface (PCI). If this bit is set, the bridge must take its normal action when a parity error is detected. If this bit is cleared, the bridge must ignore any parity errors that it detects and continue normal operation. A bridge must generate parity even if the parity error reporting is disabled. Also, the bridge must always forward posted write data with poisoning, from PCI to PCI Express on a PCI data parity error, regardless of the setting of this bit. Secondary SERR Enable. This bit controls the forwarding of secondary interface (PCI) SERR# assertions to the primary interface (PCI Express). The bridge transmits an ERR_FATAL message on the primary interface when all of the following are true: * SERR# is asserted on the secondary interface. * This bit is set. * The SERR Enable bit is set in the PCI Command register or the Fatal or Non-Fatal Error Reporting Enable bits are set in the PCI Express Device Control register. ISA Enable. This bit modifies the response by the bridge to ISA I/O addresses that are enabled by the I/O Base and I/O Limit registers and are in the first 64 KBytes of the PCI I/O address space. If this bit is set, the bridge blocks any forwarding from primary to secondary of I/O transactions addressing the last 768 bytes in each 1 KByte block. In the opposite direction (secondary to primary), I/O transactions are forwarded if they address the last 768 bytes in each 1 KByte block. VGA Enable. This bit modifies the response by the bridge to VGA-compatible addresses. If this bit is set, the bridge positively decodes and forwards the following accesses on the primary interface to the secondary interface (and, conversely, blocks the forwarding of these addresses from the secondary to primary interface): * Memory accesses in the range 000A0000h to 000B FFFFh. * I/O address in the first 64 KB of the I/O address space (Address[31:16] for PCI Express are 0000h) and where Address[9:0] is in the range of 3B0h to 3BBh or 3C0h to 3DFh (inclusive of ISA address aliases - Address[15:10] may possess any value and is not used in the decoding) CFG If the VGA Enable bit is set, forwarding of VGA addresses is independent of the value of the ISA Enable bit (located in the Bridge Control register), the I/O address range and memory address ranges defined by the I/O Base and Limit registers, the Memory Base and Limit registers, and the Prefetchable Memory Base and Limit registers of the bridge. The forwarding of VGA addresses is qualified by the I/O Enable and Memory Enable bits in the PCI Command register. 0 - Do not forward VGA compatible memory and I/O addresses from the primary to secondary interface (addresses defined above) unless they are enabled for forwarding by the defined I/O and memory address ranges. 1 - Forward VGA compatible memory and I/O addresses (addresses defined above) from the primary interface to the secondary interface (if the I/O Enable and Memory Enable bits are set) independent of the I/O and memory address ranges and independent of the ISA Enable bit. MM EE Default RW RW WO 0 RW RW WO 0 RW RW WO 0 RW RW WO 0 PR EL IM IN AR Y Bits PLX Technology, Inc. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 Table 21-42. Bits 4 PCI-Compatible Configuration Registers (Type 1) (Address 3Eh; BRIDGECTL) Bridge Control (Forward Bridge Mode) (Cont.) Description VGA 16-bit Decode. This bit enables the bridge to provide 16-bit decoding of VGA I/O address precluding the decoding of alias addresses every 1KB. This bit only has meaning if bit 3 (VGA Enable) of this register is also set to 1, enabling VGA I/O decoding and forwarding by the bridge. This bit enables system configuration software to select between 10 and 16-bit I/O address decoding for all VGA I/O register accesses that are forwarded from primary to secondary whenever the VGA Enable bit is set to 1. 0 - execute 10-bit address decodes on VGA I/O accesses. 1 - execute 16-bit address decodes on VGA I/O accesses. Master Abort Mode. This bit controls the behavior of a bridge when it receives a Master-Abort termination on the PCI bus or an Unsupported Request on PCI Express. CFG RW MM EE Default RW WO 0 RW RW WO 0 RW RW WO 0 RO RO -- 0 5 PR EL IM IN AR Y 0 - Do not report Master-Aborts. If PCI Express UR is received: * Return FFFFFFFFh to PCI bus for reads * Complete non-posted write normally on PCI bus (assert TRDY#) and * Discard the write data * Discard posted PCI to PCI Express write data If PCI transaction terminates with Master Abort: * Complete non-posted transaction with Unsupported Request * Discard posted write data from PCI Express to PCI 1 - Report Master-Aborts If PCI Express UR is received: * Complete reads and non-posted writes with PCI Target Abort * Discard posted PCI to PCI Express write data 6 7 If PCI transaction terminates with Master Abort: * Complete non-posted transaction with Unsupported Request * Discard posted write data from PCI Express to PCI * Send ERR_NONFATAL Message for posted writes. Secondary Bus Reset. When set, forces the assertion of RST# on the secondary bus. The bridge secondary bus interface and any buffers between the two interfaces (primary and secondary) must be initialized back to their default state whenever this bit is set. The primary bus interface and all configuration space registers must not be affected by the setting of this bit. Because RST# is asserted for as long as this bit is set, software must observe proper PCI reset timing requirements. Fast Back to Back Enable. This bit controls the ability of the bridge to generate fast back-to-back transactions to different devices on the secondary interface. The PEX 8111 does not support this feature. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 115 Configuration Registers Table 21-42. 8 9 10 11 15:12 116 (Address 3Eh; BRIDGECTL) Bridge Control (Forward Bridge Mode) (Cont.) Description Primary Discard Timer. In Forward Bridge mode, this bit does not apply and is forced to 0. Secondary Discard Timer. Selects the number of PCI clocks that the bridge waits for a master on the secondary interface to repeat a Delayed Transaction request. The counter starts once the completion (PCI Express Completion associated with the Delayed Transaction Request) has reached the head of the downstream queue of the bridge (i.e., all ordering requirements have been satisfied and the bridge is ready to complete the Delayed Transaction with the originating master on the secondary bus). If the originating master does not repeat the transaction before the counter expires, the bridge deletes the Delayed Transaction from its queue and sets the Discard Timer Status bit. 0 - The Secondary Discard Timer counts 215 PCI clock periods. 1 - The Secondary Discard Timer counts 210 PCI clock periods. Discard Timer Status. This bit is set to a 1 when the Secondary Discard Timer expires and a Delayed Completion is discarded from a queue in the bridge. Writing a 1 clears this bit. Discard Timer SERR Enable. When set to 1, this bit enables the bridge to generate an ERR_NONFATAL Message on the primary interface when the Secondary Discard Timer expires and a Delayed Transaction is discarded from a queue in the bridge. 0 - Do not generate ERR_NONFATAL Message on the primary interface as a result of the expiration of the Secondary Discard Timer. 1 - Generate ERR_NONFATAL Message on the primary interface if the Secondary Discard Timer expires and a Delayed Transaction is discarded from a queue in the bridge. Reserved CFG MM EE Default RO RO -- 0 RW RW WO 0 RW1C RW1C WO 0 RW RW WO 0 RsvdP RsvdP -- 0 PR EL IM IN AR Y Bits PLX Technology, Inc. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 Table 21-43. 0 1 2 3 (Address 3Eh; BRIDGECTL) Bridge Control (Reverse Bridge Mode) Description Secondary Parity Error Response Enable. This bit controls the response of the bridge to data parity errors forwarded from the primary interface (e.g., a poisoned TLP). If clear, the bridge must ignore any data parity errors that it detects and continue normal operation. If set, the bridge must take its normal action when a data parity error is detected. Secondary SERR Enable. This bit has no affect in Reverse Bridge mode. Secondary bus error reporting using SERR# is controlled by the ROOTCTL register. ISA Enable. This bit modifies the response by the bridge to ISA I/O addresses that are enabled by the I/O Base and I/O Limit registers and are in the first 64 KBytes of the PCI I/O address space. If this bit is set, the bridge blocks any forwarding from primary to secondary of I/O transactions addressing the last 768 bytes in each 1 KByte block. In the opposite direction (secondary to primary), I/O transactions are forwarded if they address the last 768 bytes in each 1 KByte block. VGA Enable. This bit modifies the response by the bridge to VGA-compatible addresses. If this bit is set, the bridge positively decodes and forwards the following accesses on the primary interface to the secondary interface (and, conversely, block the forwarding of these addresses from the secondary to primary interface): * Memory accesses in the range 000A0000h to 000B FFFFh. * I/O address in the first 64 KB of the I/O address space (Address[31:16] for PCI Express are 0000h) and where Address[9:0] is in the range of 3B0h to 3BBh or 3C0h to 3DFh (inclusive of ISA address aliases - Address[15:10] may possess any value and is not used in the decoding) If the VGA Enable bit is set, forwarding of VGA addresses is independent of the value of the ISA Enable bit (located in the Bridge Control register), the I/O address range and memory address ranges defined by the I/O Base and Limit registers, the Memory Base and Limit registers, and the Prefetchable Memory Base and Limit registers of the bridge. The forwarding of VGA addresses is qualified by the I/O Enable and Memory Enable bits in the PCI Command register. 0 - Do not forward VGA compatible memory and I/O addresses from the primary to secondary interface (addresses defined above) unless they are enabled for forwarding by the defined I/O and memory address ranges. 1 - Forward VGA compatible memory and I/O addresses (addresses defined above) from the primary interface to the secondary interface (if the I/O Enable and Memory Enable bits are set) independent of the I/O and memory address ranges and independent of the ISA Enable bit. CFG PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 MM EE Default RW RW WO 0 RW RW WO 0 RW RW WO 0 RW WO 0 PR EL IM IN AR Y Bits PCI-Compatible Configuration Registers (Type 1) RW 117 Configuration Registers Table 21-43. 4 5 (Address 3Eh; BRIDGECTL) Bridge Control (Reverse Bridge Mode) (Cont.) Description VGA 16-bit Decode. This bit enables the bridge to provide 16-bit decoding of VGA I/O address precluding the decoding of alias addresses every 1KB. This bit only has meaning if bit 3 (VGA Enable) of this register is also set to 1, enabling VGA I/O decoding and forwarding by the bridge. This bit enables system configuration software to select between 10 and 16-bit I/O address decoding for all VGA I/O register accesses that are forwarded from primary to secondary whenever the VGA Enable bit is set to 1. 0 - execute 10-bit address decodes on VGA I/O accesses. 1 - execute 16-bit address decodes on VGA I/O accesses. Master Abort Mode. This bit controls the behavior of a bridge when it receives a Master-Abort termination on the PCI bus or an Unsupported Request on PCI Express. 0 - Do not report Master-Aborts. If PCI Express UR is received: * Return FFFFFFFFh to PCI bus for reads * Complete non-posted write normally on PCI bus (assert TRDY#) and discard the write data * Discard posted PCI to PCI Express write data CFG RW If PCI transaction terminates with Master Abort: * Complete non-posted transaction with Unsupported Request * Discard posted write data from PCI Express to PCI MM EE Default RW WO 0 RW RW WO 0 RW RW WO 0 RO RO -- 0 PR EL IM IN AR Y Bits PLX Technology, Inc. 1 - Report Master-Aborts If PCI Express UR is received: * Complete reads and non-posted writes with PCI Target Abort * Discard posted PCI to PCI Express write data 6 7 118 If PCI transaction terminates with Master Abort: * Complete non-posted transaction with Unsupported Request * Discard posted write data from PCI Express to PCI * Send ERR_NONFATAL Message for posted writes. Secondary Bus Reset. When set, causes a Hot Reset to be communicated on the secondary bus. The bridge's secondary bus interface and any buffers between the two interfaces (primary and secondary) must be initialized back to their default state whenever this bit is set. The primary bus interface and all configuration space registers are not affected by the setting of this bit. Fast Back to Back Enable. This bit controls the ability of the bridge to generate fast back-to-back transactions to different devices on the secondary interface. The PEX 8111 does not support this feature. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 Table 21-43. 8 9 10 11 15:12 (Address 3Eh; BRIDGECTL) Bridge Control (Reverse Bridge Mode) (Cont.) Description Primary Discard Timer. Selects the number of PCI clocks that the bridge waits for a master on the primary interface to repeat a Delayed Transaction request. The counter starts once the completion (PCI Express Completion associated with the Delayed Transaction Request) has reached the head of the downstream queue of the bridge (i.e., all ordering requirements have been satisfied and the bridge is ready to complete the Delayed Transaction with the originating master on the secondary bus). If the originating master does not repeat the transaction before the counter expires, the bridge deletes the Delayed Transaction from its queue and sets the Discard Timer Status bit. 0 - The Secondary Discard Timer counts 215 PCI clock periods. 1 - The Secondary Discard Timer counts 210 PCI clock periods. Secondary Discard Timer. In Reverse Bridge mode, this bit does not apply and is forced to 0. Discard Timer Status. This bit is set to a 1 when the Primary Discard Timer expires and a Delayed Completion is discarded from a queue in the bridge. Discard Timer SERR Enable. When set to 1, this bit enables the bridge to assert SERR# on the primary interface when the Primary Discard Timer expires and a Delayed Transaction is discarded from a queue in the bridge. 0 - Do not assert SERR# on the primary interface as a result of the expiration of the Primary Discard Timer. 1 - Generate SERR# on the primary interface if the Primary Discard Timer expires and a Delayed Transaction is discarded from a queue in the bridge. Reserved CFG PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 MM EE Default RW RW WO 0 RO RO -- 0 RW1C RW1C -- 0 RW RW WO 0 RsvdP RsvdP -- 0 PR EL IM IN AR Y Bits PCI-Compatible Configuration Registers (Type 1) 119 Configuration Registers 21.7 PCI-Compatible Extended Capability Registers Table 21-44. 7:0 Description Power Management Capability ID. This register specifies the Power Management Capability ID. Table 21-45. Bits 7:0 2:0 3 4 5 8:6 9 10 15:11 120 CFG MM RO RO EE -- Default 1 (Address 41h; PWRMNGNEXT) Power Management Next Pointer Description PCI Power Management Next Pointer. This register points to the first location of the next item in the capabilities linked list. Table 21-46. Bits (Address 40h; PWRMNGID) Power Management Capability ID CFG MM RO RW EE WO Default 50h (Address 42h; PWRMNGCAP) Power Management Capabilities (Forward) PR EL IM IN AR Y Bits PLX Technology, Inc. Description PME Version. This field specifies the revision of the PCI Power Management Interface Specification to which this device complies PME Clock. For Forward Bridge mode, does not apply to PCI Express, so this bit should always have a value of 0. Reserved Device Specific Initialization. This bit indicates that the device requires special initialization following a transition to the D0uninitialized state before the generic class device driver can use it. AUX Current. This field reports the 3.3Vaux auxiliary current requirements for the PCI function. If PME# generation from D3cold is not supported by the function, this field must return a value of 0. D1 Support. This bit specifies that the device supports the D1 state. D2 Support. This bit specifies that the device supports the D2 state. PME Support. This field indicates the power states in which the device may send a PME message Description Value XXXX1 Can be asserted from D0 XXX1X Can be asserted from D1 XX1XX Can be asserted from D2 X1XXX Can be asserted from D3hot 1XXXX Can be asserted from D3cold CFG MM EE Default RO RW WO 2 RO RO -- 0 RsvdP RsvdP -- 0 RO RW WO 0 RO RW WO 0 RO RW WO 1 RO RW WO 0 RO RW WO 0Bh PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 Table 21-47. 2:0 3 4 5 8:6 9 10 15:11 (Address 42h; PWRMNGCAP) Power Management Capabilities (Reverse) Description PME Version. This field specifies the revision of the PCI Power Management Interface Specification to which this device complies PME Clock. When low, this bit indicates that no PCI clock is required to generate PME#. When high, this bit indicates that a PCI clock is required to generate PME#. Reserved Device Specific Initialization. This bit indicates that the device requires special initialization following a transition to the D0uninitialized state before the generic class device driver can use it. AUX Current. This field reports the 3.3Vaux auxiliary current requirements for the PCI function. If PME# generation from D3cold is not supported by the function, this field must return a value of 0. D1 Support. This bit specifies that the device supports the D1 state. D2 Support. This bit specifies that the device supports the D2 state. PME Support. This field indicates the power states in which the device may assert the PME# pin. Value Description XXXX1 Can be asserted from D0 XXX1X Can be asserted from D1 XX1XX Can be asserted from D2 X1XXX Can be asserted from D3hot 1XXXX Can be asserted from D3cold CFG PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 MM EE Default RO RW WO 2 RO RW WO 0 RsvdP RsvdP -- 0 RO RW WO 0 RO RW WO 0 RO RW WO 1 RO RW WO 0 RO RW WO 0Bh PR EL IM IN AR Y Bits PCI-Compatible Extended Capability Registers 121 Configuration Registers Table 21-48. 1:0 7:2 8 12:9 14:13 15 Description Power State. This field is used to determine or change the current power state. State Value 00 D0 01 D1 10 D2 11 D3hot A transition from state D3 to state D0 causes a soft reset to occur. In states D1 and D2, if the corresponding D1 Support and D2Support bits are set, PCI memory and I/O accesses are disabled, as well as the PCI interrupt, and only configuration cycles are allowed. In state D3hot, these functions are also disabled. Reserved PME Enable. This bit enables a PME Message to be transmitted upstream. Data Select. This field is not supported, and always returns a value of 0 Data Scale. This field is not supported, and always returns a value of 0. PME Status. This bit indicates that a PME Message has been transmitted upstream. Writing a 1 clears the bit. Table 21-49. Bits 1:0 7:2 8 12:9 14:13 15 122 (Address 44h; PWRMNGCSR) Power Management Control/Status (Forward) CFG MM EE Default RW RW WO 0 RsvdP RsvdP -- 0 RW RW WO 0 RO RO -- 0 RO RO -- 0 RW1C RW1C -- 0 PR EL IM IN AR Y Bits PLX Technology, Inc. (Address 44h; PWRMNGCSR) Power Management Control/Status (Reverse) Description Power State. This field is used to determine or change the current power state. Value State 00 D0 01 D1 10 D2 11 D3hot A transition from state D3 to state D0 causes a soft reset to occur. In states D1 and D2, if the corresponding D1 Support and D2 Support bits are set, PCI memory and I/O accesses are disabled, as well as the PCI interrupt, and only configuration cycles are allowed. In state D3hot, these functions are also disabled. Reserved PME Enable. This bit enables the PME# pin to be asserted. Data Select. This field is not supported, and always returns a value of 0 Data Scale. This field is not supported, and always returns a value of 0. PME Status. This bit indicates that the PME# pin is being driven if PME Enable bit is set high. Writing a 1 from the PCI bus clears the bit. CFG MM EE Default RW RW WO 0 RsvdP RsvdP -- 0 RW RW WO 0 RO RO -- 0 RO RO -- 0 RW1C RW1C -- 0 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 Table 21-50. 6 7 Description Reserved B2/B3 Support. Does not apply to PCI Express, so this bit is forced to 0. Bus Power/Clock Control Enable. Does not apply to PCI Express, so this bit is forced to 0. Table 21-51. Bits 5:0 6 7 7:0 CFG RsvdP MM RsvdP EE -- Default 0 RO RO -- 0 RO RO -- 0 Address 46h; PWRMNGBRIDGE) Power Management Bridge Support (Reverse) Description Reserved B2/B3 Support. When set, indicates that, when the bridge function is programmed to D3hot , its secondary bus PCI clock is stopped (B2). When clear, indicates that, when the bridge function is programmed to D3hot , its secondary bus has its power removed (B3). This bit is only meaningful if bit 7 is set. Bus Power/Clock Control Enable. When set, indicates that the bus power/clock control mechanism as defined in section 4.7.1 of the PCI Bridge spec is enabled. Table 21-52. Bits (Address 46h; PWRMNGBRIDGE) Power Management Bridge Support (Forward) CFG RsvdP MM RsvdP EE -- Default 0 RO RW WO 0 RO RW WO 0 PR EL IM IN AR Y Bits 5:0 PCI-Compatible Extended Capability Registers (Address 47h; PWRMNGDATA) Power Management Data Description Power Management Data. This function is not supported, and always returns a value of 0. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 CFG RO MM RO EE -- Default 0 123 Configuration Registers Table 21-53. 0 1 2 3 7:4 9:8 10 11 12 15:13 20:16 31:21 124 (Address 48h; DEVSPECCTL) Device Specific Control Description Blind Prefetch Enable. When this bit is clear, a Memory Read command on the PCI bus that targets the PCI Express prefetchable memory space causes only 1 word to be read from PCI Express bus. When this bit is set, a Memory Read command on the PCI bus that targets the PCI Express prefetchable memory space causes a cache line to be read from PCI Express bus. PCI Base Address 0 Enable. When set, this bit enables the PCI Base Address 0 space for memory-mapped access to the configuration registers and shared memory. Reserved PMU Power Off. When set, the link has transitioned to the L2/L3 Ready state, and is ready to be powered-down. PMU Link State. This field indicates the state of the link. State Value 0001 L0 0010 L0s 0100 L1 1000 L2 CRS Retry Control. This field determines the response of the PEX 8111 in Reverse Bridge Mode when a PCI to PCI Express configuration transaction is terminated with a Configuration Request Retry Status. Value Response 00 Retry once after 1 second. If another CRS is received, Target Abort on the PCI bus. 01 Retry 8 times, once per second. If another CRS is received, Target Abort on the PCI bus. 10 Retry once per second until successful completion. 11 Reserved WAKE Out Enable. When set, the WAKEOUT# pin is asserted when the PME# pin is asserted and the link is in the L2 state. This bit is only valid in Forward Bridge mode. Beacon Generate Enable. When set, a beacon is generated when the PME# pin is asserted and the link is in the L2 state. This bit is only valid in Forward Bridge mode. Beacon Detect Enable. When set, a beacon detected while the link is in the L2 state causes the PME Status bit to be set. This bit is only valid in Reverse Bridge mode. CFG Reserved Link State Machine. For internal use only. Reserved MM EE Default RW RW WO 0 RW RW WO 1 RsvdP RsvdP -- 0 RO RO -- 0 RO RO -- -- RW RW WO 0 RW RW WO 0 RW RW WO 0 RW RW WO 0 RsvdP RsvdP -- 0 RO RO -- -- RsvdP RsvdP -- 0 PR EL IM IN AR Y Bits PLX Technology, Inc. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 Table 21-54. 7:0 Description MSI Capability ID. This register specifies the Message Signaled Interrupts Capability ID. Table 21-55. Bits 7:0 0 3:1 6:4 7 8 15:9 CFG RO MM RO EE -- Default 5 (Address 51h; MSINEXT) Message Signaled Interrupts Next Pointer Description MSI Next Pointer. This register points to the first location of the next item in the capabilities linked list. Table 21-56. Bits (Address 50h; MSIID) Message Signaled Interrupts Capability ID CFG RO MM EE Default RW WO 60h MM EE Default (Address 52h; MSICTL) Message Signaled Interrupts Control Description MSI Enable. When set, this bit enables the PEX 8111 to use MSI to request service. When set, virtual interrupt support for internal interrupt sources are disabled for Forward Bridge mode. When set, INTx# outputs are disabled in Reverse Bridge mode. Multiple Message Capable. System software reads this field to determine the number of requested messages. The number of requested messages must be aligned to a power of two (if a function requires three messages, it requests four. The encoding is defined as: Value Number of Messages Requested 000 1 001 2 010 4 011 8 100 16 101 32 110 Reserved 111 Reserved Multiple Message Enable. System software writes to this field to indicate the number of allocated messages (equal to or less than the number of requested messages). The number of allocated messages is aligned to a power of two. The encoding is defined as: Value Number of Messages Requested 000 1 001 2 010 4 011 8 100 16 101 32 110 Reserved 111 Reserved MSI 64-Bit Address Capable. When set, the PEX 8111 is capable of generating a 64-bit message address. Per Vector Masking Capable. This feature is not supported by the PEX 8111, so this bit is forced to 0. Reserved CFG PR EL IM IN AR Y Bits PCI-Compatible Extended Capability Registers PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 RW RW WO 0 RO RO -- 0 RW RW WO 0 RO RW WO 1 (Fwd) 0 (Rev) RO RO -- 0 RsvdP RsvdP -- 0 125 Configuration Registers Table 21-57. 31:2 Description Reserved MSI Address. If the Message Enable bit (bit 0 of the Message Control register) is set, the contents of this register specify the DWORD aligned address for the MSI memory write transaction. Address bits 1 and 0 are driven to zero during the address phase. Table 21-58. Bits 31:0 15:0 31:16 126 CFG RsvdP MM RsvdP EE -- Default 0 RW RW WO 0 (Address 58h; MSIUPPERADDR) Message Signaled Interrupts Upper Address Description MSI Upper Address. This register is optional and is implemented only if the device supports a 64-bit message address (64-bit Address Capable bit in Message Control register set). If the Message Enable bit (bit 0 of the Message Control register) is set, the contents of this register specify the upper 32 bits of a 64-bit message address. If the contents of this register are zero, the PEX 8111 uses the 32-bit address specified by the Message Address register. Table 21-59. Bits (Address 54h; MSIADDR) Message Signaled Interrupts Address CFG RW PR EL IM IN AR Y Bits 1:0 PLX Technology, Inc. MM RW EE WO Default 0 (Address 5Ch; MSIDATA) Message Signaled Interrupts Data Description MSI Data. If the Message Enable bit is set, the message data is driven onto the lower word (AD[15:0]) of the memory write transaction data phase. Reserved CFG MM EE Default RW RW WO 0 RsvdP RsvdP -- 0 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 Table 21-60. 7:0 Description PCI Express Capability ID. This register specifies the PCI Express Capability ID. Table 21-61. Bits 7:0 3:0 7:4 8 13:9 15:14 CFG RO MM RW EE Default -- 10h (Address 61h; PCIEXNEXT) PCI Express Next Pointer Description PCI Express Next Pointer. This register points to the first location of the next item in the capabilities linked list. Table 21-62. Bits (Address 60h; PCIEXID) PCI Express Capability ID CFG RO MM RW EE Default WO 0 (Address 62h; PCIEXCAP) PCI Express Capabilities Description Capability Version. This field indicates the PCI Express capability structure version number. Device/Port Type. This field indicates the type of PCI Express logical device. Device encodings are: Value Device/Port Type 0000 PCI Express Endpoint device 0001 Legacy PCI Express Endpoint Device 0100 Root Port of PCI Express Root Complex 0101 Upstream Port of PCI Express Switch 0110 Downstream Port of PCI Express Switch 0111 PCI Express-to-PCI/PCI-X Bridge 1000 PCI/PCI-X to PCI Express Bridge Others Reserved Slot Implemented. When set, this bit indicates that the PCI Express Link associated with this port is connected to a slot. Interrupt Message Number. If this function is allocated more than one MSI interrupt number, this field is required to contain the offset between the base Message Data and the MSI Message that is generated when any of the status bits in either the Slot Status register or the Root Port Status register of this capability structure are set. Hardware is required to update this field so that it is correct if the number of MSI Messages assigned to the device changes. Reserved CFG PR EL IM IN AR Y Bits PCI-Compatible Extended Capability Registers PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 RO RO MM RW EE WO Default 1 7 (Forward Bridge) RW WO 8 (Reverse Bridge) RO RW WO 0 RO RO -- 0 RsvdP RsvdP -- 0 127 Configuration Registers Table 21-63. 2:0 4:3 5 8:6 11:9 128 (Address 64h; DEVCAP) Device Capabilities Description MAX Payload Size Supported. This field indicates the maximum payload size that the device can support for TLPs. Defined encodings are: Value Max Payload Size 000 128 bytes 001 256 bytes 010 512 bytes 011 1024 bytes 100 2048 bytes 101 4096 bytes 110 Reserved 111 Reserved Since the PEX 8111 only supports a maximum payload size of 128 bytes, this field is hardwired to 0. Phantom Functions Supported. This feature is not supported in the PEX 8111. This field is hardwired to 0. Extended Tag Field Supported. This field indicates the maximum supported size of the Tag field. If clear, a 5-bit Tag field is supported. If set, an 8-bit Tag field is supported. CFG RO Note: 8-bit Tag field support must be enabled by the corresponding control field in the Device Control register. Endpoint L0s Acceptable Latency. This field indicates the acceptable total latency that an Endpoint can withstand due to the transition from L0s state to the L0 state. It is essentially an indirect measure of the internal buffering of the Endpoint. Power management software uses the reported L0s Acceptable Latency number to compare against the L0s exit latencies reported by all components comprising the data path from this Endpoint to the Root Complex Root Port to determine whether Active State Link PM L0s entry can be used with no loss of performance. Defined encodings are: Latency Value 000 Less than 64 ns 001 64 ns to less than 128 ns 010 128 ns to less than 256 ns 011 256 ns to less than 512 ns 100 512 ns to 1 s 101 1 s to less than 2 s 110 2 s to 4 s 111 More than 4 s Endpoint L1 Acceptable Latency. This field indicates the acceptable total latency that an Endpoint can withstand due to the transition from L1 state to the L0 state. It is essentially an indirect measure of the internal buffering of the Endpoint. Power management software uses the report L1 Acceptable Latency number to compare against the L1 exit latencies reported by all components comprising the data path from this Endpoint to the Root Complex Root Port to determine whether Active State Link PM L1 entry can be used with no loss of performance. Defined encodings are: Value Latency 000 Less than 1 s 001 1 s to less than 2 s 010 2 s to less than 4 s 011 4 s to less than 8 s 100 8 s to less than 16 s 101 16 s to less than 32 s 110 32 s to 64 s 111 More than 64 s MM EE Default RO -- 0 RO RO -- 0 RO RW WO 0 RO RW WO 0 RO RW WO 0 PR EL IM IN AR Y Bits PLX Technology, Inc. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 Table 21-63. 12 13 14 17:15 25:18 27:26 31:28 (Address 64h; DEVCAP) Device Capabilities (Cont.) Description Attention Button Present. The PEX 8111 does not support an attention button, so this bit is forced to 0. Attention Indicator Present. The PEX 8111 does not support an attention indicator, so this bit is forced to 0. Power Indicator Present. The PEX 8111 does not support a power indicator, so this bit is forced to 0. Reserved Captured Slot Power Limit Value. Specifies the upper limit on power supplied by slot in combination with the Slot Power Limit Scale value. Power limit (in Watts) is calculated by multiplying the value in this field by the value in the Slot Power Limit Scale field. This value is set by the Set_Slot_Power_Limit message. Captured Slot Power Limit Scale. Specifies the scale used for the Slot Power Limit Value. Range of values: Value Scale 00 1.0x 01 0.1x 10 0.01x 11 0.001x This value is set by the Set_Slot_Power_Limit message. Reserved CFG PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 MM EE Default RO RO -- 0 RO RO -- 0 RO RO -- 0 RsvdP RsvdP -- 0 RO RW WO 0 RO RW WO 0 RsvdP RsvdP -- 0 PR EL IM IN AR Y Bits PCI-Compatible Extended Capability Registers 129 Configuration Registers Table 21-64. 0 1 2 3 4 7:5 130 (Address 68h; DEVCTL) PCI Express Device Control Description Correctable Error Reporting Enable. This bit controls reporting of correctable errors. If an ERR_COR is detected in Forward Bridge mode and this bit is set, an ERR_COR message is sent to the Root Complex. Non-Fatal Error Reporting Enable. This bit controls reporting of non-fatal errors. If a non-fatal error is detected in Forward Bridge mode and this bit is set, an ERR_NONFATAL Message is sent to the Root Complex. Fatal Error Reporting Enable. This bit controls reporting of fatal errors. If a fatal error is detected in Forward Bridge mode and this bit is set, an ERR_FATAL Message is sent to the Root Complex. Unsupported Request Reporting Enable. This bit controls reporting of Unsupported Requests. If an Unsupported Request response is received from the PCI Express in Forward Bridge mode and this bit is set, a non-ERR_FATAL Message is sent to the Root Complex. Enable Relaxed Ordering. If set, the device is permitted to set the Relaxed Ordering bit in the Attributes field of transactions it initiates that do not require strong write ordering. The PEX 8111 does not support relaxed ordering, so this bit is forced to 0. MAX Payload Size. This field sets the maximum TLP payload size for the device. As a receiver, the device must handle TLPs as large as the set value; as transmitter, the device must not generate TLPs exceeding the set value. Permissible values that can be programmed are indicated by the MAX Payload Size Supported field of the Device Capabilities register. Defined encodings are: Value Max Payload Size 000 128 bytes 001 256 bytes 010 512 bytes 011 1024 bytes 100 2048 bytes 101 4096 bytes 110,111 Reserved CFG MM EE Default RW RW WO 0 RW RW WO 0 RW RW WO 0 RW RW WO 0 RO RO -- 0 RW RW WO 0 PR EL IM IN AR Y Bits PLX Technology, Inc. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 Table 21-64. 8 9 10 11 14:12 15 (Address 68h; DEVCTL) PCI Express Device Control (Cont.) Description Extended Tag Field Enable. When clear, the device is restricted to a 5-bit Tag field. When set, this bit enables a device to use an 8-bit Tag field as a requester. Phantom Function Enable. This feature is not supported in the PEX 8111. This field is hardwired to 0. Auxiliary (AUX) Power PM Enable. When set, this bit enables a device to draw AUX power independent of PME AUX power. Devices that require AUX power on legacy operating systems should continue to indicate PME AUX power requirements. AUX power is allocated as requested in the AUX Current field of the Power Management Capabilities register, independent of the PME Enable bit in the Power Management Control/Status register. The PEX 8111 does not support AUX power, so this bit is hardwired to 0. Enable No Snoop. When set, the device is permitted to set the No Snoop bit in the Requester Attributes of transactions it initiates that do not require hardware enforced cache coherency. Setting this bit to 1 should not cause a device to blindly set the No Snoop attribute on all transactions that it initiates. Even when this bit is set to 1, a device may only set the No Snoop attribute on a transaction when it can guarantee that the address of the transaction is not stored in any cache in the system. The PEX 8111 never sets the No Snoop attribute, so this bit is forced to 0. MAX Read Request Size. This field sets the maximum Read Request size for the Device as a Requester. The Device must not generate read requests with size exceeding the set value. Defined encodings are: Value Max Payload Size 000 128 bytes 001 256 bytes 010 512 bytes 011 1024 bytes 100 2048 bytes 101 4096 bytes 110,111 Reserved Bridge Configuration Retry Enable. When clear, the PEX 8111 does not generate completions with Completion Retry Status on behalf of PCI Express to PCI configuration transactions. When set, the PEX 8111 generates completions with Completion Retry Status on behalf of PCI Express to PCI configuration transactions. This occurs after a delay determined by the CRSTIMER register. CFG PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 MM EE Default RW RW WO 0 RO RO -- 0 RO RO -- 0 RO RO -- 0 RW RW WO `b010 RW RW WO 0 PR EL IM IN AR Y Bits PCI-Compatible Extended Capability Registers 131 Configuration Registers Table 21-65. 0 1 2 3 4 5 15:6 132 (Address 6Ah; DEVSTAT) PCI Express Device Status Description Correctable Error Detected. This bit indicates status of correctable errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. Non-Fatal Error Detected. This bit indicates status of non-fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. Fatal Error Detected. This bit indicates status of fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. Unsupported Request Detected. This bit indicates that the device received an Unsupported Request. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. AUX Power Detected. Devices that require AUX power report this bit as set if AUX power is detected by the device. Transactions Pending. Since the PEX 8111 does not generate any non-posted transactions internally, this bit is forced to 0. Reserved CFG MM RW1C RW1C -- 0 RW1C RW1C -- 0 RW1C RW1C -- 0 RW1C RW1C -- 0 RO RO -- 0 RO RO -- 0 RsvdZ RsvdZ -- 0 PR EL IM IN AR Y Bits PLX Technology, Inc. EE Default PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 Table 21-66. 3:0 9:4 11:10 14:12 17:15 23:18 31:24 (Address 6Ch; LINKCAP) Link Capabilities Description Maximum Link Speed. This field indicates the maximum Link speed of the given PCI Express Link. Defined encodings are: Max Link Speed Value 0001 2.5 Gb/s Link Others Reserved Maximum Link Width. This field indicates the maximum width of the given PCI Express Link. Defined encodings are: Value Latency 000000 Reserved 000001 x1 000010 x2 000100 x4 001000 x8 001100 x12 010000 x16 100000 x32 Others Reserved Active State Link PM Support. This field indicates the level of active state power management supported on the given PCI Express Link. Defined encodings are: Value Latency 00 Reserved 01 L0s Entry Supported 10 Reserved 11 L0s and L1 Supported L0s Exit Latency. This field indicates the L0s exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from L0s to L0. Defined encodings are: Value Latency 000 Less than 64 ns 001 64 ns to less than 128 ns 010 128 ns to less than 256 ns 011 256 ns to less than 512 ns 100 512 ns to 1 s 101 1 s to less than 2 s 110 2 s to 4 s 111 More than 4 s L1 Exit Latency. This field indicates the L1 exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from L1 to L0. Defined encodings are: Value Latency 000 Less than 1 s 001 1 s to less than 2 s 010 2 s to less than 4 s 011 4 s to less than 8 s 100 8 s to less than 16 s 101 16 s to less than 32 s 110 32 s to 64 s 111 More than 64 s Reserved Port Number. This field indicates the PCI Express port number for the given PCI Express Link. CFG PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 MM EE Default RO RO -- 1 RO RO -- 1 RO RW WO `b11 RO RW WO `b100 RO RW WO `b100 RsvdP RsvdP -- 0 RO RW WO 0 PR EL IM IN AR Y Bits PCI-Compatible Extended Capability Registers 133 Configuration Registers Table 21-67. 1:0 2 3 4 5 6 7 15:8 134 (Address 70h; LINKCTL) Link Control Description Active State Link PM Control. This field controls the level of active state PM supported on the given PCI Express Link. Defined encodings are: PM Control Value 00 Disabled 01 L0s Entry Supported 10 Reserved 11 L0s and L1 Entry Supported Note: "L0s Entry Enabled" indicates the Transmitter entering L0s. Reserved Read Completion Boundary (RCB) Control. When clear, the read completion boundary is 64 bytes. When set, the read completion boundary is 128 bytes. Link Disable. This bit disables the Link when set to 1. This bit is only valid in Reverse Bridge mode in the PEX 8111. Writes to this bit are immediately reflected in the value read from the bit, regardless of actual Link state. Retrain Link. This bit initiates Link retraining when set. It is only valid in Reverse Bridge mode in the PEX 8111. This bit always returns 0 when read. Common Clock Configuration. This bit when set indicates that this component and the component at the opposite end of this Link are operating with a distributed common reference clock. A value of 0 indicates that this component and the component at the opposite end of this Link are operating with asynchronous reference clock. Components utilize this common clock configuration information to report the correct L0s and L1 Exit Latencies. Extended Sync. This bit when set forces extended transmission of FTS ordered sets in FTS and extra TS2 at exit from L1 prior to entering L0. This mode provides external devices monitoring the link time to achieve bit and symbol lock before the link enters L0 state and resumes communication. Reserved CFG MM EE Default RW RW WO 0 RsvdP RsvdP -- 0 RW (Fwd) RO (Rev) RW WO 1 PR EL IM IN AR Y Bits PLX Technology, Inc. RO (Fwd) RW (Rev) RO (Fwd) RW (Rev) -- (Fwd) WO (Rev) 0 RO (Fwd) RW (Rev) RO (Fwd) RW (Rev) -- (Fwd) WO (Rev) 0 RW RW WO 0 RW RW WO 0 RsvdP RsvdP -- 0 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 Table 21-68. 3:0 9:4 10 11 12 15:13 (Address 72h; LINKSTAT) Link Status Description Link Speed. This field indicates the negotiated Link speed of the given PCI Express Link. Defined encodings are: Max Link Speed Value 0001 2.5 Gb/s Link Others Reserved Negotiated Link Width. This field indicates the negotiated width of the given PCI Express Link. Defined encodings are: Value Width 000000 Reserved 000001 x1 000010 x2 000100 x4 001000 x8 001100 x12 010000 x16 100000 x32 Others Reserved Link Training Error. This read-only bit indicates that a Link training error occurred. This field is only applicable in Reverse Bridge mode. This bit is cleared by hardware upon successful training of the Link to the L0 Link state. Link Training. This read-only bit indicates that Link training is in progress; hardware clears this bit once Link training is complete. This field is only applicable in Reverse Bridge mode. Slot Clock Configuration. This bit indicates that the component uses the same physical reference clock that the platform provides on the connector. If the device uses an independent clock irrespective of the presence of a reference on the connector, this bit must be clear. Reserved CFG PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 MM EE Default RO RO -- 1 RO RO -- 1 RO RO -- 0 RO RO -- 0 HwInit RW WO 0 RsvdZ RsvdZ -- 0 PR EL IM IN AR Y Bits PCI-Compatible Extended Capability Registers 135 Configuration Registers Table 21-69. 0 1 2 3 4 5 6 14:7 16:15 18:17 31:19 136 (Address 74h; SLOTCAP) Slot Capabilities Description Attention Button Present. The PEX 8111 does not support the Attention Button, so this bit is forced to 0. Power Controller Present. The PEX 8111 does not support a Power Controller, so this bit is forced to 0. MRL Sensor Present. The PEX 8111 does not support an MRL Sensor, so this bit is forced to 0. Attention Indicator Present. The PEX 8111 does not support the Attention Indicator, so this bit is forced to 0. Power Indicator Present. The PEX 8111 does not support the Power Indicator, so this bit is forced to 0. Hot-Plug Surprise. The PEX 8111 does not support Hot-Plug Surprise, so this bit is forced to 0. Hot-Plug Capable. The PEX 8111 does not support Hot-Plug, so this bit is forced to 0. Slot Power Limit Value. In combination with the Slot Power Limit Scale value, specifies the upper limit on power supplied by the slot. The Power limit (in Watts) is calculated by multiplying the value in this field by the value in the Slot Power Limit Scale field. Writes to this register cause the PEX 8111 to send the Set Slot Power Limit Message downstream in Reverse Bridge mode. This field is only valid in Reverse Bridge mode. Slot Power Limit Scale. This field specifies the scale used for the Slot Power Limit Value. Writes to this register cause the PEX 8111 to send the Set Slot Power Limit Message downstream in Reverse Bridge mode. This field is only valid in Reverse Bridge mode. Defined encodings are: Scale Value 00 1.0x 01 0.1x 10 0.01x 11 0.001x Reserved Physical Slot Number. This field is not supported by the PEX 8111, and is forced to 0. CFG MM EE Default RO RO -- 0 RO RO -- 0 RO RO -- 0 RO RO -- 0 RO RO -- 0 RO RO -- 0 RO RO -- 0 RO RW WO 0 RO RW WO `b00 RsvdP RsvdP -- 0 RO RO -- 0 PR EL IM IN AR Y Bits PLX Technology, Inc. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 Table 21-70. 0 1 2 3 4 5 10 7:6 9:8 15:11 Description Attention Button Pressed Enable. The PEX 8111 does not support the Attention Button, so this bit is ignored. Power Fault Detected Enable. The PEX 8111 does not support the Power Fault Detected feature, so this bit is ignored. MRL Sensor Changed Enable. The PEX 8111 does not support an MRL Sensor Changed feature, so this bit is ignored. Presence Detect Changed Enable. The PEX 8111 does not support the Presence Detect Changed feature, so this bit is ignored. Command Completed Interrupt Enable. The PEX 8111 does not support the Command Completed Interrupt, so this bit is ignored. Hot Plug Interrupt Enable. The PEX 8111 does not support the Hot-Plug Interrupt, so this bit is ignored. Power Controller Control. The PEX 8111 does not support a Power Controller, so this bit is ignored. Attention Indicator Control. The PEX 8111 does not support the Attention Indicator, so this field is ignored. Power Indicator Control. The PEX 8111 does not support the Power Indicator, so this field is ignored. Reserved Table 21-71. Bits 0 1 2 3 4 5 6 15:7 (Address 78h; SLOTCTL) Slot Control CFG MM EE Default RW RW WO 0 RW RW WO 0 RW RW WO 0 RW RW WO 0 RW RW WO 0 RW RW WO 0 RW RW WO 0 RW RW WO 0 RW RW WO 0 RsvdP RsvdP -- 0 PR EL IM IN AR Y Bits PCI-Compatible Extended Capability Registers (Address 7Ah; SLOTSTAT) Slot Status Description Attention Button Pressed. The PEX 8111 does not support the Attention Button, so this bit is forced to 0. Power Fault Detected. The PEX 8111 does not support the Power Fault feature, so this bit is forced to 0. MRL Sensor Changed. The PEX 8111 does not support an MRL Sensor Changed feature, so this bit is forced to 0. Presence Detect Changed. The PEX 8111 does not support the Presence Detect Changed feature, so this bit is forced to 0. Command Completed. The PEX 8111 does not support the Command Completed Interrupt, so this bit is forced to 0. MRL Sensor State. The PEX 8111 does not support the MRL Sensor feature, so this bit is forced to 0. Presence Detect State. The PEX 8111 does not support the Presence Detect feature, so this field is forced to 1. Reserved PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 CFG MM EE Default RO RO -- 0 RO RO -- 0 RO RO -- 0 RO RO -- 0 RO RO -- 0 RO RO -- 0 RO RO -- 1 RsvdP RsvdP -- 0 137 Configuration Registers Table 21-72. 0 1 2 3 31:4 Description System Error on Correctable Error Enable. When set, a system error (SERR#) is generated if an ERR_COR is reported by any of the devices in the hierarchy associated with this Root Port, or by the Root Port itself. System Error on Non-Fatal Error Enable. When set, a system error (SERR#) is generated if an ERR_NONFATAL is reported by any of the devices in the hierarchy associated with this Root Port, or by the Root Port itself. System Error on Fatal Error Enable. When set, a system error (SERR#) is generated if an ERR_FATAL is reported by any of the devices in the hierarchy associated with this Root Port, or by the Root Port itself. PME Interrupt Enable. When set, enables PME interrupt generation upon receipt of a PME message as reflected in the PME Status register bit. A PME interrupt is also generated if the PME Status register bit is set when this bit is set from a cleared state. Reserved Table 21-73. Bits 15:0 16 17 31:18 138 (Address 7Ch; ROOTCTL) Root Control (Reverse Bridge Mode) CFG MM EE Default RW RW WO 0 RW RW WO 0 RW RW WO 0 RW RW WO 0 RsvdP RsvdP -- 0 PR EL IM IN AR Y Bits PLX Technology, Inc. (Address 80h; ROOTSTAT) Root Status (Reverse Bridge Mode) Description PME Requester ID. This field indicated the PCI Requester ID of the last PME requester. PME Status. This bit indicates that PME was asserted by the Requester ID indicated in the PME Requester ID field. Subsequent PMEs are kept pending until the status register is cleared by software by writing a 1. PME Pending. This read-only bit indicates that another is pending when the PME Status bit is set. When the PME Status bit is cleared by software, the PME is delivered by hardware by setting the PME Status bit again and updating the Requester ID appropriately. The PME pending bit is cleared by hardware if no more PMEs are pending. Reserved CFG MM EE Default RO RO -- -- RW1C RW1C -- 0 RO RO -- -- RsvdP RsvdP -- 0 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 PCI Express Extended Capability Registers 21.8 PCI Express Extended Capability Registers 21.8.1 PCI Express Power Budgeting Registers Table 21-74. 15:0 19:16 31:20 Description PCI Express Extended Capability ID. This field is a PCI-SIG defined ID number that indicates the nature and format of the extended capability. Capability Version. This field is a PCI-SIG defined version number that indicates the version of the capability structure present. Next Capability Offset. This field contains the offset to the next PCI Express capability structure or 000h if no other items exist in the linked list of capabilities. Table 21-75. Bits 7:0 31:8 (Address 100h; PWRCAPHDR) Power Budgeting Capability Header PR EL IM IN AR Y Bits CFG MM EE Default RO RW WO 4 RO RW WO 1 RO RW WO 'h110 (Address 104h; PWRDATASEL) Power Budgeting Data Select Description Data Select Register. This register indexes the Power Budgeting Data reported through the Data register and selects the DWORD of Power Budgeting Data that should appear in the Data register. The PEX 8111 supports values from 0 to 31 for this field. For values greater than 31, a value of 0 is returned when the PWRDATA register is read. Reserved PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 CFG MM EE Default RW RW WO 0 RsvdP RsvdP -- 0 139 Configuration Registers PLX Technology, Inc. This register returns the DWORD of Power Budgeting Data selected by the Data Select register. If the Data Select register contains a value greater than or equal to the number of operating conditions for which the device provides power information, this register should return all zeros. The PEX 8111 supports 32 operating conditions. Table 21-76. 7:0 9:8 12:10 14:13 17:15 20:18 31:21 140 Description Base Power. Specifies in watts the base power value in the given operating condition. This value must be multiplied by the data scale to produce the actual power consumption value. Data Scale. Specifies the scale to apply to the Base Power value. The power consumption of the device is determined by multiplying the contents of the Base Power register field with the value corresponding to the encoding return by this field. Defined encodings are: Value Scale Factor 00 1.0x 01 0.1x 10 0.01x 11 0.001x PM Sub State. Specifies the power management sub state of the operating condition being described. Defined encodings are: Value Sub State 000 Default Sub State Others Device Specific Sub State PM State. Specifies the power management state of the operating condition being described. A device returns 11b in this field and Aux or PME Aux in the Type field to specify the D3cold PM State. An encoding of 11b along with any other Type field value specifies the D3hot state. Defined encodings are: Value PM State 00 D0 01 D1 10 D2 11 D3 PM Type. Specifies the type of the operating condition being described. Defined encodings are: PM Type Value 000 PME Aux 001 Auxiliary 010 Idle 011 Sustained 111 Maximum Other Reserved Power Rail. Specifies the power rail of the operating condition being described. Defined encodings are: Value Power Rail 000 Power (12V) 001 Power (3.3V) 010 Power (1.8V) 111 Thermal Other Reserved Reserved CFG MM EE Default RO RW WO 0 RO RW WO 0 RO RW WO 0 RO RW WO 0 RO RW WO 0 RO RW WO 0 RsvdP RsvdP -- 0 PR EL IM IN AR Y Bits (Address 108h; PWRDATA) Power Budgeting Data PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 Table 21-77. 0 31:1 Description System Allocated. When set, this bit indicates that the power budget for the device is included within the system power budget. Reported Power Budgeting Data for this device should be ignored by software for power budgeting decision if this bit is set. Reserved 21.8.2 15:0 19:16 31:20 31:0 31:0 EE Default RO RW WO 0 RsvdP RsvdP -- 0 MM EE Default CFG RO RO -- 3 RO RO -- 1 RO RO -- 0 (Address 114h; SERNUMLOW) Serial Number Low Description PCI Express Device Serial Number. This field contains the lower DWORD of the IEEE defined 64-bit extended unique identifier. This identifier includes a 24-bit company id value assigned by the IEEE registration authority and a 40-bit extension identifier assigned by the manufacturer. Table 21-80. Bits MM (Address 110h; SERCAPHDR) Serial Number Capability Header Description PCI Express Extended Capability ID. This field is a PCI-SIG defined ID number that indicates the nature and format of the extended capability. Capability Version. This field is a PCI-SIG defined version number that indicates the version of the capability structure present. Next Capability Offset. This field contains the offset to the next PCI Express capability structure or 000h if no other items exist in the linked list of capabilities. Table 21-79. Bits CFG PCI Express Serial Number Registers Table 21-78. Bits (Address 10Ch; PWRBUDCAP) Power Budget Capability PR EL IM IN AR Y Bits PCI Express Serial Number Registers CFG RO MM RW EE WO Default 0 (Address 118h; SERNUMHI) Serial Number Hi Description PCI Express Device Serial Number. This field contains the upper DWORD of the IEEE defined 64-bit extended unique identifier. This identifier includes a 24-bit company id value assigned by the IEEE registration authority and a 40-bit extension identifier assigned by the manufacturer. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 CFG RO MM RW EE WO Default 0 141 Configuration Registers 21.9 Main Control Registers Table 21-81. 3:0 4 5 31:6 142 (Address 1000h; DEVINIT) Device Initialization Description PCLKO Clock Frequency. This field controls the frequency of the PCLKO pin. When set to 0, the clock is stopped. Non-zero values represent divisors of the 100 MHz clock. The default value is 3, representing a frequency of 66 MHz. Value Frequency (MHz) 0000 0 0001 100 0010 50 0011 33.3/66 (If M66EN is high, then PCLKO frequency is 66 MHz) 0100 25 0101 20 0110 16.7 0111 14.3 1000 12.5 1001 11.1 1010 10 1011 9.1 1100 8.3 1101 7.7 1110 7.1 1111 6.7 PCI Express Enable. When clear, all configuration accesses to the PEX 8111 result in a completion status of: Configuration Request Retry Status. When set, the PEX 8111 responds normally to PCI Express configuration accesses. If no valid EEPROM is detected, this bit is automatically set. PCI Enable. When clear, all PCI accesses to the PEX 8111 result in a Target Retry response. When set, the PEX 8111 responds normally to PCI accesses. If no valid EEPROM is detected, this bit is automatically set. Reserved PR EL IM IN AR Y Bits PLX Technology, Inc. Access Default RW 3 RW 0 RW 0 RsvdP 0 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 Table 21-82. 7:0 15:8 16 17 18 19 20 21 22 24:23 30:25 31 Description EEPROM Write Data. This field determines the byte written to the EEPROM when the EEPROM Byte Write Start bit is set. This field can represent an opcode, address, or data being written to the EEPROM. EEPROM Read Data. This field determines the byte read from the EEPROM when the EEPROM Byte Read Start bit is set. EEPROM Byte Write Start. When set, the value in the EEPROM Write Data field is written to the EEPROM. This bit is automatically cleared when the write operation is complete. EEPROM Byte Read Start. When set, a byte is read from the EEPROM, and can be accessed using the EEPROM Read Data field. This bit is automatically cleared when the read operation is complete. EEPROM Chip Select Enable. When set, the EEPROM chip select is enabled. EEPROM Busy. When set, the EEPROM controller is busy performing a byte read or write operation. An interrupt can be generated whenever this bit goes false. EEPROM Valid. An EEPROM with 'h5A in the first byte has been detected. EEPROM Present. This bit is set if the EEPROM controller determines that an EEPROM is connected to the PEX 8111. EEPROM Chip Select Active. This bit is set if the chip select pin to the EEPROM is active. The chip select can be active across multiple byte operations. EEPROM Address Width. This field reports the addressing width of the installed EEPROM. If the addressing width cannot be determined, a zero is returned. Value Address Width 00 undetermined 01 1 byte 10 2 byte 11 3 byte Reserved EEPROM Reload. Writing a 1 to this bit causes the EEPROM controller to perform an initialization sequence. Configuration registers and shared memory are loaded from the EEPROM. Reading this bit returns a 0 while the initialization is in progress, and a 1 when it is complete. Table 21-83. Bits 2:0 31:3 (Address 1004h; EECTL) EEPROM Control PR EL IM IN AR Y Bits Main Control Registers Access Default RW 0 RO -- RW 0 RW 0 RW 0 RO 0 RO -- RO -- RO -- RO -- RsvdP 0 RW 0 Access Default RW 0 RsvdP 0 (Address 1008h; EECLKFREQ) EEPROM Clock Frequency Description EEPROM Clock Frequency. This field controls the frequency of the EECLK pin. Frequency Value 000 2 MHz 001 5 MHz 010 8.3 MHz 011 10 MHz 100 12.5 MHz 101 16.7 MHz 110 25 MHz 111 Reserved Reserved PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 143 Configuration Registers Table 21-84. 0 3:1 4 5 6 7 15:8 23:16 24 25 31:26 144 (Address 100Ch; PCICTL) PCI Control Description PCI Multi-Level Arbiter. When clear, all PCI requesters are placed into a single-level round-robin arbiter, each with equal access to the PCI bus. When set, a 2 level arbiter is selected. PCI Arbiter Park Select. This field determines which PCI master controller is granted the PCI bus when there are no pending requests. Value Park 000 Last Grantee 001 PCI Express Bus 010 Reserved 011 Reserved 100 External Requester 0 101 External Requester 1 110 External Requester 2 111 External Requester 3 Bridge Mode. This bit reflects the status of the FORWARD pin. When low, the device operates as a Reverse Bridge (PCI to PCI Express). When high, the device operates as a Forward Bridge (PCI Express to PCI). PCI External Arbiter. This bit reflects the state of the EXTARB pin. When low, the PEX 8111 enables its internal arbiter. It then expects external requests on REQ[3:0]# and issues bus grants on GNT[3:0]#. When high, the PEX 8111 asserts REQ[0]# and expects GNT[0]# from an external arbiter. Locked Transaction Enable. When clear, PCI Express Memory Read Lock requests are completed with UR status, and the PCI LOCK# pin is not driven in Forward Bridge mode. In Reverse Bridge mode, the PCI LOCK# pin is ignored. When set, Locked Transactions are propagated through the bridge from the primary to secondary bus. M66EN. This bit reflects the state of the M66EN pin. When low, the PEX 8111 PCI bus is operating at 33 MHz. When high, the PEX 8111 PCI bus is operating at 66 MHz. PCI to PCI Express Retry Count. This field determines how many times to retry a PCI Type 1 Configuration transaction to PCI Express before aborting the transfer. Values range from 0 to 255. A value of 0 indicates that the transaction is retried forever. A value of 255 selects a retry count of 224. When the timer times out, a Master Abort is returned to the PCI bus. This field is only valid in Reverse Bridge mode when the PCI Express link is down. PCI Express to PCI Retry Count. This field determines how many times to retry a PCI Express to PCI transaction before aborting the transfer. Values range from 0 to 255. A value of 0 indicates that the transaction is retried forever. A value of 255 selects a retry count of 224. Memory Read Line Enable. When clear, the PEX 8111 issues a Memory Read command for transactions that do not start on a cache boundary. When set, a Memory Read Line command is issued if a transaction is not aligned to a cache boundary, and the burst transfer size is at least one cache line of data. The PCI burst is stopped at the cache line boundary if the burst transfer size is less than one cache line of data or if a Memory Read Multiple command can be started. Memory Read Multiple Enable. When clear, the PEX 8111 issues a Memory Read command for transactions that start on a cache boundary. When set, a Memory Read Multiple command is issued if a transaction is aligned to a cache boundary, and the burst transfer size is at least one cache line of data. The PCI burst continues if the burst transfer size remains greater than or equal to one cache line of data. Reserved PR EL IM IN AR Y Bits PLX Technology, Inc. Access Default RW 0 RW 0 RO -- RO -- RW 0 RO 0 RW 'hFF RW 0 RW 1 RW 1 RsvdP 0 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 Table 21-85. 0 1 2 3 4 5 6 7 30:8 31 Description EEPROM Done Interrupt Enable. When set, this bit enables a PCI Express interrupt to be generated when an EEPROM read or write transaction completes. GPIO Interrupt Enable. When set, this bit enables a PCI Express interrupt to be generated when an interrupt is active from one of the GPIO pins. Reserved PCI Express to PCI Retry Interrupt Enable. When set, this bit enables a PCI Express interrupt to be generated when the PCI Express to PCI retry count has been reached. Mailbox 0 Interrupt Enable. When set, this bit enables a PCI Express interrupt to be generated when Mailbox 0 is written. Mailbox 1 Interrupt Enable. When set, this bit enables a PCI Express interrupt to be generated when Mailbox 1 is written. Mailbox 2 Interrupt Enable. When set, this bit enables a PCI Express interrupt to be generated when Mailbox 2 is written. Mailbox 3 Interrupt Enable. When set, this bit enables a PCI Express interrupt to be generated when Mailbox 3 is written. Reserved PCI Express Internal Interrupt Enable. When set, this bit enables a PCI Express interrupt to be generated as a result of an internal PEX 8111 interrupt source. The internal interrupt is serviced as either a Message Signaled Interrupt (MSI) or a virtual wire interrupt. Table 21-86. Bits 0 1 2 3 4 5 6 7 8 30:9 31 (Address 1010h; PCIEIRQENB) PCI Express Interrupt Request Enable PR EL IM IN AR Y Bits Main Control Registers Access Default RW 0 RW 0 RsvdP 0 RW 0 RW 0 RW 0 RW 0 RW 0 RsvdP 0 RW 1 (Fwd) 0 (Rev) Access Default RW 0 RW 0 RsvdP 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RsvdP 0 RW 0 (Fwd) 1 (Rev) (Address 1014h; PCIIRQENB) PCI Interrupt Request Enable Description EEPROM Done Interrupt Enable. When set, this bit enables a PCI interrupt to be generated when an EEPROM read or write transaction completes. GPIO Interrupt Enable. When set, this bit enables a PCI interrupt to be generated when an interrupt is active from one of the GPIO pins. Reserved PCI Express to PCI Retry Interrupt Enable. When set, this bit enables a PCI interrupt to be generated when the PCI Express to PCI retry count has been reached. Mailbox 0 Interrupt Enable. When set, this bit enables a PCI interrupt to be generated when Mailbox 0 is written. Mailbox 1 Interrupt Enable. When set, this bit enables a PCI interrupt to be generated when Mailbox 1 is written. Mailbox 2 Interrupt Enable. When set, this bit enables a PCI interrupt to be generated when Mailbox 2 is written. Mailbox 3 Interrupt Enable. When set, this bit enables a PCI interrupt to be generated when Mailbox 3 is written. Unsupported Request Interrupt Enable. When set, this bit enables a PCI interrupt to be generated when an Unsupported Request Completion response is received from the PCI Express. Reserved PCI Internal Interrupt Enable. When set, this bit enables a PCI interrupt to be generated as a result of an internal PEX 8111 interrupt source. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 145 Configuration Registers Table 21-87. 0 1 2 3 4 5 6 7 8 31:9 Description EEPROM Done Interrupt. This bit is set when an EEPROM read or write transaction completes. Writing a 1 clears this status bit. GPIO Interrupt. This bit conveys the interrupt status for the four GPIO pins. When set, the GPIO Status register should be read to determine the cause of the interrupt. This bit is set independently of the interrupt enable bit. Reserved PCI Express to PCI Retry Interrupt. This bit is set when the PCI Express to PCI retry count has been reached. Writing a 1 clears this status bit. Mailbox 0 Interrupt. This bit is set when Mailbox 0 is written. Writing a 1 clears this bit. Mailbox 1 Interrupt. This bit is set when Mailbox 1 is written. Writing a 1 clears this bit. Mailbox 2 Interrupt. This bit is set when Mailbox 2 is written. Writing a 1 clears this bit. Mailbox 3 Interrupt. This bit is set when Mailbox 3 is written. Writing a 1 clears this bit. Unsupported Request Interrupt. This bit is set when an Unsupported Request Completion is received from the PCI Express. Writing a 1 clears this bit Reserved Table 21-88. Bits 7:0 15:8 23:16 31:24 146 (Address 1018h; IRQSTAT) Interrupt Request Status PR EL IM IN AR Y Bits PLX Technology, Inc. Access Default RW1C 0 RO 0 RsvdP 0 RW1C 0 RW1C 0 RW1C 0 RW1C 0 RW1C 0 RW1C 0 RsvdZ 0 (Address 101Ch; POWER) Power Register Description Power Compare 0. This field specifies the power required for this device and any downstream PCI devices in Forward Bridge mode. It is compared with the Captured Slot Power Limit Value field in the DEVCAP register. If the Captured Slot Power Limit Value is greater than or equal to this field, the PWR_OK pin is asserted. This field is used when the Captured Slot Power Limit Scale field is 00 (scale = 1.0x). Power Compare 1. This field specifies the power required for this device and any downstream PCI devices in Forward Bridge mode. It is compared with the Captured Slot Power Limit Value field in the DEVCAP register. If the Captured Slot Power Limit Value is greater than or equal to this field, the PWR_OK pin is asserted. This field is used when the Captured Slot Power Limit Scale field is 01 (scale = 0.1x). Power Compare 2. This field specifies the power required for this device and any downstream PCI devices in Forward Bridge mode. It is compared with the Captured Slot Power Limit Value field in the DEVCAP register. If the Captured Slot Power Limit Value is greater than or equal to this field, the PWR_OK pin is asserted. This field is used when the Captured Slot Power Limit Scale field is 10 (scale = 0.01x). Power Compare 3. This field specifies the power required for this device and any downstream PCI devices in Forward Bridge mode. It is compared with the Captured Slot Power Limit Value field in the DEVCAP register. If the Captured Slot Power Limit Value is greater than or equal to this field, the PWR_OK pin is asserted. This field is used when the Captured Slot Power Limit Scale field is 11 (scale = 0.001x). Access Default RW 0 RW 0 RW 0 RW 0 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 Table 21-89. 0 1 2 3 4 5 6 7 8 9 10 11 12 31:13 (Address 1020h; GPIOCTL) General Purpose I/O Control Description GPIO0 Data. When programmed as an output, values written to this bit appear on the GPIO0 pin. Reading this bit returns the value that was previously written. When programmed as an input, reading this bit returns the value present on the GPIO0 pin. GPIO1 Data. When programmed as an output, values written to this bit appear on the GPIO1 pin. Reading this bit returns the value that was previously written. When programmed as an input, reading this bit returns the value present on the GPIO1 pin. GPIO2 Data. When programmed as an output, values written to this bit appear on the GPIO2 pin. Reading this bit returns the value that was previously written. When programmed as an input, reading this bit returns the value present on the GPIO2 pin. GPIO3 Data. When programmed as an output, values written to this bit appear on the GPIO3 pin. Reading this bit returns the value that was previously written. When programmed as an input, reading this bit returns the value present on the GPIO3 pin. GPIO0 Output Enable. When clear, the GPIO0 pin is an input. When set, the GPIO0 pin is an output. GPIO1 Output Enable. When clear, the GPIO1 pin is an input. When set, the GPIO1 pin is an output. GPIO2 Output Enable. When clear, the GPIO2 pin is an input. When set, the GPIO2 pin is an output. GPIO3 Output Enable. When clear, the GPIO3 pin is an input. When set, the GPIO3 pin is an output. GPIO0 Interrupt Enable. When set, changes on the GPIO0 pin (when programmed as an input), are enabled to generate an interrupt. GPIO1 Interrupt Enable. When set, changes on the GPIO1 pin (when programmed as an input), are enabled to generate an interrupt. GPIO2 Interrupt Enable. When set, changes on the GPIO2 pin (when programmed as an input), are enabled to generate an interrupt. GPIO3 Interrupt Enable. When set, changes on the GPIO3 pin (when programmed as an input), are enabled to generate an interrupt. LTSSM Output Enable. When set, the lower four bits of the LTSSM state machine are output on the GPIO pins. Reserved PR EL IM IN AR Y Bits Main Control Registers PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 Access Default RW 0 RW 0 RW 0 RW 0 RW 1 RW 1 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RsvdP 0 147 Configuration Registers Table 21-90. 0 1 2 3 31:4 Description GPIO0 Interrupt. This bit is set when the state of the GPIO0 pin changes and the pin is programmed as an input. Writing a 1 clears this bit. GPIO1 Interrupt. This bit is set when the state of the GPIO1 pin changes and the pin is programmed as an input. Writing a 1 clears this bit. GPIO2 Interrupt. This bit is set when the state of the GPIO2 pin changes and the pin is programmed as an input. Writing a 1 clears this bit. GPIO3 Interrupt. This bit is set when the state of the GPIO3 pin changes and the pin is programmed as an input. Writing a 1 clears this bit. Reserved Table 21-91. Bits 31:0 31:0 Bits 31:0 Bits 31:0 148 RW1C 0 RW1C 0 RW1C 0 RW1C 0 RsvdZ 0 Access Default RW 'hFEED FACE Access Default RW 0 Access Default (Address 1038h; MAILBOX 2) Mailbox 2 Description Mailbox Data. This register can be written or read from the PCI Express or PCI. Interrupts can be generated to either of the buses when this register is written. Table 21-94. Default (Address 1034h; MAILBOX 1) Mailbox 1 Description Mailbox Data. This register can be written or read from the PCI Express or PCI. Interrupts can be generated to either of the buses when this register is written. Table 21-93. Access (Address 1030h; MAILBOX 0) Mailbox 0 Description Mailbox Data. This register can be written or read from the PCI Express or PCI. Interrupts can be generated to either of the buses when this register is written. Table 21-92. Bits (Address 1024h; GPIOSTAT) General Purpose I/O Status PR EL IM IN AR Y Bits PLX Technology, Inc. RW 0 (Address 103Ch; MAILBOX 3) Mailbox 3 Description Mailbox Data. This register can be written or read from the PCI Express or PCI. Interrupts can be generated to either of the buses when this register is written. Access Default RW 0 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 Table 21-95. Bits 15:0 31:18 Main Control Registers (Address 1040h; CHIPREV) Chip Silicon Revision Description Chip Revision. This register returns the current silicon revision number of the PEX 8111. Reserved Note: Table 21-96. 0 1 2 3 31:4 RO RsvdP Default Current Revision 0 CHIPREV is the silicon revision, encoded as a 4-digit BCD value. The value of CHIPREV for the first release of the chip is 0100h. The least-significant digit is incremented for mask changes, and the most-significant digit is incremented for major revisions. Address 1044h; DIAG) Diagnostic Control Description Fast Times. When set, internal timers and counters operate at a fast speed for factory chip testing. Force PCI Interrupt. When set, this bit forces the PCI INTx# interrupt pin to be asserted. The particular INTx# pin that is asserted is determined by the PCIINTPIN register. This bit is only effective if the Interrupt Disable bit of the PCICMD register is low. Force PCI SERR. When set, this bit forces the PCI SERR# interrupt pin to be asserted if the SERR# Enable bit in the PCI Command register is set (Reverse Bridge mode). In Forward Bridge mode, the Secondary SERR Enable in the Bridge Control register must be set. Force PCI Express Interrupt. When set, this bit forces an interrupt to the PCI Express host using Message Signaled Interrupts or virtual INTx# interrupts. Reserved PR EL IM IN AR Y Bits Access PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 Access Default RW 0 RW 0 RW 0 RW 0 RsvdP 0 149 Configuration Registers Table 21-97. 7:0 8 9 10 11 12 13 14 15 16 17 31:18 Description CFG_NUM_FTS. Forced NUM_FTS signal. NUM_FTS stands for number of Fast Training sequence (0 - 255). Read PCI Express Base Specification 1.0a, section 4.2.4.3, for detailed information. CFG_ACK_FMODE. PCI Express core ACK_DLLP sending interval mode. 0: Core hardware uses own interval value 1: Core hardware uses CFG_ACK_COUNT as interval value. CFG_TO_FMODE. PCI Express core Timeout detection mode for replay timer. 0: Core hardware uses own timer value. 1: Core hardware uses CFG_TO_COUNT as timer value CFG_PORT_DISABLE. When set, the SERDES in PCI Express core is disabled. This allows endpoint to disable the PCI Express connection when power up or before the configuration is completed. CFG_RCV_DETECT. This signal is asserted when the PCI Express core establishes the PCI Express connection. CFG_LPB_MODE. Link Loopback mode. CFG_PORT_MODE. When set, Link core is configured as downstream port (Root Complex). When clear, Link core is configured as upstream port (endpoint). Reserved CFG_ECRC_GEN_ENABLE. When set, link is allowed generate ECRC. The PEX 8111 does not support ECRC, so this bit should be set to 0. TLB_CPLD_NOSUCCESS_MALFORM_ENABLE. When set, completion received when completion timeout expired is treated as a malformed TLB and is discarded. When clear, received completion is kept. Scrambler Disable. When clear, data scrambling is enabled. When set, data scrambling is disabled. This bit should only be set for testing and debugging. Reserved Table 21-98. Bits 20:0 30:21 31 15:0 31:16 150 Access Default RW 'h20 RW 0 RW 0 RW 0 RO 0 RW 0 RW F(0) R(1) RsvdP 0 RW 0 RW 1 RW 0 RsvdP 'h20 Access Default RW 'hD4 RW 0 RsvdP 0 (Address 104Ch; TLPCFG1) TLP Controller Configuration 1 Description CFG_TO_COUNT. PCI Express core replay timer timeout value if CFG_TO_FMODE is set to 1. CFG_ACK_COUNT. PCI Express core ACK DLLP sending interval value if CFG_ACK_MODE is set to 1. Reserved Table 21-99. Bits (Address 1048h; TLPCFG0) TLP Controller Configuration 0 PR EL IM IN AR Y Bits PLX Technology, Inc. (Address 1050h; TLPCFG2) TLP Controller Configuration 2 Description CFG_COMPLETER_ID0. Bits [15:8]: Bus number Bits [7:3]: Device number Bits [2:0]: Function number When TLB0_TRANS is asserted with Type 0 Configuration Cycle, this signal latches CFG_TLB0_BUS_NUMBER[7:0] and CFG_TLB0_DEV_NUMBER[4:0] into corresponding bits. Reserved Access Default RW 0 RsvdP 0 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 Table 21-100. Main Control Registers (Address 1054h; TLPTAG) TLP Controller Tag Bits 7:0 15:8 23:16 31:24 Description TAG BME1. Tag field for message request. TAG ERM. Tag field for Error Manager. TAG PME. Tag field for Power Manager. Reserved Table 21-101. Access Default RW 0 RW 0 RW 0 RsvdP 0 Default 'h6A4 (M66EN low) 'hA2C2A (M66EN high 'h4 (M66EN low) 'h8 (M66EN high) 0 (Address 1058h; TLPTIMELIMIT0) TLP Controller Time Limit 0 Description BME_COMPLETION_TIMEOUT_LIMIT. Bus master engine completion timeout in units of PCI clocks. The default value produces a 10 ms timeout. Access RW 27:24 L2L3_PWR_REMOVAL_TIME_LIMIT. This value determines the amount of time before power is removed after entering the L2 state. This value should be at least 100 ns. This field has units of PCI clocks. RW 31:28 Reserved RsvdP Table 21-102. Bits 10:0 31:11 PR EL IM IN AR Y Bits 23:0 (Address 105Ch; TLPTIMELIMIT1) TLP Controller Time Limit 1 Description ASPM_LI_DLLP_INTERVAL_TIME_LIMIT. This field determines the time interval between two consecutive PM_ACTIVE_STATE_REQUEST_L1 DLLP transmissions. There should be at least 10 us spent in LTSSM L0 and L0s state before the next PM_ACTIVE_STATE_REQUEST_L1 DLLP can be transmitted. Detailed information is on page 19 of the PCI Express 1.0a Base Specification Errata. This field has units of PCI clocks. Reserved PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 Access RW RsvdP Default 'h14D (M66EN low) 'h29A (M66EN high) 0 151 Configuration Registers Table 21-103. 15:0 31:16 Description CRS Timer. This field determines how many microseconds to wait before returning a completion with CRS status in response to a PCI Express to PCI Configuration Transaction. If the timer times out and the completion with CRS status is returned, the transaction is discarded from the Non-Posted Transaction Queue. This field is only valid in Forward Bridge mode when the Bridge Configuration Retry Enable bit in the DEVCTL register is set. Reserved Table 21-104. Bits 11:0 14:12 19:15 27:20 30:28 31 152 (Address 1060h; CRSTIMER) CRS Time Access Default RW 25 RsvdP 0 (Address 1064h; ECFGADDR) Enhanced Configuration Address Description Reserved Configuration Function Number. This field provides the function number for an enhanced Configuration Transaction. Configuration Device Number. This field provides the device number for an enhanced Configuration Transaction. Configuration Bus Number. This field provides the bus number for an enhanced Configuration Transaction. Reserved Enhanced Configuration Enable. When clear, accesses to Base Address Register 0 offset 'h2000 are not responded to by the PEX 8111. When set, accesses to Base Address Register 0 offset 'h2000 are forwarded to the PCI Express bus as a Configuration Request. This bit is only used in Reverse Bridge mode. PR EL IM IN AR Y Bits PLX Technology, Inc. Access RsvdP Default 0 RW 0 RW 0 RW 0 RsvdP 0 RW 0 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 Chapter 22 22.1 Testability and Debug JTAG Interface The PEX 8111 provides a JTAG Boundary Scan interface, which is utilized to debug board connectivity for each ball. 22.1.1 IEEE Standard 1149.1 Test Access Port The IEEE Standard 1149.1 Test Access Port (TAP), commonly referred to as the JTAG (Joint Test Action Group) debug port, is an architectural standard described in the IEEE Standard 1149.1-1990 IEEE Standard Test Access Port and Boundary-Scan Architecture. This standard describes a method for accessing internal chip facilities, using a four- or five-signal interface. PR EL IM IN AR Y The JTAG debug port, originally designed to support scan-based board testing, is enhanced to support the attachment of debug tools. The enhancements, which comply with the IEEE Standard 1149.1b-1994 Specifications for Vendor-Specific Extensions, are compatible with standard JTAG hardware for boundary-scan system testing. * JTAG Signals - JTAG debug port implements the four required JTAG signals (TCK, TDI, TDO, TMS) and the optional TRST# signal. * JTAG Clock Requirements - TCK signal frequency can range from DC to 10 MHz. * JTAG Reset Requirements - Refer to Section 22.1.4, "JTAG Reset Input TRST#". 22.1.2 JTAG Instructions The JTAG debug port provides the IEEE standard 1149.1 EXTEST, IDCODE, SAMPLE/PRELOAD, BYPASS, and PRIVATE instructions, as listed in Table 22-1. PRIVATE instructions are for PLX use only. Invalid instructions behave as the BYPASS instruction. Table 22-1 lists the JTAG instructions, along with their input codes. The PEX 8111 returns the IDCODE values listed in Table 22-2 Table 22-1. EXTEST, IDCODE, SAMPLE/PRELOAD, BYPASS, and PRIVATE Instructions Instruction Input Code EXTEST 00000b IDCODE 00001b SAMPLE/PRELOAD 00011b BYPASS 11111b Comments 00011b 00100b IEEE Standard 1149.1-1990 00101b 00110b PRIVATEa 00111b 01000b 01001b 01010b a. Warning: Non-PLX use of PRIVATE instructions can cause a component to operate in a hazardous manner. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 153 Testability and Debug PLX Technology, Inc. Table 22-2. 22.1.3 PEX 8111 JTAG IDCODE Values PEX 8111 Version Part Number PLX Manufacturer Identity Least Significant Bit Bits 0000b 1000_0001_1101_0010 000_0001_0000 1 Hex 0h 81D2h 10h 1h Decimal 0 33234 16 1 JTAG Boundary Scan Boundary PR EL IM IN AR Y Scan Description Language (BSDL), IEEE 1149.1b-1994, is a supplement to IEEE Standard 1149.11990 and IEEE 1149.1a-1993, IEEE Standard Test Access Port and Boundary-Scan Architecture. BSDL, a subset of the IEEE 1076-1993 Standard VHSIC Hardware Description Language (VHDL), which allows a rigorous description of testability features in components which comply with the standard. It is used by automated test pattern generation tools for package interconnect tests and Electronic Design Automation (EDA) tools for synthesized test logic and verification. BSDL supports robust extensions that can be used for internal test generation and to write software for hardware debug and diagnostics. The primary components of BSDL include the logical port description, physical ball map, instruction set, and boundary register description. The logical port description assigns symbolic names to the chip balls. Each ball has a logical type of in, out, in out, buffer, or linkage that defines the logical direction of signal flow. The physical ball map correlates the chip logical ports to the physical balls of a specific package. A BSDL description can have several physical ball maps; each map is given a unique name. Instruction set statements describe the bit patterns that must be shifted into the Instruction register to place the chip in the various test modes defined by the standard. Instruction set statements also support descriptions of instructions that are unique to the chip. The boundary register description lists each cell or shift stage of the Boundary register. Each cell has a unique number; the cell numbered 0 is the closest to the Test Data Out (TDO) ball and the cell with the highest number is closest to the Test Data In (TDI) ball. Each cell contains additional information, including: * * * * * * * 22.1.4 Cell type Logical port associated with the cell Logical function of the cell Safe value Control cell number Disable value Result value JTAG Reset Input TRST# The TRST# input ball is the asynchronous JTAG logic reset. When TRST# is asserted, it causes the PEX 8111 TAP controller to initialize. In addition, when the TAP controller is initialized, it selects the PEX 8111 normal logic path (core-to-I/O). It is recommended that the following be taken into consideration when implementing the asynchronous JTAG logic reset on a board: * If JTAG functionality is required, one of the following should be considered: - TRST# input signal should use a low-to-high transition once during the PEX 8111 boot-up, along with the RST# signal - Hold the PEX 8111 TMS ball high while transitioning the PEX 8111 TCK ball five times * If JTAG functionality is not required, the TRST# signal must be directly connected to ground 154 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 Chapter 23 23.1 Electrical Specifications Absolute Maximum Ratings Note: Conditions that exceed the Absolute Maximum limits may destroy the device. Table 23-1. Absolute Maximum Ratings Symbol Parameter Conditions 3.3V Supply Voltages With Respect to Ground -0.5 4.6 V VDD5 5V Supply Voltage With Respect to Ground -0.5 6.6 V DC input voltage 3.3 V buffer -0.5 4.6 V 5 V Tolerant buffer (PCI) -0.5 6.6 V 3mA Buffer -10 10 mA 6mA Buffer -20 20 mA TSTG TAMB VESD PR EL IM IN AR Y VDD3.3, VDDQ DC Output Current, per pin 1.8 Unit 1.5V Supply Voltages IOUT -0.5 Max VDD1.5, VDD_P, VDD_R, VDD_T, AVDD VI With Respect to Ground Min V 12mA Buffer -40 40 mA 24mA Buffer (PCI) -70 70 mA Storage Temperature No bias -65 150 C Ambient temperature Under bias -40 85 C ESD Rating R = 1.5K, C = 100pF 2 KV PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 155 Electrical Specifications 23.2 PLX Technology, Inc. Recommended Operating Conditions Note: Conditions that exceed the Operating limits may cause the device to function incorrectly. Table 23-2. Recommended Operating Conditions Parameter Conditions Min Max Unit VDD1.5, VDD_P, VDD_R, VDD_T, AVDD 1.5V Supply Voltages 1.4 1.6 V VDD3.3, VDDQ 3.3V Supply Voltages 3.0 3.6 V VDD5 5V Supply Voltage Note 1 4.75 5.25 V VN Negative trigger voltage 3.3 V buffer 0.8 1.7 V 5 V tolerant buffer (PCI) 0.8 1.7 V 3.3 V buffer 1.3 2.4 V PR EL IM IN AR Y Symbol 5 V tolerant buffer (PCI) 1.3 2.4 V 3.3 V buffer 0 0.7 V 5 V tolerant buffer (PCI) 0 0.8 V 3.3 V buffer 1.7 VDD3 V 5 V tolerant buffer (PCI) 2.0 VDD5+0.5 V 3mA buffer (VOL = 0.4) 3 mA 6mA buffer (VOL = 0.4) 6 mA 12mA buffer (VOL = 0.4) 12 mA 24mA buffer (VOL = 0.4) (PCI) 24 mA 3mA buffer (VOH = 2.4) -3 mA 6mA buffer (VOH = 2.4) -6 mA 12mA buffer (VOH = 2.4) -12 mA 24mA buffer (VOH = 2.4) (PCI) -24 mA 0 70 C VP Positive trigger voltage VIL Low Level Input Voltage VIH IOL High Level Input Voltage Low Level Output Current IOH High Level Output Current TA Operating Temperature tR Input rise times Normal input 0 200 ns tF Input fall time Normal input 0 200 ns tR Input rise times Schmitt input 0 10 ms tF Input fall time Schmitt input 0 10 ms Notes: 1, In a 3.3 V only system, the VDD5 pins can be connected to the 3.3 V supply (3.0 to 3.6 V). 2, Power up sequence The power supply voltages should be applied in the following sequence: First: VDD5, Second: 3.3 V and 1.5 V supplies, in any order. If the VDD5 pins are connected to the same 3.3 V supply used by the VDD3.3 and VDDQ pins, then power can be applied at the same time to the VDD5, VDD3.3, and VDDQ pins. 3, Power down sequence The power supply voltages should be removed in the following sequence: First: 3.3 V and 1.5 V supplies, in any order. Second: VDD5 If the VDD5 pins are connected to the same 3.3 V supply used by the VDD3.3 and VDDQ pins, then power can be removed at the same time from the VDD5, VDD3.3, and VDDQ pins. 156 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 DC Specifications 23.3 DC Specifications Operating Conditions: VDD1.5: 1.5V 0.1V, VDD3.3: 3.3V 0.3V, TA = 0 C to 70 C All typical values are at VDD1.5 = 1.5V, VDD3.3 = 3.3V and TA = 25 C Table 23-3. Core DC Specifications Symbol Parameter Conditions Min VDD1.5 Supply Current VDD1.5 = 1.5V IVDDSERDES VDD_P, VDD_R, VDD_T, AVDD, Supply Currents VDD_P, VDD_R, VDD_T, AVDD = 1.5V IVDD3.3 VDD3.3 Supply Current VDD3.3 = 3.3V IVDDQ VDDQ Supply Current VDDQ= 3.3V IVDD5 VDD5 Supply Current VDD5= 5.0V 23.3.1 PR EL IM IN AR Y IVDD1.5 Typ Max Unit 180 207 mA 19 22 mA .003 .004 mA PCI Bus DC Specification Operating Conditions: VDD1.5: 1.5V 0.1V, VDD3.3: 3.3V 0.3V, TA = 0 C to 70 C All typical values are at VDD1.5 = 1.5V, VDD3.3 = 3.3V and TA = 25 C Table 23-4. PCI Bus DC Specification Symbol Parameter Conditions Min Typ Max Unit VIHd PCI 3.3V Input High Voltage 0.5*VDD3.3 VDD3.3 V VILd PCI 3.3V Input Low Voltage 0 0.7 V VIH PCI 5.0V Input High Voltage 2.0 5.5 V VIL PCI 5.0V Input Low Voltage 0 0.8 V IIL Input Leakage 0V < VIN < VDD5 -10 10 A IOZ Hi-Z State Data Line Leakage 0V < VIN < VDD5 10 A VOH3 PCI 3.3V Output High Voltage IOUT = -500 A VOL3 PCI 3.3V Output Low Voltage IOUT = 1500 A VOH PCI 5.0V Output High Voltage IOUT = -12mA VOL PCI 5.0V Output Low Voltage IOUT = 12mA 0.4 V CIN Input Capacitance Pin to GND 10 pF CCLK CLK Pin Capacitance Pin to GND 12 pF CIDSEL IDSEL Pin Capacitance Pin to GND 8 pF 0.9*VDD3.3 V 0.1*VDD3.3 2.4 5 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 V V 157 Electrical Specifications PLX Technology, Inc. 23.4 AC Specifications 23.4.1 PCI Bus 33-MHz AC Specifications Operating Conditions: VDD1.5: 1.5V 0.1V, VDD3.3: 3.3V 0.3V, TA = 0 C to 70 C All typical values are at VDD1.5 = 1.5V, VDD3.3 = 3.3V and TA = 25 C Table 23-5. PCI Bus 33-MHz AC Specifications Symbol Parameter Conditions Min Max Unit Notes PCI CLK Cycle Time 30 ns TVAL CLK to signal valid delay - bused signals 2 11 ns 2, 3 TVAL(ptp) CLK to signal valid delay - point to point 2 12 ns 2, 3 TON Float to Active Delay 2 ns 7 TOFF Active to Float Delay ns 7 TSU Input Setup to CLK - bused signals 6 ns 3, 8 TSU(ptp) Input Setup to CLK - point to point 10,12 ns 3 TH Input Hold from CLK 0 ns TRST Reset active time after power stable 1 ms 5 TRST-CLK Reset active time after CLK stable 100 s 5 TRST-OFF Reset active to Output Float delay ns 5, 6, 7 TRHFA RST# high to first configuration access 225 clocks 9 TRHFF RST# high to first FRAME# assertion 5 clocks Notes: PR EL IM IN AR Y TCYC 28 40 2, For parts compliant to the 5V signaling environment: Minimum times are evaluated with 0pF equivalent load; maximum times are evaluated with 50pF equivalent load. Actual test capacitance may vary, but results must be correlated to these specifications. Faster buffers may exhibit some ring back when attached to a 50pF lump load which should be of no consequence as long as the output buffers are in full compliance with slew rate and V/I curve specifications. For parts compliant to the 3.3V signaling environment: Minimum times are evaluated with the same load used for slew rate measurement; maximum times are evaluated with a parallel RC load of 25 ohms and 10pF. 3, REQ# and GNT# are point-to-point signals and have different output valid delay and input setup times than do bused signals. GNT# has a setup of 10; REQ# has a setup of 12. All other signals are bused. 5, CLK is stable when it meets the PCI CLK specifications. RST# is asserted and de-asserted asynchronously with respect to CLK. 6, All output drivers must be asynchronously floated when RST# is active. 7, For purposes of Active/Float timing measurements, the Hi-Z or "off" state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 8, Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at the same time. 9, At 66 MHz, the device needs to be ready to accept a configuration access within 1 second after RST# is high. 158 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 23.4.2 PCI Bus 66-MHz AC Specifications PCI Bus 66-MHz AC Specifications Operating Conditions: VDD1.5: 1.5V 0.1V, VDD3.3: 3.3V 0.3V, TA = 0 C to 70 C All typical values are at VDD1.5 = 1.5V, VDD3.3 = 3.3V and TA = 25 C Table 23-6. PCI Bus 66-MHz AC Specifications Symbol Parameter Conditions Min Max Unit Notes TCYC PCI CLK Cycle Time 15 ns TVAL CLK to signal valid delay - bused signals 2 6 ns 3, 8 TVAL(ptp) CLK to signal valid delay - point to point 2 6 ns 3, 8 TON Float to Active Delay 2 ns 8, 9 TOFF Active to Float Delay ns 9 TSU Input Setup to CLK - bused signals 3 ns 3, 10 TSU(ptp) Input Setup to CLK - point to point 5 ns 3 TH Input Hold from CLK 0 ns TRST Reset active time after power stable 1 ms 5 TRST-CLK Reset active time after CLK stable 100 s 5 TRST-OFF Reset active to Output Float delay ns 5, 6 TRHFA RST# high to first configuration access 225 clocks 9 TRHFF RST# high to first FRAME# assertion 5 clocks PR EL IM IN AR Y Notes: 14 40 3. REQ# and GNT# are point-to-point signals and have different input setup times than do bused signals. GNT# and REQ# have a setup of 5 ns at 66 MHz. All other signals are bused. 5. If M66EN is asserted, CLK is stable when it meets the requirements in PCI Local Bus Specification Section 7.6.4.1. RST# is asserted and de-asserted asynchronously with respect to CLK. Refer to PCI r2.3, Section 4.3.2 for further information. 6. All output drivers must be floated when RST# is active. 8. When M66EN is asserted, the minimum specification for Tval(min), Tval(ptp)(min), and Ton may be reduced to 1 ns if a mechanism is provided to guarantee a minimum value of 2 ns when M66EN is de-asserted. 9. For purposes of Active/Float timing measurements, the Hi-Z or "off" state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 10. Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at the same time. Refer to PCI Section 3.10, item 9 for further details. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 r2.3, 159 PLX Technology, Inc. PR EL IM IN AR Y Electrical Specifications 160 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 Chapter 24 PBGA (144 Pin Package) PR EL IM IN AR Y 24.1 Mechanical PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 161 Mechanical FBGA (161 Pin Package) PR EL IM IN AR Y 24.2 PLX Technology, Inc. 162 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 June, 2005 PCB Layout PR EL IM IN AR Y 24.3 PCB Layout PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 163 PLX Technology, Inc. PR EL IM IN AR Y Mechanical 164 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 Appendix A General Information A.1 Product Ordering Information Table A-1. Product Ordering Information Part Number Description PCI Express-to-PCI Bridge, Standard BGA Package (144-Ball, 13 x 13 mm) PEX8111-AA66FBC PCI Express-to-PCI Bridge, Fine-Pitch BGA Package (161-Ball, 10 x 10 mm) PEX8111-AA66BC F PCI Express-to-PCI Bridge, Standard BGA Package (144-Ball, 13 x 13 mm), Lead Free PR EL IM IN AR Y PEX8111-AA66BC PEX8111-AA66FBC F PEX8111RDK-F PEX8111RDK-R A.2 PCI Express-to-PCI Bridge, Fine-Pitch BGA Package (161-Ball, 10 x 10 mm), Lead Free Forward Bridge Reference Design Kit Reverse Bridge Reference Design Kit United States and International Representatives and Distributors A list of PLX Technology, Inc., representatives and distributors can be found at http://www.plxtech.com. A.3 Technical Support PLX Technology, Inc., technical support information is listed at http://www.plxtech.com/support/, or call 408 774-9060 or 800 759-3735. PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82 165 PLX Technology, Inc. PR EL IM IN AR Y General Information 166 PEX 8111AA PCI Express-to-PCI Bridge Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved -- Version 0.82