Features
80C52 Compatible
8051 Instruction Compatible
Six 8-bit I/O Ports (64 Pins or 68 Pins Versions)
Four 8-bit I/O Ports (44 Pins Version)
Three 16-bit Timer/Counters
256 Bytes Scratch Pad RAM
9 Interrupt Sources with 4 Priority Levels
Integrated Power Monitor (POR/PFD) to Supervise Internal Power Supply
ISP (In-System Programming) Using Standard V
CC
Power Supply
2048 Bytes Boot ROM Contains Low Level Flash Programming Routines and a Default
Serial Loader
High-speed Architecture
In Standard Mode:
40 MHz (Vcc 2.7V to 5.5V, both Internal and external code execution)
60 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)
In X2 mode (6 Clocks/machine cycle)
20 MHz (Vcc 2.7V to 5.5V, both Internal and external code execution)
30 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)
64K Bytes On-chip Flash Program/Data Memory
Byte and Page (128 Bytes) Erase and Write
100k Write Cycles
On-chip 1792 bytes Expanded RAM (XRAM)
Software Selectable Size (0, 256, 512, 768, 1024, 1792 Bytes)
768 Bytes Selected at Reset for T89C51RD2 Compatibility
On-chip 2048 Bytes EEPROM Block for Data Storage (AT89C51ED2 Only)
100K Write Cycles
Dual Data Pointer
Variable Length MOVX for Slow RAM/Peripherals
Improved X2 Mode with Independent Selection for CPU and Each Peripheral
Keyboard Interrupt Interface on Port 1
SPI Interface (Master/Slave Mode)
8-bit Clock Prescaler
16-bit Programmable Counter Array
High Speed Output
Compare/Capture
Pulse Width Modulator
Watchdog Timer Capabilities
Asynchronous Port Reset
Full-duplex Enhanced UART with Dedicated Internal Baud Rate Generator
Low EMI (Inhibit ALE)
Hardware Watchdog Timer (One-time Enabled with Reset-Out), Power-off Flag
Power Control Modes: Idle Mode, Power-down Mode
Single Range Power Supply: 2.7V to 5.5V
Industrial Temperature Range (-40 to +85°C)
Packages: PLCC44, VQFP44, PLCC68, VQFP64
8-bit Flash
Microcontroller
AT89C51RD2
AT89C51ED2
2
4235K–8051–05/08
AT89C51RD2/ED2
1. Description
AT89C51RD2/ED2 is high performance CMOS Flash version of the 80C51 CMOS single chip 8-
bit microcontroller. It contains a 64-Kbyte Flash memory block for code and for data.
The 64-Kbytes Flash memory can be programmed either in parallel mode or in serial mode with
the ISP capability or with software. The programming voltage is internally generated from the
standard V
CC
pin.
The AT89C51RD2/ED2 retains all of the features of the Atmel 80C52 with 256 bytes of internal
RAM, a 9-source 4-level interrupt controller and three timer/counters. The AT89C51ED2 pro-
vides 2048 bytes of EEPROM for nonvolatile data storage.
In addition, the AT89C51RD2/ED2 has a Programmable Counter Array, an XRAM of 1792
bytes, a Hardware Watchdog Timer, SPI interface, Keyboard, a more versatile serial channel
that facilitates multiprocessor communication (EUART) and a speed improvement mechanism
(X2 Mode).
The fully static design of the AT89C51RD2/ED2 allows to reduce system power consumption by
bringing the clock frequency down to any value, including DC, without loss of data.
The AT89C51RD2/ED2 has 2 software-selectable modes of reduced activity and an 8-bit clock
prescaler for further reduction in power consumption. In the Idle mode the CPU is frozen while
the peripherals and the interrupt system are still operating. In the Power-down mode the RAM is
saved and all other functions are inoperative.
The added features of the AT89C51RD2/ED2 make it more powerful for applications that need
pulse width modulation, high speed I/O and counting capabilities such as alarms, motor control,
corded phones, and smart card readers.
Table 1-1. Memory Size and I/O Pins
Package Flash (Bytes) XRAM (Bytes) Total RAM (Bytes) I/O
PLCC44/VQFP44 64K 1792 2048 34
PLCC68/VQFP64 64K 1792 2048 50
3
4235K–8051–05/08
AT89C51RD2/ED2
2. Block Diagram
Figure 2-1. Block Diagram
Timer 0 INT
RAM
256x8
T0
T1
RxD
TxD
WR
RD
EA
PSEN
ALE/
XTALA2
XTALA1 EUART
CPU
Timer 1
INT1
Ctrl
INT0
(2)
(2)
C51
CORE
(2) (2) (2) (2)
Port 0
P0
Port 1
Port 2
Port 3
P1
P2
P3
XRAM
1792 x 8
IB-bus
PCA
RESET
PROG
Watch
-dog
PCA
ECI
VSS
VCC
(2)(2) (1)
(1): Alternate function of Port 1
(2): Alternate function of Port 3
(1)
Timer2
T2EX
T2
(1) (1)
Flash
64K x 8
Keyboard
(1)
Keyboard
MISO
MOSI
SCK
SS
Port4
P4
(1) (1)(1)(1)
BOOT
2K x 8
ROM
Regulator
POR / PFD
Port 5
P5
Parallel I/O Ports &
External Bus SPI
EEPROM*
2K x 8
(AT89C51ED2)
4
4235K–8051–05/08
AT89C51RD2/ED2
3. SFR Mapping
The Special Function Registers (SFRs) of the AT89C51RD2/ED2 fall into the following
categories:
C51 core registers: ACC, B, DPH, DPL, PSW, SP
I/O port registers: P0, P1, P2, P3, PI2
Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L,
RCAP2H
Serial I/O port registers: SADDR, SADEN, SBUF, SCON
PCA (Programmable Counter Array) registers: CCON, CCAPMx, CL, CH, CCAPxH, CCAPxL
(x: 0 to 4)
Power and clock control registers: PCON
Hardware Watchdog Timer registers: WDTRST, WDTPRG
Interrupt system registers: IE0, IPL0, IPH0, IE1, IPL1, IPH1
Keyboard Interface registers: KBE, KBF, KBLS
SPI registers: SPCON, SPSTR, SPDAT
BRG (Baud Rate Generator) registers: BRL, BDRCON
Clock Prescaler register: CKRL
Others: AUXR, AUXR1, CKCON0, CKCON1
Table 3-1. C51 Core SFRs
Mnemonic Add Name 7 6 5 4 3 2 1 0
ACC E0h Accumulator
B F0h B Register
PSW D0h Program Status Word CY AC F0 RS1 RS0 OV F1 P
SP 81h Stack Pointer
DPL 82h Data Pointer Low Byte
DPH 83h Data Pointer High Byte
Table 3-2. System Management SFRs
Mnemonic Add Name 7 6 5 4 3 2 1 0
PCON 87h Power Control SMOD1 SMOD0 - POF GF1 GF0 PD IDL
AUXR 8Eh Auxiliary Register 0 DPU - M0 XRS2 XRS1 XRS0 EXTRAM AO
AUXR1 A2h Auxiliary Register 1 - - ENBOOT - GF3 0 - DPS
CKRL 97h Clock Reload Register - - - - - - - -
CKCKON0 8Fh Clock Control Register 0 - WDTX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2
CKCKON1 AFh Clock Control Register 1 - - - - - - - SPIX2
5
4235K–8051–05/08
AT89C51RD2/ED2
Table 3-3. Interrupt SFRs
Mnemonic Add Name 7 6 5 4 3 2 1 0
IEN0 A8h Interrupt Enable Control 0 EA EC ET2 ES ET1 EX1 ET0 EX0
IEN1 B1h Interrupt Enable Control 1 - - - - - ESPI KBD
IPH0 B7h Interrupt Priority Control High 0 - PPCH PT2H PHS PT1H PX1H PT0H PX0H
IPL0 B8h Interrupt Priority Control Low 0 - PPCL PT2L PLS PT1L PX1L PT0L PX0L
IPH1 B3h Interrupt Priority Control High 1 - - - - - SPIH KBDH
IPL1 B2h Interrupt Priority Control Low 1 - - - - - SPIL KBDL
Table 3-4. Port SFRs
Mnemonic Add Name 7 6 5 4 3 2 1 0
P0 80h 8-bit Port 0
P1 90h 8-bit Port 1
P2 A0h 8-bit Port 2
P3 B0h 8-bit Port 3
P4 C0h 8-bit Port 4
P5 E8h 8-bit Port 5
P5 C7h 8-bit Port 5 (byte addressable)
Table 3-5. Timer SFRs
Mnemonic Add Name 7 6 5 4 3 2 1 0
TCON 88h Timer/Counter 0 and 1 Control TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
TMOD 89h Timer/Counter 0 and 1 Modes GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00
TL0 8Ah Timer/Counter 0 Low Byte
TH0 8Ch Timer/Counter 0 High Byte
TL1 8Bh Timer/Counter 1 Low Byte
TH1 8Dh Timer/Counter 1 High Byte
WDTRST A6h WatchDog Timer Reset
WDTPRG A7h WatchDog Timer Program - - - - - WTO2 WTO1 WTO0
T2CON C8h Timer/Counter 2 control TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#
T2MOD C9h Timer/Counter 2 Mode - - - - - - T2OE DCEN
RCAP2H CBh Timer/Counter 2 Reload/Capture
High Byte
RCAP2L CAh Timer/Counter 2 Reload/Capture
Low Byte
TH2 CDh Timer/Counter 2 High Byte
6
4235K–8051–05/08
AT89C51RD2/ED2
TL2 CCh Timer/Counter 2 Low Byte
Table 3-5. Timer SFRs
Mnemonic Add Name 7 6 5 4 3 2 1 0
Table 3-6. PCA SFRs
Mnemo
-nic Add Name 7 6 5 4 3 2 1 0
CCON D8h PCA Timer/Counter Control CF CR CCF4 CCF3 CCF2 CCF1 CCF0
CMOD D9h PCA Timer/Counter Mode CIDL WDTE CPS1 CPS0 ECF
CL E9h PCA Timer/Counter Low Byte
CH F9h PCA Timer/Counter High Byte
CCAPM0
CCAPM1
CCAPM2
CCAPM3
CCAPM4
DAh
DBh
DCh
DDh
DEh
PCA Timer/Counter Mode 0
PCA Timer/Counter Mode 1
PCA Timer/Counter Mode 2
PCA Timer/Counter Mode 3
PCA Timer/Counter Mode 4
ECOM0
ECOM1
ECOM2
ECOM3
ECOM4
CAPP0
CAPP1
CAPP2
CAPP3
CAPP4
CAPN0
CAPN1
CAPN2
CAPN3
CAPN4
MAT0
MAT1
MAT2
MAT3
MAT4
TOG0
TOG1
TOG2
TOG3
TOG4
PWM0
PWM1
PWM2
PWM3
PWM4
ECCF0
ECCF1
ECCF2
ECCF3
ECCF4
CCAP0H
CCAP1H
CCAP2H
CCAP3H
CCAP4H
FAh
FBh
FCh
FDh
FEh
PCA Compare Capture Module 0 H
PCA Compare Capture Module 1 H
PCA Compare Capture Module 2 H
PCA Compare Capture Module 3 H
PCA Compare Capture Module 4 H
CCAP0H7
CCAP1H7
CCAP2H7
CCAP3H7
CCAP4H7
CCAP0H6
CCAP1H6
CCAP2H6
CCAP3H6
CCAP4H6
CCAP0H5
CCAP1H5
CCAP2H5
CCAP3H5
CCAP4H5
CCAP0H4
CCAP1H4
CCAP2H4
CCAP3H4
CCAP4H4
CCAP0H3
CCAP1H3
CCAP2H3
CCAP3H3
CCAP4H3
CCAP0H2
CCAP1H2
CCAP2H2
CCAP3H2
CCAP4H2
CCAP0H1
CCAP1H1
CCAP2H1
CCAP3H1
CCAP4H1
CCAP0H0
CCAP1H0
CCAP2H0
CCAP3H0
CCAP4H0
CCAP0L
CCAP1L
CCAP2L
CCAP3L
CCAP4L
EAh
EBh
ECh
EDh
EEh
PCA Compare Capture Module 0 L
PCA Compare Capture Module 1 L
PCA Compare Capture Module 2 L
PCA Compare Capture Module 3 L
PCA Compare Capture Module 4 L
CCAP0L7
CCAP1L7
CCAP2L7
CCAP3L7
CCAP4L7
CCAP0L6
CCAP1L6
CCAP2L6
CCAP3L6
CCAP4L6
CCAP0L5
CCAP1L5
CCAP2L5
CCAP3L5
CCAP4L5
CCAP0L4
CCAP1L4
CCAP2L4
CCAP3L4
CCAP4L4
CCAP0L3
CCAP1L3
CCAP2L3
CCAP3L3
CCAP4L3
CCAP0L2
CCAP1L2
CCAP2L2
CCAP3L2
CCAP4L2
CCAP0L1
CCAP1L1
CCAP2L1
CCAP3L1
CCAP4L1
CCAP0L0
CCAP1L0
CCAP2L0
CCAP3L0
CCAP4L0
Table 3-7. Serial I/O Port SFRs
Mnemonic Add Name 7 6 5 4 3 2 1 0
SCON 98h Serial Control FE/SM0 SM1 SM2 REN TB8 RB8 TI RI
SBUF 99h Serial Data Buffer
SADEN B9h Slave Address Mask
SADDR A9h Slave Address
BDRCON 9Bh Baud Rate Control BRR TBCK RBCK SPD SRC
BRL 9Ah Baud Rate Reload
Table 3-8. SPI Controller SFRs
Mnemonic Add Name 7 6 5 4 3 2 1 0
SPCON C3h SPI Control SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0
SPSTA C4h SPI Status SPIF WCOL SSERR MODF
SPDAT C5h SPI Data SPD7 SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPD0
7
4235K–8051–05/08
AT89C51RD2/ED2
shows all SFRs with their address and their reset value.
Table 3-9. Keyboard Interface SFRs
Mnemonic Add Name 7 6 5 4 3 2 1 0
KBLS 9Ch Keyboard Level Selector KBLS7 KBLS6 KBLS5 KBLS4 KBLS3 KBLS2 KBLS1 KBLS0
KBE 9Dh Keyboard Input Enable KBE7 KBE6 KBE5 KBE4 KBE3 KBE2 KBE1 KBE0
KBF 9Eh Keyboard Flag Register KBF7 KBF6 KBF5 KBF4 KBF3 KBF2 KBF1 KBF0
Table 3-10. EEPROM data Memory SFR (AT89C51ED2 only)
Mnemonic Add Name 7 6 5 4 3 2 1 0
EECON D2h EEPROM Data Control EEE EEBUSY
Table 3-11. SFR Mapping
Bit
Addressable Non Bit Addressable
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
F8h CH
0000 0000
CCAP0H
XXXX XXXX
CCAP1H
XXXX XXXX
CCAP2H
XXXX XXXX
CCAP3H
XXXX XXXX
CCAP4H
XXXX XXXX FFh
F0h B
0000 0000 F7h
E8h
P5 bit
addressable
1111 1111
CL
0000 0000
CCAP0L
XXXX XXXX
CCAP1L
XXXX XXXX
CCAP2L
XXXX XXXX
CCAP3L
XXXX XXXX
CCAP4L
XXXX XXXX EFh
E0h ACC
0000 0000 E7h
D8h CCON
00X0 0000
CMOD
00XX X000
CCAPM0
X000 0000
CCAPM1
X000 0000
CCAPM2
X000 0000
CCAPM3
X000 0000
CCAPM4
X000 0000 DFh
D0h PSW
0000 0000
FCON
XXXX 0000
EECON
xxxx xx00 D7h
C8h T2CON
0000 0000
T2MOD
XXXX XX00
RCAP2L
0000 0000
RCAP2H
0000 0000
TL2
0000 0000
TH2
0000 0000 CFh
C0h P4
1111 1111
SPCON
0001 0100
SPSTA
0000 0000
SPDAT
XXXX XXXX
P5 byte
Addressable
1111 1111
C7h
B8h IPL0
X000 000
SADEN
0000 0000 BFh
B0h P3
1111 1111
IEN1
XXXX X000
IPL1
XXXX X000
IPH1
XXXX X000
IPH0
X000 0000 B7h
A8h IEN0
0000 0000
SADDR
0000 0000
CKCON1
XXXX XXX0 AFh
8
4235K–8051–05/08
AT89C51RD2/ED2
A0h P2
1111 1111
AUXR1
0XXX X0X0
WDTRST
XXXX XXXX
WDTPRG
XXXX X000 A7h
98h SCON
0000 0000
SBUF
XXXX XXXX
BRL
0000 0000
BDRCON
XXX0 0000
KBLS
0000 0000
KBE
0000 0000
KBF
0000 0000 9Fh
90h P1
1111 1111
CKRL
1111 1111 97h
88h TCON
0000 0000
TMOD
0000 0000
TL0
0000 0000
TL1
0000 0000
TH0
0000 0000
TH1
0000 0000
AUXR
0X00 1000
CKCON0
0000 0000 8Fh
80h P0
1111 1111
SP
0000 0111
DPL
0000 0000
DPH
0000 0000
PCON
00X1 0000 87h
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
Table 3-11. SFR Mapping
reserved
9
4235K–8051–05/08
AT89C51RD2/ED2
4. Pin Configurations
Figure 4-1. Pin Configurations
43 42 41 40 3944 38 37 36 35 34
P1.4/CEX1
P1.0/T2
P1.1/T2EX/SS
P1.3/CEX0
P1.2/ECI
VCC
P0.0/AD0
P0.2/AD2
P0.3/AD3
P0.1/AD1
P0.4/AD4
P0.6/AD6
P0.5/AD5
P0.7/AD7
ALE/PROG
PSEN
EA
P2.7/A15
P2.5/A13
P2.6/A14
P1.5/CEX2/MISO
P1.6/CEX3/SCK
P1.7/CEX4/MOSI
RST
P3.0/RxD
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
NIC*
12 13 17161514 201918 21 22
33
32
31
30
29
28
27
26
25
24
23
AT89C51RD2/ED2
1
2
3
4
5
6
7
8
9
10
11
VQFP44 1.4
NIC*
NIC*
NIC*
PLCC44
AT89C51RD2/ED2
NIC*
NIC*
NIC*
18 19 23222120 262524 27 28
5 4 3 2 1 6 44 43 42 41 40
P1.4/CEX1
P1.0/T2
P1.1/T2EX/SS
P1.3/CEX0
P1.2/ECI
VCC
P0.0/AD0
P0.2/AD2
P0.1/AD1
P0.4/AD4
P0.6/AD6
P0.5/AD5
P0.7/AD7
ALE/PROG
PSEN
EA
P2.7/A15
P2.5/A13
P2.6/A14
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P1.5/CEX2/MISO
P1.6/CEX3/SCK
P1.7/CEx4/MOSI
RST
P3.0/RxD
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P0.3/AD3
NIC*
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
10
4235K–8051–05/08
AT89C51RD2/ED2
50
49
48
47
44
45
46
P4.5
P3.7/
RD
XTAL2
XTAL1
P4.4
P3.6/
WR
P4.3
NIC
NIC
P3.1/TxD
P3.2/I
NT0
P3.3/
INT1
P3.4/T0
P3.5/T1
37
38
39
40
41
42
43
AT89C51ED2
PLCC68
P0.4/AD4
P5.4
P5.3
P0.5/AD5
P0.6/AD6
NIC
P0.7/AD7
EA
NIC
ALE
P1.6/CEX3/SCK
P1.7/CEX4/MOSI
RST
NIC
NIC
NIC
P3.0/RxD
NIC
NIC
P1.5/CEX2/MISO
60
59
58
57
56
55
54
53
51
52
10
11
12
13
14
15
16
17
19
18
27
28
29
30
31
32
33
34
35
36
9
8
7
6
5
3
2
1
68
P5.0
P2.4/A12
P2.3/A11
P4.7
P2.2/A10
P4.6
P2.0/A8
P2.1/A9
NIC
VSS
P5.5
P0.3/AD3
P0.2/AD2
P5.6
P0.1/AD1
P0.0/AD0
P5.7
VCC
NIC
P1.0/T2
4
PSEN
NIC
P2.7/A15
P2.6/A14
P5.2
P5.1
P2.5/A13
67
65
64
63
62
61
66
20
21
22
23
26
25
24
P4.0
P1.1/T2EX/
SS
P1.2/ECI
P1.3/CEX0
P4.1
P1.4/CEX1
P4.2
NIC: Not Internaly Connected
54
53
52
51
50
49
AT89C51ED2
VQFP64
P0.4/AD4
P5.4
P5.3
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
NIC
ALE
PSEN#
P1.5/CEX2/MISO
P1.6/CEX3/SCK
P1.7/A17/CEX4/MOSI
RST
NIC
NIC
NIC
P3.0/RxD
NIC
P4.2
48
47
46
45
44
43
42
41
39
40
1
2
3
4
5
6
7
8
10
9
17
18
19
20
21
22
23
24
25
26
64
63
62
61
60
59
58
57
56
55
P2.4/A12
P2.3/A11
P4.7
P2.2/A10
P2.1/A9
NIC
P4.6
P2.0/A8
VSS
P4.5
P5.5
P0.3/AD3
P0.2/AD2
P5.6
P0.1/AD1
P0.0/AD0
P5.7
VCC
NIC
P1.0/T2
11
12
13
16
15
14
P4.0
P1.1/T2EX/
SS
P1.2/ECI
P1.3/CEX0
P4.1
P1.4/CEX1
38
37
36
33
34
35
P3.7/
RD
XTAL2
XTAL1
P4.4
P3.6/
WR
P4.3
NIC
P3.1/TxD
P3.2/
INT0
P3.3
/INT1
P3.4/T0
P3.5/T1
27
28
29
30
31
32
P2.7/A15
P2.6/A14
P5.2
P5.1
P2.5/A13
P5.0
11
4235K–8051–05/08
AT89C51RD2/ED2
Table 4-1. Pin Description
Mnemonic
Pin Number
Type
Name and FunctionPLCC44 VQFP44 PLCC68 VQFP64
VSS 22 16 51 40 I Ground: 0V reference
VCC 44 38 17 8 I Power Supply: This is the power supply voltage for normal, idle and
power-down operation
P0.0 - P0.7 43 - 36 37 - 30
15, 14,
12, 11,
9,6, 5, 3
6, 5, 3, 2,
64,
61,60,59
I/O
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that
have 1s written to them float and can be used as high impedance inputs.
Port 0 must be polarized to VCC or VSS in order to prevent any parasitic
current consumption. Port 0 is also the multiplexed low-order address
and data bus during access to external program and data memory. In this
application, it uses strong internal pull-up when emitting 1s. Port 0 also
inputs the code bytes during EPROM programming. External pull-ups are
required during program verification during which P0 outputs the code
bytes.
P1.0 - P1.7 2 - 9 40 - 44
1 - 3
19, 21,
22, 23,
25, 27,
28, 29
10, 12,
13, 14,
16, 18,
19, 20
I/O
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1
pins that have 1s written to them are pulled high by the internal pull-ups
and can be used as inputs. As inputs, Port 1 pins that are externally
pulled low will source current because of the internal pull-ups. Port 1 also
receives the low-order address byte during memory programming and
verification.
Alternate functions for AT89C51RD2/ED2 Port 1 include:
2 40 19 10 I/O P1.0: Input/Output
I/O T2 (P1.0): Timer/Counter 2 external count input/Clockout
3 41 21 12 I/O P1.1: Input/Output
IT2EX: Timer/Counter 2 Reload/Capture/Direction Control
ISS: SPI Slave Select
4 42 22 13 I/O P1.2: Input/Output
IECI: External Clock for the PCA
5 43 23 14 I/O P1.3: Input/Output
I/O CEX0: Capture/Compare External I/O for PCA module 0
6 44 25 16 I/O P1.4: Input/Output
I/O CEX1: Capture/Compare External I/O for PCA module 1
7 1 27 18 I/O P1.5: Input/Output
I/O CEX2: Capture/Compare External I/O for PCA module 2
I/O MISO: SPI Master Input Slave Output line
When SPI is in master mode, MISO receives data from the slave
peripheral. When SPI is in slave mode, MISO outputs data to the master
controller.
8 2 28 19 I/O P1.6: Input/Output
I/O CEX3: Capture/Compare External I/O for PCA module 3
I/O SCK: SPI Serial Clock
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9 3 29 20 I/O P1.7: Input/Output:
I/O CEX4: Capture/Compare External I/O for PCA module 4
I/O MOSI: SPI Master Output Slave Input line
When SPI is in master mode, MOSI outputs data to the slave peripheral.
When SPI is in slave mode, MOSI receives data from the master
controller.
XTALA1 21 15 49 38 I XTALA 1: Input to the inverting oscillator amplifier and input to the
internal clock generator circuits.
XTALA2 20 14 48 37 O XTALA 2: Output from the inverting oscillator amplifier
P2.0 - P2.7 24 - 31 18 - 25
54, 55,
56, 58,
59, 61,
64, 65
43, 44,
45, 47,
48, 50,
53, 54
I/O
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2
pins that have 1s written to them are pulled high by the internal pull-ups
and can be used as inputs. As inputs, Port 2 pins that are externally
pulled low will source current because of the internal pull-ups. Port 2
emits the high-order address byte during fetches from external program
memory and during accesses to external data memory that use 16-bit
addresses (MOVX @DPTR).In this application, it uses strong internal
pull-ups emitting 1s. During accesses to external data memory that use
8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR.
P3.0 - P3.7 11,
13 - 19
5,
7 - 13
34, 39,
40, 41,
42, 43,
45, 47
25, 28,
29, 30,
31, 32,
34, 36
I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3
pins that have 1s written to them are pulled high by the internal pull-ups
and can be used as inputs. As inputs, Port 3 pins that are externally
pulled low will source current because of the internal pull-ups. Port 3 also
serves the special features of the 80C51 family, as listed below.
11 5 34 25 I RXD (P3.0): Serial input port
13 7 39 28 O TXD (P3.1): Serial output port
14 8 40 29 I INT0 (P3.2): External interrupt 0
15 9 41 30 I INT1 (P3.3): External interrupt 1
16 10 42 31 I T0 (P3.4): Timer 0 external input
17 11 43 32 I T1 (P3.5): Timer 1 external input
18 12 45 34 O WR (P3.6): External data memory write strobe
19 13 47 36 O RD (P3.7): External data memory read strobe
P4.0 - P4.7 - -
20, 24,
26, 44,
46, 50,
53, 57
11, 15,
17,33,
35,39,
42, 46
I/O
Port 4: Port 4 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3
pins that have 1s written to them are pulled high by the internal pull-ups
and can be used as inputs. As inputs, Port 3 pins that are externally
pulled low will source current because of the internal pull-ups.
P5.0 - P5.7 - -
60, 62,
63, 7, 8,
10, 13, 16
49, 51,
52, 62,
63, 1, 4, 7
I/O
Port 5: Port 5 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3
pins that have 1s written to them are pulled high by the internal pull-ups
and can be used as inputs. As inputs, Port 3 pins that are externally
pulled low will source current because of the internal pull-ups.
RST 10 4 30 21 I
Reset: A high on this pin for two machine cycles while the oscillator is
running, resets the device. An internal diffused resistor to VSS permits a
power-on reset using only an external capacitor to VCC. This pin is an
output when the hardware watchdog forces a system reset.
Table 4-1. Pin Description (Continued)
Mnemonic
Pin Number
Type
Name and FunctionPLCC44 VQFP44 PLCC68 VQFP64
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ALE/PRO
G33 27 68 56 O (I) Address Latch Enable/Program Pulse: Output pulse for latching the
low byte of the address during an access to external memory. In normal
operation, ALE is emitted at a constant rate of 1/6 (1/3 in X2 mode) the
oscillator frequency, and can be used for external timing or clocking. Note
that one ALE pulse is skipped during each access to external data
memory. This pin is also the program pulse input (PROG) during Flash
programming. ALE can be disabled by setting SFR’s AUXR.0 bit. With
this bit set, ALE will be inactive during internal fetches.
PSEN 32 26 67 55 O Program Strobe ENable: The read strobe to external program memory.
When executing code from the external program memory, PSEN is
activated twice each machine cycle, except that two PSEN activations
are skipped during each access to external data memory. PSEN is not
activated during fetches from internal program memory.
EA 35 29 2 58 I External Access Enable: EA must be externally held low to enable the
device to fetch code from external program memory locations 0000H to
FFFFH. If security level 1 is programmed, EA will be internally latched on
Reset.
Table 4-1. Pin Description (Continued)
Mnemonic
Pin Number
Type
Name and FunctionPLCC44 VQFP44 PLCC68 VQFP64
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5. Port Types
AT89C51RD2/ED2 I/O ports (P1, P2, P3, P4, P5) implement the quasi-bidirectional output that
is common on the 80C51 and most of its derivatives. This output type can be used as both an
input and output without the need to reconfigure the port. This is possible because when the port
outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. When the
pin is pulled low, it is driven strongly and able to sink a fairly large current. These features are
somewhat similar to an open drain output except that there are three pull-up transistors in the
quasi-bidirectional output that serve different purposes. One of these pull-ups, called the "weak"
pull-up, is turned on whenever the port latch for the pin contains a logic 1. The weak pull-up
sources a very small current that will pull the pin high if it is left floating. A second pull-up, called
the "medium" pull-up, is turned on when the port latch for the pin contains a logic 1 and the pin
itself is also at a logic 1 level. This pull-up provides the primary source current for a quasi-bidi-
rectional pin that is outputting a 1. If a pin that has a logic 1 on it is pulled low by an external
device, the medium pull-up turns off, and only the weak pull-up remains on. In order to pull the
pin low under these conditions, the external device has to sink enough current to overpower the
medium pull-up and take the voltage on the port pin below its input threshold.
The third pull-up is referred to as the "strong" pull-up. This pull-up is used to speed up low-to-
high transitions on a quasi-bidirectional port pin when the port latch changes from a logic 0 to a
logic 1. When this occurs, the strong pull-up turns on for a brief time, two CPU clocks, in order to
pull the port pin high quickly. Then it turns off again.
The DPU bit (bit 7 in AUXR register) allows to disable the permanent weak pull up of all ports
when latch data is logical 0.
The quasi-bidirectional port configuration is shown in Figure 5-1.
Figure 5-1. Quasi-Bidirectional Output
2 CPU
Input
Pin
Strong Medium
N
Weak
P
Clock Delay
Port Latch
Data
Data
DPU
AUXR.7
P P
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6. Oscillator
To optimize the power consumption and execution time needed for a specific task, an internal
prescaler feature has been implemented between the oscillator and the CPU and peripherals.
6.1 Registers
Table 6-1. CKRL Register
CKRL – Clock Reload Register (97h)
Reset Value = 1111 1111b
Not bit addressable
Table 6-2. PCON Register
PCON – Power Control Register (87h)
Reset Value = 00X1 0000b Not bit addressable
7 6 5 4 3 2 1 0
CKRL7 CKRL6 CKRL5 CKRL4 CKRL3 CKRL2 CKRL1 CKRL0
Bit Number Mnemonic Description
7:0 CKRL Clock Reload Register
Prescaler value
7 6 5 4 3 2 1 0
SMOD1 SMOD0 - POF GF1 GF0 PD IDL
Bit Number Bit Mnemonic Description
7 SMOD1 Serial Port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3.
6 SMOD0
Serial Port Mode bit 0
Cleared to select SM0 bit in SCON register.
Set to select FE bit in SCON register.
5 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
4 POF
Power-off Flag
Cleared by software to recognize the next reset type.
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be
set by software.
3 GF1
General-purpose Flag
Cleared by software for general-purpose usage.
Set by software for general-purpose usage.
2 GF0
General-purpose Flag
Cleared by software for general-purpose usage.
Set by software for general-purpose usage.
1 PD
Power-down Mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
0 IDL
Idle Mode bit
Cleared by hardware when interrupt or reset occurs.
Set to enter idle mode.
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6.2 Functional Block Diagram
Figure 6-1. Functional Oscillator Block Diagram
6.2.1 Prescaler Divider
A hardware RESET puts the prescaler divider in the following state:
CKRL = FFh: F
CLK CPU
= F
CLK PERIPH
= F
OSC
/2 (Standard C51 feature)
Any value between FFh down to 00h can be written by software into CKRL register in order to
divide frequency of the selected oscillator:
CKRL = 00h: minimum frequency
F
CLK CPU
= F
CLK PERIPH
= F
OSC
/1020 (Standard Mode)
F
CLK CPU
= F
CLK PERIPH
= F
OSC
/510 (X2 Mode)
CKRL = FFh: maximum frequency
F
CLK CPU
= F
CLK PERIPH
= F
OSC
/2 (Standard Mode)
F
CLK CPU
= F
CLK PERIPH
= F
OSC
(X2 Mode)
F
CLK CPU
and F
CLK PERIPH
In X2 Mode, for CKRL<>0xFF:
In X1 Mode, for CKRL<>0xFF then:
Xtal2
Xtal1
Osc
CLK
Idle
CPU Clock
CKRL
Reload
8-bit
Prescaler-Divider
Reset
Peripheral Clock
:2
X2
0
1
FOSC
CKCON0
CLK
Periph
CPU
CKRL = 0xFF?
0
1
F
CPU
F
=
CLKP ERIPH
F
OSC
2 255 CKRL( )×
-----------------------------------------------=
F
CPU
F
=
CLKP ERIPH
F
OSC
4 255 CKRL( )×
-----------------------------------------------=
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7. Enhanced Features
In comparison to the original 80C52, the AT89C51RD2/ED2 implements some new features,
which are
:
X2 option
Dual Data Pointer
Extended RAM
Programmable Counter Array (PCA)
Hardware Watchdog
SPI interface
4-level interrupt priority system
Power-off flag
ONCE mode
ALE disabling
Some enhanced features are also located in the UART and the Timer 2
7.1 X2 Feature
The AT89C51RD2/ED2 core needs only 6 clock periods per machine cycle. This feature called
‘X2’ provides the following advantages:
Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
Save power consumption while keeping same CPU power (oscillator power saving).
Save power consumption by dividing dynamically the operating frequency by 2 in operating
and idle modes.
Increase CPU power by 2 while keeping same crystal frequency.
In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 sig-
nal and the main clock input of the core (phase generator). This divider may be disabled by
software.
7.1.1 Description
The clock for the whole circuit and peripherals is first divided by two before being used by the
CPU core and the peripherals.
This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is
bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%.
Figure 7-1 shows the clock generation block diagram. X2 bit is validated on the rising edge of
the XTAL1 ÷ 2 to avoid glitches when switching from X2 to STD mode. Figure 7-2 shows the
switching mode waveforms.
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AT89C51RD2/ED2
Figure 7-1. Clock Generation Diagram
Figure 7-2. Mode Switching Waveforms
The X2 bit in the CKCON0 register (see Table 7-1) allows a switch from 12 clock periods per
instruction to 6 clock periods and vice versa. At reset, the speed is set according to X2 bit of
Hardware Security Byte (HSB). By default, Standard mode is active. Setting the X2 bit activates
the X2 feature (X2 mode).
The T0X2, T1X2, T2X2, UartX2, PcaX2, and WdX2 bits in the CKCON0 register (Table 7-1) and
SPIX2 bit in the CKCON1 register (see Table 7-2) allows a switch from standard peripheral
speed (12 clock periods per peripheral clock cycle) to fast peripheral speed (6 clock periods per
peripheral clock cycle). These bits are active only in X2 mode.
Table 7-1. CKCON0 Register
CKCON0 - Clock Control Register (8Fh)
XTAL1 2
CKCON0
X2
8-bit Prescaler
FOSC
FXTAL
0
1
XTAL1:2
FCLK CPU
FCLK PERIPH
CKRL
XTAL1:2
XTAL1
CPU Clock
X2 Bit
X2 ModeSTD Mode STD Mode
FOSC
7 6 5 4 3 2 1 0
- WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2
Bit
Number
Bit
Mnemonic Description
7 Reserved The values for this bit are indeterminite. Do not set this bit.
6 WDX2
Watchdog Clock
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no
effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
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Reset Value = 0000 000’HSB. X2’b (See “Hardware Security Byte”)
Not bit addressable
Table 7-2. CKCON1 Register
CKCON1 - Clock Control Register (AFh)
5 PCAX2
Programmable Counter Array Clock
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no
effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
periods per peripheral clock cycle.
4 SIX2
Enhanced UART Clock (Mode 0 and 2)
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no
effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
periods per peripheral clock cycle.
3 T2X2
Timer2 Clock
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no
effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
2 T1X2
Timer1 Clock
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no
effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
periods per peripheral clock cycle.
1 T0X2
Timer0 Clock
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no
effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
periods per peripheral clock cycle.
0 X2
CPU Clock
Cleared to select 12 clock periods per machine cycle (STD mode) for CPU and all the
peripherals. Set to select 6 clock periods per machine cycle (X2 mode) and to enable the
individual peripherals’X2’ bits. Programmed by hardware after Power-up regarding
Hardware Security Byte (HSB), Default setting, X2 is cleared.
7 6 5 4 3 2 1 0
- - - - - - - SPIX2
Bit
Number
Bit
Mnemonic Description
7 - Reserved
6 - Reserved
5 - Reserved
4 - Reserved
3 - Reserved
Bit
Number
Bit
Mnemonic Description
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AT89C51RD2/ED2
Reset Value = XXXX XXX0b
Not bit addressable
2 - Reserved
1 - Reserved
0 SPIX2
SPI (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit
has no effect).
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Bit
Number
Bit
Mnemonic Description
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AT89C51RD2/ED2
8. Dual Data Pointer Register (DPTR)
The additional data pointer can be used to speed up code execution and reduce code size.
The dual DPTR structure is a way by which the chip will specify the address of an external data
memory location. There are two 16-bit DPTR registers that address the external memory, and a
single bit called DPS = AUXR1.0 (see Table 8-1) that allows the program code to switch
between them (Refer to Figure 8-1).
Figure 8-1. Use of Dual Pointer
Table 8-1. AUXR1 Register
AUXR1- Auxiliary Register 1(0A2h)
External Data Memory
AUXR1(A2H)
DPS
DPH(83H) DPL(82H)
07
DPTR0
DPTR1
7 6 5 4 3 2 1 0
- - ENBOOT - GF3 0 - DPS
Bit
Number
Bit
Mnemonic Description
7 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
6 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
5 ENBOOT
Enable Boot Flash
Cleared to disable boot ROM.
Set to map the boot ROM between F800h - 0FFFFh.
4 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
3 GF3 This bit is a general-purpose user flag.(1)
2 0 Always cleared
1 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
0 DPS
Data Pointer Selection
Cleared to select DPTR0.
Set to select DPTR1.
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AT89C51RD2/ED2
Reset Value = XXXX XX0X0b
Not bit addressable
Note: 1. Bit 2 stuck at 0; this allows to use INC AUXR1 to toggle DPS without changing GF3.
ASSEMBLY LANGUAGE
; Block move using dual data pointers
; Modifies DPTR0, DPTR1, A and PSW
; note: DPS exits opposite of entry state
; unless an extra INC AUXR1 is added
;
00A2 AUXR1 EQU 0A2H
;
0000 909000MOV DPTR,#SOURCE ; address of SOURCE
0003 05A2 INC AUXR1 ; switch data pointers
0005 90A000 MOV DPTR,#DEST ; address of DEST
0008 LOOP:
0008 05A2 INC AUXR1 ; switch data pointers
000A E0 MOVX A,@DPTR ; get a byte from SOURCE
000B A3 INC DPTR ; increment SOURCE address
000C 05A2 INC AUXR1 ; switch data pointers
000E F0 MOVX @DPTR,A ; write the byte to DEST
000F A3 INC DPTR ; increment DEST address
0010 70F6JNZ LOOP ; check for 0 terminator
0012 05A2 INC AUXR1 ; (optional) restore DPS
INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR.
However, note that the INC instruction does not directly force the DPS bit to a particular state,
but simply toggles it. In simple routines, such as the block move example, only the fact that DPS
is toggled in the proper sequence matters, not its actual value. In other words, the block move
routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruc-
tion (INC AUXR1), the routine will exit with DPS in the opposite state.
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9. Expanded RAM (XRAM)
The AT89C51RD2/ED2 provides additional on-chip random access memory (RAM) space for
increased data parameter handling and high level language usage.
AT89C51RD2/ED2 device haS expanded RAM in external data space configurable up to 1792
bytes (see Table 9-1).
The AT89C51RD2/ED2 internal data memory is mapped into four separate segments.
The four segments are:
1. The Lower 128 bytes of RAM (addresses 00h to 7Fh) are directly and indirectly
addressable.
2. The Upper 128 bytes of RAM (addresses 80h to FFh) are indirectly addressable only.
3. The Special Function Registers, SFRs, (addresses 80h to FFh) are directly address-
able only.
4. The expanded RAM bytes are indirectly accessed by MOVX instructions, and with the
EXTRAM bit cleared in the AUXR register (see Table 9-1).
The lower 128 bytes can be accessed by either direct or indirect addressing. The Upper 128
bytes can be accessed by indirect addressing only. The Upper 128 bytes occupy the same
address space as the SFR. That means they have the same address, but are physically sepa-
rate from SFR space.
Figure 9-1. Internal and External Data Memory Address
When an instruction accesses an internal location above address 7Fh, the CPU knows whether
the access is to the upper 128 bytes of data RAM or to SFR space by the addressing mode used
in the instruction.
Instructions that use direct addressing access SFR space. For example: MOV 0A0H, # data,
accesses the SFR at location 0A0h (which is P2).
Instructions that use indirect addressing access the Upper 128 bytes of data RAM. For
example: MOV @R0, # data where R0 contains 0A0h, accesses the data byte at address
0A0h, rather than P2 (whose address is 0A0h).
The XRAM bytes can be accessed by indirect addressing, with EXTRAM bit cleared and
MOVX instructions. This part of memory which is physically located on-chip, logically
occupies the first bytes of external data memory. The bits XRS0 and XRS1 are used to hide a
XRAM
Upper
128 Bytes
Internal
RAM
Lower
128 Bytes
Internal
RAM
Special
Function
Register
80h 80h
00
0FFh or 6FFh 0FFh
00
0FFh
External
Data
Memory
0000
00FFh up to 06FFh
0FFFFh
Indirect Accesses Direct Accesses
Direct or Indirect
Accesses
7Fh
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4235K–8051–05/08
AT89C51RD2/ED2
part of the available XRAM as explained in Table 9-1. This can be useful if external
peripherals are mapped at addresses already used by the internal XRAM.
With EXTRAM = 0, the XRAM is indirectly addressed, using the MOVX instruction in
combination with any of the registers R0, R1 of the selected bank or DPTR. An access to
XRAM will not affect ports P0, P2, P3.6 (WR) and P3.7 (RD). For example, with EXTRAM =
0, MOVX @R0, # data where R0 contains 0A0H, accesses the XRAM at address 0A0H
rather than external memory. An access to external data memory locations higher than the
accessible size of the XRAM will be performed with the MOVX DPTR instructions in the same
way as in the standard 80C51, with P0 and P2 as data/address busses, and P3.6 and P3.7
as write and read timing signals. Accesses to XRAM above 0FFH can only be done by the
use of DPTR.
With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard
80C51.MOVX @ Ri will provide an eight-bit address multiplexed with data on Port0 and any
output port pins can be used to output higher order address bits. This is to provide the
external paging capability. MOVX @DPTR will generate a sixteen-bit address. Port2 outputs
the high-order eight address bits (the contents of DPH) while Port0 multiplexes the low-order
eight address bits (DPL) with data. MOVX @ Ri and MOVX @DPTR will generate either read
or write signals on P3.6 (WR) and P3.7 (RD).
The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM)
internal data memory. The stack may not be located in the XRAM.
The M0 bit allows to stretch the XRAM timings; if M0 is set, the read and write pulses are
extended from 6 to 30 clock periods. This is useful to access external slow peripherals.
9.1 Registers
Table 9-1. AUXR Register
AUXR - Auxiliary Register (8Eh)
7 6 5 4 3 2 1 0
DPU - M0 XRS2 XRS1 XRS0 EXTRAM AO
Bit
Number
Bit
Mnemonic Description
7 DPU
Disable Weak Pull-up
Cleared by software to activate the permanent weak pull-up (default)
Set by software to disable the weak pull-up (reduce power consumption)
6 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
5 M0
Pulse length
Cleared to stretch MOVX control: the RD and the WR pulse length is 6 clock periods
(default).
Set to stretch MOVX control: the RD and the WR pulse length is 30 clock periods.
4 XRS2 XRAM Size
XRS2XRS1XRS0 XRAM size
0 0 0 256 bytes
0 0 1 512 bytes
0 1 0 768 bytes(default)
0 1 1 1024 bytes
1 0 0 1792 bytes
3 XRS1
2 XRS0
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AT89C51RD2/ED2
Reset Value = 0X00 1000
Not bit addressable
1 EXTRAM
EXTRAM bit
Cleared to access internal XRAM using movx @ Ri/ @ DPTR.
Set to access external memory.
Programmed by hardware after Power-up regarding Hardware Security Byte (HSB),
default setting, XRAM selected.
0 AO
ALE Output bit
Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2
mode is used). (default) Set, ALE is active only during a MOVX or MOVC instruction is
used.
Bit
Number
Bit
Mnemonic Description
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AT89C51RD2/ED2
10. Reset
10.1 Introduction
The reset sources are: Power Management, Hardware Watchdog, PCA Watchdog and Reset
input.
Figure 10-1. Reset schematic
10.2 Reset Input
The Reset input can be used to force a reset pulse longer than the internal reset controlled by
the Power Monitor. RST input has a pull-down resistor allowing power-on reset by simply con-
necting an external capacitor to V
CC
as shown in Figure 10-2. Resistor value and input
characteristics are discussed in the Section DC Characteristics of the AT89C51RD2/ED2
datasheet.
Figure 10-2. Reset Circuitry and Power-On Reset
10.3 Reset Output
Reset output can be generated by two sources:
Internal POR/PFD
Hardware watchdog timer
As detailed in Section Hardware Watchdog Timer”, page 84, the WDT generates a 96-clock
period pulse on the RST pin.
In order to properly propagate this pulse to the rest of the application in case of external capaci-
tor or power-supply supervisor circuit, a 1 k resistor must be added as shown Figure 10-3.
RST
R
RST
VSS
To internal reset
RST
VDD
+
b. Power-on Reseta. RST input circuitry
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Figure 10-3. Recommended Reset Output Schematic
RST
VDD
+
VSS
VDD
RST
1K
To other
on-board
circuitry
AT89C51XD2
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11. Power Monitor
The POR/PFD function monitors the internal power-supply of the CPU core memories and the
peripherals, and if needed, suspends their activity when the internal power supply falls below a
safety threshold. This is achieved by applying an internal reset to them.
By generating the Reset the Power Monitor insures a correct start up when AT89C51RD2/ED2
is powered up.
11.1 Description
In order to startup and maintain the microcontroller in correct operating mode, V
CC
has to be sta-
bilized in the V
CC
operating range and the oscillator has to be stabilized with a nominal amplitude
compatible with logic level VIH/VIL.
These parameters are controlled during the three phases: power-up, normal operation and
power going down. See Figure 11-1.
Figure 11-1. Power Monitor Block Diagram
Note: 1. Once XTAL1 High and low levels reach above and below VIH/VIL. a 1024 clock period delay
will extend the reset coming from the Power Fail Detect. If the power falls below the Power Fail
Detect threshold level, the Reset will be applied immediately.
The Voltage regulator generates a regulated internal supply for the CPU core the memories and
the peripherals. Spikes on the external Vcc are smoothed by the voltage regulator.
The Power fail detect monitor the supply generated by the voltage regulator and generate a
reset if this supply falls below a safety threshold as illustrated in the Figure 11-2 below.
VCC
Power On Reset
Power Fail Detect
Voltage Regulator
XTAL1
(1)
CPU core
Memories
Peripherals
Regulated
Supply
RST pin
Hardware
Watchdog
PCA
Watchdog
Internal Reset
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Figure 11-2. Power Fail Detect
When the power is applied, the Power Monitor immediately asserts a reset. Once the internal
supply after the voltage regulator reach a safety level, the power monitor then looks at the XTAL
clock input. The internal reset will remain asserted until the Xtal1 levels are above and below
VIH and VIL. Further more. An internal counter will count 1024 clock periods before the reset is
de-asserted.
If the internal power supply falls below a safety level, a reset is immediately asserted.
.
Vcc
t
Reset
Vcc
VPFDP
VPFDM
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12. Timer 2
The Timer 2 in the AT89C51RD2/ED2 is the standard C52 Timer 2. It is a 16-bit timer/counter:
the count is maintained by two eight-bit timer registers, TH2 and TL2 are cascaded. It is con-
trolled by T2CON (Table 12-1) and T2MOD (Table 12-2) registers. Timer 2 operation is similar to
Timer 0 and Timer 1. C/T2 selects F
OSC
/12 (timer operation) or external pin T2 (counter opera-
tion) as the timer clock input. Setting TR2 allows TL2 to increment by the selected input.
Timer 2 has 3 operating modes: capture, autoreload and Baud Rate Generator. These modes
are selected by the combination of RCLK, TCLK and CP/RL2 (T2CON).
Refer to the Atmel 8-bit Microcontroller Hardware Manual for the description of Capture and
Baud Rate Generator Modes.
Timer 2 includes the following enhancements:
Auto-reload mode with up or down counter
Programmable clock-output
12.1 Auto-reload Mode
The auto-reload mode configures Timer 2 as a 16-bit timer or event counter with automatic
reload. If DCEN bit in T2MOD is cleared, Timer 2 behaves as in 80C52 (refer to the Atmel C51
Microcontroller Hardware Manual). If DCEN bit is set, Timer 2 acts as an Up/down timer/counter
as shown in Figure 12-1. In this mode the T2EX pin controls the direction of count.
When T2EX is high, Timer 2 counts up. Timer overflow occurs at FFFFh which sets the TF2 flag
and generates an interrupt request. The overflow also causes the 16-bit value in RCAP2H and
RCAP2L registers to be loaded into the timer registers TH2 and TL2.
When T2EX is low, Timer 2 counts down. Timer underflow occurs when the count in the timer
registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers. The under-
flow sets TF2 flag and reloads FFFFh into the timer registers.
The EXF2 bit toggles when Timer 2 overflows or underflows according to the direction of the
count. EXF2 does not generate any interrupt. This bit can be used to provide 17-bit resolution.
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Figure 12-1. Auto-reload Mode Up/Down Counter (DCEN = 1)
12.2 Programmable
Clock-output
In the clock-out mode, Timer 2 operates as a 50% duty-cycle, programmable clock generator
(See Figure 12-2). The input clock increments TL2 at frequency F
CLK PERIPH
/2. The timer repeat-
edly counts to overflow from a loaded value. At overflow, the contents of RCAP2H and RCAP2L
registers are loaded into TH2 and TL2. In this mode, Timer 2 overflows do not generate inter-
rupts. The formula gives the clock-out frequency as a function of the system oscillator frequency
and the value in the RCAP2H and RCAP2L registers:
For a 16 MHz system clock, Timer 2 has a programmable frequency range of 61 Hz
(F
CLK PERIPH
/2
16
)
to 4 MHz (F
CLK PERIPH
/4). The generated clock signal is brought out to T2 pin
(P1.0).
Timer 2 is programmed for the clock-out mode as follows:
Set T2OE bit in T2MOD register.
Clear C/T2 bit in T2CON register.
Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L
registers.
Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the reload value
or a different one depending on the application.
To start the timer, set TR2 run control bit in T2CON register.
(DOWN COUNTING RELOAD VALUE)
C/T2
TF2
TR2
T2
EXF2
TH2
(8-bit)
TL2
(8-bit)
RCAP2H
(8-bit)
RCAP2L
(8-bit)
FFh
(8-bit)
FFh
(8-bit)
TOGGLE
(UP COUNTING RELOAD VALUE)
TIMER 2
INTERRUPT
F
CLK PERIPH
0
1
T2CON T2CON
T2CON
T2CON
T2EX:
If DCEN = 1, 1 = UP
If DCEN = 1, 0 = DOWN
If DCEN = 0, up counting
:
6
Clock OutFrequency F
CLKPERIPH
4 65536 RCAP2H RCAP2L )(×
---------------------------------------------------------------------------------------------=
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It is possible to use Timer 2 as a baud rate generator and a clock generator simultaneously. For
this configuration, the baud rates and clock frequencies are not independent since both func-
tions use the values in the RCAP2H and RCAP2L registers.
Figure 12-2. Clock-out Mode C/T2 = 0
12.3 Registers
Table 12-1. T2CON Register
T2CON - Timer 2 Control Register (C8h)
:6
EXF2
TR2
OVER-
FLOW
T2EX
TH
2
(8-bit)
TL2
(8-bit)
TIMER 2
RCAP2H
(8-bit)
RCAP2L
(8-bit)
T2OE
T2
FCLK PERIPH
T2CON
T2CON
T2CON
T2MOD
INTERRUPT
Q D
Toggle
EXEN2
7 6 5 4 3 2 1 0
TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#
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Reset Value = 0000 0000b
Bit addressable
Bit
Number
Bit
Mnemonic Description
7 TF2
Timer 2 overflow Flag
Must be cleared by software.
Set by hardware on Timer 2 overflow, if RCLK = 0 and TCLK = 0.
6 EXF2
Timer 2 External Flag
Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2
= 1.
When set, causes the CPU to vector to Timer 2 interrupt routine when Timer 2 interrupt
is enabled.
Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down counter mode
(DCEN = 1).
5 RCLK
Receive Clock bit
Cleared to use timer 1 overflow as receive clock for serial port in mode 1 or 3.
Set to use Timer 2 overflow as receive clock for serial port in mode 1 or 3.
4 TCLK
Transmit Clock bit
Cleared to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.
Set to use Timer 2 overflow as transmit clock for serial port in mode 1 or 3.
3 EXEN2
Timer 2 External Enable bit
Cleared to ignore events on T2EX pin for Timer 2 operation.
Set to cause a capture or reload when a negative transition on T2EX pin is detected, if
Timer 2 is not used to clock the serial port.
2 TR2
Timer 2 Run control bit
Cleared to turn off Timer 2.
Set to turn on Timer 2.
1 C/T2#
Timer/Counter 2 select bit
Cleared for timer operation (input from internal clock system: FCLK PERIPH).
Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for
clock out mode.
0 CP/RL2#
Timer 2 Capture/Reload bit
If RCLK = 1 or TCLK = 1, CP/RL2# is ignored and timer is forced to auto-reload on Timer
2 overflow.
Cleared to auto-reload on Timer 2 overflows or negative transitions on T2EX pin if
EXEN2=1.
Set to capture on negative transitions on T2EX pin if EXEN2 = 1.
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Table 12-2. T2MOD Register
T2MOD - Timer 2 Mode Control Register (C9h)
Reset Value = XXXX XX00b
Not bit addressable
7 6 5 4 3 2 1 0
- - - - - - T2OE DCEN
Bit
Number
Bit
Mnemonic Description
7 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
6 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
5 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
4 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
3 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
2 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
1 T2OE
Timer 2 Output Enable bit
Cleared to program P1.0/T2 as clock input or I/O port.
Set to program P1.0/T2 as clock output.
0 DCEN
Down Counter Enable bit
Cleared to disable Timer 2 as up/down counter.
Set to enable Timer 2 as up/down counter.
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13. Programmable Counter Array (PCA)
The PCA provides more timing capabilities with less CPU intervention than the standard
timer/counters. Its advantages include reduced software overhead and improved accuracy. The
PCA consists of a dedicated timer/counter which serves as the time base for an array of five
compare/capture modules. Its clock input can be programmed to count any one of the following
signals:
Peripheral clock frequency (F
CLK PERIPH
)
÷
6
Peripheral clock frequency (F
CLK PERIPH
)
÷
2
Timer 0 overflow
External input on ECI (P1.2)
Each compare/capture module can be programmed in any one of the following modes:
Rising and/or falling edge capture
Software timer
High-speed output
Pulse width modulator
Module 4 can also be programmed as a watchdog timer (see Section "PCA Watchdog Timer",
page 46).
When the compare/capture modules are programmed in the capture mode, software timer, or
high speed output mode, an interrupt can be generated when the module executes its function.
All five modules plus the PCA timer overflow share one interrupt vector.
The PCA timer/counter and compare/capture modules share Port 1 for external I/O. These pins
are listed below. If one or several bits in the port are not used for the PCA, they can still be used
for standard I/O.
The PCA timer is a common time base for all five modules (see Figure 13-1). The timer count
source is determined from the CPS1 and CPS0 bits in the CMOD register (Table 13-1) and can
be programmed to run at:
1/6 the
peripheral clock frequency (F
CLK PERIPH
)
1/2 the
peripheral clock frequency (F
CLK PERIPH
)
The Timer 0 overflow
The input on the ECI pin (P1.2)
The CMOD register includes three additional bits associated with the PCA (See Figure 13-1 and
Table 13-1).
The CIDL bit which allows the PCA to stop during idle mode.
The WDTE bit which enables or disables the watchdog function on module 4.
PCA Component External I/O Pin
16-bit Counter P1.2/ECI
16-bit Module 0 P1.3/CEX0
16-bit Module 1 P1.4/CEX1
16-bit Module 2 P1.5/CEX2
16-bit Module 3 P1.6/CEX3
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The ECF bit which when set causes an interrupt and the PCA overflow flag CF (in the CCON
SFR) to be set when the PCA timer overflows.
Figure 13-1. PCA Timer/Counter
CIDL CPS1 CPS0 ECF
IT
CH CL
16 Bit Up Counter
To PCA
Modules
FCLK PERIPH/6
FCLK PERIPH/2
T0 OVF
P1.2
Idle
CMOD
0xD9
WDTE
CF CR CCON
0xD8
CCF4 CCF3 CCF2 CCF1 CCF0
Overflow
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Table 13-1. CMOD Register
CMOD - PCA Counter Mode Register (D9h)
Reset Value = 00XX X000b
Not bit addressable
The CCON register contains the run control bit for the PCA and the flags for the PCA timer (CF)
and each module (Refer to Table 13-2).
Bit CR (CCON.6) must be set by software to run the PCA. The PCA is shut off by clearing this
bit.
Bit CF: The CF bit (CCON.7) is set when the PCA counter overflows and an interrupt will be
generated if the ECF bit in the CMOD register is set. The CF bit can only be cleared by
software.
Bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and
are set by hardware when either a match or a capture occurs. These flags also can only be
cleared by software.
7 6 5 4 3 2 1 0
CIDL WDTE - - - CPS1 CPS0 ECF
Bit
Number
Bit
Mnemonic Description
7 CIDL
Counter Idle Control
Cleared to program the PCA Counter to continue functioning during idle Mode.
Set to program PCA to be gated off during idle.
6 WDTE
Watchdog Timer Enable
Cleared to disable Watchdog Timer function on PCA Module 4.
Set to enable Watchdog Timer function on PCA Module 4.
5 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
4 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
3 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
2 CPS1 PCA Count Pulse Select
CPS1CPS0 Selected PCA input
0 0 Internal clock FCLK PERIPH/6
0 1 Internal clock FCLK PERIPH/2
1 0 Timer 0 Overflow
1 1 External clock at ECI/P1.2 pin (max rate = FCLK PERIPH/4)
1 CPS0
0 ECF
PCA Enable Counter Overflow Interrupt
Cleared to disable CF bit in CCON to inhibit an interrupt.
Set to enable CF bit in CCON to generate an interrupt.
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Table 13-2. CCON Register
CCON - PCA Counter Control Register (D8h)
Reset Value = 00X0 0000b
Bit addressable
The watchdog timer function is implemented in Module 4 (See Figure 13-4).
The PCA interrupt system is shown in Figure 13-2.
7 6 5 4 3 2 1 0
CF CR - CCF4 CCF3 CCF2 CCF1 CCF0
Bit
Number
Bit
Mnemonic Description
7 CF
PCA Counter Overflow flag
Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is
set. CF
may be set by either hardware or software but can only be cleared by software.
6 CR
PCA Counter Run control bit
Must be cleared by software to turn the PCA counter off.
Set by software to turn the PCA counter on.
5 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
4 CCF4
PCA Module 4 interrupt flag
Must be cleared by software.
Set by hardware when a match or capture occurs.
3 CCF3
PCA Module 3 interrupt flag
Must be cleared by software.
Set by hardware when a match or capture occurs.
2 CCF2
PCA Module 2 interrupt flag
Must be cleared by software.
Set by hardware when a match or capture occurs.
1 CCF1
PCA Module 1 interrupt flag
Must be cleared by software.
Set by hardware when a match or capture occurs.
0 CCF0
PCA Module 0 interrupt flag
Must be cleared by software.
Set by hardware when a match or capture occurs.
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Figure 13-2. PCA Interrupt System
PCA Modules: each one of the five compare/capture modules has six possible functions. It can
perform:
16-bit Capture, positive-edge triggered
16-bit Capture, negative-edge triggered
16-bit Capture, both positive and negative-edge triggered
16-bit Software Timer
16-bit High Speed Output
8-bit Pulse Width Modulator
In addition, Module 4 can be used as a Watchdog Timer.
Each module in the PCA has a special function register associated with it. These registers are:
CCAPM0 for Module 0, CCAPM1 for Module 1, etc. (See Table 13-3). The registers contain the
bits that control the mode that each module will operate in.
The ECCF bit (CCAPMn.0 where n = 0, 1, 2, 3, or 4 depending on the module) enables the
CCF flag in the CCON SFR to generate an interrupt when a match or compare occurs in the
associated module.
PWM (CCAPMn.1) enables the pulse width modulation mode.
The TOG bit (CCAPMn.2) when set causes the CEX output associated with the module to
toggle when there is a match between the PCA counter and the modules capture/compare
register.
The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON register to be
set when there is a match between the PCA counter and the modules capture/compare
register.
The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge that a
capture input will be active on. The CAPN bit enables the negative edge, and the CAPP bit
enables the positive edge. If both bits are set both edges will be enabled and a capture will
occur for either transition.
The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function.
CF CR CCON
0xD8
CCF4 CCF3 CCF2 CCF1 CCF0
Module 4
Module 3
Module 2
Module 1
Module 0
ECF
PCA Timer/Counter
ECCFn CCAPMn.0CMOD.0 IEN0.6 IEN0.7
To Interrupt
Priority Decoder
EC EA
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Table 13-3 shows the CCAPMn settings for the various PCA functions.
Table 13-3. CCAPMn Registers (n = 0-4)
CCAPM0 - PCA Module 0 Compare/Capture Control Register (0DAh)
CCAPM1 - PCA Module 1 Compare/Capture Control Register (0DBh)
CCAPM2 - PCA Module 2 Compare/Capture Control Register (0DCh)
CCAPM3 - PCA Module 3 Compare/Capture Control Register (0DDh)
CCAPM4 - PCA Module 4 Compare/Capture Control Register (0DEh)
Reset Value = X000 0000b
Not bit addressable
7 6 5 4 3 2 1 0
- ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
Bit
Number
Bit
Mnemonic Description
7 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
6 ECOMn
Enable Comparator
Cleared to disable the comparator function.
Set to enable the comparator function.
5 CAPPn
Capture Positive
Cleared to disable positive edge capture.
Set to enable positive edge capture.
4 CAPNn
Capture Negative
Cleared to disable negative edge capture.
Set to enable negative edge capture.
3 MATn
Match
When MATn = 1, a match of the PCA counter with this module's compare/capture
register causes the CCFn bit in CCON to be set, flagging an interrupt.
2 TOGn
Toggle
When TOGn = 1, a match of the PCA counter with this module's compare/capture
register causes the CEXn pin to toggle.
1 PWMn
Pulse Width Modulation Mode
Cleared to disable the CEXn pin to be used as a pulse width modulated output.
Set to enable the CEXn pin to be used as a pulse width modulated output.
0 CCF0
Enable CCF interrupt
Cleared to disable compare/capture flag CCFn in the CCON register to generate an
interrupt.
Set to enable compare/capture flag CCFn in the CCON register to generate an interrupt.
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Table 13-4. PCA Module Modes (CCAPMn Registers)
There are two additional registers associated with each of the PCA modules. They are CCAPnH
and CCAPnL and these are the registers that store the 16-bit count when a capture occurs or a
compare should occur. When a module is used in the PWM mode these registers are used to
control the duty cycle of the output (See Table 13-5 & Table 13-6).
Table 13-5. CCAPnH Registers (n = 0 - 4)
CCAP0H - PCA Module 0 Compare/Capture Control Register High (0FAh)
CCAP1H - PCA Module 1 Compare/Capture Control Register High (0FBh)
CCAP2H - PCA Module 2 Compare/Capture Control Register High (0FCh)
CCAP3H - PCA Module 3 Compare/Capture Control Register High (0FDh)
CCAP4H - PCA Module 4 Compare/Capture Control Register High (0FEh)
Reset Value = 0000 0000b
Not bit addressable
ECOMn CAPPn CAPNn MATn TOGn PWMm ECCFn Module Function
0 0 0 0 0 0 0 No Operation
X 1 0 0 0 0 X 16-bit capture by a positive-edge
trigger on CEXn
X 0 1 0 0 0 X 16-bit capture by a negative trigger on
CEXn
X 1 1 0 0 0 X 16-bit capture by a transition on CEXn
1 0 0 1 0 0 X 16-bit Software Timer/Compare mode.
1 0 0 1 1 0 X 16-bit High Speed Output
1 0 0 0 0 1 0 8-bit PWM
1 0 0 1 X 0 X Watchdog Timer (module 4 only)
7 6 5 4 3 2 1 0
--------
Bit
Number
Bit
Mnemonic Description
7 - 0 - PCA Module n Compare/Capture Control
CCAPnH Value
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Table 13-6. CCAPnL Registers (n = 0 - 4)
CCAP0L - PCA Module 0 Compare/Capture Control Register Low (0EAh)
CCAP1L - PCA Module 1 Compare/Capture Control Register Low (0EBh)
CCAP2L - PCA Module 2 Compare/Capture Control Register Low (0ECh)
CCAP3L - PCA Module 3 Compare/Capture Control Register Low (0EDh)
CCAP4L - PCA Module 4 Compare/Capture Control Register Low (0EEh)
Reset Value = 0000 0000b
Not bit addressable
Table 13-7. CH Register
CH - PCA Counter Register High (0F9h)
Reset Value = 0000 0000b
Not bit addressable
Table 13-8. CL Register
CL - PCA Counter Register Low (0E9h)
Reset Value = 0000 0000b
Not bit addressable
7 6 5 4 3 2 1 0
--------
Bit
Number
Bit
Mnemonic Description
7 - 0 - PCA Module n Compare/Capture Control
CCAPnL Value
7 6 5 4 3 2 1 0
--------
Bit
Number
Bit
Mnemonic Description
7 - 0 - PCA counter
CH Value
7 6 5 4 3 2 1 0
--------
Bit
Number
Bit
Mnemonic Description
7 - 0 - PCA Counter
CL Value
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13.1 PCA Capture Mode
To use one of the PCA modules in the capture mode either one or both of the CCAPM bits
CAPN and CAPP for that module must be set. The external CEX input for the module (on port 1)
is sampled for a transition. When a valid transition occurs the PCA hardware loads the value of
the PCA counter registers (CH and CL) into the module's capture registers (CCAPnL and
CCAPnH). If the CCFn bit for the module in the CCON SFR and the ECCFn bit in the CCAPMn
SFR are set then an interrupt will be generated (Refer to Figure 13-3).
Figure 13-3. PCA Capture Mode
13.2 16-bit Software Timer/ Compare Mode
The PCA modules can be used as software timers by setting both the ECOM and MAT bits in
the modules CCAPMn register. The PCA timer will be compared to the module's capture regis-
ters and when a match occurs an interrupt will occur if the CCFn (CCON SFR) and the ECCFn
(CCAPMn SFR) bits for the module are both set (See Figure 13-4).
CF CR CCON
0xD8
CH CL
CCAPnH CCAPnL
CCF4 CCF3 CCF2 CCF1 CCF0
PCA IT
PCA Counter/Timer
ECOMn CCAPMn, n= 0 to 4
0xDA to 0xDE
CAPNn MATn TOGn PWMn ECCFnCAPPn
Cex.n
Capture
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Figure 13-4. PCA Compare Mode and PCA Watchdog Timer
Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, other-
wise an unwanted match could happen. Writing to CCAPnH will set the ECOM bit.
Once ECOM is set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t occur
while modifying the compare value. Writing to CCAPnH will set ECOM. For this reason, user
software should write CCAPnL first, and then CCAPnH. Of course, the ECOM bit can still be
controlled by accessing to CCAPMn register.
13.3 High Speed Output Mode
In this mode the CEX output (on port 1) associated with the PCA module will toggle each time a
match occurs between the PCA counter and the modules capture registers. To activate this
mode the TOG, MAT, and ECOM bits in the module's CCAPMn SFR must be set (See
Figure 13-5).
A prior write must be done to CCAPnL and CCAPnH before writing the ECOMn bit.
CH CL
CCAPnH CCAPnL
ECOMn CCAPMn, n = 0 to 4
0xDA to 0xDE
CAPNn MATn TOGn PWMn ECCFnCAPPn
16 bit comparator
Match
CCON
0xD8
PCA IT
Enable
PCA counter/timer
RESET *
CIDL CPS1 CPS0 ECF CMOD
0xD9
WDTE
Reset
Write to
CCAPnL
Write to
CCAPnH
CF CCF2 CCF1 CCF0
CR CCF3CCF4
1 0
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Figure 13-5. PCA High Speed Output Mode
Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, other-
wise an unwanted match could happen.
Once ECOM is set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t occur
while modifying the compare value. Writing to CCAPnH will set ECOM. For this reason, user
software should write CCAPnL first, and then CCAPnH. Of course, the ECOM bit can still be
controlled by accessing to CCAPMn register.
13.4 Pulse Width Modulator Mode
All of the PCA modules can be used as PWM outputs. Figure 13-6 shows the PWM function.
The frequency of the output depends on the source for the PCA timer. All of the modules will
have the same frequency of output because they all share the PCA timer. The duty cycle of each
module is independently variable using the modules capture register CCAPLn. When the value
of the PCA CL SFR is less than the value in the modules CCAPLn SFR the output will be low,
when it is equal to or greater than the output will be high. When CL overflows from FF to 00,
CCAPLn is reloaded with the value in CCAPHn. This allows updating the PWM without glitches.
The PWM and ECOM bits in the module's CCAPMn register must be set to enable the PWM
mode.
CH CL
CCAPnH CCAPnL
ECOMn CCAPMn, n = 0 to 4
0xDA to 0xDE
CAPNn MATn TOGn PWMn ECCFnCAPPn
16 bit comparator Match
CF CR
CCON
0xD8
CCF4 CCF3 CCF2 CCF1 CCF0
PCA IT
Enable
CEXn
PCA counter/timer
Write to
CCAPnH
Reset
Write to
CCAPnL
10
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Figure 13-6. PCA PWM Mode
13.5 PCA Watchdog Timer
An on-board watchdog timer is available with the PCA to improve the reliability of the system
without increasing chip count. Watchdog timers are useful for systems that are susceptible to
noise, power glitches, or electrostatic discharge. Module 4 is the only PCA module that can be
programmed as a watchdog. However, this module can still be used for other modes if the
watchdog is not needed. Figure 13-4 shows a diagram of how the watchdog works. The user
pre-loads a 16-bit value in the compare registers. Just like the other compare modes, this 16-bit
value is compared to the PCA timer value. If a match is allowed to occur, an internal reset will be
generated. This will not cause the RST pin to be driven high.
In order to hold off the reset, the user has three options:
1. Periodically change the compare value so it will never match the PCA timer.
2. Periodically change the PCA timer value so it will never match the compare values.
3. Disable the watchdog by clearing the WDTE bit before a match occurs and then re-
enable it.
CL
CCAPnH
CCAPnL
ECOMn CCAPMn, n= 0 to 4
0xDA to 0xDE
CAPNn MATn TOGn PWMn ECCFnCAPPn
8-bit Comparator
CEXn
“0”
“1”
Enable
PCA Counter/Timer
Overflow
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The first two options are more reliable because the watchdog timer is never disabled as in option
#3. If the program counter ever goes astray, a match will eventually occur and cause an internal
reset. The second option is also not recommended if other PCA modules are being used.
Remember, the PCA timer is the time base for all modules; changing the time base for other
modules would not be a good idea. Thus, in most applications the first solution is the best option.
This watchdog timer won’t generate a reset out on the reset pin.
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14. Serial I/O Port
The serial I/O port in the AT89C51RD2/ED2 is compatible with the serial I/O port in the 80C52.
It provides both synchronous and asynchronous communication modes. It operates as a Univer-
sal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and
3). Asynchronous transmission and reception can occur simultaneously and at different baud
rates
Serial I/O port includes the following enhancements:
Framing error detection
Automatic address recognition
14.1 Framing Error Detection
Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To
enable the framing bit error detection feature, set SMOD0 bit in PCON register (See Figure 14-
1).
Figure 14-1. Framing Error Block Diagram
When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit.
An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by
two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in SCON register (See Table
14-4.) bit is set.
Software may examine FE bit after each reception to check for data errors. Once set, only soft-
ware or a reset can clear FE bit. Subsequently received frames with valid stop bits cannot clear
FE bit. When FE feature is enabled, RI rises on stop bit instead of the last data bit (See Figure
14-2. and Figure 14-3.).
Figure 14-2. UART Timings in Mode 1
RITIRB8TB8RENSM2SM1SM0/FE
IDLPDGF0GF1POF-SMOD0SMOD1
To UART framing error control
SM0 to UART mode control (SMOD0 = 0)
Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1)
SCON (98h)
PCON (87h)
Data byte
RI
SMOD0=X
Stop
bit
Start
bit
RXD D7D6D5D4D3D2D1D0
FE
SMOD0=1
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Figure 14-3. UART Timings in Modes 2 and 3
14.2 Automatic Address Recognition
The automatic address recognition feature is enabled when the multiprocessor communication
feature is enabled (SM2 bit in SCON register is set).
Implemented in hardware, automatic address recognition enhances the multiprocessor commu-
nication feature by allowing the serial port to examine the address of each incoming command
frame. Only when the serial port recognizes its own address, the receiver sets RI bit in SCON
register to generate an interrupt. This ensures that the CPU is not interrupted by command
frames addressed to other devices.
If desired, the user may enable the automatic address recognition feature in mode 1.In this con-
figuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the received
command frame address matches the device’s address and is terminated by a valid stop bit.
To support automatic address recognition, a device is identified by a given address and a broad-
cast address.
Note: The multiprocessor communication and automatic address recognition features cannot be
enabled in mode 0 (i. e. setting SM2 bit in SCON register in mode 0 has no effect).
14.2.1 Given Address
Each device has an individual address that is specified in SADDR register; the SADEN register
is a mask byte that contains dont-care bits (defined by zeros) to form the devices given
address. The don’t-care bits provide the flexibility to address one or more slaves at a time. The
following example illustrates how a given address is formed.
To address a device by its individual address, the SADEN mask byte must be 1111 1111b.
For example:
SADDR0101 0110b
SADEN1111 1100b
Given0101 01XXb
The following is an example of how to use given addresses to address different slaves:
Slave A:SADDR1111 0001b
SADEN1111 1010b
Given1111 0X0Xb
Slave B:SADDR1111 0011b
SADEN1111 1001b
Given1111 0XX1b
RI
SMOD0=0
Data byte Ninth
bit
Stop
bit
Start
bit
RXD D8D7D6D5D4D3D2D1D0
RI
SMOD0=1
FE
SMOD0=1
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Slave C:SADDR1111 0010b
SADEN1111 1101b
Given1111 00X1b
The SADEN byte is selected so that each slave may be addressed separately.
For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1.To communicate
with slave A only, the master must send an address where bit 0 is clear (e. g. 1111 0000b).
For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves
B and C, but not slave A, the master must send an address with bits 0 and 1 both set (e. g. 1111
0011b).
To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1
clear, and bit 2 clear (e. g. 1111 0001b).
14.2.2 Broadcast Address
A broadcast address is formed from the logical OR of the SADDR and SADEN registers with
zeros defined as don’t-care bits, e. g. :
SADDR0101 0110b
SADEN1111 1100b
Broadcast =SADDR OR SADEN1111 111Xb
The use of don’t-care bits provides flexibility in defining the broadcast address, however in most
applications, a broadcast address is FFh. The following is an example of using broadcast
addresses:
Slave A:SADDR1111 0001b
SADEN1111 1010b
Broadcast1111 1X11b,
Slave B:SADDR1111 0011b
SADEN1111 1001b
Broadcast1111 1X11B,
Slave C:SADDR=1111 0011b
SADEN1111 1101b
Broadcast1111 1111b
For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of
the slaves, the master must send an address FFh. To communicate with slaves A and B, but not
slave C, the master can send and address FBh.
14.2.3 Reset Addresses
On reset, the SADDR and SADEN registers are initialized to 00h, i. e. the given and broadcast
addresses are XXXX XXXXb (all don’t-care bits). This ensures that the serial port will reply to any
address, and so, that it is backwards compatible with the 80C51 microcontrollers that do not
support automatic address recognition.
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14.3 Registers
Table 14-1. SADEN Register
SADEN - Slave Address Mask Register (B9h)
Reset Value = 0000 0000b
Not bit addressable
Table 14-2. SADDR Register
SADDR - Slave Address Register (A9h)
Reset Value = 0000 0000b
Not bit addressable
14.4 Baud Rate Selection for UART for Mode 1 and 3
The Baud Rate Generator for transmit and receive clocks can be selected separately via the
T2CON and BDRCON registers.
Figure 14-4. Baud Rate Selection
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
RCLK
/ 16
RBCK
INT_BRG
0
1
TIMER1
0
1
0
1
TIMER2
INT_BRG
TIMER1
TIMER2
TIMER_BRG_RX
Rx Clock
/ 16
0
1
TIMER_BRG_TX
Tx Clock
TBCK
TCLK
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Table 14-3. Baud Rate Selection Table UART
14.4.1 Internal Baud Rate Generator (BRG)
When the internal Baud Rate Generator is used, the Baud Rates are determined by the BRG
overflow depending on the BRL reload value, the value of SPD bit (Speed Mode) in BDRCON
register and the value of the SMOD1 bit in PCON register.
Figure 14-5. Internal Baud Rate
The baud rate for UART is token by formula:
TCLK
(T2CON)
RCLK
(T2CON)
TBCK
(BDRCON)
RBCK
(BDRCON)
Clock Source
UART Tx
Clock Source
UART Rx
0 0 0 0 Timer 1 Timer 1
1 0 0 0 Timer 2 Timer 1
0 1 0 0 Timer 1 Timer 2
1 1 0 0 Timer 2 Timer 2
X 0 1 0 INT_BRG Timer 1
X 1 1 0 INT_BRG Timer 2
0 X 0 1 Timer 1 INT_BRG
1 X 0 1 Timer 2 INT_BRG
X X 1 1 INT_BRG INT_BRG
0
1
Overflow
SPD
BDRCON.1
BRG
(8 bits)
BRL
(8 bits)
FClk Periph ÷ 6
BRR
BDRCON.4
0
1
SMOD1
PCON.7
÷ 2
INT_BRG
Baud_Rate = 6(1-SPD) 32 (256 -BRL)
2SMOD1 FPER
BRL = 256 - 6(1-SPD) 32 Baud_Rate
2SMOD1 FPER
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Table 14-4. SCON Register
SCON - Serial Control Register (98h)
Reset Value = 0000 0000b
Bit addressable
7 6 5 4 3 2 1 0
FE/SM0 SM1 SM2 REN TB8 RB8 TI RI
Bit
Number
Bit
Mnemonic Description
7
FE
Framing Error bit (SMOD0=1)
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
SMOD0 must be set to enable access to the FE bit.
SM0
Serial port Mode bit 0
Refer to SM1 for serial port mode selection.
SMOD0 must be cleared to enable access to the SM0 bit.
6 SM1
Serial port Mode bit 1
SM0SM1Mode Baud Rate
0 0 Shift Register FXTAL/12 (or FXTAL /6 in mode X2)
0 1 8-bit UART Variable
1 0 9-bit UARTFXTAL/64 or FXTAL/32
1 1 9-bit UARTVariable
5 SM2
Serial port Mode 2 bit / Multiprocessor Communication Enable bit
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3, and
eventually mode 1.This bit should be cleared in mode 0.
4 REN
Reception Enable bit
Clear to disable serial reception.
Set to enable serial reception.
3 TB8
Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
2 RB8
Receiver Bit 8 / Ninth bit received in modes 2 and 3
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.
1 TI
Transmit Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the
stop bit in the other modes.
0 RI
Receive Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 14-2. and
Figure 14-3. in the other modes.
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Table 14-5. Example of Computed Value When X2=1, SMOD1=1, SPD=1
Table 14-6. Example of Computed Value When X2=0, SMOD1=0, SPD=0
The baud rate generator can be used for mode 1 or 3 (refer to Figure 14-4.), but also for mode 0
for UART, thanks to the bit SRC located in BDRCON register (Table 14-13.)
14.5 UART Registers
Table 14-7. SADEN Register
SADEN - Slave Address Mask Register for UART (B9h)
Reset Value = 0000 0000b
Table 14-8. SADDR Register
SADDR - Slave Address Register for UART (A9h)
Reset Value = 0000 0000b
Baud Rates FOSC = 16. 384 MHz FOSC = 24MHz
BRL Error (%) BRL Error (%)
115200 247 1.23 243 0.16
57600 238 1.23 230 0.16
38400 229 1.23 217 0.16
28800 220 1.23 204 0.16
19200 203 0.63 178 0.16
9600 149 0.31 100 0.16
4800 43 1.23 - -
Baud Rates FOSC = 16. 384 MHz FOSC = 24MHz
BRL Error (%) BRL Error (%)
4800 247 1.23 243 0.16
2400 238 1.23 230 0.16
1200 220 1.23 202 3.55
600 185 0.16 152 0.16
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
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Table 14-9. SBUF Register
SBUF - Serial Buffer Register for UART (99h)
Reset Value = XXXX XXXXb
Table 14-10. BRL Register
BRL - Baud Rate Reload Register for the internal baud rate generator, UART (9Ah)
Reset Value = 0000 0000b
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
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Table 14-11. T2CON Register
T2CON - Timer 2 Control Register (C8h)
Reset Value = 0000 0000b
Bit addressable
7 6 5 4 3 2 1 0
TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#
Bit
Number
Bit
Mnemonic Description
7 TF2
Timer 2 overflow Flag
Must be cleared by software.
Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0.
6 EXF2
Timer 2 External Flag
Set when a capture or a reload is caused by a negative transition on T2EX pin if
EXEN2=1.
When set, causes the CPU to vector to timer 2 interrupt routine when timer 2 interrupt is
enabled.
Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down counter
mode (DCEN = 1)
5 RCLK
Receive Clock bit for UART
Cleared to use timer 1 overflow as receive clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3.
4 TCLK
Transmit Clock bit for UART
Cleared to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3.
3 EXEN2
Timer 2 External Enable bit
Cleared to ignore events on T2EX pin for timer 2 operation.
Set to cause a capture or reload when a negative transition on T2EX pin is detected, if
timer 2 is not used to clock the serial port.
2 TR2
Timer 2 Run control bit
Cleared to turn off timer 2.
Set to turn on timer 2.
1 C/T2#
Timer/Counter 2 select bit
Cleared for timer operation (input from internal clock system: FCLK PERIPH).
Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for
clock out mode.
0 CP/RL2#
Timer 2 Capture/Reload bit
If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2
overflow.
Cleared to auto-reload on timer 2 overflows or negative transitions on T2EX pin if
EXEN2=1.
Set to capture on negative transitions on T2EX pin if EXEN2=1.
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Table 14-12. PCON Register
PCON - Power Control Register (87h)
Reset Value = 00X1 0000b
Not bit addressable
Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn’t affect
the value of this bit.
7 6 5 4 3 2 1 0
SMOD1 SMOD0 - POF GF1 GF0 PD IDL
Bit
Number
Bit
Mnemonic Description
7 SMOD1 Serial port Mode bit 1 for UART
Set to select double baud rate in mode 1, 2 or 3.
6 SMOD0
Serial port Mode bit 0 for UART
Cleared to select SM0 bit in SCON register.
Set to select FE bit in SCON register.
5 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
4 POF
Power-Off Flag
Cleared to recognize next reset type.
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by
software.
3 GF1
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
2 GF0
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
1 PD
Power-Down mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
0 IDL
Idle mode bit
Cleared by hardware when interrupt or reset occurs.
Set to enter idle mode.
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Table 14-13. BDRCON Register
BDRCON - Baud Rate Control Register (9Bh)
Reset Value = XXX0 0000b
Not bit addressable
7 6 5 4 3 2 1 0
- - - BRR TBCK RBCK SPD SRC
Bit
Number
Bit
Mnemonic Description
7 - Reserved
The value read from this bit is indeterminate. Do not set this bit
6 - Reserved
The value read from this bit is indeterminate. Do not set this bit
5 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
4 BRR
Baud Rate Run Control bit
Cleared to stop the internal Baud Rate Generator.
Set to start the internal Baud Rate Generator.
3 TBCK
Transmission Baud rate Generator Selection bit for UART
Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator.
Set to select internal Baud Rate Generator.
2 RBCK
Reception Baud Rate Generator Selection bit for UART
Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator.
Set to select internal Baud Rate Generator.
1 SPD
Baud Rate Speed Control bit for UART
Cleared to select the SLOW Baud Rate Generator.
Set to select the FAST Baud Rate Generator.
0 SRC
Baud Rate Source select bit in Mode 0 for UART
Cleared to select FOSC/12 as the Baud Rate Generator (FCLK PERIPH/6 in X2 mode).
Set to select the internal Baud Rate Generator for UARTs in mode 0.
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15. Keyboard Interface
The AT89C51RD2/ED2 implements a keyboard interface allowing the connection of a
8 x n matrix keyboard. It is based on 8 inputs with programmable interrupt capability on both
high or low level. These inputs are available as alternate function of P1 and allow to exit from
idle and power-down modes.
The keyboard interfaces with the C51 core through 3 special function registers: KBLS, the Key-
board Level Selection register (Table 15-3), KBE, the Keyboard interrupt Enable register
(Table 15-2), and KBF, the Keyboard Flag register (Table 15-1).
15.0.1 Interrupt
The keyboard inputs are considered as 8 independent interrupt sources sharing the same inter-
rupt vector. An interrupt enable bit (KBD in IE1) allows global enable or disable of the keyboard
interrupt (see Figure 15-1). As detailed in Figure 15-2 each keyboard input has the capability to
detect a programmable level according to KBLS. x bit value. Level detection is then reported in
interrupt flags KBF.x that can be masked by software using KBE. x bits.
This structure allow keyboard arrangement from 1 by n to 8 by n matrix and allows usage of P1
inputs for other purpose.
Figure 15-1. Keyboard Interface Block Diagram
Figure 15-2. Keyboard Input Circuitry
15.0.2 Power Reduction Mode
P1 inputs allow exit from idle and power-down modes as detailed in Section Power Manage-
ment”, page 80.
P1:x
KBE.x
KBF.x
KBLS.x
0
1
Vcc
Internal Pullup
P1.0
Keyboard Interface
Interrupt Request
KBD
IE1
Input Circuitry
P1.1 Input Circuitry
P1.2 Input Circuitry
P1.3 Input Circuitry
P1.4 Input Circuitry
P1.5 Input Circuitry
P1.6 Input Circuitry
P1.7 Input Circuitry
KBDIT
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15.1 Registers
Table 15-1. KBF Register
KBF-Keyboard Flag Register (9Eh)
Reset Value = 0000 0000b
This register is read only access, all flags are automatically cleared by reading the register.
7 6 5 4 3 2 1 0
KBF7 KBF6 KBF5 KBF4 KBF3 KBF2 KBF1 KBF0
Bit Number
Bit
Mnemonic Description
7 KBF7
Keyboard line 7 flag
Set by hardware when the Port line 7 detects a programmed level. It generates a
Keyboard interrupt request if the KBKBIE.7 bit in KBIE register is set.
Must be cleared by software.
6 KBF6
Keyboard line 6 flag
Set by hardware when the Port line 6 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.6 bit in KBIE register is set.
Must be cleared by software.
5 KBF5
Keyboard line 5 flag
Set by hardware when the Port line 5 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.5 bit in KBIE register is set.
Must be cleared by software.
4 KBF4
Keyboard line 4 flag
Set by hardware when the Port line 4 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.4 bit in KBIE register is set.
Must be cleared by software.
3 KBF3
Keyboard line 3 flag
Set by hardware when the Port line 3 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.3 bit in KBIE register is set.
Must be cleared by software.
2 KBF2
Keyboard line 2 flag
Set by hardware when the Port line 2 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.2 bit in KBIE register is set.
Must be cleared by software.
1 KBF1
Keyboard line 1 flag
Set by hardware when the Port line 1 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.1 bit in KBIE register is set.
Must be cleared by software.
0 KBF0
Keyboard line 0 flag
Set by hardware when the Port line 0 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.0 bit in KBIE register is set.
Must be cleared by software.
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Table 15-2. KBE Register
KBE-Keyboard Input Enable Register (9Dh)
Reset Value = 0000 0000b
7 6 5 4 3 2 1 0
KBE7 KBE6 KBE5 KBE4 KBE3 KBE2 KBE1 KBE0
Bit
Number
Bit
Mnemonic Description
7 KBE7
Keyboard line 7 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.7 bit in KBF register to generate an interrupt request.
6 KBE6
Keyboard line 6 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.6 bit in KBF register to generate an interrupt request.
5 KBE5
Keyboard line 5 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.5 bit in KBF register to generate an interrupt request.
4 KBE4
Keyboard line 4 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.4 bit in KBF register to generate an interrupt request.
3 KBE3
Keyboard line 3 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.3 bit in KBF register to generate an interrupt request.
2 KBE2
Keyboard line 2 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.2 bit in KBF register to generate an interrupt request.
1 KBE1
Keyboard line 1 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.1 bit in KBF register to generate an interrupt request.
0 KBE0
Keyboard line 0 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.0 bit in KBF register to generate an interrupt request.
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Table 15-3. KBLS Register
KBLS-Keyboard Level Selector Register (9Ch)
Reset Value = 0000 0000b
7 6 5 4 3 2 1 0
KBLS7 KBLS6 KBLS5 KBLS4 KBLS3 KBLS2 KBLS1 KBLS0
Bit Number
Bit
Mnemonic Description
7 KBLS7
Keyboard line 7 Level Selection bit
Cleared to enable a low level detection on Port line 7.
Set to enable a high level detection on Port line 7.
6 KBLS6
Keyboard line 6 Level Selection bit
Cleared to enable a low level detection on Port line 6.
Set to enable a high level detection on Port line 6.
5 KBLS5
Keyboard line 5 Level Selection bit
Cleared to enable a low level detection on Port line 5.
Set to enable a high level detection on Port line 5.
4 KBLS4
Keyboard line 4 Level Selection bit
Cleared to enable a low level detection on Port line 4.
Set to enable a high level detection on Port line 4.
3 KBLS3
Keyboard line 3 Level Selection bit
Cleared to enable a low level detection on Port line 3.
Set to enable a high level detection on Port line 3.
2 KBLS2
Keyboard line 2 Level Selection bit
Cleared to enable a low level detection on Port line 2.
Set to enable a high level detection on Port line 2.
1 KBLS1
Keyboard line 1 Level Selection bit
Cleared to enable a low level detection on Port line 1.
Set to enable a high level detection on Port line 1.
0 KBLS0
Keyboard line 0 Level Selection bit
Cleared to enable a low level detection on Port line 0.
Set to enable a high level detection on Port line 0.
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16. Serial Port Interface (SPI)
The Serial Peripheral Interface Module (SPI) allows full-duplex, synchronous, serial communica-
tion between the MCU and peripheral devices, including other MCUs.
16.1 Features
Features of the SPI Module include the following:
Full-duplex, three-wire synchronous transfers
Master or Slave operation
Eight programmable Master clock rates
Serial clock with programmable polarity and phase
Master Mode fault error flag with MCU interrupt capability
Write collision flag protection
16.2 Signal Description
Figure 16-1 shows a typical SPI bus configuration using one Master controller and many Slave
peripherals. The bus is made of three wires connecting all the devices.
Figure 16-1. SPI Master/Slaves Interconnection
The Master device selects the individual Slave devices by using four pins of a parallel port to
control the four SS pins of the Slave devices.
16.2.1 Master Output Slave Input (MOSI)
This 1-bit signal is directly connected between the Master Device and a Slave Device. The MOSI
line is used to transfer data in series from the Master to the Slave. Therefore, it is an output sig-
nal from the Master, and an input signal to a Slave. A Byte (8-bit word) is transmitted most
significant bit (MSB) first, least significant bit (LSB) last.
16.2.2 Master Input Slave Output (MISO)
This 1-bit signal is directly connected between the Slave Device and a Master Device. The MISO
line is used to transfer data in series from the Slave to the Master. Therefore, it is an output sig-
nal from the Slave, and an input signal to the Master. A Byte (8-bit word) is transmitted most
significant bit (MSB) first, least significant bit (LSB) last.
Slave 1
MISO
MOSI
SCK
SS
MISO
MOSI
SCK
SS
PORT
0
1
2
3
Slave 3
MISO
MOSI
SCK
SS
Slave 4
MISO
MOSI
SCK
SS
Slave 2
MISO
MOSI
SCK
SS
VDD
Master
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16.2.3 SPI Serial Clock (SCK)
This signal is used to synchronize the data movement both in and out of the devices through
their MOSI and MISO lines. It is driven by the Master for eight clock cycles which allows to
exchange one Byte on the serial lines.
16.2.4 Slave Select (SS)
Each Slave peripheral is selected by one Slave Select pin (SS). This signal must stay low for any
message for a Slave. It is obvious that only one Master (SS high level) can drive the network.
The Master may select each Slave device by software through port pins (Figure 16-2). To pre-
vent bus conflicts on the MISO line, only one slave should be selected at a time by the Master
for a transmission.
In a Master configuration, the SS line can be used in conjunction with the MODF flag in the SPI
Status register (SPSTA) to prevent multiple masters from driving MOSI and SCK (see Error
conditions).
A high level on the SS pin puts the MISO line of a Slave SPI in a high-impedance state.
The SS pin could be used as a general-purpose if the following conditions are met:
The device is configured as a Master and the SSDIS control bit in SPCON is set. This kind of
configuration can be found when only one Master is driving the network and there is no way
that the SS pin could be pulled low. Therefore, the MODF flag in the SPSTA will never be
set
(1)
.
The Device is configured as a Slave with CPHA and SSDIS control bits set
(2)
. This kind of
configuration can happen when the system comprises one Master and one Slave only.
Therefore, the device should always be selected and there is no reason that the Master uses
the SS pin to select the communicating Slave device.
Note: 1. Clearing SSDIS control bit does not clear MODF.
2. Special care should be taken not to set SSDIS control bit when CPHA = ’0’ because in this
mode, the SS is used to start the transmission.
16.2.5 Baud Rate
In Master mode, the baud rate can be selected from a baud rate generator which is controlled by
three bits in the SPCON register: SPR2, SPR1 and SPR0.The Master clock is selected from one
of seven clock rates resulting from the division of the internal clock by 2, 4, 8, 16, 32, 64 or 128.
Table 16-1 gives the different clock rates selected by SPR2:SPR1:SPR0.
Table 16-1. SPI Master Baud Rate Selection
SPR2 SPR1 SPR0 Clock Rate Baud Rate Divisor (BD)
0 0 0 FCLK PERIPH /2 2
0 0 1 FCLK PERIPH /4 4
0 1 0 FCLK PERIPH/8 8
0 1 1 FCLK PERIPH /16 16
1 0 0 FCLK PERIPH /32 32
1 0 1 FCLK PERIPH /64 64
1 1 0 FCLK PERIPH /128 128
1 1 1 Don’t Use No BRG
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16.3 Functional Description
Figure 16-2 shows a detailed structure of the SPI Module.
Figure 16-2. SPI Module Block Diagram
16.3.1 Operating Modes
The Serial Peripheral Interface can be configured in one of the two modes: Master mode or
Slave mode. The configuration and initialization of the SPI Module is made through one register:
The Serial Peripheral Control register (SPCON)
Once the SPI is configured, the data exchange is made using:
SPCON
The Serial Peripheral STAtus register (SPSTA)
The Serial Peripheral DATa register (SPDAT)
During an SPI transmission, data is simultaneously transmitted (shifted out serially) and
received (shifted in serially). A serial clock line (SCK) synchronizes shifting and sampling on the
two serial data lines (MOSI and MISO). A Slave Select line (SS) allows individual selection of a
Slave SPI device; Slave devices that are not selected do not interfere with SPI bus activities.
When the Master device transmits data to the Slave device via the MOSI line, the Slave device
responds by sending data to the Master device via the MISO line. This implies full-duplex trans-
mission with both data out and data in synchronized with the same clock (Figure 16-3).
Shift Register
01
234567
Internal Bus
Pin
Control
Logic
MISO
MOSI
SCK
M
S
Clock
Logic
Clock
Divider
Clock
Select
/4
/64
/128
SPI Interrupt Request
8-bit bus
1-bit signal
SS
FCLK PERIPH
/32
/8
/16
Receive Data Register
SPDAT
SPI
Control
SPSTA
CPHA SPR0
SPR1
CPOLMSTRSSDISSPEN
SPR2
SPCON
WCOL MODFSPIF - - - - -
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Figure 16-3. Full-Duplex Master-Slave Interconnection
16.3.1.1 Master Mode
The SPI operates in Master mode when the Master bit, MSTR
(1)
, in the SPCON register is set.
Only one Master SPI device can initiate transmissions. Software begins the transmission from a
Master SPI Module by writing to the Serial Peripheral Data Register (SPDAT). If the shift register
is empty, the Byte is immediately transferred to the shift register. The Byte begins shifting out on
MOSI pin under the control of the serial clock, SCK. Simultaneously, another Byte shifts in from
the Slave on the Master’s MISO pin. The transmission ends when the Serial Peripheral transfer
data flag, SPIF, in SPSTA becomes set. At the same time that SPIF becomes set, the received
Byte from the Slave is transferred to the receive data register in SPDAT. Software clears SPIF
by reading the Serial Peripheral Status register (SPSTA) with the SPIF bit set, and then reading
the SPDAT.
16.3.1.2 Slave Mode
The SPI operates in Slave mode when the Master bit, MSTR
(2)
, in the SPCON register is
cleared. Before a data transmission occurs, the Slave Select pin, SS, of the Slave device must
be set to ’0’. SS must remain low until the transmission is complete.
In a Slave SPI Module, data enters the shift register under the control of the SCK from the Mas-
ter SPI Module. After a Byte enters the shift register, it is immediately transferred to the receive
data register in SPDAT, and the SPIF bit is set. To prevent an overflow condition, Slave software
must then read the SPDAT before another Byte enters the shift register
(3)
. A Slave SPI must
complete the write to the SPDAT (shift register) at least one bus cycle before the Master SPI
starts a transmission. If the write to the data register is late, the SPI transmits the data already in
the shift register from the previous transmission. The maximum SCK frequency allowed in slave
mode is
FCLK PERIPH /4.
16.3.2 Transmission Formats
Software can select any of four combinations of serial clock (SCK) phase and polarity using two
bits in the SPCON: the Clock Polarity (CPOL
(4)
) and the Clock Phase (CPHA
4
). CPOL defines
the default SCK line level in idle state. It has no significant effect on the transmission format.
CPHA defines the edges on which the input data are sampled and the edges on which the out-
put data are shifted (Figure 16-4 and Figure 16-5). The clock phase and polarity should be
identical for the Master SPI device and the communicating Slave device.
8-bit Shift register
SPI
Clock Generator
Master MCU
8-bit Shift register
MISOMISO
MOSI MOSI
SCK SCK
VSS
VDD SSSS
Slave MCU
1. The SPI Module should be configured as a Master before it is enabled (SPEN set). Also, the Mas-
ter SPI should be configured before the Slave SPI.
2. The SPI Module should be configured as a Slave before it is enabled (SPEN set).
3. The maximum frequency of the SCK for an SPI configured as a Slave is the bus clock speed.
4. Before writing to the CPOL and CPHA bits, the SPI should be disabled (SPEN = ’0’).
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Figure 16-4. Data Transmission Format (CPHA = 0)
Figure 16-5. Data Transmission Format (CPHA = 1)
Figure 16-6. CPHA/SS Timing
As shown in Figure 16-4, the first SCK edge is the MSB capture strobe. Therefore, the Slave
must begin driving its data before the first SCK edge, and a falling edge on the SS pin is used to
start the transmission. The SS pin must be toggled high and then low between each Byte trans-
mitted (Figure 16-6).
Figure 16-5 shows an SPI transmission in which CPHA is ’1’. In this case, the Master begins
driving its MOSI pin on the first SCK edge. Therefore, the Slave uses the first SCK edge as a
start transmission signal. The SS pin can remain low between transmissions (Figure 16-6). This
format may be preferred in systems having only one Master and only one Slave driving the
MISO data line.
16.3.3 Error Conditions
The following flags in the SPSTA signal SPI error conditions:
MSB bit6 bit5 bit4 bit3 bit2 bit1 LSB
bit6 bit5 bit4 bit3 bit2 bit1MSB LSB
1 32 4 5 6 7 8
Capture Point
SS (to Slave)
MISO (from Slave)
MOSI (from Master)
SCK (CPOL = 1)
SCK (CPOL = 0)
SPEN (Internal)
SCK Cycle Number
MSB bit6 bit5 bit4 bit3 bit2 bit1 LSB
bit6 bit5 bit4 bit3 bit2 bit1
MSB LSB
1 32 4 5 6 7 8
Capture Point
SS (to Slave)
MISO (from Slave)
MOSI (from Master)
SCK (CPOL = 1)
SCK (CPOL = 0)
SPEN (Internal)
SCK Cycle Number
Byte 1 Byte 2 Byte 3
MISO/MOSI
Master SS
Slave SS
(CPHA = 1)
Slave SS
(CPHA = 0)
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16.3.3.1 Mode Fault (MODF)
Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS) pin is
inconsistent with the actual mode of the device. MODF is set to warn that there may be a multi-
master conflict for system control. In this case, the SPI system is affected in the following ways:
An SPI receiver/error CPU interrupt request is generated
The SPEN bit in SPCON is cleared. This disables the SPI
The MSTR bit in SPCON is cleared
When SS Disable (SSDIS) bit in the SPCON register is cleared, the MODF flag is set when the
SS signal becomes ’0’.
However, as stated before, for a system with one Master, if the SS pin of the Master device is
pulled low, there is no way that another Master attempts to drive the network. In this case, to
prevent the MODF flag from being set, software can set the SSDIS bit in the SPCON register
and therefore making the SS pin as a general-purpose I/O pin.
Clearing the MODF bit is accomplished by a read of SPSTA register with MODF bit set, followed
by a write to the SPCON register. SPEN Control bit may be restored to its original set state after
the MODF bit has been cleared.
16.3.3.2 Write Collision (WCOL)
A Write Collision (WCOL) flag in the SPSTA is set when a write to the SPDAT register is done
during a transmit sequence.
WCOL does not cause an interruption, and the transfer continues uninterrupted.
Clearing the WCOL bit is done through a software sequence of an access to SPSTA and an
access to SPDAT.
16.3.3.3 Overrun Condition
An overrun condition occurs when the Master device tries to send several data Bytes and the
Slave devise has not cleared the SPIF bit issuing from the previous data Byte transmitted. In this
case, the receiver buffer contains the Byte sent after the SPIF bit was last cleared. A read of the
SPDAT returns this Byte. All others Bytes are lost.
This condition is not detected by the SPI peripheral.
16.3.3.4 SS Error Flag (SSERR)
A Synchronous Serial Slave Error occurs when SS goes high before the end of a received data
in slave mode. SSERR does not cause in interruption, this bit is cleared by writing 0 to SPEN bit
(reset of the SPI state machine).
16.3.4 Interrupts
Two SPI status flags can generate a CPU interrupt requests:
Table 16-2. SPI Interrupts
Flag Request
SPIF (SP data transfer) SPI Transmitter Interrupt request
MODF (Mode Fault) SPI Receiver/Error Interrupt Request (if SSDIS = ’0’)
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Serial Peripheral data transfer flag, SPIF: This bit is set by hardware when a transfer has been
completed. SPIF bit generates transmitter CPU interrupt requests.
Mode Fault flag, MODF: This bit becomes set to indicate that the level on the SS is inconsistent
with the mode of the SPI. MODF with SSDIS reset, generates receiver/error CPU interrupt
requests. When SSDIS is set, no MODF interrupt request is generated.
Figure 16-7 gives a logical view of the above statements.
Figure 16-7. SPI Interrupt Requests Generation
16.3.5 Registers
There are three registers in the Module that provide control, status and data storage functions. These registers are
describes in the following paragraphs.
16.3.5.1 Serial Peripheral Control Register (SPCON)
The Serial Peripheral Control Register does the following:
Selects one of the Master clock rates
Configure the SPI Module as Master or Slave
Selects serial clock polarity and phase
Enables the SPI Module
Frees the SS pin for a general-purpose
Table 16-3 describes this register and explains the use of each bit
Table 16-3. SPCON Register
SPCON - Serial Peripheral Control Register (0C3H)
SSDIS
MODF
CPU Interrupt Request
SPI Receiver/error
CPU Interrupt Request
SPI Transmitter SPI
CPU Interrupt Request
SPIF
7 6 5 4 3 2 1 0
SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0
Bit Number Bit Mnemonic Description
7 SPR2 Serial Peripheral Rate 2
Bit with SPR1 and SPR0 define the clock rate.
6 SPEN
Serial Peripheral Enable
Cleared to disable the SPI interface.
Set to enable the SPI interface.
5 SSDIS
SS Disable
Cleared to enable SS in both Master and Slave modes.
Set to disable SS in both Master and Slave modes. In Slave mode, this bit
has no effect if CPHA =’0’. When SSDIS is set, no MODF interrupt request
is generated
.
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Reset Value = 0001 0100b
Not bit addressable
16.3.5.2 Serial Peripheral Status Register (SPSTA)
The Serial Peripheral Status Register contains flags to signal the following conditions:
Data transfer complete
Write collision
Inconsistent logic level on SS pin (mode fault error)
Table 16-4 describes the SPSTA register and explains the use of every bit in the register.
Table 16-4. SPSTA Register
SPSTA - Serial Peripheral Status and Control register (0C4H)
4 MSTR
Serial Peripheral Master
Cleared to configure the SPI as a Slave.
Set to configure the SPI as a Master.
3 CPOL
Clock Polarity
Cleared to have the SCK set to ’0’ in idle state.
Set to have the SCK set to ’1’ in idle low.
2 CPHA
Clock Phase
Cleared to have the data sampled when the SCK leaves the idle state (see
CPOL).
Set to have the data sampled when the SCK returns to idle state (see
CPOL).
1SPR1
SPR2 SPR1 SPR0 Serial Peripheral Rate
0 0 1 FCLK PERIPH /2
0 0 1 FCLK PERIPH /4
0 1 0 FCLK PERIPH /8
0 1 1FCLK PERIPH /16
1 0 0FCLK PERIPH /32
1 0 1FCLK PERIPH /64
1 1 0FCLK PERIPH /128
1 1 1Invalid
SPR0
Bit Number Bit Mnemonic Description
7 6 5 4 3 2 1 0
SPIF WCOL SSERR MODF - - - -
Bit Number
Bit
Mnemonic Description
7 SPIF
Serial Peripheral Data Transfer Flag
Cleared by hardware to indicate data transfer is in progress or has been approved by a
clearing sequence.
Set by hardware to indicate that the data transfer has been completed.
6 WCOL
Write Collision Flag
Cleared by hardware to indicate that no collision has occurred or has been approved by a
clearing sequence.
Set by hardware to indicate that a collision has been detected.
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Reset Value = 00X0 XXXXb
Not Bit addressable
16.3.5.3 Serial Peripheral DATa Register (SPDAT)
The Serial Peripheral Data Register (Table 16-5) is a read/write buffer for the receive data regis-
ter. A write to SPDAT places data directly into the shift register. No transmit buffer is available in
this model.
A Read of the SPDAT returns the value located in the receive buffer and not the content of the
shift register.
Table 16-5. SPDAT Register
SPDAT - Serial Peripheral Data Register (0C5H)
Reset Value = Indeterminate
R7:R0: Receive data bits
SPCON, SPSTA and SPDAT registers may be read and written at any time while there is no on-
going exchange. However, special care should be taken when writing to them while a transmis-
sion is on-going:
Do not change SPR2, SPR1 and SPR0
Do not change CPHA and CPOL
Do not change MSTR
Clearing SPEN would immediately disable the peripheral
Writing to the SPDAT will cause an overflow.
5 SSERR
Synchronous Serial Slave Error Flag
Set by hardware when SS is de-asserted before the end of a received data.
Cleared by disabling the SPI (clearing SPEN bit in SPCON).
4 MODF
Mode Fault
Cleared by hardware to indicate that the SS pin is at appropriate logic level, or has been
approved by a clearing sequence.
Set by hardware to indicate that the SS pin is at inappropriate logic level.
3 - Reserved
The value read from this bit is indeterminate. Do not set this bit
2 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
1 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
0 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
Bit Number
Bit
Mnemonic Description
7 6 5 4 3 2 1 0
R7 R6 R5 R4 R3 R2 R1 R0
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17. Interrupt System
The AT89C51RD2/ED2 has a total of 9 interrupt vectors: two external interrupts (INT0 and
INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt, SPI interrupt, Keyboard
interrupt and the PCA global interrupt. These interrupts are shown in Figure 17-1.
Figure 17-1. Interrupt Control System
Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit
in the Interrupt Enable register (Table 17-4 and Table 17-6). This register also contains a global
disable bit, which must be cleared to disable all interrupts at once.
Each interrupt source can also be individually programmed to one out of four priority levels by
setting or clearing a bit in the Interrupt Priority register (Table 17-7) and in the Interrupt Priority
High register (Table 17-5 and Table 17-6) shows the bit values and priority levels associated
with each combination.
IE1
0
3
High Priority
Interrupt
Interrupt
Polling
Sequence, Decreasing from
High to Low Priority
Low Priority
Interrupt
Global Disable
Individual Enable
EXF2
TF2
TI
RI
TF0
INT0
INT1
TF1
IPH, IPL
IE0
0
3
0
3
0
3
0
3
0
3
0
3
PCA IT
KBD IT
SPI IT
0
3
0
3
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17.1 Registers
The PCA interrupt vector is located at address 0033H, the SPI interrupt vector is located at
address 004BH and Keyboard interrupt vector is located at address 003BH. All other vectors
addresses are the same as standard C52 devices.
Table 17-1. Priority Level Bit Values
A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-prior-
ity interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source.
If two interrupt requests of different priority levels are received simultaneously, the request of
higher priority level is serviced. If interrupt requests of the same priority level are received simul-
taneously, an internal polling sequence determines which request is serviced. Thus within each
priority level there is a second priority structure determined by the polling sequence.
17.2 Interrupt Sources and Vector Addresses
Table 17-2. Interrupt Sources and Vector Addresses
IPH.x IPL.x Interrupt Level Priority
0 0 0 (Lowest)
011
102
1 1 3 (Highest)
Number Polling Priority Interrupt Source
Interrupt
Request
Vector
Address
0 0 Reset 0000h
1 1 INT0 IE0 0003h
2 2 Timer 0 TF0 000Bh
3 3 INT1 IE1 0013h
4 4 Timer 1 IF1 001Bh
5 6 UART RI+TI 0023h
6 7 Timer 2 TF2+EXF2 002Bh
7 5 PCA CF + CCFn (n = 0 - 4) 0033h
8 8 Keyboard KBDIT 003Bh
9 9 - - 0043h
10 10 SPI SPIIT 004Bh
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Table 17-3. IENO Register
IEN0 - Interrupt Enable Register (A8h)
Reset Value = 0000 0000b
Bit addressable
7 6 5 4 3 2 1 0
EA EC ET2 ES ET1 EX1 ET0 EX0
Bit
Number
Bit
Mnemonic Description
7 EA
Enable All interrupt bit
Cleared to disable all interrupts.
Set to enable all interrupts.
6 EC
PCA interrupt enable bit
Cleared to disable.
Set to enable.
5 ET2
Timer 2 overflow interrupt Enable bit
Cleared to disable timer 2 overflow interrupt.
Set to enable timer 2 overflow interrupt.
4 ES
Serial port Enable bit
Cleared to disable serial port interrupt.
Set to enable serial port interrupt.
3 ET1
Timer 1 overflow interrupt Enable bit
Cleared to disable timer 1 overflow interrupt.
Set to enable timer 1 overflow interrupt.
2 EX1
External interrupt 1 Enable bit
Cleared to disable external interrupt 1.
Set to enable external interrupt 1.
1 ET0
Timer 0 overflow interrupt Enable bit
Cleared to disable timer 0 overflow interrupt.
Set to enable timer 0 overflow interrupt.
0 EX0
External interrupt 0 Enable bit
Cleared to disable external interrupt 0.
Set to enable external interrupt 0.
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Table 17-4. IPL0 Register
IPL0 - Interrupt Priority Register (B8h)
Reset Value = X000 0000b
Bit addressable
7 6 5 4 3 2 1 0
- PPCL PT2L PSL PT1L PX1L PT0L PX0L
Bit
Number
Bit
Mnemonic Description
7 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6 PPCL
PCA interrupt Priority bit
Refer to PPCH for priority level.
5 PT2L
Timer 2 overflow interrupt Priority bit
Refer to PT2H for priority level.
4 PSL
Serial port Priority bit
Refer to PSH for priority level.
3 PT1L
Timer 1 overflow interrupt Priority bit
Refer to PT1H for priority level.
2 PX1L
External interrupt 1 Priority bit
Refer to PX1H for priority level.
1 PT0L
Timer 0 overflow interrupt Priority bit
Refer to PT0H for priority level.
0 PX0L
External interrupt 0 Priority bit
Refer to PX0H for priority level.
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Table 17-5. IPH0 Register
IPH0 - Interrupt Priority High Register (B7h)
Reset Value = X000 0000b
Not bit addressable
7 6 5 4 3 2 1 0
- PPCH PT2H PSH PT1H PX1H PT0H PX0H
Bit
Number
Bit
Mnemonic Description
7 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6 PPCH
PCA interrupt Priority high bit.
PPCHPPCL Priority Level
0 0 Lowest
0 1
1 0
1 1Highest
5 PT2H
Timer 2 overflow interrupt Priority High bit
PT2HPT2L Priority Level
0 0Lowest
0 1
1 0
1 1Highest
4 PSH
Serial port Priority High bit
PSH PSLPriority Level
0 0Lowest
0 1
1 0
1 1Highest
3 PT1H
Timer 1 overflow interrupt Priority High bit
PT1HPT1L Priority Level
0 0 Lowest
0 1
1 0
1 1 Highest
2 PX1H
External interrupt 1 Priority High bit
PX1HPX1LPriority Level
0 0Lowest
0 1
1 0
1 1Highest
1 PT0H
Timer 0 overflow interrupt Priority High bit
PT0HPT0LPriority Level
0 0Lowest
0 1
1 0
1 1Highest
0 PX0H
External interrupt 0 Priority High bit
PX0H PX0LPriority Level
0 0Lowest
0 1
1 0
1 1Highest
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Table 17-6. IEN1 Register
IEN1 - Interrupt Enable Register (B1h)
Reset Value = XXXX X000b
Bit addressable
7 6 5 4 3 2 1 0
- - - - - ESPI - KBD
Bit
Number
Bit
Mnemonic Description
7 -
Reserved
6 -
Reserved
5 -
Reserved
4 -
Reserved
3 -
Reserved
2 ESPI
SPI interrupt Enable bit
Cleared to disable SPI interrupt.
Set to enable SPI interrupt.
1
Reserved
0 KBD
Keyboard interrupt Enable bit
Cleared to disable keyboard interrupt.
Set to enable keyboard interrupt.
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Table 17-7. IPL1 Register
IPL1 - Interrupt Priority Register (B2h)
Reset Value = XXXX X000b
Bit addressable
7 6 5 4 3 2 1 0
- - - - - SPIL TWIL KBDL
Bit
Number
Bit
Mnemonic Description
7 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2 SPIL
SPI interrupt Priority bit
Refer to SPIH for priority level.
1 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
0 KBDL
Keyboard interrupt Priority bit
Refer to KBDH for priority level.
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Table 17-8. IPH1 Register
IPH1 - Interrupt Priority High Register (B3h)
Reset Value = XXXX X000b
Not bit addressable
7 6 5 4 3 2 1 0
- - - - - SPIH - KBDH
Bit
Number
Bit
Mnemonic Description
7 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2 SPIH
SPI interrupt Priority High bit
SPIHSPILPriority Level
0 0 Lowest
0 1
1 0
1 1 Highest
1 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
0 KBDH
Keyboard interrupt Priority High bit
KB DHKBDLPriority Level
0 0 Lowest
0 1
1 0
1 1 Highest
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18. Power Management
18.1 Introduction
Two power reduction modes are implemented in the AT89C51RD2/ED2. The Idle mode and the
Power-Down mode. These modes are detailed in the following sections. In addition to these
power reduction modes, the clocks of the core and peripherals can be dynamically divided by 2
using the X2 mode detailed in Section “Enhanced Features”, page 17.
18.2 Idle Mode
Idle mode is a power reduction mode that reduces the power consumption. In this mode, pro-
gram execution halts. Idle mode freezes the clock to the CPU at known states while the
peripherals continue to be clocked. The CPU status before entering Idle mode is preserved, i.e.,
the program counter and program status word register retain their data for the duration of Idle
mode. The contents of the
SFRs
and RAM are also retained. The status of the Port pins during
Idle mode is detailed in Table 18-1.
18.2.1 Entering Idle Mode
To enter Idle mode, set the IDL bit in PCON register (see Table 18-2). The AT89C51RD2/ED2
enters Idle mode upon execution of the instruction that sets IDL bit. The instruction that sets IDL
bit is the last instruction executed.
Note: If IDL bit and PD bit are set simultaneously, the AT89C51RD2/ED2 enters Power-Down mode.
Then it does not go in Idle mode when exiting Power-Down mode.
18.2.2 Exiting Idle Mode
There are two ways to exit Idle mode:
1. Generate an enabled interrupt.
Hardware clears IDL bit in PCON register which restores the clock to the CPU.
Execution resumes with the interrupt service routine. Upon completion of the
interrupt service routine, program execution resumes with the instruction
immediately following the instruction that activated Idle mode. The general purpose
flags (GF1 and GF0 in PCON register) may be used to indicate whether an interrupt
occurred during normal operation or during Idle mode. When Idle mode is exited by
an interrupt, the interrupt service routine may examine GF1 and GF0.
2. Generate a reset.
A logic high on the RST pin clears IDL bit in PCON register directly and
asynchronously. This restores the clock to the CPU. Program execution momentarily
resumes with the instruction immediately following the instruction that activated the
Idle mode and may continue for a number of clock cycles before the internal reset
algorithm takes control. Reset initializes the AT89C51RD2/ED2 and vectors the CPU
to address C:0000h.
Note: During the time that execution resumes, the internal RAM cannot be accessed; however, it is pos-
sible for the Port pins to be accessed. To avoid unexpected outputs at the Port pins, the instruction
immediately following the instruction that activated Idle mode should not write to a Port pin or to
the external RAM.
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18.3 Power-Down Mode
The Power-Down mode places the AT89C51RD2/ED2 in a very low power state. Power-Down
mode stops the oscillator, freezes all clock at known states. The CPU status prior to entering
Power-Down mode is preserved, i.e., the program counter, program status word register retain
their data for the duration of Power-Down mode. In addition, the
SFR
and RAM contents are pre-
served. The status of the Port pins during Power-Down mode is detailed in Table 18-1.
Note: VCC may be reduced to as low as V
RET
during Power-Down mode to further reduce power dissi-
pation. Take care, however, that VDD is not reduced until Power-Down mode is invoked.
18.3.1 Entering Power-Down Mode
To enter Power-Down mode, set PD bit in PCON register. The AT89C51RD2/ED2 enters the
Power-Down mode upon execution of the instruction that sets PD bit. The instruction that sets
PD bit is the last instruction executed.
18.3.2 Exiting Power-Down Mode
Note: If VCC was reduced during the Power-Down mode, do not exit Power-Down mode until VCC is
restored to the normal operating level.
There are three ways to exit the Power-Down mode:
1. Generate an enabled external interrupt.
The AT89C51RD2/ED2 provides capability to exit from Power-Down using INT0#,
INT1#.
Hardware clears PD bit in PCON register which starts the oscillator and restores the
clocks to the CPU and peripherals. Using INTx# input, execution resumes when the
input is released (see Figure 18-1). Execution resumes with the interrupt service
routine. Upon completion of the interrupt service routine, program execution
resumes with the instruction immediately following the instruction that activated
Power-Down mode.
Note: The external interrupt used to exit Power-Down mode must be configured as level sensitive
(INT0# and INT1#) and must be assigned the highest priority. In addition, the duration of the inter-
rupt must be long enough to allow the oscillator to stabilize. The execution will only resume when
the interrupt is deasserted.
Note: Exit from power-down by external interrupt does not affect the
SFRs
nor the internal RAM content.
Figure 18-1. Power-Down Exit Waveform Using INT1:0#
2. Generate a reset.
A logic high on the RST pin clears PD bit in PCON register directly and
asynchronously. This starts the oscillator and restores the clock to the CPU and
peripherals. Program execution momentarily resumes with the instruction
immediately following the instruction that activated Power-Down mode and may
INT1:0#
OSC
Power-down phase Oscillator restart phase Active phaseActive phase
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continue for a number of clock cycles before the internal reset algorithm takes
control. Reset initializes the AT89C51RD2/ED2 and vectors the CPU to address
0000h.
3. Generate an enabled external Keyboard interrupt (same behavior as external interrupt).
Note: During the time that execution resumes, the internal RAM cannot be accessed; however, it is pos-
sible for the Port pins to be accessed. To avoid unexpected outputs at the Port pins, the instruction
immediately following the instruction that activated the Power-Down mode should not write to a
Port pin or to the external RAM.
Note: Exit from power-down by reset redefines all the
SFRs
, but does not affect the internal RAM
content.
Table 18-1. Pin Conditions in Special Operating Modes
Mode Port 0 Port 1 Port 2 Port 3 Port 4 ALE PSEN#
Reset Floating High High High High High High
Idle (internal
code) Data Data Data Data Data High High
Idle (external
code) Floating Data Data Data Data High High
Power-Down
(internal
code)
Data Data Data Data Data Low Low
Power-Down
(external
code)
Floating Data Data Data Data Low Low
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18.4 Registers
Table 18-2. PCON Register
PCON (S87:h) Power configuration Register
Reset Value= XXXX 0000b
7 6 5 4 3 2 1 0
- - - - GF1 GF0 PD IDL
Bit Number
Bit
Mnemonic Description
7-4 -
Reserved
The value read from these bits is indeterminate. Do not set these bits.
3 GF1
General Purpose flag 1
One use is to indicate whether an interrupt occurred during normal operation or during
Idle mode.
2 GF0
General Purpose flag 0
One use is to indicate whether an interrupt occurred during normal operation or during
Idle mode.
1 PD
Power-Down Mode bit
Cleared by hardware when an interrupt or reset occurs.
Set to activate the Power-Down mode.
If IDL and PD are both set, PD takes precedence.
0 IDL
Idle Mode bit
Cleared by hardware when an interrupt or reset occurs.
Set to activate the Idle mode.
If IDL and PD are both set, PD takes precedence.
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19. Hardware Watchdog Timer
The WDT is intended as a recovery method in situations where the CPU may be subjected to
software upset. The WDT consists of a 14-bit counter and the Watchdog Timer ReSeT
(WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable the WDT, user
must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When WDT is
enabled, it will increment every machine cycle while the oscillator is running and there is no way
to disable the WDT except through reset (either hardware reset or WDT overflow reset). When
WDT overflows, it will drive an output RESET HIGH pulse at the RST-pin.
19.1 Using the WDT
To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR loca-
tion 0A6H. When WDT is enabled, the user needs to service it by writing to 01EH and 0E1H to
WDTRST to avoid WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH)
and this will reset the device. When WDT is enabled, it will increment every machine cycle while
the oscillator is running. This means the user must reset the WDT at least every 16383 machine
cycle. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write
only register. The WDT counter cannot be read or written. When WDT overflows, it will generate
an output RESET pulse at the RST-pin. The RESET pulse duration is 96 x T
CLK PERIPH
, where
T
CLK PERIPH
= 1/F
CLK PERIPH
. To make the best use of the WDT, it should be serviced in those sec-
tions of code that will periodically be executed within the time required to prevent a WDT reset.
To have a more powerful WDT, a 2
7
counter has been added to extend the Time-out capability,
ranking from 16 ms to 2s @ F
OSCA
= 12 MHz. To manage this feature, refer to WDTPRG register
description, Table 19-1. The WDTPRG register should be configured before the WDT activation
sequence, and can not be modified until next reset.
Table 19-1. WDTRST Register
WDTRST - Watchdog Reset Register (0A6h)
Reset Value = XXXX XXXXb
Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in sequence.
7 6 5 4 3 2 1 0
--------
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Table 19-2. WDTPRG Register
WDTPRG - Watchdog Timer Out Register (0A7h)
Reset Value = XXXX X000
19.2 WDT during Power-down and Idle
In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-
down mode the user does not need to service the WDT. There are 2 methods of exiting Power-
down mode: by a hardware reset or via a level activated external interrupt which is enabled prior
to entering Power-down mode. When Power-down is exited with hardware reset, servicing the
WDT should occur as it normally should whenever the AT89C51RD2/ED2 is reset. Exiting
Power-down with an interrupt is significantly different. The interrupt is held low long enough for
the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent
the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until
the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service
routine.
To ensure that the WDT does not overflow within a few states of exiting of powerdown, it is bet-
ter to reset the WDT just before entering powerdown.
In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the
AT89C51RD2/ED2 while in Idle mode, the user should always set up a timer that will periodically
exit Idle, service the WDT, and re-enter Idle mode.
7 6 5 4 3 2 1 0
- - - - - S2 S1 S0
Bit
Number
Bit
Mnemonic Description
7 -
Reserved
The value read from this bit is undetermined. Do not try to set this bit.
6 -
5 -
4 -
3 -
2 S2
WDT Time-out select bit 2
1 S1
WDT Time-out select bit 1
0 S0
WDT Time-out select bit 0
S2 S1 S0Selected Time-out
0 00 (2
14
- 1) machine cycles, 16. 3 ms @ F
OSCA
=12 MHz
0 01 (2
15
- 1) machine cycles, 32.7 ms @ F
OSCA
=12 MHz
0 10 (2
16
- 1) machine cycles, 65. 5 ms @ F
OSCA
=12 MHz
0 11 (2
17
- 1) machine cycles, 131 ms @ F
OSCA
=12 MHz
1 00 (2
18
- 1) machine cycles, 262 ms @ F
OSCA
=12 MHz
1 01 (2
19
- 1) machine cycles, 542 ms @ F
OSCA
=12 MHz
1 10 (2
20
- 1) machine cycles, 1.05 ms @ F
OSCA
=12 MHz
1 11 (2
21
- 1) machine cycles, 2.09 ms @ F
OSCA
=12 MHz
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20. ONCE
®
Mode (ON- Chip Emulation)
The ONCE mode facilitates testing and debugging of systems using AT89C51RD2/ED2 without
removing the circuit from the board. The ONCE mode is invoked by driving certain pins of the
AT89C51RD2/ED2; the following sequence must be exercised:
Pull ALE low while the device is in reset (RST high) and PSEN is high.
Hold ALE low as RST is deactivated.
While the AT89C51RD2/ED2 is in ONCE mode, an emulator or test CPU can be used to drive
the circuit. Table 20-1 shows the status of the port pins during ONCE mode.
Normal operation is restored when normal reset is applied.
Table 20-1. External Pin Status During ONCE Mode
ALE PSEN Port 0 Port 1 Port 2 Port 3 Port I2 XTALA1/2 XTALB1/2
Weak pull-
up
Weak pull-
up Float Weak pull-
up
Weak pull-
up
Weak pull-
up Float Active Active
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21. Power-off Flag
The power-off flag allows the user to distinguish between a “cold start” reset and a “warm start”
reset.
A cold start reset is the one induced by V
CC
switch-on. A warm start reset occurs while V
CC
is still
applied to the device and could be generated for example by an exit from power-down.
The power-off flag (POF) is located in PCON register (Table 21-1). POF is set by hardware
when V
CC
rises from 0 to its nominal voltage. The POF can be set or cleared by software allow-
ing the user to determine the type of reset.
Table 21-1. PCON Register
PCON - Power Control Register (87h)
Reset Value = 00X1 0000b
Not bit addressable
7 6 5 4 3 2 1 0
SMOD1 SMOD0 - POF GF1 GF0 PD IDL
Bit
Number
Bit
Mnemonic Description
7 SMOD1
Serial port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3.
6 SMOD0
Serial port Mode bit 0
Cleared to select SM0 bit in SCON register.
Set to select FE bit in SCON register.
5 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4 POF
Power-Off Flag
Cleared by software to recognize the next reset type.
Set by hardware when V
CC
rises from 0 to its nominal voltage. Can also be set by
software.
3 GF1
General-purpose Flag
Cleared by user for general-purpose usage.
Set by user for general-purpose usage.
2 GF0
General-purpose Flag
Cleared by user for general-purpose usage.
Set by user for general-purpose usage.
1 PD
Power-down mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
0 IDL
Idle mode bit
Cleared by hardware when interrupt or reset occurs.
Set to enter idle mode.
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22. Reduced EMI Mode
The ALE signal is used to demultiplex address and data buses on port 0 when used with exter-
nal program or data memory. Nevertheless, during internal code execution, ALE signal is still
generated. In order to reduce EMI, ALE signal can be disabled by setting AO bit.
The AO bit is located in AUXR register at bit location 0. As soon as AO is set, ALE is no longer
output but remains active during MOVX and MOVC instructions and external fetches. During
ALE disabling, ALE pin is weakly pulled high.
Table 22-1. AUXR Register
AUXR - Auxiliary Register (8Eh)
Reset Value = XX00 10’HSB. XRAM’0b
Not bit addressable
7 6 5 4 3 2 1 0
DPU - M0 XRS2 XRS1 XRS0 EXTRAM AO
Bit
Number
Bit
Mnemonic Description
7 DPU
Disable Weak Pull-up
Cleared by software to activate the permanent weak pull-up (default)
Set by software to disable the weak pull-up (reduce power consumption)
6 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5 M0
Pulse length
Cleared to stretch MOVX control: the RD and the WR pulse length is 6 clock periods
(default).
Set to stretch MOVX control: the RD and the WR pulse length is 30 clock periods.
4 XRS2
XRAM Size
XRS2 XRS1XRS0XRAM size
0 0 0 256 bytes
0 0 1 512 bytes
0 1 0 768 bytes(default)
0 1 1 1024 bytes
1 0 0 1792 bytes
3 XRS1
2 XRS0
1 EXTRAM
EXTRAM bit
Cleared to access internal XRAM using MOVX @ Ri/ @ DPTR.
Set to access external memory.
Programmed by hardware after Power-up regarding Hardware Security Byte (HSB),
default setting, XRAM selected.
0 AO
ALE Output bit
Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2
mode is used) (default). Set, ALE is active only during a MOVX or MOVC instruction is
used.
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23. EEPROM Data Memory
This feature is available only for the AT89C51ED2 device.
The 2K bytes on-chip EEPROM memory block is located at addresses 0000h to 07FFh of the
XRAM/ERAM memory space and is selected by setting control bits in the EECON register.
A read or write access to the EEPROM memory is done with a MOVX instruction.
23.1 Write Data
Data is written by byte to the EEPROM memory block as for an external RAM memory.
The following procedure is used to write to the EEPROM memory:
Check EEBUSY flag
If the user application interrupts routines use XRAM memory space: Save and disable
interrupts.
Load DPTR with the address to write
Store A register with the data to be written
Set bit EEE of EECON register
Execute a MOVX @DPTR, A
Clear bit EEE of EECON register
Restore interrupts.
EEBUSY flag in EECON is then set by hardware to indicate that programming is in progress
and that the EEPROM segment is not available for reading or writing.
The end of programming is indicated by a hardware clear of the EEBUSY flag.
Figure 23-1 represents the optimal write sequence to the on-chip EEPROM data memory.
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Figure 23-1. Recommended EEPROM Data Write Sequence
23.2 Read Data
The following procedure is used to read the data stored in the EEPROM memory:
Check EEBUSY flag
If the user application interrupts routines use XRAM memory space: Save and disable
interrupts.
Load DPTR with the address to read
Set bit EEE of EECON register
Execute a MOVX A, @DPTR
Clear bit EEE of EECON register
Restore interrupts.
EEPROM Data Write
Sequence
Data Write
DPTR= Address
ACC= Data
Exec: MOVX @DPTR, A
Last Byte
to Load?
EEPROM Mapping
EECON = 00h (EEE=0)
Save & Disable IT
EA= 0
Restore IT
EEPROM Data Mapping
EECON = 02h (EEE=1)
EEBusy
Cleared?
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Figure 23-2. Recommended EEPROM Data Read Sequence
23.3 Registers
Table 23-1. EECON Register
EECON (0D2h)
EEPROM Control Register
EEPROM Data Read
Sequence
Data Read
DPTR= Address
ACC= Data
Exec: MOVX A, @DPTR
Last Byte
to Read?
EEPROM Data Mapping
EECON = 02h (EEE=1)
EEPROM Data Mapping
EECON = 00h (EEE = 0
Save & Disable IT
EA= 0
Restore IT
EEBusy
Cleared?
7 6 5 4 3 2 1 0
- - - - - - EEE EEBUSY
Bit Number
Bit
Mnemonic Description
7 - 2 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
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Reset Value = XXXX XX00b
Not bit addressable
1 EEE
Enable EEPROM Space bit
Set to map the EEPROM space during MOVX instructions (Write or Read to the
EEPROM.
Clear to map the XRAM space during MOVX.
0 EEBUSY
Programming Busy flag
Set by hardware when programming is in progress.
Cleared by hardware when programming is done.
Can not be set or cleared by software.
Bit Number
Bit
Mnemonic Description
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24. Flash/EEPROM Memory
The Flash memory increases EEPROM and ROM functionality with in-circuit electrical erasure
and programming. It contains 64K bytes of program memory organized respectively in 512
pages of 128 bytes. This memory is both parallel and serial In-System Programmable (ISP). ISP
allows devices to alter their own program memory in the actual end product under software con-
trol. A default serial loader (bootloader) program allows ISP of the Flash.
The programming does not require external dedicated programming voltage. The necessary
high programming voltage is generated on-chip using the standard V
CC
pins of the
microcontroller.
24.1 Features
Flash EEPROM Internal Program Memory
Boot vector allows user provided Flash loader code to reside anywhere in the Flash memory
space. This configuration provides flexibility to the user.
Default loader in Boot ROM allows programming via the serial port without the need of a user
provided loader.
Up to 64K bytes external program memory if the internal program memory is disabled (EA =
0).
Programming and erasing voltage with standard power supply
Read/Programming/Erase:
Byte-wise read without wait state
Byte or page erase and programming (10 ms)
Typical programming time (64K bytes) is 22s with on chip serial bootloader
Parallel programming with 87C51 compatible hardware interface to programmer
Programmable security for the code in the Flash
100K write cycles
10 years data retention
24.2 Flash Programming and Erasure
The 64-K byte Flash is programmed by bytes or by pages of 128 bytes. It is not necessary to
erase a byte or a page before programming. The programming of a byte or a page includes a
self erase before programming.
There are three methods of programming the Flash memory:
1. The on-chip ISP bootloader may be invoked which will use low level routines to pro-
gram the pages. The interface used for serial downloading of Flash is the UART.
2. The Flash may be programmed or erased in the end-user application by calling low-
level routines through a common entry point in the Boot ROM.
3. The Flash may be programmed using the parallel method by using a conventional
EPROM programmer. The parallel programming method used by these devices is simi-
lar to that used by EPROM 87C51 but it is not identical and the commercially available
programmers need to have support for the AT89C51RD2/ED2. The bootloader and the
Application Programming Interface (API) routines are located in the BOOT ROM.
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24.3 Flash Registers and Memory Map
The AT89C51RD2/ED2 Flash memory uses several registers for its management:
Hardware register can only be accessed through the parallel programming modes which are
handled by the parallel programmer.
Software registers are in a special page of the Flash memory which can be accessed through
the API or with the parallel programming modes. This page, called "Extra Flash Memory", is
not in the internal Flash program memory addressing space.
24.3.1 Hardware Register
The only hardware register of the AT89C51RD2/ED2 is called Hardware Byte or Hardware
Security Byte (HSB).
Table 24-1. Hardware Security Byte (HSB)
Boot Loader Jump Bit (BLJB)
One bit of the HSB, the BLJB bit, is used to force the boot address:
When this bit is programmed (‘0’ value) the boot address is F800h.
When this bit is unprogrammed (‘1’ value) the boot address is 0000h.
By default, this bit is programmed and the ISP is enabled.
24.3.2 Flash Memory Lock Bits
The three lock bits provide different levels of protection for the on-chip code and data when pro-
grammed as shown in Table 24-2.
7 6 5 4 3 2 1 0
X2 BLJB - - XRAM LB2 LB1 LB0
Bit
Number
Bit
Mnemonic Description
7 X2
X2 Mode
Programmed (‘0’ value) to force X2 mode (6 clocks per instruction) after reset.
Unprogrammed (‘1’ Value) to force X1 mode, Standard Mode, after reset (Default).
6 BLJB
Boot Loader Jump Bit
Unprogrammed (‘1’ value) to start the user’s application on next reset at address 0000h.
Programmed (‘0’ value) to start the boot loader at address F800h on next reset (Default).
5 - Reserved
4 -
Reserved
3 XRAM
XRAM config bit (only programmable by programmer tools)
Programmed to inhibit XRAM.
Unprogrammed, this bit to valid XRAM (Default).
2-0 LB2-0
User Memory Lock Bits (only programmable by programmer tools)
See Table 24-2
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Table 24-2. Program Lock Bits
Note: U: Unprogrammed or "one" level.
P: Programmed or "zero" level.
X: Do not care
WARNING: Security level 2 and 3 should only be programmed after Flash and code verification.
These security bits protect the code access through the parallel programming interface. They
are set by default to level 4. The code access through the ISP is still possible and is controlled
by the "software security bits" which are stored in the extra Flash memory accessed by the ISP
firmware.
To load a new application with the parallel programmer, a chip erase must first be done. This will
set the HSB in its inactive state and will erase the Flash memory. The part reference can always
be read using Flash parallel programming modes.
24.3.3 Default Values
The default value of the HSB provides parts ready to be programmed with ISP:
BLJB: Programmed force ISP operation.
X2: Unprogrammed to force X1 mode (Standard Mode).
XRAM: Unprogrammed to valid XRAM
LB2-0: Security level four to protect the code from a parallel access with maximum security.
24.3.4 Software Registers
Several registers are used in factory and by parallel programmers. These values are used by
Atmel ISP.
These registers are in the "Extra Flash Memory" part of the Flash memory. This block is also
called "XAF" or eXtra Array Flash. They are accessed in the following ways:
Commands issued by the parallel memory programmer.
Commands issued by the ISP software.
Calls of API issued by the application software.
Several software registers are described in Table 24-3.
Table 24-3. Default Values
Program Lock Bits
Protection Description
Security
Level LB0 LB1 LB2
1 U U U No program lock features enabled.
2 P U U
MOVC instruction executed from external program memory is disabled from
fetching code bytes from internal memory, EA is sampled and latched on reset,
and further parallel programming of the on chip code memory is disabled.
ISP and software programming with API are still allowed.
3 X P U Same as 2, also verify code memory through parallel programming interface is
disabled.
4 X X P Same as 3, also external execution is disabled (Default).
Mnemonic Definition Default value Description
SBV Software Boot Vector FCh
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After programming the part by ISP, the BSB must be cleared (00h) in order to allow the applica-
tion to boot at 0000h.
The content of the Software Security Byte (SSB) is described in Table 24-4 and Table 24-5.
To assure code protection from a parallel access, the HSB must also be at the required level.
Table 24-4. Software Security Byte
The two lock bits provide different levels of protection for the on-chip code and data, when pro-
grammed as shown in Table 24-5.
BSB Boot Status Byte 0FFh
SSB Software Security Byte FFh
Copy of the Manufacturer Code 58h Atmel
Copy of the Device ID #1: Family Code D7h C51 X2, Electrically Erasable
Copy of the Device ID #2: Memories Size and
Type ECh AT89C51RD2/ED2 64KB
Copy of the Device ID #3: Name and Revision EFh AT89C51RD2/ED2 64KB,
Revision 0
7 6 5 4 3 2 1 0
- - - - - - LB1 LB0
Bit
Number
Bit
Mnemonic Description
7 -
Reserved
Do not clear this bit.
6 -
Reserved
Do not clear this bit.
5 -
Reserved
Do not clear this bit.
4 -
Reserved
Do not clear this bit.
3 -
Reserved
Do not clear this bit.
2 -
Reserved
Do not clear this bit.
1-0 LB1-0 User Memory Lock Bits
See Table 24-5
Mnemonic Definition Default value Description
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Table 24-5. User Memory Lock Bits of the SSB
Note: X: Do not care
WARNING: Security level 2 and 3 should only be programmed after Flash verification.
24.4 Flash Memory Status
AT89C51RD2/ED2 parts are delivered in standard with the ISP ROM bootloader.
After ISP or parallel programming, the possible contents of the Flash memory are summarized in
Figure 24-1:
Figure 24-1. Flash Memory Possible Contents
24.5 Memory Organization
When the EA pin is high, the processor fetches instructions from internal program Flash. If the
EA pin is tied low, all program memory fetches are from external memory.
24.6 Bootloader Architecture
24.6.1 Introduction
The bootloader manages communication according to a specifically defined protocol to provide
the whole access and service on Flash memory. Furthermore, all accesses and routines can be
called from the user application.
Program Lock Bits
Protection Description
Security
Level LB0 LB1
1 1 1 No program lock features enabled.
2 0 1 ISP programming of the Flash is disabled.
3 X 0 Same as 2, also verify through ISP programming interface is disabled.
0000h
Virgin
Default After ISP After Parallel
Programming
After Parallel
Programming
After Parallel
Programming
ApplicationApplication Virgin
After ISP
or
Dedicated
ISP Dedicated
ISP
Application
Virgin
or
Application
Virgin
or
Application
FFFFh
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Figure 24-2. Diagram Context Description
24.6.2 Acronyms
ISP: In-System Programming
SBV: Software Boot Vector
BSB: Boot Status Byte
SSB: Software Security Byte
HW: Hardware Byte
Bootloader Flash Memory
Access Via
Specific
Protocol
Access From
User
Application
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24.6.3 Functional Description
Figure 24-3. Bootloader Functional Description
On the above diagram, the on-chip bootloader processes are:
ISP Communication Management
The purpose of this process is to manage the communication and its protocol between the on-
chip bootloader and a external device. The on-chip ROM implements a serial protocol (see sec-
tion Bootloader Protocol”). This process translate serial communication frame (UART) into
Flash memory access (read, write, erase, etc.).
User Call Management
Several Application Program Interface (API) calls are available for use by an application pro-
gram to permit selective erasing and programming of Flash pages. All calls are made through a
common interface (API calls), included in the ROM bootloader. The programming functions are
selected by setting up the microcontroller’s registers before making a call to a common entry
point (0xFFF0). Results are returned in the registers. The purpose on this process is to translate
the registers values into internal Flash Memory Management.
Flash Memory Management
This process manages low level access to Flash memory (performs read and write access).
ISP Communication
Management
User
Application
Specific Protocol
Communication
Management
Flash
Memory
External Host with
Flash Memory
User Call
Management (API)
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24.6.4 Bootloader Functionality
The bootloader can be activated by two means: Hardware conditions or regular boot process.
The Hardware conditions (EA = 1, PSEN = 0) during the Reset# falling edge force the on-chip
bootloader execution. This allows an application to be built that will normally execute the end
user’s code but can be manually forced into default ISP operation.
As PSEN is a an output port in normal operating mode after reset, user application should take
care to release PSEN after falling edge of reset signal. The hardware conditions are sampled at
reset signal falling edge, thus they can be released at any time when reset input is low.
To ensure correct microcontroller startup, the PSEN pin should not be tied to ground during
power-on (See Figure 24-4).
Figure 24-4. Hardware conditions typical sequence during power-on.
The on-chip bootloader boot process is shown Figure 24-5.
VCC
PSEN
RST
Table 24-6. Bootloader Process Description
Purpose
Hardware Conditions The Hardware Conditions force the bootloader execution whatever BLJB,
BSB and SBV values.
BLJB
The Boot Loader Jump Bit forces the application execution.
BLJB = 0 => Bootloader execution
BLJB = 1 => Application execution
The BLJB is a fuse bit in the Hardware Byte.
It can be modified by hardware (programmer) or by software (API).
Note: The BLJB test is performed by hardware to prevent any program
execution.
SBV
The Software Boot Vector contains the high address of customer bootloader
stored in the application.
SBV = FCh (default value) if no customer bootloader in user Flash.
Note: The customer bootloader is called by JMP [SBV]00h instruction.
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24.6.5 Boot Process
Figure 24-5. Bootloader Process
RESET
Hardware
Condition?
BLJB!= 0
?
User Application
Hardware
Software
Atmel BOOT LOADERUSER BOOT LOADER
BLJB = 1
BSB = 00h
?
SBV = FCh
?
PC = 0000h
PC= [SBV]00h
BLJB = 0
If BLJB = 0 then ENBOOT Bit (AUXR1) is Set
else ENBOOT Bit (AUXR1) is Cleared
ENBOOT = 1
ENBOOT = 0
Yes (PSEN = 0, EA = 1, and ALE =1 or Not Connected)
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24.7 ISP Protocol Description
24.7.1 Physical Layer
The UART used to transmit information has the following configuration:
Character: 8-bit data
Parity: none
Stop: 2 bits
Flow control: none
Baudrate: autobaud is performed by the bootloader to compute the baudrate chosen by the
host.
24.7.2 Frame Description
The Serial Protocol is based on the Intel Hex-type records.
Intel Hex records consist of ASCII characters used to represent hexadecimal values and are
summarized below.
Figure 24-6. Intel Hex Type Frame
Record Mark:
Record Mark is the start of frame. This field must contain ’:’.
Reclen:
Reclen specifies the number of bytes of information or data which follows the Record Type field
of the record.
Load Offset:
Load Offset specifies the 16-bit starting load offset of the data bytes, therefore this field is used
only for Data Program Record (see Section “ISP Commands Summary”).
Record Type:
Record Type specifies the command type. This field is used to interpret the remaining informa-
tion within the frame. The encoding for all the current record types is described in Section ISP
Commands Summary”.
Data/Info:
Data/Info is a variable length field. It consists of zero or more bytes encoded as pairs of hexa-
decimal digits. The meaning of data depends on the Record Type.
Checksum:
The two’s complement of the 8-bit bytes that result from converting each pair of ASCII hexadec-
imal digits to one byte of binary, and including the Reclen field to and including the last byte of
the Data/Info field. Therefore, the sum of all the ASCII pairs in a record after converting to
binary, from the Reclen field to and including the Checksum field, is zero.
Record Record
Load Data
Mark
’:’
Reclen Offset Type or
Info
Checksum
1-byte 1-byte 2-bytes 1-byte n-bytes 1-byte
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24.8 Functional Description
24.8.1 Software Security Bits (SSB)
The SSB protects any Flash access from ISP command.
The command "Program Software Security Bit" can only write a higher priority level.
There are three levels of security:
level 0: NO_SECURITY (FFh)
This is the default level.
From level 0, one can write level 1 or level 2.
level 1: WRITE_SECURITY (FEh)
For this level it is impossible to write in the Flash memory, BSB and SBV.
The Bootloader returns ’P’ on write access.
From level 1, one can write only level 2.
level 2: RD_WR_SECURITY (FCh
The level 2 forbids all read and write accesses to/from the Flash/EEPROM memory.
The Bootloader returns ’L’ on read or write access.
Only a full chip erase in parallel mode (using a programmer) or ISP command can reset the soft-
ware security bits.
From level 2, one cannot read and write anything.
Table 24-7. Software Security Byte Behavior
24.8.2 Full Chip Erase
The ISP command "Full Chip Erase" erases all user Flash memory (fills with FFh) and sets
some bytes used by the bootloader at their default values:
BSB = FFh
Level 0 Level 1 Level 2
Flash/EEPROM Any access allowed Read-only access allowed Any access not allowed
Fuse Bit Any access allowed Read-only access allowed Any access not allowed
BSB & SBV Any access allowed Read-only access allowed Any access not allowed
SSB Any access allowed Write level 2 allowed Read-only access allowed
Manufacturer Info Read-only access allowed Read-only access allowed Read-only access allowed
Bootloader Info Read-only access allowed Read-only access allowed Read-only access allowed
Erase Block Allowed Not allowed Not allowed
Full Chip Erase Allowed Allowed Allowed
Blank Check Allowed Allowed Allowed
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SBV = FCh
SSB = FFh
The Full Chip Erase does not affect the bootloader.
24.8.3 Checksum Error
When a checksum error is detected, send ‘X’ followed with CR&LF.
24.9 Flow Description
24.9.1 Overview
An initialization step must be performed after each Reset. After microcontroller reset, the boot-
loader waits for an autobaud sequence (see section ‘Autobaud Performances’).
When the communication is initialized, the protocol depends on the record type requested by the
host.
FLIP, a software utility to implement ISP programming with a PC, is available from the Atmel
web site.
24.9.2 Communication Initialization
The host initializes the communication by sending a ’U’ character to help the bootloader to com-
pute the baudrate (autobaud).
Figure 24-7. Initialization
24.9.3 Autobaud Performances
The ISP feature allows a wide range of baud rates in the user application. It is also adaptable to
a wide range of oscillator frequencies. This is accomplished by measuring the bit-time of a single
bit in a received character. This information is then used to program the baud rate in terms of
timer counts based on the oscillator frequency. The ISP feature requires that an initial character
(an uppercase U) be sent to the AT89C51RD2/ED2 to establish the baud rate. Table show the
autobaud capability.
Host Bootloader
"U" Performs Autobaud
Init Communication
If (Not Received "U")
"U"
Communication Opened
Else Sends Back “U” Character
Table 24-8. Autobaud Performances
Frequency
(MHz)
Baudrate (kHz) 1.8432 2 2.4576 3 3.6864 4 5 6 7.3728
2400 OK OK OK OK OK OK OK OK OK
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24.9.4 Command Data Stream Protocol
All commands are sent using the same flow. Each frame sent by the host is echoed by the
bootloader.
Figure 24-8. Command Flow
4800 OK - OK OK OK OK OK OK OK
9600 OK - OK OK OK OK OK OK OK
19200 OK - OK OK OK - - OK OK
38400 - - OK OK - OK OK OK
57600 - - - - OK - - - OK
115200 - - - - - - - - OK
Frequency
(MHz)
Baudrate (kHz) 8 10 11.0592 12 14.746 16 20 24 26.6
2400 OK OK OK OK OK OK OK OK OK
4800 OK OK OK OK OK OK OK OK OK
9600 OK OK OK OK OK OK OK OK OK
19200 OK OK OK OK OK OK OK OK OK
38400 - - OK OK OK OK OK OK OK
57600 - - OK - OK OK OK OK OK
115200 - - OK - OK - - - -
Table 24-8. Autobaud Performances (Continued)
Frequency
(MHz)
Baudrate (kHz) 1.8432 2 2.4576 3 3.6864 4 5 6 7.3728
Bootloader
":"
Sends First Character of the
Frame
If (not received ":")
Sends Frame (made of 2 ASCII Gets Frame, and Sends Back Echo
for Each Received Byte
Host
Else
":"
Sends Echo and Start
Reception
Characters Per Byte)
Echo Analysis
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24.9.5 Write/Program Commands Description
This flow is common to the following frames:
Flash/EEPROM Programming Data Frame
EOF or Atmel Frame (only Programming Atmel Frame)
Config Byte Programming Data Frame
Baud Rate Frame
Figure 24-9. Write/Program Flow
Host Bootloader
Write Command
’X’ & CR & LF
NO_SECURITY
Wait Write Command
Checksum Error
Wait Programming
Send Security Error
Send COMMAND_OK
Send Write Command
Wait Checksum Error
Wait COMMAND_OK
Wait Security Error
OR
COMMAND ABORTED
COMMAND FINISHED
Send Checksum Error
COMMAND ABORTED
’P’ & CR & LF
OR
’.’ & CR & LF
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24.9.5.1 Example
24.9.6 Blank Check Command Description
Figure 24-10. Blank Check Flow
HOST : 01 0010 00 55 9A
BOOTLOADER : 01 0010 00 55 9A . CR LF
Programming Data (write 55h at address 0010h in the Flash)
HOST : 02 0000 03 05 01 F5
BOOTLOADER : 02 0000 03 05 01 F5. CR LF
Programming Atmel function (write SSB to level 2)
HOST : 03 0000 03 06 00 55 9F
BOOTLOADER : 03 0000 03 06 00 55 9F . CR LF
Writing Frame (write BSB to 55h)
Host Bootloader
Blank Check Command
’X’ & CR & LF
Flash Blank
Wait Blank Check Command
Send First Address
Send COMMAND_OK
Send Blank Check Command
Wait Checksum Error
Wait Address not
Erased
Wait COMMAND_OK
OR
COMMAND ABORTED
COMMAND FINISHED
Send Checksum Error
COMMAND FINISHED
’.’ & CR & LF
OR
address & CR & LF
not Erased
Checksum Error
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24.9.6.1 Example
HOST : 05 0000 04 0000 7FFF 01 78
BOOTLOADER : 05 0000 04 0000 7FFF 01 78 . CR LF
Blank Check ok
BOOTLOADER : 05 0000 04 0000 7FFF 01 70 X CR LF CR LF
Blank Check with checksum error
HOST : 05 0000 04 0000 7FFF 01 70
BOOTLOADER : 05 0000 04 0000 7FFF 01 78 xxxx CR LF
Blank Check ok at address xxxx
HOST : 05 0000 04 0000 7FFF 01 78
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24.9.7 Display Data Description
Figure 24-11. Display Flow
24.9.7.1 Example
24.9.8 Read Function Description
This flow is similar for the following frames:
Host Bootloader
Display Command
’X’ & CR & LF
RD_WR_SECURITY
Wait Display Command
Read Data
Send Security Error
Send Display Data
Send Display Command
Wait Checksum Error
Wait Display Data
Wait Security Error
OR
COMMAND ABORTED
COMMAND FINISHED
Send Checksum Error
COMMAND ABORTED
’L’ & CR & LF
OR
"Address = "
All Data Read
Complet Frame
"Reading Value"
CR & LF
All Data ReadAll Data Read
COMMAND FINISHED
Checksum error
HOST : 05 0000 04 0000 0020 00 D7
BOOTLOADER : 05 0000 04 0000 0020 00 D7
BOOTLOADER 0000=-----data------ CR LF (16 data)
BOOTLOADER 0010=-----data------ CR LF (16 data)
BOOTLOADER 0020=data CR LF ( 1 data)
Display data from address 0000h to 0020h
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Reading Frame
EOF Frame/ Atmel Frame (only reading Atmel Frame)
Figure 24-12. Read Flow
24.9.8.1 Example
24.9.9 ISP Commands Summary
Host Bootloader
Read Command
’X’ & CR & LF
RD_WR_SECURITY
Wait Read Command
Read Value
Send Security error
Send Data Read
Send Read Command
Wait Checksum Error
Wait Value of Data
Wait Security Error
OR
COMMAND ABORTED
COMMAND FINISHED
Send Checksum error
COMMAND ABORTED
’L’ & CR & LF
OR
’value’ & ’.’ & CR & LF
Checksum error
HOST : 02 0000 05 07 02 F0
BOOTLOADER : 02 0000 05 07 02 F0 Value . CR LF
HOST : 02 0000 01 02 00 FB
BOOTLOADER : 02 0000 01 02 00 FB Value . CR LF
Read function (read SBV)
Atmel Read function (read Bootloader version)
Table 24-9. ISP Commands Summary
Command Command Name Data[0] Data[1] Command Effect
00h Program Code
Program Nb Code Byte.
Bootloader will accept up to 128 (80h) data bytes. The data
bytes should be 128 byte page flash boundary.
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03h Write Function
01h
00h Erase block0 (0000h-1FFFh)
20h Erase block1 (2000h-3FFFh)
40h Erase block2 (4000h-7FFFh)
80h Erase block3 (8000h- BFFFh)
C0h Erase block4 (C000h- FFFFh)
03h 00h Hardware Reset
04h 00h Erase SBV & BSB
05h
00h Program SSB level 1
01h Program SSB level 2
06h
00h Program BSB (value to write in data[2])
01h Program SBV (value to write in data[2])
07h - Full Chip Erase (This command needs about 6 sec to be
executed)
0Ah 04h Program BLJB fuse (value to write in data[2])
08h Program X2 fuse (value to write in data[2])
04h Display Function
Data[0:1] = start address
Data [2:3] = end address
Data[4] = 00h:Display Code
Data[4] = 01h: Blank check
Data[4] = 02h: Display EEPROM
Display Code
Blank Check
Display EEPROM data
05h Read Function
00h
00h Manufacturer Id
01h Device Id #1
02h Device Id #2
03h Device Id #3
07h
00h Read SSB
01h Read BSB
02h Read SBV
06h Read Extra Byte
0Bh 00h Read Hardware Byte
0Eh
00h Read Device Boot ID1
01h Read Device Boot ID2
0Fh 00h Read Bootloader Version
07h Program EEPROM data Program Nn EEprom Data Byte.
Bootloader will accept up to 128 (80h) data bytes.
Table 24-9. ISP Commands Summary (Continued)
Command Command Name Data[0] Data[1] Command Effect
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24.10 API Call Description
The IAP allows to reprogram a microcontroller on-chip Flash memory without removing it from
the system and while the embedded application is running.
The user application can call some Application Programming Interface (API) routines allowing
IAP. These API are executed by the bootloader.
To call the corresponding API, the user must use a set of Flash_api routines which can be linked
with the application.
Example of Flash_api routines are available on the Atmel web site on the software application
note:
C Flash Drivers for the AT89C51RD2/ED2
The API calls description and arguments are shown in Table 24-10.
24.10.1 Process
The application selects an API by setting R1, ACC, DPTR0 and DPTR1 registers.
All calls are made through a common interface “USER_CALL” at the address FFF0h.
The jump at the USER_CALL must be done by LCALL instruction to be able to comeback in the
application.
Before jump at the USER_CALL, the bit ENBOOT in AUXR1 register must be set.
24.10.2 Constraints
The interrupts are not disabled by the bootloader.
Interrupts must be disabled by user prior to jump to the USER_CALL, then re-enabled when
returning.
Interrupts must also be disabled before accessing EEPROM Data then re-enabled after.
The user must take care of hardware watchdog before launching a Flash operation.
Table 24-10. API Call Summary
Command R1 A DPTR0 DPTR1 Returned Value Command Effect
READ MANUF ID 00h XXh 0000h XXh ACC = Manufacturer Id Read Manufacturer identifier
READ DEVICE ID1 00h XXh 0001h XXh ACC = Device Id 1 Read Device identifier 1
READ DEVICE ID2 00h XXh 0002h XXh ACC = Device Id 2 Read Device identifier 2
READ DEVICE ID3 00h XXh 0003h XXh ACC = Device Id 3 Read Device identifier 3
ERASE BLOCK 01h XXh
DPH = 00h
00h ACC = DPH
Erase block 0
DPH = 20h Erase block 1
DPH = 40h Erase block 2
DPH = 80h Erase block 3
DPH = C0h Erase block 4
PROGRAM DATA BYTE 02h Vaue to write
Address of
byte to
program
XXh ACC = 0: DONE Program up one data byte in the on-chip
flash memory.
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PROGRAM SSB 05h XXh
DPH = 00h
DPL = 00h
00h ACC = SSB value
Set SSB level 1
DPH = 00h
DPL = 01h Set SSB level 2
DPH = 00h
DPL = 10h Set SSB level 0
DPH = 00h
DPL = 11h Set SSB level 1
PROGRAM BSB 06h New BSB
value 0000h XXh none Program boot status byte
PROGRAM SBV 06h New SBV
value 0001h XXh none Program software boot vector
READ SSB 07h XXh 0000h XXh ACC = SSB Read Software Security Byte
READ BSB 07h XXh 0001h XXh ACC = BSB Read Boot Status Byte
READ SBV 07h XXh 0002h XXh ACC = SBV Read Software Boot Vector
PROGRAM DATA PAGE 09h
Number of
byte to
program
Address of
the first byte
to program in
the Flash
memory
Address in
XRAM of the
first data to
program
ACC = 0: DONE
Program up to 128 bytes in user Flash.
Remark: number of bytes to program is
limited such as the Flash write remains in a
single 128 bytes page. Hence, when ACC is
128, valid values of DPL are 00h, or, 80h.
PROGRAM X2 FUSE 0Ah Fuse value
00h or 01h 0008h XXh none Program X2 fuse bit with ACC
PROGRAM BLJB FUSE 0Ah Fuse value
00h or 01h 0004h XXh none Program BLJB fuse bit with ACC
READ HSB 0Bh XXh XXXXh XXh ACC = HSB Read Hardware Byte
READ BOOT ID1 0Eh XXh DPL = 00h XXh ACC = ID1 Read boot ID1
READ BOOT ID2 0Eh XXh DPL = 01h XXh ACC = ID2 Read boot ID2
READ BOOT VERSION 0Fh XXh XXXXh XXh ACC = Boot_Version Read bootloader version
Table 24-10. API Call Summary (Continued)
Command R1 A DPTR0 DPTR1 Returned Value Command Effect
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25.
E
lectrical Characteristics
25.1 Absolute Maximum Ratings
25.2 DC Parameters for Standard Voltage
I = industrial ........................................................-40°C to 85°C
Storage Temperature .................................... -65°C to + 150°C
Voltage on V
CC
to V
SS
......................................-0.5V to + 6.5V
VVoltage on Any Pin to V
SS
.......................-0.5V to V
CC
+ 0.5V
Power Dissipation........................................................... 1 W
(2)
Note: Stresses at or above those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other condi-
tions above those indicated in the operational
sections of this specification is not implied. Exposure
to absolute maximum rating conditions may affect
device reliability.
Power dissipation is based on the maximum allow-
able die temperature and the thermal resistance of
the package.
T
A
= -40°C to +85°C; V
SS
= 0V;
V
CC
=2.7V to 5.5V and F = 0 to 40 MHz (both internal and external code execution)
V
CC
=4.5V to 5.5V and F = 0 to 60 MHz (internal code execution only)
Symbol Parameter Min Typ Max Unit Test Conditions
V
IL
Input Low Voltage -0.5 0.2 V
CC
- 0.1 V
V
IH
Input High Voltage except RST, XTAL1 0.2 V
CC
+ 0.9 V
CC
+ 0.5 V
V
IH1
Input High Voltage RST, XTAL1 0.7 V
CC
V
CC
+ 0.5 V
V
OL
Output Low Voltage, ports 1, 2, 3, 4
(6)
0.3
0.45
1.0
V
V
V
V
CC
= 4.5V to 5.5V
I
OL
= 100
µ
A
(4)
I
OL
= 1.6 mA
(4)
I
OL
= 3.5 mA
(4)
0.45 V
V
CC
= 2.7V to 5.5V
I
OL
= 0.8 mA
(4)
V
OL1
Output Low Voltage, port 0, ALE, PSEN
(6)
0.3
0.45
1.0
V
V
V
V
CC
= 4.5V to 5.5V
I
OL
= 200
µ
A
(4)
I
OL
= 3.2 mA
(4)
I
OL
= 7.0 mA
(4)
0.45 V
V
CC
= 2.7V to 5.5V
I
OL
= 1.6 mA
(4)
V
OH
Output High Voltage, ports 1, 2, 3, 4
V
CC
- 0.3
V
CC
- 0.7
V
CC
- 1.5
V
V
V
V
CC
= 5V
±
10%
I
OH
= -10
µ
A
I
OH
= -30
µ
A
I
OH
= -60
µ
A
0.9 V
CC
V
V
CC
= 2.7V to 5.5V
I
OH
= -10
µ
A
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Notes: 1. Operating I
CC
is measured with all output pins disconnected; XTAL1 driven with T
CLCH
, T
CHCL
= 5 ns (see Figure 25-4), V
IL
=
V
SS
+ 0.5V, V
IH
= V
CC
- 0.5V; XTAL2 N.C.; EA = RST = Port 0 = V
CC
. I
CC
would be slightly higher if a crystal oscillator used
(see Figure 25-1).
2. Idle I
CC
is measured with all output pins disconnected; XTAL1 driven with T
CLCH
, T
CHCL
= 5 ns, V
IL
= V
SS
+ 0.5V, V
IH
= V
CC
-
0.5V; XTAL2 N.C; Port 0 = V
CC
; EA = RST = V
SS
(see Figure 25-2).
3. Power-down I
CC
is measured with all output pins disconnected; EA = V
SS
, PORT 0 = V
CC
; XTAL2 NC.; RST = V
SS
(see Fig-
ure 25-3).
4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the V
OLS
of ALE and Ports 1
and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0
transitions during bus operation. In the worst cases (capacitive loading 100 pF), the noise pulse on the ALE line may exceed
0.45V with maxi V
OL
peak 0.6V. A Schmitt Trigger use is not necessary.
5. Typical values are based on a limited number of samples and are not guaranteed. The values listed are at room temperature
and 5V.
6. Under steady state (non-transient) conditions, I
OL
must be externally limited as follows:
Maximum I
OL
per port pin: 10 mA
Maximum I
OL
per 8-bit port:
V
OH1
Output High Voltage, port 0, ALE, PSEN
V
CC
- 0.3
V
CC
- 0.7
V
CC
- 1.5
V
V
V
V
CC
= 5V
±
10%
I
OH
= -200
µ
A
I
OH
= -3.2 mA
I
OH
= -7.0 mA
0.9 V
CC
V
V
CC
= 2.7V to 5.5V
I
OH
= -10
µ
A
R
RST
RST Pull-down Resistor 50 200
(5)
250 k
I
IL
Logical 0 Input Current ports 1, 2, 3, 4 and 5 -50
µ
A V
IN
= 0.45V
I
LI
Input Leakage Current
±
10
µ
A 0.45V < V
IN
< V
CC
I
TL
Logical 1 to 0 Transition Current, ports 1, 2, 3, 4 -650
µ
A V
IN
= 2.0V
C
IO
Capacitance of I/O Buffer 10 pF F
C
= 3 MHz
T
A
= 25
°
C
I
PD
Power-down Current 75 150
µ
A 2.7 < V
CC <
5.5V
(3)
I
CCOP
Power Supply Current on normal mode 0.4 x Frequency (MHz) + 5 mA V
CC
= 5.5V
(1)
I
CCIDLE
Power Supply Current on idle mode 0.3 x Frequency (MHz) + 5 mA V
CC
= 5.5V
(2)
I
CCWRITE
Power Supply Current on flash or EEdata write 0.8 x Frequency (MHz) + 15 mA V
CC
= 5.5V
t
WRITE
Flash or EEdata programming time 7 17 ms 2.7 < V
CC <
5.5V
VPFDP Internal POR/PFD VPFDP threshold 2.25 2.5 2.69 V
VPFDM Internal POR/PFD VPFDM threshold 2.15 2.35 2.62 V
Vhyst Internal POR/PFD Hysteresys 70 140 250 mV
Vcc
dV/dt Maximum Vcc Power supply slew rate
(7)
0.1 V/µs
T
A
= -40°C to +85°C; V
SS
= 0V;
V
CC
=2.7V to 5.5V and F = 0 to 40 MHz (both internal and external code execution)
V
CC
=4.5V to 5.5V and F = 0 to 60 MHz (internal code execution only) (Continued)
Symbol Parameter Min Typ Max Unit Test Conditions
116
4235K–8051–05/08
AT89C51RD2/ED2
Port 0: 26 mA
Ports 1, 2 and 3: 15 mA
Maximum total I
OL
for all output pins: 71 mA
If I
OL
exceeds the test condition, V
OL
may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
7. The maximum dV/dt value specifies the maximum Vcc drop to issure no internal POR/PFD reset.
Figure 25-1. I
CC
Test Condition, Active Mode
Figure 25-2. I
CC
Test Condition, Idle Mode
Figure 25-3. I
CC
Test Condition, Power-down Mode
EA
V
CC
V
CC
I
CC
(NC)
CLOCK
SIGNAL
V
CC
All other pins are disconnected.
RST
XTAL2
XTAL1
V
SS
V
CC
P0
RST EA
XTAL2
XTAL1
V
SS
V
CC
V
CC
I
CC
(NC)
P0
V
CC
All other pins are disconnected.
CLOCK
SIGNAL
RST EA
XTAL2
XTAL1
V
SS
V
CC
V
CC
I
CC
(NC)
P0
V
CC
All other pins are disconnected.
117
4235K–8051–05/08
AT89C51RD2/ED2
Figure 25-4. Clock Signal Waveform for I
CC
Tests in Active and Idle Modes
25.3 AC Parameters
25.3.1 Explanation of the AC Symbols
Each timing symbol has 5 characters. The first character is always a T” (stands for time). The
other characters, depending on their positions, stand for the name of a signal or the logical sta-
tus of that signal. The following is a list of all the characters and what they stand for.
Example:T
AVLL
= Time for Address Valid to ALE Low.
T
LLPL
= Time for ALE Low to PSEN Low.
(Load Capacitance for port 0, ALE and PSEN = 100 pF; Load Capacitance for all other outputs =
80 pF.)
Table 25-1 Table 25-4, and Table 25-7 give the description of each AC symbols.
Table 25-2, Table 25-3, Table 25-5 and Table 25-8 gives the range for each AC parameter.
Table 25-2, Table 25-3 and Table 25-9 give the frequency derating formula of the AC parameter
for each speed range description. To calculate each AC symbols. take the x value in the corre-
ponding column (-M) and use this value in the formula.
Example: T
LLIU
for -M and 20 MHz, Standard clock.
x = 35 ns
T 50 ns
T
CCIV
= 4T - x = 165 ns
V
CC
-0.5V
0.45V
0.7V
CC
0.2V
CC
-0.1
T
CLCH
T
CHCL
T
CLCH
= T
CHCL
= 5ns.
118
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25.3.2 External Program Memory Characteristics
Table 25-1. Symbol Description
Table 25-2. AC Parameters for a Fix Clock
Symbol Parameter
T Oscillator clock period
T
LHLL
ALE pulse width
T
AVLL
Address Valid to ALE
T
LLAX
Address Hold After ALE
T
LLIV
ALE to Valid Instruction In
T
LLPL
ALE to PSEN
T
PLPH
PSEN Pulse Width
T
PLIV
PSEN to Valid Instruction In
T
PXIX
Input Instruction Hold After PSEN
T
PXIZ
Input Instruction Float After PSEN
T
AVIV
Address to Valid Instruction In
T
PLAZ
PSEN Low to Address Float
Symbol -M Units
Min Max
T 25 ns
T
LHLL
35 ns
T
AVLL
5 ns
T
LLAX
5 ns
T
LLIV
n 65 ns
T
LLPL
5 ns
T
PLPH
50 ns
T
PLIV
30 ns
T
PXIX
0 ns
T
PXIZ
10 ns
T
AVIV
80 ns
T
PLAZ
10 ns
119
4235K–8051–05/08
AT89C51RD2/ED2
Table 25-3. AC Parameters for a Variable Clock
25.3.3 External Program Memory Read Cycle
25.3.4 External Data Memory Characteristics
Symbol Type Standard Clock X2 Clock
X parameter for
-M range Units
T
LHLL
Min 2 T - x T - x 15 ns
T
AVLL
Min T - x 0.5 T - x 20 ns
T
LLAX
Min T - x 0.5 T - x 20 ns
T
LLIV
Max 4 T - x 2 T - x 35 ns
T
LLPL
Min T - x 0.5 T - x 15 ns
T
PLPH
Min 3 T - x 1.5 T - x 25 ns
T
PLIV
Max 3 T - x 1.5 T - x 45 ns
T
PXIX
Min x x 0 ns
T
PXIZ
Max T - x 0.5 T - x 15 ns
T
AVIV
Max 5 T - x 2.5 T - x 45 ns
T
PLAZ
Max x x 10 ns
T
PLIV
TPLAZ
ALE
PSEN
PORT 0
PORT 2
A0-A7A0-A7 INSTR ININSTR IN INSTR IN
ADDRESS
OR SFR-P2 ADDRESS A8-A15ADDRESS A8-A15
12 T
CLCL
T
AVIV
T
LHLL
T
AVLL
T
LLIV
T
LLPL
T
PLPH
T
PXAV
T
PXIX
T
PXIZ
T
LLAX
120
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AT89C51RD2/ED2
Table 25-4. Symbol Description
Table 25-5. AC Parameters for a Fix Clock
Symbol Parameter
T
RLRH
RD Pulse Width
T
WLWH
WR Pulse Width
T
RLDV
RD to Valid Data In
T
RHDX
Data Hold After RD
T
RHDZ
Data Float After RD
T
LLDV
ALE to Valid Data In
T
AVDV
Address to Valid Data In
T
LLWL
ALE to WR or RD
T
AVWL
Address to WR or RD
T
QVWX
Data Valid to WR Transition
T
QVWH
Data Set-up to WR High
T
WHQX
Data Hold After WR
T
RLAZ
RD Low to Address Float
T
WHLH
RD or WR High to ALE high
Symbol
-M
UnitsMin Max
T
RLRH
125 ns
T
WLWH
125 ns
T
RLDV
95 ns
T
RHDX
0 ns
T
RHDZ
25 ns
T
LLDV
155 ns
T
AVDV
160 ns
T
LLWL
45 105 ns
T
AVWL
70 ns
T
QVWX
5 ns
T
QVWH
155 ns
T
WHQX
10 ns
T
RLAZ
0 ns
T
WHLH
5 45 ns
121
4235K–8051–05/08
AT89C51RD2/ED2
25.3.5 External Data Memory Write Cycle
Table 25-6. AC Parameters for a Variable Clock
Symbol Type
Standard
Clock X2 Clock
X parameter for
-M range Units
T
RLRH
Min 6 T - x 3 T - x 25 ns
T
WLWH
Min 6 T - x 3 T - x 25 ns
T
RLDV
Max 5 T - x 2.5 T - x 30 ns
T
RHDX
Min x x 0 ns
T
RHDZ
Max 2 T - x T - x 25 ns
T
LLDV
Max 8 T - x 4T -x 45 ns
T
AVDV
Max 9 T - x 4.5 T - x 65 ns
T
LLWL
Min 3 T - x 1.5 T - x 30 ns
T
LLWL
Max 3 T + x 1.5 T + x 30 ns
T
AVWL
Min 4 T - x 2 T - x 30 ns
T
QVWX
Min T - x 0.5 T - x 20 ns
T
QVWH
Min 7 T - x 3.5 T - x 20 ns
T
WHQX
Min T - x 0.5 T - x 15 ns
T
RLAZ
Max x x 0 ns
T
WHLH
Min T - x 0.5 T - x 20 ns
T
WHLH
Max T + x 0.5 T + x 20 ns
T
QVWH
T
LLAX
ALE
PSEN
WR
PORT 0
PORT 2
A0-A7 DATA OUT
ADDRESS
OR SFR-P2
T
AVWL
T
LLWL
T
QVWX
ADDRESS A8-A15 OR SFR P2
T
WHQX
T
WHLH
T
WLWH
122
4235K–8051–05/08
AT89C51RD2/ED2
25.3.6 External Data Memory Read Cycle
25.3.7 Serial Port Timing - Shift Register Mode
Table 25-7. Symbol Description
Table 25-8. AC Parameters for a Fix Clock
ALE
PSEN
RD
PORT 0
PORT 2
A0-A7 DATA IN
ADDRESS
OR SFR-P2
T
AVWL
T
LLWL
T
RLAZ
ADDRESS A8-A15 OR SFR P2
T
RHDZ
T
WHLH
T
RLRH
T
LLDV
T
RHDX
T
LLAX
T
AVDV
Symbol Parameter
T
XLXL
Serial port clock cycle time
T
QVHX
Output data set-up to clock rising edge
T
XHQX
Output data hold after clock rising edge
T
XHDX
Input data hold after clock rising edge
T
XHDV
Clock rising edge to input data valid
Symbol
-M
UnitsMin Max
T
XLXL
300 ns
T
QVHX
200 ns
T
XHQX
30 ns
T
XHDX
0 ns
T
XHDV
117 ns
123
4235K–8051–05/08
AT89C51RD2/ED2
Table 25-9. AC Parameters for a Variable Clock
25.3.8 Shift Register Timing Waveforms
25.3.9 External Clock Drive Waveforms
25.3.10 AC Testing Input/Output Waveforms
AC inputs during testing are driven at V
CC
- 0.5 for a logic 1” and 0.45V for a logic “0”. Timing
measurement are made at V
IH
min for a logic “1” and V
IL
max for a logic “0”.
Symbol Type
Standard
Clock X2 Clock
X Parameter For
-M Range Units
T
XLXL
Min 12 T 6 T ns
T
QVHX
Min 10 T - x 5 T - x 50 ns
T
XHQX
Min 2 T - x T - x 20 ns
T
XHDX
Min x x 0 ns
T
XHDV
Max 10 T - x 5 T- x 133 ns
INPUT DATA
VALIDVALID VALID VALID
0 1 2 3 4 5 6 87
ALE
CLOCK
OUTPUT DATA
WRITE to SBUF
CLEAR RI
T
XLXL
T
QVXH
T
XHQX
T
XHDV
T
XHDX
SET TI
SET RI
INSTRUCTION
0 1 2 3 4 5 6 7
VALID VALID VALID VALID
V
CC
-0.5V
0.45V
0.7V
CC
0.2V
CC
-0.1
T
CHCL
T
CLCX
T
CLCL
T
CLCH
T
CHCX
INPUT/OUTPUT 0.2 V
CC
+ 0.9
0.2 V
CC
- 0.1
V
CC
-0.5V
0.45V
124
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AT89C51RD2/ED2
25.3.11 Float Waveforms
For timing purposes as port pin is no longer floating when a 100 mV change from load voltage
occurs and begins to float when a 100 mV change from the loaded V
OH
/V
OL
level occurs. I
OL
/I
OH
± 20 mA.
25.3.12 Clock Waveforms
Valid in normal clock mode. In X2 mode XTAL2 must be changed to XTAL2/2.
FLOAT
V
OH
- 0.1V
V
OL
+ 0.1V
V
LOAD
V
LOAD
+ 0.1V
V
LOAD
- 0.1V
125
4235K–8051–05/08
AT89C51RD2/ED2
Figure 25-5. Internal Clock Signals
This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however,
ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin loading. Propa-
gation also varies from output to output and component. Typically though (T
A
= 25°C fully loaded) RD and WR propagation
delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC
specifications.
DATA PCL OUT DATA PCL OUT DATA PCL OUT
SAMPLED SAMPLED SAMPLED
STATE4 STATE5 STATE6 STATE1 STATE2 STATE3 STATE4 STATE5
P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2
FLOAT FLOAT FLOAT
THESE SIGNALS ARE NOT ACTIVATED DURING THE
EXECUTION OF A MOVX INSTRUCTION
INDICATES ADDRESS TRANSITIONS
EXTERNAL PROGRAM MEMORY FETCH
FLOAT
DATA
SAMPLED
DPL OR Rt OUT
INDICATES DPH OR P2 SFR TO PCH TRANSITION
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
PCL OUT (EVEN IF PROGRAM
MEMORY IS INTERNAL)
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
OLD DATA NEW DATA
P0 PINS SAMPLED
P1, P2, P3 PINS SAMPLED P1, P2, P3 PINS SAMPLED
P0 PINS SAMPLED
RXD SAMPLED
INTERNAL
CLOCK
XTAL2
ALE
PSEN
P0
P2 (EXT)
READ CYCLE
WRITE CYCLE
RD
P0
P2
WR
PORT OPERATION
MOV PORT SRC
MOV DEST P0
MOV DEST PORT (P1. P2. P3)
(INCLUDES INTO. INT1. TO T1)
SERIAL PORT SHIFT CLOCK
TXD (MODE 0)
DATA OUT
DPL OR Rt OUT
INDICATES DPH OR P2 SFR TO PCH TRANSITION
P0
P2
RXD SAMPLED
126
4235K–8051–05/08
AT89C51RD2/ED2
26. Ordering Information
Note: 1. For PLCC68 and VQFP64 packages, please contact Atmel sales office for availability.
Table 26-1. Possible Order Entries
Part Number Data EEPROM Supply Voltage
Temperature
Range Package Packing Product Marking
AT89C51RD2-SLSUM
No
2.7V - 5.5V Industrial &
Green
PLCC44 Stick AT89C51RD2-UM
AT89C51RD2-RLTUM VQFP44 Tray AT89C51RD2-UM
AT89C51RD2-RDTUM
(1)
VQFP64 Tray AT89C51RD2-UM
AT89C51RD2-SMSUM
(1)
PLCC68 Stick AT89C51RD2-UM
AT89C51ED2-SLSUM
Yes
PLCC44 Stick AT89C51ED2-UM
AT89C51ED2-RLTUM VQFP44 Tray AT89C51ED2-UM
AT89C51ED2- SMSUM PLCC68 Stick AT89C51ED2-UM
AT89C51ED2-RDTUM VQFP64 Tray AT89C51ED2-UM
127
4235K–8051–05/08
AT89C51RD2/ED2
27. Packaging Information
27.1 PLCC44
128
4235K–8051–05/08
AT89C51RD2/ED2
STANDARD NOTES FOR PLCC
1/ CONTROLLING DIMENSIONS : INCHES
2/ DIMENSIONING AND TOLERANCING PER ANSI Y 14.5M - 1982.
3/ "D" AND "E1" DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTUSIONS.
MOLD FLASH OR PROTUSIONS SHALL NOT EXCEED 0.20 mm (.008 INCH) PER
SIDE.
129
4235K–8051–05/08
AT89C51RD2/ED2
27.2 VQFP44
130
4235K–8051–05/08
AT89C51RD2/ED2
STANDARD NOTES FOR PQFP/ VQFP / TQFP / DQFP
1/ CONTROLLING DIMENSIONS : INCHES
2/ ALL DIMENSIONING AND TOLERANCING CONFORM TO ANSI Y 14.5M -
1982.
3/ "D1 AND E1" DIMENSIONS DO NOT INCLUDE MOLD PROTUSIONS.
MOLD PROTUSIONS SHALL NOT EXCEED 0.25 mm (0.010 INCH).
THE TOP PACKAGE BODY SIZE MAY BE SMALLER THAN THE BOTTOM
PACKAGE BODY SIZE BY AS MUCH AS 0.15 mm.
4/ DATUM PLANE "H" LOCATED AT MOLD PARTING LINE AND
COINCIDENT WITH LEAD, WHERE LEAD EXITS PLASTIC BODY AT
BOTTOM OF PARTING LINE.
5/ DATUM "A" AND "D" TO BE DETERMINED AT DATUM PLANE H.
6/ DIMENSION " f " DOES NOT INCLUDE DAMBAR PROTUSION ALLOWABLE
DAMBAR PROTUSION SHALL BE 0.08mm/.003" TOTAL IN EXCESS OF THE
" f " DIMENSION AT MAXIMUM MATERIAL CONDITION .
DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT.
131
4235K–8051–05/08
AT89C51RD2/ED2
27.3 PLCC68
132
4235K–8051–05/08
AT89C51RD2/ED2
27.4 VQFP64
133
4235K–8051–05/08
AT89C51RD2/ED2
28. Document Revision History
28.1 Changes from 4235A -04/03 to 4135B - 06/03
1. V
IH
min changed from 0.2 V
CC
+ 1.1 to 0.2 V
CC
+ 0.9.
2. Added POR/PFD and reset specific sections.
3. Added DIL40 package.
4. Added Flash write programming time specification.
28.2 Changes from 4235B -06/03 to 4235C - 08/03
1. Changed maximum frequency to 60 MHz in X1 mode and 30 MHz in X2 mode for Vcc =
4.5V to 5.5V and internal code execution.
2. Added PDIL40 Packaging for AT89C51ED2.
28.3 Changes from 4235C - 08/03 to 4235D - 12/03
1. Improved explanations throughout the document.
28.4 Changes from 4235D - 12/03 to 4235E - 04/04
1. Improved explanations throughout the document.
28.5 Changes from 4235E - 04/04 to 4235F - 09/04
1. Improved explanations in Flash and EEPROM sections.
28.6 Changes from 4235F - 09/04 to 4235G 08/05
1. Added ‘Industrial & Green” product versions.
28.7 Changes from 4235G 08/05 to 4235H - 10/06
1. Correction to PDIL figure on page 9.
28.8 Changes from 4235H - 10/06 to 4235I - 04/07
1. Removal of PDIL40 package offering.
28.9 Changes from 4235I - 04/07 to 4235J - 01/08
1. Minor corrections throughout the document.
2. Updated Package drawings.
28.10 Changes from 4235J - 01/08 to 4235K - 05/08
1. Removed non-green packages from product ordering information.
135
4235K–8051–05/08
AT89C51RD2/ED2
Features .................................................................................................... 1
1 Description ............................................................................................... 2
2 Block Diagram .......................................................................................... 3
3 SFR Mapping ............................................................................................ 4
4 Pin Configurations ................................................................................... 9
5 Port Types .............................................................................................. 14
6 Oscillator ................................................................................................ 15
6.1 Registers .........................................................................................................15
6.2 Functional Block Diagram ................................................................................16
7 Enhanced Features ................................................................................ 17
7.1 X2 Feature .......................................................................................................17
8 Dual Data Pointer Register (DPTR) ...................................................... 21
9 Expanded RAM (XRAM) ......................................................................... 23
9.1 Registers .........................................................................................................24
10 Reset ....................................................................................................... 26
10.1 Introduction ......................................................................................................26
10.2 Reset Input ......................................................................................................26
10.3 Reset Output ...................................................................................................26
11 Power Monitor ........................................................................................ 28
11.1 Description .......................................................................................................28
12 Timer 2 .................................................................................................... 30
12.1 Auto-reload Mode ............................................................................................30
12.2 Programmable Clock-output ............................................................................31
12.3 Registers .........................................................................................................32
13 Programmable Counter Array (PCA) .................................................... 35
13.1 PCA Capture Mode .........................................................................................43
13.2 16-bit Software Timer/ Compare Mode ...........................................................43
13.3 High Speed Output Mode ................................................................................44
13.4 Pulse Width Modulator Mode ..........................................................................45
13.5 PCA Watchdog Timer ......................................................................................46
136
4235K–8051–05/08
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14 Serial I/O Port ......................................................................................... 48
14.1 Framing Error Detection ..................................................................................48
14.2 Automatic Address Recognition ......................................................................49
14.3 Registers .........................................................................................................51
14.4 Baud Rate Selection for UART for Mode 1 and 3 ............................................51
14.5 UART Registers ...............................................................................................54
15 Keyboard Interface ................................................................................ 59
15.1 Registers .........................................................................................................60
16 Serial Port Interface (SPI) ...................................................................... 63
16.1 Features ..........................................................................................................63
16.2 Signal Description ............................................................................................63
16.3 Functional Description .....................................................................................65
17 Interrupt System .................................................................................... 72
17.1 Registers .........................................................................................................73
17.2 Interrupt Sources and Vector Addresses .........................................................73
18 Power Management ............................................................................... 80
18.1 Introduction ......................................................................................................80
18.2 Idle Mode .........................................................................................................80
18.3 Power-Down Mode ..........................................................................................81
18.4 Registers .........................................................................................................83
19 Hardware Watchdog Timer ................................................................... 84
19.1 Using the WDT ................................................................................................84
19.2 WDT during Power-down and Idle ...................................................................85
20 ONCE
®
Mode (ON- Chip Emulation) ..................................................... 86
21 Power-off Flag ........................................................................................ 87
22 Reduced EMI Mode ................................................................................ 88
23 EEPROM Data Memory .......................................................................... 89
23.1 Write Data ........................................................................................................89
23.2 Read Data .......................................................................................................90
23.3 Registers .........................................................................................................91
24 Flash/EEPROM Memory ........................................................................ 93
24.1 Features ..........................................................................................................93
24.2 Flash Programming and Erasure .....................................................................93
137
4235K–8051–05/08
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24.3 Flash Registers and Memory Map ...................................................................94
24.4 Flash Memory Status....................................................................................... 97
24.5 Memory Organization ......................................................................................97
24.6 Bootloader Architecture ...................................................................................97
24.7 ISP Protocol Description ................................................................................102
24.8 Functional Description ...................................................................................103
24.9 Flow Description ............................................................................................104
24.10 API Call Description .......................................................................................112
25 Electrical Characteristics .................................................................... 114
25.1 Absolute Maximum Ratings ...........................................................................114
25.2 DC Parameters for Standard Voltage ............................................................114
25.3 AC Parameters ..............................................................................................117
26 Ordering Information ........................................................................... 126
27 Packaging Information ........................................................................ 127
27.1 PLCC44 .........................................................................................................127
27.2 VQFP44 .........................................................................................................129
27.3 PLCC68 .........................................................................................................131
27.4 VQFP64 .........................................................................................................132
28 Document Revision History ................................................................ 133
28.1 Changes from 4235A -04/03 to 4135B - 06/03 ..............................................133
28.2 Changes from 4235B -06/03 to 4235C - 08/03 ..............................................133
28.3 Changes from 4235C - 08/03 to 4235D - 12/03 ............................................133
28.4 Changes from 4235D - 12/03 to 4235E - 04/04 .............................................133
28.5 Changes from 4235E - 04/04 to 4235F - 09/04 .............................................133
28.6 Changes from 4235F - 09/04 to 4235G 08/05 ...............................................133
28.7 Changes from 4235G 08/05 to 4235H - 10/06 ..............................................133
28.8 Changes from 4235H - 10/06 to 4235I - 04/07 ..............................................133
28.9 Changes from 4235I - 04/07 to 4235J - 01/08 ...............................................133
28.10 Changes from 4235J - 01/08 to 4235K - 05/08 .............................................133
4235K–8051–05/08
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