Cyclone V Device Datasheet
2016.12.09
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is datasheet describes the electrical characteristics, switching characteristics, conguration specications, and I/O timing for Cyclone® V devices.
Cyclone V devices are oered in commercial and industrial grades. Commercial devices are oered in –C6 (fastest), –C7, and –C8 speed grades.
Industrial grade devices are oered in the –I7 speed grade. Automotive devices are oered in the –A7 speed grade.
Related Information
Cyclone V Device Overview
Provides more information about the densities and packages of devices in the Cyclone V family.
Electrical Characteristics
e following sections describe the operating conditions and power consumption of Cyclone V devices.
Operating Conditions
Cyclone V devices are rated according to a set of dened parameters. To maintain the highest possible performance and reliability of the Cyclone V
devices, you must consider the operating requirements described in this section.
Absolute Maximum Ratings
is section denes the maximum operating conditions for Cyclone V devices. e values are based on experiments conducted with the devices
and theoretical modeling of breakdown and damage mechanisms.
e functional operation of the device is not implied for these conditions.
Caution: Conditions outside the range listed in the following table may cause permanent damage tothe device. Additionally, device operation at
the absolute maximum ratings for extended periods of time may have adverse eects on the device.
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at
any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specications before relying on any published information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
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Table 1: Absolute Maximum Ratings for Cyclone V Devices
Symbol Description Minimum Maximum Unit
VCC Core voltage and periphery circuitry power supply –0.5 1.43 V
VCCPGM Conguration pins power supply –0.5 3.90 V
VCC_AUX Auxiliary supply –0.5 3.25 V
VCCBAT Battery back-up power supply for design security volatile key
register
–0.5 3.90 V
VCCPD I/O pre-driver power supply –0.5 3.90 V
VCCIO I/O power supply –0.5 3.90 V
VCCA_FPLL Phase-locked loop (PLL) analog power supply –0.5 3.25 V
VCCH_GXB Transceiver high voltage power –0.5 3.25 V
VCCE_GXB Transceiver power –0.5 1.50 V
VCCL_GXB Transceiver clock network power –0.5 1.50 V
VIDC input voltage –0.5 3.80 V
VCC_HPS HPS core voltage and periphery circuitry power supply –0.5 1.43 V
VCCPD_HPS HPS I/O pre-driver power supply –0.5 3.90 V
VCCIO_HPS HPS I/O power supply –0.5 3.90 V
VCCRSTCLK_HPS HPS reset and clock input pins power supply –0.5 3.90 V
VCCPLL_HPS HPS PLL analog power supply –0.5 3.25 V
VCC_AUX_SHARED(1) HPS auxiliary power supply –0.5 3.25 V
IOUT DC output current per pin –25 40 mA
TJOperating junction temperature –55 125 °C
TSTG Storage temperature (no bias) –65 150 °C
(1) VCC_AUX_SHARED must be powered by the same source as VCC_AUX for Cyclone V SX C5, C6, D5, and D6 devices, and Cyclone V SE A5 and A6
devices.
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Altera Corporation Cyclone V Device Datasheet
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Maximum Allowed Overshoot and Undershoot Voltage
During transitions, input signals may overshoot to the voltage listed in the following table and undershoot to –2.0 V for input currents less than 100
mA and periods shorter than 20 ns.
e maximum allowed overshoot duration is specied as a percentage of high time over the lifetime of the device. A DC signal is equivalent to
100% duty cycle.
For example, a signal that overshoots to 4.00 V can only be at 4.00 V for ~15% over the lifetime of the device; for a device lifetime of 10 years, this
amounts to 1.5 years.
Table 2: Maximum Allowed Overshoot During Transitions for Cyclone V Devices
is table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime.
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Symbol Description Condition (V) Overshoot Duration as % of High Time Unit
Vi (AC) AC input voltage
3.8 100 %
3.85 68 %
3.9 45 %
3.95 28 %
4 15 %
4.05 13 %
4.1 11 %
4.15 9 %
4.2 8 %
4.25 7 %
4.3 5.4 %
4.35 3.2 %
4.4 1.9 %
4.45 1.1 %
4.5 0.6 %
4.55 0.4 %
4.6 0.2 %
Recommended Operating Conditions
is section lists the functional operation limits for the AC and DC parameters for Cyclone V devices.
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Recommended Operating Conditions
Table 3: Recommended Operating Conditions for Cyclone V Devices
is table lists the steady-state voltage values expected from Cyclone V devices. Power supply ramps must all be strictly monotonic, without
plateaus.
Symbol Description Condition Minimum(2) Typical Maximum(2) Unit
VCC
Core voltage, periphery circuitry power
supply, transceiver physical coding
sublayer (PCS) power supply, and
transceiver PCI Express® (PCIe®) hard IP
digital power supply
Devices without
internal scrubbing
feature
1.07 1.1 1.13 V
Devices with internal
scrubbing feature (with
SC sux) (3)
1.12 1.15 1.18 V
VCC_AUX Auxiliary supply — 2.375 2.5 2.625 V
VCCPD(4) I/O pre-driver power supply
3.3 V 3.135 3.3 3.465 V
3.0 V 2.85 3.0 3.15 V
2.5 V 2.375 2.5 2.625 V
(2) e power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements.
Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.
(3) e SEU internal scrubbing feature is available for Cyclone V E, GX, SE, and SX devices with the "SC" sux in the part number. For device availability
and ordering, contact your local Altera sales representatives.
(4) VCCPD must be 2.5 V when VCCIO is 2.5, 1.8, 1.5, 1.35, 1.25, or 1.2 V. VCCPD must be 3.0 V when VCCIO is 3.0 V. VCCPD must be 3.3 V when VCCIO is
3.3 V.
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Symbol Description Condition Minimum(2) Typical Maximum(2) Unit
VCCIO I/O buers power supply
3.3 V 3.135 3.3 3.465 V
3.0 V 2.85 3.0 3.15 V
2.5 V 2.375 2.5 2.625 V
1.8 V 1.71 1.8 1.89 V
1.5 V 1.425 1.5 1.575 V
1.35 V 1.283 1.35 1.418 V
1.25 V 1.19 1.25 1.31 V
1.2 V 1.14 1.2 1.26 V
VCCPGM Conguration pins power supply
3.3 V 3.135 3.3 3.465 V
3.0 V 2.85 3.0 3.15 V
2.5 V 2.375 2.5 2.625 V
1.8 V 1.71 1.8 1.89 V
VCCA_FPLL(5) PLL analog voltage regulator power
supply
— 2.375 2.5 2.625 V
VCCBAT(6) Battery back-up power supply
(For design security volatile key register)
— 1.2 — 3.0 V
VIDC input voltage — –0.5 — 3.6 V
VOOutput voltage — 0 — VCCIO V
(2) e power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements.
Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.
(5) PLL digital voltage is regulated from VCCA_FPLL.
(6) If you do not use the design security feature in Cyclone V devices, connect VCCBAT to a 1.5-V, 2.5-V, or 3.0-V power supply. Cyclone V power-on reset
(POR) circuitry monitors VCCBAT. Cyclone V devices do not exit POR if VCCBAT is not powered up.
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Symbol Description Condition Minimum(2) Typical Maximum(2) Unit
TJOperating junction temperature
Commercial 0 — 85 °C
Industrial –40 — 100 °C
Automotive –40 — 125 °C
tRAMP(7) Power supply ramp time Standard POR 200µs — 100ms —
Fast POR 200µs — 4ms —
Transceiver Power Supply Operating Conditions
Table 4: Transceiver Power Supply Operating Conditions for Cyclone V GX, GT, SX, and ST Devices
Symbol Description Minimum(8) Typical Maximum(8) Unit
VCCH_GXBL Transceiver high voltage power (le side) 2.375 2.5 2.625 V
VCCE_GXBL(9)(10) Transmitter and receiver power (le side) 1.07/1.17 1.1/1.2 1.13/1.23 V
VCCL_GXBL(9)(10) Clock network power (le side) 1.07/1.17 1.1/1.2 1.13/1.23 V
(2) e power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements.
Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.
(7) is is also applicable to HPS power supply. For HPS power supply, refer to tRAMP specications for standard POR when HPS_PORSEL = 0 and tRAMP
specications for fast POR when HPS_PORSEL = 1.
(8) e power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements.
Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.
(9) Altera recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V to 1.2 V for Cyclone V GT and ST FPGA systems which
require full compliance to the PCIe Gen2 transmit jitter specication. For more information about the maximum full duplex channels recommended
in Cyclone V GT and ST devices under this condition, refer to the Transceiver Protocol Congurations in Cyclone V Devices chapter.
(10) Altera recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V to 1.2 V for full compliance to CPRI transmit jitter specica‐
tion at 4.9152 Gbps ( Cyclone V GT and ST devices) and 6.144Gbps ( Cyclone V GT and ST devices only). For more information about the maximum
full duplex channels recommended in Cyclone V GT and ST devices for CPRI 6.144 Gbps, refer to the Transceiver Protocol Congurations in Cyclone
V Devices chapter.
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2016.12.09 Transceiver Power Supply Operating Conditions 7
Cyclone V Device Datasheet Altera Corporation
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Related Information
•PCIe Supported Congurations and Placement Guidelines
Provides more information about the maximum full duplex channels recommended in Cyclone V GT and ST devices which require full
compliance to the PCIe Gen2 transmit jitter specication.
•6.144-Gbps Support Capability in Cyclone V GT Devices
Provides more information about the maximum full duplex channels recommended in Cyclone V GT and ST devices for CPRI 6.144 Gbps.
HPS Power Supply Operating Conditions
Table 5: HPS Power Supply Operating Conditions for Cyclone V SX and ST Devices
is table lists the steady-state voltage and current values expected from Cyclone V system-on-a-chip (SoC) devices with ARM®-based hard
processor system (HPS). Power supply ramps must all be strictly monotonic, without plateaus. Refer to Recommended Operating Conditions for
Cyclone V Devices table for the steady-state voltage values expected from the FPGA portion of the Cyclone V SoC devices.
Symbol Description Condition Minimum(11) Typical Maximum(11) Unit
VCC_HPS HPS core voltage and periphery circuitry
power supply
— 1.07 1.1 1.13 V
VCCPD_HPS (12) HPS I/O pre-driver power supply
3.3 V 3.135 3.3 3.465 V
3.0 V 2.85 3.0 3.15 V
2.5 V 2.375 2.5 2.625 V
(11) e power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements.
Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.
(12) VCCPD_HPS must be 2.5 V when VCCIO_HPS is 2.5, 1.8, 1.5, or 1.2 V. VCCPD_HPS must be 3.0 V when VCCIO_HPS is 3.0 V. VCCPD_HPS must be 3.3 V when
VCCIO_HPS is 3.3 V.
8HPS Power Supply Operating Conditions CV-51002
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Symbol Description Condition Minimum(11) Typical Maximum(11) Unit
VCCIO_HPS HPS I/O buers power supply
3.3 V 3.135 3.3 3.465 V
3.0 V 2.85 3.0 3.15 V
2.5 V 2.375 2.5 2.625 V
1.8 V 1.71 1.8 1.89 V
1.5 V 1.425 1.5 1.575 V
1.35 V (13) 1.283 1.35 1.418 V
1.2 V 1.14 1.2 1.26 V
VCCRSTCLK_HPS HPS reset and clock input pins power
supply
3.3 V 3.135 3.3 3.465 V
3.0 V 2.85 3.0 3.15 V
2.5 V 2.375 2.5 2.625 V
1.8 V 1.71 1.8 1.89 V
VCCPLL_HPS HPS PLL analog voltage regulator power
supply
— 2.375 2.5 2.625 V
VCC_AUX_
SHARED(14)
HPS auxiliary power supply — 2.375 2.5 2.625 V
Related Information
Recommended Operating Conditions on page 5
Provides the steady-state voltage values for the FPGA portion of the device.
(11) e power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements.
Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.
(13) VCCIO_HPS 1.35 V is supported for HPS row I/O bank only.
(14) VCC_AUX_SHARED must be powered by the same source as VCC_AUX for Cyclone V SX C5, C6, D5, and D6 devices, and Cyclone V SE A5 and A6
devices.
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Cyclone V Device Datasheet Altera Corporation
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DC Characteristics
Supply Current and Power Consumption
Altera oers two ways to estimate power for your design—the Excel-based Early Power Estimator (EPE) and the Quartus® Prime PowerPlay Power
Analyzer feature.
Use the Excel-based EPE before you start your design to estimate the supply current for your design. e EPE provides a magnitude estimate of the
device power because these currents vary greatly with the resources you use.
e Quartus Prime PowerPlay Power Analyzer provides better quality estimates based on the specics of the design aer you complete place-and-
route. e PowerPlay Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities that, when
combined with detailed circuit models, yields very accurate power estimates.
Related Information
•PowerPlay Early Power Estimator User Guide
Provides more information about power estimation tools.
•PowerPlay Power Analysis chapter, Quartus Prime Handbook
Provides more information about power estimation tools.
I/O Pin Leakage Current
Table 6: I/O Pin Leakage Current for Cyclone V Devices
Symbol Description Condition Min Typ Max Unit
IIInput pin VI = 0 V to VCCIOMAX –30 — 30 µA
IOZ Tri-stated I/O pin VO = 0 V to VCCIOMAX –30 — 30 µA
Bus Hold Specications
Table 7: Bus Hold Parameters for Cyclone V Devices
e bus-hold trip points are based on calculated input voltages from the JEDEC standard.
10 DC Characteristics CV-51002
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Parameter Symbol Condition
VCCIO (V)
Unit1.2 1.5 1.8 2.5 3.0 3.3
Min Max Min Max Min Max Min Max Min Max Min Max
Bus-hold,
low,
sustaining
current
ISUSL VIN > VIL
(max)
8 — 12 — 30 — 50 — 70 — 70 — µA
Bus-hold,
high,
sustaining
current
ISUSH VIN < VIH
(min)
–8 — –12 — –30 — –50 — –70 — –70 — µA
Bus-hold,
low,
overdrive
current
IODL 0 V < VIN
< VCCIO
— 125 — 175 — 200 — 300 — 500 — 500 µA
Bus-hold,
high,
overdrive
current
IODH 0 V <VIN
<VCCIO
— –125 — –175 — –200 — –300 — –500 — –500 µA
Bus-hold
trip point
VTRIP — 0.3 0.9 0.375 1.125 0.68 1.07 0.7 1.7 0.8 2 0.8 2 V
OCT Calibration Accuracy Specications
If you enable on-chip termination (OCT) calibration, calibration is automatically performed at power up for I/Os connected to the calibration
block.
Table 8: OCT Calibration Accuracy Specications for Cyclone V Devices
Calibration accuracy for the calibrated on-chip series termination (RS OCT) and on-chip parallel termination (RT OCT) are applicable at the
moment of calibration. When process, voltage, and temperature (PVT) conditions change aer calibration, the tolerance may change.
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Symbol Description Condition (V)
Calibration Accuracy
Unit
–C6 –I7, –C7 –C8, –A7
25-Ω RSInternal series termination with
calibration (25-Ω setting)
VCCIO = 3.0, 2.5, 1.8, 1.5,
1.2
±15 ±15 ±15 %
50-Ω RSInternal series termination with
calibration (50-Ω setting)
VCCIO = 3.0, 2.5, 1.8, 1.5,
1.2
±15 ±15 ±15 %
34-Ω and 40-Ω RSInternal series termination with
calibration (34-Ω and 40-Ω
setting)
VCCIO = 1.5, 1.35, 1.25,
1.2
±15 ±15 ±15 %
48-Ω, 60-Ω, and 80-
Ω RS
Internal series termination with
calibration (48-Ω, 60-Ω, and
80-Ω setting)
VCCIO = 1.2 ±15 ±15 ±15 %
50-Ω RTInternal parallel termination
with calibration (50-Ω setting)
VCCIO = 2.5, 1.8, 1.5, 1.2 –10 to +40 –10 to +40 –10 to +40 %
20-Ω, 30-Ω, 40-Ω,60-
Ω, and 120-Ω RT
Internal parallel termination
with calibration (20-Ω, 30-Ω,
40-Ω, 60-Ω, and 120-Ω setting)
VCCIO = 1.5, 1.35, 1.25 –10 to +40 –10 to +40 –10 to +40 %
60-Ω and 120-Ω RTInternal parallel termination
with calibration (60-Ω and 120-
Ω setting)
VCCIO = 1.2 –10 to +40 –10 to +40 –10 to +40 %
25-Ω RS_le_shi Internal le shi series
termination with calibration
(25-Ω RS_le_shi setting)
VCCIO = 3.0, 2.5, 1.8, 1.5,
1.2
±15 ±15 ±15 %
OCT Without Calibration Resistance Tolerance Specications
Table 9: OCT Without Calibration Resistance Tolerance Specications for Cyclone V Devices
is table lists the Cyclone V OCT without calibration resistance tolerance to PVT changes.
12 OCT Without Calibration Resistance Tolerance Specications CV-51002
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Symbol Description Condition (V)
ResistanceTolerance
Unit
–C6 –I7, –C7 –C8, –A7
25-Ω RSInternal series termination without
calibration (25-Ω setting)
VCCIO = 3.0, 2.5 ±30 ±40 ±40 %
25-Ω RSInternal series termination without
calibration (25-Ω setting)
VCCIO = 1.8, 1.5 ±30 ±40 ±40 %
25-Ω RSInternal series termination without
calibration (25-Ω setting)
VCCIO = 1.2 ±35 ±50 ±50 %
50-Ω RSInternal series termination without
calibration (50-Ω setting)
VCCIO = 3.0, 2.5 ±30 ±40 ±40 %
50-Ω RSInternal series termination without
calibration (50-Ω setting)
VCCIO = 1.8, 1.5 ±30 ±40 ±40 %
50-Ω RSInternal series termination without
calibration (50-Ω setting)
VCCIO = 1.2 ±35 ±50 ±50 %
100-Ω RDInternal dierential termination
(100-Ω setting)
VCCIO = 2.5 ±25 ±40 ±40 %
Figure 1: Equation for OCT Variation Without Recalibration
e denitions for the equation are as follows:
•e ROCT value calculated shows the range of OCT resistance with the variation of temperature and VCCIO.
• RSCAL is the OCT resistance value at power-up.
• ΔT is the variation of temperature with respect to the temperature at power up.
• ΔV is the variation of voltage with respect to the VCCIO at power up.
• dR/dT is the percentage change of RSCAL with temperature.
• dR/dV is the percentage change of RSCAL with voltage.
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2016.12.09 OCT Without Calibration Resistance Tolerance Specications 13
Cyclone V Device Datasheet Altera Corporation
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OCT Variation after Power-Up Calibration
Table 10: OCT Variation after Power-Up Calibration for Cyclone V Devices
is table lists OCT variation with temperature and voltage aer power-up calibration. e OCT variation is valid for a VCCIO range of ±5% and a
temperature range of 0°C to 85°C.
Symbol Description VCCIO (V) Value Unit
dR/dV OCT variation with voltage without recalibration
3.0 0.100
%/mV
2.5 0.100
1.8 0.100
1.5 0.100
1.35 0.150
1.25 0.150
1.2 0.150
dR/dT OCT variation with temperature without
recalibration
3.0 0.189
%/°C
2.5 0.208
1.8 0.266
1.5 0.273
1.35 0.200
1.25 0.200
1.2 0.317
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Pin Capacitance
Table 11: Pin Capacitance for Cyclone V Devices
Symbol Description Maximum Unit
CIOTB Input capacitance on top and bottom I/O pins 6 pF
CIOLR Input capacitance on le and right I/O pins 6 pF
COUTFB Input capacitance on dual-purpose clock output and feedback pins 6 pF
Hot Socketing
Table 12: Hot Socketing Specications for Cyclone V Devices
Symbol Description Maximum Unit
IIOPIN (DC) DC current per I/O pin 300 μA
IIOPIN (AC) AC current per I/O pin 8(15) mA
IXCVR-TX (DC) DC current per transceiver transmitter (TX) pin 100 mA
IXCVR-RX (DC) DC current per transceiver receiver (RX) pin 50 mA
Internal Weak Pull-Up Resistor
All I/O pins, except conguration, test, and JTAG pins, have an option to enable weak pull-up.
(15) e I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C dv/dt, in which C is the I/O pin capacitance and dv/dt is the slew
rate.
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Table 13: Internal Weak Pull-Up Resistor Values for Cyclone V Devices
Symbol Description Condition (V)(16) Value(17) Unit
RPU
Value of the I/O pin pull-up resistor before and during
conguration, as well as user mode if you have enabled the
programmable pull-up resistor option.
VCCIO = 3.3 ±5% 25 kΩ
VCCIO = 3.0 ±5% 25 kΩ
VCCIO = 2.5 ±5% 25 kΩ
VCCIO = 1.8 ±5% 25 kΩ
VCCIO = 1.5 ±5% 25 kΩ
VCCIO = 1.35 ±5% 25 kΩ
VCCIO = 1.25 ±5% 25 kΩ
VCCIO = 1.2 ±5% 25 kΩ
Related Information
Cyclone V Device Family Pin Connection Guidelines
Provides more information about the pins that support internal weak pull-up and internal weak pull-down features.
I/O Standard Specications
Tables in this section list the input voltage (VIH and VIL), output voltage (VOH and VOL), and current drive characteristics (IOH and IOL) for various
I/O standards supported by Cyclone V devices.
You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards.
(16) Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO.
(17) Valid with ±10% tolerances to cover changes over PVT.
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Single-Ended I/O Standards
Table 14: Single-Ended I/O Standards for Cyclone V Devices
I/O Standard
VCCIO (V) VIL (V) VIH (V) VOL (V) VOH (V) IOL(18)
(mA) IOH(18) (mA)
Min Typ Max Min Max Min Max Max Min
3.3-V
LVTTL
3.135 3.3 3.465 –0.3 0.8 1.7 3.6 0.45 2.4 4 –4
3.3-V
LVCMOS
3.135 3.3 3.465 –0.3 0.8 1.7 3.6 0.2 VCCIO – 0.2 2 –2
3.0-V
LVTTL
2.85 3 3.15 –0.3 0.8 1.7 3.6 0.4 2.4 2 –2
3.0-V
LVCMOS
2.85 3 3.15 –0.3 0.8 1.7 3.6 0.2 VCCIO – 0.2 0.1 –0.1
3.0-V PCI 2.85 3 3.15 — 0.3 × VCCIO 0.5 × VCCIO VCCIO + 0.3 0.1 × VCCIO 0.9 × VCCIO 1.5 –0.5
3.0-V
PCI-X
2.85 3 3.15 — 0.35 × VCCIO 0.5 × VCCIO VCCIO + 0.3 0.1 × VCCIO 0.9 × VCCIO 1.5 –0.5
2.5 V 2.375 2.5 2.625 –0.3 0.7 1.7 3.6 0.4 2 1 –1
1.8 V 1.71 1.8 1.89 –0.3 0.35 × VCCIO 0.65 × VCCIO VCCIO + 0.3 0.45 VCCIO – 0.45 2 –2
1.5 V 1.425 1.5 1.575 –0.3 0.35 × VCCIO 0.65 × VCCIO VCCIO + 0.3 0.25 × VCCIO 0.75 × VCCIO 2 –2
1.2 V 1.14 1.2 1.26 –0.3 0.35 × VCCIO 0.65 × VCCIO VCCIO + 0.3 0.25 × VCCIO 0.75 × VCCIO 2 –2
(18) To meet the IOL and IOH specications, you must set the current strength settings accordingly. For example, to meet the 3.3-V LVTTL specication (4
mA), you should set the current strength settings to 4 mA. Setting at lower current strength may not meet the IOL and IOH specications in the
datasheet.
CV-51002
2016.12.09 Single-Ended I/O Standards 17
Cyclone V Device Datasheet Altera Corporation
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Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specications
Table 15: Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specications for Cyclone V Devices
I/O Standard
VCCIO (V) VREF (V) VTT (V)
Min Typ Max Min Typ Max Min Typ Max
SSTL-2
Class I, II
2.375 2.5 2.625 0.49 × VCCIO 0.5 × VCCIO 0.51 × VCCIO VREF – 0.04 VREF VREF + 0.04
SSTL-18
Class I, II
1.71 1.8 1.89 0.833 0.9 0.969 VREF – 0.04 VREF VREF + 0.04
SSTL-15
Class I, II
1.425 1.5 1.575 0.49 × VCCIO 0.5 × VCCIO 0.51 × VCCIO 0.49 × VCCIO 0.5 × VCCIO 0.51 × VCCIO
SSTL-135
Class I, II
1.283 1.35 1.418 0.49 × VCCIO 0.5 × VCCIO 0.51 × VCCIO 0.49 × VCCIO 0.5 × VCCIO 0.51 × VCCIO
SSTL-125
Class I, II
1.19 1.25 1.26 0.49 × VCCIO 0.5 × VCCIO 0.51 × VCCIO 0.49 × VCCIO 0.5 × VCCIO 0.51 × VCCIO
HSTL-18
Class I, II
1.71 1.8 1.89 0.85 0.9 0.95 — VCCIO/2 —
HSTL-15
Class I, II
1.425 1.5 1.575 0.68 0.75 0.9 — VCCIO/2 —
HSTL-12
Class I, II
1.14 1.2 1.26 0.47 × VCCIO 0.5 × VCCIO 0.53 × VCCIO — VCCIO/2 —
HSUL-12 1.14 1.2 1.3 0.49 × VCCIO 0.5 × VCCIO 0.51 × VCCIO — — —
18 Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specications CV-51002
2016.12.09
Altera Corporation Cyclone V Device Datasheet
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Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specications
Table 16: Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specications for Cyclone V Devices
I/O Standard
VIL(DC) (V) VIH(DC) (V) VIL(AC) (V) VIH(AC) (V) VOL (V) VOH (V) IOL(19)
(mA) IOH(19) (mA)
Min Max Min Max Max Min Max Min
SSTL-2
Class I
–0.3 VREF – 0.15 VREF + 0.15 VCCIO + 0.3 VREF – 0.31 VREF + 0.31 VTT – 0.608 VTT + 0.608 8.1 –8.1
SSTL-2
Class II
–0.3 VREF – 0.15 VREF + 0.15 VCCIO + 0.3 VREF – 0.31 VREF + 0.31 VTT – 0.81 VTT + 0.81 16.2 –16.2
SSTL-18
Class I
–0.3 VREF – 0.125 VREF + 0.125 VCCIO + 0.3 VREF – 0.25 VREF + 0.25 VTT – 0.603 VTT + 0.603 6.7 –6.7
SSTL-18
Class II
–0.3 VREF – 0.125 VREF + 0.125 VCCIO + 0.3 VREF – 0.25 VREF + 0.25 0.28 VCCIO – 0.28 13.4 –13.4
SSTL-15
Class I
— VREF – 0.1 VREF + 0.1 — VREF – 0.175 VREF + 0.175 0.2 × VCCIO 0.8 × VCCIO 8 –8
SSTL-15
Class II
— VREF – 0.1 VREF + 0.1 — VREF – 0.175 VREF + 0.175 0.2 × VCCIO 0.8 × VCCIO 16 –16
SSTL-135 — VREF – 0.09 VREF + 0.09 — VREF – 0.16 VREF + 0.16 0.2 × VCCIO 0.8 × VCCIO — —
SSTL-125 — VREF – 0.85 VREF + 0.85 — VREF – 0.15 VREF + 0.15 0.2 × VCCIO 0.8 × VCCIO — —
HSTL-18
Class I
— VREF – 0.1 VREF + 0.1 — VREF – 0.2 VREF + 0.2 0.4 VCCIO – 0.4 8 –8
HSTL-18
Class II
— VREF – 0.1 VREF + 0.1 — VREF – 0.2 VREF + 0.2 0.4 VCCIO – 0.4 16 –16
HSTL-15
Class I
— VREF – 0.1 VREF + 0.1 — VREF – 0.2 VREF + 0.2 0.4 VCCIO – 0.4 8 –8
(19) To meet the IOL and IOH specications, you must set the current strength settings accordingly. For example, to meet the SSTL15CI specication (8
mA), you should set the current strength settings to 8 mA. Setting at lower current strength may not meet the IOL and IOH specications in the
datasheet.
CV-51002
2016.12.09 Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specications 19
Cyclone V Device Datasheet Altera Corporation
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I/O Standard
VIL(DC) (V) VIH(DC) (V) VIL(AC) (V) VIH(AC) (V) VOL (V) VOH (V) IOL(19)
(mA) IOH(19) (mA)
Min Max Min Max Max Min Max Min
HSTL-15
Class II
— VREF – 0.1 VREF + 0.1 — VREF – 0.2 VREF + 0.2 0.4 VCCIO – 0.4 16 –16
HSTL-12
Class I
–0.15 VREF – 0.08 VREF + 0.08 VCCIO + 0.15 VREF – 0.15 VREF + 0.15 0.25 × VCCIO 0.75 × VCCIO 8 –8
HSTL-12
Class II
–0.15 VREF – 0.08 VREF + 0.08 VCCIO+ 0.15 VREF – 0.15 VREF + 0.15 0.25 × VCCIO 0.75 × VCCIO 16 –16
HSUL-12 — VREF – 0.13 VREF + 0.13 — VREF – 0.22 VREF + 0.22 0.1 × VCCIO 0.9 × VCCIO — —
Dierential SSTL I/O Standards
Table 17: Dierential SSTL I/O Standards for Cyclone V Devices
I/O Standard
VCCIO (V) VSWING(DC) (V) VX(AC) (V) VSWING(AC) (V)
Min Typ Max Min Max Min Typ Max Min Max
SSTL-2
Class I, II
2.375 2.5 2.625 0.3 VCCIO + 0.6 VCCIO/2 – 0.2 — VCCIO/2
+ 0.2
0.62 VCCIO + 0.6
SSTL-18
Class I, II
1.71 1.8 1.89 0.25 VCCIO + 0.6 VCCIO/2 –
0.175
— VCCIO/2
+ 0.175
0.5 VCCIO + 0.6
SSTL-15
Class I, II
1.425 1.5 1.575 0.2 (20) VCCIO/2 –
0.15
— VCCIO/2
+ 0.15
2(VIH(AC) –
VREF)
2(VIL(AC) – VREF)
SSTL-135 1.283 1.35 1.45 0.18 (20) VCCIO/2 –
0.15
VCCIO/2 VCCIO/2
+ 0.15
2(VIH(AC) –
VREF)
2(VIL(AC) – VREF)
(19) To meet the IOL and IOH specications, you must set the current strength settings accordingly. For example, to meet the SSTL15CI specication (8
mA), you should set the current strength settings to 8 mA. Setting at lower current strength may not meet the IOL and IOH specications in the
datasheet.
(20) e maximum value for VSWING(DC) is not dened. However, each single-ended signal needs to be within the respective single-ended limits (VIH(DC)
and VIL(DC)).
20 Dierential SSTL I/O Standards CV-51002
2016.12.09
Altera Corporation Cyclone V Device Datasheet
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I/O Standard
VCCIO (V) VSWING(DC) (V) VX(AC) (V) VSWING(AC) (V)
Min Typ Max Min Max Min Typ Max Min Max
SSTL-125 1.19 1.25 1.31 0.18 (20) VCCIO/2 –
0.15
VCCIO/2 VCCIO/2
+ 0.15
2(VIH(AC) –
VREF)
2(VIL(AC) – VREF)
Dierential HSTL and HSUL I/O Standards
Table 18: Dierential HSTL and HSUL I/O Standards for Cyclone V Devices
I/O Standard
VCCIO (V) VDIF(DC) (V) VX(AC) (V) VCM(DC) (V) VDIF(AC) (V)
Min Typ Max Min Max Min Typ Max Min Typ Max Min Max
HSTL-18
Class I, II
1.71 1.8 1.89 0.2 — 0.78 — 1.12 0.78 — 1.12 0.4 —
HSTL-15
Class I, II
1.425 1.5 1.575 0.2 — 0.68 — 0.9 0.68 — 0.9 0.4 —
HSTL-12
Class I, II
1.14 1.2 1.26 0.16 VCCIO
+ 0.3
— 0.5 ×
VCCIO
— 0.4 ×
VCCIO
0.5 ×
VCCIO
0.6 ×
VCCIO
0.3 VCCIO + 0.48
HSUL-12 1.14 1.2 1.3 0.26 0.26 0.5 ×
VCCIO –
0.12
0.5 ×
VCCIO
0.5 ×
VCCIO
+ 0.12
0.4 ×
VCCIO
0.5 ×
VCCIO
0.6 ×
VCCIO
0.44 0.44
Dierential I/O Standard Specications
Table 19: Dierential I/O Standard Specications for Cyclone V Devices
Dierential inputs are powered by VCCPD which requires 2.5 V.
CV-51002
2016.12.09 Dierential HSTL and HSUL I/O Standards 21
Cyclone V Device Datasheet Altera Corporation
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I/O Standard
VCCIO (V) VID (mV)(21) VICM(DC) (V) VOD (V)(22) VOCM (V)(22)(23)
Min Typ Max Min Condition Max Min Condition Max Min Typ Max Min Typ Max
PCML Transmitter, receiver, and input reference clock pins of high-speed transceivers use the PCML I/O standard. For transmitter, receiver, and
reference clock I/O pin specications, refer to Transceiver Specications for Cyclone V GX, GT, SX, and ST Devices table.
2.5 V
LVDS(24) 2.375 2.5 2.625 100 VCM =
1.25 V —
0.05 DMAX ≤
700 Mbps
1.80
0.247 — 0.6 1.125 1.25 1.375
1.05 DMAX >
700 Mbps
1.55
BLVDS(25)
(26)
2.375 2.5 2.625 100 — — — — — — — — — — —
RSDS
(HIO)(27)
2.375 2.5 2.625 100 VCM =
1.25 V
— 0.25 — 1.45 0.1 0.2 0.6 0.5 1.2 1.4
Mini-LVDS
(HIO)(28)
2.375 2.5 2.625 200 — 600 0.300 — 1.425 0.25 — 0.6 1 1.2 1.4
LVPECL(29) — — — 300 — —
0.60 DMAX ≤
700 Mbps
1.80
————— —
1.00 DMAX >
700 Mbps
1.60
(21) e minimum VID value is applicable over the entire common mode range, VCM.
(22) RL range: 90 ≤ RL ≤ 110 Ω.
(23) is applies to default pre-emphasis setting only.
(24) For optimized LVDS receiver performance, the receiver voltage input range must be within 1.0 V to 1.6 V for data rate above 700 Mbps and 0.00 V to
1.85 V for data rate below 700 Mbps.
(25) ere are no xed VICM, VOD, and VOCM specications for BLVDS. ey depend on the system topology.
(26) For more information about BLVDS interface support in Altera devices, refer to AN522: Implementing Bus LVDS Interface in Supported Altera
Device Families.
(27) For optimized RSDS receiver performance, the receiver voltage input range must be within 0.25 V to 1.45 V.
(28) For optimized mini-LVDS receiver performance, the receiver voltage input range must be within 0.300 V to 1.425 V.
(29) For optimized LVPECL receiver performance, the receiver voltage input range must be within 0.85 V to 1.75 V for data rate above 700 Mbps and 0.45
V to 1.95 V for data rate below 700 Mbps.
22 Dierential I/O Standard Specications CV-51002
2016.12.09
Altera Corporation Cyclone V Device Datasheet
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I/O Standard
VCCIO (V) VID (mV)(21) VICM(DC) (V) VOD (V)(22) VOCM (V)(22)(23)
Min Typ Max Min Condition Max Min Condition Max Min Typ Max Min Typ Max
SLVS 2.375 2.5 2.625 100 VCM =
1.25 V
— 0.05 — 1.80 — — — — — —
Sub-LVDS 2.375 2.5 2.625 100 VCM =
1.25 V
— 0.05 — 1.80 — — — — — —
HiSpi 2.375 2.5 2.625 100 VCM =
1.25 V
— 0.05 — 1.80 — — — — — —
Related Information
•AN522: Implementing Bus LVDS Interface in Supported Altera Device Families
Provides more information about BLVDS interface support in Altera devices.
•Transceiver Specications for Cyclone V GX, GT, SX, and ST Devices on page 24
Provides the specications for transmitter, receiver, and reference clock I/O pin.
Switching Characteristics
is section provides performance characteristics of Cyclone V core and periphery blocks.
(21) e minimum VID value is applicable over the entire common mode range, VCM.
(22) RL range: 90 ≤ RL ≤ 110 Ω.
(23) is applies to default pre-emphasis setting only.
CV-51002
2016.12.09 Switching Characteristics 23
Cyclone V Device Datasheet Altera Corporation
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Transceiver Performance Specications
Transceiver Specications for Cyclone V GX, GT, SX, and ST Devices
Table 20: Reference Clock Specications for Cyclone V GX, GT, SX, and ST Devices
Symbol/Description Condition
Transceiver Speed Grade 5(30) Transceiver Speed Grade 6 Transceiver Speed Grade 7
Unit
Min Typ Max Min Typ Max Min Typ Max
Supported I/O
standards
1.2 V PCML, 1.5 V PCML, 2.5 V PCML, Dierential LVPECL(31), HCSL, and LVDS
Input frequency
from REFCLK input
pins(32)
— 27 — 550 27 — 550 27 — 550 MHz
Rise time Measure at ±60
mV of dierential
signal(33)
— — 400 — — 400 — — 400 ps
Fall time Measure at ±60
mV of dierential
signal(33)
— — 400 — — 400 — — 400 ps
Duty cycle — 45 — 55 45 — 55 45 — 55 %
Peak-to-peak
dierential input
voltage
— 200 — 2000 200 — 2000 200 — 2000 mV
Spread-spectrum
modulating clock
frequency
PCIe 30 — 33 30 — 33 30 — 33 kHz
(30) Transceiver Speed Grade 5 covers specications for Cyclone V GT and ST devices.
(31) Dierential LVPECL signal levels must comply to the minimum and maximum peak-to-peak dierential input voltage specied in this table.
(32) e reference clock frequency must be ≥ 307.2 MHz to be fully compliance to CPRI transmit jitter specication at 6.144 Gbps. For more information
about CPRI 6.144 Gbps, refer to the Transceiver Protocol Congurations in Cyclone V Devices chapter.
(33) REFCLK performance requires to meet transmitter REFCLK phase noise specication.
24 Transceiver Performance Specications CV-51002
2016.12.09
Altera Corporation Cyclone V Device Datasheet
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Symbol/Description Condition
Transceiver Speed Grade 5(30) Transceiver Speed Grade 6 Transceiver Speed Grade 7
Unit
Min Typ Max Min Typ Max Min Typ Max
Spread-spectrum
downspread
PCIe — 0 to –
0.5%
— — 0 to –
0.5%
— — 0 to –
0.5%
— —
On-chip termination
resistors
— — 100 — — 100 — — 100 — Ω
VICM (AC coupled) — VCCE_GXBL supply(34)(35) VCCE_GXBL supply VCCE_GXBL supply V
VICM (DC coupled) HCSL I/O standard
for the PCIe
reference clock
250 — 550 250 — 550 250 — 550 mV
Transmitter REFCLK
phase noise(36)
10 Hz — — –50 — — –50 — — –50 dBc/Hz
100 Hz — — –80 — — –80 — — –80 dBc/Hz
1 KHz — — –110 — — –110 — — –110 dBc/Hz
10 KHz — — –120 — — –120 — — –120 dBc/Hz
100 KHz — — –120 — — –120 — — –120 dBc/Hz
≥1 MHz — — –130 — — –130 — — –130 dBc/Hz
RREF — — 2000
±1%
— — 2000
±1%
— — 2000
±1%
— Ω
(30) Transceiver Speed Grade 5 covers specications for Cyclone V GT and ST devices.
(34) Altera recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V to 1.2 V for Cyclone V GT and ST FPGA systems which
require full compliance to the PCIe Gen2 transmit jitter specication. For more information about the maximum full duplex channels recommended
in Cyclone V GT and ST devices under this condition, refer to the Transceiver Protocol Congurations in Cyclone V Devices chapter.
(35) Altera recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V to 1.2 V for full compliance to CPRI transmit jitter
specication at 4.9152 Gbps ( Cyclone V GT and ST devices) and 6.144 Gbps ( Cyclone V GT and ST devices only). For more information about the
maximum full duplex channels recommended in Cyclone V GT and ST devices for CPRI 6.144 Gbps, refer to the Transceiver Protocol Congurations
in Cyclone V Devices chapter.
(36) e transmitter REFCLK phase jitter is 30 ps p-p at bit error rate (BER) 10-12.
CV-51002
2016.12.09 Transceiver Specications for Cyclone V GX, GT, SX, and ST Devices 25
Cyclone V Device Datasheet Altera Corporation
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Table 21: Transceiver Clocks Specications for Cyclone V GX, GT, SX, and ST Devices
Symbol/Description Condition
Transceiver Speed Grade 5(30) Transceiver Speed Grade 6 Transceiver Speed Grade 7
Unit
Min Typ Max Min Typ Max Min Typ Max
fixedclk clock
frequency
PCIe Receiver
Detect
— 125 — — 125 — — 125 — MHz
Transceiver Recon‐
guration Controller
IP (mgmt_clk_clk)
clock frequency
— 75 — 100/
125(37)
75 — 100/
125(37)
75 — 100/
125(37)
MHz
Table 22: Receiver Specications for Cyclone V GX, GT, SX, and ST Devices
Symbol/Description Condition
Transceiver Speed Grade 5(30) Transceiver Speed Grade 6 Transceiver Speed Grade 7
Unit
Min Typ Max Min Typ Max Min Typ Max
Supported I/O
standards
1.5 V PCML, 2.5 V PCML, LVPECL, and LVDS
Data rate(38) — 614 — 5000/
6144(35)
614 — 3125 614 — 2500 Mbps
Absolute VMAX for a
receiver pin(39)
— — — 1.2 — — 1.2 — — 1.2 V
Absolute VMIN for a
receiver pin
— –0.4 — — –0.4 — — –0.4 — — V
Maximum peak-to-
peak dierential
input voltage VID
(di p-p) before
device conguration
— — — 1.6 — — 1.6 — — 1.6 V
(37) e maximum supported clock frequency is 100 MHz if the PCIe hard IP block is enabled or 125 MHz if the PCIe hard IP block is not enabled.
(38) To support data rates lower than the minimum specication through oversampling, use the CDR in LTR mode only.
(39) e device cannot tolerate prolonged operation at this absolute maximum.
26 Transceiver Specications for Cyclone V GX, GT, SX, and ST Devices CV-51002
2016.12.09
Altera Corporation Cyclone V Device Datasheet
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Symbol/Description Condition
Transceiver Speed Grade 5(30) Transceiver Speed Grade 6 Transceiver Speed Grade 7
Unit
Min Typ Max Min Typ Max Min Typ Max
Maximum peak-to-
peak dierential
input voltage VID
(di p-p) aer
device conguration
— — — 2.2 — — 2.2 — — 2.2 V
Minimum dieren‐
tial eye opening at
the receiver serial
input pins(40)
— 110 — — 110 — — 110 — — mV
Dierential on-chip
termination resistors
85-Ω setting — 85 — — 85 — — 85 — Ω
100-Ω setting — 100 — — 100 — — 100 — Ω
120-Ω setting — 120 — — 120 — — 120 — Ω
150-Ω setting — 150 — — 150 — — 150 — Ω
VICM (AC coupled)
2.5 V PCML,
LVPECL, and
LVDS
VCCE_GXBL supply(34)(35) VCCE_GXBL supply VCCE_GXBL supply V
1.5 V PCML 0.65/0.75/0.8 (41) V
tLTR(42) — — — 10 — — 10 — — 10 µs
tLTD(43) — — — 4 — — 4 — — 4 µs
(40) e dierential eye opening specication at the receiver input pins assumes that you have disabled the Receiver Equalization feature. If you enable the
Receiver Equalization feature, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.
(41) e AC coupled VICM = 650 mV for Cyclone V GX and SX in PCIe mode only. e AC coupled VICM = 750mV for Cyclone V GT and ST in PCIe
mode only.
(42) tLTR is the time required for the receive clock data recovery (CDR) to lock to the input reference clock frequency aer coming out of reset.
(43) tLTD is time required for the receiver CDR to start recovering valid data aer the rx_is_lockedtodata signal goes high.
CV-51002
2016.12.09 Transceiver Specications for Cyclone V GX, GT, SX, and ST Devices 27
Cyclone V Device Datasheet Altera Corporation
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Symbol/Description Condition
Transceiver Speed Grade 5(30) Transceiver Speed Grade 6 Transceiver Speed Grade 7
Unit
Min Typ Max Min Typ Max Min Typ Max
tLTD_manual(44) — — — 4 — — 4 — — 4 µs
tLTR_LTD_manual(45) — 15 — — 15 — — 15 — — µs
Programmable ppm
detector(46)
— ±62.5, 100, 125, 200, 250, 300, 500, and 1000 ppm
Run length — — — 200 — — 200 — — 200 UI
Programmable
equalization AC and
DC gain
AC gain setting = 0
to 3 (47)
DC gain setting =
0 to 1
Refer to CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC
Gain for Cyclone V GX, GT, SX, and ST Devices and CTLE Response at Data Rates ≤ 3.25
Gbps across Supported AC Gain and DC Gain for Cyclone V GX, GT, SX, and ST Devices
diagrams.
dB
Table 23: Transmitter Specications for Cyclone V GX, GT, SX, and ST Devices
Symbol/Description Condition
Transceiver Speed Grade 5(30) Transceiver Speed Grade 6 Transceiver Speed Grade 7
Unit
Min Typ Max Min Typ Max Min Typ Max
Supported I/O
standards
1.5 V PCML
Data rate — 614 — 5000/
6144(35)
614 — 3125 614 — 2500 Mbps
VOCM (AC coupled) — — 650 — — 650 — — 650 — mV
(44) tLTD_manual is the time required for the receiver CDR to start recovering valid data aer the rx_is_lockedtodata signal goes high when the CDR is
functioning in the manual mode.
(45) tLTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode aer the rx_is_lockedtoref signal goes high when the
CDR is functioning in the manual mode.
(46) e rate matcher supports only up to ±300 parts per million (ppm).
(47) e Quartus Prime soware allows AC gain setting = 3 for design with data rate between 614 Mbps and 1.25 Gbps only.
28 Transceiver Specications for Cyclone V GX, GT, SX, and ST Devices CV-51002
2016.12.09
Altera Corporation Cyclone V Device Datasheet
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Symbol/Description Condition
Transceiver Speed Grade 5(30) Transceiver Speed Grade 6 Transceiver Speed Grade 7
Unit
Min Typ Max Min Typ Max Min Typ Max
Dierential on-chip
termination resistors
85-Ω setting — 85 — — 85 — — 85 — Ω
100-Ω setting — 100 — — 100 — — 100 — Ω
120-Ω setting — 120 — — 120 — — 120 — Ω
150-Ω setting — 150 — — 150 — — 150 — Ω
Intra-dierential
pair skew
TX VCM = 0.65 V
and slew rate of 15
ps
— — 15 — — 15 — — 15 ps
Intra-transceiver
block transmitter
channel-to-channel
skew
×6 PMA bonded
mode
— — 180 — — 180 — — 180 ps
Inter-transceiver
block transmitter
channel-to-channel
skew
×N PMA bonded
mode
— — 500 — — 500 — — 500 ps
Table 24: CMU PLL Specications for Cyclone V GX, GT, SX, and ST Devices
Symbol/Description Condition
Transceiver Speed Grade 5(30) Transceiver Speed Grade 6 Transceiver Speed Grade 7
Unit
Min Typ Max Min Typ Max Min Typ Max
Supported data
range
— 614 — 5000/
6144(35)
614 — 3125 614 — 2500 Mbps
fPLL supported data
range
— 614 — 3125 614 — 3125 614 — 2500 Mbps
CV-51002
2016.12.09 Transceiver Specications for Cyclone V GX, GT, SX, and ST Devices 29
Cyclone V Device Datasheet Altera Corporation
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Table 25: Transceiver-FPGA Fabric Interface Specications for Cyclone V GX, GT, SX, and ST Devices
Symbol/Description Condition
Transceiver Speed Grade 5(30) Transceiver Speed Grade 6 Transceiver Speed Grade 7
Unit
Min Typ Max Min Typ Max Min Typ Max
Interface speed
(single-width mode)
— 25 — 187.5 25 — 187.5 25 — 163.84 MHz
Interface speed
(double-width
mode)
— 25 — 163.84 25 — 163.84 25 — 156.25 MHz
Related Information
•CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain on page 31
•CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain on page 32
•PCIe Supported Congurations and Placement Guidelines
Provides more information about the maximum full duplex channels recommended in Cyclone V GT and ST devices which require full
compliance to the PCIe Gen2 transmit jitter specication.
•6.144-Gbps Support Capability in Cyclone V GT Devices
Provides more information about the maximum full duplex channels recommended in Cyclone V GT and ST devices for CPRI 6.144 Gbps.
30 Transceiver Specications for Cyclone V GX, GT, SX, and ST Devices CV-51002
2016.12.09
Altera Corporation Cyclone V Device Datasheet
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CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain
Figure 2: Continuous Time-Linear Equalizer (CTLE) Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain for Cyclone V GX,
GT, SX, and ST Devices
CV-51002
2016.12.09 CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain 31
Cyclone V Device Datasheet Altera Corporation
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CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain
Figure 3: CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain for Cyclone V GX, GT, SX, and ST Devices
32 CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain CV-51002
2016.12.09
Altera Corporation Cyclone V Device Datasheet
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Typical TX VOD Setting for Cyclone V Transceiver Channels with termination of 100 Ω
Table 26: Typical TX VOD Setting for Cyclone V Transceiver Channels with termination of 100 Ω
Symbol VOD Setting(48) VOD Value (mV) VOD Setting(48) VOD Value (mV)
VOD dierential peak-to-peak
typical
6(49) 120 34 680
7(49) 140 35 700
8(49) 160 36 720
9 180 37 740
10 200 38 760
11 220 39 780
12 240 40 800
13 260 41 820
14 280 42 840
15 300 43 860
16 320 44 880
17 340 45 900
18 360 46 920
19 380 47 940
20 400 48 960
21 420 49 980
22 440 50 1000
23 460 51 1020
24 480 52 1040
(48) Convert these values to their binary equivalent form if you are using the dynamic reconguration mode for PMA analog controls.
(49) Only valid for data rates ≤ 5 Gbps.
CV-51002
2016.12.09 Typical TX VOD Setting for Cyclone V Transceiver Channels with termination of 100 Ω 33
Cyclone V Device Datasheet Altera Corporation
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Symbol VOD Setting(48) VOD Value (mV) VOD Setting(48) VOD Value (mV)
25 500 53 1060
26 520 54 1080
27 540 55 1100
28 560 56 1120
29 580 57 1140
30 600 58 1160
31 620 59 1180
32 640 60 1200
33 660
Transmitter Pre-Emphasis Levels
e following table lists the simulation data on the transmitter pre-emphasis levels in dB for the rst post tap under the following conditions:
• Low-frequency data pattern—ve 1s and ve 0s
• Data rate—2.5 Gbps
e levels listed are a representation of possible pre-emphasis levels under the specied conditions only and the pre-emphasis levels may change
with data pattern and data rate.
Cyclone V devices only support 1st post tap pre-emphasis with the following conditions:
•e 1st post tap pre-emphasis settings must satisfy |B| + |C| ≤ 60 where |B| = VOD setting with termination value, RTERM = 100 Ω and |C| = 1st
post tap pre-emphasis setting.
• |B| – |C| > 5 for data rates < 5 Gbps and |B| – |C| > 8.25 for data rates > 5 Gbps.
• (VMAX/VMIN – 1)% < 600%, where VMAX = |B| + |C| and VMIN = |B| – |C|.
(48) Convert these values to their binary equivalent form if you are using the dynamic reconguration mode for PMA analog controls.
34 Transmitter Pre-Emphasis Levels CV-51002
2016.12.09
Altera Corporation Cyclone V Device Datasheet
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Exception for PCIe Gen2 design:
• VOD setting = 50 and pre-emphasis setting = 22 are allowed for PCIe Gen2 design with transmit de-emphasis –6dB setting (pipe_txdeemp =
1’b0) using Altera PCIe Hard IP and PIPE IP cores.
• VOD setting = 50 and pre-emphasis setting = 12 are allowed for PCIe Gen2 design with transmit de-emphasis –3.5dB setting (pipe_txdeemp =
1’b1) using Altera PCIe Hard IP and PIPE IP cores.
For example, when VOD = 800 mV, the corresponding VOD value setting is 40. e following conditions show that the 1st post tap pre-emphasis
setting = 2 is valid:
• |B| + |C| ≤ 60→ 40 + 2 = 42
• |B| – |C| > 5→ 40 – 2 = 38
• (VMAX/VMIN – 1)% < 600%→ (42/38 – 1)% = 10.52%
To predict the pre-emphasis level for your specic data rate and pattern, run simulations using the Cyclone V HSSI HSPICE models.
Table 27: Transmitter Pre-Emphasis Levels for Cyclone V Devices
Quartus Prime 1st
Post Tap Pre-
Emphasis Setting
Quartus Prime VOD Setting
Unit
10 (200 mV) 20 (400 mV) 30 (600 mV) 35 (700 mV) 40 (800 mV) 45 (900 mV) 50 (1000 mV)
0 0 0 0 0 0 0 0 dB
1 1.97 0.88 0.43 0.32 0.24 0.19 0.13 dB
2 3.58 1.67 0.95 0.76 0.61 0.5 0.41 dB
3 5.35 2.48 1.49 1.2 1 0.83 0.69 dB
4 7.27 3.31 2 1.63 1.36 1.14 0.96 dB
5 — 4.19 2.55 2.1 1.76 1.49 1.26 dB
6 — 5.08 3.11 2.56 2.17 1.83 1.56 dB
7 — 5.99 3.71 3.06 2.58 2.18 1.87 dB
8 — 6.92 4.22 3.47 2.93 2.48 2.11 dB
9 — 7.92 4.86 4 3.38 2.87 2.46 dB
10 — 9.04 5.46 4.51 3.79 3.23 2.77 dB
11 — 10.2 6.09 5.01 4.23 3.61 — dB
CV-51002
2016.12.09 Transmitter Pre-Emphasis Levels 35
Cyclone V Device Datasheet Altera Corporation
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Quartus Prime 1st
Post Tap Pre-
Emphasis Setting
Quartus Prime VOD Setting
Unit
10 (200 mV) 20 (400 mV) 30 (600 mV) 35 (700 mV) 40 (800 mV) 45 (900 mV) 50 (1000 mV)
12 — 11.56 6.74 5.51 4.68 3.97 — dB
13 — 12.9 7.44 6.1 5.12 4.36 — dB
14 — 14.44 8.12 6.64 5.57 4.76 — dB
15 — — 8.87 7.21 6.06 5.14 — dB
16 — — 9.56 7.73 6.49 — — dB
17 — — 10.43 8.39 7.02 — — dB
18 — — 11.23 9.03 7.52 — — dB
19 — — 12.18 9.7 8.02 — — dB
20 — — 13.17 10.34 8.59 — — dB
21 — — 14.2 11.1 — — — dB
22 — — 15.38 11.87 — — — dB
23 — — — 12.67 — — — dB
24 — — — 13.48 — — — dB
25 — — — 14.37 — — — dB
26 — — — — — — — dB
27 — — — — — — — dB
28 — — — — — — — dB
29 — — — — — — — dB
30 — — — — — — — dB
31 — — — — — — — dB
36 Transmitter Pre-Emphasis Levels CV-51002
2016.12.09
Altera Corporation Cyclone V Device Datasheet
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Related Information
SPICE Models for Altera Devices
Provides the Cyclone V HSSI HSPICE models.
Transceiver Compliance Specication
e following table lists the physical medium attachment (PMA) specication compliance of all supported protocol for Cyclone V GX, GT, SX, and
ST devices. For more information about the protocol parameter details and compliance specications, contact your Altera Sales Representative.
Table 28: Transceiver Compliance Specication for All Supported Protocol for Cyclone V GX, GT, SX, and ST Devices
Protocol Sub-protocol Data Rate (Mbps)
PCIe
PCIe Gen1 2,500
PCIe Gen2(50) 5,000
PCIe Cable 2,500
XAUI XAUI 2135 3,125
Serial RapidIO® (SRIO)
SRIO 1250 SR 1,250
SRIO 1250 LR 1,250
SRIO 2500 SR 2,500
SRIO 2500 LR 2,500
SRIO 3125 SR 3,125
SRIO 3125 LR 3,125
SRIO 5000 SR 5,000
SRIO 5000 MR 5,000
SRIO 5000 LR 5,000
(50) For PCIe Gen2 sub-protocol, Altera recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V to 1.2 V for Cyclone V GT and
ST FPGA systems which ensure full compliance to the PCIe Gen2 transmit jitter specication. For more information about the maximum full duplex
channels recommended in Cyclone V GT and ST devices under this condition, refer to the Transceiver Protocol Congurations in Cyclone V Devices
chapter.
CV-51002
2016.12.09 Transceiver Compliance Specication 37
Cyclone V Device Datasheet Altera Corporation
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Protocol Sub-protocol Data Rate (Mbps)
Common Public Radio Interface (CPRI)
CPRI E6LV 614.4
CPRI E6HV 614.4
CPRI E6LVII 614.4
CPRI E12LV 1,228.8
CPRI E12HV 1,228.8
CPRI E12LVII 1,228.8
CPRI E24LV 2,457.6
CPRI E24LVII 2,457.6
CPRI E30LV 3,072
CPRI E30LVII 3,072
CPRI E48LVII(51) 4,915.2
CPRI E60LVII(51) 6,144
Gbps Ethernet (GbE) GbE 1250 1,250
OBSAI
OBSAI 768 768
OBSAI 1536 1,536
OBSAI 3072 3,072
Serial digital interface (SDI)
SDI 270 SD 270
SDI 1485 HD 1,485
SDI 2970 3G 2,970
VbyOne VbyOne 3750 3,750
(51) For CPRI E48LVII and E60LVII, Altera recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V to 1.2 V for full compliance to
CPRI transmit jitter specication at 4.9152 Gbps ( Cyclone V GT and ST devices) and 6.144 Gbps ( Cyclone V GT and ST devices only). For more
information about the maximum full duplex channels recommended in Cyclone V GT and ST devices for CPRI 6.144 Gbps, refer to the Transceiver
Protocol Congurations in Cyclone V Devices chapter.
38 Transceiver Compliance Specication CV-51002
2016.12.09
Altera Corporation Cyclone V Device Datasheet
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Protocol Sub-protocol Data Rate (Mbps)
HiGig+ HIGIG 3750 3,750
Related Information
•PCIe Supported Congurations and Placement Guidelines
Provides more information about the maximum full duplex channels recommended in Cyclone V GT and ST devices which require full
compliance to the PCIe Gen2 transmit jitter specication.
•6.144-Gbps Support Capability in Cyclone V GT Devices
Provides more information about the maximum full duplex channels recommended in Cyclone V GT and ST devices for CPRI 6.144 Gbps.
Core Performance Specications
Clock Tree Specications
Table 29: Clock Tree Specications for Cyclone V Devices
Parameter
Performance
Unit
–C6 –C7, –I7 –C8, –A7
Global clock and Regional clock 550 550 460 MHz
Peripheral clock 155 155 155 MHz
PLL Specications
Table 30: PLL Specications for Cyclone V Devices
is table lists the Cyclone V PLL block specications. Cyclone V PLL block does not include HPS PLL.
CV-51002
2016.12.09 Core Performance Specications 39
Cyclone V Device Datasheet Altera Corporation
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Symbol Parameter Condition Min Typ Max Unit
fIN Input clock frequency
–C6 speed grade 5 — 670(52) MHz
–C7, –I7 speed
grades
5 — 622(52) MHz
–C8, –A7 speed
grades
5 — 500(52) MHz
fINPFD Integer input clock frequency to the
phase frequency detector (PFD)
— 5 — 325 MHz
fFINPFD Fractional input clock frequency to the
PFD
— 50 — 160 MHz
fVCO(53) PLL voltage-controlled oscillator
(VCO) operating range
–C6, –C7, –I7 speed
grades
600 — 1600 MHz
–C8, –A7 speed
grades
600 — 1300 MHz
tEINDUTY Input clock or external feedback clock
input duty cycle
— 40 — 60 %
fOUT Output frequency for internal global or
regional clock
–C6, –C7, –I7 speed
grades
— — 550(54) MHz
–C8, –A7 speed
grades
— — 460(54) MHz
fOUT_EXT Output frequency for external clock
output
–C6, –C7, –I7 speed
grades
— — 667(54) MHz
–C8, –A7 speed
grades
— — 533(54) MHz
(52) is specication is limited in the Quartus Prime soware by the I/O maximum frequency. e maximum I/O frequency is dierent for each I/O
standard.
(53) e VCO frequency reported by the Quartus Prime soware takes into consideration the VCO post-scale counter K value. erefore, if the counter K
has a value of 2, the frequency reported can be lower than the fVCO specication.
(54) is specication is limited by the lower of the two: I/O fMAX or FOUT of the PLL.
40 PLL Specications CV-51002
2016.12.09
Altera Corporation Cyclone V Device Datasheet
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Symbol Parameter Condition Min Typ Max Unit
tOUTDUTY Duty cycle for external clock output
(when set to 50%)
— 45 50 55 %
tFCOMP External feedback clock compensation
time
— — — 10 ns
tDYCONFIGCLK Dynamic conguration clock for mgmt_
clk and scanclk — — — 100 MHz
tLOCK Time required to lock from end-of-
device conguration or deassertion of
areset
— — — 1 ms
tDLOCK Time required to lock dynamically
(aer switchover or reconguring any
non-post-scale counters/delays)
— — — 1 ms
fCLBW PLL closed-loop bandwidth
Low — 0.3 — MHz
Medium — 1.5 — MHz
High(55) — 4 — MHz
tPLL_PSERR Accuracy of PLL phase shi — — — ±50 ps
tARESET Minimum pulse width on the areset
signal
— 10 — — ns
tINCCJ(56)(57) Input clock cycle-to-cycle jitter FREF ≥ 100 MHz — — 0.15 UI (p-p)
FREF < 100 MHz — — ±750 ps (p-p)
tOUTPJ_DC(58) Period jitter for dedicated clock output
in integer PLL
FOUT ≥ 100 MHz — — 300 ps (p-p)
FOUT < 100 MHz — — 30 mUI (p-p)
(55) High bandwidth PLL settings are not supported in external feedback mode.
(56) A high input jitter directly aects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter < 120 ps.
(57) FREF is fIN/N, specication applies when N = 1.
(58) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% condence level). e output jitter specication applies to the
intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. e external memory interface clock output jitter specications use a dierent
measurement method and are available in Memory Output Clock Jitter Specication for Cyclone V Devices table.
CV-51002
2016.12.09 PLL Specications 41
Cyclone V Device Datasheet Altera Corporation
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Symbol Parameter Condition Min Typ Max Unit
tFOUTPJ_DC(58) Period jitter for dedicated clock output
in fractional PLL
FOUT ≥ 100 MHz — — 425(61), 300(59) ps (p-p)
FOUT < 100 MHz — — 42.5(61), 30(59) mUI (p-p)
tOUTCCJ_DC(58) Cycle-to-cycle jitter for dedicated clock
output in integer PLL
FOUT ≥ 100 MHz — — 300 ps (p-p)
FOUT < 100 MHz — — 30 mUI (p-p)
tFOUTCCJ_DC(58) Cycle-to-cycle jitter for dedicated clock
output in fractional PLL
FOUT ≥ 100 MHz — — 425(61), 300(59) ps (p-p)
FOUT < 100 MHz — — 42.5(61), 30(59) mUI (p-p)
tOUTPJ_IO(58)(60) Period jitter for clock output on a
regular I/O in integer PLL
FOUT ≥ 100 MHz — — 650 ps (p-p)
FOUT < 100 MHz — — 65 mUI (p-p)
tFOUTPJ_IO(58)(60)(61) Period jitter for clock output on a
regular I/O in fractional PLL
FOUT ≥ 100 MHz — — 650 ps (p-p)
FOUT < 100 MHz — — 65 mUI (p-p)
tOUTCCJ_IO(58)(60) Cycle-to-cycle jitter for clock output on
regular I/O in integer PLL
FOUT ≥ 100 MHz — — 650 ps (p-p)
FOUT < 100 MHz — — 65 mUI (p-p)
tFOUTCCJ_IO(58)(60)(61) Cycle-to-cycle jitter for clock output on
regular I/O in fractional PLL
FOUT ≥ 100 MHz — — 650 ps (p-p)
FOUT < 100 MHz — — 65 mUI (p-p)
tCASC_OUTPJ_DC(58)(62) Period jitter for dedicated clock output
in cascaded PLLs
FOUT ≥ 100 MHz — — 300 ps (p-p)
FOUT < 100 MHz — — 30 mUI (p-p)
tDRIFT Frequency dri aer PFDENA is disabled
for a duration of 100 µs
— — — ±10 %
(59) is specication only covers fractional PLL for low bandwidth. e fVCO for fractional value range 0.20–0.80 must be ≥ 1200 MHz.
(60) External memory interface clock output jitter specications use a dierent measurement method, which are available in Memory Output Clock Jitter
Specication for Cyclone V Devices table.
(61) is specication only covers fractional PLL for low bandwidth. e fVCO for fractional value range 0.05–0.95 must be ≥ 1000 MHz.
(62) e cascaded PLL specication is only applicable with the following conditions:
• Upstream PLL: 0.59 MHz ≤ Upstream PLL BW < 1 MHz
• Downstream PLL: Downstream PLL BW > 2 MHz
42 PLL Specications CV-51002
2016.12.09
Altera Corporation Cyclone V Device Datasheet
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Symbol Parameter Condition Min Typ Max Unit
dKBIT Bit number of Delta Sigma Modulator
(DSM)
— 8 24 32 Bits
kVALUE Numerator of fraction — 128 8388608 2147483648 —
fRES Resolution of VCO frequency fINPFD = 100 MHz 390625 5.96 0.023 Hz
Related Information
Memory Output Clock Jitter Specications on page 49
Provides more information about the external memory interface clock output jitter specications.
DSP Block Performance Specications
Table 31: DSP Block Performance Specications for Cyclone V Devices
Mode
Performance
Unit
–C6 –C7, –I7 –C8, –A7
Modes using One DSP
Block
Independent 9 × 9 multiplication 340 300 260 MHz
Independent 18 × 19 multiplication 287 250 200 MHz
Independent 18 × 18 multiplication 287 250 200 MHz
Independent 27 × 27 multiplication 250 200 160 MHz
Independent 18 × 25 multiplication 310 250 200 MHz
Independent 20 × 24 multiplication 310 250 200 MHz
Two 18 × 19 multiplier adder mode 310 250 200 MHz
18 × 18 multiplier added summed with 36-
bit input
310 250 200 MHz
Modes using Two
DSP Blocks
Complex 18 × 19 multiplication 310 250 200 MHz
CV-51002
2016.12.09 DSP Block Performance Specications 43
Cyclone V Device Datasheet Altera Corporation
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Memory Block Performance Specications
To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL
and set to 50% output duty cycle. Use the Quartus Prime soware to report timing for the memory block clocking schemes.
When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in fMAX.
Table 32: Memory Block Performance Specications for Cyclone V Devices
Memory Mode
Resources Used Performance
Unit
ALUTs Memory –C6 –C7, –I7 –C8, –A7
MLAB
Single port, all supported widths 0 1 420 350 300 MHz
Simple dual-port, all supported widths 0 1 420 350 300 MHz
Simple dual-port with read and write at
the same address
0 1 340 290 240 MHz
ROM, all supported width 0 1 420 350 300 MHz
M10K
Block
Single-port, all supported widths 0 1 315 275 240 MHz
Simple dual-port, all supported widths 0 1 315 275 240 MHz
Simple dual-port with the read-during-
write option set to Old Data, all supported
widths
0 1 275 240 180 MHz
True dual port, all supported widths 0 1 315 275 240 MHz
ROM, all supported widths 0 1 315 275 240 MHz
Periphery Performance
is section describes the periphery performance, high-speed I/O, and external memory interface.
Actual achievable frequency depends on design and system specic factors. Ensure proper timing closure in your design and perform HSPICE/IBIS
simulations based on your specic design and system setup to determine the maximum achievable frequency in your system.
44 Memory Block Performance Specications CV-51002
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Altera Corporation Cyclone V Device Datasheet
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High-Speed I/O Specications
Table 33: High-Speed I/O Specications for Cyclone V Devices
When J = 1 or 2, bypass the serializer/deserializer (SERDES) block.
For LVDS applications, you must use the PLLs in integer PLL mode. is is achieved by using the LVDS clock network.
e Cyclone V devices support the following output standards using true LVDS output buer types on all I/O banks.
• True RSDS output standard with data rates of up to 360 Mbps
• True mini-LVDS output standard with data rates of up to 400 Mbps
Symbol Condition
–C6 –C7, –I7 –C8, –A7
Unit
Min Typ Max Min Typ Max Min Typ Max
fHSCLK_in (input clock frequency) True
Dierential I/O Standards
Clock boost
factor W = 1
to 40(63)
5 — 437.5 5 — 420 5 — 320 MHz
fHSCLK_in (input clock frequency) Single-
Ended I/O Standards
Clock boost
factor W = 1
to 40(63)
5 — 320 5 — 320 5 — 275 MHz
fHSCLK_OUT (output clock frequency) — 5 — 420 5 — 370 5 — 320 MHz
Transmitter True Dierential I/O
Standards - fHSDR (data rate)
SERDES factor
J =4 to 10(64)
(65) — 840 (65) — 740 (65) — 640 Mbps
(63) Clock boost factor (W) is the ratio between the input data rate and the input clock rate.
(64) e Fmax specication is based on the fast clock used for serial data. e interface Fmax is also dependent on the parallel clock domain which is design
dependent and requires timing analysis.
(65) e minimum specication depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional, or
local) that you use. e I/O dierential buer and input register do not have a minimum toggle rate.
CV-51002
2016.12.09 High-Speed I/O Specications 45
Cyclone V Device Datasheet Altera Corporation
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Symbol Condition
–C6 –C7, –I7 –C8, –A7
Unit
Min Typ Max Min Typ Max Min Typ Max
SERDES factor
J = 1 to 2, uses
DDR registers
(65) —(66) (65) —(66) (65) —(66) Mbps
Emulated Dierential I/O
Standards with ree
External Output Resistor
Networks- fHSDR (data rate)
(67)
SERDES factor
J = 4 to 10
(65) — 640 (65) — 640 (65) — 550 Mbps
Emulated Dierential I/O
Standards with One External
Output Resistor Network -
fHSDR (data rate)
SERDES factor
J = 4 to 10
(65) — 170 (65) — 170 (65) — 170 Mbps
tx Jitter -True Dierential I/O
Standards(67)
Total Jitterfor
Data Rate, 600
Mbps – 840
Mbps
— — 350 — — 380 — — 500 ps
Total Jitter for
Data Rate <
600Mbps
— — 0.21 — — 0.23 — — 0.30 UI
tx Jitter -Emulated
Dierential I/O
Standards with ree
External Output Resistor
Networks
Total Jitter for
Data Rate <
640Mbps
— — 500 — — 500 — — 500 ps
(66) e maximum ideal data rate is the SERDES factor (J) × PLL max output frequency (fout), provided you can close the design timing and the signal
integrity simulation is clean. You can estimate the achievable maximum data rate by performing link timing closure analysis. You must consider the
board skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported.
(67) You must calculate the leover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin,
transmitter channel-to-channel skew, and receiver sampling margin to determine the leover timing margin.
46 High-Speed I/O Specications CV-51002
2016.12.09
Altera Corporation Cyclone V Device Datasheet
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Symbol Condition
–C6 –C7, –I7 –C8, –A7
Unit
Min Typ Max Min Typ Max Min Typ Max
tx Jitter -Emulated
Dierential I/O
Standards with One
External Output Resistor
Network
Total Jitter for
Data Rate <
640Mbps
— — 0.15 — — 0.15 — — 0.15 UI
tDUTY TX output
clock duty
cycle for both
True and
Emulated
Dierential I/
O Standards
45 50 55 45 50 55 45 50 55 %
tRISE and tFALL
True
Dierential I/
O Standards
— — 200 — — 200 — — 200 ps
Emulated
Dierential I/
O Standards
with ree
External
Output
Resistor
Networks
— — 250 — — 250 — — 300 ps
Emulated
Dierential I/
O Standards
with One
External
Output
Resistor
Network
— — 300 — — 300 — — 300 ps
CV-51002
2016.12.09 High-Speed I/O Specications 47
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Symbol Condition
–C6 –C7, –I7 –C8, –A7
Unit
Min Typ Max Min Typ Max Min Typ Max
TCCS
True
Dierential I/
O Standards
— — 200 — — 250 — — 250 ps
Emulated
Dierential I/
O Standards
with ree
External
Output
Resistor
Networks
— — 300 — — 300 — — 300 ps
Emulated
Dierential I/
O Standards
with One
External
Output
Resistor
Network
— — 300 — — 300 — — 300 ps
Receiver fHSDR (data rate)
SERDES factor
J =4 to 10(64)
(65) — 875(67) (65) — 840(67) (65) — 640(67) Mbps
SERDES factor
J = 1 to 2, uses
DDR registers
(65) —(66) (65) —(66) (65) —(66) Mbps
Sampling Window — — — 350 — — 350 — — 350 ps
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DLL Frequency Range Specications
Table 34: DLL Frequency Range Specications for Cyclone V Devices
Parameter –C6 –C7, –I7 –C8 Unit
DLL operating frequency range 167 – 400 167 – 400 167 – 333 MHz
DQS Logic Block Specications
Table 35: DQS Phase Shift Error Specication for DLL-Delayed Clock (tDQS_PSERR) for Cyclone V Devices
is error specication is the absolute maximum and minimum error.
Number of DQS Delay Buer –C6 –C7, –I7 –C8 Unit
2 40 80 80 ps
Memory Output Clock Jitter Specications
Table 36: Memory Output Clock Jitter Specications for Cyclone V Devices
e memory output clock jitter measurements are for 200 consecutive clock cycles, as specied in the JEDEC DDR2/DDR3 SDRAM standard.
e memory output clock jitter is applicable when an input jitter of 30 ps (p-p) is applied with bit error rate (BER) 10–12, equivalent to 14 sigma.
Altera recommends using the UniPHY intellectual property (IP) with PHYCLK connections for better jitter performance.
Parameter Clock Network Symbol
–C6 –C7, –I7 –C8
Unit
Min Max Min Max Min Max
Clock period jitter PHYCLK tJIT(per) –60 60 –70 70 –70 70 ps
Cycle-to-cycle period jitter PHYCLK tJIT(cc) — 90 — 100 — 100 ps
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OCT Calibration Block Specications
Table 37: OCT Calibration Block Specications for Cyclone V Devices
Symbol Description Min Typ Max Unit
OCTUSRCLK Clock required by OCT calibration blocks — — 20 MHz
TOCTCAL Number of OCTUSRCLK clock cycles required for RS
OCT/RT OCT calibration
— 1000 — Cycles
TOCTSHIFT Number of OCTUSRCLK clock cycles required for OCT
code to shi out
— 32 — Cycles
TRS_RT Time required between the dyn_term_ctrl and oe
signal transitions in a bidirectional I/O buer to
dynamically switch between RS OCT and RT OCT
— 2.5 — ns
Figure 4: Timing Diagram for oe and dyn_term_ctrl Signals
TX RXRX
oe
dyn_term_ctrl
TRS_RT
TRS_RT
Tristate Tristate
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Duty Cycle Distortion (DCD) Specications
Table 38: Worst-Case DCD on Cyclone V I/O Pins
e output DCD cycle only applies to the I/O buer. It does not cover the system DCD.
Symbol
–C6 –C7, –I7 –C8, –A7
Unit
Min Max Min Max Min Max
Output Duty Cycle 45 55 45 55 45 55 %
HPS Specications
is section provides HPS specications and timing for Cyclone V devices.
For HPS reset, the minimum reset pulse widths for the HPS cold and warm reset signals (HPS_nRST and HPS_nPOR) are six clock cycles of
HPS_CLK1.
HPS Clock Performance
Table 39: HPS Clock Performance for Cyclone V Devices
Symbol/Description –C6 –C7, –I7 –A7 –C8 Unit
mpu_base_clk (microprocessor unit clock) 925 800 700 600 MHz
main_base_clk (L3/L4 interconnect clock) 400 400 350 300 MHz
h2f_user0_clk 100 100 100 100 MHz
h2f_user1_clk 100 100 100 100 MHz
h2f_user2_clk 200 200 160 160 MHz
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HPS PLL Specications
HPS PLL VCO Frequency Range
Table 40: HPS PLL VCO Frequency Range for Cyclone V Devices
Description Speed Grade Minimum Maximum Unit
VCO range –C7, –I7, –A7, –C8 320 1,600 MHz
–C6 320 1,850 MHz
HPS PLL Input Clock Range
e HPS PLL input clock range is 10 – 50 MHz. is clock range applies to both HPS_CLK1 and HPS_CLK2 inputs.
Related Information
Clock Select, Booting and Conguration chapter
Provides more information about the clock range for dierent values of clock select (CSEL).
HPS PLL Input Jitter
Use the following equation to determine the maximum input jitter (peak-to-peak) the HPS PLLs can tolerate. e divide value (N) is the value
programmed into the denominator eld of the VCO register for each PLL. e PLL input reference clock is divided by this value. e range of the
denominator is 1 to 64.
Maximum input jitter = Input clock period × Divide value (N) × 0.02
Table 41: Examples of Maximum Input Jitter
Input Reference Clock Period Divide Value (N) Maximum Jitter Unit
40 ns 1 0.8 ns
40 ns 2 1.6 ns
40 ns 4 3.2 ns
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Quad SPI Flash Timing Characteristics
Table 42: Quad Serial Peripheral Interface (SPI) Flash Timing Requirements for Cyclone V Devices
Symbol Description Min Typ Max Unit
Fclk SCLK_OUT clock frequency (External clock) — — 108 MHz
Tqspi_clk QSPI_CLK clock period (Internal reference
clock)
2.32 — — ns
Tdutycycle SCLK_OUT duty cycle 45 — 55 %
Tdssfrst Output delay QSPI_SS valid before rst clock
edge
— 1/2 cycle of
SCLK_OUT
— ns
Tdsslst Output delay QSPI_SS valid aer last clock
edge
–1 — 1 ns
Tdio I/O data output delay –1 — 1 ns
Tdin_start Input data valid start — — (2 + Rdelay) ×
Tqspi_clk – 7.52 (68)
ns
Tdin_end Input data valid end (2 + Rdelay) ×
Tqspi_clk – 1.21 (68)
— — ns
(68) Rdelay is set by programming the register qspiregs.rddatacap. For the SoC EDS soware version 13.1 and later, Altera provides automatic Quad SPI
calibration in the preloader. For more information about Rdelay, refer to the Quad SPI Flash Controller chapter in the Cyclone V Hard Processor
System Technical Reference Manual.
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Figure 5: Quad SPI Flash Timing Diagram
is timing diagram illustrates clock polarity mode 0 and clock phase mode 0.
QSPI_SS
SCLK_OUT
QSPI_DATA
Tdin_start
Tdsslst
Tdio
Tdin_end
Tdssfrst
Data Out Data In
Related Information
Quad SPI Flash Controller Chapter, Cyclone V Hard Processor System Technical Reference Manual
Provides more information about Rdelay.
SPI Timing Characteristics
Table 43: SPI Master Timing Requirements for Cyclone V Devices
e setup and hold times can be used for Texas Instruments SSP mode and National Semiconductor Microwire mode.
Symbol Description Min Max Unit
Tclk CLK clock period 16.67 — ns
Tsu SPI Master-in slave-out (MISO) setup time 8.35 (69) — ns
ThSPI MISO hold time 1 — ns
Tdutycycle SPI_CLK duty cycle 45 55 %
(69) is value is based on rx_sample_dly = 1 and spi_m_clk = 120 MHz. spi_m_clk is the internal clock that is used by SPI Master to derive it’s SCLK_
OUT. ese timings are based on rx_sample_dly of 1. is delay can be adjusted as needed to accommodate slower response times from the slave.
Note that a delay of 0 is not allowed. e setup time can be used as a reference starting point. It is very crucial to do a calibration to get the correct rx_
sample_dly value because each SPI slave device may have dierent output delay and each application board may have dierent path delay. For more
information about rx_sample_delay, refer to the SPI Controller chapter in the Hard Processor System Technical Reference Manual.
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Symbol Description Min Max Unit
Tdssfrst Output delay SPI_SS valid before rst clock edge 8 — ns
Tdsslst Output delay SPI_SS valid aer last clock edge 8 — ns
Tdio Master-out slave-in (MOSI) output delay –1 1 ns
Figure 6: SPI Master Timing Diagram
SPI_SS
SPI_CLK (scpol = 0)
SPI_MOSI (scph = 1)
SPI_MISO (scph = 1)
Tdssfrst
SPI_CLK (scpol = 1)
SPI_MOSI (scph = 0)
SPI_MISO (scph = 0)
Tdio
Tdio
Tdsslst
Tsu Th
Tsu Th
Table 44: SPI Slave Timing Requirements for Cyclone V Devices
e setup and hold times can be used for Texas Instruments SSP mode and National Semiconductor Microwire mode.
Symbol Description Min Max Unit
Tclk CLK clock period 20 — ns
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Symbol Description Min Max Unit
TsMOSI Setup time 5 — ns
ThMOSI Hold time 5 — ns
Tsuss Setup time SPI_SS valid before rst clock edge 8 — ns
Thss Hold time SPI_SS valid aer last clock edge 8 — ns
TdMISO output delay — 6 ns
Figure 7: SPI Slave Timing Diagram
SPI_SS
SPI_CLK (scpol = 0)
SPI_MOSI (scph = 1)
SPI_MISO (scph = 1)
SPI_CLK (scpol = 1)
SPI_MOSI (scph = 0)
SPI_MISO (scph = 0)
Tsuss
Td
Td
Ts
Th
TsTh
Thss
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Related Information
SPI Controller, Cyclone V Hard Processor System Technical Reference Manual
Provides more information about rx_sample_delay.
SD/MMC Timing Characteristics
Table 45: Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Cyclone V Devices
Aer power up or cold reset, the Boot ROM uses drvsel = 3 and smplsel = 0 to execute the code. At the same time, the SD/MMC controller enters
the Identication Phase followed by the Data Phase. During this time, the value of interface output clock SDMMC_CLK_OUT changes from a maximum
of 400 kHz (Identication Phase) up to a maximum of 12.5 MHz (Data Phase), depending on the internal reference clock SDMMC_CLK and the CSEL
setting. e value of SDMMC_CLK is based on the external oscillator frequency and has a maximum value of 50 MHz.
Aer the Boot ROM code exits and control is passed to the preloader, soware can adjust the value of drvsel and smplsel via the system manager.
drvsel can be set from 1 to 7 and smplsel can be set from 0 to 7. While the preloader is executing, the values for SDMMC_CLK and SDMMC_CLK_OUT
increase to a maximum of 200 MHz and 50 MHz respectively.
e SD/MMC interface calibration support will be available in a future release of the preloader through the SoC EDS soware update.
Symbol Description Min Max Unit
Tsdmmc_clk (internal reference
clock)
SDMMC_CLK clock period
(Identication mode)
20 — ns
SDMMC_CLK clock period
(Default speed mode)
5 — ns
SDMMC_CLK clock period
(High speed mode)
5 — ns
Tsdmmc_clk_out (interface output
clock)
SDMMC_CLK_OUT clock
period (Identication mode)
2500 — ns
SDMMC_CLK_OUT clock
period (Default speed mode)
40 — ns
SDMMC_CLK_OUT clock
period (High speed mode)
20 — ns
Tdutycycle SDMMC_CLK_OUT duty cycle 45 55 %
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Symbol Description Min Max Unit
TdSDMMC_CMD/SDMMC_D
output delay
(Tsdmmc_clk × drvsel)/2
– 1.23 (70)
(Tsdmmc_clk × drvsel)/2
+ 1.69 (70)
ns
Tsu Input setup time 1.05 – (Tsdmmc_clk ×
smplsel)/2 (71)
— ns
ThInput hold time (Tsdmmc_clk × smplsel)/
2 (71)
— ns
Figure 8: SD/MMC Timing Diagram
Command/Data In
SDMMC_CLK_OUT
SDMMC_CMD & SDMMC_D (Out)
SDMMC_CMD & SDMMC_D (In)
Command/Data Out
Tsu
Td
Th
Related Information
Booting and Conguration Chapter, Cyclone V Hard Processor System Technical Reference Manual
Provides more information about CSEL pin settings in the SD/MMC Controller CSEL Pin Settings table.
USB Timing Characteristics
PHYs that support LPM mode may not function properly with the USB controller due to a timing issue. It is recommended that designers use the
MicroChip USB3300 PHY device that has been proven to be successful on the development board.
(70) drvsel is the drive clock phase shi select value.
(71) smplsel is the sample clock phase shi select value.
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Table 46: USB Timing Requirements for Cyclone V Devices
Symbol Description Min Typ Max Unit
Tclk USB CLK clock period — 16.67 — ns
TdCLK to USB_STP/USB_DATA[7:0] output delay 4.4 — 11 ns
Tsu Setup time for USB_DIR/USB_NXT/USB_DATA[7:0] 2 — — ns
ThHold time for USB_DIR/USB_NXT/USB_DATA[7:0] 1 — — ns
Figure 9: USB Timing Diagram
USB_CLK
USB_STP
USB_DATA[7:0]
USB_DIR & USB_NXT
To PHY From PHY
Tsu Th
Td
Ethernet Media Access Controller (EMAC) Timing Characteristics
Table 47: Reduced Gigabit Media Independent Interface (RGMII) TX Timing Requirements for Cyclone V Devices
Symbol Description Min Typ Max Unit
Tclk (1000Base-T) TX_CLK clock period — 8 — ns
Tclk (100Base-T) TX_CLK clock period — 40 — ns
Tclk (10Base-T) TX_CLK clock period — 400 — ns
Tdutycycle TX_CLK duty cycle 45 — 55 %
TdTX_CLK to TXD/TX_CTL output data delay –0.85 — 0.15 ns
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Figure 10: RGMII TX Timing Diagram
TX_CLK
TX_D[3:0]
TX_CTL
Td
Table 48: RGMII RX Timing Requirements for Cyclone V Devices
Symbol Description Min Typ Unit
Tclk (1000Base-T) RX_CLK clock period — 8 ns
Tclk (100Base-T) RX_CLK clock period — 40 ns
Tclk (10Base-T) RX_CLK clock period — 400 ns
Tsu RX_D/RX_CTL setup time 1 — ns
ThRX_D/RX_CTL hold time 1 — ns
Figure 11: RGMII RX Timing Diagram
Table 49: Management Data Input/Output (MDIO) Timing Requirements for Cyclone V Devices
Symbol Description Min Typ Max Unit
Tclk MDC clock period — 400 — ns
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Symbol Description Min Typ Max Unit
TdMDC to MDIO output data delay 10 — 20 ns
TsSetup time for MDIO data 10 — — ns
ThHold time for MDIO data 0 — — ns
Figure 12: MDIO Timing Diagram
MDC
MDIO_OUT
MDIO_IN
Tsu
Th
Td
I2C Timing Characteristics
Table 50: I2C Timing Requirements for Cyclone V Devices
Symbol Description
Standard Mode Fast Mode
Unit
Min Max Min Max
Tclk Serial clock (SCL) clock period 10 — 2.5 — µs
Tclkhigh SCL high time 4.7 — 0.6 — µs
Tclklow SCL low time 4 — 1.3 — µs
TsSetup time for serial data line (SDA) data to SCL 0.25 — 0.1 — µs
ThHold time for SCL to SDA data 0 3.45 0 0.9 µs
TdSCL to SDA output data delay — 0.2 — 0.2 µs
Tsu_start Setup time for a repeated start condition 4.7 — 0.6 — µs
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Symbol Description
Standard Mode Fast Mode
Unit
Min Max Min Max
Thd_start Hold time for a repeated start condition 4 — 0.6 — µs
Tsu_stop Setup time for a stop condition 4 — 0.6 — µs
Figure 13: I2C Timing Diagram
Data In
Td
Data Out
I2C_SCL
I2C_SDA
Ts
Th
Tsu_start Thd_start
Tsu_stop
NAND Timing Characteristics
Table 51: NAND ONFI 1.0 Timing Requirements for Cyclone V Devices
e NAND controller supports Open NAND FLASH Interface (ONFI) 1.0 Mode 5 timing as well as legacy NAND devices. is table lists the
requirements for ONFI 1.0 mode 5 timing. e HPS NAND controller can meet this timing by programming the C4 output of the main HPS PLL
and timing registers provided in the NAND controller.
Symbol Description Min Max Unit
Twp(72) Write enable pulse width 10 — ns
Twh(72) Write enable hold time 7 — ns
Trp(72) Read enable pulse width 10 — ns
Treh(72) Read enable hold time 7 — ns
Tclesu(72) Command latch enable to write enable setup time 10 — ns
(72) Timing of the NAND interface is controlled through the NAND conguration registers.
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Symbol Description Min Max Unit
Tcleh(72) Command latch enable to write enable hold time 5 — ns
Tcesu(72) Chip enable to write enable setup time 15 — ns
Tceh(72) Chip enable to write enable hold time 5 — ns
Talesu(72) Address latch enable to write enable setup time 10 — ns
Taleh(72) Address latch enable to write enable hold time 5 — ns
Tdsu(72) Data to write enable setup time 10 — ns
Tdh(72) Data to write enable hold time 5 — ns
Tcea Chip enable to data access time — 25 ns
Trea Read enable to data access time — 16 ns
Trhz Read enable to data high impedance — 100 ns
Trr Ready to read enable low 20 — ns
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Figure 14: NAND Command Latch Timing Diagram
Command
NAND_CLE
NAND_CE
NAND_WE
NAND_DQ[7:0]
Tclesu
Tcesu Tcleh
Tceh
Twp
Talesu Taleh
Tdsu Tdh
NAND_ALE
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Figure 15: NAND Address Latch Timing Diagram
Address
NAND_CLE
NAND_WE
NAND_ALE
NAND_DQ[7:0]
Tclesu
Tcesu
Twh
Twp
Talesu Taleh
Tdsu Tdh
NAND_CE
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Figure 16: NAND Data Write Timing Diagram
NAND_CLE
NAND_WE
NAND_ALE
NAND_DQ[7:0]
Tceh
Tcleh
Twp
Talesu
Tdsu
Tdh
NAND_CE
Din
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Figure 17: NAND Data Read Timing Diagram
NAND_RE
NAND_RB
NAND_DQ[7:0]
NAND_CE
Dout
Tcea
Trp Treh
Trea
Trhz
Trr
ARM Trace Timing Characteristics
Table 52: ARM Trace Timing Requirements for Cyclone V Devices
Most debugging tools have a mechanism to adjust the capture point of trace data.
Description Min Max Unit
CLK clock period 12.5 — ns
CLK maximum duty cycle 45 55 %
CLK to D0 –D7 output data delay –1 1 ns
UART Interface
e maximum UART baud rate is 6.25 megasymbols per second.
GPIO Interface
e minimum detectable general-purpose I/O (GPIO) pulse width is 2 μs. e pulse width is based on a debounce clock frequency of 1 MHz.
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CAN Interface
e maximum controller area network (CAN) data rate is 1 Mbps.
HPS JTAG Timing Specications
Table 53: HPS JTAG Timing Parameters and Values for Cyclone V Devices
Symbol Description Min Max Unit
tJCP TCK clock period 30 — ns
tJCH TCK clock high time 14 — ns
tJCL TCK clock low time 14 — ns
tJPSU (TDI) TDI JTAG port setup time 2 — ns
tJPSU (TMS) TMS JTAG port setup time 3 — ns
tJPH JTAG port hold time 5 — ns
tJPCO JTAG port clock to output — 12(73) ns
tJPZX JTAG port high impedance to valid output — 14(73) ns
tJPXZ JTAG port valid output to high impedance — 14(73) ns
Conguration Specications
is section provides conguration specications and timing for Cyclone V devices.
(73) A 1-ns adder is required for each VCCIO _HPS voltage step down from 3.0 V. For example, tJPCO= 13 ns if VCCIO _HPS of the TDO I/O bank = 2.5 V, or
14 ns if it equals 1.8 V.
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POR Specications
Table 54: Fast and Standard POR Delay Specication for Cyclone V Devices
POR Delay Minimum Maximum Unit
Fast 4 12(74) ms
Standard 100 300 ms
Related Information
MSEL Pin Settings
Provides more information about POR delay based on MSEL pin settings for each conguration scheme.
FPGA JTAG Conguration Timing
Table 55: FPGA JTAG Timing Parameters and Values for Cyclone V Devices
Symbol Description Min Max Unit
tJCP TCK clock period 30, 167(75) — ns
tJCH TCK clock high time 14 — ns
tJCL TCK clock low time 14 — ns
tJPSU (TDI) TDI JTAG port setup time 1 — ns
tJPSU (TMS) TMS JTAG port setup time 3 — ns
tJPH JTAG port hold time 5 — ns
tJPCO JTAG port clock to output — 11(76) ns
tJPZX JTAG port high impedance to valid output — 14(76) ns
(74) e maximum pulse width of the fast POR delay is 12 ms, providing enough time for the PCIe hard IP to initialize aer the POR trip.
(75) e minimum TCK clock period is 167 ns if VCCBAT is within the range 1.2 V – 1.5 V when you perform the volatile key programming.
(76) A 1-ns adder is required for each VCCIO voltage step down from 3.0 V. For example, tJPCO= 13 ns if VCCIO of the TDO I/O bank = 2.5 V, or 14 ns if
it equals 1.8 V.
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Symbol Description Min Max Unit
tJPXZ JTAG port valid output to high impedance — 14(76) ns
FPP Conguration Timing
DCLK-to-DATA[] Ratio (r) for FPP Conguration
Fast passive parallel (FPP) conguration requires a dierent DCLK-to-DATA[] ratio when you turn on encryption or the compression feature.
Depending on the DCLK-to-DATA[] ratio, the host must send a DCLK frequency that is r times the DATA[] rate in byte per second (Bps) or word per
second (Wps). For example, in FPP ×16 where the r is 2, the DCLK frequency must be 2 times the DATA[] rate in Wps.
Cyclone V devices use additional clock cycles to decrypt and decompress the conguration data. If the DCLK-to-DATA[] ratio is greater than 1, at the
end of conguration, you can only stop the DCLK (DCLK-to-DATA[] ratio – 1) clock cycles aer the last data is latched into the Cyclone V device.
Table 56: DCLK-to-DATA[] Ratio for Cyclone V Devices
Conguration Scheme Encryption Compression DCLK-to-DATA[] Ratio (r)
FPP (8-bit wide)
O O 1
On O 1
O On 2
On On 2
FPP (16-bit wide)
O O 1
On O 2
O On 4
On On 4
FPP Conguration Timing when DCLK-to-DATA[] = 1
When you enable decompression or the design security feature, the DCLK-to-DATA[] ratio varies for FPP ×8 and FPP ×16. For the respective DCLK-
to-DATA[] ratio, refer to the DCLK-to-DATA[] Ratio for Cyclone V Devices table.
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Table 57: FPP Timing Parameters When DCLK-to-DATA[] Ratio is 1 for Cyclone V Devices
Symbol Parameter Minimum Maximum Unit
tCF2CD nCONFIG low to CONF_DONE low — 600 ns
tCF2ST0 nCONFIG low to nSTATUS low — 600 ns
tCFG nCONFIG low pulse width 2 — µs
tSTATUS nSTATUS low pulse width 268 1506(77) µs
tCF2ST1 nCONFIG high to nSTATUS high — 1506(78) µs
tCF2CK(79) nCONFIG high to rst rising edge on DCLK 1506 — µs
tST2CK(79) nSTATUS high to rst rising edge of DCLK 2 — µs
tDSU DATA[] setup time before rising edge on DCLK 5.5 — ns
tDH DATA[] hold time aer rising edge on DCLK 0 — ns
tCH DCLK high time 0.45 × 1/fMAX — s
tCL DCLK low time 0.45 × 1/fMAX — s
tCLK DCLK period 1/fMAX — s
fMAX DCLK frequency (FPP ×8/ ×16) — 125 MHz
tCD2UM CONF_DONE high to user mode(80) 175 437 µs
tCD2CU CONF_DONE high to CLKUSR enabled 4× maximum DCLK period — —
tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU + (Tinit × CLKUSR
period)
— —
Tinit Number of clock cycles required for device initialization 8,576 — Cycles
(77) You can obtain this value if you do not delay conguration by extending the nCONFIG or the nSTATUS low pulse width.
(78) You can obtain this value if you do not delay conguration by externally holding the nSTATUS low.
(79) If nSTATUS is monitored, follow the tST2CK specication. If nSTATUS is not monitored, follow the tCF2CK specication.
(80) e minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
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Related Information
FPP Conguration Timing
Provides the FPP conguration timing waveforms.
FPP Conguration Timing when DCLK-to-DATA[] >1
Table 58: FPP Timing Parameters When DCLK-to-DATA[] Ratio is >1 for Cyclone V Devices
Use these timing parameters when you use the decompression and design security features.
Symbol Parameter Minimum Maximum Unit
tCF2CD nCONFIG low to CONF_DONE low — 600 ns
tCF2ST0 nCONFIG low to nSTATUS low — 600 ns
tCFG nCONFIG low pulse width 2 — µs
tSTATUS nSTATUS low pulse width 268 1506(81) µs
tCF2ST1 nCONFIG high to nSTATUS high — 1506(82) µs
tCF2CK(83) nCONFIG high to rst rising edge on DCLK 1506 — µs
tST2CK(83) nSTATUS high to rst rising edge of DCLK 2 — µs
tDSU DATA[] setup time before rising edge on DCLK 5.5 — ns
tDH DATA[] hold time aer rising edge on DCLK N – 1/fDCLK(84) — s
tCH DCLK high time 0.45 × 1/fMAX — s
tCL DCLK low time 0.45 × 1/fMAX — s
tCLK DCLK period 1/fMAX — s
fMAX DCLK frequency (FPP ×8/ ×16) — 125 MHz
tRInput rise time — 40 ns
(81) is value can be obtained if you do not delay conguration by extending the nCONFIG or nSTATUS low pulse width.
(82) is value can be obtained if you do not delay conguration by externally holding nSTATUS low.
(83) If nSTATUS is monitored, follow the tST2CK specication. If nSTATUS is not monitored, follow the tCF2CK specication.
(84) N is the DCLK-to-DATA[] ratio and fDCLK is the DCLK frequency of the system.
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Symbol Parameter Minimum Maximum Unit
tFInput fall time — 40 ns
tCD2UM CONF_DONE high to user mode(85) 175 437 µs
tCD2CU CONF_DONE high to CLKUSR enabled 4 × maximum DCLK period — —
tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU + (Tinit × CLKUSR
period)
— —
Tinit Number of clock cycles required for device initialization 8,576 — Cycles
Related Information
FPP Conguration Timing
Provides the FPP conguration timing waveforms.
AS Conguration Timing
Table 59: AS Timing Parameters for AS ×1 and ×4 Congurations in Cyclone V Devices
e minimum and maximum numbers apply to both the internal oscillator and CLKUSR when either one is used as the clock source for device
conguration.
e tCF2CD, tCF2ST0, tCFG, tSTATUS, and tCF2ST1 timing parameters are identical to the timing parameters for passive serial (PS) mode listed in PS
Timing Parameters for Cyclone V Devices table. You can obtain the tCF2ST1 value if you do not delay conguration by externally holding nSTATUS
low.
Symbol Parameter Minimum Maximum Unit
tCO DCLK falling edge to the AS_DATA0/ASDO output — 2 ns
tSU Data setup time before the falling edge on DCLK 1.5 — ns
tDH Data hold time aer the falling edge on DCLK 0 — ns
tCD2UM CONF_DONE high to user mode 175 437 µs
tCD2CU CONF_DONE high to CLKUSR enabled 4 × maximum DCLK period — —
(85) e minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
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Symbol Parameter Minimum Maximum Unit
tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU + (Tinit × CLKUSR
period)
— —
Tinit Number of clock cycles required for device initialization 8,576 — Cycles
Related Information
•PS Conguration Timing on page 74
•AS Conguration Timing
Provides the AS conguration timing waveform.
DCLK Frequency Specication in the AS Conguration Scheme
Table 60: DCLK Frequency Specication in the AS Conguration Scheme
is table lists the internal clock frequency specication for the AS conguration scheme. e DCLK frequency specication applies when you use
the internal oscillator as the conguration clock source. e AS multi-device conguration scheme does not support DCLK frequency of 100 MHz.
Parameter Minimum Typical Maximum Unit
DCLK frequency in AS conguration scheme
5.3 7.9 12.5 MHz
10.6 15.7 25.0 MHz
21.3 31.4 50.0 MHz
42.6 62.9 100.0 MHz
PS Conguration Timing
Table 61: PS Timing Parameters for Cyclone V Devices
Symbol Parameter Minimum Maximum Unit
tCF2CD nCONFIG low to CONF_DONE low — 600 ns
tCF2ST0 nCONFIG low to nSTATUS low — 600 ns
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Symbol Parameter Minimum Maximum Unit
tCFG nCONFIG low pulse width 2 — µs
tSTATUS nSTATUS low pulse width 268 1506(86) µs
tCF2ST1 nCONFIG high to nSTATUS high — 1506(87) µs
tCF2CK(88) nCONFIG high to rst rising edge on DCLK 1506 — µs
tST2CK(88) nSTATUS high to rst rising edge of DCLK 2 — µs
tDSU DATA[] setup time before rising edge on DCLK 5.5 — ns
tDH DATA[] hold time aer rising edge on DCLK 0 — ns
tCH DCLK high time 0.45 × 1/fMAX — s
tCL DCLK low time 0.45 × 1/fMAX — s
tCLK DCLK period 1/fMAX — s
fMAX DCLK frequency — 125 MHz
tCD2UM CONF_DONE high to user mode(89) 175 437 µs
tCD2CU CONF_DONE high to CLKUSR enabled 4 × maximum DCLK period — —
tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU + (Tinit × CLKUSR
period)
— —
Tinit Number of clock cycles required for device initialization 8,576 — Cycles
Related Information
PS Conguration Timing
Provides the PS conguration timing waveform.
(86) You can obtain this value if you do not delay conguration by extending the nCONFIG or nSTATUS low pulse width.
(87) You can obtain this value if you do not delay conguration by externally holding nSTATUS low.
(88) If nSTATUS is monitored, follow the tST2CK specication. If nSTATUS is not monitored, follow the tCF2CK specication.
(89) e minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
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Initialization
Table 62: Initialization Clock Source Option and the Maximum Frequency for Cyclone V Devices
Initialization Clock Source Conguration Scheme Maximum Frequency (MHz) Minimum Number of Clock Cycles
Internal Oscillator AS, PS, and FPP 12.5
Tinit
CLKUSR(90) PS and FPP 125
AS 100
DCLK PS and FPP 125
Conguration Files
Table 63: Uncompressed .rbf Sizes for Cyclone V Devices
Use this table to estimate the le size before design compilation. Dierent conguration le formats, such as a hexadecimal le (.hex) or tabular
text le (.ttf) format, have dierent le sizes.
For the dierent types of conguration le and le sizes, refer to the Quartus Prime soware. However, for a specic version of the Quartus Prime
soware, any design targeted for the same device has the same uncompressed conguration le size.
e IOCSR raw binary le (.rbf) size is specically for the Conguration via Protocol (CvP) feature.
(90) To enable CLKUSR as the initialization clock source, turn on the Enable user-supplied start-up clock (CLKUSR) option in the Quartus Prime
soware from the General panel of the Device and Pin Options dialog box.
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Variant Member Code Conguration .rbf Size (bits) IOCSR .rbf Size (bits) Recommended EPCQ Serial Conguration
Device(91)
Cyclone V E (92)
A2 21,061,280 275,608 EPCQ64
A4 21,061,280 275,608 EPCQ64
A5 33,958,560 322,072 EPCQ128
A7 56,167,552 435,288 EPCQ128
A9 102,871,776 400,408 EPCQ256
Cyclone V GX
C3 14,510,912 320,280 EPCQ32
C4 33,958,560 322,072 EPCQ128
C5 33,958,560 322,072 EPCQ128
C7 56,167,552 435,288 EPCQ128
C9 102,871,776 400,408 EPCQ256
Cyclone V GT
D5 33,958,560 322,072 EPCQ128
D7 56,167,552 435,288 EPCQ128
D9 102,871,776 400,408 EPCQ256
Cyclone V SE (92)
A2(93) 33,958,560 322,072 EPCQ128
A4(93) 33,958,560 322,072 EPCQ128
A5 56,057,632 324,888 EPCQ128
A6 56,057,632 324,888 EPCQ128
(91) e recommended EPCQ serial conguration devices are able to store more than one image.
(92) No PCIe hard IP, conguration via protocol (CvP) is not supported in this family.
(93) is device will be supported in a future release of the Quartus Prime soware.
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Variant Member Code Conguration .rbf Size (bits) IOCSR .rbf Size (bits) Recommended EPCQ Serial Conguration
Device(91)
Cyclone V SX
C2(93) 33,958,560 322,072 EPCQ128
C4(93) 33,958,560 322,072 EPCQ128
C5 56,057,632 324,888 EPCQ128
C6 56,057,632 324,888 EPCQ128
Cyclone V ST D5 56,057,632 324,888 EPCQ128
D6 56,057,632 324,888 EPCQ128
Minimum Conguration Time Estimation
Table 64: Minimum Conguration Time Estimation for Cyclone V Devices
e estimated values are based on the conguration .rbf sizes in Uncompressed .rbf Sizes for Cyclone V Devices table.
Variant Member Code
Active Serial(94) Fast Passive Parallel(95)
Width DCLK (MHz) Minimum Congura‐
tion Time (ms)
Width DCLK (MHz) Minimum Conguration Time
(ms)
Cyclone V E
A2 4 100 53 16 125 11
A4 4 100 53 16 125 11
A5 4 100 85 16 125 17
A7 4 100 140 16 125 28
A9 4 100 257 16 125 51
(91) e recommended EPCQ serial conguration devices are able to store more than one image.
(94) DCLK frequency of 100 MHz using external CLKUSR.
(95) Maximum FPGA FPP bandwidth may exceed bandwidth available from some external storage or control logic.
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Variant Member Code
Active Serial(94) Fast Passive Parallel(95)
Width DCLK (MHz) Minimum Congura‐
tion Time (ms)
Width DCLK (MHz) Minimum Conguration Time
(ms)
Cyclone V GX
C3 4 100 36 16 125 7
C4 4 100 85 16 125 17
C5 4 100 85 16 125 17
C7 4 100 140 16 125 28
C9 4 100 257 16 125 51
Cyclone V GT
D5 4 100 85 16 125 17
D7 4 100 140 16 125 28
D9 4 100 257 16 125 51
Cyclone V SE
A2 4 100 85 16 125 17
A4 4 100 85 16 125 17
A5 4 100 140 16 125 28
A6 4 100 140 16 125 28
Cyclone V SX
C2 4 100 85 16 125 17
C4 4 100 85 16 125 17
C5 4 100 140 16 125 28
C6 4 100 140 16 125 28
Cyclone V ST D5 4 100 140 16 125 28
D6 4 100 140 16 125 28
(94) DCLK frequency of 100 MHz using external CLKUSR.
(95) Maximum FPGA FPP bandwidth may exceed bandwidth available from some external storage or control logic.
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Related Information
Conguration Files on page 76
Remote System Upgrades
Table 65: Remote System Upgrade Circuitry Timing Specications for Cyclone V Devices
Parameter Minimum Unit
tRU_nCONFIG(96) 250 ns
tRU_nRSTIMER(97) 250 ns
Related Information
•Remote System Upgrade State Machine
Provides more information about conguration reset (RU_CONFIG) signal.
•User Watchdog Timer
Provides more information about reset_timer (RU_nRSTIMER) signal.
User Watchdog Internal Oscillator Frequency Specications
Table 66: User Watchdog Internal Oscillator Frequency Specications for Cyclone V Devices
Parameter Minimum Typical Maximum Unit
User watchdog internal oscillator frequency 5.3 7.9 12.5 MHz
I/O Timing
Altera oers two ways to determine I/O timing—the Excel-based I/O timing and the Quartus Prime Timing Analyzer.
(96) is is equivalent to strobing the reconguration input of the ALTREMOTE_UPDATE IP core high for the minimum timing specication.
(97) is is equivalent to strobing the reset timer input of the ALTREMOTE_UPDATE IP core high for the minimum timing specication.
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Excel-based I/O timing provides pin timing performance for each device density and speed grade. e data is typically used prior to designing the
FPGA to get an estimate of the timing budget as part of the link timing analysis.
e Quartus Prime Timing Analyzer provides a more accurate and precise I/O timing data based on the specics of the design aer you complete
place-and-route.
Related Information
Cyclone V I/O Timing Spreadsheet
Provides the Cyclone V Excel-based I/O timing spreadsheet.
Programmable IOE Delay
Table 67: I/O element (IOE) Programmable Delay for Cyclone V Devices
Parameter(98) Available
Settings
Minimum
Oset(99)
Fast Model Slow Model
Unit
Industrial Commercial –C6 –C7 –C8 –I7 –A7
D1 32 0 0.508 0.517 0.971 1.187 1.194 1.179 1.160 ns
D3 8 0 1.761 1.793 3.291 4.022 3.961 3.999 3.929 ns
D4 32 0 0.510 0.519 1.180 1.187 1.195 1.180 1.160 ns
D5 32 0 0.508 0.517 0.970 1.186 1.194 1.179 1.179 ns
Programmable Output Buer Delay
Table 68: Programmable Output Buer Delay for Cyclone V Devices
is table lists the delay chain settings that control the rising and falling edge delays of the output buer.
You can set the programmable output buer delay in the Quartus Prime soware by setting the Output Buer Delay Control assignment to either
positive, negative, or both edges, with the specic values stated here (in ps) for the Output Buer Delay assignment.
(98) You can set this value in the Quartus Prime soware by selecting D1, D3, D4, and D5 in the Assignment Name column of Assignment Editor.
(99) Minimum oset does not include the intrinsic delay.
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Symbol Parameter Typical Unit
DOUTBUF Rising and/or falling edge delay
0 (default) ps
50 ps
100 ps
150 ps
Glossary
Table 69: Glossary
Term Denition
Dierential I/O standards Receiver Input Waveforms
Single-Ended Waveform
Differential Waveform
Positive Channel (p) = VIH
Negative Channel (n) = VIL
Ground
VID
VID
VID
p - n = 0 V
VCM
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Term Denition
Transmitter Output Waveforms
Single-Ended Waveform
Differential Waveform
Positive Channel (p) = VOH
Negative Channel (n) = VOL
Ground
VOD
VOD
VOD
p - n = 0 V
VCM
fHSCLK Le/right PLL input clock frequency.
fHSDR High-speed I/O block—Maximum/minimum LVDS data transfer rate (fHSDR =1/TUI).
J High-speed I/O block—Deserialization factor (width of parallel data bus).
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Term Denition
JTAG timing specications JTAG Timing Specications
TDO
TCK
tJPZX tJPCO
tJPH
tJPXZ
t JCP
t JPSU
t JCL
t JCH
TDI
TMS
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Term Denition
PLL specications Diagram of PLL specications
Core Clock
External Feedback
Reconfigurable in User Mode
Legend
CLK
N
PFD
Switchover
Delta Sigma
Modulator
VCO
CP LF
CLKOUT Pins
GCLK
RCLK
fINPFD
fIN
fVCO fOUT
fOUT _EXT
Counters
C0..C17
4
Note:
(1) Core Clock can only be fed by dedicated clock input pins or PLL outputs.
RLReceiver dierential input discrete resistor (external to the Cyclone V device).
Sampling window (SW) Timing diagram—e period of time during which the data must be valid in order to capture it correctly.
e setup and hold times determine the ideal strobe position in the sampling window, as shown:
Bit Time
0.5 x TCCS RSKM Sampling Window
(SW)
RSKM 0.5 x TCCS
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Term Denition
Single-ended voltage referenced I/O
standard e JEDEC standard for the SSTL and HSTL I/O denes both the AC and DC input signal values. e AC
values indicate the voltage levels at which the receiver must meet its timing specications. e DC values
indicate the voltage levels at which the nal logic state of the receiver is unambiguously dened. Aer the
receiver input has crossed the AC value, the receiver changes to the new logic state.
e new logic state is then maintained as long as the input stays beyond the DC threshold. is approach
is intended to provide predictable receiver timing in the presence of input waveform ringing.
Single-Ended Voltage Referenced I/O Standard
VIH(AC )
VIH(DC )
VREF VIL(DC )
VIL(AC )
VOH
VOL
VCCIO
VSS
tCHigh-speed receiver/transmitter input and output clock period.
TCCS (channel-to-channel-skew) e timing dierence between the fastest and slowest output edges, including the tCO variation and clock
skew, across channels driven by the same PLL. e clock is included in the TCCS measurement (refer to
the Timing Diagram gure under SW in this table).
tDUTY High-speed I/O block—Duty cycle on high-speed transmitter output clock.
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Term Denition
tFALL Signal high-to-low transition time (80–20%)
tINCCJ Cycle-to-cycle jitter tolerance on the PLL clock input
tOUTPJ_IO Period jitter on the GPIO driven by a PLL
tOUTPJ_DC Period jitter on the dedicated clock output driven by a PLL
tRISE Signal low-to-high transition time (20–80%)
Timing Unit Interval (TUI) e timing budget allowed for skew, propagation delays, and the data sampling window. (TUI = 1/
(Receiver Input Clock Frequency Multiplication Factor) = tC/w)
VCM(DC) DC common mode input voltage.
VICM Input common mode voltage—e common mode of the dierential signal at the receiver.
VID Input dierential voltage swing—e dierence in voltage between the positive and complementary
conductors of a dierential transmission at the receiver.
VDIF(AC) AC dierential input voltage—Minimum AC input dierential voltage required for switching.
VDIF(DC) DC dierential input voltage— Minimum DC input dierential voltage required for switching.
VIH Voltage input high—e minimum positive voltage applied to the input which is accepted by the device as
a logic high.
VIH(AC) High-level AC input voltage
VIH(DC) High-level DC input voltage
VIL Voltage input low—e maximum positive voltage applied to the input which is accepted by the device as
a logic low.
VIL(AC) Low-level AC input voltage
VIL(DC) Low-level DC input voltage
VOCM Output common mode voltage—e common mode of the dierential signal at the transmitter.
VOD Output dierential voltage swing—e dierence in voltage between the positive and complementary
conductors of a dierential transmission line at the transmitter.
VSWING Dierential input voltage
VXInput dierential cross point voltage
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Term Denition
VOX Output dierential cross point voltage
W High-speed I/O block—Clock boost factor
Document Revision History
Date Version Changes
December 2016 2016.12.09 • Updated VICM (AC coupled) specications for 1.5 V PCML in Receiver Specications for Cyclone V GX, GT,
SX, and ST Devices table.
• Added maximum specication for Td in Management Data Input/Output (MDIO) Timing Requirements for
Cyclone V Devices table.
• Updated Tinit specications in the following tables:
• FPP Timing Parameters When DCLK-to-DATA[] Ratio is 1 for Cyclone V Devices
• FPP Timing Parameters When DCLK-to-DATA[] Ratio is >1 for Cyclone V Devices
• AS Timing Parameters for AS ×1 and ×4 Congurations in Cyclone V Devices
• PS Timing Parameters for Cyclone V Devices
June 2016 2016.06.10 • Changed pin capacitance to maximum values.
• Updated SPI Master Timing Requirements for Cyclone V Devices table.
• Added Tsu and Th specications.
• Removed Tdinmax specications.
• Updated SPI Master Timing Diagram.
• Updated Tclk spec from maximum to minimum in I2C Timing Requirements for Cyclone V Devices table.
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Date Version Changes
December 2015 2015.12.04 • Updated Quad Serial Peripheral Interface (SPI) Flash Timing Requirements for Cyclone V Devices table.
• Updated Fclk, Tdutycycle, and Tdssfrst specications.
• Added Tqspi_clk, Tdin_start, and Tdin_end specications.
• Removed Tdinmax specications.
• Updated the minimum specication for Tclk to 16.67 ns and removed the maximum specication in SPI
Master Timing Requirements for Cyclone V Devices table.
• Updated Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Cyclone V Devices table.
• Updated T clk to Tsdmmc_clk_out symbol.
• Updated Tsdmmc_clk_out and Td specications.
• Added Tsdmmc_clk, Tsu, and Th specications.
• Removed Tdinmax specications.
• Updated the following diagrams:
• Quad SPI Flash Timing Diagram
• SD/MMC Timing Diagram
• Updated conguration .rbf sizes for Cyclone V devices.
• Changed instances of Quartus II to Quartus Prime.
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Date Version Changes
June 2015 2015.06.12 • Updated the supported data rates for the following output standards using true LVDS output buer types in
the High-Speed I/O Specications for Cyclone V Devices table:
• True RSDS output standard: data rates of up to 360 Mbps
• True mini-LVDS output standard: data rates of up to 400 Mbps
• Changed Queued Serial Peripheral Interface (QSPI) to Quad Serial Peripheral Interface (SPI) Flash.
• Updated Th location in I2C Timing Diagram.
• Updared Twp location in NAND Address Latch Timing Diagram.
• Updated the maximum value for tCO from 4 ns to 2 ns in AS Timing Parameters for AS ×1 and ×4 Congu‐
rations in Cyclone V Devices table.
• Moved the following timing diagrams to the Conguration, Design Security, and Remote System Upgrades
in Cyclone V Devices chapter.
• FPP Conguration Timing Waveform When DCLK-to-DATA[] Ratio is 1
• FPP Conguration Timing Waveform When DCLK-to-DATA[] Ratio is >1
• AS Conguration Timing Waveform
• PS Conguration Timing Waveform
March 2015 2015.03.31 • Added VCC specications for devices with internal scrubbing feature (with SC sux) in Recommended
Operating Conditions table.
• Corrected the unit for tDH from ns to s in FPP Timing Parameters When DCLK-to-DATA[] Ratio is >1 for
Cyclone V Devices table.
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Date Version Changes
January 2015 2015.01.23 • Updated the transceiver specication for Cyclone V ST from 5 Gbps to 6.144 Gbps. Updated the note in the
following tables:
• Transceiver Power Supply Operating Conditions for Cyclone V GX, GT, SX, and ST Devices
• Transceiver Specications for Cyclone V GX, GT, SX, and ST Devices
• Transceiver Compliance Specication for All Supported Protocol for Cyclone V Devices
• Updated the description for VCC_AUX_SHARED to “HPS auxiliary power supply”. Added a note to state that
VCC_AUX_SHARED must be powered by the same source as VCC_AUX for Cyclone V SX C5, C6, D5, and D6
devices, and Cyclone V SE A5 and A6 devices. Updated in the following tables:
• Absolute Maximum Ratings for Cyclone V Devices
• HPS Power Supply Operating Conditions for Cyclone V SE, SX, and ST Devices
• Added statement in I/O Standard Specications: You must perform timing closure analysis to determine the
maximum achievable frequency for general purpose I/O standards.
• Updated the conditions for transceiver reference clock rise time and fall time: Measure at ±60 mV of
dierential signal. Added a note to the conditions: REFCLK performance requires to meet transmitter REFCLK
phase noise specication.
• Updated fVCO maximum value from 1400 MHz to 1600 MHz for –C7 and –I7 speed grades in the PLL
specications table.
• Updated the description in Periphery Performance Specications to mention that proper timing closure is
required in design.
• Added the following notes in the High-Speed I/O Specications for Cyclone V Devices table:
•e Cyclone V devices support true RSDS output standard with data rates of up to 230 Mbps using true
LVDS output buer types on all I/O banks.
•e Cyclone V devices support true mini-LVDS output standard with data rates of up to 340 Mbps using
true LVDS output buer types on all I/O banks.
• Updated HPS Clock Performance main_base_clk specications from 462 MHz to 400 MHz for –C6 speed
grade.
• Updated HPS PLL VCO maximum frequency to 1,600 MHz (for –C7, –I7, –A7, and –C8 speed grades) and
1,850 MHz (for –C6 speed grade).
• Changed the symbol for HPS PLL input jitter divide value from NR to N.
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• Removed “Slave select pulse width (Texas Instruments SSP mode)” parameter from the following tables:
• SPI Master Timing Requirements for Cyclone V Devices
• SPI Slave Timing Requirements for Cyclone V Devices
• Added descriptions to USB Timing Characteristics section in HPS Specications: PHYs that support LPM
mode may not function properly with the USB controller due to a timing issue. It is recommended that
designers use the MicroChip USB3300 PHY device that has been proven to be successful on the development
board.
• Added HPS JTAG timing specications.
• Updated the conguration .rbf size (bits) for Cyclone V devices.
• Added a note to Uncompressed .rbf Sizes for Cyclone V Devices table: e recommended EPCQ serial
conguration devices are able to store more than one image.
July 2014 3.9 • Added a note in Table 3, Table 4, and Table 5: e power supply value describes the budget for the DC
(static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN
tool for the additional budget for the dynamic tolerance requirements.
• Added a note in Table 19: Dierential inputs are powered by VCCPD which requires 2.5 V.
• Updated "Minimum dierential eye opening at the receiver serial input pins" specication in Table 20.
• Updated h2f_user2_clk specication for –C6, –C7, and –I7 speed grades in Table 34.
• Updated description in “HPS PLL Specications” section.
• Updated VCO range maximum specication in Table 35.
• Updated Td and Th specications in Table 41.
• Added Th specication in Table 43 and Figure 10.
• Updated a note in Figure 17, Figure 18, and Figure 20 as follows: Do not leave DCLK oating aer congu‐
ration. DCLK is ignored aer conguration is complete. It can toggle high or low if required.
• Removed “Remote update only in AS mode” specication in Table 54.
• Added DCLK device initialization clock source specication in Table 56.
• Added description in “Conguration Files” section: e IOCSR .rbf size is specically for the Congura‐
tion via Protocol (CvP) feature.
• Added "Recommended EPCQ Serial Conguration Device" values in Table 57.
• Removed fMAX_RU_CLK specication in Table 59.
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February 2014 3.8 • Updated VCCRSTCLK_HPS maximum specication in Table 1.
• Added VCC_AUX_SHARED specication in Table 1.
December 2013 3.7 • Updated Table 1, Table 3, Table 19, Table 20, Table 23, Table 25, Table 27, Table 34, Table 44, Table 51, Table
52, Table 55, and Table 61.
• Removed Preliminary tags for Table 1, Table 2, Table 3, Table 4, Table 5, Table 6, Table 7, Table 9, Table 12,
Table 13, Table 14, Table 15, Table 16, Table 17, Table 18, Table 19, Table 20, Table 24, Table 25, Table 26,
Table 27, Table 28, Table 32, Table 33, Table 49, Table 50, Table 51, Table 52, Table 53, Table 54, Table 55,
Table 57, Table 58, Table 59, Table 60, and Table 62.
November 2013 3.6 Updated Table 23, Table 30, and Table 31.
October 2013 3.5 • Added “HPS PLL Specications”.
• Added Table 23, Table 35, and Table 36.
• Updated Table 1, Table 5, Table 11, Table 19, Table 20, Table 21, Table 22, Table 25, Table 28, Table 34, Table
37, Table 38, Table 39, Table 40, Table 41, Table 42, Table 43, Table 44, Table 45, Table 46, Table 47, and Table
53.
• Updated Figure 1, Figure 2, Figure 4, Figure 10, Figure 12, Figure 13, and Figure 16.
• Removed table: GPIO Pulse Width for Cyclone V Devices.
June 2013 3.4 • Updated Table 20, Table 27, and Table 34.
• Updated “UART Interface” and “CAN Interface” sections.
• Removed the following tables:
• Table 45: UART Baud Rate for Cyclone V Devices
• Table 47: CAN Pulse Width for Cyclone V Devices
May 2013 3.3 • Added Table 33.
• Updated Figure 5, Figure 6, Figure 17, Figure 19, and Figure 20.
• Updated Table 1, Table 4, Table 5, Table 10, Table 13, Table 19, Table 20, Table 26, Table 32, Table 35, Table
36, Table 43, Table 53, Table 54, Table 57, and Table 61.
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March 2013 3.2 • Added HPS reset information in the “HPS Specications” section.
• Added Table 57.
• Updated Table 1, Table 2, Table 17, Table 20, Table 52, and Table 56.
• Updated Figure 18.
January 2013 3.1 Updated Table 4, Table 20, and Table 56.
November 2012 3.0 • Updated Table 1, Table 4, Table 5, Table 9, Table 14, Table 16, Table 17, Table 19, Table 20, Table 25, Table 28,
Table 52, Table 55, Table 56, and Table 59.
• Removed table: Transceiver Block Jitter Specications for Cyclone V GX Devices.
• Added HPS information:
• Added “HPS Specications” section.
• Added Table 33, Table 34, Table 35, Table 36, Table 37, Table 38, Table 39, Table 40, Table 41, Table 42,
Table 43, Table 44, Table 45, and Table 46.
• Added Figure 4, Figure 5, Figure 6, Figure 7, Figure 8, Figure 9, Figure 10, Figure 11, Figure 12, Figure 13,
Figure 14, Figure 15, and Figure 16.
• Updated Table 3.
June 2012 2.0 Updated for the Quartus II soware v12.0 release:
• Restructured document.
• Removed “Power Consumption” section.
• Updated Table 1,Table 3, Table 19, Table 20, Table 25, Table 27, Table 28, Table 30, Table 31, Table 34, Table
36, Table 37, Table 38, Table 39, Table 41, Table 43, and Table 46.
• Added Table 22, Table 23, and Table 29.
• Added Figure 1 and Figure 2.
• Added “Initialization” and “Conguration Files” sections.
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February 2012 1.2 • Added automotive speed grade information.
• Added Figure 2–1.
• Updated Table 2–3, Table 2–8, Table 2–9, Table 2–19, Table 2–20, Table 2–21, Table 2–22, Table 2–23, Table
2–24, Table 2–25, Table 2–26, Table 2–27, Table 2–28, Table 2–30, Table 2–35, and Table 2–43.
• Minor text edits.
November 2011 1.1 • Added Table 2–5.
• Updated Table 2–3, Table 2–4, Table 2–11, Table 2–13, Table 2–20, and Table 2–21.
October 2011 1.0 Initial release.
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