100344FC - National Semiconductor

TL/F/9883

100344 Low Power 8-Bit Latch with Cut-Off Drivers

July 1992

100344

Low Power 8-Bit Latch with Cut-Off Drivers

General Description

The 100344 contains eight D-type latches, individual inputs

(Dn), outputs (Qn), a common enable pin (E), latch enable

(LE), and output enable pin (OEN). A Q output follows its D

input when both E and LE are LOW. When either E or LE (or

both) are HIGH, a latch stores the last valid data present on

its D input prior to E or LE going HIGH.

A HIGH on OEN holds the outputs in a cut-off state. The

cut-off state is designed to be more negative than a normal

ECL LOW level. This allows the output emitter-followers to

turn off when the termination supply is b2.0V, presenting a

high impedance to the data bus. This high impedance re-

duces termination power and prevents loss of low state

noise margin when several loads share the bus.

The 100344 outputs are designed to drive a doubly termi-

nated 50Xtransmission line (25Xload impedance). All in-

puts have 50 kXpull-down resistors.

Features

YCut-off drivers

YDrives 25Xload

YLow power operation

Y2000V ESD protection

YVoltage compensated operating range eb

4.2V to

b5.7V

YAvailable to MIL-STD-883

Logic Symbol

TL/F/9883–4

Pin Names Description

D0–D7Data Inputs

EEnable Input

LE Latch Enable Input

OEN Output Enable Input

Q0–Q7Data Outputs

Connection Diagrams

24-Pin DIP

TL/F/9883–1

28-Pin PCC

TL/F/9883–3

24-Pin Quad Cerpak

TL/F/9883–2

C1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

Logic Diagram

TL/F/9883–5

Truth Table

Inputs Outputs

DnE LE OEN Qn

LLL L L

HLL L H

X H X L Latched*

X X H L Latched*

X X X H Cutoff

*Retains data present before either LE or E go HIGH.

HeHIGH Voltage level

LeLOW Voltage level

Cutoff elower-than-LOW state

XeDon’t Care

Absolute Maximum Ratings

Above which the useful life may be impaired (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Storage Temperature (TSTG)b65§Ctoa

150§C

Maximum Junction Temperature (TJ)

Ceramic a175§C

Plastic a150§C

VEE Pin Potential to Ground Pin b7.0V to a0.5V

Input Voltage (DC) VEE to a0.5V

Output Current (DC Output HIGH) b100 mA

ESD (Note 2) t2000V

Note 1: Absolute maximum ratings are those values beyond which the de-

vice may be damaged or have its useful life impaired. Functional operation

under these conditions is not implied.

Note 2: ESD testing conforms to MIL-STD-883, Method 3015.

Recommended Operating

Conditions

Case Temperature (TC)

Commercial 0§Ctoa

85§C

Industrial b40§Ctoa

85§

Military b55§Ctoa

125§C

Supply Voltage (VEE)b5.7V to b4.2V

Commercial Version

DC Electrical Characteristics

VEE eb

4.2V to b5.7V, VCC eVCCA eGND, TCe0§Ctoa

85§C (Note 3)

Symbol Parameter Min Typ Max Units Conditions

VOH Output HIGH Voltage b1025 b955 b870 mV VIN eVIH (Max) Loading with

VOL Output LOW Voltage b1830 b1705 b1620 mV or VIL (Min) 25Xto b2.0V

VOHC Output HIGH Voltage b1035 mV VIN eVIH (Min) Loading with

VOLC Output LOW Voltage b1610 mV or VIL (Max) 25Xto b2.0V

VOLZ Cutoff LOW Voltage b1950 mV VIN eVIH (Min) OEN eHIGH

or VIL (Max)

VIH Input HIGH Voltage b1165 b870 mV Guaranteed HIGH Signal for All Inputs

VIL Input LOW Voltage b1830 b1475 mV Guaranteed LOW Signal for All Inputs

IIL Input LOW Current 0.50 mAV

IN eVIL (Min)

IIH Input HIGH Current 240 mAV

IN eVIH (Max)

IEE Power Supply Current Inputs Open

b178 b85 mA VEE eb

4.2V to b4.8V

b185 b85 VEE eb

4.2V to b5.7V

Note 3: The specified limits represent the ‘‘worst case’’ value for the parameter. Since these values normally occur at the temperature extremes, additional noise

immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to

guarantee operation under ‘‘worst case’’ conditions.

DIP AC Electrical Characteristics

VEE eb

4.2V to b5.7V, VCC eVCCA eGND

Symbol Parameter TCe0§CT

25§CT

85§CUnits Conditions

Min Max Min Max Min Max

tPLH Propagation Delay 0.90 2.10 0.90 2.10 1.00 2.30 ns

Figures 1, 2

tPHL Dnto Output (Note 1)

tPLH Propagation Delay 1.60 3.10 1.60 3.10 1.80 3.40 ns

Figures 1, 4

tPHL LE,Eto Output (Note 1)

tPZH Propagation Delay 1.60 4.20 1.60 4.20 1.60 4.20 ns

Figures 1, 2

tPHZ OEN to Output 1.00 2.70 1.00 2.70 1.00 2.70 (Note 1)

tTLH Transition Time 0.45 2.00 0.45 2.00 0.45 2.00 ns

Figures 1, 3

tTHL 20% to 80%, 80% to 20%

Note 1: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching.

Commercial Version (Continued)

DIP AC Electrical Characteristics (Continued)

VEE eb

4.2V to b5.7V, VCC eVCCA eGND

Symbol Parameter TCe0§CT

25§CT

85§CUnits Conditions

Min Max Min Max Min Max

tSSetup Time

D0–D71.00 1.00 1.10 ns

Figures 1, 3

tHHold Time

D0–D70.10 0.10 0.10 ns

Figures 1, 3

tpw(H) Pulse Width HIGH

LE,E 2.00 2.00 2.00 ns

Figures 1, 3

PCC and Cerpak AC Electrical Characteristics

VEE eb

4.2V to b5.7V, VCC eVCCA eGND

Symbol Parameter TCe0§CT

25§CT

85§CUnits Conditions

Min Max Min Max Min Max

tPLH Propagation Delay 0.90 1.90 0.90 1.90 1.00 2.10 ns

Figures 1, 2

tPHL Dnto Output (Note 2)

tPLH Propagation Delay 1.60 2.90 1.60 2.90 1.80 3.20 ns

Figures 1, 4

tPHL LE,Eto Output (Note 2)

tPZH Propagation Delay 1.60 4.00 1.60 4.00 1.60 4.00 ns

Figures 1, 2

tPHZ OEN to Output 1.00 2.50 1.00 2.50 1.00 2.50 (Note 2)

tTLH Transition Time 0.45 1.90 0.45 1.90 0.45 1.90 ns

Figures 1, 3

tTHL 20% to 80%, 80% to 20%

tSSetup Time

D0–D70.90 0.90 1.00 ns

Figures 1, 3

tHHold Time

D0–D70.00 0.00 0.00 ns

Figures 1, 3

tpw(H) Pulse Width HIGH

LE,E 2.00 2.00 2.00 ns

Figures 1, 3

tOSHL Maximum Skew Common Edge PCC Only

Output-to-Output Variation 330 330 330 ps (Note 1)

Data to Output Path

tOSLH Maximum Skew Common Edge PCC Only

Output-to-Output Variation 330 330 330 ps (Note 1)

Data to Output Path

tOST Maximum Skew Opposite Edge PCC Only

Output-to-Output Variation 330 330 330 ps (Note 1)

Data to Output Path

tps Maximum Skew PCC Only

Pin (Signal) Transition Variation 230 230 230 ps (Note 1)

Data to Output Path

Note 1: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged

device. The specifications apply to any outputs switching in the same direction either HIGH to LOW (tOSHL), or LOW to HIGH (tOSLH), or in opposite directions both

HL and LH (tOST). Parameters tOST and tps guaranteed by design.

Note 2: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching.

Military Version

DC Electrical Characteristics

VEE eb

4.2V to b5.7V, VCC eVCCA eGND, TCeb

55§Ctoa

125§C

Symbol Parameter Min Max Units TCConditions Notes

VOH Output HIGH Voltage b1025 b870 mV 0§Cto

125§C

b1085 b870 mV b55§CV

IN eVIH (Max) Loading with 1, 2, 3

VOL Output LOW Voltage b1830 b1620 mV 0§Cto or VIL (Min) 25Xto b2.0V

a125§C

b1830 b1555 mV b55§C

VOHC Output HIGH Voltage b1035 mV 0§Cto

125§C

b1085 mV b55§CV

IN eVIH (Min) Loading with 1, 2, 3

VOLC Output LOW Voltage b1610 mV 0§Cto or VIL (Max) 25Xto b2.0V

a125§C

b1555 mV b55§C

VOLZ Cutoff LOW Voltage b1950 0§Cto V

IN eVIH (MIN)

mV a125§Cor VIL (Max) OEN eHIGH 1, 2, 3

b1850 b55§C

VIH Input HIGH Voltage b1165 b870 mV b55§C to Guaranteed HIGH Signal 1, 2, 3, 4

a125§C for All Inputs

VIL Input LOW Voltage b1830 b1475 mV b55§C to Guaranteed LOW Signal 1, 2, 3, 4

a125§C for All Inputs

IIL Input LOW Current 0.50 mAb55§Cto V

EE eb

4.2V 1, 2, 3

a125§CV

IN eVIL (Min)

IIH Input HIGH Current 240 mA0§Cto V

EE eb

5.7V

a125§CVIN eVIH (Max) 1, 2, 3

340 mAb55§C

IEE Power Supply Current b55§Cto Inputs Open

b195 b65 mA a125§CVEE eb

4.2V to b4.8V 1, 2, 3

b205 b65 VEE eb

4.2V to b5.7V

Note 1: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals b55§C), then testing

immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides ‘‘cold start’’ specs which can be

considered a worst case condition at cold temperatures.

Note 2: Screen tested 100% on each device at b55§C, a25§C, and a125§C, Subgroups 1, 2, 3, 7, and 8.

Note 3: Sample tested (Method 5005, Table I) on each manufactured lot at b55§C, a25§C, and a125§C, Subgroups A1, 2, 3, 7, and 8.

Note 4: Guaranteed by applying specified input condition and testing VOH/VOL.

Military Version (Continued)

AC Electrical Characteristics

VEE eb

4.2V to b5.7V, VCC eVCCA eGND

Symbol Parameter TCeb

55§CT

25§CT

125§CUnits Conditions Notes

Min Max Min Max Min Max

tPLH Propagation Delay 0.50 2.60 0.70 2.60 0.70 3.10 ns

Figures 1, 2

1, 2, 3, 5

tPHL Dnto Output

tPLH Propagation Delay 0.80 3.30 1.00 3.30 1.10 3.80 ns

Figures 1, 4

1, 2, 3, 5

tPHL LE,Eto Output

tPZH Propagation Delay 1.00 4.60 1.10 4.20 1.20 4.40 ns

Figures 1, 2

1, 2, 3, 5

tPHZ OEN to Output 0.70 3.00 0.70 2.80 0.70 3.20

tTLH Transition Time 0.40 2.50 0.40 2.40 0.40 2.70 ns

Figures 1, 3

tTHL 20% to 80%, 80% to 20%

tsSetup Time

D0–D71.50 1.50 1.70 ns

Figures 1, 3

thHold Time

D0–D70.60 0.60 0.60 ns

Figures 1, 3

tpw(H) Pulse Width HIGH

LE,E 2.40 2.40 2.40 ns

Figures 1, 3

Note 1: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals b55§C), then testing

immediately after power-up. This provides ‘‘cold start’’ specs which can be considered a worst case condition at cold temperatures.

Note 2: Screen tested 100% on each device at a25§C temperature only, Subgroup A9.

Note 3: Sample tested (Method 5005, Table I) on each manufactured lot at a25§C, Subgroup A9, and at a125§C and b55§C temperatures, Subgroups A10 and

A11.

Note 4: Not tested at a25§C, a125§C, and b55§C temperature (design characterization data).

Note 5: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching.

Test Circuitry

TL/F/9883–6

Notes: FIGURE 1. AC Test Circuit

VCC,V

CCA ea

2V, VEE eb

2.5V

L1 and L2 eequal length 50Ximpedance lines

RTe50Xterminator internal to scope

Decoupling 0.1 mF from GND to VCC and VEE

All unused outputs are loaded with 25Xto GND

CLeFixture and stray capacitance s3pF

Switching Waveforms

TL/F/9883–7

FIGURE 2. Propagation Delay and Cutoff Times

TL/F/9883–8

FIGURE 3. Setup, Hold and Pulse Width Times

TL/F/9883–9

FIGURE 4. Propagation Delay LE,Eto Q

Ordering Information

The device number is used to form part of a simplified purchasing code where a package type and temperature range are

defined as follows:

100344 D C QB

Device Type (Basic) Special Variation

QB eMilitary grade device with

Package Code environmental and burn-in

DeCeramic DIP processing

FeQuad Cerpak

PePlastic DIP Temperature Range

QePlastic Leaded Chip Carrier (PCC) C eCommercial (0§Ctoa

85§C)

MeMilitary (b55§Ctoa

125§C)

Physical Dimensions inches (millimeters)

24-Lead Ceramic Dual-In-Line Package (0.400×Wide) (D)

NS Package Number J24E

Physical Dimensions inches (millimeters) (Continued)

24-Lead Plastic Dual-In-Line Package (P)

NS Package Number N24E

28-Lead Plastic Chip Carrier (Q)

NS Package Number V28A

---OVERFLOWDATATHISPAGE---

100344 Low Power 8-Bit Latch with Cut-Off Drivers

Physical Dimensions inches (millimeters) (Continued) Lit. Ý114917

24-Lead Quad Cerpak (F)

NS Package Number W24B

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failure to perform, when properly used in accordance support device or system, or to affect its safety or

with instructions for use provided in the labeling, can effectiveness.

be reasonably expected to result in a significant injury

to the user.

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