PM3351 ELAN 1X100
DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INT ERNAL USE 125
15. When the frame data has been completely read into the transmit FIFO by the
destination ELAN 1x100, the DMA Controller will automatically send an
acknowledge back to the source device, notifying it that the data copy is
complete and the memory resources used in the source device may be freed.
This is done by initiating a single-word PCI write transaction to the proper
acknowledge counter in the source device; in a manner identical to request
counters, the acknowledge counter in the source device will automatically
increment when a write is performed to its assigned PCI address. Once the
acknowledge counter in the source has been incremented, the transfer
handshake is complete; the destination and source devices will autonomously
perform the necessary final processing required to transmit the frame and free
the resources, respectively.
16. The acknowledge counter increment performed by the DMA Controller in the
destination device to the source device in the preceding step will generate an
acknowledge counter interrupt
to the Switch Processor in the source device.
The Switch Processor will then execute the acknowledge counter interrupt
service routine, which will first verify that the ackno wledge notif ication was valid
(i.e., at least one frame was queued for transfer to the destination device
making the n otificat ion). If the acknowledge was expected, the firmware will then
remove the entry at the head of the transfer ring for the destination device,
updating the corresponding expansion port descriptor device accordingly.
If the transfer ring entry indicates a unicast frame, the packet buffer chain for the
frame is immediately freed (returned to the free packet buffer pool); if a
multicast or broadcast is indicated, then the reference count field (RefCount) in
the last packet buffer is decremented first, and the packet buffer chain is only
freed if the reference count goes to zero. If the packet buffer chain is freed, the
MaxBuffers field in the original source local port descriptor is incremented by the
count of buffers freed, to permit the free buffers to be re-used for future received
traffic. The firmware also notifies the DMA Controller that an entry in the
transmit ring has been freed; the DMA Controller adjusts its internal pointer
registers to take this into account.
17. The DMA Controller constantly reads data out of the head of the transmit FIFO
and passes them to the MAC logic for transmission on the medium. When the
frame that was transferred in steps 11 through 15 reaches the head of the
transmit FIFO, then it will check the disposition FIFO entry for that f rame. If the
FIFO entry indicates a send code, the DMA Controller will read the frame data
out of the transmit FIFO and present them to the MAC logic. The MAC logic will
initiate frame transmission over the medium according to the IEEE 802.3u
specification, beginning with the preamble and SFD and ending with the 4-byte
CRC field. The MAC logic is completely responsible for inserting any required
interframe gap, counting off backoff intervals for half-duplex, and regulating the
data rate; the DMA Controller simply reads data out of the transmit FIFO and