IN
up to 600 V
TO
LOAD
VCC VB
VS
HO
LO
COM
IN
DT
VSS
SD
VCC
SD
VSS RDT
VCC VB
VS
HO
LOCOM
IN
SD
SD
IN
up to 600 V
TO
LOAD
VCC
IRS2184/IRS21844(S)PbF
Typical Connection
HALF-BRIDGE DRIVER
Features
·Floating channel designed for bootstrap operation
·Fully operational to +600 V
·Tolerant to negative transient voltage, dV/dt immune
·Gate drive supply range from 10 V to 20 V
·Undervoltage lockout for both channels
·3.3 V and 5 V input logic compatible
·Matched propagation delay for both channels
·Logic and power ground +/- 5 V offset
·Lower di/dt gate driver for better noise immunity
·Output source/sink current capability 1.4 A/1.8 A
·RoHS compliant
IRS21844
IRS2184
www.irf.com 1
Data Sheet No. PD60252 revA
(Refer to Lead Assignments for correct
configuration).These diagrams show
electrical connections only. Please refer
to our Application Notes and DesignTips
for proper circuit board layout.
Description
The IRS2184/IRS21844 are high volt-
age, high speed power MOSFET and
IGBT drivers with dependent high- and
low-side referenced output channels.
Proprietary HVIC and latch immune
CMOS technologies enable ruggedized
monolithic construction. The logic in-
put is compatible with standard CMOS
or LSTTL output, down to 3.3 V logic. The
output drivers feature a high pulse cur-
rent buffer stage designed for minimum driver cross-conduction. The floating channel can be used to drive an
N-channel power MOSFET or IGBT in the high-side configuration which operates up to 600 V.
Packages
8-Lead PDIP
IRS2184
8-Lead SOIC
IRS2184S
14-Lead PDIP
IRS21844
14-Lead SOIC
IRS21844S
Feature Comparison
Part Input
logic
Cross-
conduction
prevention
logic
Deadtime
(ns) Ground Pins ton/toff
(ns)
2181 COM
21814 HIN/LIN no none VSS/COM 180/220
2183 Internal 400 COM
21834 HIN/LIN yes Program 400-5000 VSS/COM 180/220
2184 Internal 400 COM
21844 IN/SD yes Program 400-5000 VSS/COM 680/270
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Symbol Definition Min. Max. Units
VBHigh-side floating absolute voltage -0.3 620 (Note 1)
VSHigh-side floating supply offset voltage VB - 20 VB + 0.3
VHO High-side floating output voltage VS - 0.3 VB + 0.3
VCC Low-side and logic fixed supply voltage -0.3 20 (Note 1)
VLO Low-side output voltage -0.3 VCC + 0.3
DT Programmable dead-time pin voltage (IRS21844 only) VSS - 0.3 VCC + 0.3
VIN Logic input voltage (IN & SD) VSS - 0.3 VCC + 0.3
VSS Logic ground (IRS21844 only) VCC - 20 VCC + 0.3
dVS/dt Allowable offset supply voltage transient — 50 V/ns
(8-lead PDIP) — 1.0
PDPackage power dissipation @ TA £ +25 °C(8-lead SOIC) — 0.625
(14-lead PDIP) — 1.6
(14-lead SOIC) — 1.0
(8-lead PDIP) — 125
RthJAThermal resistance, junction to ambient (8-lead SOIC) — 200
(14-lead PDIP) — 75
(14-lead SOIC) — 120
TJJunction temperature — 150
TSStorage temperature -50 150
TLLead temperature (soldering, 10 seconds) — 300
V
°C/W
W
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters
are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board
mounted and still air conditions.
Note 1: All supplies are fully tested at 25 V and an internal 20 V clamp exists for each supply.
°C
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IRS2184/IRS21844(S)PbF
Note 2: Logic operational for VS of -5 V to +600 V. Logic state held for VS of -5 V to -VBS. (Please refer to the Design
Tip DT97-3 for more details).
Note 3: Operational for transient negative VS of COM - 50 V with a 50 ns pulse width. Guaranteed by design. Refer to
the Application Information section of this datasheet for more details.
Recommended Operating Conditions
The input/output logic timing diagram is shown in Fig. 1. For proper operation the device should be used within the
recommended conditions. The VS and VSS offset rating are tested with all supplies biased at a 15 V differential.
VBHigh-side floating supply absolute voltage VS + 10 VS + 20
VSHigh-side floating supply offset voltage COM -8 (Note 2) 600
VSt Transient high-side floating supply offset voltage -50 (Note 3) 600
VHO High-side floating output voltage VSVB
VCC Low-side and logic fixed supply voltage 10 20
VLO Low-side output voltage 0 VCC
VIN Logic input voltage (IN & SD) VSS VCC
DT Programmable deadtime pin voltage (IRS21844 only) VSS VCC
VSS Logic ground (IRS21844 only) -5 5
TAAmbient temperature -40 125 °C
V
Symbol Definition Min. Max. Units
Dynamic Electrical Characteristics
VBIAS (VCC, VBS) = 15 V, VSS = COM, CL = 1000 pF, TA = 25° C, DT = VSS unless otherwise specified.
Symbol Definition Min. Typ. Max.UnitsTest Conditions
ton Turn-on propagation delay — 680 900 VS = 0 V
toff Turn-off propagation delay — 270 400 VS = 0 V or 600 V
tsd Shut-down propagation delay —180 270
MTon Delay matching, HS & LS turn-on — 0 90
MToff Delay matching, HS & LS turn-off — 0 40
trTurn-on rise time — 40 60
tfTurn-off fall time — 20 35
DT Deadtime: LO turn-off to HO turn-on(DTLO-HO) & 280 400 520 RDT= 0 W
HO turn-off to LO turn-on (DTHO-LO) 4 5 6 ms RDT = 200 kW
MDT Deadtime matching = DTLO - HO - DTHO-LO
— 0 50 RDT=0 W
— 0 600 RDT = 200 kW
ns
ns
VS = 0 V
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Static Electrical Characteristics
VBIAS (VCC, VBS) = 15 V, VSS = COM, DT= VSS and TA = 25 °C unless otherwise specified. The VIL, VIH, and IIN
parameters are referenced to VSS /COM and are applicable to the respective input leads: IN and SD. The VO, IO, and
Ron parameters are referenced to COM and are applicable to the respective output leads: HO and LO.
Symbol Definition Min. Typ.Max.UnitsTest Conditions
VIH Logic “1” input voltage for HO & logic “0” for LO 2.5 — —
VIL Logic “0” input voltage for HO & logic “1” for LO — — 0.8
VSD,TH+ SD input positive going threshold 2.5 — —
VSD,TH- SD input negative going threshold — — 0.8
VOH High level output voltage, VBIAS - VO— — 1.4 IO = 0 A
VOL Low level output voltage, VO— — 0.2 IO = 20 mA
ILK Offset supply leakage current — — 50 VB = VS = 600 V
IQBS Quiescent VBS supply current 20 60 150
IQCC Quiescent VCC supply current 0.4 1.0 1.6 mA
IIN+ Logic “1” input bias current — 25 60 IN = 5 V, SD = 0 V
IIN- Logic “0” input bias current — — 5.0 IN = 0 V, SD = 5 V
VCCUV+ VCC and VBS supply undervoltage positive going 8.0 8.9 9.8
VBSUV+ threshold
VCCUV- VCC and VBS supply undervoltage negative going 7.4 8.2 9.0
VBSUV- threshold
VCCUVH Hysteresis 0.3 0.7 —
VBSUVH
IO+ Output high short circuit pulsed current 1.4 1.9 — VO = 0 V,
PW £ 10 µs
IO- Output low short circuit pulsed current 1.8 2.3 — VO = 15 V,
PW £ 10 µs
V
µA
µA
V
VCC = 10 V to 20 V
VIN = 0 V or 5 V
A
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IRS2184/IRS21844(S)PbF
Functional Block Diagrams
2184
SD
UV
DETECT
DELAY
IN VS
HO
VB
PULSE
FILTER
HV
LEVEL
SHIFTER
R
R
S
Q
UV
DETECT
PULSE
GENERATOR
VSS/COM
LEVEL
SHIFT
VSS/COM
LEVEL
SHIFT
+5V
DEADTIME
COM
LO
VCC
21844
SD
UV
DETECT
DELAY
IN
DT
VSS
VS
HO
VB
PULSE
FILTER
HV
LEVEL
SHIFTER
R
R
S
Q
UV
DETECT
PULSE
GENERATOR
VSS/COM
LEVEL
SHIFT
VSS/COM
LEVEL
SHIFT
+5V
DEADTIME
COM
LO
VCC
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14-Lead PDIP 14-Lead SOIC
IRS21844PbF IRS21844SPbF
Lead Assignments
8-Lead PDIP 8-Lead SOIC
Lead Definitions
SymbolDescription
IN Logic input for high-side and low-side gate driver outputs (HO and LO), in phase with HO
(referenced to COM for IRS2184 and VSS for IRS21844)
SD Logic input for shutdown (referenced to COM for IRS2184 and VSS for IRS21844)
DT Programmable deadtime lead, referenced to VSS. (IRS21844 only)
VSS Logic ground (IRS21844 only)
VBHigh-side floating supply
HO High-side gate drive output
VSHigh-side floating supply return
VCC Low-side and logic fixed supply
LO Low-side gate drive output
COM Low-side return
IRS2184PbF IRS2184SPbF
1
2
3
4
8
7
6
5
IN
SD
COM
LO
VB
HO
VS
VCC
1
2
3
4
8
7
6
5
IN
SD
COM
LO
VB
HO
VS
VCC
1
2
3
4
5
6
7
14
13
12
11
10
9
8
IN
SD
VSS
DT
COM
LO
VCC
VB
HO
VS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
IN
SD
VSS
DT
COM
LO
VCC
VB
HO
VS
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IRS2184/IRS21844(S)PbF
Figure 1. Input/Output Timing Diagram Figure 2. Switching Time Waveform Definitions
SD
IN
HO
LO
IN(HO)
tr
ton tf
toff
LO
HO
50% 50%
90% 90%
10% 10%
IN(LO)
Figure 5. Delay Matching Waveform Definitions
HO
50% 50%
10%
LO
90%
MT
HOLO
MT
IN(LO)
IN (HO)
Figure 3. Shutdown Waveform Definitions
SD
tsd
HO
LO
50%
90%
Figure 4. Deadtime Waveform Definitions
IN
HO
50% 50%
90%
10%
LO 90%
10%
DTLO-HO
DTLO-HO
MDT= - DTHO-LO
DTHO-LO
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Q1
ON
D2
VS1
Q2
OFF
IU
DC+ BUS
DC-BUS
DC+ BUS
Q1
OFF
D1
D2
DC-BUS
VS1
Q2
OFF
IU
Figure 7: Q1 conducting Figure 8: D2 conducting
Also when the phase current flows from the load back to the inverter (see Figures 9 and 10), and Q4
switches on, the current commutation occurs from D3 to Q4. At the same instance, the voltage node, VS2,
swings from the positive DC bus voltage to the negative DC bus voltage.
Tolerant to Negative VS Transients
A common problem in today’s high-power switching converters is the transient response of the switch
node’s voltage as the power switches transition on and off quickly while carrying a large current. A typical
half bridge circuit is shown in Figure 6; here we define the power switches and diodes of the inverter.
If the high-side switch (e.g., Q1 in Figures 7 and 8) switches off, while the phase current is flowing to a
load, a current commutation occurs from high-side switch (Q1) to the diode (D2) in parallel with the low-
side switch of the same inverter leg. At the same instance, the voltage node VS1, swings from the positive
DC bus voltage to the negative DC bus voltage.
Q1
Q2
D1
D2
VS
DC+ BUS
DC-BUS
Input
Voltage
To
Load
Figure 6: Half Bridge Circuit
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IRS2184/IRS21844(S)PbF
The circuit shown in Figure 11 depicts a half bridge circuit with parasitic elements shown; Figures 12 and 13
show a simplified illustration of the commutation of the current between Q1 and D2. The parasitic
inductances in the power circuit from the die bonding to the PCB tracks are lumped together in LC and LE
for each switch. When the high-side switch is on, VS1 is below the DC+ voltage by the voltage drops
associated with the power switch and the parasitic elements of the circuit. When the high-side power
switch turns off, the load current can momentarily flow in the low-side freewheeling diode due to the
inductive load connected to VS1, for instance (the load is not shown in these figures). This current flows
from the DC- bus (which is connected to the COM pin of the HVIC) to the load and a negative voltage
between VS1 and the DC- Bus is induced (i.e., the COM pin of the HVIC is at a higher potential than the VS
pin).
In a typical power circuit, dV/dt is typically designed to be in the range of 1-5 V/ns. The negative V
S
transient voltage can exceed this range during some events such as short circuit and over-current
shutdown, when di/dt is greater than in normal operation.
International Rectifier’s HVICs have been designed for the robustness required in many of today’s
demanding applications. An indication of the IRS2184(4)’s robustness can be seen in Figure 14, where there
is represented the IRS2184(4) Safe Operating Area at VBS=15V based on repetitive negative VS spikes. A
negative VS transient voltage falling in the grey area (outside SOA) may lead to IC permanent damage;
viceversa unwanted functional anomalies or permanent damage to the IC do not appear if negative Vs
transients fall inside SOA.
Figure 9: Parasitic Elements
Figure 10: Vs
positive Figure 11: Vs
negative
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DC+ BUS
D1
D2
DC-BUS
VS1
Q1
Q2
LC1
LE1
LC2
LE2
DC+ BUS
DC-BUS
Q1
ON
D2
Q2
OFF
VS1
VLC1
+
-
VLE1
+
-IU
DC+ BUS
Q1
OFF
D1
DC-BUS
Q2
OFF
VS1 VLC2
-
+
VLE2
-
+
IU
VD2
-
+
IRS2184/IRS21844(S)PbF
www.irf.com 10
Even though the IRS2184(4) has been shown able to handle these large negative VS transient conditions, it
is highly recommended that the circuit designer always limit the negative VS transients as much as possible
by careful PCB layout and component use.
Figure 12: Negative V
S
transient SOA for IRS2184 @ VBS=15V
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IRS2184/IRS21844(S)PbF
400
600
800
1000
1200
1400
10 12 14 16 18 20
Supply Voltage (V)
Turn-on P ropagation D el ay (ns)
Typ.
Max.
100
200
300
400
500
600
700
-50 -25 0 25 50 75 100 125
Temperature (oC)
Turn-off Propagation Delay (ns)
Typ.
Max.
100
200
300
400
500
600
700
10 12 14 16 18 20
Supply Voltage (V)
Turn-of f Pr opagati on Delay (ns)
Typ.
Max.
0
100
200
300
400
500
-50 -25 0 25 50 75 100 125
Temperature (oC)
SD Propagation Delay (ns)
Typ.
Max.
Figure 13A. Turn-On Propagation Delay Time
vs. Temperature
Figure 13B. Turn-On Propagation Delay Time
vs. Supply Voltage
Figure 14A. Turn-Off Propagation Delay Time
vs. Temperature
Figure 14B. Turn-Off Propagation Delay Time
vs. Supply Voltage
)
)
)
)
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0
100
200
300
400
500
-50 -25 0 25 50 75 100 125
Temperature (oC)
Typ.
Max.
0
100
200
300
400
500
10 12 14 16 18 20
Supply Voltage (V)
Max.
Typ.
0
20
40
60
80
100
120
-50 -25 0 25 50 75 100 125
Temperature (oC)
Typ.
Max
0
20
40
60
80
100
120
10 12 14 16 18 20
Supply Voltage (V)
Typ.
Max.
SD Propagation Delay (ns)
SD Propagation Delay (ns)
Turn-On Rise Time (ns)
Turn-On Rise Time (ns)
Figure 15A. SD Propagation Delay
vs. Temperature
Figure 15B. SD Propagation Delay
vs. Supply Voltage
Figure 16A. Turn on Rise Time
vs. Temperature
Figure 16B. Turn on Rise Time
vs. Supply Voltage
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IRS2184/IRS21844(S)PbF
0
20
40
60
80
-50 -25 0 25 50 75 100 125
Temperature (oC)
Turn-off Fall Time (n
Typ
Max.
0
20
40
60
80
10 12 14 16 18 20
Supply Voltage (V)
Turn-off Fall Time (ns)
Typ.
Max.
100
300
500
700
900
1100
10 12 14 16 18 20
Supply Voltage (V)
Deadtim e (ns)
Typ.
Max.
Min.
Figure 17A. Turn-Off Fall Time
vs. Temperature
Figure 17B. Turn-Off Fall Time
vs. Supply Voltage
Figure 18A. Deadtime
vs. Temperature
Figure 18B. Deadtime
vs. Supply Voltage
100
300
500
700
900
1100
-50 -25 0 25 50 75 100 125
Temperature (oC)
Deadtim e (ns)
Min.
Typ.
Max.
)
)
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s)
IRS2184/IRS21844(S)PbF
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0
1
2
3
4
5
6
7
050 100 150 200
RDT (KW)
Deadtime (
m
s)
Typ.
Max.
Min.
0
1
2
3
4
5
6
-50 -25 0 25 50 75 100 125
Temperature (oC)
Logic "0" Input Voltage
Max.
0
1
2
3
4
5
6
-50 -25 0 25 50 75 100 125
Temperature (oC)
Input Voltage (V)
Min.
0
1
2
3
4
5
6
10 12 14 16 18 20
VBAIS Supply Voltage (V)
Input Voltage (V)
Max.
Figure 18C. Deadtime
vs. RDT
Figure 19A. Logic “1” Input Voltage
vs. Temperature
Figure 19B. Logic “1” Input Voltage
vs. Supply Voltage
Figure 20A. Logic “0” Input Voltage
vs. Temperature
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IRS2184/IRS21844(S)PbF
0
1
2
3
4
5
6
10 12 14 16 18 20
Supply Voltage (V)
Logic "0" Input V ol tage (V)
Max.
0
1
2
3
4
5
-50 -25 0 25 50 75 100 125
Temperature (oC)
SD Input Negative Going Threshold
Max.
Max.
1
2
3
4
5
6
10 12 14 16 18 20
VCC Supply Voltage (V)
SD I nput threshold (+) (V)
Max.
1
2
3
4
5
6
-50 -25 0 25 50 75 100 125
Temperature (oC)
SD Input threshold (+) (V)
Figure 20B. Logic “0” Input Voltage
vs. Supply Voltage
Figure 21A. SD Input Positive Going Threshold (+)
vs. Temperature
Figure 22A. SD Input Negative Going Threshold
vs. Temperature
Figure 21B. SD Input Positive Going Threshold (+)
vs. Supply Voltage
))
)
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0
1
2
3
4
5
10 12 14 16 18 20
Supply Voltage (V)
SD Input Negative Going Threshold
Max.
0.0
0.1
0.2
0.3
0.4
0.5
-50 -25 0 25 50 75 100 125
Temperature (oC)
Low Level Output (V)
Max.
Max.
0.0
1.0
2.0
3.0
4.0
5.0
-50 -25 0 25 50 75 100 125
Temperature (oC)
High L evel Output Voltage (V)
Max
0.0
1.0
2.0
3.0
4.0
5.0
10 12 14 16 18 20
High L evel Output Vol tage (V)
Figure 23A. High Level Output Voltage
vs. Temperature (Io = 0 mA)
Figure 23B. High Level Output Voltage
vs. Supply Voltage (Io = 0 mA)
VBIAS Supply Voltage (V)
Figure 22B. SD Input Negative Going Threshold
vs. Supply Voltage
Figure 24A. Low Level Output
vs. Temperature
)
)
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IRS2184/IRS21844(S)PbF
0
100
200
300
400
500
-50 -25 0 25 50 75 100 125
Temperature (oC)
Offset Supply Leakage Current (
m
A)
Max.
0
100
200
300
400
500
100 200 300 400 500 600
VB Boost Voltage (V)
Offset Supply Leakage Current (
m
A)
Max.
0
50
100
150
200
250
-50 -25 0 25 50 75 100 125
Temperature (oC)
VBS Supply Current (
m
A)
Min.
Typ.
Max.
0.0
0.1
0.2
0.3
0.4
0.5
10 12 14 16 18 20
Supply Voltage (V)
Low Level Output (V)
Max.
Figure 25A. Offset Supply Leakage Current
vs. Temperature
Figure 24B. Low Level Output
vs. Supply Voltage
Figure 26A. V
BS Supply Current
vs. Temperature
Figure 25B. Offset Supply Leakage Current
vs. VB
Boost Voltage
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0
50
100
150
200
250
10 12 14 16 18 20
VBS Floating Supply Voltage (V)
VBS Supply Current (
m
A)
Typ.
Max.
Min.
0
1
2
3
4
5
-50 -25 0 25 50 75 100 125
Temperature (oC)
VCC
Supply Current (mA)
Min.
Typ.
Max.
0
1
2
3
4
5
10 12 14 16 18 20
VCC Supply Voltage (V)
VCC
Supply Current (mA)
Typ.
Max.
Min
0
20
40
60
80
100
120
-50 -25 0 25 50 75 100 125
Temperature (oC)
Logic "1" Input Bias Current (
m
A)
Typ.
Max.
Figure 27A. V
CC Supply Current
vs. Temperature
Figure 26B. V
BS Supply Current
vs. V
BS Supply Voltage
Figure 28A. Logic “1” Input Bias Current
vs. Temperature
Figure 27B. V
CC Supply Current
vs. VCC Supply Voltage
)
)
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IRS2184/IRS21844(S)PbF
0
20
40
60
80
100
120
10 12 14 16 18 20
Supply Voltage (V)
Logic "1" Input Bias Current (
m
A)
Typ.
Max.
6
7
8
9
10
11
12
-50 -25 0 25 50 75 100 125
Temperature (oC)
VCC and VBS
UV T hreshold (+) (V)
Min.
Typ.
Max.
Max
0
1
2
3
4
5
6
-50 -25 0 25 50 75 100 125
Temperature (°C)
Logic "0" Input Bias Current (µA)
Max
0
1
2
3
4
5
6
10 12 14 16 18 20
Supply Voltage (V)
Logic "0" Input Bias Current (µA)
Figure 20B. Logic "0" Input Bias Current
Figure 29A. Logic “0” Input Bias Current
vs. Temperature
Figure 28B. Logic “1” Input Bias Current
vs. Supply Voltage
Figure 30. V
CC and VBS Undervoltage Threshold (+)
vs. Temperature
Figure 29B. Logic “0” Input Bias Current
vs. Supply Voltage
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6
7
8
9
10
11
12
-50 -25 0 25 50 75 100 125
Temperature (oC)
VCC and VBS UVThreshold (-) (V)
Min.
Typ.
Max.
0
1
2
3
4
5
-50 -25 0 25 50 75 100 125
Temperature (oC)
Output Source Current (A)
Min.
Typ.
0
1
2
3
4
5
10 12 14 16 18 20
Supply Voltage (V)
Output Source Current (A)
Typ.
Min. 1.0
2.0
3.0
4.0
5.0
-50 -25 0 25 50 75 100 125
Temperature (oC)
Output Sink Current (A)
Min.
Typ.
Figure 32A. Output Source Current
vs. Temperature
Figure 31. V
CC and VBS Undervoltage Threshold (-)
vs. Temperature
Figure 33A. Output Sink Current
vs. Temperature
Figure 32B. Output Source Current
vs. Supply Voltage
)
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IRS2184/IRS21844(S)PbF
0
1
2
3
4
5
10 12 14 16 18 20
Supply Voltage (V)
Output Sink Current (A)
Typ.
Min.
20
40
60
80
100
120
140
110 100 1000
Frequency (kHz)
Temprature (
oC)
140v
70v
0v
140v
70v
0v
20
40
60
80
100
120
140
1 10 100 1000
Frequency (kHz)
Temperature (
oC)
140v
70v
0v
20
1 10 100 1000
Frequency (kHz)
20
40
60
80
100
120
140
Temperature (
oC)
Figure 34. IRS2184 vs. Frequency (IRFBC20),
Rgate = 33W, Vcc = 15V
Figure 33B. Output Sink Current
vs. Supply Voltage
Figure 35. IRS2184 vs. Frequency (IRFBC30),
Rgate = 22W, Vcc = 15V
Figure 36. IRS2184 vs. Frequency (IRFBC40),
Rgate = 15W, Vcc = 15V
)
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IRS2184/IRS21844(S)PbF
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20
40
60
80
100
120
140
1 10 100 1000
Frequency (kHz)
Temperature (
oC)
70v
0v
140v
20
40
60
80
100
120
140
1 10 100 1000
Frequency (kHz)
Temperature (
oC)
140v
70v
0v
20
40
60
80
100
120
140
1 10 100 1000
Frequency (kHz)
Temperature (
oC)
140v
70v
0v
20
40
60
80
100
120
140
1 10 100 1000
Frequency (kHz)
Temperature (
oC)
140v
70v
0v
Figure 37. IRS2184 vs. Frequency (IRFBC50),
Rgate = 10W, Vcc = 15V
Figure 38. IRS21844 vs. Frequency (IRFBC20),
Rgate = 33W, Vcc = 15V
Figure 39. IRS21844 vs. Frequency (IRFBC30),
Rgate = 22W, Vcc = 15V
Figure 40. IRS21844 vs. Frequency (IRFBC40),
Rgate = 15W, Vcc = 15V
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IRS2184/IRS21844(S)PbF
20
40
60
80
100
120
140
1 10 100 1000
Frequency (kHz)
Temperature (
oC)
70v
0v
140v
20
40
60
80
100
120
140
110 100 1000
Frequency (kHz)
Temperature (
oC)
140v
70v
0v
20
40
60
80
100
120
140
1 10 100 1000
Frequency (kHz)
Temperature (
oC)
140v
70v
0v
20
40
60
80
100
120
140
1 10 100 1000
Frequency (kHz)
Temperature (
oC)
0v
140v 70v
Figure 41. IRS21844 vs. Frequency (IRFBC50),
Rgate = 10W, Vcc = 15V
Figure 42. IRS2184s vs. Frequency (IRFBC20),
Rgate = 33W, Vcc = 15V
Figure 43. IRS2184s vs. Frequency (IRFBC30),
Rgate = 22W, Vcc = 15V
Figure 44. IRS2184s vs. Frequency (IRFBC40),
Rgate = 15W, Vcc = 15V
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IRS2184/IRS21844(S)PbF
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20
40
60
80
100
120
140
1 10 100 1000
Frequency (kHz)
Tempreture (
o
C)
140V 70V 0V
20
40
60
80
100
120
140
1 10 100 1000
Frequency (kHz)
Temperature (
oC)
140v
70v
0v
20
40
60
80
100
120
140
110 100 1000
Frequency (kHz)
140v
70v
0v
20
40
60
80
100
120
140
110 100 1000
Frequency (kHz)
Temperature (
oC)
140v
70v
0v
Figure 45. IRS2184s vs. Frequency (IRFBC50),
Rgate = 10W, Vcc = 15V
Figure 46. IRS21844s vs. Frequency (IRFBC20),
Rgate = 33W, Vcc = 15V
Figure 47. IRS21844s vs. Frequency (IRFBC30),
Rgate = 22W, Vcc = 15V
Figure 48. IRS21844s vs. Frequency (IRFBC40),
Rgate = 15W, Vcc = 15V
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IRS2184/IRS21844(S)PbF
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01-6014
01-3003 01 (MS-001AB)
8-Lead PDIP
01-6027
01-0021 11 (MS-012AA)
8-Lead SOIC
8 7
5
6 5
D B
E
A
e
6X
H
0.25 [.010] A
6
431 2
4. OUTLINE CONFORMS TO JEDEC OUTLINE MS-012AA.
NOTES:
1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994.
2. CONTROLLING DIMENSION: MILLIMETER
3. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES].
7
K x 45°
8X L 8X c
y
FOOTPRINT
8X 0.72 [.028]
6.46 [.255]
3X 1.27 [.050] 8X 1.78 [.070]
4. OUTLINE CONFORMS TO JEDEC OUTLINE MS-012AA.
5 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
6 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
MOLD PROTRUSIONS NOT TO EXCEED 0.25 [.010].
7 DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO
A SUBSTRATE.
MOLD PROTRUSIONS NOT TO EXCEED 0.15 [.006].
0.25 [.010] CAB
e1 A
A1
8X b
C
0.10 [.004]
e1
D
E
y
b
A
A1
H
K
L
.189
.1497
0°
.013
.050 BASIC
.0532
.0040
.2284
.0099
.016
.1968
.1574
8°
.020
.0688
.0098
.2440
.0196
.050
4.80
3.80
0.33
1.35
0.10
5.80
0.25
0.40
0°
1.27 BASIC
5.00
4.00
0.51
1.75
0.25
6.20
0.50
1.27
MIN MAX MILLIMETERSINCHES MIN MAX
DIM
8°
e
c.0075 .0098 0.19 0.25
.025 BASIC 0.635 BASIC
Cast Outlines
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IRS2184/IRS21844(S)PbF
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CARRIER TAPE DIMENSION FOR 8SOICN
Code Min Max Min Max
A7.90 8.10 0.311 0.318
B 3.90 4.10 0.153 0.161
C 11.70 12.30 0.46 0.484
D5.45 5.55 0.214 0.218
E6.30 6.50 0.248 0.255
F5.10 5.30 0.200 0.208
G1.50 n/a 0.059 n/a
H1.50 1.60 0.059 0.062
Metric Imperial
REEL DIMENSIONS FOR 8SOICN
Code Min Max Min Max
A 329.60 330.25 12.976 13.001
B20.95 21.45 0.824 0.844
C 12.80 13.20 0.503 0.519
D1.95 2.45 0.767 0.096
E 98.00 102.00 3.858 4.015
Fn/a 18.40 n/a 0.724
G 14.50 17.10 0.570 0.673
H 12.40 14.40 0.488 0.566
Metric Imperial
E
F
A
C
D
G
A
B
H
NOTE : CONTROLLING
DIMENSION IN MM
LOADED TAPE FEED DIRECTION
A
H
F
E
G
D
B
C
Tape & Reel
8-lead SOIC
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IRS2184/IRS21844(S)PbF
CARRIER TAPE DIMENSION FOR 14SOICN
Code Min Max Min Max
A7.90 8.10 0.311 0.318
B 3.90 4.10 0.153 0.161
C 15.70 16.30 0.618 0.641
D7.40 7.60 0.291 0.299
E6.40 6.60 0.252 0.260
F9.40 9.60 0.370 0.378
G1.50 n/a 0.059 n/a
H1.50 1.60 0.059 0.062
Metric Imperial
REEL DIMENSIONS FOR 14SOICN
Code Min Max Min Max
A 329.60 330.25 12.976 13.001
B20.95 21.45 0.824 0.844
C 12.80 13.20 0.503 0.519
D1.95 2.45 0.767 0.096
E 98.00 102.00 3.858 4.015
Fn/a 22.40 n/a 0.881
G 18.50 21.10 0.728 0.830
H 16.40 18.40 0.645 0.724
Metric Imperial
E
F
A
C
D
G
A
B
H
NOTE : CONTROLLING
DIMENSION IN MM
LOADED TAPE FEED DIRECTION
A
H
F
E
G
D
B
C
Tape & Reel
14-lead SOIC
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IRS2184/IRS21844(S)PbF
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8-Lead PDIP IRS2184PbF 14-Lead PDIP IR2S1844PbF
8-Lead SOIC IRS2184SPbF 14-Lead SOIC IRS21844SPbF
8-Lead SOIC Tape & Reel IRS2184STRPbF 14-Lead SOIC Tape & Reel IRS21844STRPbF
ORDER INFORMATION
LEADFREE PART MARKING INFORMATION
Lead Free Released
Non-Lead Free
Released
Part number
Date code
IRSxxxxx
YWW?
?XXXX
Pin 1
Identifier
IR logo
Lot Code
(Prod mode - 4 digit SPN code)
Assembly site code
Per SCOP 200-002
P
?MARKING CODE
SOIC8 &14 are MSL2 qualified.
This product has been designed and qualified for the industrial level.
Qualification standards can be found at www.irf.com
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
Data and specifications subject to change without notice. 12/1/2006
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