User’s Manual 10.94
Data Communications ICs
High-Level Serial Communication
Controller Extended (HSCX)
SAB 82525; SAB 82526
SAF 82525; SAF 82526
Data Classification
Maximum Ratings
Maximum ratings are absolute ratings; exceeding only one of these values may cause irrevers-
ible damage to the integrated circuit.
Characteristics
The listed characteristics are ensured over the operating range of the integrated circuit. Typical
characteristics specify mean values expected over the production spread. If not otherwise
specified, typical characteristics apply at TA = 25 °C and the given supply vo ltage.
Operating Range
In the operating range the functions given in the circuit description are fulfilled.
For detailed technical information about “Processing Guidelines” and
“Quality Assurance” for ICs, see our “Product Overview”.
SAB 82525; SAF 82525; SAB 82526; SAF 82526
Revision History: 10.94
Previous Releases: 01.92
Page Subjects (changes since la st revi sion)
Update
Published by Siemens AG, Bereich Halbleiter, Marketing-Kommunikation,
Balanstraße 73, D-81541 München
Siemens AG 1994. All Rights Reserved.
As far as pa tents or oth er ri gh ts of th ird partie s are c onc erne d, l ia bil it y i s onl y as su med for c om pon ents , n ot f o
r
applications, processes and circuits implemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics.
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For questions on technology, delivery, and prices please contact the Offices of Semiconductor Group in German
y
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Edition 10.94
This edition was realized using the software system FrameMaker.
General Information
Semic onduct or Grou p 3
Table of Contents Page
1Features..................................................................................................................... 6
1.1 Pin Definitions and Functions ................................................................................... 10
1.2 System Integration.................................................................................................... 17
1.3 Functional Description ..............................................................................................22
2 Operating Modes .....................................................................................................24
2.1 Auto-Mode (MODE: MDS1, MDS0 = 00) ..................................................................24
2.2 Non-Auto Mode (MODE: MDS1, MDS0 = 01) ..........................................................24
2.3 Transpa re nt Mo de 1 (MODE: MDS1, MDS 0, ADM = 101 ) ........ ..... ..... .... .................25
2.4 Transpa re nt Mo de 0 (MODE: MDS1, MDS 0, ADM = 100 ) ........ ..... ..... .... .................25
2.5 Extended Transparent Modes 0; 1 (MODE: MDS1, MDS0 = 11) .............................25
2.6 Receive Data Flow (Summary) .................................................................................26
2.7 Transmit Data Flow ...................................................................................................27
3 Procedural Support (Layer-2 Functions) ..............................................................28
3.1 Full-Duplex LAPB/LAPD Operation ..........................................................................28
3.2 Half-Duplex SDLC-NRM Operation ..........................................................................34
3.3 Error Handling ...........................................................................................................38
4 CPU Interface ..........................................................................................................38
4.1 Register Set.............................................................................................................. 38
4.2 Data Transfer Modes.................................................................................................38
4.3 Interrupt Interface ......................................................................................................39
4.4 DMA Interface........................................................................................................... 43
4.5 FIFO Structure ..........................................................................................................47
5 Serial Interface (Layer-1 Functions) ......................................................................49
5.1 Clock Modes......... ........................ ....................... ....................... ........................ .......49
5.2 Clock Recovery (DPLL) ................ .... ..... ..... ....................... ....................... ................ 57
5.3 Bus Configuration ..................................................................................................... 60
5.4 Data Encoding ..........................................................................................................63
5.5 Modem Control Functions (RTS/CTS, CD) ...............................................................63
6 Special Functions ...................................................................................................65
6.1 Fully Transparent Transmission and Reception .......................................................65
6.2 Cyclic Transmission (Fully Transparent) ...................................................................65
6.3 Continuous Transmission (DMA Mode only) ............................................................66
6.4 Receive Length Check Feature ................................................................................66
6.5 One Bit Insertion ............ .... ........................ ....................... ....................... .................67
6.6 Data Inversion........................................................................................................... 67
General Information
Semic onduct or Grou p 4
Table of Contents Page
6.8 Test Mode .................................................................................................................68
6.7 Special RTS Function ...............................................................................................68
7 Operational Description .........................................................................................69
7.1 RESET...................................................................................................................... 69
7.2 Initialization ...............................................................................................................70
7.3 Operational Phase.................................................................................................... 71
7.4 Data Transmission.................................................................................................... 71
7.5 Data Reception .........................................................................................................75
8 Detailed Register Description................................ ....................... ....................... .. 79
8.1 Register Address Arrangement .................................................................................79
8.2 Register Definitions ...................................................................................................80
9 Electrical Characteristics .....................................................................................108
10 Quartz Specifications ...........................................................................................118
11 Package Outlines ..................................................................................................125
General Information
Semic onduct or Grou p 5
Adva nced CMOS technology
Low power consumption: active 25 mW at 4 MHz
standby 4 mW
General
The SAB 82525 is a High-Level Serial Communication Controller compatible to the SAB 82520
HSCC with extended features and functionality (HSCX).
The SAB 82526 is pin and software compatible to the SAB 82525, realizing one HDLC channel
(channel B).
The HSCX has been designed to implement high-speed communication links using HDLC
protocols and to reduce the hardware and software overhead needed for serial synchronous
communications.
Due to its 8-bi t demultiple xed adaptive b us interface it fits pe rfectly int o every Siemens/Inte l or
Motorola 8- or 16-bit microcontroller or microprocessor system. The data through-put from/to
system memory is optimized transferring blocks of data (usually 32 bytes) by means of DMA
or in terrup t re quest. Togeth er wi th th e stor ing capacity of up to 6 4 byte s in on-ch ip FIFO’ s, t he
serial interfaces are effectively decoupled from the system bus which drastically reduces the
dynamic load and reaction time of the CPU.
The HSCX directly supports the X.25 LAPB, the ISDN LAPD, and SDLC (normal response
mode) protocols and is capable of handling a large set of layer-2 protocol functions
independently from the host processor.
Furthe rmore, the HSCX open s a wide ar ea for applicatio ns which use time di vision mu ltiplex
methods (e.g. time-slot oriented PCM systems, systems designed for packet switching, ISDN
applications) by its prog rammable telecom-specific f eatures .
The HSCX is fabricated using Siemens advanced ACMOS 3 technology and available in a
P-LCC-44 pin package.
The data link controller handles all functions necessary to establish and maintain an HDLC
data link, such as
– Flag insertion and detection,
– Bit stuffing,
– CRC generation a nd che cking,
– Address field recognition.
Associated with each serial channel is a set of independent command and status registers
(SP-REG) and 64-byte deep FIFO’s for transmit and receive direction.
DMA capability has been added to the HSCX by means of a 4-channel DMA interface
(SAB 82525) with one DMA request line for each transmitter and receiver of both channels.
Semic onduct or Grou p 6
82525
82526
82525
82526
SAB
SAB
SAF
SAF
Type Ordering Code Package
SAB 82525 N Q67100-H6486 P-LCC-44-1 (SMD)
SAB 82526 N Q67100-H6512 P-LCC-44-1 (SMD)
SAF 82525 N Q67100-H6504 P-LCC-44-1 (SMD)
SAF 82526 N Q67100-H6511 P-LCC-44-1 (SMD)
SAB 82525 H Q67101-H6482 P-M Q FP-4 4- 2 (SMD)
1Features
Preliminary Data CMOS IC
Two independent full-duplex HDLC channels
(SAB 82526: one channel)
Serial Interface
Different modes of data encoding
Modem control lines (RTS, CTS, CD)
Support of bus configuration by collision resolution
Programmable bit inversion
Transparent receive/transmit of data bytes
without HDLC framing
Continuous transmission of 1 to 32 bytes possible
Data rate up to 4 Mbit/s
On chip clock generation or external clock source
On chip DPLL for clock recovery for each channel
–
–
–
–
Two independent baudrate generators
(SAB 82526: one baudrate generator)
Independent time-slot assignment for each channel
with programma ble time-slot len gth (1-256 bit)
High-Level Serial
Communications Controller Extended
(HSCX)
82525
82526
82525
82526
SAB
SAB
SAF
SAF
10.94
P-LCC-44-1
P-MQFP-44-2
Semic onduct or Grou p 7
82525
82526
82525
82526
SAB
SAB
SAF
SAF
Features (cont’d)
Protocol Support
–
–
–
Auto-mode
Non- auto mode
Transparent mode
Various types of protocol support depending on operating mode
Handling of bit oriented functions in all modes
Support of LAPB/LAPD/SDLC/HDLC protocol in auto-mode (I- and S-frame handling)
Modulo 8 or modulo 128 operation
Programmable time-out and retry conditions
Programmable maximum packet size checking
64 byte FIFO’s per channel and direction
Storage capacity of up to 17 short frames in receive direction
Efficient transfer of data blocks from/to system memory by DMA or interrupt request
8-bit demultip lexed or multiple xed bus interface
Intel or Motorola type µP interface
µP Interface
Semiconductor Grou
p
8
82525
82526
82525
82526
SAB
SAB
SAF
SAF
Pin Configurations
(top view)
18 19 20 21 22 23 24 25 26 27 28
IM1
ALE/IM0
V
A6
A5
A4
A3
A2
A1
A0
INT
29 DACKB
30 DACKA
31 AxCLKB
32 TxCLKB
33 RxCLKB
34 AxCLKA
35 RxCLKA
36 TxCLKA
37 DRQRB
38 DRQTB
39 DRQRA7
8
9
10
11
12
13
14
15
16
17
4041424344123456
RES
RxDB
RTSB
CTSB/CxDB
TxDB
TxDA
CTSA/CxDA
RTSA
RxDA
CS
WR/IC0
RD/IC1
D7
D6
D5
D4
D3
D2
D1
D0
DRQTA
V
DD
ITP00944
SS
HSCX
SAB 82525
SAF 85525
P-LCC-44
18 19 20 21 22 23 24 25 26 27 28
IM1
ALE/IM0
V
A6
A5
A4
A3
A2
A1
A0
INT
29 DACKB
30 N.C.
31 AxCLKB
32 TxCLKB
33 RxCLKB
34 AxCLKA
35 RxCLKA
36 N.C.
37 DRQRB
38 DRQTB
39 N.C.7
8
9
10
11
12
13
14
15
16
17
4041424344123456
RES
RxDB
RTSB
CTSB/CxDB
TxDB
N.C.
N.C.
N.C.
N.C.
CS
WR/IC0
RD/IC1
D7
D6
D5
D4
D3
D2
D1
D0
N.C.
V
DD
ITP00945
SS
HSCX
SAB 82526
SAF 82526
P-LCC-44
1
Semic onduct or Grou p 9
82525
82526
82525
82526
SAB
SAB
SAF
SAF
Pin Configurations
(top view)
22
INT
V
DD
0D
IM
SS
V
0
CS
RxDA
RTSA
CTSA/CxDA
TxDB
CTSB/CxDB
RTSB
RxDB
RES
12 13 14 15 16 17 18 19 20 21
ITP05885
44
2311
43 42 41 40 39 38 37 36 35 34
10 24
925
826
727
628
529
430
331
232
133
DRQRA
DRQTB
DRQRB
TxCLKA
AxCLKA
AxCLKB
DACKA
DACKB
RxCLKA
RxCLKB
DRQTA
D1
D2
D3
D4
D5
D6
D7
1RD/IC ALE/IM
A0
0
1
1A2A3A4A5A6A
TxCLKB
TxDA
WR/IC
HSCX
SAB 82525 H
P-MQFP-44-2
Semic onduct or Grou p 10
82525
82526
82525
82526
SAB
SAB
SAF
SAF
1.1 Pin Definitions and Functions
Pin No. Symbol Input (I)
Output (O) Function
6 RD/IC1 I
7 WR/IC0 IWrite, Intel bus mode
This signal indicates a write operation. When CS is active
the HSCX loads an internal register with data provided via
the data bus. When DACK is active for DMA transfers the
HSCX loads data from the data bus on the top of the
respective transmit FIFO.
Input Control Motorola bus mode
In Motorola bus mode, this pin serves as the R/W input to
distinguish between read or write operations.
42
43
44
1
2
3
4
5
D0
D1
D2
D3
D4
D5
D6
D7
I/O Data Bus
The d ata bus line s are bidir ectional th reestate li nes which
interface with the system’s data bus.
These lines carry data and command/status to and from
the HSCX.
8 CS ICh ip Select
A low s ignal se lects the HSCX for a read/write operation.
Input Control 1, Motorola bus mode IM1 connected to
high.
If Motorola bus mode has been selected this pin serves
either as
E = Enable, active high (IM0 tied to low) or
DS = Data Strobe, active low (IM0 tied to high)
inp ut (d ependi ng o n t he se lect ion vi a I M0) t o co ntro l read /
write operations.
Read, Intel bus mode, IM1 connected to low
This signal indicates a read operation. When the HSCX is
selected via CS the read signal enables the bus drivers to
put data from an internal register addressed via A0-A6 on
the data bus.
When the HSCX is selected for DMA transfers via DACK,
the RD signal enables the bus driver to put data from the
respective receive FIFO on the data bus. Inputs to A0-A6
are ignored.
P-LCC P-MQFP
11
12
3
4
5
6
7
8
9
10
13
Semic onduct or Grou p 11
82525
82526
82525
82526
SAB
SAB
SAF
SAF
Pin Definitions and Functions (cont’d)
Pin No. Symbol Input (I)
Output (O) Function
9
16 RXDA
RXDB IReceive Data (channel A/channel B)
Serial data is received on these pins at standard TTL or
CMOS levels.
10
15 O
11
14
IClea r to Send (cha nnel A/chan nel B)
A low on the CTS inputs enables the respective transmitter.
Additiona l l y, an i nte rr u pt ma y be issued i f a state tr an si tion
occurs at the CTS pin (programmable feature). If no "Clear
To Send" function is required, the CTS inputs can be
connected di r ectly to VSS.
Collision Data (channel A/channel B)
In a bus configuration, the external serial bus must be
connected to the respective C ×D pin for collision
detection.
12
13 TXDA
TXDB OTransmit Data (channel A/channel B)
Tran smit data is shifted out via these pins at standard TTL
or CMOS levels. These pins can be programmed to work
either as push-pull, or open drain outputs supporting bus
configurations.
17 RES IRESET
A high signal on this input forces the HSCX into the reset
state. The HSCX is in power-up mode during reset and in
power-down mode after reset. The minimum pulse width is
1.8 µs.
Request to Send (channel A/channel B)
When the RTS bit in the mode register is set, the RTS
signal goes low. When the RTS is reset, the signal goes
high if the transmitter has finished and there is no further
request for a transmission.
In a bus configuration, this pin can be programmed via
CCR2 to:
stay always high (RTS di sab l ed).
go low during the actual transmission of a frame shifted
by one clock period, excluding collision bits
go low during the reception of a data frame
–
–
–
RTSA
RTSB
CTSA/
CXDA
CTSB/
CXDB
14
21
15
20
16
19
17
18
22
P-LCC P-MQFP
Semic onduct or Grou p 12
82525
82526
82525
82526
SAB
SAB
SAF
SAF
Pin Definitions and Functions (cont’d)
Pin No. Symbol Input (I)
Output (O) Function
18 IM1 IInput Mode 1
Connecting this pin to either VSS or VDD the bus interface can
be adapted to either Siemens/Intel or Motorola
environment.
IM1 = LOW: Intel bus mode
IM1 = HIGH: Motorola bus mode
19 ALE/
IM0 IAddress Latch Enable (Intel bus mode)
A high on this line indicates an address on the external
address/data bus, which will select one of the HSCX’s
intern al registers. The a ddress is latched by t he HSCX with
the fallin g edge of ALE. This allows the HSCX to be directly
connected to a CPU with multiplexed address/data bus
compatible to SAB 82520 HSCC.
The address input pins A0-A6 must be externally
connect ed to the data bus pins (D0-D6 for 8- bit CPU’s, D1-
D7 for 16-bit CPU’s, i.e. multiply all internal register
addresses by 2).
This pin should be connected to high for a de-multiplexed
bus.
Input Mode 0, Motorola bus mode
In Motorola Bus Mode, the level at this pin determines the
function of the IC1 pin (see descrip tion of pin 6) .
20 VSS IGround
27
26
25
24
23
22
21
A0
A1
A2
A3
A4
A5
A6
IAddres s Bus
These inputs interface with seven bits of the system’s
address bus to select one of the internal registers for read
or write.
They are u sually con nect ed a t A 0-A6 in 8-bit syste m s o r at
A1-A7 in 16-bit systems.
23
24
25
32
31
30
29
28
27
26
P-LCC P-MQFP
Semic onduct or Grou p 13
82525
82526
82525
82526
SAB
SAB
SAF
SAF
INT
Pin Definitions and Functions (cont’d)
Pin No. Symbol Input (I)
Output (O) Function
30
29 I
34
31 AxCLK
A
AxCLK
B
I
DMA Acknowledge (channel A/channel B)
When low, t his input signal from the DMA cont roller notifies,
the HSCX, that the requested DMA cycle controlled via
DRQxx (pins 37–40) is in progress, i.e. the DMA controller
has achieved bus mastership from the CPU and will start
data transfer cycles (either read or write).
Together with RD, if DMA has been requested from the
receiver, or with W R, if DMA has been requested from the
transmitter, this input works like CS to enab le a data byte to
be read from or written to the top of the receive or transmit
FIFO of the specified channel.
If DACKn is active , the in put on pin s A 0–A 6 is i gnor ed an d
the FIFOs are implicitly selected.
If the DACKn signals are not used, these pins must be
connected to VDD.
Alternative Clock (channel A/channel B)
These pins realize several input functions. Depending on
the selected clock mode, they may supply either a
This pin can be programmed to functions as receiver
enable if the "auto start" feature is selected (CAS bit in
XBCH set). The state at this pin can be read from VSTR
register,
or a receive strobe signal (clock mode 1)– or a frame synchronization signal in time-slot oriented
oper ation mode (clock mode 5)
–
or, together with RxCLK, a crystal connection for the
internal oscillator (clock mode 4, 6, 7, AxCLK A only).
–
CD (= Carrier Detect) modem control or general purpose
input.
–
DACKA
DACKB
28 oD Interrupt Request
The signal is activated, when the HSCX requests an
interrupt.
The CPU ma y determ ine the par ticular so urce and cause of
the interrupt by reading the HSCX’s interrupt status
registe rs. (ISTA, EXIR).
INT is an open drain output, thus the interrupt requests
outputs of several HSCX’s can be connected to one
interrup t inp ut in a "wired-or" combin ation.
This pin must be connected t o a pull-up resistor.
P-LCC P-MQFP
35
34
39
36
33
Semic onduct or Grou p 14
82525
82526
82525
82526
SAB
SAB
SAF
SAF
Pin Definitions and Functions (cont’d)
Pin No. Symbol Input (I)
Output (O) Function
36
32 TxCLK A
TxCLK B I/O
35
33 RxCLK A
RxCLK B I
39
37 DRQRA
DRQRB O
Transmit Clock (channel A/channel B)
The functions of these pins depend on the programmed
clock mode, provided that the TSS bit in the CCR2 register
is reset. Programmed as inputs (if the TIO bit in CCR2 is
reset), they may supply either
the transmit clock for the respective channel (clock
mode 0, 2, 6),
–
or a transmit strobe signal (clock mode 1).–
Programmed as outputs (if the TIO bit in CCR2 is set), the
TxCLK pins supply either the
transmit clock of the respective channel which is
generated either
–
from t he baudra te gener ator (cl ock mode 2 , 6; TSS bit in
CCR2 set),
or from the DPLL circuit (clock mode 3, 7),
or from the crystal oscillator (clock mode 4)
or a tristate control signal indicating the programmed
transmit time-slot (clock mode 5).
–
Receive Clock (channel A/channel B)
The functions of these pins also depend on the
programmed clock mode. In each channel, RxCLK may
supply either
or a crystal connection for the internal
oscillator (clock mode 4,6,7, RxCLK A/B tog ether
with AxCLK A)
–
or the clock for the baudrate generator (clock mode 2,
3),
–or the receive and transmit clock (clock mode 1, 5)– the receive clock (clock mode 0)–
DMA Request Receiver (channel A/channel B)
The rece iver of th e HSCX r equests a DMA dat a transfe r by
activating this line.
The DRQRn remains high as long as the receive FIFO
requires data transfe rs, thus always blocks of data (32, 16,
8 or 4 bytes) are transferred.
DRQRn is deactivated immediately following the falling
edge of the last read cycle.
41
37
40
38
44
42
P-LCC P-MQFP
Semic onduct or Grou p 15
82525
82526
82525
82526
SAB
SAB
SAF
SAF
Pin Definitions and Functions (cont’d)
Pin No. Symbol Input (I)
Output (O) Function
40
38 DRQTA
DRQTB ODMA Request Transmitter (channel A/channel B)
The tran sm it ter of the H SCX req uest s a DM A d ata transfe r
by activating this line.
The DRQTn remains high as long as the transmit FIFO
requires data transfers.
The amount of data bytes to be transferred from system
memory to the HS CX (= byte co un t) must b e writt en first to
the XBCH, XBCL registers.
Always blocks of data (n x 32 bytes + REST, n = 0, 1,…)
are transferred till the byte count is reached.
DRQTn is deactivated immediately following the falling
edge of the last WR cycle.
41 VDD IPower supply + 5 V.
1
43
2
P-LCC P-MQFP
Semic onduct or Grou p 16
82525
82526
82525
82526
SAB
SAB
SAF
SAF
Figure 1
Block Diagram SAB 82525/SAB 82526
The HSCX SAB 82526 comprises one (channel B), the SAB 82525 two completely
independent full-duplex HDLC channels (channel A and channel B), supporting various layer-1
functions by mean s of internal oscillator, Baud Rate Generator (BRG), Digital Pha se Locked
Loop (DPLL), and Time-Slot Assignment (TSA) circuits.
Further more, la yer-2 funct ions are p erformed by an on- chip LA P (Link Acce ss Procedure , e.g.
LAPB or LAPD) controller.
µP Bus
Interface
SP-REG LAP
Controller
FIFO
Transmit
Receive
FIFO
Data
Link
Controller
TSA
Decoder
Collision
Detection
DPLL
Clock
Controll
DMA
Interface
Channel A
ITB00946
Channel B
A0-A6
D0-D7
RD/IC1
WR/IC0
CS
ALE/IMO
INT
RES
IM1
DRQTA
DRQRA
DACKA
DACKB
DRQRB
DRQTB
BRG
RxDA
TxDA
RTSA
CTSA/
CxDA
TxCLKB
AxCLKB
RxCLKB
TxDB
RTSB
CxDB
RxDB
CTSB/
TxCLKA
AxCLKA
RxCLKA
Semic onduct or Grou p 17
82525
82526
82525
82526
SAB
SAB
SAF
SAF
1.2 System Integration
General Aspects
Figure 2 gives a general overview of the system integration of HSCX.
Figure 2
General System Integration of HSCX
The HSCX bus interface consists of an 8-bit bidirectional data bus (D0–D7), seven address
line inputs (A0–A6), three control inputs (RD/DS, WR/R/W, CS), one interr upt reques t outpu t
(INT) and a 4-chan nel DMA inte rface ( DRQTA, DRQRA, D ACKA, DRQTB, DRQRB, DACKB).
Mode input pins (strapping options) allow the bus interface to be configured for either Siemens/
Intel or Motorola environment.
Generally, there are two types of transfers occurring via the system bus:
– command/status transfers, which are always controlled by the CPU. The CPU sets the
oper ation mode (initialization), controls function sequences and gets st atus in formation by
writing or reading the HSCX’s registers (via CS, WR or RD, and register address via A0-A6).
– data transfers, which are effectively performed by DMA without CPU interaction using the
HSCX’s DMA interface (DMA mode). Optionally, interrupt controlled data transfer can be
done by the CPU (interrupt mode).
Memory CPU
CS
System Bus
HSCX
DATA
DRQTA,
DRQTB,
DMA
Controller
Command
Status
Serial
Channel
INT
ITS00947
ABChannel
Serial
DRQRA,
DRQRB,
DACKA
DACKB
Semic onduct or Grou p 18
82525
82526
82525
82526
SAB
SAB
SAF
SAF
Specific Applications
HSCX with SAB 8051 Microcontroller
For cost-sensitive applications, the HSCX can be interfaced with a small SAB 8051
microcontroller system (without DMA support) very easily as shown in figure 3.
Figure 3
HSCX with 8051 CPU
Although the HSCX provides a demultiplexed bus interface, it can optionally be connected
directly to the local multiplexed bus of SAB 8051 because of the internal address latch function
(via ALE, compatibility to SAB 82520 HSCC).
The address lines A0 … A6 must be wired externally to the data lines D0 … D6 (direct
connection) in this case.
Intel bus mode is selected con necting IM1 pin to l ow (VSS). Since data transfer is controlled by
interrupt, the DMA acknowledge inputs (DACKA, DACKB) are connecte d to VDD (+ 5 V).
INT0
RD
WR
ALE
A8 - A15
AD0 - AD7
INT
RD
WR
ALE
CS
A0 - A6
D0 - D7
DACKA DACKB
Channel B
Channel A
AD0 - AD7
ALE
WR
RD
Latch
A8 - A15
Memory
Common Bus
ITS00948
CPU
SAB 8051 SAB 82525
HSCX
A0 - A15,D0 - D7
IM1
+5 VV+5
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SAB
SAB
SAF
SAF
HSCX with SAB 80188 Microprocessor
A system with minimized additional hardware expense can be with a SAB 80188
microprocessor as shown in figure 4.
Figure 4
HSCX with SAB 80188 CPU
The HSCX is co nnected to th e de mul tiplexe d system bus. Data transfer for one serial channe l
can be don e by th e 2-channel on -chip DMA cont roller of the S AB 80188, the other channel i s
serviced by i nter rupt. Since the SAB 8 0188 does not provi de DM A ackn owled ge ou tputs, data
transfer from/ to HSCX is contro lled via CS, RD or WR add ress inf orm ation ( A0 … A6) and t he
DACKA, DACKB inputs are not used.
This solution supports applications with a high speed data rate in one serial channel with
minim um har dware ex pense making use of th e on- chip per ipher al f unctions of the SAB 8 0188
(chip select logic, interrupt controller, DMA controller).
DRQ1 DRQRA
System
System Bus
ITS00949
DRQTADRQ0
D0 - D7A0 - A6
Serial
Channel A
Serial
Channel B
D0-D7A0-A6
Memory
Latches Transceiver
A8 - A15
AD0 - AD7
SAB 80188
CPU HSCX
SAB 82525
INTn PSCn
+5 V
DACKA
ALE
DACKB
CS
+5 V
INT IM1
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SAB
SAB
SAF
SAF
HSCX with SAB 80186 Microprocessor
and SAB 82258 Advanced DMA Controller (ADMA)
In applica tions, whe re two high -speed channels a re req uired, a 1 6-bit syste m with SAB 801 86
CPU and SAB 82258 ADMA is suitable. This is sho wn in figure 5.
Figure 5
HSCX with SAB 80186 CPU/SAB 82258 ADMA
HLDA
DRQRA
System
System Bus
ITS00950
DRQTA
HOLD
D0 - D7A0 - A6
Serial
Channel A
Serial
Channel B
D0 - D7A0 - A6
Memory
Latches Transceiver
AD0 - AD15
SAB 80186
CPU HSCX
SAB 82525
INTn PSCn
DACKA
DACKB
CS
+5 V
INT IM1
S0 - S2
ADMA
SAB 82258
DREQ0
DREQ1
Bus
Control
&
DACK0
DACK1
DREQ3
DREQ2 DRQTB
DRQRB
DACK3
DACK2
&
AD0 - AD15 S0 - S2
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SAB
SAB
SAF
SAF
The four selector channels of ADMA are used for serving the four DMA request sources of
HSCX, allowing very high data rates at both the system bus and the serial channels.
Another big advantage of the ADMA is it’s data chaining feature, providing an optimized
memory m anagement f or receive a nd transmit data. Reco rding the H SCX, a linked chain of 32
byte deep buffers can be se t up, which are subsequently fille d with the conten ts of the HSCX’s
FIFOs during reception. Not used buffers can be saved and linked to another buffer chain
reserved for the reception of the next frame.
As a result, it’s not necessary to reserve a very large space in system memory, determined by
the maximum frame length of every received fr ame.
In this example, the ADMA works directly at the CPU’s local bus and shares the same bus
interface logic (address latches, transceivers, bus controller) with the SAB 80186. Since one
DMA acknow ledge lin e is provi ded f or ea ch DMA r equest, two DACK o utputs must be ANDed
together for input to the HSCX.
The HSCX’s data lines are connected to the lower half of the system data bu s (D0 … D7) and
the address lines to A1 … A7, thus (from the CPU’s point of view) all internal register
addresses must be multiplied by two (even register addresses only).
e.g. CMDR register: HSCX address 61H < = > system address C2H.
1.3 Functional Description
General
The HSCX distinguishes from other low level HDLC devices by its advanced characteristics.
The most important ar e:
Beyond the point-to-point configurations, the HSCX directly enables point-to-multipoint or
multima ster configurations without additional hardware or software ex pense.
In point-to-multipoint configurations, the HSCX can be used as a master as well as a slave
station . Even wh en w orking as sla ve st ation, t he HS CX ca n in itia te the tran smissio n of d ata at
any time. An internal function block provides means of idle and collision detection and collision
resolution, which are necessary if several stations start transmitting simultaneously.
These features were integrated to support multimaster configurations.
Enlarged support of link configurations.
Semic onduct or Grou p 22
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SAB
SAB
SAF
SAF
Figure 6
Link Configuration
ITC02695
CxD TxD RxD
HSCX
Master 1
Controller
CxD TxD RxD
HSCX
CxD TxD RxD
HSCX
CxD TxD RxD
HSCX
RxD - Receive Data CxD - Collision Data
TxD - Transmit Data
Master 2 Master 3 Master n
Controller Controller Controller
ITC02694
CxD TxD RxD
HSCX
Slave1
Controller
CxD TxD RxD
HSCX
2Slave
CxD TxD RxD
HSCX
3Slave
CxD TxD RxD
HSCX
nSlave
Master
HSCX
TxD RxD
Controller
RxD - Receive Data CxD - Collision Data
TxD - Transmit Data
Controller Controller Controller
ITC02705
TxD RxD
HSCX
Controller
RxD - Receive Data
TxD - Transmit Data
HSCX
RxDTxD
Controller
Point-to-Point Configuration
Point-to-Multipoint Configuration
Multimaster Configuration
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SAB
SAB
SAF
SAF
Support of layer-2 functions by HSCX
Beside those bit-oriented functions usually supported with the HDLC protocol, such as bit
stuffing, CRC check, flag and address recognition, the HSCX provides a high degree of
procedural support. In a special operating mode (auto-mode), the HSCX processes the
information transfer and the procedure handshaking (I-, and S-frames of HDLC protocol)
autonomously. The only restriction is, that the window size (= number of outstanding
unacknowledged frames) is limited to 1, which will be sufficient in most applications. The
communi cation proce dures are m ainly pr ocessed betw een the com municat ion contro llers and
not between the processors. Thus the dynamic load of the CPU and the software expense is
largely reduced.
Figure 7
Procedural Support in Auto-Mode
ITS05502
HSCX HSCXPµ
SFrame
FrameI FrameU
µP
The CPU is informed about the status of the procedure and has to manage the receive and
transmit data mainly. In order to maintain cost effectiveness and flexibility, such functions as
link setup/disconnection and error recovery in case of protocol errors (U-frames of HDLC
protocols) are not implemented in hardware and must be done by user’s software.
Telecom specific features
In a speci al opera ting mode , the HSCX can tran smit or r eceive da ta packets i n one o f up to 64
time-slots of programmable width (clock mode 5). Furthermore, the HSCX can transmit or
receive variable data portions wit hin a defined window of one or more clock cycles, which has
to be selected by an external strobe signal (clock mode 1). These features make the HSCX
especially suitable for all applications using time division multiplex methods, such as time-slot
oriented PCM systems, systems designed for packet switching, or in ISDN applications.
FIFO buffers to efficient transfer of data packets.
A further speciality of HSCX are the FIFO buffers used for the temporary storage of data
packets transf erred between t he serial communications interfac e and the p arallel system bus.
Also because of the overlapping input/output operation (dual-port behaviour), the maximum
message length is not limited by the size of the buffer. Together with the DMA capability, the
dynamic load of the CPU is drastically reduced by transferring the data packets block by block
via direct memory access. The CPU only has to initiate the data transmission by the HSCX and
determine the status in case of completely received frames, but is not involved in data
transfers.
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SAB
SAB
SAF
SAF
The HD LC cont ro lle r of each ch anne l can be p rogr amm ed to oper ate in va rio us mo des, w hich
are different in the treatment of the HDLC frame in receive direction. Thus, the receive data
flow an d the address recognition features can be effected in a very flexible way, which satisfies
most requirements.
There are 6 different operating modes which can be set via the MODE register.
2 Operating Modes
Characteristics: Window size 1, arbitrary message length, address recognition.
The HSCX processes autonomously all numbered frames (S-, I-frames) of an HDLC
procedure.
The HDLC control field, data in the I-field of the frames and an additional status byte is
temporarily stored in the RFIFO. The HDLC control field as well as additional information can
also be read from special registers (RHCR, RSTA).
According to the selected address mode, the HSCX can perform a 2-byte or 1-byte address
recognition. If a 2-byte address field is selected, the high address byte is compared with the
fixed value FEH or FC H (gr ou p a ddre ss) a s wel l as w it h two i n divi dua lly pr og ra mm a ble va lues
in RAH1 and RAH2 registers. According to the ISDN LAPD protocol, bit 1 of the high byte
address will be interpreted as COMMAND/RESPONSE bit (C/R), dependent on the setting of
the CRI bit in RAH1, and will be excluded from the address comparison.
Similary, two compare values can be programmed in special registers (RAL1, RAL2) for the
low address byte. A valid address will be recognized in case the high and low byte of the
address field correspond to one of the compare values. Thus, the HSCX can be called
(addressed) with 6 different address combinations, however, only the logical connection
identified thr ough the ad dress combi nation RAH1, RAL1 will be processed in the auto-mode,
all others in the non-auto mode. HDLC frames with address fields that do not match with any
of the address combinat ions, are ignored by the HSCX.
In case of a 1-byte address, RAL1 and RAL2 will be used as compare registers. According to
the X.25 LAPB protocol, the value in RAL1 will be interpreted as COMMAND and the value in
RAL2 as RESPONSE.
After receiving a frame it takes 5 clock cycles to generate the response frame and to start
transmission.
2.1 Auto-Mode (MODE: MDS1, MDS0 = 00)
Characteristics: address recognition, arbitrary window size.
All frames with valid addresses (address recognition identical to auto-mode) are forwarded
directly to the system memory.
The HD LC contro l field, data in the I-field and an additional status byte are temporari l y stored
in the RFIFO . The HDLC contro l field and a dditional i nformati on can also be rea d from special
registers (RHCR, RSTA).
In non-auto mode, all frames are treated similarly.
2.2 Non-Auto Mode (MODE: MDS1, MDS0 = 01)
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SAB
SAB
SAF
SAF
Charac te risti cs: add r ess recogn i ti on high byt e
Only the high byte of a 2-byte address fie ld will be com pared . The whole frame except the first
address byte will be stored in RFIFO. RAL1 contains the second and RHCR the third byte
following the opening flag.
2.3 Transparent Mode 1 (MODE: MDS1, MDS0, ADM = 101)
Charac te risti cs: no add r ess rec ogn it ion
No address recognition is performed and each frame will be stored in the RFIFO. RAL1
cont ains the first and RHCR the second byte following the opening flag.
2.4 Transparent Mode 0 (MODE: MDS1, MDS0, ADM = 100)
Char acteris tics: fu lly transparen t
In extended transparent modes, fully transparent data transmission/reception without HDLC
framing is performed, i.e. without FLAG generation/recognition, CRC generation/check, bit-
stuffing mechanism. This allows user specific protocol variations or the usage of Character
Oriented Protocols (such as IBM BISYNC).
Data transmission is always performed out of the XFIFO. In extended transparent mode 0
(ADM = 0), data reception is d one via the RAL1 register, which always contains t he actual data
byte assembled at the RxD pin. In extended transparent mode 1 (ADM = 1), the receive data
are additional shifted into the RFIFO.
Also refer to chapter 6.1 and 6.2.
2.5 Extended Transparent Modes 0; 1 (MODE: MDS1, MDS0 = 11)
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SAB
SAB
SAF
SAF
2.6 Receive Data Flow (Summary)
The following figure gives an overview of the management of the received HDLC frames as
affected by different operating modes.
Figure 8
Receive Data Flow of HSCX
ITD00228
FLAG ADDR CTRL ΙCRC FLAG
ADDRESS
CONTROL
DATA STATUS
Auto/16
RAH1, 2 RAL1, 2 RFIFO
RHCR RSTA
001
ADMMDS0MDS1
RSTARHCR
RFIFO
X
RAL1, 2
000 Auto/8
Auto/16011
RAH1, 2 RAL1, 2 RFIFO
RHCR RSTA
Auto/8010
XRFIFO
RHCR RSTA
Transparent101
RAH1, 2 RFIFO
RHCR RSTA
100
RFIFO
RSTA
Non
Non
RAL1, 2
RAL1
1
0Transparent RAL1 RHCR
MODE
Note:In case of on 8 Bit Address,
the Control Field starts here!
Description of Symbols:
Compared with (register)
Processed autonomously
Stored (FIFO,register)
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SAB
SAB
SAF
SAF
82525
82526
82525
82526
SAB
SAB
SAF
SAF
Two different types of frames can be transmitted:
2.7 Transmit Data Flow
Figure 9
Transmit Data Flow of HSCX
ITD00229
FLAG ADDR CTRL ΙCRC FLAG
ADDRESS
CONTROL
DATA CHECKRAM
XFIFO
XAD1 XAD2 XFIFO
*1
*1
Transmit
Transparent
Frame
(XTF)
Transmit
I-Frame
(XIF)
*1 Optional checkram handling in version 2 upward
I-frames and–transparent frames–
as shown below.
For I-frames ( command XIF via CMDR r eg ister ) , th e a dd re ss a nd control fiel d s are gener at ed
autonomously by the HSCX and the data in the XFIFO is entered into the information field of
the frame. This is possible only, if the HSCX is operated in the auto-mode.
For transp arent fram es (command XTF via CMDR register) , the address an d the control fiel ds
have to be e ntered i n the XFIFO as w ell. This is possi ble in al l operating modes and used also
in auto-mode for sending U-frames.
Semic onduct or Grou p 28
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SAB
SAB
SAF
SAF
When operating in the auto-mode, the HSCX offers a high degree of procedural support. In
addition to address recognition, the HSCX autonomously processes all (numbered) S- and
I-frames (prerequisite window size 1) with either normal or extended control field format
(modulo 8 or modulo 128 sequence numbers – selectable via RAH2 register).
3 Procedural Support (Layer-2 Functions)
updating of transmit and receive counter– evaluation of tr ansmit and rece ive counter–
In addition, all unnumbered frames are forwarded directly to the processor.
The following function s will be performed:
processing of S commands– flow control wi th RR/RNR– generation of responses–
transmitting of S commands, if acknowledgement is missing– continuo us status quer y of oppo site termination after RNR has been rece ived– programmable timer/repeater functions.–
recog nition of prot ocol errors–
Additional logic connections can be operated in parallel by software. The logic link can be
initialized by software at any time (RHR).
Initially (i.e. after RESET), the LAP controllers of the two serial channels are configured to
functio n as a combine d station, w here they au tonomous ly perform a su bset of the X.2 5 LAPB/
ISDN LAPD protocol.
3.1 Full-Duplex LAPB/LAPD Operation
The logi c pro cess i ng of re cei v ed S- fr ames is p erfo rme d b y t he HSC X wi th ou t int e rrup ti ng the
µC. The µC is merely informed by interrupt with respect to status changes in the opposite
station (receive ready/not receive ready) and protocol errors (unacceptable N(R) or S-frame
with I field).
Reception of Frames
I-frames are also processed autonomously and checked for protocol errors. The I-frame will
not be accepted in the case of N(s) error (no interrupt is forwarded to the µC), but is
immediately confirmed by an S response. If the µC sets the HSCX into a "receive not ready"
status, an I-frame will not be accepted (no interrupt) and an RNR response is transmitted.
U-frames are always stored in the RFIFO and forwarded directly to the µC. The logic sequence
and the reception of a frame in the a uto -mode is illustrated in figure 10.
Note: The state variables N(S), N(R) are evaluated within the window size, i.e. the HSCX
checks only the Isb of the receive and transmit counter regardless of the selected
modulo count.
Semic onduct or Grou p 29
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SAB
SAB
SAF
SAF
The HSCX autonomously transmits S commands and S responses in the auto-mode. Either
transparent or I-fra mes ca n be t ransmitte d by the u ser. Th e softwar e tim er ha s to be operat ed
in the internal timer mode to transmit I-frame s. After the frame ha s been transmitted, the time r
is self-started, the XFIFO is inhibited, and the HSCX waits for the arrival of a positive
acknowledgement. This ackn owledge m ent can be provided by me ans of a n S- or I-frame.
Transmission of Frames
message has been acknowledged as positive (XPR interrupt)–message must be repeated (XMR interrupt)–
Transparent frames can be transmitted in all operating modes. After the transmission of a
transparent frame the XFIFO is immediately enabled, which is confirmed by interrupt (XPR).
In this case, time monitoring can be performed with the timer in the external timer mode.
Note: The internal timer mode should only be used in the auto-mode.
respo nse has not been received (TIN interrupt)–
Upon arrival of an RNR frame, the software timer is started and the status of the opposite
station is polled periodically after expiration of t1, until the status "receive ready" has been
detected. The user is informed accordingly via interrupt. If no response is received after n1
times an interrupt will be generated (TIN interrupt). As a result, the process will be terminated
as illustrated in figure 11.
If no pos itive ackno wledg ement is received d uring tim e t1, the HSCX t ransmits an S co mmand
(p = 1), which must be followed by an S response (f = 1). If the S response is omitted, the
process is performed n1 times before it is terminated.
Upon the arrival of an acknowledgement or after the completion of this poll procedure the
XFIFO is enabled and an interrupt is forwarded to the µC. Interrupt s may be trigge red by the
following:
Semic onduct or Grou p 30
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SAB
SAB
SAF
SAF
Figure 10
Processing of Received Frames in Auto-Mode
ITD00230
Command
with p = 1
?
Y
?
Ready
Rec. N
f = p
Trm RR
ActivRec.
Set RRNR
Response
PCE
Int :
1
Response
Trm RNR
f = p
?
Overflow
Data
N
:
Int RME
Set RDO
Response
Trm RR
f = p
RME
Int :
N
Y
Y
N
Y
Rec. Ready :
Int RME
N
Set RDO
Data
Overflow
?
N
Y
Acknowledge
RESET Wait for
Y
Y
?
Acknowledge
Wait for
N
Y
:
Int XMR
RESET Wait for
Acknowledge
Acknowledge
RESET Wait for
ALLS
Int :
Response
f = 1
?
N
(S) + 1N(R) = V
N
Y
Wait for
Acknowledge
?
NN
Y
?
CRC Error
Set CRCE
N
N
Set RAB
Aborted
?
Y
U Frame
1
YProt. Error
?
N
PCE
Int :
:
Int RME
Set CRCE N
?
CRC Error
Y
Set RAB
Aborted
?N
Y
I Frame
N
1
YProt. Error
?
N
or Abort
CRC Error
Y
RNR
?
1
RESET RRNR
?
,
YCRC Error
or Abort
N
?
Prot. Error
Y
N
:
Int PCE
SREJ
REJ
RR,
1
Y
V(S)
V=
(S) + 1
Y
?
ALLS
:
Int
N(R) (S) + 1
= V
?
V(S)
=
(S) V+ 1
ALLS
Int :
= V
N(S) (R) + 1
?
(R) (R)
V=V+ 1
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SAB
SAB
SAF
SAF
Figure 11
Timer Procedure/Poll Cycle
ITD00231
Wait for
Acknowledge
Set
?
?
2
?
with f = 1
Response
Wait for
Acknowledge
?
RRNR
N
NN
Y Y
N
2
YY
=
?
(R) (S) + 1
VN
Y
N
1
t
Load
Rec.RNRRec. RR
I
Rec. Frame
T Proc.Activ
TIN
Int :
1
Load t1
Y
?
Ready
Rec. N
Command, p = 1
Trm RR Trm RNR
Command, p = 1
n1 n1 - 1
=
N
?
Y
Y
?
N
n1 =7
n1=0
Run Out
1 2
2
Load t1
Trm RR/RNR
CMDR ; STI
Command p = 1
Trm I Frame
Acknowledge
Set wait for
InactivT Proc. 1
RNR
Set RRNR
Rec.
1
t
Load n1
Load n1
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SAB
SAB
SAF
SAF
Examples
The interaction between the HSCX and the CPU during the transmission and reception of
I-frames is illustrated in figure 12, the flow control with RR/RNR during the reception of
I-fra mes i n figure 13, and duri ng the t ransmission of I-fra mes i n figure 14. Both the sequence
of the poll cycle and protocol errors are illustrated in figure 15.
Figure 12
Transmission/Reception I-Frames
Figure 13
Flow Control/Reception
ITD00232
RME
RME
WFA
Transmitwith
Frame
Ι
Confirm ΙFrame
ALLS
ALLS WFA
Reception Frame
Ι
Transmit Frame
Ι
RR (1)
(0.0)
Ι
RR (1)
Ι(0.1)
(1.1)
Ι
(1.2)
Ι
RR (2)
XPR
XPR
ITD00234
RNR
RME
XRNR RNR (0)
RR
(0.0)
Ι
RR (0) p = 1
RR (0) f = 1
RR (0) p = 1
RR (0) f = 1
Ι(0.0)
RR (1)
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SAB
SAB
SAF
SAF
Figure 14
Flow Control/Transmission
Figure 15
S Commands/Protocol Error
ITD00233
RR (0) f = 1
RNR
RSC(RNR)
RSC (RR)
XMR
WFA
t1
t1 RR (0) p = 1
RNR (0) f = 1
RNR (0)
Ι(0.0)
RR (0) p = 1
XPR
ALLS
ITD00235
t1
t1
t1
RR p = 1
Poll Cycle
Protocol Error
Ι
RR (0) p = 1
RR (1)
RR (2)
ALLS
PCE
TIN
WFA
ALLS
RR (0)
WFA
RR p = 1
(0.0)
XPR
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Semic onduct or Grou p 34 901.90
3.2 Half-Duplex SDLC-NRM Operation
The LAP controllers of the two serial channels can be configured to function in a half-duplex
Normal Response Mode (NRM), where they will operate as a slave (secondary) station, by
sett ing the NRM bit in the XBCH register of the respect ive cha nnel.
In contrast to the full-duplex LAPB/LAPD operation, where the combined (primary +
secondary) station transmits both commands and responses and may transmit data at any
time, the NRM mode allows only responses to be transmitted and the secondary station may
transmit only when instructed to do so by the master (primary) station.
The HSCX get s t he pe rmi ssi on t o tra nsm it a f ra me fr om t he p rim ar y by an S -, or I-frame with
the poll bit (p) set!
The NRM mode can be profitably used in a point-to-multipoint configuration with a fixed
master-slave relationship and avoids collisions on the common transmit line. It’s the
responsibility of the master station to poll the slaves periodically and to process the error
recovery.
Prerequisite for NRM operation is:
MODE: MDS0, MDS1, ADM = 000
MODE: TDM = 0
XAD1 = X AD2 = RAL1 = RAL2 ← (address of secondary)
Note: The broadcast address may be programmed in RAL2 if broadcasting is required.
Reception of Frames
The reception of frames functions equally to the LAPB/LAPD oper ation.
Transmission of Frames
The HSCX does not transmit S-, or I-frames if not instructed to do so by the primary station
sending an S-, or I-frame with the poll bit set.
The HSCX can be prepared to send an I-frame by the CPU issuing an XIF command (via
CMDR) at any time. The transmission of the frame, however, will not be initiated by the HSCX
prior to the reception of either a
RR, or
I-frame
with a poll bit set (p = 1).
After the frame has been transmitted (with the final bit set), the XFIFO is inhibited and the
HSCX waits for the arrival of a po s itive acknowledg ement.
auto-mode wi th 8-bit address field selected
external timer mode
same transmit and receive addresses, since only responses can be transmitted, i.e.
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Since th e on-chip tim er of the HSCX must be o perated in the extern al mode (a secondary may
not poll the primary for acknowledgements), time supervisory must be done by the primary
station.
Upon the arrival of an acknowledgement the XFIFO is enabled and an interrupt is forwarded
to the CPU, either the
– message has been acknowledged as positive (XPR interrupt), or the
– message must be re peated (XMR interru pt).
Additionally, the timer can be used under CPU control to provide timer recovery of the
secondary if no acknowledgem ents are recei ved at all.
Note: The transmission of transparent frames is possible only if the permission to send is
achieved by an S-frame (p = 1) or I-frame.
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Examples
A few examples of HSCX/CPU interaction in case of NRM mode are provided in figure 16 to
figure 19.
Figure 16
No Data to Send
Figure 17
Data Reception/Transmission
ITD00236
RR (0) f = 1
RR (0) p = 1
Primary
HSCX
Secondary
(0,1) f = 1
(0,0) p = 1
ITD00237
(1,1) p = 1
RR (2) f = 1
ALLS
RME
XIF Ι
Ι
Ι
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Figure 18
Data Transmission (no Error)
Figure 19
Data Transmission (Error)
(0,0) f = 1
RR (0) p = 1
ITD00238
RR (1) p = 0
ALLS
XIF
Ι
ITD00239
XIF
Read EXIR
RR (0) p = 1
Ι(0.0) f = 1
XMR
t
RR (0) p = 1
RR (0) f = 1
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3.3 Error Handling
Depending on the error type, erroneous frames are handled according table 1.
Table 1
Error Handling
Frame Type Error Type Generated
Response Generated
Inter rupt Rec. Status
ICRC err or
aborted
unexpec. N(S)
unexpec. N(R)
–
–
S-frame
–
RME
RME
–
PCE
CRC error
abort
–
S CRC err or
aborted
unexpec. N(R)
with I-field
–
–
–
–
–
–
PCE
PCE
–
–
Note: The station variables (V(S), V(R)) are not changed.
4 CPU Interface
4.1 Register Set
The communication between th e CPU and the HSCX is do ne via a set of dir ectly accessible
8-bit registers. The CPU sets the operating modes, controls function sequences, and gets
status in for mati o n by w ri ti ng or readin g these re gi ste r s (Co mm an d/ Stat us tr an sfe r). Com p le te
information concerning the register functions is provided in detailed register description. The
most important functions programmable via these registers are:
– setting of operating and clocking modes
– layer-2 functions
– data transfer modes (Interrupt, DMA)
– bus mode
– DPLL mo de
– baudrate generator
– test loop
Each of two serial channels of HSCX is controlled via an equal, but totally inde pendent register
file (channel A and channel B).
4.2 Data Transfe r Modes
Data transfer between the system memory and the HSCX for both transmit and receive
direction is controlled by either interrupts (Interrupt Mode), or independently from CPU
interaction using the HSCX’s 4-channel DMA interface (D MA Mode).
After RESET, the HSCX operates in Interrupt Mode, where data transfer must be done by the
CPU. The user selects the DMA Mode by setting the DMA bit in the XBCH register. Both
channels can be independently operated in either Interrupt or DMA Mode (e.g. Channel
A-DMA, Channel B-Interrupt).
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4.3 Interrupt Interface
Special events in the HSCX are indicated by means of a single interrupt output, which requests
the CPU to read status information from the HSCX, or, if Interrupt Mode is selected, transfer
data from/to HSCX.
Since only one INT reques t output is provided , the cau se of an inte rrupt must be determ ined
by the CPU reading the HSCX’s interrupt status registers (ISTA, EXIR).
The st ructure of the interrupt status regist ers is shown in figure 20.
Figure 20
HSCX Interrupt Status Registers
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Five inte rru pt in di cati ons c an b e re ad di rec tly f ro m the ISTA reg ist er an d a not her s ix in te rrup t
indications from the extended interrupt register (EXIR).
After the HSCX has requested an interrupt by setting its INT pin to low, the CPU must first read
the interrupt status register of channel B (ISTA-B) in the associated interrupt service routine.
The thre e lo west orde r bits ( bit 2- 0) of I STA-B (IC A, EXA, EXB) poi nt are set to th ose re gisters
in which the actual interrupt source is indicated. It is possible that several interrupt sources are
indicated referring to one interrupt request (e.g. if the ICA bit is set, at least one interrupt is
indi cated in the IST A register of channel A).
An interrupt source from channel B is implicitly indicated by bits 7-3 of ISTA-B; therefore these
bits must also always be checked.
The INT pin of the HSC X rema ins ac tive un til al l interru pt sou rces are clea red b y readi ng th e
correspon ding inte rrupt re gister . Therefore it is poss ible t hat the I NT pin is still active when the
interrup t service routine is finished.
For some interrupt controlle rs or CPUs it might be necessary to generate a new edge on the
interrupt line to recognize pending interrupts. This can be done by masking all interrupts at the
end of the interru pt serv ic e r ou t ine (wri ti ng FF H into the MASK register) and write back the old
mask to the MASK register.
The HSCX interrupt sources can be logically grouped into
– receive interrupts,
– transmit interrupts, and
– special condition interrupts.
Each interrupt indication of the ISTA registers can be selectively masked by setting the
respective bit in the MASK register.
The following tables give a complete overview of the individual interrupt indications and the
cause of their activation as well as specific restrictions (marked with ’’*’’).
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Table 2
Receive Interrupts
RECEIVE INTERRUPTS
RPF Receive Pool Full
(ISTA) *Only activated in Interrupt Mode!
Activated as soon as 32-bytes are stored in
the RFIFO but the message is not yet
completed.
RME Receive Message End
(ISTA) Interrupt Mode:
Activated if either one message up to 32 bytes
or the last part of a message with more than
32 bytes is stored in the RFIFO, i.e. after the
reception of the CRC and closing flag
sequence.
DMA Mode:
Activated after the complete message has
been read out by the DMA controller.
RFO Receive Frame Overflow
(EXIR) Activated if a complete frame could not be
stored due to occupied RFIFO, i.e. the RFIFO
is full and the HSCX has detected the start of
a new fram e.
RFS Receive Frame Start
(EXIR) *Only activated if enabled by setting the RIE
bit in CCR2 register.
Activated after the start of a valid frame has
been detected, i.e. after a valid address check
in operation modes providing address
recognition, otherwise after the opening flag
(transparent mode 0), delayed by two bytes.
After an RFS interrupt, the contents of
– RHCR
– RAL1
– RSTA – bit 3-0
are valid and can be read by the CPU.
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Table 3
Transmit Interrupts
TRANSMIT INTERRUPTS
XPR Transmit Pool Ready
(ISTA) Activated whenever a 32-byte FIFO pool is
empty and accessible to the CPU, i.e.
– following a XRES command via CMDR.
Interrupt Mode:
Repeat edly during frame tran smission start ed
by XTF or XIF command, and no end of
message indication (XME command) has
been issued yet by the CPU,
– after the end-of-message indication
when frame transmission of a transparent
frame is completed (i.e. CRC and closing flag
sequence are shifted out),
Auto-Mode:
If an I-frame has been positively
acknowledged by the opposite station.
XMR Transmit Message Repeat
(EXIR) Auto-Mode:
Activated if the last transmitted I-frame has to
be repeated due to the reception of a negative
acknowledgement (S-, or I-frame with
unaccording receive sequence number) of the
opposite station.
Bus Configuration:
A collision has occurred after sending the
32nd data byte of a message.
Point-to-Point Configuration:
CTS has been withdrawn after sending the
32nd data byte.
XDU T ransmit Data Underrun
(EXIR) Activated if the XFIFO holds no further data,
i.e. all data has been shifted out via the serial
T×D pin, but no End Of Message (EOM)
indication has been detected by the HSCX.
The EOM indica tion is supplied either
– by a XME command from the CPU in
Interrupt Mode,
– or by checking the pre- pr o gr amm ed
transmit byte count (via XBCH, XBCL ) against
the actual amount of data bytes shifted out in
DMA Mode.
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Table 4
Special Condition Interrupts
SPECIAL CONDITION INTERRUPTS
Layer 2-Specific * Activated only if the "Auto" operating mode has been selected
via MODE register)
RSC Receive Status Change Activated after a status change of the opposite
stations receiver has been detected (Receiver
Ready/Receiver Not Ready) due to the
reception of a
– RR frame, if receiver was not ready, or
– RNR frame, if receive r was ready.
PCE Protocol Error Activated if a protocol violation has been
detected due to the reception of
– an S-, or I-frame with incorrect N(R),
– an S-frame containing an I-field.
Internal Timer
TIN Timer Interrupt
(ISTA) Activated if the internal timer and repeat
counter has been expired (see description of
TIMR register in chapter 8).
External Pin
CSC CTS Status Change
(EXIR) * Only activated if enabled by setting the CIE
bit in the CCR2 register.
4.4 DMA Interface
The HSCX comprises a 4-channel DMA interface for fast and effective data transfers.
For both serial channels, a separate DMA Request Output for Transmit (DRQT) and receive
direction (DRQR) as well as a DMA Acknowledgement (DACK) input is provided.
The HSCX activates the DRQ line as long as data transfers are needed from/to the specific
FIFO (level triggered demand tran sfer mode of DMA controller).
It’s the responsibility of the DMA controller to perform the correct amount of bus cycles. Either
read cycles will be performed if the DMA transfer has been requested from the receiver, or write
cycles if DMA has been requested from the transmitter. If the DMA controller provides a DMA
acknowledg e signal (input to the HSCX’s DAC K pin), each bus cycle implicitly selects the top
of the specific FIFO and neither address (via A0-A6) nor chip select need to be supplied (I/O
to Memory transfers). If no DACK signal is supplied, normal read/write operations (providing
addresses) must be performed (memory to memory transfers).
The HSCX deactivates the DRQ line immediately after the last read/write cycle of the data
transfer has started.
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HSCX supports target synchronous as well as source synchronous DMA transfer. In source
synchronous DMA transfer mode a DMA cycle is started when an active level occurs an the
DMA request line. This request is controlled by the source (transfer peripheral device →
memory).
First of all the data is read out of the periph eral device. During the second clock cycle it is writ-
ten into the memory according to the target address.
If there is target synchronous DMA transfer the DMA cycle is started when there is an active
level on the DMA request line. The request is controlled by the target (transfer memory →
peripheral).
First of all the da ta is read from th e memory. During th e second clock cycle it is written into the
peripheral IC. The DMA request line continues being activated until it is reset by a write cycle
to a p e riph eral d evic e IC.
ITD02697
T1 T2 T3 T4 T1 T2 T3 T4
t
DRHSYS
t
CLRL
t
INVCL
CLOCKOUT
DRQ
RD
(FIFO)
WR
(Memory)
f
CLKOUT
t
CLCL
t
CLRL
t
INVCL
t
DRHSYS
max
8 MHz 125 ns 44 ns 15 ns 316 ns
ns188ns15ns37ns80MHz12.5 ns141.5ns15ns31ns62.5MHz16
INVCL
t
-
t
CLCL
-
t
CLRL
x3=
INVCL
t
-
CLRL
t
-T4+T3=
max
DRHSYS
t
+T2
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If you use the write signal instead of the chip select signal in order to reset the DMA request
you gain some time. The extra circuit is just an AND gate. The first input of the AND gate is
connected to the DMA request line of the peripheral IC; the second input is connected to the
chip select line. The AND gate’s output is the DMA request signal for the 80(C)188.
Theore ticall y, the requ est lin e of an 80(C) 188, for examp le, woul d still be acti ve when the de-
termina tion is made and DMA cycles w ould be p erformed p ermanently. Therefore t he decision
of the DMA request line is delayed; it is already made two clock cycles before the end of the
write cycle. If no wait-states are inserted the decision is made at the end of the T2 clock cycle.
Due to the fact th at the write si gnal will be val id at the b eginning of T2 there is onl y little time
left for resetting the DMA request line.
ITD02698
T1 T2 T3 T4 T1 T2 T3 T4
t
DRHSYS
t
CVCTV
t
INVCL
CLOCKOUT
DRQ
RD
(Memory)
WR
(FIFO)
t
DRHSYS
max
=T2-
t
CVCTV
-
t
INVCL
f
CLKOUT
t
CLCL
t
CVCTV
t
INVCL
t
DRHSYS
max
8 MHz 125 ns 56 ns 15 ns 54 ns
ns18ns15ns47ns80MHz12.5 ns16.5ns15ns31ns62.5MHz16
ITS02699
&
DRQ
PCS
80(C)188 HSCX
DRQTx
CS
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The circuit mentioned above results in a slower data transfer with the HSCX. HSCX usually
performs block transfers. The block length is up to 32 bytes. The DMA request line of the IC
remains active as long as more data are needed. Having transmitted the last byte the DMA
request is bei ng rese t. U sing th e addi tion al circuit th e DMA re que st lin e will be active at l east
shortly before T4. So the next DMA c ycle will be started four (instead of two) clock cycles later.
Therefore the maximum transmission rate is reduced from 1.25 Mbyte/s to 1.04 Mbyte/s (clock
rate: 12.5 MHz).
For more information refer to chapter 7.2 (Data Transmission: DMA Mode), chapter 7.3 (Data
Reception: DMA mode), and Appendix C (Application Example HSCX with 80(C)188 using
DMA).
ITD02700
T1 T2 T3 T4 T1 T2 T3 T4
t
DRHSYS
t
CLCSV
t
CHCSX
CLOCKOUT
DRQTx
RD
(Memory)
CS
(FIFO)
WR
(FIFO)
t
DRHSYS
max
= T2 + T3 -
t
CVCTV
+
t
CHCSX
f
CLKOUT
t
CLCL
t
CVCTV
t
CHCSX
t
DRHSYS
max
8 MHz 125 ns 56 ns 5 ns 261ns
ns158ns5ns47ns80MHz12.5 ns130ns5ns31ns62.5MHz16
T4/2+
DRQ
CVCTV
t
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4.5 FIFO Structure
In bo th transmit a nd receive direction 64-byte d eep FIFO’s are provid ed for the intermedi ate
storage of data between the serial interface and the CPU interface. The FIFO’s are divided into
two halv es of 32-byte s, wher e only one half is accessib le to th e CPU or DM A contro ller at any
time.
The organization of the Receive FIFO (RFIFO) is such, that in the case of a frame at most 64
bytes long, the whole frame may be stored in the RFIFO. After the first 32 bytes have been
received, the HSCX prompts to read the 32-byte block by means of interrupt or DMA request
(RPF interrupt or activation of DRQR line). This block remains in the RFIFO until a confirmation
is given t o th e HSCX ac kn o wledg ing th e tr ans fer of th e dat a blo ck . This co nfir mat io n is eith er
a RMC (Receive Message Complete) command via the CMDR register in Interrupt Mode, or
is impl icitly achi eved in DM A mode afte r 32-bytes have been r ead from t he RFIFO. As a result,
it’s possible in Interrupt Mode, to read out the data block any number of times until the RMC
command is issued.
The configuration of the RFIFO prior to and after acknowledgement is shown in figure 21.
Figure 21
Configuration of RFIFO (Long Frames)
ITD01582
32
Inaccessible
Accessible
32
a) Prior to
Acknowledgement b) After
Acknowledgement
Block
B + 1
Block
B
Free
B + 1
Block
Bytes
Bytes
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If frames longer than 64 bytes are received, the device will repeatedly prompt to read out 32-
byte data blocks via interrupt or DMA.
In the case of several shorter frames, up to 17 may be stored in the HSCX.
If the acce ssible ha lf of the RFIFO co ntains a fr ame i (or the las t part of frame i) , up to 16 short
frames may be stored in the other half (i + 1,. . ., i + n) meanwhile, prior to frame i being fetched
from the RFIFO.
This is illustrated in figure 22.
For a description of a transmit and receive sequence in both Interrupt or DMA Mode, please
refer to chapter 7.2 and 7.3.
Figure 22
Configuration of RFIFO (Short Frames)
Note: The number of 17 frames applies e.g. for the HSCX operating in the auto or non-auto
mode (ad dress reco gnition), and sho rt frames o nly contai ning the H DLC Address and
Control field are received. Since the address is not stored, the control field is always
stored first in the RFIFO, and an additional status byte is always appended at the end
of each frame in the RFIFO, these frames will occupy two bytes.
32
Inaccessible
Accessible
32
a) Prior to
Acknowledgement b) After
Acknowledgement
Frame
Last Part
of Frame
Frame
i + n
i + 1
Frame i + n
Frame i + 2
Frame i + 1
16n<0
ITD00486
Bytes
Bytes
i
_
<
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5.1 Clock Modes
The HSC X includes an interna l Oscillator (OSC) as wel l as indepen dent Baud rate Gene rator
(BRG) and Digital Phase Locked Loop (DPLL) circuitry for each serial channel.
The transmit and receive clock can be either generated
– externally, and supplied via the R×CLK and/or T×CLK pins, or
– internally, by means of the
* OSC and/or BRG, and
* DPLL, recovering the receive (and optionally transmit) clock from the received data
stream if an external crystal is connected to the R×CLKA-A×CLKA pins.
Totally, there are 8 different clocking modes programmable via the CCR1 register, providing a
wide variety of clock generation and clock pin functions, as shown in table 5.
Table 5
Overview of Clock Modes
Type Source Generation Mode
Clock
Receive
Clock
R×CLK Pins
DPLL
OSC
Externally
Internally
0, 1, 5
2, 3, 6, 7
4
Transmit
Clock
T×CLK Pins
R×CLK Pins
DPLL
BRG/16
OSC
Externally
Internally
0, 2, 6
1, 5
3, 7
2, 6
4
The transmit clock pin s (T×CLK) may also o utput clock or con trol signal in ce rtain clock modes
if programmed as outputs via the CCR2 register (TIO bit set).
The clocking source for the DPLL’s is always the internal BRG; the scaling factor (divider) of
the BRG can be programmed through CCR2 and BGR registers between 1,2,4 ,6 . . .2048.
The HSCX system clock is always derived from the transmit clock thus eliminating the need
for additional clock sources.
5 Serial Interface (Layer-1 Functions)
The two serial interfaces of the HSCX provide two fully independent communications
channels, supporting layer-1 functions to a high degree by various means of clock generation
and clock recovery.
Clock Mode 0 (External Clocks)
Separate, externally generated receive and transmit clocks are forwarded to the HSCX via
their respective pins.
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Clock Mode 1 (Receive/Tran sm it Strobes )
Externally gen erated, but iden tical receive and transmit clo cks are forwarded via R × CLK pins.
In addition, a receive strobe can be connected via A×CLK an d a trans mit strobe v ia T × CLK
pins. The operating m ode can be appl ied in time di vision multip lex applicati ons or for adju sting
disparate transmit and receive data rates.
Clock Mode 2 (Receive Clock from DPLL)
The BRG is driven with an external clock (R × CLK) and it delivers a reference clock for the
DPLL which in turn generate the receive clock. Depending on the programming of the CCR2
register (TSS bit), the transmit clock will be either an external clock signal (T × CLK) or the clock
deliv ered by t he BR G d i vid ed by 16. In this c ase, the tr an sm it clock can be outpu t vi a T × CLK
(CCR2 : TIO = 1).
Clock Mode 3 (Receive and Transmit Clock from DPLL)
The BRG is fed with an externally generated clock via R × CLK and supplies the reference clock
for DPLL, which generates both the receive and transmit clock. This clock can also be output
via T × CLK pi n.
Clock Mode 4 (OSC-Direct)
The receive an d transmit clocks are directly supplied by the OSC. In addition this clock can
be output via T × CLK.
Clock Mode 5 (Time-Slots)
This operating mode has been designed for application in time-slot oriented PCM systems.
The receive and transmit clock is identical for each channel and must be suppli ed externally
via R × CLK pins. The HSCX receives and transmits only during certain time-slots of
programmable width (1. . .256 bit, via RCCR and XCCR registers) and location with respect to
a frame synchronization signal, which must be delivered to the HSCX via the
A × CLK pin. One of up to 64 time-slots can be programmed independently for receive and
transmit direction via TSAR and TSAX registers, and an additional clock shift of 0…7 bits via
TSAR, TSAX, and CCR2 registers. Together with bits XCS0 and RCS0 (LSB of clock shift),
located in the CCR2 register, there are 9 bits to determine the location of a time-slot.
According to the value programmed via those bits, the receive/transmit window (time-slot)
starts with a delay of 1 (minimum delay) up to 512 clock periods following the frame
synchronization signal and is active during the number of clock periods programmed via
RCCR, XCCR (number of bits to be received/transmitted within a time-slot) as shown in
figure 23.
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Figure 23
Location of Time-Slots
The transmit time-slot is additionally indicated by a control signal via T × CLK, which output is
set to log 0 during the transmit window.
Note: In extended transparen t mode the width of the time-slots has to be n × 8 bit.
ITD00240
Time Slot Number
TSN (6 Bits) Clock Shift
CS (3 Bits)
9 Bits
2XCS 1 0
RCS01RCSRCS2
XCS XCS CCR2
TSNR
TSNX
TSAR
TSAX
Register :
N
TIME SLOT
DELAY
1+ SNx8 + CS
(1...512 Clocks)
WIDTH
Via RCCR, XCCR
(1...256 Clocks)
CD
R x CLK
T x CLK
~
~~
~
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RTS Signal in Clock Mode 5
When using the RTS signal in clock mode 5, it has to be considered, that the RTS signal is
deactiva ted a fter the tran smissio n of t he second last bi t (inst ead o f th e la st) of a closi ng fla g, if
that second last bit is the last bit of a time-slot “window“. In other words, RTS is inactive during
the transmission of the last bit, transmitted in the next time-slot window. See figure 24.
Figure 24
ITD05965
INT
XPR Int Status
RTS
TxD
TxCLK
(TS,- Ctrl)
Time-Slot n Time-Slot n + 1
IDLE, interframe time-fill
D = Valid data bitsDDD...D D Last bit of a frame
Last bit of closing flag
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This must be considered for applications, where several transmitters are sharing the same
time-slot on a non open-drain bus, e.g. a balanced bus, not using collision detection as the
resolution mechanism. One such application is slave stations in a point-to-multipoint
configuration sharing the same time-slot and using NRM auto-mode. Thus, RTS and the time -
slot marker TxCLK cannot simply be gated to generate a driver control signal. Instead the
foll owing recommendations apply:
a) Do not use the RTS signal directly in clock mode 5 e.g. to enable drivers for TxD in a
balanced bus configuration. Instead, use an arrangement of the type shown in the figure 25
or
Figure 25
ITD05980
HSCX
TxD
D
V
DD
SS
V
Transmission Line
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b) de lay the rising edge of RTS (e.g. for NRM mode with balanced bus).
Figure 26
Timing diagram for recommendation b ) :
Figure 27
DQ
CLK CLK
QD
&
1
Bus
ITD05966
HSCX
RTS
TxCLK
TxD
_
<
ITD05981
INT
XPR Int Status
RTS
(rec. b)
RTS
ideal
RTS
TxD
TxCLK
(TS-Ctrl)
Time-Slot n Time-Slot n + 1
IDLE, interframe time-fill
D = Valid data bitsDDD...D D Last bit of a frame
Last bit of a closing flag
Semic onduct or Grou p 55
SAB 82525
SAB 82526
SAF 82525
SAF 82526
CTS Signal in Clock Mode 5
In clock mode 5 the CTS signal is evaluated not only in the time-slot “window“, but also
between the time-slot “windows“. If data transmission must not be stopped, CTS has to be
active, even between the time-slot “windows“, until the transmission of the frame has been
completed. In other words, a deactivation of CTS stops the transmitter immediately.
Note: When several HDLC channels are sharing the same time-slot on a bus without using
the bus collision detection, the strobe signals (AxCLKA/B) can be used to select/
deselect particular time-slot “windows“ for an individual HDLC channel.
Clock Mode 6 (OSC – Receive Clock from DPLL)
This clock mode equals the features of Clock Mode 2, with the only exception that the clock for
the BRG is delivered by the OSC and must not be provided externally.
Clock Mode 7 (OSC – Receive and Transmit Clock from DPLL)
Similar to Clock Mode 3, but BRG clock is provided by OSC.
Semic onduct or Grou p 56
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Summary
The features of the different clock modes are summa rized in table 6.
Table 6
Clock Modes of HSCX
Note: 1) The max imum data rat e in an extern ally clo cke d oper ating mod e is 4.1 Mb it/s. In an
internally clocked operating mode with an external reference clock, or using the OSC,
the maximum clock rate is 12 MHz or 19.2 MHz if the scaling factor of the BRG is
progra mmed to 1. The maximum data rate will be 1200 kbit/s.
2) The ratio between the receive frequency (fr) and the transmit frequency (fx) for a
channel mu st satisfy the condition fr/fx less than 3 in clock modes 0, 2, 6; there are no
restrictions on the phase shift. Slower transmit data rates can be realized with receive
and transmit strobes (clock mode 1).
3) The clo ck m od es 4 , 6 , 7 use the inter nal OSC and need a n e xter n al qu ar tz cr ysta l to
be connected at the RxCLK A-AxCLK A pins.
It is not necessary to use two separate crystals for the two serial channels, instead it is
sufficient to apply the crystal to channel A and provide the reference clock for channel
B by externally connecting the AxCLKA and RxCLKB pins. The SAB 82526 also uses
the RxCLK A-AxCLK A pins to connect to an external quartz crystal.
Channel C onfiguration Clock Sou r ces Control So urces Timer
Source
Clock Mode
CCR1
CM2, CM1, CM0
CCR2 Output
via
TxCLK
TSS TIO BRG DPLL REC TRM CD R-Strobe X-Strobe F-Sync TCP
0
1
2
2
3
4
4
5
6
6
6
7
7
0
0
0
1
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
1
0
0
0
1
0
1
–
–
RxCLK
RxCLK
RxCLK
–
–
–
OSC
OSC
OSC
OSC
OSC
–
–
BRG
BRG
BRG
–
–
–
BRG
BRG
BRG
BRG
BRG
RxCLK
RxCLK
DPLL
DPLL
DPLL
OSC
OSC
RxCLK
DPLL
DPLL
DPLL
DPLL
DPLL
TxCLK
RxCLK
TxCLK
BRG/16
DPLL
OSC
OSC
RxCLK
TxCLK
BRG/16
BRG/16
DPLL
DPLL
AxCLK
–
AxCLK
AxCLK
AxCLK
TxCLK
…
TxCLK
–
TxCLK
–
TxCLK
–
–
AxCLK
–
–
–
–
–
(TSAR)
–
–
–
–
–
–
TxCLK
–
–
–
–
–
(TSAX)
–
–
–
–
–
–
–
–
–
–
–
–
AxCLK
–
–
–
–
–
–
–
–
BRG/16
DPLL
–
OSC
TS-Control
–
–
BRG/16
–
DPLL
TxCLK
RxCLK
TxCLK
DPLL
DPLL
OSC
OSC
RxCLK
TxCLK
BRG/16
BRG/16
DPLL
DPLL
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Semic onduct or Grou p 57
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Normall y 33 pF ca pacitors are used for freque ncies belo w 10 MHz and 2 2 pF capa citors are
used for frequencies above 10 MHz.
To guarantee oscillation use the ca pacitances which are specified by the crystal manufacturer.
ITS01450
RxCLKA
AxCLKA
5.2 Clock Recov ery (DPLL)
The HSCX offers the advantage of recovering the receive clock from the receive data by
means of internal DPLL circuitry, thus eliminating the need to transfer additional clock
information via the serial link.
For this purpose, the DPLL is supp li e d wit h a re fe re nce clock fro m BRG w hic h is 16 times th e
data clock rate (clock mode 2, 3, 6, 7). Additionally, the transmit clock may be obtained dividing
the output of the BRG by a constant factor of 16 (clock mode 2, 6; TSS bit in CCR2 set) or also
directly from the DPLL (clock mode 3, 7).
Figure 28a
The DPLL ci rcuits imp lemented in the HSC X are opt imized with re spect to the H DLC proto col.
The main task of the DPLL is to derive a receive clock and to adjust its phase to the incoming
data stream in order to enable the bit sampling in the middle of a bit-cell with the falling edge
of the receive clock. For this purpose, edges in the receive data, indicating the begin of a bit-
cell, are necessary.
When using the NRZI encoding, the zero insert/zero delete method ensures that a sufficient
number of edges occur in the data stream during the reception of an HDLC frame. Furthermore
a completely new "one insertion" mechanism has been implemented with the HSCX, which
also guarantees sufficient number of edges when using NRZ encoding (especially for bus
configurations, see chapter 6.5 for details).
ITT06028
Interference Rejection
RxD
DPLL CLK
1Rec. Data 1
Semic onduct or Grou p 58
SAB 82525
SAB 82526
SAF 82525
SAF 82526
The following functions have been implemented to facilitate a high-speed and reliable
synchronization (see figures 28).
– Interference Rejection
In the case where two or more edges appear in the data stream within a time period of 16
reference clocks, these are detected as interference without performing additional
adjustments.
Figure 28b
– Phase Adjustment
In the case where an edge with a p hase angle of 20 to 112 degrees appears in the data stream
within the time window, the pha se will be adjusted by 1/16 of the da ta clock.
Figure 28c
ITT00241
Rec. Data 10
DPLL CLK
Phase Adjustment
DxR φφφ
ITS06029
DPLL
Receiver
Receive
Clock
Receive Data
Reference Clock
16
Data Clock Rate
=
x Nominal
Semic onduct or Grou p 59
SAB 82525
SAB 82526
SAF 82525
SAF 82526
– Phase Shift
In the case the DPLL de tects an edge in the data stream in the range of DPLL count 5 to 10
(Phase Shift) and this is the only one in the assumed bit cell period, then the DPLL receive
clock phase is shifted by a certain DPLL count value.
Figure 28d
Synchronization of the Data Clock in DPLL Mode: Interference Rejection and Phase
Adjustment
The DPLL value and its corresponding phase shift in degree is listed below for the HSCX
versions VA3 and V2.1:
Note: The operating characteristics of the DPLL therefore allow a phase jitter of 18.75% of the
frequency.
HSCX Version DPLL Count Phase Shift
VA3 8 180o
V2.1 7 157,5o
ITD05884
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Phase Adjust Phase Shift
+
-
Assumed Bit Cell
DPLL Input
Receive Data
DPLL Count
DPLL
Phase Correction
DPLL Output
Receive Clock
++17 1-Phase Adjust
Phase Shift
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Semic onduct or Grou p 60
5.3 Bus Configuration
Besid e the po int-to-poin t config uration, the HSCX e ffectivel y suppor ts point- to-multip oint (pt-
mpt, or bus) configurations by means of internal idle and collision detection/collision resolution
methods.
In a pt-mpt configuration, comprising a central station (master) and several peripheral stations
(slaves) , or in a multi master co nfig uratio n (see figure 6), data transmission can be initiated by
each station over a common transmit line (bus). In case more than one station attempt to
transmit data simultaneously (collision), the bus is assigned to one station by a collision-
resolution pr ocedure implemented by the HSCX. The bus assignment function is based on a
priority principle wi th both fixed and rotating priorities that enables each station to access the
bus in a predeterminable time. As a result, any number of transmitters can be connected to the
serial bus.
Prerequisites for bus operation are:
– NRZ encoding
– OR conn ection of data at the bus
– feedback of bus information (C×DA/C×DB input)
The bus c onfiguration is selected via the CCR1 re gister.
Note: Central clock supply for each station is not necessary if both the receive and transmit
clock is recovered by the DPLL (clock mode 7). In this case, the function of the DPLL
also minimizes the phase shift betwee n the transmit clocks of t he individual transmitters
so that an opening flag se que nce w ill be suff i cie nt to allow a corr ect co llis ion detection.
The bus m ode can be oper ated in depen dentl y of th e clo ck mode, e .g. al so du rin g clock
mode 1 (receive and transmission strobe) or clock mode 5 (programmable ti me-slots).
Semic onduct or Grou p 61
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Since a transmitted zero is given priority over a 1 due to the OR connection at the bus, and
since the individually combined stations in the address field of the transmitted HDLC frame
differ from one another, the fact that a collision has occurred will be detected pr ior to or at the
latest within the address field. The fram e of the transmitt er with the highest temporar y priority
(address field) is not affected and is transmitted without interruptions. All other transmitters
terminate their operation immediately.
Note: If a wired OR connection has been realized by an external pull- up resistor without decoupling,
the data output (T×DA/T×DB) can be used as an open drain output and connected directly to
the C×DA, C×DB input.
Priority Principle
When the HDLC frame has been successfully transmitted by the HSCX, the priority is
decremented. In order to transmit an additional frame, ten successive 1’s must be present on
the bus. This fact is used as a criterion to ensure that the higher priority transmitters do not
contain any transmit requests. It is now possible to transmit a frame and the priority can be
increased again (8 successive 1’s). This method offers a priority allocation based on the
selection of a part icular ad dress. It a lso en sures t ha t each su bscribe r can a ccess t he b us a t a
pre-determinable time.
Timing Modes
If a bus configuration has been selected, the HSCX provides two timing modes, differing in the
period between sending data and evaluation of the transmitted data for collision detection.
timin g mode 1 (C CR1: SC1, SC0 = 01)
Data is output with the rising edge of the tran smit clock via the T×D pins, and eva l uat ed
1/2 clock period later with the falling clock edge at the C×D pins.
timin g mode 2 (C CR1: SC1, SC0 = 11)
Data is output with the falling clock edge and evaluated with the next falling clock edge.
Thus one complete clock period is available during data output and their evaluation.
Note: If the bus is occupied by other tran smitters and/or there is no t ransmit request in the HSCX, log 1
will be continuously transmitted at the T×DA/T×DB output.
Bus Access Procedure
The idle state of the bu s is ident if ied by eight or more su ccessive 1 ’ s. In case o f a tran smit re-
quest in th e HSCX, the frame is tra nsmitted an d the bus is ide ntified as b usy with the fir st zero
of the opening flag (start flag).
After the frame has been transmitted, the bus bec omes available a gain by transmitting 1’s.
Collisions
During the transmitting process, the data transmitted from the HSCX is compared with the data
on the bus. In case an erroneous bit is detected (log 1 sent and log 0 detected, or vice versa)
the frame is immediately aborted, and idle (log 1) is transmitted. Transmission will be initiated
again by the HSCX as soon as possible.
Semic onduct or Grou p 62
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Functions of RTS Output
In clock modes 0, 1, 4 and 5, the RTS output can be programmed via CCR2 (SOC bits) to be
active when a frame is being transmitted. The signal is delayed by one clock period with
respect to the data output T×DA/T×DB, and marks all data bits that could be transmitted without
collision. In this way a configuration may be implemented in which the bus access is resolved
on a local basis (collision bus) and where the data are sent one clock period later on a separate
transmission line.
If the RTS output is used to control an external driver it has to be ANDed with the TxD pin in
order to drive the first bit correctly.
Figure 29
Request-to-Send in Bus Operat ion
ITS02701
&
CxDA/B
TxDA/B
RTSA/B
Line
ITT00242
Collision
RTS
TDx
xDC
Note: For regular and special RTS functions refer to chapter 5.5 and 6.6.
Semic onduct or Grou p 63
SAB 82525
SAB 82526
SAF 82525
SAF 82526
5.4 Data Encoding
In the point-to-point configuration, the HSCX supports both NRZ and NRZI data encoding
(selectable via CCR1 reg ister).
Figure 30
NRZ Encoding/NRZI Encoding
During NRZI encoding, level changes are interpreted as log 0, and no changes in level as
log 1. Sinc e no mo re tha n 5 su ccess ive lo g 1’s can appe ar in a HDLC frame , this typ e of e n-
coding is especially suitable in clock modes, where the clock is recovered from the received
data b y m e ans o f the D P LL ci rc uits, because a t le ast one transi tion appears wi thi n 5 cl ock cy-
cles.
Thus, NRZI coding is especially recommended in clock modes 2, 3, 6, 7.
Data output is pe rformed with the risi ng, data input with the falling clo ck edge.
5.5 Modem Control Functions (RTS/CTS, CD)
RTS/CTS Handshaking
The HSCX provides two pins (RTS, CTS) per serial channel supporting the standard RTS-CTS
modem handshaking procedure to control the HDLC transmitters.
Data output is performed with the rising clock edge, data input with the falling clock edge. A
transmit request will be indicated by outputting log 0 at the request-to-send output (RTSA/
RTSB). It is also possible to program the RTS outputs by software. After having received the
permission to transmit (CTSA/CTSB) the HSCX tran smits a frame.
In the case where permission to transmit is withdrawn during the transmission process, the
frame is aborted (idle). After a new permission to transmit has been received and if all of the
data are still available in the HSCX, the terminated frame will be re-transmitted (self-recovery),
without interrupting the CPU. However, if the permission to transmit is withdrawn after the 32nd
byte in the information field, the transmitter and the XFIFO are reset, the RTS output is deac-
tivated and an interrupt is generated for the µC.
ITT00243
01
1
00
111 0
NRZI Encoding
NRZ Encoding
0
11
0
1
Semic onduct or Grou p 64
SAB 82525
SAB 82526
SAF 82525
SAF 82526
CTS Signal Clock Mode 5
In clock mode 5 the CTS signal is evaluated not only in the time-slot "window", but also
between the time-slot "windows". CTS must not be disabled during the transmission of a
frame. Even between the time-slot "windows" CTS has to be active until the transmission of
the fr ame ha s been com pleted . Thus, CTS cannot be used to select/deselect particular time-
slot "windows" for HSCX.
Note: In the case where pe rmission to transmit is not r equired, th e CTSA/CTSB in puts can be
connected directly to VSS.
Additionally, any state transition o n the CTS input pin will gene rate an interrupt indica ted via
the EXIR register, if this function is enabled by setting the CIE bit in the CCR2 register.
Figure 31
RTS-CTS Handshaking
ITT00244
Sampling
CTS
T CLKx
xDT
RTS
~
~~
~~
~~
~
Carrier Detect (CD) Receiver Control
Similar to the RTS/CTS control for the transmitter, the HSCX supports the carrier detect
modem control functio n for the serial receivers, if the Carrier Detect Au to S tart (CAS) function
is programmed setting the CAS bit in the XBCH register. This function is always available in
clock modes 0, 2, 3 via the A×CLK pin, an d i n clock modes 4 , 6, 7 via the T × CLK pin only if it
has been programmed as input clearing the TIO bit in the CCR2 register. In clock mode 1 the
CD function is not supported (see table 6 for an overview).
If the CAS functi on is se lected , the respe ctive H DLC rece iver is enab led and data r eception is
started when an high level is sampled at the CD input.
Semic onduct or Grou p 65
SAB 82525
SAB 82526
SAF 82525
SAF 82526
This feature can be profitably used e.g. for:
FLAG in ser ti o n and deletion
CRC gene ration and checking
Bit-stuff ing me chanism.
6 Special Functions
6.1 Fully Transparent Transmission and Reception
When programmed to the extended transparent mode via the MODE register (MDS1,
MDS0 = 11), each channel of the HSCX supports fully transparent data transmission and
reception without HDLC framing overhead, i.e. without
In order to enable fully transparent data transfer, RAC bit in MODE has to be reset and FFH
has to be written to XAD1, XAD2 and RAH2.
Data transmission is always performed out of the transmit FIFO by directly shifting the contents
of the XFIFO via the serial transmit data pin (T×D). Transmission is initiated by setting
CMDR : XTF (08H); end of transmission is indicated by EXIR : EXE (40H).
In receive direction, the character currently assembled via the receive data line (R×D) is
available in the RAL1 register. Additionally, in extended transparent mode 1 (MODE: MDS1,
MDS0, ADM = 111), the received data is shifted into the RFIFO.
user specific protocol variations
the application of character oriented protocols (e.g. BISYNC)
test purposes, lin e intentionally violation of HDLC protocol rules (e.g. wrong CRC)
Character synchronization can be achieved either in
clock mode 1, with an e xternal receive strobe input to A×CLK pin, or
clock mode 5, with a programmed time-slot and a frame synchronization signal input to
A×CLK.
Using clock mode 1 or 5 multiples of 8 bits received per time-slot.
6.2 Cyclic Transmission (Fully Transparent)
If the extend ed transparent mode i s selected, the HSCX sup ports the continuou s transm ission
of the transmit FIFO’s contents.
After having written 1 to 32 bytes to the XFIFO, the command
XREP.XTF.XME
via the CMDR reg ister (bit 7. . .0 = "001010 10" = 2 AH) forces the HSCX to repea tedly tran smit
the data stored in the XFIFO via T×D pin.
The cyclic transmission continues until a reset command (CMDR : XRES) is issued, after
which continuous ’1’-s are transmitted.
Note: In DMA-mode the command XREP, XTF has to be written to CMDR.
Semic onduct or Grou p 66
SAB 82525
SAB 82526
SAF 82525
SAF 82526
SAB 82525
SAB 82526
SAF 82525
SAF 82526
6.3 Continuous Transmission (DMA Mode only)
If data transfer from system memory to the HSCX is done by DMA (DMA bit in XBCH set), the
number of bytes to be transmitted is usually defined via the Transmit Byte Count registers
(XBCH, XBCL : bits XBC11. . .XBC0).
Setting the "Transmit Continuously" (XC) bit in XBCH, however, the byte count value is ignored
and the DMA interface of the HSCX will continuously request for transmit data any time
32 bytes can be stored in the XFIFO.
This fe ature can be used e.g. to
Note: If the XC bit is res et duri ng cont inuous transm ission, t he tr ansmit b yte coun t beco mes
valid again, and the HSCX will request the amount of DMA transfers programmed via
XBC11. . .XBC0. Otherwise the continuous transmission is stopped when a data
underrun condition occurs in the XFIFO, i.e. the DMA controller does not transfer further
data to the HSCX. In this case continuous ’1’-s (IDLE), without appendin g a CRC, are
transmitted.
1) The frame length includes all bytes which are stored in the RFIFO.
6.4 Receive Length Check Feature
The HSCX offers the possibility to supervise the maximum length of received frames and to
terminate data reception in case this length is exceeded.
This feature is controlled via the special Receive Length Check Register (RLCR).
The function is enabled by setting the RC (Receive Check) bit in RLCR and programming the
maximum frame length via bits RL6. . .RL01).
According to the value written to RL6. . .RL0, the maximum receive length can be adjusted in
multiples of 32-byte blocks as follows:
MAX. LENGTH = (RL + 1) × 32.
All frames exceeding this length are treated as if they have been aborted from the opposite
station, i.e. the CPU is in formed via a
– RME interrup t, and the
– RAB bit in RSTA register is set!
To distingu ish bet ween frame s reall y abo rted from t he opposite stati on, t he re ceive byte co unt
(readable from RBCH, RBCL registers) exceeds the maximum receive length (via RL6. . .RL0)
by one or two bytes in this case.
The check i n clu de s a ll data that is copied into t he RF IFO. It does not inclu de th e address byte
(s) if address recognition is selected. It includes the RSTA value in all operating modes.
continuously transmit voice or data onto a PCM highway (clock mode 5/extended
transparent mode), or to
transmit frames exceeding the byte count programmable via XBCH, XBCL (frames with
more than 4095 bytes).
Semic onduct or Grou p 67
SAB 82525
SAB 82526
SAF 82525
SAF 82526
6.5 One Bit Insertion
Simil ar to the ze ro bi t inser tion (b it-st uffin g) me chanism , as defi ned by the HD LC prot ocol, t he
HSCX offers a completely new feature of inserting/deleting a one after seven consecutive
zeros in the transmit/receive data stream, if the serial channel is operating in a bus
configuration.
This method is pr ofitable if clock rec ov ery should be perfo rmed by DPLL.
Since only NRZ data encoding is supported in a bus configuration (see chapter 5.4), ther e are
possibly long sequ ence s witho ut e dges in the receive da ta st ream in ca se o f succe ssive "0"-s
received, and the DPLL may loose synchronization.
Using the one bit insertion feature by setting the OIN bit in the CCR1 register, however, it is
guaranteed that at least after
– 5 consecutive "1"-s a "0" will appea r (bit-stuffing), and
– 7 consecu t ive "0"-s a "1" will appear (one insertion)
and thus a correct function of the DPLL is ensured.
Note: As with the bit-stuffing, this method is fully transparent to the user, but it is not in
accordance with the HDLC protoc ol, i.e. it can on ly be applied in private systems using
HSCX circuits exclusively.
6.6 Dat a Inve rsion
When NRZ data encoding has been selected, the HSCX may transmit and receive data
inverted, i.e. a
"one" bit is transmitted as phys. zero (0 V) and a "zero" bit as phys. one (+ 5 V) via the T×D line.
This feature is selected by setting the DIV bit in the CCR2 register.
Please note that data cannot be inverted in bus mode unless you invert the T×D / R×D signal
before it is sent into C×D.
ITD00245
Transmit
Receive
Log. Data Bit 1
0Phys. Level
5
0
V
V
+
Semic onduct or Grou p 68
SAB 82525
SAB 82526
SAF 82525
SAF 82526
6.8 Test Mode
To provid e for fast and effi cient t esting, th e HSCX can be o perated in th e test mod e by sett ing
the TLP bit in the MODE register.
The on-chip serial input and output (T ×DA – R×DA, T×DB – R×DB) are co nnec ted ge nera ting
a local lo opback.
R×DA and R ×DB input is ignored. T×DA and T×DB remain active.
As a result, the user can perform a self-test of the HDLC channels of the HSCX.
6.7 Special RTS Function
Beyond the regular RTS function, signifying the transmission of a frame (Request To Send),
the RTS output may be programmed for a special function via SOC1, SOC0 bits in the CCR2
register, provided the serial channel is operating in a bus configuration in clock mode 0, 1, or 5.
– If SOC1, SOC0 bits are set to ’11’; the RTS output is active (= low) during the
reception of a frame.
– If SOC1, SOC0 bits are set to ’10’; the RTS output function is disabled and the RTS
pin remains always high.
Semic onduct or Grou p 69
SAB 82525
SAB 82526
SAF 82525
SAF 82526
7 O perational Description
7.1 RESET
The HSCX is forced into th e reset sta te if a high signal is inpu t to the RE S pin for a minim um
period of 1.8 µs. During RESET, the HSCX is temporarily in the power-up mode, and a subset
of the registers is initialized with defined values.
After R ESET, the HSCX is in po wer down mo de, and t he following r egisters contain define d
values:
Table 7
RESET Values
Register RESET
Value Meaning
CCR1 00H– power down mod e
serial po rt con figura tion; pt-pt, N RZ coding , tran smit data pins
are open drain outputs
– clock mode 0
CCR2 00HRTS pin norm al function
– CTS and RFS interrupts disabled no data in version
MODE 00Hauto-mode
1 byte address field
external timer mode
– receivers inactive
RTS output contr olled by HSCX, timer resolution:
k = 32.768, no testloop
STAR 48HXFIFO write enable
receive line i nact ive
no commands exe cuting
ISTA
EXIR 00H– no interrupts masked
CMDR 00Hno commands
XBCH
RBCH 00H– interrupt controlled data transfer (DMA disabled)
– full-duplex LAPB/LAPD operation of LAP controller
– carrier detect auto start of receiver disabled
XCCR
RCCR 00H1-bit time-slot
Semic onduct or Grou p 70
SAB 82525
SAB 82526
SAF 82525
SAF 82526
7.2 Initialization
After reset the CPU has to write a minimum set of registers and an optionally set dependent
on the required featur es and operating modes.
First, the configuration of the serial port and the clock mode has to be defined via the CCR1
register. The clock mode must be set before power-up, or in the same step with power-up.
The CPU may switch the HSCX between power-up and power-down mode, which has no
influence upon the contents of the re gisters, i.e. the internal state remains store d.
In powe r-down mode however, all internal clocks and the o scillator circuitry are disab led, no
interrup ts are forwarded to the CPU.
This state can be used as standby mode, when the HSCX is temporarily not used, thus
lessening the power consumption to a high degree.
The individual operating mode must be defined writing the MODE register.
The need for programming further registers depends on the selected features (clock mode,
operating mode, address mode, user demands) according to the following tables:
Clock Mode Register
0, 1 –
2, 3, 4, 6, 7 BGR, CCR2
5 CCR2, TSAR, TSAX, XCCR, RCCR
Address
Mode
Operating
Mode
2 Byte
Address Field
(MODE: ADM = 1)
1 Byt e
Address Field
(MODE: ADM = 0)
Table 8
Register Setup
Auto
Non Auto
RAH1
RAH2
RAL1
RAL2
RAH1 set to 00H
RAH2 set to 00H
RAL1
Transparent RAH1
RAH2 –
TIMR
XAD1
XAD2
RAH1
RAH2
RAL1
RAL2
RAH1 set to 00H
RAH2
RAL1
RAL2
Semic onduct or Grou p 71
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Table 9
User Demand Registers
User Demand Register
CTS/RFS Interrupt Provided CCR2
Selec tive Interrup ts Shou l d be Masked MASK
Timer will be used by CPU (external timer mode) TIMR
DMA Controlled Data Transfer XBCH
Receive Length Check Feature RLCR
Extended (module 128) Counting RAH2
7.3 Operational Phase
After having performed the initialization, the CPU switches each individual channel of the
HSCX into operational phase by setting the PU bit in the CCR1 register (power-up, if not
alread y done during initialization).
Initially, the CPU should bring the transmitter and receiver to a defined state by issuing a XRES
(transmitter reset) and RHR (receiver reset) command via the CMDR register. If data reception
should be performed, the receiver must be activated by setting the RAC bit in MODE to 1.
If no "Clear to send" function is provided via a modem, the CTS pin of the HSCX must be
connected directly to ground, in order to enable data transmission.
Now the HSCX is ready to transmit and receive data. The control of the data transfer phase is
mainly done by commands from CPU to HSCX via the CMDR register, and by interrupt
indications from HSCX to CPU.
Additional status information, which does not trigger an interrupt, is available in the STAR
register.
7.4 Data Transmission
Interrupt Mode
In transmit direction 2×32 byte FIFO buffers (transmit pools) are provided for each channel.
After checking the XFIFO status by polling the Tran smit FIFO Write Ena ble bit (XFW in STAR
register ) or afte r a Transmit Pool Re ady (XPR) in terrup t, up to 32 bytes m ay be entere d by the
CPU to the XFIFO.
The transmi ssion of a frame can then be started i ssuing a XTF or XI F command via the CMD R
register. If the transmit command does not include an end of message indication
(CMDR : XME), the HSCX will repeatedly request for the next data block by means of a XPR
interrupt as soon as no more than 32 bytes are stored in the XFIFO, i.e. a 32-byte pool is
accessible to the CPU.
This process will be repeated until the CPU indicates the end of message per comma nd, after
which frame transmission is finished correctly by appending the CRC and closing flag
sequence.
In case no more data is available in the XFIFO prior to the arrival of XM E, the transmission of
the frame is terminated with an abort sequence and the CPU is notified per interrupt
(EXIR : XDU). The frame may also be aborted per software (CMDR : XRES ) .
The data transmission sequence, from the CPU’s point of view, is outlined in figure 32.
Semic onduct or Grou p 72
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Figure 32
Interrupt Driven Data Transmission (Flow Diagra m)
The activities at both serial and CPU interface during frame transmission (supposed frame
length = 70 bytes) is shown in figure 33.
Figure 33
Interrupt Driven Transmission Sequence Example
ITD00246
XPR Interrupt or
XFW Bit in STAR Register = 1
N
Command
XTF XIF
/Write Data
(up to 32 Bytes)
to XFIFO
End of
Massage
?
Command
/
XTF XIF +XME
END
Transmit
Pool Ready
?
START
N
Y
Y
Serial
Interface
HSCX
CPU
Interface
ITD00247
WR XTF
Bytes32
. . . . . .
32 Bytes
WR Command WR
Bytes6
. . .
XPR
XTF + XME
XPR
XPR
XTF
Transmit
32 32 6
Frame (70 Bytes)
Semic onduct or Grou p 73
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Back to Back Frames
If two or mo re fr ames sh ould be tr ansm itted i n a high sp eed seq uence wi thout i nterfr ame t ime
fill, the transmissio n sequence according figure 34 has to be used.
This means that the closing flag wil l be immediately followed by an opening flag. The HSCX
receiver, however, is c apable of receiving frames separate d by only one (shared) flag.
Figure 34
Continuous Frames Transmission (Flow Diagram)
ITD05883
START
Transmit
Pool Ready
?
Y
XFIFO
Last Frame
?
XPR Interrupt or
XFW Bit in STAR Register = 1
: Data
?
END
FRAME
XTF:CMDR
?
Pool Ready
Transmit
Y
CMDR : XTF
END
+XME
Y
Y
CMDR : XME
_
<
( 32 Bytes)
Semic onduct or Grou p 74
SAB 82525
SAB 82526
SAF 82525
SAF 82526
The activities during frame transmission (supposed two frames, 18 bytes and 52 bytes) is
shown in figure 35.
Figure 35
Continuous Frames Transmission Sequence Example
Serial
Interface
HSCX
CPU
Interface
ITD00249
18
WR XTF
Bytes18
. . .
XME
. . .
32 Bytes
WR XTF WR
Bytes20
. . .
XTF
XPR
XTF + XME
XPR
ITF Bytes 32
Frame 1Bytes Frame 2Bytes20 ITF
XPR XPR
DMA Mode
Prior to the data transmission, the length of the next frame to be transmitted must be
programmed via the Transmit Byte Count Registers (XBCH, XBCL). The resulting byte count
equals the programmed value plus one byte, i.e. since 12 bits are provided via XBCH, XBCL
(XBC11. . .XBC0) a frame length of 1 up to 4096 bytes (4 Kbytes) can be selected.
After this, data transmission can be initiated by command (XTF or XIF). The HSCX will then
autonomously request the correct amount of write bus cycles by activating the DRQT line.
Depending on the programmed frame length, block data transfers of
n × 32-bytes + re mainder (n = 0, 1,…128)
are requested everytime a 32-byte FIFO half (transmit pool) is empty and accessible to the
DMA controlle r.
Semic onduct or Grou p 75
SAB 82525
SAB 82526
SAF 82525
SAF 82526
The following figure gives an example of a DMA driven transmission sequence with a
supposed frame length of 70 bytes, i.e. programmed transmit byte count (XCNT) equal
69 bytes.
Figure 36
DMA Driven Transmission Sequence Example
WR
XCNT
WR
XTF
Transmit Frame (70
Serial
Interface
HSCX
CPU/DMA
Interface
ITD00250
(69) DRQT(32)
WR
. . .
WR
DRQT(32)
WR WR
DRQT(6)
WR
32 32 6
DMA Write Cycles (70) XPR
. . .
. . .
Bytes)
7.5 D at a Re ce ption
Interrupt Mode
Also 2×32 byte FIFO buffers (receive pools) are provided for each channel in receive direction.
There are two di fferent interr upt indications concerned with the r eceptio n of data :
– RPF ( Receive Pool Full) interrupt, indicating that a 32 b yte block o f data can be read from
the RFIFO and the received message is not yet complete.
– RME (Receive Message End) interrupt, indicating that the reception of one message is
completed, i.e. either
one message with less than 32 bytes, or the
last part of a message with more than 32 bytes
is stored in the RFIFO.
After an interrupt has been processed, i.e. the received data has been read from the RFIFO,
this mu st be explicitly acknowledged by the CPU issuing a RMC (Receive Message Complete)
command.
The CPU has to handle the RPF i nterrupt bef ore additio nal 32 bytes are r eceived via the se rial
interface which w ould cause a "Recei ve Data Overflow" condition.
Semic onduct or Grou p 76
SAB 82525
SAB 82526
SAF 82525
SAF 82526
In addition to the message end (RME) interrupt, the following information about the received
frame is stored by the HSCX in special registers and/or RFIFO:
Table 10
Status Information after RME Interrupt
Length of message (bytes) RBCH, RBCL register
Address com bina ti on and/o r RSTA RFIFO: last byte
RAL1 RFIFOAddress fiel d
RHCR RFIFOControl fiel d
RSTA RFIFO: last byteType of frame (COMMAND/RESPONSE)
RSTA RFIFO: last byteCRC result (good/bad)
RSTA RFIFO: last byteValid frame (yes/no)
RSTA RFIFO: last byteABORT sequence recognized (yes/no)
RSTA RFIFO: last byteData overflow
Semic onduct or Grou p 77
SAB 82525
SAB 82526
SAF 82525
SAF 82526
The following figure gives an example of an interrupt controlled reception sequence, supposed
that a long fr ame (66 bytes) followed by two short frames (6 bytes each) are rec eived.
Figure 37
Interrupt Driven Reception Sequence Example
Serial
Interface
HSCX
CPU
Interface
ITD00251
RPF RMC
RD
32 32RD
RMCRPF RME RMC RMCRME RME RMC
RD Status
32 32 2 6 6
Receive Frame Bytes)
Bytes Bytes
RD Count
RD Count
RD Status
. . . . . . ... ... ...
RD Count
RD Status
1(66
DMA Mode
If the RFIFO contains 32 bytes, the HSCX autonomously requests a block data transfer by
DMA activating the DRQR line a s long as the start of the 32nd read cycle. This forces the DMA
controller to continuously perform bus cycles till 32 bytes are transferred from the HSCX to the
system memory.
If the RFIFO contains less than 32 bytes (one short frame or the last part of a long frame) the
HSCX r equests a bl ock data tran sfer depen ding on the contents of the RFIFO according t o the
following table:
RFIFO
Contents
(Bytes)
DMA
Request
(Bytes)
1, 2, 3
4 - 7
8 - 15
16 - 32
4
8
16
32
Note: All available status informations after RME are summarized in table 10.
Semic onduct or Grou p 78
SAB 82525
SAB 82526
SAF 82525
SAF 82526
After t he DMA contro ller ha s been set up for th e recepti on of the next f rame, the CPU must be
issue a RMC command to acknowledge the completion of the receive frame processing.
The HSCX will not initiate further DMA cycles by activating the DRQR line prior to the reception
of RMC.
Note: It’s also possi b le to set up the DMA con tr ol ler im m edi a tely after the sta rt o f a fr ame has
been detected using the HSCX’s RFS (Receive Frame Start) interrupt option (see
chapter 4.3).
The foll owing fi gure gives an example of a DMA controll ed reception se quence, supp osed that
a long frame (66 bytes) followed by two short frames (6 bytes each) are received.
Figure 38
DMA Driven Reception Sequence Example
Serial
Interface
HSCX
CPU/DMA
Interface
ITD00252
RME
32 32 2 6
RF2
RMC
Receive Frame
(66
DMA Read Cycles (68)
DRQR(8)
. . . . . .
DRQR(8)
RD
. . .
DRQR(4)DRQR(32)
. . .
RD RDRDRD
. . .
DRQR(32)
RF3
6
RD Count
1
Bytes)
RD RD
RME RMC
RD RD RD
RME RMC
RD Count
RD Count
Semic onduct or Grou p 79
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SAB 82526
SAF 82525
SAF 82526
8 Detailed Register Description
8.1 Register Address Arrangement
Table 11
Layout of Register Addresses
ABReadWrite
Refer
to
page:
ADDRESS REGISTER
Channel
73 74
00
1F
:
:
40
5F
:
:RFIFO X FIFO Receive/Transmit FIFO
75 7620 60 ISTA MASK Interrupt STAtus/Mask
79 8021 61 STAR CMDR STAtus/CoManD
8222 62 MODE MODE
8423 63 TIMR TIMer
85 8524 64 EXIR XAD1 EXtended Interrupt/Transmit ADdress 1
86 8625 65 RBCL XAD2 Receive Byte Count Low/Transmit ADdress 2
–8726 66 – RAH1 Receive Addre ss High 1
87 8727 67 RSTA RAH2 Receive STAtus/Rec. Addr. High 2
9028 68 RAL1 Receive Address Low 1
91 9029 69 RHCR RAL2 Receive HDLC Control/Receive Addr. Low 2
– 922A 6A – XBCL Transmit Byte Count Low
– 922B 6B – BGR Baudrate Generator Register
932C 6C CCR2 Ch annel Configuration Re gi ste r 2
96 952D 6D RBCH XBCH Receive/Tran smit Byte Count High
96 972E 6E VSTR RLCR Version STatus/Receive Frame Length Check
972F 6F CCR1 Ch an nel Configur ation Registe r 1
– 9930 7 0 – TSAX Time-Slot Assignment Transmit
– 9931 7 1 – TSAR Time-Sl ot Assignment Rece ive
– 9932 72 – XCCR Transmit Channel Capacity
– 9933 73 – RCCR Receive Channel Capacity
Note: Channel A is not implemented in SAB 82526
RAL1
Semic onduct or Grou p 80
SAB 82525
SAB 82526
SAF 82525
SAF 82526
8.2 Register Definitions
Receive FIFO (Read) RFIFO (00. . .1F/40. . .5F)
Interrupt Controlled Data Transfer (Interrupt Mode)
selected if DMA bit in XBCH is reset.
Up to 32 bytes of receive data can be read from the RFIFO following an RPF or an RME
interrupt.
RPF Interrupt: Exactly 32 bytes to be read.
RME Interrupt: Number of bytes to be determined by reading the RBCL, RBCH registers.
DMA Controlled Data Transfer (DMA Mode)
selected if DMA bit in XBCH
If the RFIFO contains 32 bytes, the HSCX autonomously requests a block data transfer by
DMA activating the DRQR line a s long as the start of the 32nd read cycle. This forces the DMA
controller to continuously perform bus cycles till 32 bytes are transferred from the HSCX to the
system memory, (level triggered, demand transfer mode of DMA controller).
If the RFIFO contains less than 32 bytes (one short frame or the last of a long frame) the HSCX
requests a block data transfer depending on the contents of the RFIFO according to the
following table:
RFIFO
Contents
(Bytes)
DMA
Request
(Bytes)
1, 2, 3
4 - 7
8 - 15
16 - 32
4
8
16
32
Additionally an RME interrupt is issued after the last byte has been transferred.
As a result, the DMA controller may transfer more bytes as actually valid in the current received
frame. The valid byte count must therefore be determined by reading the RBCH, RBCL
registers following the RME interrupt.
Semic onduct or Grou p 81
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Transmit FIFO (WRITE) XFIFO (00. . .1F/40. . .5F)
Interrupt Mode
selected if DMA bit in XBCH is reset.
Up to 32 bytes of transmit data can be written to the XFIFO following an XPR interrupt.
DMA Mode
selected if DMA bit in XBCH is set.
Prior to any data transfer, the actual byte count of the frame to be transmitted must be written
to the XBCH, XBCL registers by the user.
If data transfer is then initiated via the CMDR register (command XTF or XIF), the HSCX
autonomously requests the correct amount of block data transfers (n × 32 + REST, n = 0, 1, …).
Note: Addresses with in the address sp ace of the FIFO’s a re interpr eted equally, i.e. the actua l
data byte can be accessed with any address within the valid scope.
Semic onduct or Grou p 82
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Interrupt Status Register (READ)
ISTA (20/60)RME RPF RSC XPR TIN ICA EXA EXB
7 0
Value after RESET: 00H
RME. . .Receive Message End
One message up to 32 bytes or the last part of a message gr eater then 32 bytes has
been received and is now available in the RFIFO. The message is complete!
The actual message length can be determined reading the RBCH, RBCL registers.
Additional information is available in the RSTA register.
RPF. . .Receive Pool Full
A block of 32 bytes of a message is stored in the RFIFO. The message is not yet
completed!
Note: This interrupt is only generated in Interrupt Mode!
RSC. . .Receive Status Change (significant in auto-mode only!)
A status change (receiver ready/receiver not ready) of the opposite station has been
detected in auto-mode. (i.e. the HSCX has received a RR/RNR supervisory frame
according to the HDLC protocol.) The current status can be read from the STAR
register (RRNR bit).
XPR. . .Transmit Pool Ready
A data block of up to 32 bytes can be written to the transmit FIFO.
TIN. . .Timer Interrupt
The internal timer and repeat counter has been expired. (See also description of TIMR
register!)
ICA … Interrupt of Channel A (Channel B only)
Indicates, that an interrupt is caused by channel A and the interrupt source(s) is (are)
indicated in the ISTA register of channel A (i.e. at least one bit of the ISTA register of
channel A is set).
Semic onduct or Grou p 83
SAB 82525
SAB 82526
SAF 82525
SAF 82526
The ICA, EXA, and EXB bit are prese nt in ch annel B only and point to the ISTA (CHA),
EXIR ( CHA), and EXI R (CHB) reg i sters.
After the H SCX h as requested an int er r upt by t ur ning i ts IN T pin to low, the CPU must
first read the ISTA register of channel B and check the state of these bits in order to
determine which interrupt source(s) of which channel(s) has caused the interrupt. More
than one int errupt source m ay be indicated by a singl e interr upt request.
After the respective registe r has been read, EXA, and EXB are reset. All other bits will be
reset after reading ISTA. To prevent malfunctions, each bit is individually monitored and
reset.
To generate edges at the INT pin it is necessary to mask all interrupts at the end of the
interrup t service routine and write back the old mask to the mask register.
Mask Register (WRITE)
Value aft er RESET: 00H (all interrupts enabled)
Each interrupt source can be selectively masked by setting the respective bit in MASK (bit
positions corresponding to ISTA register). Masked interrupts are not indicated when reading
ISTA. Instead, they remain internally stored and will be indicated after the respective MASK bit
is reset.
MASK RME RPF RSC XPR TIN ICA EXA EXB (20/60)
70
EXA … Extended Interrupt of Channel A (Channel B only)
An inter rup t is cau sed by ch an nel B and s ourc e(s ) is (ar e) in dic ate d in t he EX IR regis te r of
channel B.
Note:
In the event of an extended interrupt, no interrupt request will be generated with a
masked EXA, EXB bit, although this bit is set in ISTA.
Note:
Semic onduct or Grou p 84
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Extended Interrupt Register (READ)
Value aft er RESET: 00H
EXIR XMR XDU
EXE PCE RFO CSC RFS 0 0 (24/64)
70
XDU/EXE … Transmit Data Underrun/Extended Transmission End
The actual frame has been abor ted with IDLE, because the XFIFO holds no further data,
but the frame is not yet complete!
In extended transparent mode, this bit indicates the transmission-end condition.
The transmission of the last message has to be repeated because
the HSCX has received a negative acknowledgement in aut o-mode,–or a collision has occurred after sending the 32nd data byte of a message in a bus–configuration.
or CTS ( t ransm i ssi on en able) has be en w it hdr a wn a fter se nd in g the 32nd data byte of a–message in point-to-point configuration.
XMR … Transmit Message Repeat
It is not possible to send transparent-, or I-frames when a XMR or XDU interrupt is
indicated.
Note:
Semic onduct or Grou p 85
SAB 82525
SAB 82526
SAF 82525
SAF 82526
PCE … Protocol Error (significant in auto-mode only!)
RFO … Receive Frame Overflow
One frame could not be stored due to occupied RFIFO (i.e. whole frame has been lost). This
interr upt ca n be used for st atistica l pu rpose s a nd indi cates, that the C PU doe s n ot re spond
quickly enough to an incoming RPF, or RME interrupt.
CSC … Clear to send St atus Change
Indicates, that a state transition has occurred at the CTS pin. The actual state can be read
from STAR register (CTS bit).
This interrupt must be enabled setting the CIE bit in CCR2.
RFS. . .Receive Frame Start
This is an early receiver interrupt activated after the start of a valid frame has been detected,
i.e. after a valid address check in operation modes providing address recognition, otherwise
after the opening flag (transparent mo de 0), delayed by two bytes.
After an RFS interrupt, the contents of
RHCR
RAL1
RSTA – bit 3-0
are valid and can be read by the CPU.
This interrupt must be enabled setting the RIE bit in CCR2.
The HSCX has detected a protocol error, i.e. it has received
an S-, or I-frame wi t h in c orrect N (R)– an S-frame containing an I-field.–
Semic onduct or Grou p 86
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Status Register (READ)
Value aft er RESET: 48H
STAR XDOV XFW XRNR RRNR RLI CEC CTS WFA (21/61)
70
XDOV … Transmit Data Overflow
More than 32 bytes have been written to the XFIFO.
XFW … Transmit FIFO Write Enable
Data can be written to the XFIFO.
XFW is valid if CEC = 0 only!Note:
XRNR … Transmit RNR (significant in auto-mode only!)
Indicates the status of the HSCX.
0 … receiver ready
1 … receiver not ready
RRNR … Receive RNR (significant in auto-mode only!)
Indicates the status of the remote station.
0 … receiver ready
1 … receiver not ready
RLI … Receive Line Inactive
Neither FLAGs as interframe time fill nor frames are received via the receive line.
Significant in point-to-point configurations!Note:
CEC … Command Executing
0 … no command is currently executed, the CMDR register can be written to.
1 … a comm and (written p reviously to CMD R) is currently e xecuted, no f urther comman d
can be temporarily written via CMDR register.
CEC will be active at most 2.5 transmit clock periods. If the HSCX is in power down
mode CEC will stay active.
Note:
CTS … Clear To Send State
If the CIE bit in CCR2 is set, this bit indicates the state of the CTS p in.
0 … CTS is inactive (high signal at CTS)
1 … CTS is active (low signal at CTS)
WFA … Waiting for Acknowledgement (significant in auto-mode only)
Indicates the ’Waiting for Acknowledgement’ status of HSCX.
Semic onduct or Grou p 87
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Command Register (WRITE)
Value aft er RESET: 00H
CMDR (21/61)
70
RMC RHR RNR
XREP STI XTF XIF XME XRES
The maximum time between writing to the CMDR register and the execution of the
command is 2.5 clock cycles. Therefore, if the CPU operates with a very high clock in
comparison with the HSCX’s clock, it's recommended that the CEC bit of the STAR
registe r is checked bef ore writing to the CMD R register to avoid any loss o f commands.
Note:
RMC … Receive Message Complete
Confirmation from CPU to HSCX, that the actual frame or data block has been fetched
follo wing an R PF or RME inte rrupt, thu s the occupi ed space i n the RFIFO can b e releas ed.
RHR … Reset HDLC Receiver
All data in the RFIFO and the HDLC receiver deleted.
In DMA mode, this command is only issued once after a RME interrupt. The HSCX does
not generat e further DMA requests prior to the recept ion of this command.
Note:
In auto-mode, additionally the transmit and receive sequence number counters are reset.
RNR/XREP … Receiver Not Ready/Transmission Repeat
The function of this command depends on the selected operation mode (MDS1, MDS0,
ADM bit in MODE):
Auto-mode: RNR
0 … Receiver Ready (RR)
1 … Receiver Not Ready (RNR)
The status of the HSCX receiver is set. Determines, whether a received frame is
acknowledged via an RR, or RNR supe rvisory frame in auto-mode.
Extended transparent mode 0, 1 : XREP
Together with XTF and XME set (write 2 AH to CMDR), the HSCX repeatedly transmits the
contents of the XFIFO (1 … 32 bytes) without HDLC framing fully transparent, i.e. without
FLAG, CRC insertion, bit stuffing.
The cyclic transmission is stopped with an XRES command!
Semic onduct or Grou p 88
SAB 82525
SAB 82526
SAF 82525
SAF 82526
XTF … Transmit Transparent Frame
Interrupt mode
After having writte n up to 32 b ytes th e XFIFO, this command initiate s th e tran smission o f a
transparent frame. An opening flag sequence is automatically added to the data by the
HSCX.
DMA mode
After having writte n the len gth o f t he frame to be tra nsmitte d to the X BCH, X BCL registe rs,
this command initiates the data transfer from system memory to HSCX by DMA. Serial data
transmission starts as soon as 32 bytes are stored in the XFIFO.
XIF … Transmit I-Frame (used in auto-mode only!)
Initiates the transmission of an I-frame in auto-mode. Additional to the opening flag
sequence, the address and control field of the frame is automatically added by HSCX.
XME … Transmit Message End (used in interrupt mode only!)
Indicates, that the data block written last to the transmit FIFO completes the actual frame.
The HSCX can terminate the tra nsmission oper ation pro perly by ap pending the CRC and
the closing flag sequence to the data.
XRES … Transmit Reset
The contents of the XFIFO is deleted and IDLE is transmitted. This command can be used
by the CPU to abort a frame curre ntly in transmissio n. After setting XRE S an XPR interru pt
is generated in every case.
In DMA mode, the end of the frame is determined by the transmit byte count in XBCH,
XBCL! This bit must not be set in DMA mode.
STI … Start Timer
The internal timer is started.
Note: The timer is stopped by rewriting the TIMR register after start.
Semic onduct or Grou p 89
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Mode Register (READ/WRITE)
Value aft er RESET: 00H
MODE MDS1 MDS0 ADM TMD RAC RTS TRS TLP (22/62)
70
MDS1, MDS0 … Mode Select
The operating mode of the HDLC controller is selected.
00 … auto-mode
01 … non-auto mode
10 … transparent mode
11 … extended transparent mode
ADM … Address Mode
Auto-mode, non-auto mode
The meaning of this bi t varies depending on the select ed oper ating mode:
Defines the length of the HDLC address field.
0 … 8-bit address field
1 … 16-bit address field
Transparent mode
0 … transparent mode 0; no ad dress re cognition.
1 … transparent mode 1; high byte address recognition.
In transparent modes, this bit differentiates between two sub-modes:
Extended transparent mode; without HDLC framing.
0 … extended transparent mode 0; received data in RAL1.
1 … extended transparent mode 1; received data in RFIFO and RAL1.
In extended transparent modes, the RAC bit must set to "0" to enable fully transparent
reception!
Note:
Semic onduct or Grou p 90
SAB 82525
SAB 82526
SAF 82525
SAF 82526
TMD … Timer Mode
The operation mode of t he internal timer is set.
0 … external mode
The timer is controlled by the CPU and can be started at any time setting the STI bit in
CMDR.
1 … internal mode
The timer is used internally by the HSCX for time-out and retry conditions in auto-mode.
(refer to the description of the TIMR register)
RAC … Receiver Active
Switches the receiver to inoperational state.
0 … HDLC receiver inactive
1 … HDLC receiver active
In extended transparent modes this bit must be reset to enable fully transparent reception!
RTS … Request To Send
Defines the state and control of RTS pin.
0 … The RTS pin is controlled by the HSCX autonomously.
RTS is acti vated when a frame transmission starts and deactivated after the transmission
operation is completed.
1 … The RTS pin is controlled by the CPU.
If this bit is set, the RTS pin is activated immediately and remains active till this bit is reset
(not valid in bus configuration).
TRS … Timer Resolution
The resolution of the internal timer (factor k, see description of TIMR register) is selected
0 … k = 32.768
1 … k = 512
RxD is discon ne c ted fr om the mec hanical pin and int er na lly con ne c ted to TxD of th e same
channel. TxD pin remains active.
TLP … Test Loop
Semic onduct or Grou p 91
SAB 82525
SAB 82526
SAF 82525
SAF 82526
k is the timer resolution factor which is either 32.768 or 512-clock cycles dependent on
the programming of TRS bit in MODE.
TCP is the clock period of transmit data.
–
–
Timer Register (READ/WRITE)
TIMR CNT VALUE (23/63)
75 40
VALUE … Sets the time period t1 as follows:
t1 = k
× (VALUE + 1) ×TCP
where
CNT … Interpreted differently dependent on the selected timer mode (bit TMD in MODE).
Inter na l ti me r mo de (MO DE .T M D = 1)
retry counter (in HDLC known as N2 )
CNT indicates the number of S-commands (max. 6) which are transmitted autonomously by
the HSCX after expiration of time period t1, in case an I-frame is not ackn owledged by the
oppo site station.
If CNT is set to 7, the number of S-commands is unlimited.
External timer mode (MODE,TMD = 0)
CNT plus VALUE indicates the time period t2 after which a timer interrupt will be
generated. The time period t2 is
t2 = 32 × k
× CNT × TCP + t1
If CNT is set to 7, a timer interrupt periodically generated after the expiration of t1.
Semic onduct or Grou p 92
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Transmit Address Byte 1 (WRITE)
XAD 1 2-byte address (24/ 64)
70
XAD1 (high byte) 0 (0)
1-byte address XAD1 (COMMAND )
XAD1 (and XAD2) can be programmed with one individual address byte which is appended
automatically to the frame by HSCX in auto-mode. The function depends on the selected
address mode (bit ADM in MODE).
2-byte address field (MODE.ADM = 1)––
XAD1 forms the high byte of the 2-byte address field. Bit 1 must be set to 0! According to the
ISDN LAPD protocol, bit 1 is interpreted as the C/R (COMMAND/RESPONSE) bit. This is
manipulated automatically by the HSCX dependent on the setting of the CRI bit in RAH1:
Commands transmit
Responses transmit 1Bit 1 (C/R)
0
CRI = 1
0
1
CRI = 0
(In the ISDN, the high address byte is known as SAPI).
In accord an ce w i th t he H DLC protocol, b it 0 sh oul d be set to 0, indicating the exte nsi on of t he
address field to two bytes.
1-byte address field (MODE.ADM = 0)–– Accord ing with the X.25 LAPB proto col, XA D 1 indicates a COMMAND.
Semic onduct or Grou p 93
SAB 82525
SAB 82526
SAF 82525
SAF 82526
1-byte address XAD2 (RESPONSE)
Second individually programmable address byte.
2-byte address (MODE .ADM = 1)–– XAD2 builds up the low byte of the 2-byte address field
(In the ISDN, the low address byte is known as TEI)
1-byte address (MODE .ADM = 0)–– According to the X.25 LAPB protocol, XAD2 indi cates a RESPONS E,
XAD1, XAD2 regist ers are used only if the HSCX is operated in auto-mode.Note:
Receive Byte Count Low (READ)
RBCL (25/65)
70
RBC7 RBC0
Together with RBCH (bits RBC11 – RBC8), the length of the actual received frame
(1…4095 bytes) can be determined. These registers must be read by the CPU following an
RME interrupt.
Transmit Address Byte 2 (WRITE)
XAD 2 2-byte address (25/ 65)
70
XAD2 (low byte)
Semic onduct or Grou p 94
SAB 82525
SAB 82526
SAF 82525
SAF 82526
RAH1 (26/66)
70
RAH1 CRI 0
In operating modes that provide high byte address recognition, the high byte of the received
address is compared with the individual programmable values in RAH1, or RAH2.
RAH1 … Value of the first individual high address byt e
The setting of the CRI bit affects the meaning of the C/R bit in RSTA as follows:
Receive Address Byte High Register 1 (WRITE)
CRI … Command/Response Interpretation (auto-mode and non-auto mode only)
Command s received
Responses received
C/R meanin g 0C/R value
1
CRI = 1
1
0
CRI = 0
Important: If the 1 byte address field is selected in auto-mode, RAH1 must be set to 00H.
RAH2 (27/67)
70
RAH2 MCS 0
Receive Address Byte High Register 2 (WRITE)
10
RAH2 … Value of second individual programmable high addre ss byte.
MCS … Module Count Select; valid in auto-mode only.
0 … basic operation (modulo 8)
1 … extended operation (modulo 128)
The MCS bit adjusts the control fie l d format a ccording t o the HDLC (ISDN/LAPD).
When modulo 128 is selected, in auto-mode the "RHCR" register contains compressed
information of the extended control field (see RHCR, register description). RAH1, RAH2
registers are used in auto and non-auto operating modes when a 2-byte address field
has been selected (MODE.ADM = 1) and in the transparent mode 0.
RAH2 has to be initialized.
Note:
Semic onduct or Grou p 95
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Receive Status Register (READ)
RSTA VFR RDO CRC RAB HA1 HA0 C/R LA (27/67)
70
VFR … Valid Frame
1 … Valid
0 … Invalid
Determines whether a valid frame has been received.
a fr ame which is not an integer number of 8 bits (n × 8 bits) in length (e.g. 25 bit), or
a frame which is too short depend ing on the selected ope ration mod e via MODE (MDS1,
MDS0, ADM) as follows:
––
–
Auto-/non-auto mode (16-bit address): 4 bytes
Auto-/non-auto mode (8-bit address): 3 bytes
Transparent mode 1:3 bytes.
Transparent mode 0:2 bytes.
Shorter frames are not reported.Note:
RDO … Receive Data Overflow
A data overflow has occurred within the actual frame.
Caution: Data loss because the CPU did not serve RME or RPF interrupt in time.
CRC … CRC compare/check
0 … CRC check failed; received frame contains errors.
1 … CRC check o.k.; received frame is error-free.
RAB … Receive Messa ge Aborted
An invalid frame is either
The received frame was aborted from the transmitting station.
Accord ing to the HDLC proto col, this frame must be discarded by th e CPU.
Semic onduct or Grou p 96
SAB 82525
SAB 82526
SAF 82525
SAF 82526
In operating modes which provide high byte address recognition, the HSCX compares the
high byte of a 2-bytes address with the contents of two individual programmable registers
(RAH1, RAH2) and the fixed values FEH and FCH (group address).
HA1, HA0 … High Byte Address Compare; significant only if 2-byte address mode has
been selected.
Dep endent o n the result of this comparison, the following bit combinations are pos sible:
10 … RAH1 has been recognized
00 … RAH2 has been recognized
01 … group address has been recognized
If RAH1, RAH2 contain the identical values, the comb ination 00 will be omitte d.Note:
C/R … Command/Response; significant only, if 2-byte address mode has been selected.
Value of the C/R bit (bit of high address byte) in the received frame. The interpretation
depends on the setting of the CRI bit in the RAH1 register. Refer also to the description of
RAH1 register.
LA … Low Byte Address Compare; not significant in transparent and extended
transparent operating modes.
The low byte address of a 2-byte address field, or the single address byte of a 1-byte
addr ess field is compared with two p r ogrammable registers (RAL1, RAL2)
0 … RAL2 has been recognized
1 … RAL1 has been recognized
According to the X.25 LAPB protocol, RAL1 is interpreted as COMMAND and RAL2
interprete d as RESPONSE.
RSTA corresponds to the last received HDLC frame; it is duplicated into RFIFO for
every frame (last byte of frame).
Note:
Semic onduct or Grou p 97
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Recei ve Address Byte Low Register 1 (READ/WRITE)
RAL1 (28/68)
70
RAL1
Auto-/non-auto mode (16-bi t address) – WRITE only:
RAL1 c an be programme d with the value of the firs t indivi dual low address byte.
Auto-/non-auto mode (8-bi t addres s) – WRITE only:
According to X.25 LAPB proto col, the addres s in RAL1 is recognized a s COMMAND
address.
Transparent mode 1 (high byte address recognition) – READ only:
RAL1 contains the byte following the high byte of the address in the receive frame (i.e.
the second byte after the opening flag).
Transparent mode 0 (no address recognition) – READ only:
RAL1 contains the first byte after the opening flag (first byte of received frame).
Extended transparent modes 0, 1 – READ only:
RAL1 conta ins the act ual data byte curr ently assembl ed at the R × D pin, by passing the
HDLC receiver (fully transparent reception without HDLC framing).
––
–
–
–
–
The gene ral functi on (RE AD/W RITE) an d the m eanin g or co ntent s of thi s reg ister de pend s on
the selected operating mode:
Receive Address Byte Low Register 2 (WRITE)
RAL2 (29/69)
70
RAL2
Value of the second individual programmable low address byte. If a one byte address field is
selected, RAL2 is recognized as RESPONSE according to X.25 LAPB protocol.
Semic onduct or Grou p 98
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Receive HDLC Control Register (READ)
RHCR (29/69)
70
RHCR
Value of the HDLC control field corresponds to the last re ceived frame.
RHCR is duplicated into RFIFO for every frame.Note:
Mode
Auto-mode,1-byte address
(U-frames) (Not e 1)
Auto-mode, 2-byte addr ess
(U-frames) (Not e 1)
Auto-mode, 1-byte addr ess
(I-frames) (Note 1)
Auto-mode, 2-byte addr ess
(I-frames) (Note 1)
Modulo 8 (MCS = 0)
Control field
Control field
Control field
Control field
Modulo 128 (MCS = 1)
Control field
(Note 2)
Control field
(Note 2)
Control field in
compressed form (Note 3)
Control field in
compressed form (Note 3)
Contents of RHCR
Non-auto mode,
1-byte address
Non-auto mode,
2-byte address
Transparent
mode 1
Transparent
mode 0
2nd byte after flag
3rd byte after flag
3rd byte after flag
2nd byte after flag
S-frames are handled automatically and are not transferred to the microprocessor.Note 1:
For I-frames (bit 0 of RHC R = 0) th e comp ressed contro l field h as the same forma t
as in the modulo 8 case, but only the three LSB’s of the receive and transmit
counters are visible:
Note 3: For U-frames (bit 0 of RHCR = 1) the control field is as in the modulo 8 case.Note 2:
N(R) PN(S) 0
bit 76543210
Semic onduct or Grou p 99
SAB 82525
SAB 82526
SAF 82525
SAF 82526
XBCL XBC7 XBC0 (2A/6A)
70
Together with XBC H (bits XBC1 1…XBC8) th is registe r is used in DMA mode on ly, to prog ram
the length (1…4095 bytes) of the next frame to be transmitted.
This allows the HSCX to request the correct amount of DMA cycles after an XTF or XIF
command via CMDR.
Note: The number of transmitted byte s is XBC + 1 , e.g. if the content of XBC is 00 exactly on e
byte will be transmitted.
Baudrate Generator Register (WRITE)
BGR BR7 BR0 (2B/6B)
70
Together with bits BR9, BR8 of CCR2, the division factor of the baudrate generator is adjusted.
Dependent on the programmed value N in BR9 – BR8 (N = 0…1023) the division factor k
results as follows:
BR7 – BR0…Baudrate, bit 7 - 0
Transmit Byte Count Low (WRITE)
k = (N + 1) × 2
Semic onduct or Grou p 100
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Channel Configuration Register 2 (READ/WRITE)
Value after RESET: 00H
The meaning of the individual bits in CCR2 depends on the selected clock mode via
CCR 1 as follows:
clock mode 0,1 SOC1 SOC0 (2C/6C)0 0 0 CIE RIE DIV
CCR2
clock mode 2,6 BR9 BR8 BDF TSS TIO CIE RIE DIV
clock mode 3,7 BR9 BR8 BDF 0 TIO CIE RIE DIV
clock mode 5 SOC1 SOC0 XCS0 RCS0 TIO CIE RIE DIV
clock mode 4 SOC1 SOC0 0 0 TIO CIE RIE DIV
In a bus configuration (selected via CCR1) the function of pin RTS can be defined
00 … RTS output is activated dur ing the trans missio n of a frame.
10 … RT S output is always high (RTS disabled).
11 … RT S indicates the reception of a data frame (active low).
In point-to-point configurat ion (selected via CCR1 ) the T × D and R × D pins may be flipped
0X … data is transmitted on T × D, received on R × D pin (normal case)
1X … data is transmitted on R × D, received on T × D pin
SOC1, SOC0 … Special Output Control
BR9, BR8 … Baudrate, Bit 9-8 (higher significant bits, refer to description of BGR
register).
0 … The division factor of the baudrate generator is set to 1 (constant).
1 … The division factor is adjusted with BR9 – BR0 bits of CCR2 and BRG register.
BDF … Baudrate Division Factor
0 … The transmit clock is input to the T × CLKA/T × CLKB pins.
1 … The transmit clock is derived from the baudrate generators output divided by 16.
TSS … Transmit Clock Source Select
0 … T × CLKA, T × CLKB pi ns ar e in put s
1 … T × CLKA, T × CLKB pi ns ar e outp uts
TIO … Transmit Clock Input Output Switch
Semic onduct or Grou p 101
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Any state transition at the CTS input pin may cause an interrupt which is indicated in the
EXIR register (CSC bit). The actual state at the CTS pin can be determined reading the CTS
bit of the STAR register.
0 … disable
1 … enable
CIE … Clear To Send Interrupt Enable
When, the RFS interrupt (via EXIR) is enabled!
RIE … Rece ive Frame Start Interrupt Enable
Only valid if NRZ data encoding is selected. Data is tran s mitted and receiv ed inverted.
DIV … Data Inversion
Together with bits XCS2, XCS1 (RCS2, RCS1) in TSAX (TSAR) the clock shift relative to
the frame synchronization signal of the transmit (receive) time-slot can be adjusted.
A clock shift of 0 … 7 bits is programmab le (clock mode 5 only!).
XCS0, RCS0 … Transmit/Receive Clock Shift, Bit 0
Semic onduct or Grou p 102
SAB 82525
SAB 82526
SAF 82525
SAF 82526
XBCH (2D/6D)
73
DMA NRM CAS XC XBC11 XBC8
0
Transmit Byte Count High (WRITE)
Value after RESET: 000xxxxx
Selects the data transfer mode of HSCX to system memory.
0 … Interrupt controlled data transfer (interrupt mode)
1 … DMA control led data tra nsfe r (DMA Mo de )
DMA … DMA Mode
Valid in auto-mode only! Use in auto-mode only; reset this bit in non auto-mode, transparent
mode, and extended transparent mode.
Determines the function of the LAP controller:
0 … full-duplex LAPB/LAPD operation
1 … half-duplex NRM operation
NRM … Normal Response Mode
When set, a high at the CD (A × CLK) pin enables the respective receiver and data reception
is started.
CAS … Carrier Detect Auto Start
CAS has to be "0" for clock mode 1 and 5Note:
Only valid if DMA mode is selected!
If the XC bit is set, the HSCX continuously requests for transmit data ignoring the transmit
byte count programmed via XBCH, XBCL.
XC … Transmit Continuously
Valid only if DMA mode is selected!
Together with XBC7 … XBC0 the length of the frame to be programmed.
XBC11 … XBC8 … Transmit Byte Count (most significant bits)
Semic onduct or Grou p 103
SAB 82525
SAB 82526
SAF 82525
SAF 82526
RBCH (2D/6D)
73
DMA NRM CAS OV RBC11 RBC8
0
Received Byte Count High (READ)
Value after RESET: 000xxxxx
DMA, NRM, CAS … These bits represent the read-back value programmed in XBCH
(see XBCH!)
More than 4095 bytes received!
The received frame exceeded the byte count in RBC11 … RBC0.
OV … Counter Overflow
Together with RBCL (bits RBC7 … RBC0) the length of the received frame can be
determined.
RBC11 … RBC8 … Receive Byte Count (most significant bits)
see XBCH
VSTR (2E/6E)
73
CD 0 0 0VN3 VN0
0
Version Status Register (READ)
This bit represents the inverted state at the CD (A×CLK) pin even when CAS is not enabled.
1 … CD active (low)
0 … CD inactive (high)
CD … Carrier Detect
0:000 … Version A1
2:010 … Version A2
4:100 … Version A3
5:101 … Version 2.1
VN3 … VN0 … Ver sion Num ber of Chip
Semic onduct or Grou p 104
SAB 82525
SAB 82526
SAF 82525
SAF 82526
CCR1 (2F/6F)
7PU SC1 SC0 ODS ITF
OIN CM2 CM1 CM0
0
0 … power down (standby)
1 … power up (active )
PU … Switches between Power Up and Power Down mode
00 … NRZ data enc oding
10 … NRZI data encoding
01 … bus c onfiguration, timing mode 1
11 … bus c onfiguration, timing mode 2
SC1, SC0. . .Serial Port Configuration
Value after RESET: 00H
Channel Configuration Register 1 (READ/WRITE)
If bus configuration is selected, only NRZ coding is supported.Note:
RLCR (2E/6E)
7RC RL6 RL0
0
Receive Length Check Register (WRITE)
0 … receive length check feature disabled
1 … receive length check feature enabled
RC … Receive Check (on/off)
The maximum receive length after which data reception is suspended can be programmed
here. Depending on the value RL programmed via RL6 … RL0, the receive length is
(RL + 1) × 32 bytes! A frame exceeding this length is treated as if it was aborted by the
opposite station (RME Interrupt, RAB bit set).
RL … Receive Length
In this case, the Receive Byte Count (RBCH, RBCL) is greater than the programmed
recei ve length.
All bytes sto red in the RFIFO are releva nt for the receive leng th check feature in cluding
the recei ver statu s byt e.
Note:
Semic onduct or Grou p 105
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Defines the function of the transmit data pins (T × DA, T × DB)
0. . .T × D pins are open drain outputs
1. . .T × D pins are push-pull outputs
ODS … Output Driver Select
The function of this bit depends on the selected serial po rt configuration (bit SC0)
ITF/OIN … Interframe Time Fill/One Insertion
Point-to-point configurations: ITF
Bus configurations: OIN
Determines the idle (= no data to send) state of the transmit data pins (T × DA, T × DB)
0 … Cont inuous I D LE sequ ences ar e output (T × D pins remain in the "1" state)
1 … Cont inuous FLAG sequences are output ("01111110" bit pat terns)
In bus configurations, the ITF is implicitly set to 0, i.e. continuous "1"s are transmitted,
and data encoding is NRZ!
When this bit is set, a "ONE" insertion (deletion) mechanism is activated, inserting a "1"
after seven consecutive "0"s in the transmit data stream or deleting a "1" in the receive
data stream.
Similar to the HDLC’s bit-stuffing mechanism (inserting a "0" after five consecu tive "1"s),
this method proves to be advantageous when the receive clock is recovered from the
receiv e data stream by mean s of DPLL, because it is guarante ed that at least afte r seven
bits a transition occurs in the receive data in case of long "0" sequences!
CM2, CM1, CMO … Clock Mode
Selects one of the 8 different clock modes
000 clock mode 0
..
..
..
111 clock mode 7
Since in t ime-slot oriente d syste ms the T × D pin is not tristated automa tically out o f the
programmed time-slot, the T × D pin should be configured as open drain in time-slot
oriented bus systems.
Note:
Semic onduct or Grou p 106
SAB 82525
SAB 82526
SAF 82525
SAF 82526
TSAX (30/70)
7TSNX XCS2 XCS1
This registers is only used in clock mode 5!
Time-Slot Assignment Register Transmit (WRITE)
210
Selects one of up 64 possible time-slots (00H – 3FH) in which data is transmitted. The
number of bits per time-slot can be pro grammed via XCCR.
TSNX … Time-Slot Number Transmit
Together with the XCS0 in CCR2, the transmit clock shift can be adjusted.
XCS2, XCS1 … Transmit Clock Shift, Bit 2-1
This register is only used in clock mode 5!
Time-Slot Assignment Register Receive (WRITE)
TSAR (31/71)
7TSNR RCS2 RCS10
Defines one of up to 64 possible time-slots (00H – 3FH) in which data is received. The
number of bits per time-slot can be programmed via RCCR.
TSNR … Time-Slot Number Receive
Together with bit RCS0 in CCR2, the receive clock shift can be adjusted.
RCS2, RCS1 … Receive Clock Shift, Bit 2-1
Semic onduct or Grou p 107
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Value aft er RESET: 00H
This register is only used in clock mode 5.
Transmit Channel Capacity Register (WRITE)
XCCR (32/72)
7XBC7 XBC00
Defines the number of bits to be transmitted with a time-slot:
Number of bits = XBC + 1. (1 … 256 bits/time-slot)
XBC7 … XBC0 … Transmit Bit Count, Bit 7-0
Receive Channel Capacity Register (WRITE)
RCCR (33/73)
7RBC7 RBC00
Value after RESET: 00H
This reg i ster is only used in clo ck mode 5.
Defines the number of bits to be received within a time-slot:
Number of bits = RBC + 1. (1 … 256 bits/time-slot)
RBC7 … RBC0 … Receive Bit Count , Bit 7-0
Semic onduct or Grou p 108
SAB 82525
SAB 82526
SAF 82525
SAF 82526
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Absolute Maximum Ratings
9 Electr ical Ch aracteristics
Symbol
TA
TA
Tstg
VS
Vmax
Parameter
Ambient temperature under bias: SAB
SAF
Storage temperature
Voltage on any pin with respect to ground
Maximum voltage on any pin
Limit Values
0 to 70
– 40 to 85
– 65 to 125
– 0.4 to VDD + 0.4
6
Unit
°C
°C
°C
V
V
Note:Stresses above those listed here may cause permanent damage to the device.
Exposure to absolute maximum ratings conditions for extended periods may affect
device reliability.
Characteristics
SAB: TA = 0 to 70 °C; VDD = 5 V ± 5 %; VSS = 0 V
SAF: TA = – 40 to 85 °C; VDD = 5 V ± 5 %; VSS = 0 V
Parameter Symbol
min.
Unit ConditionLimit Values
L-input voltage VIL – 0.4 V
H-input voltage VIH 2.0 V
max.
0.8
VCC + 0.4
L-outp ut volt ag e VOL V
VIOL = 7 mA (pins T × D, R × D)
IOL = 2 mA (all other)
0.45
H-output voltage
H-output voltage VOH
VOH
2.4
VDD – 0.5 V
VIOH = – 400 µA
IOH = – 100 µA
Power
supply
current
operational
power down
8
1.5
mA
mA
VDD = 5 V, Cp = 4 MHz
Inputs at 0 V/VDD,
no output loads
Input leakage current
Output leakage
current
ILI
ILO
µA0 V < VIN < VDD to 0 V
0 V < VOUT < VDD to 0 V
10
ICC
ICC
Semic onduct or Grou p 109
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Capacitances
TA = 25 °C; VDD = 5 V ± 5 %; VSS = 0 V, fC = 1 MHz, unmeasured pins returned to GND.
Characteristics
SAB: TA = 0 to 70 °C; VDD = 5 V ± 5 %
SAF: TA = – 40 to 85 °C; VDD = 5 V ± 5 %
Inputs ar e dr iven to 2.4 V for a l ogical "1" a nd to 0. 4 V for a logica l "0". Ti min g measur emen ts
are made at 2.0 V for a logical "1" and at 0.8 V for a logical "0".
The AC testing input/output waveforms are shown below.
Input/Output Waveform for AC Tests
Parameter Symbol
typ.
Unit
Limit Values
Input capacitance
f
C = 1 MHz CIN 5pF
Output capacitan ce COUT 8pF
max.
10
15
I/O CI/O 10 pF20
ITS02702
=
Load
C
Test
Under
Device
0.45/0.4
2.4/2.4 2.0
0.80.8
2.0 Test Points
pF150
Semic onduct or Grou p 110
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Microcontroller Interface Timi ng Intel Bus Mode
µP Read Cycle
µP Write Cycle
Multiplexed Address Timing
CS x RD
D0 - D7
t
RD
Data
t
DF
RR
tt
RI
ITT00953DRH
t
DRQR
CS x WR
D0 - D7
t
DW
Data
t
WD
WW
tt
WI
DRH
t
DRQT
ITT00954
CS x WR
A0 - A6
t
LA
CS x RD
ALE
t
ALS
t
AL
t
AA
ITT00955
Semic onduct or Grou p 111
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Microcontroller Interface Timi ng Intel Bus Mode
Address Timing
CS x WR
A0 - A6
t
DCD
DACK
CS x RD
ITT00956
Semic onduct or Grou p 112
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Motor o l a Bu s Mo de
µP Read Cycle
µP Write Cycle
Address Timing
CS x DS
D0 - D7
t
RD
Data
t
DF
DSD
t
RR
tt
RI
R/W
t
DRH
DRQR
ITT00957
t
RWH
CS x DS
D0 - D7
t
DW
Data
t
WD
DSD
t
WW
tt
WI
R/W
DRH
t
DRQT
ITT00958
RWH
t
A0 - A6
t
AH
t
AS
DACK
CS x DS
ITT00959
Semic onduct or Grou p 113
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Parameter Symbol
min.
UnitLimit Values
Address setup time to ALE tAL 10 ns
max.
Address hold time from ALE tLA 10 ns
ALE pulse width tAA 25 ns
Address latch setup time to WR, RD tALS 0ns
Address setup time to WR, RD tAS 10 ns
Address hold time from WR, RD tAH 10 ns
DMA request delay: SAB
SAF tDRH ns
ns
80
90
RD pulse width tRR ns
Data output de lay from RD tRD ns
60
Data float delay from RD tDF ns
25
RD control interval tRI ns
WR pulse wid th tWW ns
Data setup time to WR x CS/DS x CS tDW ns
Data hold time from WR x CS/DS x CS tWD ns
WR control interval tWI ns
tDSD ns
Interface Timing
tRDH ns
tCDS ns
tRDS ns
tCDH ns
tXDD2 ns
tRTD1 ns
Serial Interface Timing
Recei ve data hold
Collision d ata setup
Receive data setup
Collision d ata hol d
Transmit data delay, falling clock edge
Request to send delay 1
5
5
20
30
20 68
10 120
60
10
35
10
60
0
70
tCP ns
tCPL ns
tRTD2 ns
tCPH ns
Clock peri od
Clock period LOW
Request to send delay 2
Clock period HIGH
240
90
10 85
90
80
90
70
25
SAB SAF
75
120
85
RD delay after WR set up
tXDD1 ns
Transmit data delay, rising clock edge 10 68 75
Semic onduct or Grou p 114
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Serial Interface Timing
t
RDS
t
RDH
t
CPL
t
CP
t
CPH
t
XDD
t
CDS
t
CDH
t
XDD
t
RTD
t
RTD
t
RTD
Bus
Timing
Bus
Timing
R
RTSA/B
Mode 2
Mode 2
CPH
t
CP
t
CPL
t
Mode 1
Timing
Bus
RTD
t
RTD
t
Clock
RxDA/B
ClockX
TxDA/B
TxDA/B
CxDA/B
CTSA/B
RTSA/B
RTSA/B
1
2
22
1
ITT00960
1
2
Semic onduct or Grou p 115
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Strobe Timing (Clock Mode1)
ITT00961
t
XDD
t
XSZ
t
XCZ
t
XDD
t
SDD
t
XSH
t
XSS
Bus
Timing
Mode 2
RxCLK
TxCLK
TxD
TxD
t
XCZ
AxCLK
RSD
t
t
XSD
RSH
t
RSS
t
Symbol
Unit
Limit Valu es
tRSS ns
tRSH ns
tRSD ns
tXSD ns
tXSS ns
tXSH ns
Parameter
Receive strobe setup
Receive strobe hold
Receive strobe delay
Transmit strobe delay
Transmit strobe setup
Transmit strobe hold
60
30
30
30
60
30
min. max.
tSDD ns
tXCZ ns
tXDD ns
tXSZ ns
Strobe data delay
High impedance fr om clock
Transmit data delay
High impedance from strobe
90
50
68
50
Semic onduct or Grou p 116
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Clock Mode 5
Synchronization Timing
ITT00962
t
SD
t
SS
t
SW
t
TCD
t
TCD
t
TCD
t
TCD
RxCLK
AxCLK
TxCLK
TxCLK Bus
Timing
Mode 2
Symbol Unit
Limit Valu es
tSS ns
tSW ns
tSD ns
tTCD ns
Parameter
Sync pulse setup
Sync pulse width
Sync pulse delay
Time-slot control delay
30
40
30
10 75
min. max.
Semic onduct or Grou p 117
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Symbol
Unit
Limit Values
fCLK MHz
fCLK MHz
Parameter
Clock frequency
Baudrate generator not used
Clock frequency
Baudrate generator used 19.3
12.3
min. max.
Clock Mode 2, 3, 6, 7
Internal Clocking
Symbol
Unit
Limit Values
tRWH ns
Parameter
RES HIGH 1800
min. max.
RESET Timing
RES Characteristics
CD Timing
ITT05882
60 ns>>ns30
RxCLK
RxD
AxCLK (CD)
Semic onduct or Grou p 118
SAB 82525
SAB 82526
SAF 82525
SAF 82526
10 Quartz Specifica t ions
Characterization of Quartz Crystals for the HSCX
– Mode of oscillation parallel resonance
– Frequency calibration tolerance 50 ppm
– Frequency shift during lifetime 10 ppm
– Temperature coefficient/frequency drift 50 ppm within the temperature range
– Motional capacitance 15 fF ± 20%
– Effective serial resistance ≤ 50 Ω for 19.2 MHz
– Shunt capacitance ≤ 7 pF
– Drive level 1 mW
– Recommended type HC - 49/U (ANSI - standard)
Semic onduct or Grou p 119
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Upgrades of HSCX Version A3
The HSCX Versi on A3 is fu lly upwa rd com patib le to Versi on A2. The differen ces with re spect
to HSCX Technical Manual Rev. 2.89 are shown in table 12.
Table 12
Differences HSCX A2 – HSCX A3
Differences Ver. A2 Ver. A3 User Manual Chapter
tRI, tWI 70 ns 9
tAA 50 ns 9
tLA 20 ns 9
tDRH 85 ns 9
tRD 120 ns 9
tRDS 5 ns 9
tRDH 30 ns 9
tXDD 70 ns 9
IOL value, pin T×D2 mA 9
VSTR value 02H 8
60 ns
25 ns
10 ns
80 ns
100 ns; SAF110 ns
20 ns
5 ns
68 ns
7 mA
04H
The following additional features are implemented in HSCX A3.
Transmission in back to back frames.
Two or more frames may be transmitted continously without interframe time fill
T×D, R×D flip
In clock modes 0, 1, 4 and 5 pins R×D and T×D may be flipped
(refer to CCR2 Register SOC0 and SO C1 bit)
Status Re gister
In auto-mode, START: bit 0 indicates the ’Waiting for Acknowledgement’ status
tCDS 0 ns 9
5 ns
tAH 20 ns 9
10 ns
tDW 30 ns 910 ns
Appendix A
Semic onduct or Grou p 120
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Upgrades of HSCX Version V2.1
3 Version ID
The bits VN3 … VN0 of the Version Status Register (VSTR) contain the value 5 for version
V2.1. All HSCX version numbers are listed below:
4 RNR Flow Control in Auto-Mode
No more timing restrictions exist for HSCX V2.1 when the CPU accesses the RNR-bit of the
Command Register (CMDR).
5I-Frames with P = 0 in NRM Auto-Mode
In multipoint configurations using the HDLC normal response mode (NRM) the P-bit of the
control field carries out the polling function. The primary station normally polls the other
secondar y stations by transmittin g either RR frames with P = 1 or I-frames with P = 1. I-frames
with P = 0 may be used by the primary station to transmit data to an individual secondary
statio n wit hout requ esting d ata from t his s tatio n at t he sa me t ime. In th is ca se the s eco ndar y
station will receive and acknowledge this I-frame, but will not react by transmitting any data to
the primary station.
In the following it is assumed that the secondary station is waiting for transmission.
A secondary station using an HSCX VA3 in NRM auto-mode will transmit data to the primary
station after it has received an I-frame with of P = 0 or = 1.
The new HSCX V2.1 handles the P-Bit of I-frames according to ISO 4335. It will transmit data
to the primary station after it has received an I-frame wi th P = 1, but not after an I-frame ha s
been received with P = 0.
6 Transmission of Back-to-Back Frames
The new HSCX V2.1 supports ba ck-to-back fra me transmission in all clock modes without any
problem, including the strobe mode s (clock mode 1 and 5).
7INT Output Signal
The INT output sign al of the HSCX V2.1 does n ot change its value during a write access to t he
HSCX (CS x WR for Intel and DS x WR for Motorola ).
VN3 … 0 Version
0: 000 VA1
2: 010 VA2
4: 100 VA3
5: 101 V2.1
Semic onduct or Grou p 121
SAB 82525
SAB 82526
SAF 82525
SAF 82526
8 Clock Recovery (DPLL)
In case the DPLL detects an edge in the data stream in the range of DPLL count 5 to 10 (Phase
Shift) and this is the only one in the assumed bit cell period, then the DPLL receive clock phase
is shi fted b y a cer ta i n D P LL cou nt val ue . The DPLL valu e and its corr esp ond ing ph ase shift in
degree is listed belo w for the HSCX versions VA3 and V2.1:
HSCX Version DPLL Count Phase Shift
VA3 8 180 °
V2.1 7 157.5 °
Differences Ver. A3 Ver. 2.1
tRD
tRR
tRI
tXDD1 min
tRTD1 min
tRTD2 min
tTCD mi n
100/110 ns
120 ns
60 ns
20 ns
30 ns
20 ns
20 ns
60/70 ns
70 ns
35 ns
10 ns
10 ns
10 ns
10 ns
Semic onduct or Grou p 122
SAB 82525
SAB 82526
SAF 82525
SAF 82526
HSCX Auto-Mode: Specific Points
Appendix B
HSCX auto -mode of SAB 82 525/S AB 8 2520 (H SCX/H SCC) is optim ized for a windo w size of
one. Therefore the follow ing simplifications are made:
No REJ-frame is generated, an RR-frame will be transmitted instead. If a REJ-frame is
receiv ed it will be handled like an RR-frame.
The tran sm it /r eceive variables N(R )/ N (S ) ar e ch ecke d wi th i n t he w indo w si ze (i .e . on e) ,
only the LSB is evaluated.
An I-frame with an incorrect N(R)-value is not accepted, an error interrupt (EXIR:PCE) is
generated.
The timer recovery state is ca ncelled if a positive acknowledgement (upda ted N(R)) is
received.
Selective reject is treated like RR.
Afte r sending an I-frame the HSCX cannot trans m it any frame before an
acknowledgement or an XRES-comman d.
Two Byte Addresses:
An I-frame with C = 0 is accepted without error indication.
Semic onduct or Grou p 123
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Appendix C
Application Example HSCX with 80(C)188 using DMA
DMA information, see chapter 4.
Appendix D
HSCX for Siemens Primary Access Interface
The Siemens devices for the Primary Access Interface are the Advanced CMOS Frame
Aligner (ACFA) and the Primary Access Transceiver (PRACT). These devices can directly be
conn ected to th e HSCX withou t any addi tional glue log ic. In combi nation wit h the HSCX t his
application is the most effective way to build a powerful and flexible Primary Access Interface,
especially supporting different combined B channel paths over long distances (LAN-WAN
Internetworkin g) . The fo llowing blo ck diag ram i llustr ates ho w ea sy it is to i ntegra te the HSCX
into a Primary Access application based on Siemens devices.
HSCX System Integration for Primary Rate Interface T1/E1 Siemens System Interface
(ACFA/PRACT)
ITS05880
TxDA
RxDA
RxCLKA
AxCLKA
TxDB
RxDB
RxCLKB
AxCLKB
HSCX
SAB 82525
V
CC
XDI
RDO
XRCLK
XDOP
XDOM
RDIP
RDIM
RRCLK
XTOP
XTOM
SYPQ SCLK
ACFA
PEB 2035
Dual
Rail
Interface
CLK4M FSC CLK2M FSC
PRACT
22320PEB
Semic onduct or Grou p 124
SAB 82525
SAB 82526
SAF 82525
SAF 82526
The adaption of the AxCLKA/B pulses is solved by means of shifting the receive data and
transmit data in the ACFA device appropriately. In this case the AxCLKA and AxCLKB
synchronization pulses are also identical. The ACFA device contains special registers to
control the bit shift of the serial bit streams at the system interface (see ACFA Data Sheet).
With the following register programming the bit shift selected is T = – 510 for the HSCX
transmit data and T = 1 for the receive data respectively. The programming is as follows:
XDI: XC1.XTO = 3DH=> X = 494 => T = – 510
XC0.XCO = 07H
RDO: RC1.RTO = 00H=> X = 3 => T = 1
RC0. RCO = 03H
The timing in principle is depicted in the following diagram. Without all details of a typical
electrical timing it illustrates how the different signa l s from HSCX, ACFA an d PRACT are
mapped in such a Primary Access system.
HSCX Signal Mapping for Primary Rate Interface T1/E1 Siemens System Interface
(ACFA/PRACT)
ITD05881
CLK4M
FSC
AxCLKA/B
RxCLKA/B
TxCLKA/B
TxDA/B
=
RxDA/B
=
=
=
=
XDI
RDO
FSC
CLK2M
(T
(T
=
=
-510)
1)
=:Channel 0,Bit 0 (Least Significant Bit)
ACFA Programming for Appropriate Delays (see ACFA Data Sheet):
XDI :
RDO :
T = - 510 = > X = 495 = > XC1.XTO = 3D XC0.XCO = 7
3=RC0.RCO0=RC1.RTO>=3=X>=1=T ,H
H
H
,
Semic onduct or Grou p 125
SAB 82525
SAB 82526
SAF 82525
SAF 82526
11 Package Outlines
GPL05102
Plastic Package, P-LCC-44-1 (SMD)
(Plastic-Leaded Chip Carrier)
SMD = Surface Mounted Device
Sorts of Packing
Package outli nes for tubes, trays etc. are contained in our
Data Book “Package Information”
Dimensions in mm
Semic onduct or Grou p 126
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Plastic Package, P-MQFP-44-2 (SMD)
(Plastic-Leaded Ch ip Carrier)
GPM 05622
SMD = Surface Mounted Device
Sorts of Packing
Package outli nes for tubes, trays etc. are contained in our
Data Book “Package Information”
Dimensions in mm
