Mixed-Signal Byte-Programmable EPROM MCU
C8051F336/7/8/9
Rev. 1.0 9/08 Copyright © 2008 by Silicon Laboratories C8051F336/7/8/9
Analog Peripherals
-10-Bit ADC (‘F336/8 only)
•Up to 200 ksps
•Up to 20 external single-ended or differential inputs
•VREF from on-chip VREF, external pin or VDD
•Internal or external start of conversion source
•Built-in temperature sensor
-10-Bit Current Output DAC (‘F336/8 only)
-Comparator
•Programmable hysteresis and response time
•Configurable as interrupt or reset source
On-Chip Debug
-On-chip debug circuitry facilitates full speed, non-
intrusive in-system debug (no emulator required)
-Provides breakpoints, single stepping,
inspect/modify memory and registers
-Superior performance to emulation systems using
ICE-chips, target pods, and sockets
-Low cost, complete development kit
Supply Voltage 2.7 to 3.6 V
-Built-in voltage supply monitor
High-Speed 8051 µC Core
-Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
-Up to 25 MIPS throughput with 25 MHz clock
-Expanded interrupt handler
Temperatu re Ra ng e : –4 0 to +85 °C
Memory
-768 bytes internal data RAM (256 + 512)
-16 kB Flash; In-system programmable in 512-byte
Sectors (512 bytes are reserved)
Digital Peripherals
-21 or 17 Port I/O; All 5 V tolerant with high sink
current
-Pin-compatible with C805 1F330 family of MCUs
-Hardware enhanced UART, SMBus™ (I2C compati-
ble), and enhanced SPI™ serial ports
-Four general purpose 16-bit counter/timers
-16-Bit programmable counter array (PCA) with three
capture/compare modules and enhanced PWM
functionality
-Real time clock mode using timer and crystal
Clock Sources
-24.5 MHz ±2% Oscillator
•Supports crystal-less UART operation
•Low-power suspend mode with fast wake time
-80/20/40/10 kHz low-frequency, low-power
oscillator
-External oscillator: Crystal, RC, C, or clock
(1 or 2 pin modes)
-Can switch between clock sources on-the-fly; useful
in power saving modes
20 or 24-Pin QFN (4 x 4 mm)
ANALOG
PERIPHERALS
16 kB
ISP FLASH 768 B SRAM
POR
DEBUG
CIRCUITRY
FLEXIBLE
INTERRUPTS
8051 CPU
(25 MIPS)
DIGITAL I/O
24.5 MHz PRECISION
INTERNAL OSCILLATOR
HIGH-SPEED CONTROLLER CORE
CROSSBAR
VOLTAGE
COMPARATOR
+
–
WDT
UART
SMBus
PCA
Timer 0
Timer 1
Timer 2
Timer 3
Port 0
SPI
LOW FREQUENCY INTERNAL
OSCILLATOR
Port 1
P2.0–
P2.3*
‘F336/8 Only P2.4*
10-bit
200 ksps
ADC
TEMP
SENSOR
A
M
U
X
10-bit
Current
DAC
*P2.1–2.4 QFN24 Only
C8051F336/7/8/9
2 Rev. 1.0
C8051F336/7/8/9
Rev.1.0 3
Table of Contents
1. System Overview..................................................................................................... 15
2. Ordering Information............................................................................................... 18
3. Pin Definitions.......................................................................................................... 19
4. QFN-20 Package Specifications............................................................................. 23
5. QFN-24 Package Specifications............................................................................. 25
6. Electrical Characteristics........................................................................................ 27
6.1. Absolute Maximum Specifications..................................................................... 27
6.2. Electrical Characteristics................................................................................... 28
6.3. Typical Performance Curves............................................................................. 36
7. 10-Bit ADC (ADC0, C8051F336/8 only)................................................................... 37
7.1. Output Code Formatting.................................................................................... 38
7.2. Modes of Operation........................................................................................... 38
7.2.1. Starting a Conversion................................................................................ 38
7.2.2. Tracking Modes......................................................................................... 39
7.2.3. Settling Time Requirements...................................................................... 40
7.3. Programmable Window Detector....................................................................... 44
7.3.1. Window Detector In Single-Ended Mode.................................................. 46
7.3.2. Window Detector In Differential Mode....................................................... 47
7.4. ADC0 Analog Multiplexer (C8051F336/8 only).................................................. 48
8. Temperature Sensor (C8051F336/8 only) .............................................................. 51
9. 10-Bit Current Mode DAC (IDA0, C8051F336/8 only)............................................ 52
9.1. IDA0 Output Scheduling.................................................................................... 52
9.1.1. Update Output On-Demand...................................................................... 52
9.1.2. Update Output Based on Timer Overflow................................................. 53
9.1.3. Update Output Based on CNVSTR Edge ................................................. 53
9.2. IDAC Output Mapping ....................................................................................... 53
10. Voltage Reference (C8051F336/8 only)................................................................ 56
11. Comparator0........................................................................................................... 58
11.1. Comparator Multiplexer................................................................................... 63
12. CIP-51 Microcontroller........................................................................................... 65
12.1. Instruction Set.................................................................................................. 66
12.1.1. Instruction and CPU Timing.................................................................... 66
12.2. CIP-51 Register Descriptions.......................................................................... 71
13. Memory Organization............................................................................................ 74
13.1. Program Memory............................................................................................. 75
13.1.1. MOVX Instruction and Program Memory................................................ 75
13.2. Data Memory................................................................................................... 75
13.2.1. Internal RAM........................................................................................... 75
13.2.1.1. General Purpose Registers ............................................................ 76
13.2.1.2. Bit Addressable Locations.............................................................. 76
13.2.1.3. Stack ............................................................................................ 76
13.2.2. External RAM.......................................................................................... 76
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4 Rev.1.0
14. Special Function Registers................................................................................... 78
15. Interrupts................................................................................................................ 82
15.1. MCU Interrupt Sources and Vectors................................................................ 83
15.1.1. Interrupt Priorities.................................................................................... 83
15.1.2. Interrupt Latency..................................................................................... 83
15.2. Interrupt Register Descriptions........................................................................ 84
15.3. External Interrupts /INT0 and /INT1................................................................. 89
16. Flash Memory......................................................................................................... 91
16.1. Programming The Flash Memory.................................................................... 91
16.1.1. Flash Lock and Key Functions................................................................ 91
16.1.2. Flash Erase Procedure ........................................................................... 91
16.1.3. Flash Write Procedure ............................................................................ 92
16.2. Non-volatile Data Storage ............................................................................... 92
16.3. Security Options.............................................................................................. 93
16.4. Flash Write and Erase Guidelines................................................................... 95
16.4.1. VDD Maintenance and the VDD monitor .................................................. 95
16.4.2. PSWE Maintenance................................................................................ 95
16.4.3. System Clock.......................................................................................... 96
17. Reset Sources...................................................................................................... 100
17.1. Power-On Reset............................................................................................ 101
17.2. Power-Fail Reset / VDD Monitor ................................................................... 102
17.3. External Reset............................................................................................... 103
17.4. Missing Clock Detector Reset ....................................................................... 103
17.5. Comparator0 Reset....................................................................................... 104
17.6. PCA Watchdog Timer Reset ......................................................................... 104
17.7. Flash Error Reset .......................................................................................... 104
17.8. Software Reset.............................................................................................. 104
18. Power Management Modes................................................................................. 106
18.1. Idle Mode....................................................................................................... 106
18.2. Stop Mode..................................................................................................... 107
18.3. Suspend Mode .............................................................................................. 107
19. Oscillators and Clock Selection......................................................................... 109
19.1. System Clock Selection................................................................................. 109
19.2. Programmable Internal High-Frequency (H-F) Oscillator.............................. 111
19.2.1. Internal Oscillator Suspend Mode......................................................... 111
19.3. Programmable Internal Low-Frequency (L-F) Oscillator ............................... 113
19.3.1. Calibrating the Internal L-F Oscillator.................................................... 113
19.4. External Oscillator Drive Circuit. .................................................................... 114
19.4.1. External Crystal Example...................................................................... 116
19.4.2. External RC Example............................................................................ 117
19.4.3. External Capacitor Example.................................................................. 118
20. Port Input/Output................................................................................................. 119
20.1. Port I/O Modes of Operation.......................................................................... 120
20.1.1. Port Pins Configured for Analog I/O...................................................... 120
20.1.2. Port Pins Configured For Digital I/O...................................................... 120
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Rev.1.0 5
20.1.3. Interfacing Port I/O to 5V Logic............................................................. 121
20.2. Assigning Port I/O Pins to Analog and Digital Functions............................... 122
20.2.1. Assigning Port I/O Pins to Analog Functions ........................................ 122
20.2.2. Assigning Port I/O Pins to Digital Functions.......................................... 122
20.2.3. Assigning Port I/O Pins to External Event Trigger Functions................ 123
20.3. Priority Crossbar Decoder............................................................................. 124
20.4. Port I/O Initialization ...................................................................................... 126
20.5. Port Match..................................................................................................... 129
20.6. Special Function Registers for Accessing and Configuring Port I/O ............. 131
21. SMBus................................................................................................................... 138
21.1. Supporting Documents.................................................................................. 139
21.2. SMBus Configuration..................................................................................... 139
21.3. SMBus Operation.......................................................................................... 139
21.3.1. Transmitter Vs. Receiver....................................................................... 140
21.3.2. Arbitration.............................................................................................. 140
21.3.3. Clock Low Extension............................................................................. 140
21.3.4. SCL Low Timeout.................................................................................. 140
21.3.5. SCL High (SMBus Free) Timeout ......................................................... 141
21.4. Using the SMBus........................................................................................... 141
21.4.1. SMBus Configuration Register.............................................................. 141
21.4.2. SMB0CN Control Register.................................................................... 145
21.4.2.1. Software ACK Generation ............................................................ 145
21.4.2.2. Hardware ACK Generation........................................................... 145
21.4.3. Hardware Slave Address Recognition .................................................. 147
21.4.4. Data Register........................................................................................ 150
21.5. SMBus Transfer Modes................................................................................. 151
21.5.1. Write Sequence (Master)...................................................................... 151
21.5.2. Read Sequence (Master)...................................................................... 152
21.5.3. Write Sequence (Slave)........................................................................ 153
21.5.4. Read Sequence (Slave)........................................................................ 154
21.6. SMBus Status Decoding................................................................................ 154
22. UART0................................................................................................................... 159
22.1. Enhanced Baud Rate Generation.................................................................. 160
22.2. Operational Modes........................................................................................ 161
22.2.1. 8-Bit UART............................................................................................ 161
22.2.2. 9-Bit UART............................................................................................ 162
22.3. Multiprocessor Communications ................................................................... 163
23. Enhanced Serial Peripheral Interface (SPI0)..................................................... 167
23.1. Signal Descriptions........................................................................................ 168
23.1.1. Master Out, Slave In (MOSI)................................................................. 168
23.1.2. Master In, Slave Out (MISO)................................................................. 168
23.1.3. Serial Clock (SCK)................................................................................ 168
23.1.4. Slave Select (NSS)............................................................................... 168
23.2. SPI0 Master Mode Operation........................................................................ 169
23.3. SPI0 Slave Mode Operation.......................................................................... 170
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6 Rev.1.0
23.4. SPI0 Interrupt Sources.................................................................................. 171
23.5. Serial Clock Phase and Polarity.................................................................... 171
23.6. SPI Special Function Registers..................................................................... 173
24. Timers................................................................................................................... 180
24.1. Timer 0 and Timer 1...................................................................................... 182
24.1.1. Mode 0: 13-bit Counter/Timer............................................................... 182
24.1.2. Mode 1: 16-bit Counter/Timer............................................................... 183
24.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload..................................... 184
24.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)... ............................. 185
24.2. Timer 2 .......................................................................................................... 190
24.2.1. 16-bit Timer with Auto-Reload............................................................... 190
24.2.2. 8-bit Timers with Auto-Reload............................................................... 191
24.2.3. Low-Frequency Oscillator (LFO) Capture Mode................................... 192
24.3. Timer 3 .......................................................................................................... 196
24.3.1. 16-bit Timer with Auto-Reload............................................................... 196
24.3.2. 8-bit Timers with Auto-Reload............................................................... 197
24.3.3. Low-Frequency Oscillator (LFO) Capture Mode................................... 198
25. Programmable Counter Array............................................................................. 202
25.1. PCA Counter/Timer....................................................................................... 203
25.2. PCA0 Interrupt Sources................................................................................. 204
25.3. Capture/Compare Modules ........................................................................... 205
25.3.1. Edge-triggered Capture Mode............................................................... 206
25.3.2. Software Timer (Compare) Mode.......................................................... 207
25.3.3. High-Speed Output Mode ..................................................................... 208
25.3.4. Frequency Output Mode ....................................................................... 209
25.3.5. 8-bit, 9-bit, 10-bit and 11-bit Pulse Width Modulator Modes................ 209
25.3.5.1. 8-bit Pulse Width Modulator Mode............................................... 210
25.3.5.2. 9/10/11-bit Pulse Width Modulator Mode..................................... 211
25.3.6. 16-Bit Pulse Width Modulator Mode..................................................... 212
25.4. Watchdog Timer Mode.................................................................................. 213
25.4.1. Watchdog Timer Operation................................................................... 213
25.4.2. Watchdog Timer Usage ........................................................................ 214
25.5. Register Descriptions for PCA0..................................................................... 215
26. C2 Interface .......................................................................................................... 221
26.1. C2 Interface Registers................................................................................... 221
26.2. C2 Pin Sharing .............................................................................................. 224
Document Change List............................................................................................. 225
Contact Information.................................................................................................. 226
C8051F336/7/8/9
Rev.1.0 7
List of Figures
1. System Overview
Figure 1.1. C8051F336/7 Block Diagram ................................................................ 16
Figure 1.2. C8051F338/9 Block Diagram ................................................................ 17
2. Ordering Information
3. Pin Definitions
Figure 3.1. QFN-20 Pinout Diagram (Top View) ..................................................... 21
Figure 3.2. QFN-24 Pinout Diagram (Top View) ..................................................... 22
4. QFN-20 Package Specifications
Figure 4.1. QFN-20 Package Drawing .................................................................... 23
Figure 4.2. QFN-20 Recommended PCB Land Pattern .......................................... 24
5. QFN-24 Package Specifications
Figure 5.1. QFN-24 Package Drawing .................................................................... 25
Figure 5.2. QFN-24 Recommended PCB Land Pattern .......................................... 26
6. Electrical Characteristics
Figure 6.1. Normal Mode Digital Supply Current vs. Frequency ............................. 36
Figure 6.2. Idle Mode Digital Supply Current vs. Frequency ................................... 36
7. 10-Bit ADC (ADC0, C8051F336/8 only)
Figure 7.1. ADC0 Functional Block Diagram ........................................................... 37
Figure 7.2. 10-Bit ADC Track and Conversion Example Timing ............................. 39
Figure 7.3. ADC0 Equivalent Input Circuits ............................................................. 40
Figure 7.4. ADC Window Compare Example: Right-Justified Single-Ended Data .. 46
Figure 7.5. ADC Window Compare Example: Left-Justified Single-Ended Data ..... 46
Figure 7.6. ADC Window Compare Example: Right-Justified Differential Data ....... 47
Figure 7.7. ADC Window Compare Example: Left-Justified Differential Data ......... 47
Figure 7.8. ADC0 Multiplexer Block Diagram .......................................................... 48
8. Temperature Sensor (C8051F336/8 only)
Figure 8.1. Temperature Sensor Transfer Function ................................................ 51
9. 10-Bit Current Mode DAC (IDA0, C8051F336/8 only)
Figure 9.1. IDA0 Functional Block Diagram ............................................................ 52
Figure 9.2. IDA0 Data Word Mapping ..................................................................... 53
10. Voltage Reference (C8051F336/8 only)
Figure 10.1. Voltage Reference Functional Block Diagram ..................................... 56
11. Comparator0
Figure 11.1. Comparator0 Functional Block Diagram ............................................. 58
Figure 11.2. Comparator Hysteresis Plot ................................................................ 59
Figure 11.3. Comparator Input Multiplexer Block Diagram ...................................... 63
12. CIP-51 Microcontroller
Figure 12.1. CIP-51 Block Diagram ......................................................................... 65
13. Memory Organization
Figure 13.1. C8051F336/7/8/9 Memory Map ........................................................... 74
Figure 13.2. Flash Program Memory Map ............................................................... 75
14. Special Function Registers
C8051F336/7/8/9
8 Rev.1.0
15. Interrupts
16. Flash Memory
Figure 16.1. Security Byte Decoding ....................................................................... 93
17. Reset Sources
Figure 17.1. Reset Sources ................................................................................... 100
Figure 17.2. Power-On and VDD Monitor Reset Timing ....................................... 101
18. Power Management Modes
19. Oscillators and Clock Selection
Figure 19.1. Oscillator Options .............................................................................. 109
Figure 19.2. External 32.768 kHz Quartz Crystal Oscillator Connection Diagram 117
20. Port Input/Output
Figure 20.1. Port I/O Functional Block Diagram .................................................... 119
Figure 20.2. Port I/O Cell Block Diagram .............................................................. 121
Figure 20.3. Port I/O Overdrive Current ................................................................ 121
Figure 20.4. Crossbar Priority Decoder - Possible Pin Assignments .................... 124
Figure 20.5. Crossbar Priority Decoder Example .................................................. 125
21. SMBus
Figure 21.1. SMBus Block Diagram ...................................................................... 138
Figure 21.2. Typical SMBus Configuration ............................................................ 139
Figure 21.3. SMBus Transaction ........................................................................... 140
Figure 21.4. Typical SMBus SCL Generation ........................................................ 142
Figure 21.5. Typical Master Write Sequence ........................................................ 151
Figure 21.6. Typical Master Read Sequence ........................................................ 152
Figure 21.7. Typical Slave Write Sequence .......................................................... 153
Figure 21.8. Typical Slave Read Sequence .......................................................... 154
22. UART0
Figure 22.1. UART0 Block Diagram ...................................................................... 159
Figure 22.2. UART0 Baud Rate Logic ................................................................... 160
Figure 22.3. UART Interconnect Diagram ............................................................. 161
Figure 22.4. 8-Bit UART Timing Diagram .............................................................. 161
Figure 22.5. 9-Bit UART Timing Diagram .............................................................. 162
Figure 22.6. UART Multi-Processor Mode Interconnect Diagram ......................... 163
23. Enhanced Serial Peripheral Interface (SPI0)
Figure 23.1. SPI Block Diagram ............................................................................ 167
Figure 23.2. Multiple-Master Mode Connection Diagram ...................................... 169
Figure 23.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram
170
Figure 23.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram
170
Figure 23.5. Master Mode Data/Clock Timing ....................................................... 172
Figure 23.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................... 172
Figure 23.7. Slave Mode Data/Clock Timing (CKPHA = 1) ................................... 173
Figure 23.8. SPI Master Timing (CKPHA = 0) ....................................................... 177
Figure 23.9. SPI Master Timing (CKPHA = 1) ....................................................... 177
Figure 23.10. SPI Slave Timing (CKPHA = 0) ....................................................... 178
C8051F336/7/8/9
Rev.1.0 9
Figure 23.11. SPI Slave Timing (CKPHA = 1) ....................................................... 178
24. Timers
Figure 24.1. T0 Mode 0 Block Diagram ................................................................. 183
Figure 24.2. T0 Mode 2 Block Diagram ................................................................. 184
Figure 24.3. T0 Mode 3 Block Diagram ................................................................. 185
Figure 24.4. Timer 2 16-Bit Mode Block Diagram ................................................. 190
Figure 24.5. Timer 2 8-Bit Mode Block Diagram ................................................... 191
Figure 24.6. Timer 2 Low-Frequency Oscillation Capture Mode Block Diagram ... 192
Figure 24.7. Timer 3 16-Bit Mode Block Diagram ................................................. 196
Figure 24.8. Timer 3 8-Bit Mode Block Diagram ................................................... 197
Figure 24.9. Timer 3 Low-Frequency Oscillation Capture Mode Block Diagram ... 198
25. Programmable Counter Array
Figure 25.1. PCA Block Diagram ........................................................................... 202
Figure 25.2. PCA Counter/Timer Block Diagram ................................................... 203
Figure 25.3. PCA Interrupt Block Diagram ............................................................ 204
Figure 25.4. PCA Capture Mode Diagram ............................................................. 206
Figure 25.5. PCA Software Timer Mode Diagram ................................................. 207
Figure 25.6. PCA High-Speed Output Mode Diagram ........................................... 208
Figure 25.7. PCA Frequency Output Mode ........................................................... 209
Figure 25.8. PCA 8-Bit PWM Mode Diagram ........................................................ 210
Figure 25.9. PCA 9, 10 and 11-Bit PWM Mode Diagram ...................................... 211
Figure 25.10. PCA 16-Bit PWM Mode ................................................................... 212
Figure 25.11. PCA Module 2 with Watchdog Timer Enabled ................................ 213
26. C2 Interface
Figure 26.1. Typical C2 Pin Sharing ...................................................................... 224
C8051F336/7/8/9
Rev.1.0 10
List of Tables
1. System Overview
2. Ordering Information
Table 2.1. Product Selection Guide .........................................................................18
3. Pin Definitions
Table 3.1. Pin Definitions for the C8051F336/7/8/9 .................................................19
4. QFN-20 Package Specifications
Table 4.1. QFN-20 Package Dimensions ................................................................23
Table 4.2. QFN-20 PCB Land Pattern Dimesions ...................................................24
5. QFN-24 Package Specifications
Table 5.1. QFN-24 Package Dimensions ................................................................25
Table 5.2. QFN-24 PCB Land Pattern Dimesions ...................................................26
6. Electrical Characteristics
Table 6.1. Absolute Maximum Ratings ....................................................................27
Table 6.2. Global Electrical Characteristics .............................................................28
Table 6.3. Port I/O DC Electrical Characteristics .....................................................29
Table 6.4. Reset Electrical Characteristics ..............................................................30
Table 6.5. Flash Electrical Characteristics ...............................................................30
Table 6.6. Internal High-Frequency Oscillator Electrical Characteristics .................31
Table 6.7. Internal Low-Frequency Oscillator Electrical Characteristics ..................31
Table 6.8. ADC0 Electrical Characteristics ..............................................................32
Table 6.9. Temperature Sensor Electrical Characteristics ......................................33
Table 6.10. Voltage Reference Electrical Characteristics ........................................33
Table 6.11. IDAC Electrical Characteristics .............................................................34
Table 6.12. Comparator Electrical Characteristics ..................................................35
7. 10-Bit ADC (ADC0, C8051F336/8 only)
8. Temperature Sensor (C8051F336/8 only)
9. 10-Bit Current Mode DAC (IDA0, C8051F336/8 only)
10. Voltage Reference (C8051F336/8 only)
11. Comparator0
12. CIP-51 Microcontroller
Table 12.1. CIP-51 Instruction Set Summary ..........................................................67
13. Memory Organization
14. Special Function Registers
Table 14.1. Special Function Register (SFR) Memory Map ....................................78
Table 14.2. Special Function Registers ...................................................................79
15. Interrupts
Table 15.1. Interrupt Summary ................................................................................84
16. Flash Memory
Table 16.1. Flash Security Summary .......................................................................94
17. Reset Sources
18. Power Management Modes
19. Oscillators and Clock Selection
20. Port Input/Output
C8051F336/7/8/9
11 Rev.1.0
Table 20.1. Port I/O Assignment for Analog Functions ......................................... 122
Table 20.2. Port I/O Assignment for Digital Functions ........................................... 122
Table 20.3. Port I/O Assignment for External Event Trigger Functions ................. 123
21. SMBus
Table 21.1. SMBus Clock Source Selection .......................................................... 142
Table 21.2. Minimum SDA Setup and Hold Times ................................................ 143
Table 21.3. Sources for Hardware Changes to SMB0CN ..................................... 147
Table 21.4. Hardware Address Recognition Examples (EHACK = 1) ................... 148
Table 21.5. SMBus Status Decoding With Hardware ACK Generation Disabled
(EHACK = 0) ....................................................................................... 155
Table 21.6. SMBus Status Decoding With Hardware ACK Generation Enabled
(EHACK = 1) ....................................................................................... 157
22. UART0
Table 22.1. Timer Settings for Standard Baud Rates
Using The Internal 24.5 MHz Oscillator .............................................. 166
Table 22.2. Timer Settings for Standard Baud Rates
Using an External 22.1184 MHz Oscillator ......................................... 166
23. Enhanced Serial Peripheral Interface (SPI0)
Table 23.1. SPI Slave Timing Parameters ............................................................ 179
24. Timers
25. Programmable Counter Array
Table 25.1. PCA Timebase Input Options ............................................................. 203
Table 25.2. PCA0CPM and PCA0PWM Bit Settings for PCA Capture/Compare Mod-
ules ..................................................................................................... 205
Table 25.3. Watchdog Timer Timeout Intervals1 ................................................... 214
26. C2 Interface
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Rev.1.0 12
List of Registers
SFR Definition 7.1. ADC0CF: ADC0 Configuration ...................................................... 41
SFR Definition 7.2. ADC0H: ADC0 Data Word MSB .................................................... 42
SFR Definition 7.3. ADC0L: ADC0 Data Word LSB ...................................................... 42
SFR Definition 7.4. ADC0CN: ADC0 Control ................................................................ 43
SFR Definition 7.5. ADC0GTH: ADC0 Greater-Than Data High Byte .......................... 44
SFR Definition 7.6. ADC0GTL: ADC0 Greater-Than Data Low Byte ............................ 44
SFR Definition 7.7. ADC0LTH: ADC0 Less-Than Data High Byte ................................ 45
SFR Definition 7.8. ADC0LTL: ADC0 Less-Than Data Low Byte ................................. 45
SFR Definition 7.9. AMX0P: AMUX0 Positive Channel Select ..................................... 49
SFR Definition 7.10. AMX0N: AMUX0 Negative Channel Select ................................. 50
SFR Definition 9.1. IDA0CN: IDA0 Control ................................................................... 54
SFR Definition 9.2. IDA0H: IDA0 Data Word MSB ....................................................... 55
SFR Definition 9.3. IDA0L: IDA0 Data Word LSB ......................................................... 55
SFR Definition 10.1. REF0CN: Reference Control ....................................................... 57
SFR Definition 11.1. CPT0CN: Comparator0 Control ................................................... 61
SFR Definition 11.2. CPT0MD: Comparator0 Mode Selection ..................................... 62
SFR Definition 11.3. CPT0MX: Comparator0 MUX Selection ...................................... 64
SFR Definition 12.1. DPL: Data Pointer Low Byte ........................................................ 71
SFR Definition 12.2. DPH: Data Pointer High Byte ....................................................... 71
SFR Definition 12.3. SP: Stack Pointer ......................................................................... 72
SFR Definition 12.4. ACC: Accumulator ....................................................................... 72
SFR Definition 12.5. B: B Register ................................................................................ 72
SFR Definition 12.6. PSW: Program Status Word ........................................................ 73
SFR Definition 13.1. EMI0CN: External Memory Interface Control .............................. 77
SFR Definition 15.1. IE: Interrupt Enable ...................................................................... 85
SFR Definition 15.2. IP: Interrupt Priority ...................................................................... 86
SFR Definition 15.3. EIE1: Extended Interrupt Enable 1 .............................................. 87
SFR Definition 15.4. EIP1: Extended Interrupt Priority 1 .............................................. 88
SFR Definition 15.5. IT01CF: INT0/INT1 Configuration ................................................ 90
SFR Definition 16.1. PSCTL: Program Store R/W Control ........................................... 97
SFR Definition 16.2. FLKEY: Flash Lock and Key ........................................................ 98
SFR Definition 16.3. FLSCL: Flash Scale ..................................................................... 99
SFR Definition 17.1. VDM0CN: VDD Monitor Control ................................................ 103
SFR Definition 17.2. RSTSRC: Reset Source ............................................................ 105
SFR Definition 18.1. PCON: Power Control ................................................................ 108
SFR Definition 19.1. CLKSEL: Clock Select ............................................................... 110
SFR Definition 19.2. OSCICL: Internal H-F Oscillator Calibration .............................. 111
SFR Definition 19.3. OSCICN: Internal H-F Oscillator Control ................................... 112
SFR Definition 19.4. OSCLCN: Internal L-F Oscillator Control ................................... 113
SFR Definition 19.5. OSCXCN: External Oscillator Control ........................................ 115
SFR Definition 20.1. XBR0: Port I/O Crossbar Register 0 .......................................... 127
SFR Definition 20.2. XBR1: Port I/O Crossbar Register 1 .......................................... 128
SFR Definition 20.3. P0MASK: Port 0 Mask Register ................................................. 129
C8051F336/7/8/9
13 Rev.1.0
SFR Definition 20.4. P0MAT: Port 0 Match Register .................................................. 130
SFR Definition 20.5. P1MASK: Port 1 Mask Register ................................................. 130
SFR Definition 20.6. P1MAT: Port 1 Match Register .................................................. 131
SFR Definition 20.7. P0: Port 0 ................................................................................... 132
SFR Definition 20.8. P0MDIN: Port 0 Input Mode ....................................................... 132
SFR Definition 20.9. P0MDOUT: Port 0 Output Mode ................................................ 133
SFR Definition 20.10. P0SKIP: Port 0 Skip ................................................................. 133
SFR Definition 20.11. P1: Port 1 ................................................................................. 134
SFR Definition 20.12. P1MDIN: Port 1 Input Mode ..................................................... 134
SFR Definition 20.13. P1MDOUT: Port 1 Output Mode .............................................. 135
SFR Definition 20.14. P1SKIP: Port 1 Skip ................................................................. 135
SFR Definition 20.15. P2: Port 2 ................................................................................. 136
SFR Definition 20.16. P2MDIN: Port 2 Input Mode ..................................................... 136
SFR Definition 20.17. P2MDOUT: Port 2 Output Mode .............................................. 137
SFR Definition 20.18. P2SKIP: Port 2 Skip ................................................................. 137
SFR Definition 21.1. SMB0CF: SMBus Clock/Configuration ...................................... 144
SFR Definition 21.2. SMB0CN: SMBus Control .......................................................... 146
SFR Definition 21.3. SMB0ADR: SMBus Slave Address ............................................ 148
SFR Definition 21.4. SMB0ADM: SMBus Slave Address Mask .................................. 149
SFR Definition 21.5. SMB0DAT: SMBus Data ............................................................ 150
SFR Definition 22.1. SCON0: Serial Port 0 Control .................................................... 164
SFR Definition 22.2. SBUF0: Serial (UART0) Port Data Buffer .................................. 165
SFR Definition 23.1. SPI0CFG: SPI0 Configuration ................................................... 174
SFR Definition 23.2. SPI0CN: SPI0 Control ............................................................... 175
SFR Definition 23.3. SPI0CKR: SPI0 Clock Rate ....................................................... 176
SFR Definition 23.4. SPI0DAT: SPI0 Data ................................................................. 176
SFR Definition 24.1. CKCON: Clock Control .............................................................. 181
SFR Definition 24.2. TCON: Timer Control ................................................................. 186
SFR Definition 24.3. TMOD: Timer Mode ................................................................... 187
SFR Definition 24.4. TL0: Timer 0 Low Byte ............................................................... 188
SFR Definition 24.5. TL1: Timer 1 Low Byte ............................................................... 188
SFR Definition 24.6. TH0: Timer 0 High Byte ............................................................. 189
SFR Definition 24.7. TH1: Timer 1 High Byte ............................................................. 189
SFR Definition 24.8. TMR2CN: Timer 2 Control ......................................................... 193
SFR Definition 24.9. TMR2RLL: Timer 2 Reload Register Low Byte .......................... 194
SFR Definition 24.10. TMR2RLH: Timer 2 Reload Register High Byte ...................... 194
SFR Definition 24.11. TMR2L: Timer 2 Low Byte ....................................................... 194
SFR Definition 24.12. TMR2H Timer 2 High Byte ....................................................... 195
SFR Definition 24.13. TMR3CN: Timer 3 Control ....................................................... 199
SFR Definition 24.14. TMR3RLL: Timer 3 Reload Register Low Byte ........................ 200
SFR Definition 24.15. TMR3RLH: Timer 3 Reload Register High Byte ...................... 200
SFR Definition 24.16. TMR3L: Timer 3 Low Byte ....................................................... 200
SFR Definition 24.17. TMR3H Timer 3 High Byte ....................................................... 201
SFR Definition 25.1. PCA0CN: PCA Control .............................................................. 215
SFR Definition 25.2. PCA0MD: PCA Mode ................................................................ 216
C8051F336/7/8/9
Rev.1.0 14
SFR Definition 25.3. PCA0PWM: PCA PWM Configuration ....................................... 217
SFR Definition 25.4. PCA0CPMn: PCA Capture/Compare Mode .............................. 218
SFR Definition 25.5. PCA0L: PCA Counter/Timer Low Byte ...................................... 219
SFR Definition 25.6. PCA0H: PCA Counter/Timer High Byte ..................................... 219
SFR Definition 25.7. PCA0CPLn: PCA Capture Module Low Byte ............................. 220
SFR Definition 25.8. PCA0CPHn: PCA Capture Module High Byte ........................... 220
C2 Register Definition 26.1. C2ADD: C2 Address ...................................................... 221
C2 Register Definition 26.2. DEVICEID: C2 Device ID ............................................... 222
C2 Register Definition 26.3. REVID: C2 Revision ID .................................................. 222
C2 Register Definition 26.4. FPCTL: C2 Flash Programming Control ........................ 223
C2 Register Definition 26.5. FPDAT: C2 Flash Programming Data ............................ 223
C8051F336/7/8/9
Rev.1.0 15
1. System Overview
C8051F336/7/8/9 devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features
are listed below. Refer to Section “2. Ordering Information” on page 18 for specific product feature
selection and part ordering numbers.
High-speed pipelined 8051-compatible microcontroller core (up to 25 MIPS)
In-system, full-speed, non-intrusive debug interface (on-chip)
True 10-bit 200 ksps 20-channel single-ended/differential ADC with analog multiplexer
10-bit Current Output DAC
Precision programmable 24.5 MHz internal oscillator
Low-power, low-frequency oscillator
16 kB of on-chip Flash memory—512 bytes are reserved
768 bytes of on-chip RAM
SMBus/I2C, Enhanced UART, and Enhanced SPI serial interfaces implemented in hardware
Four general- pu rp o se 16 - bit tim er s
Programmable Counter/Timer Array (PCA) with three capture/compare modules and Watchdog Timer
function
On-chip Power-On Reset, VDD Monitor, and Temperature Sensor
On-chip Voltage Comparator
21 or 17 Port I/O (5 V tolerant)
Low-power susp en d mo d e with fast wake-u p tim e
With on-chip Power-On Reset, VDD monitor, Watchdog Timer, and clock oscillator, the C8051F336/7/8/9
devices are truly stand-alone System-on-a-Chip solutions. The Flash me mory can be reprogrammed even
in-circuit, providing non-volatile data storage, and also allowing field upgrades of the 8051 firmware. User
software has complete control of all peripherals, and may individually sh ut down any or all pe ripherals for
power savings.
The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip
resources), full speed, in-circuit debugging using the production MCU installed in the final application. This
debug logic supports inspection and modification of memory and registers, setting breakpoints, single
stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging
using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging with-
out occupying package pins.
Each device is specified for 2.7 to 3.6 V operation over the industrial temperature range (–40 to +85 °C).
The Port I/O and RST pins are tolerant of input signals up to 5 V. The C8051F336/7 are available in a 20-
pin QFN packa ge and the C8051F33 8/9 are availa ble in a 24-pin QFN p ackage. Both package options are
lead-free and RoHS compliant. See Section “2. Ordering Information” on page 18 for ordering informa-
tion. Block diagrams are included in Figure 1.1 and Figure 1.2.
C8051F336/7/8/9
16 Rev.1.0
Figure 1.1. C8051F336/7 Block Diagram
Port 0
Drivers
Digital Peripherals
UART
Timers 0,
1, 2, 3
PCA/
WDT
SMBus
Priority
Crossbar
Decoder
P0.0/VREF
P0.1/IDA0
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7
Crossbar Cont rol
Port I/O Configuration
CIP-51 8051
Controller Core
16k Byte ISP Flash
Program Memory
256 Byte SRAM
SFR
Bus
512 Byte XRAM
Port 1
Drivers
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
Port 2
Drivers P2.0/C2D
SPI
Analog Peripherals
Comparator
+
-
Power Net
VDD
GND
XTAL1
SYSCLK
System Clock
Configuration
External
Oscillator
Circuit
Precision
24.5 MHz
Oscillator
Debug /
Programming
Hardware
Power On
Reset
Reset
C2D
C2CK/RST
10-bit
200 ksps
ADC
A
M
U
XTemp
Sensor
VREFVDD
VDD
C8051F336 Only
XTAL2
Low-Freq.
Oscillator
10-bit
IDAC
VREF
GND
P1.6
P1.7
IDA0
CP0, CP0A
C8051F336/7/8/9
Rev.1.0 17
Figure 1.2. C8051F338/9 Block Diagram
Port 0
Drivers
Digital Peripheral s
UART
Timers 0,
1, 2, 3
PCA/
WDT
SMBus
Priority
Crossbar
Decoder
P0.0/VREF
P0.1/IDA0
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7
Crossbar Control
Port I/O Configuration
CIP-51 8051
Controller Core
16 kB ISP Flash
Program Memory
256 Byte SRAM
SFR
Bus
512 Byte XRAM
Port 1
Drivers
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
Port 2
Drivers
P2.0
P2.1
P2.2
P2.3
P2.4/C2D
SPI
Analog Peripherals
Comparator
+
-
Power Net
VDD
GND
XTAL1
SYSCLK
System Clock
Configuration
External
Oscillator
Circuit
Precision
24.5 MHz
Oscillator
Debug /
Programming
Hardware
Power On
Reset
Reset
C2D
C2CK/RST
10-bit
200 ksps
ADC
A
M
U
XTemp
Sensor
VREFVDD
VDD
C8051F338 Only
XTAL2
Low-Freq.
Oscillator
10-bit
IDAC
VREF
GND
P1.6
P1.7
IDA0
CP0, CP0A
C8051F336/7/8/9
Rev.1.0 18
2. Ordering Information
Table 2.1. Product Selection Guide
Ordering Part Number
MIPS (Peak)
Flash Memory (kB)
RAM (bytes)
Calibrated Internal 24.5 MHz Oscillator
Internal 80 kHz Oscillator
SMBus/I2C
Enhanced SPI
UART
Timers (16-bit)
RTC OPeration
Programmable Counter Array
Digital Port I/Os
10-bit 200ks ps ADC
10-bit Cu rrent Output DAC
Internal Voltage Reference
Temperature Sensor
Analog Comparator
Lead-Free / RoHS Compliant
Package
C8051F336-GM2516768YYYYY4YY17YYYYYYQFN-20
C8051F337-GM2516768YYYYY4YY17————YYQFN-20
C8051F338-GM2516768YYYYY4YY21YYYYYYQFN-24
C8051F339-GM2516768YYYYY4YY21————YYQFN-24
C8051F336/7/8/9
Rev.1.0 19
3. Pin Definitions
Table 3.1. Pin Definitions for the C8051F336/7/8/9
Name Pin
’F336/7 Pin
’F338/9 Type Description
VDD 3 4 Power Supply Voltage.
GND 2 3 Ground.
This ground connection is required. The center pad may
optionally be connected to ground also.
RST/ 4 5 D I/O Device Reset. Open-drain output of internal POR or VDD
monitor. An external source can initiate a system reset by
driving this pin low for at least 10 µs.
C2CK D I/O Clock signal for th e C2 De bu g In te rfa ce .
C2D 5 6 D I/O Bi-directional dat a signal for the C2 Debug Interface.
Shared with P2.0 on 20-pin packaging and P2.4 on 24-pin
packaging.
P0.0/ 1 2 D I/O or
A In Port 0.0.
VREF A In External VREF input.
P0.1 20 1 D I/O or
A In Port 0.1.
IDA0 A Out IDA0 Output.
P0.2/ 19 24 D I/O or
A In Port 0.2.
XTAL1 A In External Clock Input. This pin is the external oscillator
return for a crystal or resonator.
P0.3/ 18 23 D I/O or
A In Port 0.3.
XTAL2 A I/O or
D In External Clock Output. For an external crystal or resonator,
this pin is the excit ation d river. This pin is the external clock
input for CMOS, capacitor, or RC oscillator configurations.
P0.4 17 22 D I/O or
A In Port 0.4.
P0.5 16 21 D I/O or
A In Port 0.5.
P0.6/ 15 20 D I/O or
A In Port 0.6.
CNVSTR D In ADC0 External Convert Start or IDA0 Update Source Input.
C8051F336/7/8/9
20 Rev.1.0
P0.7 14 19 D I/O or
A In Port 0.7.
P1.0 13 18 D I/O or
A In Port 1.0.
P1.1 12 17 D I/O or
A In Port 1.1.
P1.2 11 16 D I/O or
A In Port 1.2.
P1.3 10 15 D I/O or
A In Port 1.3.
P1.4 9 14 D I/O or
A In Port 1.4.
P1.5 8 13 D I/O or
A In Port 1.5.
P1.6 7 12 D I/O or
A In Port 1.6.
P1.7 6 11 D I/O or
A In Port 1.7.
P2.0 5 10 D I/O or
A In Port 2.0. (Also C2D on 20 -p in Pa ckagin g )
P2.1 — 9 D I/O or
A In Port 2.1.
P2.2 — 8 D I/O or
A In Port 2.2.
P2.3 — 7 D I/O or
A In Port 2.3.
P2.4 — 6 D I/O Port 2.4. (Also C2D on 24-pin Pa cka gin g )
Table 3.1. Pin Definitions for the C8051F336/7/8/9 (Continued)
Name Pin
’F336/7 Pin
’F338/9 Type Description
C8051F336/7/8/9
Rev.1.0 21
Figure 3.1. QFN-20 Pinout Diagram (Top View)
3
4
5
1
2
8
9
10
6
7
13
12
11
15
14
18
19
20
16
17
P0.0
GND
VDD
/RST/C2CK
P2.0/C2D
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
C8051F336/7
Top View
GND (optional)
C8051F336/7/8/9
22 Rev.1.0
Figure 3.2. QFN-24 Pinout Diagram (Top View)
3
4
5
1
2
9
10
11
7
8
16
15
14
18
17
22
23
24
20
21
P0.0
GND
VDD
/RST/C2CK
P2.4/C2D
P1.7
P1.6
P2.3
P2.2
P2.1
P1.2
P1.1
P1.0
P1.5
P1.4
P0.5
P0.4
P0.3
P0.2
P0.7
C8051F338/9
Top View
6
12
P2.0
13
P1.3
19
P0.6
P0.1
GND (optional)
C8051F336/7/8/9
Rev.1.0 23
4. QFN-20 Package Specifications
Figure 4.1. QFN-20 Package Drawing
Table 4.1. QFN-20 Package Dimensions
Dimension Min Typ Max Dimension Min Typ Max
A 0.80 0.90 1.00 L 0.45 0.55 0.65
A1 0.00 0.02 0.05 L1 0.00 — 0.15
b 0.18 0.25 0.30 aaa — — 0.15
D 4.00 BSC. bbb — — 0.10
D2 2.00 2.15 2.25 ddd — — 0.05
e 0.50 BSC. eee — — 0.08
E 4.00 BSC. Z — 0.43 —
E2 2.00 2.15 2.25 Y — 0.18 —
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted .
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-22 0, variation VGGD except for
custom features D2, E2, Z, Y, and L which are toleranced per supplier designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small
Body Components.
C8051F336/7/8/9
24 Rev.1.0
Figure 4.2. QFN-20 Recommended PCB Land Pattern
Table 4.2. QFN-20 PCB Land Pattern Dimesions
Dimension Min Max Dimension Min Max
C1 3.70 X2 2.15 2.25
C2 3.70 Y1 0.90 1.00
E 0.50 Y2 2.15 2.25
X1 0.20 0.30
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted .
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is base d on the IPC-7351 guidelines.
Solder Mask Design
4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60μm minimum, all the way around the pad.
Stencil Design
5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
to assure good solder paste release.
6. The stencil thickness should be 0.125mm (5 mils).
7. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
8. A 2x2 array of 0.95mm openings on a 1.1mm pitch should be used for the center pad to
assure the proper paste volume (71% Paste Coverage).
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for
Small Body Components.
C8051F336/7/8/9
Rev.1.0 25
5. QFN-24 Package Specifications
Figure 5.1. QFN-24 Package Drawing
Table 5.1. QFN-24 Package Dimensions
Dimension Min Typ Max Dimension Min Typ Max
A 0.70 0.75 0.80 L 0.30 0.40 0.50
A1 0.00 0.02 0.05 L1 0.00 — 0.15
b 0.18 0.25 0.30 aaa — — 0.15
D 4.00 BSC. bbb — — 0.10
D2 2.55 2.70 2.80 ddd — — 0.05
e 0.50 BSC. eee — — 0.08
E 4.00 BSC. Z — 0.24 —
E2 2.55 2.70 2.80 Y — 0.18 —
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted .
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Solid State Outli ne MO-220, variation WGGD except for
custom features D2, E2, Z, Y, and L which are toleranced per supplier designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small
Body Components.
C8051F336/7/8/9
26 Rev.1.0
Figure 5.2. QFN-24 Recommended PCB Land Pattern
Table 5.2. QFN-24 PCB Land Pattern Dimesions
Dimension Min Max Dimension Min Max
C1 3.90 4.00 X2 2.70 2.80
C2 3.90 4.00 Y1 0.65 0.75
E 0.50 BSC Y2 2.70 2.80
X1 0.20 0.30
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted .
2. This Land Pattern Design is base d on the IPC-7351 guidelines.
Solder Mask Design
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60μm minimum, all the way around the pad.
Stencil Design
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
to assure good solder paste release.
5. The stencil thickness should be 0.125mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
7. A 2x2 array of 1.10mm x 1.10mm openings on a 1.30mm pitch should be used for the center
pad.
Card Assembly
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for
Small Body Components.
C8051F336/7/8/9
Rev.1.0 27
6. Electrical Characteristics
6.1. Absolute Maximum Specifications
Table 6.1. Absolute Maximum Ratings
Parameter Conditions Min Typ Max Units
Ambient temperature under bias –55 — 125 °C
Storage Temperature –65 — 150 °C
Voltage on any Port I/O Pin or RST with
respect to GND –0.3 — 5.8 V
Voltage on VDD with respect to GND –0.3 — 4.2 V
Maximum Total current through VDD or GND — — 500 mA
Maximum output current sunk by RST or any
Port pin ——100mA
Note: S tresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the devi ces at th ose or any other cond itions above
those indicated in the operation list ings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
C8051F336/7/8/9
28 Rev.1.0
6.2. Electrical Characteristics
Table 6.2. Global Electrical Characteristics
–40 to +85 °C, 25 MHz system clock unless othe rwise specified.
Parameter Conditions Min Typ Max Units
Digital Supply Voltage Normal Operation VRST13.0 3.6 V
Writing or Erasing Flash Memory 2.7 3.0 3.6 V
Digital Supply RAM Data
Retention Voltage —1.5— V
SYSCLK (System Clock)
(Note 2) 0—25MHz
TSYSH (SYSCLK High Time) 18 — — ns
TSYSL (SYSCLK Low Time) 18 — — ns
Specified Operating
Temperature Range –40 — +85 °C
Digital Supply Current—CPU Active (Normal Mode, fetching instructions from Flash)
IDD (Note 3) VDD = 3.6 V, F = 25 MHz — 11.0 13.0 mA
VDD = 3.0 V, F = 25 MHz — 8.0 10.0 mA
VDD = 3.6 V, F = 1 MHz — 0.56 — mA
VDD = 3.0 V, F = 1 MHz — 0.42 — mA
VDD = 3.0 V, F = 80 kHz — 35 — µA
Digital Supply Current—CPU Inactive (Idle Mode, not fetching instructions from Flash)
IDD (Note 3) VDD = 3.6 V, F = 25 MHz — 5.0 6.0 mA
VDD = 3.0 V, F = 25 MHz — 4.1 5. 0 mA
VDD = 3.6 V, F = 1 MHz — 0.20 — mA
VDD = 3.0 V, F = 1 MHz — 0.16 — mA
VDD = 3.0 V, F = 80 kHz — 13 — µA
Digital Supply Current
(Stop or Suspend Mode, shut-
down)
Oscillator not running,
VDD Monitor Disabled —< 0.1— µA
Notes:
1. Given in Tabl e 6.4 on page 30.
2. SYSCLK must be at least 32 kHz to enable debugging.
3. Based on device characterization data; Not production tested.
C8051F336/7/8/9
Rev.1.0 29
Table 6.3. Port I/O DC Electrical Characteristics
VDD = 2.7 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameters Conditions Min Typ Max Units
Output High Voltage IOH = –3 mA, Port I/O push-pull VDD – 0.7 — — V
IOH = –10 µA, Port I/O push-pull VDD – 0.1 — — V
IOH = –10 mA, Port I/O push-pull — VDD – 0.8 — V
Output Low Voltage IOL = 8.5 mA — — 0.6 V
IOL = 10 µA — — 0.1 V
IOL = 25 mA — 1.0 — V
Input High Vo ltage 2.0 — — V
Input Low Vo ltage — — 0.8 V
Input Leakag e
Current Weak Pullup Off — — ±1 µA
Weak Pullup On, VIN = 0 V — 50 100 µA
C8051F336/7/8/9
30 Rev.1.0
Table 6.4. Reset Electrical Characteristics
–40 to +85 °C unless otherwise specified.
Parameter Conditions Min Typ Max Units
RST Output Low Voltage IOL = 8.5 mA,
VDD = 2.7 V to 3.6 V ——0.6V
RST Input Low Voltage — — 0.6
RST Input Pullup Current RST = 0.0 V — 50 100 µA
VDD POR Threshold (VRST) 2.40 2.55 2.70 V
Missing Clock Detector Time-
out Time from last system clock
rising edge to reset initiation 100 220 600 µs
Reset Time Delay Delay between release of any
reset source and code
execution at location 0x0000
——40µs
Minimum RST Low Time to
Generate a System Reset 15 — — µs
VDD Monitor Turn-on Time 100 — — µs
VDD Monitor Supply Current — 20 40 µA
Table 6.5. Flash Electrical Characteristics
VDD = 2.7 to 3.6 V; –40 to +85 ºC unless otherwise specified.
Parameter Conditions Min Typ Max Units
Flash Size 16384* — — bytes
Endurance 20 k 100 k — Erase/Write
Erase Cycle Time 25 MHz System Clock 10 15 20 ms
Write Cycle Time 25 MHz System Clock 40 55 70 µs
Note: 512 bytes at addresses 0x3E00 to 0x3FF F are reserved.
C8051F336/7/8/9
Rev.1.0 31
Table 6.6. Internal High-Frequency Oscillator Electrica l Characteristics
VDD = 2.7 to 3.6 V; TA = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings.
Parameter Conditions Min Typ Max Units
Oscillator Frequency IFCN = 11b 24 24.5 25 MHz
Oscillator Supply Current
(from VDD)25 °C, VDD = 3.0 V,
OSCICN.7 = 1,
OCSICN.5 = 0
— 450 600 µA
Power Supply Sensitivity Constant Temperature — 0.12 — %/V
Temperature Sensitivity Constant Supply — 60 — ppm/°C
Table 6.7. Internal Low-Frequency Oscillator Electrical Characteristics
VDD = 2.7 to 3.6 V; TA = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings.
Parameter Conditions Min Typ Max Units
Oscillator Frequency OSCLD = 11b 72 80 88 kHz
Oscillator Supply Current
(from VDD)25 °C, VDD = 3.0 V,
OSCLCN.7 = 1 —5.510 µA
Power Supply Sensitivity Constant Temperatur e — 2.4 — %/V
Temperature Sensitivity Constant Supply — 30 — ppm/°C
C8051F336/7/8/9
32 Rev.1.0
Table 6.8. ADC0 Electrical Characteristics
VDD = 3.0 V, VREF = 2.40 V (REFSL=0), –40 to +85 °C unless otherwise specified.
Parameter Conditions Min Typ Max Units
DC Accuracy
Resolution 10 bits
Integral Nonlinearity — ±0.5 ±1 LSB
Differential Nonlinearity Guaranteed Mo no to nic — ±0.5 ±1 LSB
Offset Error –12 3 12 LSB
Full Scale Error –5 1 5 LSB
Offset Temperature Coefficient — 3 — ppm/°C
Dynamic performance (10 kHz sine-wave single-ended input, 1 dB below Full Scale, 200 ksps)
Signal-to-Noise Plus Distortion 53 58 — dB
Total Harmonic Distortion Up to the 5th harmonic — –75 — dB
Spurio us- Fre e Dyn a mic Rang e — 75 — dB
Conversion Rate
SAR Conversion Clock — — 3.125 MHz
Conversion Time in SAR Clocks 13 — — clocks
Track/Hold Acquisition Time 300 — — ns
Throughput Rate — — 200 ksps
Analog Inputs
ADC Input Voltage Range Single Ende d (AIN+ – GND)
Dif ferential (AIN+ – AIN–) 0
–VREF —VREF
VREF V
V
Absolute Pin Voltage with respect
to GND Single Ended or Differential 0 — VDD V
Sampling Capacitance (CSAMPLE)—5—pF
Input Multiplexer Imp edance
(RMUX)—5—kΩ
Power Specifications
Power Supply Current
(VDD supplied to ADC0) Operating Mode, 200 ksps — 500 900 µA
Power Supply Rejection — 3 — mV/V
C8051F336/7/8/9
Rev.1.0 33
Table 6.9. Temperature Sensor Electrical Characteristics
VDD = 3.0 V, –40 to +85 °C unless otherwise specified.
Parameter Conditions Min Typ Max Units
Linearity — ± 0.2 — °C
Slope — 2.25 — mV/°C
Slope Error* — 23 — µV/°C
Offset Temp = 0 °C — 785 — mV
Offset Error* Temp = 0 °C — 11.6 — mV
Note: Represents one standard deviation from the mean.
Table 6.10. Voltage Reference Electrical Characteristics
VDD = 3.0 V; –40 to +85 °C unless otherwise specified.
Parameter Conditions Min Typ Max Units
Internal Reference (REFBE = 1)
Output Voltage 25 °C ambient 2.35 2.42 2.50 V
VREF Short-Circuit Current — — 10 mA
VREF Temperature
Coefficient — 30 — ppm/°C
Load Regulation Load = 0 to 200 µA to AGND — 3 — µV/µA
VREF Turn-on Time 1 4.7 µF tantalum, 0.1 µF ceramic bypass — 7 .5 — ms
VREF Turn-on Time 2 0.1 µF ceramic bypass — 200 — µs
Power Supply Rejection — –0.6 — mV/V
External Referenc e (REF BE = 0)
Input Voltage Range 0 — VDD V
Input Current Sample Rate = 200 ksps; VREF = 3.0 V — 3 — µA
Power Specifications
Reference Bias Generator REFBE = ‘1’ or TEMPE = ‘1’ — 30 50 µA
C8051F336/7/8/9
34 Rev.1.0
Table 6.11. IDAC Electrical Characteristics
–40 to +85 °C, VDD = 3.0 V Full-scale output current set to 2 mA unless otherwise specified.
Parameter Conditions Min Typ Max Units
Static Performance
Resolution 10 bits
Integral Nonlinearity — ±0.5 ±2 LSB
Differential Nonlinearity Guaranteed Monotonic — ±0.5 ±1 LSB
Output Compliance Range 0 — VDD – 1.2 V
Offset Error — 0 — µA
Full Scale Error 2 mA Full Scale Output
Current —0±30µA
Full Scale Error Tempco — 30 — ppm/°C
VDD Power Supply
Rejection Ratio —6 —µA/V
Dynamic Performance
Output Settling Time to 1/2
LSB IDA0H:L = 0x3FF to 0x000 — 5 — µs
Startup Time — 5 — µs
Gain Variation 1 mA Full Scale Output Current — ±1 — %
0.5 mA Full Scale Output Current — ±1 — %
Power Consumption
Power Supply Current (VDD
supplied to IDAC) 2 mA Full Scale Output Current — 2100 — µA
1 mA Full Scale Output Current — 1100 — µA
0.5 mA Full Scale Output Current — 600 — µA
C8051F336/7/8/9
Rev.1.0 35
Table 6.12. Comparator Electrical Characteristics
VDD = 3.0 V, –40 to +85 °C unless otherwise noted.
Parameter Conditions Min Typ Max Units
Response Time
Mode 0, Vcm* = 1.5 V CP0+ – CP0– = 100 mV — 100 — ns
CP0+ – CP0– = –100 mV — 200 — ns
Response Time
Mode 1, Vcm* = 1.5 V CP0+ – CP0– = 100 mV — 250 — ns
CP0+ – CP0– = –100 mV — 350 — ns
Response Time
Mode 2, Vcm* = 1.5 V CP0+ – CP0– = 100 mV — 400 — ns
CP0+ – CP0– = –100 mV — 800 — ns
Response Time
Mode 3, Vcm* = 1.5 V CP0+ – CP0– = 100 mV — 1100 — ns
CP0+ – CP0– = –100 mV — 5000 — ns
Common-Mode Rejection Ratio — 1.25 5 mV/V
Positive Hysteresis 1 CP0HYP1–0 = 00 — 0 1 mV
Positive Hysteresis 2 CP0HYP1–0 = 01 1 5 10 mV
Positive Hysteresis 3 CP0HYP1–0 = 10 6 10 20 mV
Positive Hysteresis 4 CP0HYP1–0 = 11 12 20 30 mV
Negative Hysteresis 1 CP0HYN1–0 = 00 0 1 mV
Negative Hysteresis 2 CP0HYN1–0 = 01 1 5 10 mV
Negative Hysteresis 3 CP0HYN1–0 = 10 6 10 20 mV
Negative Hysteresis 4 CP0HYN1–0 = 11 12 20 30 mV
Inverting or Non-Inverting Input
Voltage Range –0.25 — VDD + 0.25 V
Input Capacitance — 4 — pF
Input Bias Current — 0.001 — nA
Input Offset Voltage –5 — +5 mV
Power Supply
Power Supply Rejection — 0.1 — mV/V
Power-up Time — 10 — µs
Supply Current at DC Mode 0 — 10 20 µA
Mode 1 — 4 10 µA
Mode 2 — 2 5 µA
Mode 3 — 0.4 2.5 µA
Note: Vcm is the common-mode voltage on CP0+ and CP0–.
C8051F336/7/8/9
36 Rev.1.0
6.3. Typical Performance Curves
Figure 6.1. Normal Mode Digital Supply Current vs. Frequency
Figure 6.2. Idle Mode Digital Supply Current vs. Frequency
0.0
2.0
4.0
6.0
8.0
10.0
12.0
0 5 10 15 20 25
SYSCLK (MHz)
IDD (mA)
VDD = 3.6V VDD = 3.3V VDD = 3.0V VDD = 2.7V
0.0
1.0
2.0
3.0
4.0
5.0
6.0
0 5 10 15 20 25
SYSCLK (MHz)
IDD (mA)
VDD = 3.6V VDD = 3.3V VDD = 3.0V VDD = 2.7V
C8051F336/7/8/9
Rev.1.0 37
7. 10-Bit ADC (ADC0, C8051F336/8 only)
The ADC0 on the C8051F336/8 is a 200 ksps, 10-bit successive-approximation-register (SAR) ADC with
integrated track-and-hold and programmable window detector. The ADC is fully configurable under soft-
ware control via Special Function Registers. The ADC0 operates in both Single-ended and Differential
modes, and may be configured to me asure variou s dif fe rent signals using the analog mu ltiplexer de scribed
in Section “7.4. ADC0 Analog Multiplexer (C8051F336/8 only)” on page 48. The voltage reference for
the ADC is selected as described in Section “8. Temperature Sensor (C8051F336/8 only)” on page 51.
The ADC0 subsystem is enabled only when the AD0EN bit in the ADC 0 Control register (ADC0CN) is set
to logic 1. The ADC0 subsystem is in low power shutdown when this bit is logic 0.
Figure 7.1. ADC0 Functional Block Diagram
ADC0CF
AD0LJST
AD0SC0
AD0SC1
AD0SC2
AD0SC3
AD0SC4
10-Bit
SAR
ADC
REF
SYSCLK
ADC0H
32
ADC0CN
AD0CM0
AD0CM1
AD0CM2
AD0WINT
AD0BUSY
AD0INT
AD0TM
AD0EN
Timer 0 Overflow
Timer 2 Overflow
Timer 1 Overflow
Start
Conversion
000 AD0BUSY (W)
VDD
ADC0LTH
AD0WINT
001
010
011
100 CNVSTR Input
Window
Compare
Logic
101 Timer 3 Overflow
ADC0LTL
ADC0GTH ADC0GTL
ADC0L
AIN+
AIN-
From
AMUX0
C8051F336/7/8/9
38 Rev.1.0
7.1. Output Code Formatting
The ADC is in Single-ended mode when the negative input is connected to GND. The ADC will be in Dif fer-
ential mode when the negative input is connected to any other option. The output code format differs
between Single-ended and Differential modes. The registers ADC0H and ADC0L contain the high and low
bytes of the output conversion code fr om the ADC at the com pletion of each conver sion. Dat a can be righ t-
justified or left- justified, depending on the setting of the AD0LJST. When in Single-ended Mode, conversion
codes are represented as 10-bit unsigned integers. Inputs are measured from ‘0’ to VREF x 1023/1024.
Example codes are shown below for both right-justified and left-justified data. Unused bits in the ADC0H
and ADC0L registers are set to ‘0’.
When in Differential Mode, conversion codes are represented as 10-bit signed 2’s complement numbers.
Inputs are meas ured fro m –VREF to VREF x 511/512. Example codes are shown below for both right-jus-
tified and left-justified dat a. For right-justified data, the u nused MSBs of ADC0H are a sig n-exte nsion of the
data word. For left-justified data, the unused LSBs in the ADC0L register are set to ‘0’.
7.2. Modes of Operation
ADC0 has a maximum conversion speed of 200 ksps. The ADC0 conversion clock is a divided version of
the system clock, determined by the AD0SC bits in the ADC0CF register.
7.2.1. Starting a Conversion
A conversion can be initiated in one of six ways, dependin g on the programmed st ates of the ADC0 Start of
Conversion Mode bits (AD0CM2–0) in register ADC0CN. Conversions may be initiated by one of the fol-
lowing:
1. Writing a ‘1’ to the AD0BUSY bit of register ADC0CN
2. A Timer 0 overflow (i.e., timed continuous conversions)
3. A Timer 2 overflow
4. A Timer 1 overflow
5. A rising edge on the CNVSTR input signal (pin P0.6)
6. A Timer 3 overflow
Writing a ‘1’ to AD0BUSY provides software control of ADC0 whereby conversions are performed "on-
demand". During conversion, the AD0BUSY bit is set to logic 1 and reset to logic 0 when the conversion is
Input Voltage Right-Justified ADC0H:ADC0L
(AD0LJST = 0) Left-Justified ADC 0H: A D C0L
(AD0LJST = 1)
VREF x 1023/1024 0x03FF 0xFFC0
VREF x 512/1024 0x0200 0x8000
VREF x 256/1024 0x0100 0x4000
0 0x0000 0x0000
Input Voltage Right-Justified ADC0H:ADC0L
(AD0LJST = 0) Left-Justified ADC0H:ADC0L
(AD0LJST = 1)
VREF x 511/512 0x01FF 0x7FC0
VREF x 256/512 0x0100 0x4000
0 0x0000 0x0000
–VREF x 256/512 0xFF00 0xC000
–VREF 0xFE00 0x8000
C8051F336/7/8/9
Rev.1.0 39
complete. The falling edge of AD0BUSY triggers an interrupt (when enabled) and sets the ADC0 interrupt
flag (AD0INT). Note: When polling for ADC conversion completions, the ADC0 interrupt flag (AD0INT)
should be used. Converted data is available in the ADC0 data registe rs, ADC0H:ADC0L, when bi t AD0INT
is logic 1. Note that when Timer 2 or Timer 3 overflows are used as the conversion source, Low Byte over-
flows are used if Timer 2/3 is in 8-bit mode; High byte overflows are used if Timer 2/3 is in 16-bit mode.
See Section “24. Timers” on page 180 for timer configuration.
Import ant Note Ab out Using CNVSTR: The CNVSTR input pin also functions as Port pin P0.6. When the
CNVSTR input is used as the ADC0 conversion source, Port pin P0.6 should be skipped by the Digital
Crossbar. To configure the Crossbar to skip P0.6, set to ‘1’ Bit6 in register P0SKIP. See Section “20. Port
Input/Output” on page 119 for details on Port I/O configuration.
7.2.2. Tracking Modes
Each ADC0 conversion must be preceded by a minimum tracking time in order for the converted result to
be accurate. Refer to Section “6. Electrical Characteristics” on page 27 for minimum tracking time
specifications. The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default
state, the ADC0 input is continuously tracked, except when a conversion is in progress. When the AD0TM
bit is logic 1, ADC0 operates in low-power track-an d-hold mode. In this mode, each conversion is preceded
by a tracking period of 3 SAR clocks (after the start-of-conversion signal). When the CNVSTR signal is
used to initiate conversions in low-power tracking mode, ADC0 tracks only w hen CNVSTR is low; conver-
sion begins on the rising edge of CNVSTR (see Figure 7.2). Tracking can also be disabled (shutdown)
when the device is in low power standby or sleep modes. Low-power track-and-hold mode is also useful
when AMUX settings are frequently changed, due to the settling time requirements described in Section
“7.2.3. Settling Time Requirements” on page 40.
Figure 7.2. 10-Bit ADC Track and Conversion Example Timing
Write '1' to AD0BUSY,
Timer 0, Timer 2,
Timer 1, Timer 3 Overflow
(AD0CM[2:0]=000, 001,010
011, 101)
AD0TM=1 Track Convert Low Power Mode
AD0TM=0 Track or
Convert Convert Track
Low Power
or Convert
SAR
Clocks
SAR
Clocks
B. ADC0 Timing for Internal Trigger Source
123456789
CNVSTR
(AD0CM[2:0]=100)
AD0TM=1
A. ADC0 Timing for External Trigger Source
SAR Cloc ks
Track or Convert Convert TrackAD0TM=0
Track Convert Low Power
Mode
Low Power
or Convert
10 11 12 13 14
123456789
10 11 12 13 14
123456789
10 11 12 13 14 15 16 17
C8051F336/7/8/9
40 Rev.1.0
7.2.3. Settling Ti me Requirements
A minimum tracking time is required before each conversion to ensure that an accurate conversion is per-
formed. This tracking time is determined by any series impedance, including the AMUX0 resistance, the
the ADC0 sampling capacitance, and the accuracy required for the conversion. Note that in low-power
tracking mod e, three SAR clocks are used for trackin g at the start of every conversion. For many applica-
tions, these three SAR clocks will meet the minimum tracking time requirements.
Figure 7.3 shows the equivalent ADC0 input circuits for both Differential and Single-ended modes. Notice
that the equivalent time constant for both input circuits is the same. The required ADC0 settling time for a
given settling accuracy (SA) may be approximated by Equation 7.1. When measuring the Temperature
Sensor output or VDD with respect to GND, RTOTAL reduces to RMUX. See Section “6. Electrical Charac-
teristics” on page 27 for ADC0 minimum settling time requirements as well as the mux impedance and
sampling capacitor values.
Equation 7.1. ADC0 Settling Time Requirements
Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t is the required settling time in seconds
RTOTAL is the sum of the AMUX0 resistance and any external source resistance.
n is the ADC resolution in bits (10).
Figure 7.3. ADC0 Equivalent Input Circuits
t2n
SA
-------
RTOTALCSAMPLE
×ln=
RMUX
RCInput= RMUX * CSAMPLE
RMUX
CSAMPLE
CSAMPLE
MUX Select
MUX Select
Differential Mode
Px.x
Px.x
RMUX
CSAMPLE
RCInput= RMUX * CSAMPLE
MUX Select
Single-Ended Mode
Px.x
C8051F336/7/8/9
Rev.1.0 41
SFR Address = 0xBC
SFR Definition 7.1. ADC0CF: ADC0 Configuration
Bit76543210
Name AD0SC[4:0] AD0LJST
Type R/W R/W R R
Reset 11111000
Bit Name Function
7:3 AD0SC[4:0] ADC0 SAR Conversion Clock Period Bits.
SAR Conversion clock is derived from system clock by the fol-
lowing equation, where AD0SC re fers to the 5-bit value held in
bits AD0SC4–0. SAR Conversion clock requirements are given
in the ADC specification table.
2AD0LJST
ADC0 Left Justify Select.
0: Data in ADC0H:ADC0L registers are right-justified.
1: Data in ADC0H:ADC0L registers are left-justified.
1:0 UNUSED Unused. Read = 00b; Write = don’t care.
AD0SC SYSCLK
CLKSAR
-----------------------1–=
C8051F336/7/8/9
42 Rev.1.0
SFR Address = 0xBE
SFR Address = 0xBD
SFR Definition 7.2. ADC0H: ADC0 Data Word MSB
Bit76543210
Name ADC0H[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 ADC0H[7:0] ADC0 Data Word High-Order Bits.
For AD0LJST = 0: Bits 7–2 are the sign extension of Bit1. Bits 1–0 are the upper 2
bits of the 10-bit ADC0 Data Word.
For AD0LJST = 1: Bits 7–0 are the most-significant bits of the 10-bit ADC0 Data
Word.
SFR Definition 7.3. ADC0L: ADC0 Data Word LSB
Bit76543210
Name ADC0L[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 ADC0L[7:0] ADC0 Data Word Low-Order Bits.
For AD0LJST = 0: Bits 7–0 are the lower 8 bits of the 10-bit Data Word.
For AD0LJST = 1: Bits 7–6 are the lower 2 bits of the 10-bit Data Word. Bits 5–0 will
always read ‘0’.
C8051F336/7/8/9
Rev.1.0 43
SFR Address = 0xE8; Bit-Addressable
SFR Definition 7.4. ADC0CN: ADC0 Control
Bit76543210
Name AD0EN AD0TM AD0INT AD0BUSY AD0WINT AD0CM[2:0]
Type R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7AD0EN
ADC0 Enable Bit.
0: ADC0 Disabled. ADC0 is in low-power shutdown.
1: ADC0 Enabled. ADC0 is active and ready for data conversions.
6AD0TM
ADC0 Track Mode Bit.
0: Normal Track Mode: When ADC0 is enable d, tr ack ing is cont inu o us un less a c on-
version is in progress. Conversion begins immediately on start-of-conversion event,
as defined by AD0CM[2:0].
1: Low-power T rack Mode: For AD0CM[2:0] = 100, ADC is tracking when CNVSTR is
low, and conversion begins immediately on rising edge of CNVSTR.
For all other values of AD0CM[2:0], tracking is initiated on start-of-conversion event,
and lasts 3 SAR Clock cycles. The conversion immediately follows this tracking
phase.
5AD0INT
ADC0 Conversion Complete Interrupt Flag.
0: ADC0 has not completed a da ta conversion since AD0INT was last cleared.
1: ADC0 has completed a data conversion.
4AD0BUSY
ADC0 Busy Bit. Read:
0: ADC0 conversion is not
in progress.
1: ADC0 conversion is in
progress.
Write:
0: No Effect.
1: Initiates ADC0 Conver-
sion if AD0CM[2:0] =
000b
3 AD0WINT ADC0 Window Compare Interrupt Fla g.
0: ADC0 Window Comparison Data match has not occurred since this flag was last
cleared.
1: ADC0 Window Comparison Data ma tch has occurred.
2:0 AD0CM[2:0] ADC0 Start of Conversion Mode Select.
000: ADC0 start-of-conversion source is write of ‘1’ to AD0BUSY.
001: ADC0 start-of-conversion source is overflow of Timer 0.
010: ADC0 start-of-conversion source is overflow of Timer 2.
011: ADC0 start-of-conversion source is overflow of Timer 1.
100: ADC0 start-of-conversion source is rising edge of external CNVSTR.
101: ADC0 start-of-conversion source is overflow of Timer 3.
11x: Reserved.
C8051F336/7/8/9
44 Rev.1.0
7.3. Programmable Window Detector
The ADC Programmable Window Detector continuously compares the ADC0 output registers to user-pro-
grammed limit s, and notifies the system whe n a desired co ndition is detected. This is especially ef fective i n
an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system
response times. The window detector interrupt flag (AD0WINT in register ADC0CN) can also be used in
polled mode. The ADC0 Greater-Than (ADC0GTH, ADC0GTL) and Less-Than (ADC0LTH, ADC0LTL)
registers hold the comp arison values. The window detector flag can be programmed to in dicate when mea-
sured data is inside or outside of the user-programmed limits, depending on the contents of the ADC0
Less-Than and ADC0 Greater-Than registers.
SFR Address = 0xC4
SFR Address = 0xC3
SFR Definition 7.5. ADC0GTH: ADC0 Greater-Than Data High Byte
Bit76543210
Name ADC0GTH[7:0]
Type R/W
Reset 11111111
Bit Name Function
7:0 ADC0GTH[7:0] ADC 0 Greater-Than Data Word High-Order Bits.
SFR Definition 7.6. ADC0GTL: ADC0 Greater-Than Data Low Byte
Bit76543210
Name ADC0GTL[7:0]
Type R/W
Reset 11111111
Bit Name Function
7:0 ADC0GTL[7:0] ADC0 Greater-Than Data Word Low-Order Bits.
C8051F336/7/8/9
Rev.1.0 45
SFR Address = 0xC6
SFR Address = 0xC5
SFR Definition 7.7. ADC0LTH: ADC0 Less-Than Data High Byte
Bit76543210
Name ADC0LTH[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 ADC0LTH[7:0] ADC0 Less-Than Data Word High-Order Bits.
SFR Definition 7.8. ADC0LTL: ADC0 Less-Than Data Low Byte
Bit76543210
Name ADC0LTL[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 ADC0LTL[7:0] ADC0 Less-Than Data Word Low-Order Bits.
C8051F336/7/8/9
46 Rev.1.0
7.3.1. Window Detector In Single-Ended Mode
Figure 7.4 shows two example window comparisons for right-justified, single-ended data, with
ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). In single-ended mode,
the input voltage can range from ‘0’ to VREF x (1023/1024) with respect to GND, and is represented by a
10-bit unsigned integer value. In the left example, an AD0WINT interrupt will be generated if the ADC0
conversion word (ADC0H:ADC0L) is within the range defined by ADC0GTH:ADC0GTL and
ADC0LTH:ADC0LTL (if 0x0040 < ADC0H:ADC0L < 0x0080). In the right example, and AD0WINT interrupt
will be generated if the ADC0 conversion word is outside of the range defined by the ADC0GT and
ADC0LT registers (if ADC0H:ADC0L < 0x0040 or ADC0H:ADC0L > 0x0080). Figure 7.5 shows an exam-
ple using left-justified data with the same comparison values.
Figure 7.4. ADC Window Compare Example: Right-Justified Single-Ended Data
Figure 7.5. ADC Window Compare Example: Left-Justified Single-Ended Data
0x03FF
0x0081
0x0080
0x007F
0x0041
0x0040
0x003F
0x0000
0
Input Voltage
(Px.x - GND)
VREF x (1023/
1024)
VREF x (128/1024)
VREF x (64/1024)
AD0WINT=1
AD0WINT
not affected
AD0WINT
not affected
ADC0LTH:ADC0LTL
ADC0GTH:ADC0GTL
0x03FF
0x0081
0x0080
0x007F
0x0041
0x0040
0x003F
0x0000
0
Input Voltage
(Px.x - GND)
VREF x (1023/
1024)
VREF x (128/1024)
VREF x (64/1024)
AD0WINT
not affected
AD0WINT=1
AD0WINT=1
ADC0H:ADC0L ADC0H:ADC0L
ADC0GTH:ADC0GTL
ADC0LTH:ADC0LTL
0xFFC0
0x2040
0x2000
0x1FC0
0x1040
0x1000
0x0FC0
0x0000
0
Input Voltage
(Px.x - G ND)
VREF x (1023/
1024)
VREF x (128/1024)
VREF x (64/1024)
AD0WINT=1
AD0WINT
not affected
AD0WINT
not affected
ADC0LTH:ADC0LTL
ADC0GTH:ADC0GTL
0xFFC0
0x2040
0x2000
0x1FC0
0x1040
0x1000
0x0FC0
0x0000
0
Input Voltage
(Px.x - GND)
VREF x (1023/
1024)
VREF x (128 /1024)
VREF x (64/1024)
AD0WINT
not affected
AD0WINT=1
AD0WINT=1
ADC0H:ADC0L ADC0H:ADC0L
ADC0LTH:ADC0LTL
ADC0GTH:ADC0GTL
C8051F336/7/8/9
Rev.1.0 47
7.3.2. Window Detector In Differential Mode
Figure 7.6 shows two example window comparisons for right-justified, differential data, with
ADC0LTH:ADC0LTL = 0x0040 (+64d) and ADC0GTH:ADC0GT H = 0xFFFF (–1d). In dif fe rential mode, the
measurable voltage between the input pins is between –VREF and VREF x (511/512). Output codes are
represented as 10-bit 2s complement signed integers. In the left example, an AD0WINT interrupt will be
generated if the ADC0 conversion word (ADC0H:ADC0L) is within the range defined by
ADC0GTH:ADC0GTL and ADC0LTH:ADC0LTL (if 0xFFFF (–1d) < ADC0H:ADC0L < 0x0040 (64d)). In the
right example, an AD0WINT interrupt will be generated if the ADC0 conversion word is outside of the range
defined by the ADC0GT and ADC0LT registers (if ADC0H:ADC0L < 0xFFFF (–1d) or
ADC0H:ADC0L > 0x0040 (+64d)). Figure 7.7 shows an example using left-justified data with the same
comparison values.
Figure 7.6. ADC Window Compare Example: Right-Justified Differential Data
Figure 7.7. ADC Window Compare Example: Left-Justified Differential Data
0x01FF
0x0041
0x0040
0x003F
0x0000
0xFFFF
0xFFFE
0x0200
-VREF
Input Voltage
(Px.x - Px.x)
VREF x (511/512)
VREF x (64/512)
VREF x (-1/512)
0x01FF
0x0041
0x0040
0x003F
0x0000
0xFFFF
0xFFFE
0x0200
-VREF
Input Voltage
(Px.x - Px.x)
VREF x (511/512)
VREF x (64/512)
VREF x (-1/512)
AD0WINT=1
AD0WINT
not affected
AD0WINT
not affected
ADC0LTH:ADC0LTL
ADC0GTH:ADC0GTL
AD0WINT
not affected
AD0WINT=1
AD0WINT=1
ADC0H:ADC0LADC0H:ADC0L
ADC0GTH:ADC0GTL
ADC0LTH:ADC0LTL
0x7FC0
0x1040
0x1000
0x0FC0
0x0000
0xFFC0
0xFF80
0x8000
-VREF
Input Voltage
(Px.x - Px.y)
VREF x (511/512)
VREF x (64/512)
VREF x (-1/512)
0x7FC0
0x1040
0x1000
0x0FC0
0x0000
0xFFC0
0xFF80
0x8000
-VREF
Input Voltage
(Px.x - Px.x )
VREF x (511/512)
VREF x (64/512)
VREF x (-1/5 12)
AD0WINT=1
AD0WINT
not affected
AD0WINT
not affected
ADC0LTH:ADC0LTL
ADC0GTH:ADC0GTL
AD0WINT
not affected
ADC0GTH:ADC0GTL
AD0WINT=1
AD0WINT=1
ADC0H:ADC0LADC0H:ADC0L
ADC0LTH:ADC0LTL
C8051F336/7/8/9
48 Rev.1.0
C8051F336/7/8/9
Rev.1.0 48
7.4. ADC0 Analog Multiplexer (C8051F336/8 only)
ADC0 on the C8051F336/8 has two analog multiplexers, referred to collectively as AMUX0.
AMUX0 selects the positive and negative inputs to the ADC. Any of the following may be selected as the
positive input: Port I/O pins, the on-chip temperature sensor, or the positive power supply (VDD). Any of the
following may be selected as the negative input: Port I/O pins, VREF, or GND. When GND is selected as
the negative input, ADC0 operates in Single-ended Mode; all other times, ADC0 operates in Differ-
ential Mode. The ADC0 input channels are selected in the AMX0P and AMX0N registers as described in
SFR Definition 7.9 and SFR Definition 7.10.
Figure 7.8. ADC0 Multiplexer Block Diagram
Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be config-
ured as analog inputs, and should be skipped by the Digital Crossbar. To configure a Port pin for analog
input, set to ‘0’ the corresponding bit in register PnMDIN. To force the Crossbar to skip a Port pin, set to ‘1’
the correspondin g bit in register Pn SKIP. See Section “20. Port Input/Output” on p age 1 19 for more Port
I/O configuration details.
ADC0
AMUX
Temp
Sensor
AMUX
VDD
GND
P0.0
P2.3*
AMX0P
AMX0P4
AMX0P3
AMX0P2
AMX0P1
AMX0P0
AMX0N
AMX0N4
AMX0N3
AMX0N2
AMX0N1
AMX0N0
AIN+
AIN-
VREF
P0.0
P2.3*
*P2.0-P2.3 Only available as
inputs on QFN24 P ackaging
C8051F336/7/8/9
49 Rev.1.0
SFR Address = 0xBB
SFR Definition 7.9. AMX0P: AMUX0 Positive Channel Select
Bit76543210
Name AMX0P[4:0]
Type RRR R/W
Reset 00011111
Bit Name Function
7:5 UNUSED Unused. Read = 000b; Write = Don’t Care.
4:0 AMX0P[4:0] AMUX0 Positive Input Selection.
00000: P0.0
00001: P0.1
00010: P0.2
00011: P0.3
00100: P0.4
00101: P0.5
00110: P0.6
00111: P0.7
01000: P1.0
01001: P1.1
01010: P1.2
01011: P1.3
01100: P1.4
01101: P1.5
01110: P1.6
01111: P1.7
10000: Temp Sensor
10001: VDD
10010: P2.0 (C8051F338/9 Only)
10011: P2.1 (C8051F338/9 Only)
10100: P2.2 (C8051F338/9 Only)
10101: P2.3 (C8051F338/9 Only)
10110 – 11111: no input selected
C8051F336/7/8/9
Rev.1.0 50
SFR Address = 0xBA
SFR Definition 7.10. AMX0N: AMUX0 Negative Channel Select
Bit76543210
Name AMX0N[4:0]
Type RRR R/W
Reset 00011111
Bit Name Function
7:5 UNUSED Unused. Read = 000b; Write = Don’t Care.
4:0 AMX0N[4:0] AMUX0 Negative Input Selection.
00000: P0.0
00001: P0.1
00010: P0.2
00011: P0.3
00100: P0.4
00101: P0.5
00110: P0.6
00111: P0.7
01000: P1.0
01001: P1.1
01010: P1.2
01011: P1.3
01100: P1.4
01101: P1.5
01110: P1.6
01111: P1.7
10000: VREF
10001: GND (ADC in Single-Ended Mode)
10010: P2.0 (C8051F338/9 Only)
10011: P2.1 (C8051F338/9 Only)
10100: P2.2 (C8051F338/9 Only)
10101: P2.3 (C8051F338/9 Only)
10110 – 11111: no input selected
C8051F336/7/8/9
Rev.1.0 51
8. Temperature Sensor (C8051F336/8 only)
An on-chip temperature sensor is included on the C8051F336/8 which can be directly accessed via the
ADC multiplexer in single-ended configuration. To use the ADC to measure the temperature sensor, the
positive ADC mux channel should be configured to connect to the temperature sensor and the negative
ADC mux channel should be configured to connect to GND. The temperature sensor transfer function is
shown in Figure 8.1. The output voltage (VTEMP) is the positive ADC input when the ADC multiplexer is set
correctly. The TEMPE bit in register REF0CN enables/disables the temperature sensor, as described in
SFR Definition 10.1. While disabled, the temperature sensor defaults to a high impedance state and any
ADC measurements performed on the sensor will result in meaningless data. Refer to Section
“6. Electrical Characteristics” on page 27 for the slope and offset parameters of the temperature sen-
sor.
Figure 8.1. Temperature Sensor Transfer Function
Temperature
Voltage
VTEMP = (Slope x TempC) + Offset
Offset (V at 0 Celsius)
Slope (V / deg C)
TempC = (VTEMP - Offset) / Slope
C8051F336/7/8/9
Rev.1.0 52
9. 10-Bit Current Mode DAC (IDA0, C8051F336/8 only)
The C8051F336/8 device includes a 10-bit current-mode Digital-to-Analog Converter (IDAC). The maxi-
mum current output of the IDAC can be adjusted for three different current settings; 0.5 mA, 1 mA, and
2 mA. The IDAC is en abled or dis able d with the I DA0EN bit in the IDA0 Control Register (see SFR Defini-
tion 9.1). When IDA0EN is set to 0, the IDAC port pin (P0.1) behaves as a normal GPIO pin. When
IDA0EN is set to 1, the digital output drivers and weak pullup for the IDAC pin are automatically disabled,
and the pin is connected to the IDAC output. An internal bandgap bias generator is used to generate a ref-
erence current for the IDAC whenever it is enabled. When using the IDAC, bit 1 in the P0SKIP register
should be set to 1, to force the Crossbar to skip the IDAC pin.
9.1. IDA0 Output Scheduling
IDA0 features a flexible output update mechanism which allows for seamless full-scale changes and sup-
ports jitter-free updates for waveform generation. Three update modes are provided, allowing IDAC output
updates on a write to IDA0H, on a Timer overflow, or on an external pin edge.
9.1.1. Update Output On-Demand
In its default mode (IDA0CN.[6:4] = 111) the IDA0 output is updated “on-demand” on a write to the high-
byte of the IDA0 data register (IDA0H). It is important to note that writes to IDA0L are held in this mode,
and have no effect on the IDA0 output until a write to IDA0H takes place. If writing a full 10-bit word to the
IDAC data registers, the 10-bit data word is written to the low byte (IDA0L) and high byte (IDA0H) da t a reg-
isters. Data is latched into IDA0 after a write to the IDA0H register, so the write sequence should be
IDA0L followed by IDA0H if the full 10-bit resolution is required. The IDAC can be used in 8-bit mode by
initializing IDA0L to the desired value (typically 0x00), and writing data to only IDA0H (see Section 9.2 for
information on the fo rmat of the 10-bit IDAC data word within the 16-bit SFR space).
Figure 9.1. IDA0 Functional Block Diagram
IDA0
10 IDA0
IDA0CN
IDA0EN
IDA0CM2
IDA0CM1
IDA0CM0
IDA0OMD1
IDA0OMD0
IDA0HIDA0L
Latch
8
2
IDA0H
Timer 0
Timer 1
Timer 2
Timer 3
CNVSTR
C8051F336/7/8/9
53 Rev.1.0
9.1.2. Update Output Based on Timer Overflow
Similar to the ADC operation, in which an ADC conversion can be initiated by a timer overflow inde-
pendently of the processor, the IDAC outputs can use a Timer overflow to schedule an output update
event. This feature is useful in systems wher e th e ID AC is use d to gene r at e a wa ve fo rm of a def i ne d sam -
pling rate by eliminating the effects of variable interrupt latency and instruction execution on the timing of
the IDAC output. When the IDA0CM bits (IDA0CN.[6:4]) are set to 000, 001, 010 or 011, writes to both
IDAC data registers (IDA0L and IDA0H) are held until an associated Timer overflow event (Timer 0,
Timer 1, Timer 2 or Timer 3, respectively) occurs, at which time the IDA0H:IDA0L contents are copied to
the IDAC input latches, allowing the IDAC output to change to the new value.
9.1.3. Update Output Based on CNVSTR Edge
The IDAC output can also be configured to update on a rising edge, falling edge, or both edges of the
external CNVSTR signal. When the IDA0CM bits (IDA0CN.[6:4]) are set to 100, 101, or 110, writes to both
IDAC data registers (IDA0L and IDA0H) are held until an edge occurs on the CN VSTR input p in. The par-
ticular settin g of the IDA0 CM bits determines whether IDAC outputs are updated on rising, falling, or both
edges of CNVSTR. When a corresponding e dge occurs, the IDA0H:IDA0L contents are copied to the IDAC
input latches, allowing the IDAC output to change to the new value.
9.2. IDAC Output Mapping
The IDAC data registers (IDA0H and IDA0L) are left-justified, meaning that the eight MSBs of the IDAC
output word are mapped to bits 7–0 of the IDA0H register, and the two LSBs of the IDAC output word are
mapped to bits 7 and 6 of the IDA0L register. The data word mapping for the IDAC is shown in Figure 9.2.
Figure 9.2. IDA0 Data Word Mapping
The full-scale output current of the IDAC is selected using the IDA0OMD bits (IDA0CN[1:0]). By default,
the IDAC is set to a full-scale output curr ent of 2 mA. The IDA0OMD b its can also be configured to provide
full-scale output currents of 1 mA or 0.5 mA, as shown in SFR Definition 9.1.
IDA0H IDA0L
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Input Data Word
(IDA09–IDA00) Output Current
IDA0OMD[1:0] = 1x Output Current
IDA0OMD[1:0] = 01 Output Current
IDA0OMD[1:0] = 00
0x000 0 mA 0 mA 0 mA
0x001 1/1024 x 2 mA 1/1024 x 1 mA 1/1024 x 0.5 mA
0x200 512/1024 x 2 mA 512/1024 x 1 mA 512/1024 x 0.5 mA
0x3FF 1023/1024 x 2 mA 1023/1024 x 1 mA 1023/1024 x 0.5 mA
C8051F336/7/8/9
Rev.1.0 54
SFR Address = 0xB9
SFR Definition 9.1. IDA0CN: IDA0 Control
Bit76543210
Name IDA0EN IDA0CM[2:0] IDA0OMD[1:0]
Type R/W R/W R R R/W
Reset 01110010
Bit Name Function
7IDA0EN
IDA0 Enable.
0: IDA0 Disabled.
1: IDA0 Enabled.
6:4 IDA0CM[2:0] IDA0 Update Source Select bits.
000: DAC output updates on Timer 0 overflow.
001: DAC output updates on Timer 1 overflow.
010: DAC output updates on Timer 2 overflow.
011: DAC output updates on Timer 3 overflow.
100: DAC output updates on rising edge of CNVSTR.
101: DAC output updates on falling edge of CNVSTR.
110: DAC output updates on any edge of CNVSTR.
111: DAC output updates on write to IDA0H.
3:2 Unused Unused. Read = 00b. Write = Don’t care.
1:0 IDA0OMD[1:0] IDA0 Output Mode Select bits.
00: 0.5 mA full-scale out pu t cu rr ent.
01: 1.0 mA full-scale out pu t cu rr ent.
1x: 2.0 mA full-scale output current.
C8051F336/7/8/9
55 Rev.1.0
SFR Address = 0x97
SFR Address = 0x96
SFR Definition 9.2. IDA0H: IDA0 Data Word MSB
Bit76543210
Name IDA0[9:2]
Type R/W
Reset 00000000
Bit Name Function
7:0 IDA0[9:2] IDA0 Data Word High-Order Bits.
Upper 8 bits of the 10-bit IDA0 Data Word.
SFR Definition 9.3. IDA0L: IDA0 Data Word LSB
Bit76543210
Name IDA0[1:0]
Type R/W RRRRRR
Reset 00000000
Bit Name Function
7:6 IDA0[1:0] IDA0 Data Word Low-Order Bits.
Lower 2 bits of the 10-bit IDA0 Data Word.
5:0 Unused Unused. Read = 000000b. Write = Don’t care.
C8051F336/7/8/9
Rev.1.0 56
10. Voltage Reference (C8051F336/8 only)
The Voltage reference multiplexer for th e ADC is configurable to use an externally connected voltage refe r-
ence, the on-chip reference voltage generator routed to the VREF pin, or the VDD power supply voltage
(see Figure 10.1). The REFSL bit in the Reference Control registe r (REF0CN, SFR Definition 10.1 ) select s
the reference source for the ADC. For an extern al source or th e on-chip r eference, REFSL sho uld be set to
‘0’ to select the VREF pin. To use VDD as the reference source, REFSL should be set to ‘1’.
The BIASE bit enables the internal voltage bias ge nerator, which is used by many of the analog peripherals
on the device. Th is bias is automatically enabled when any peripheral which requires it is enabled, and it
does not need to be enabled manually. The bias generator may be en abled manually by writing a ‘1’ to the
BIASE bit in register REF0CN. The electrical specifications for the voltage reference circuit are given in
Section “6. Electrical Characteristics” on page 27.
The on-chip voltage reference circuit consists of a 1.2 V, temperature stable bandgap voltage reference
generator and a gain-of-two output buffer amplifier. The on-chip voltage reference can be driven on the
VREF pin by setting the REFBE bit in register REF0CN to a ‘1’. The maximum load seen by the VREF pin
must be less than 200 µA to GND. Bypass capacitors of 0.1 µF and 4.7 µF are recommended from the
VREF pin to GND. If the on-chip reference is not used, the REFBE bit should be cleared to ‘0’.
Important Note about the VREF Pin: When using either an external voltage reference or the on-chip ref-
erence circuitry, the VREF pin should be configured as an analog pin and skipped by the Digital Crossbar.
Refer to Section “20. Port Input/Output” on p age 119 for the location of the VREF pin, as well as details
of how to configure the pin in analog mod e and to be skipped by the crossbar.
Figure 10.1. Voltage Reference Functional Block Diagram
VREF
(to ADC)
To Analog Mux
VDD
VREF
R1
VDD External
Voltage
Reference
Circuit
GND
Tem p Sensor
EN
Bia s Ge n e ra to r To ADC, IDAC,
Inte rn a l Os cilla to rs
EN
IOSCE
N
0
1
REF0CN
REFSL
TEMPE
BIASE
REFBE
REFBE
In ter na l
Reference
EN
Recom m ended B ypass
Capacitors
+
4.7μF0.1μF
C8051F336/7/8/9
57 Rev.1.0
SFR Address = 0xD1
SFR Definition 10.1. REF0CN: Reference Control
Bit76543210
Name REFSL TEMPE BIASE REFBE
Type RRRRR/WR/WR/WR/W
Reset 00000000
Bit Name Function
7:4 UNUSED Unused. Read = 0000b ; Write = don’t care.
3 REFSL Voltage Reference Select.
This bit selects the ADCs voltage reference.
0: VREF pin used as voltage reference.
1: VDD used as voltage reference.
2 TEMPE Temperature Sensor Enable Bit.
0: Internal Tem p er at ur e Se nso r off.
1: Internal Tem p er at ur e Se nso r on.
1 BIASE Internal Analog Bias Generator Enable Bit.
0: Internal Bias Generator off.
1: Internal Bias Generator on.
0 REFBE On-chip Reference Buffer Enable Bit.
0: On-chip Reference Buffer off.
1: On-chip Reference Buffer on. Internal voltage reference driven on the VREF pin.
C8051F336/7/8/9
Rev.1.0 58
11. Comparator0
C8051F336/7/8/9 devices include an on-chip programmable voltage comparator, Comparator0, shown in
Figure 11.1.
The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0), or an asyn-
chronous “raw” output (CP0A). The asynchronous CP0A signal is available even when the system clock is
not active. This allows the Comparator to operate and generate an output with the device in STOP mode.
When assigned to a Port pin, the Comparator output may be configured as open drain or push-pull (see
Section “20.4. Port I/O Initialization” on page 126). Comparator0 may als o be used as a reset sour ce (see
Section “17.5. Comparator0 Reset” on page 104).
The Comparator0 inputs are selected by the comparator input multiplexer, as detailed in Section
“11.1. Comparator Multiplexer” on page 63.
Figure 11.1. Comparator0 Functional Block Diagram
The Comparator output can be polled in software, used as an interrupt source, and/or routed to a Port pin.
When routed to a Port pin, the Comparator output is available asynchronous or synchronous to the system
clock; the asynchronous output is available even in STOP mode (with no system clock active). When dis-
abled, the Compar ator output ( if assigne d to a Port I/O pin via the Cr ossbar ) defaults to the logic low state,
and the power supply to the comparator is turned off. See Section “20.3. Priority Crossbar Decoder” on
page 124 for details on configuring Comparator outputs via the digital Crossbar. Comparator inputs can be
VDD
Reset
Decision
Tree
+
- Crossbar
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
(SYNCHRONIZER)
GND
CP0 +
CP0 -
CPT0MD
CP0RIE
CP0FIE
CP0MD1
CP0MD0
CP0
CP0A
CP0
Interrupt
0
1
0
1
CP0RIF
CP0FIF
0
1
CP0EN 0
1
EA
Comparator
Input Mux
CPT0CN
CP0EN
CP0OUT
CP0RIF
CP0FIF
CP0HYP1
CP0HYP0
CP0HYN1
CP0HYN0
C8051F336/7/8/9
59 Rev.1.0
externally driven from –0.25 V to (VDD) + 0.25 V without damage or upset. The comple te Comp ar ator elec-
trical specifications are given in Section “6. Electrical Characteristics” on page 27.
The Comparator re sponse time may b e configured in software vi a the CPT0MD regis ter (see SFR Defini -
tion 11.2). Selecting a longer response time reduces the Comparator supply current.
Figure 11.2. Comparator Hysteresis Plot
The Comparator hysteresis is software-programmable via its Comparator Control register CPT0CN. The
user can program bo th the amount of hysteresis volt age (referred to the input volt a ge) and the posi tive and
negative-going symmetry of this hysteresis around the threshold voltage.
The Comparator hysteresis is programmed using Bits3–0 in the Comparator Control Register CPT0CN
(shown in SFR Definition 11.1). The amount of negative hysteresis volt ag e is determined by the settings of
the CP0HYN b its. As shown in Figure 11.2, settings of 20, 10 or 5 mV of negative hysteres is can be pro-
grammed, or negative hysteresis can be disabled. In a similar way, the amount of positive hysteresis is
determined by the setting the CP0HYP bits.
Comparator interrupts can be generated on both rising-e dge and falling-edge output transitions. (For Inter-
rupt enable and priority control, see Section “15.1. MCU Interrupt Sources and Vectors” on page 83). The
CP0FIF flag is set to logic 1 upon a Comparator falling-edge occurrence, and the CP0RIF flag is set to
logic 1 upon the Comparator rising-edge occurrence. Once set, these bits remain set until cleared by soft-
ware. The Comparator rising-edge interrupt mask is enabled by setting CP0RIE to a logic 1. The Compar-
ator0 falling-edge interrupt mask is enabled by setting CP0FIE to a logic 1.
Positive Hysteresis Voltage
(Programmed with CP0HYP Bits)
Negative Hysteresis Voltage
(Programmed by CP0HYN Bits)
VIN-
VIN+
INPUTS
CIRCUIT CONFIGU RATI ON
+
_
CP0+
CP0- CP0
VIN+
VIN- OUT
VOH
Positive Hysteresis
Disabled Maximum
Positive Hysteresis
Negative Hysteresis
Disabled Maximum
Negative Hysteresis
OUTPUT
VOL
C8051F336/7/8/9
Rev.1.0 60
The output state of the Comparator can be obtained at any time by reading the CP0OUT bit. The Compar-
ator is enabled by setting the CP0EN bit to logic 1, and is disabled by clearing this bit to logic 0.
Note that false rising edges and falling edges can be detected when the comparator is first powered on or
if changes are made to the hysteresis or response time control bits. Therefore, it is recommended that the
rising-edge and falling-edge flags be explicitly cleared to logic 0 a short time after the comparator is
enabled or its mode bits have been changed.
C8051F336/7/8/9
61 Rev.1.0
SFR Address = 0x9B
SFR Definition 11.1. CPT0CN: Comparator0 Control
Bit76543210
Name CP0EN CP0OUT CP0RIF CP0FIF CP0HYP[1:0] CP0HYN[1:0]
Type R/W R R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7 CP0EN Comparator0 Enable Bit.
0: Comparator0 Disab led .
1: Comparator0 Enab led .
6CP0OUT
Comparator0 Output State Flag.
0: Voltage on CP0+ < CP0–.
1: Voltage on CP0+ > CP0–.
5CP0RIF
Comparator0 Rising-Edge Flag. Must be cleared by software.
0: No Comparator0 Rising Edge has occurred since this flag was last cleared.
1: Comparator0 Rising Edge has occurred.
4CP0FIF
Comparator0 Falling-Edge Flag. Must be cleared by software.
0: No Comparator0 Falling-Edge has occurred since this flag was last cleared.
1: Comparator0 Falling-Edge has occurred.
3:2 CP0HYP[1:0] Comparator0 Positive Hysteresis Control Bits.
00: Positive Hysteresis Disabled.
01: Positive Hysteresis = 5 mV.
10: Positive Hysteresis = 10 mV.
11: Positive Hysteresis = 20 mV.
1:0 CP0HYN[1:0] Comparator0 Negative Hysteresis Control Bits.
00: Negative Hysteresis Disabled.
01: Negative Hysteresis = 5 mV.
10: Negative Hysteresis = 10 mV.
11: Negative Hysteresis = 20 mV.
C8051F336/7/8/9
Rev.1.0 62
SFR Address = 0x9D
SFR Definition 11.2. CPT0MD: Comparator0 Mode Selection
Bit76543210
Name CP0RIE CP0FIE CP0MD[1:0]
Type RRR/WR/WRR R/W
Reset 00000010
Bit Name Function
7:6 Unused Unused. Read = 00b, Write = Don’t Care.
5CP0RIE
Comparator0 Rising-Edge Interrupt Enable.
0: Comparator0 Rising-edge interrupt disabled.
1: Comparator0 Rising-edge interrupt enabled.
4CP0FIE
Comparator0 Falling-Edge Interrupt Enable.
0: Comparator0 Falling-edge interrupt disabled.
1: Comparator0 Falling-edge interrupt enabled.
3:2 Unused Unused. Read = 00b, Write = don’t care.
1:0 CP0MD[1:0] Comparator0 Mode Select.
These bits affect the response time and po wer consumption for Comparator0.
00: Mode 0 (Fastest Response Time, Highest Power Consumption)
01: Mode 1
10: Mode 2
11: Mode 3 (Slowest Response Time, Lowest Power Consumption)
C8051F336/7/8/9
Rev.1.0 63
11.1. Comparator Multiplexer
C8051F336/7/8/9 devices include an analog input multiplexer to connect Port I/O pins to the comparator
inputs. The Comp ar ator0 inputs are selected in the CPT0MX register (SFR Definition 11.3). The CMX0P1–
CMX0P0 bits select the Comparator0 positive input; the CMX0N1–CMX0N0 bits select the Comparator0
negative input. Important Note About Comparator Inputs : The Port pins selected as comparator inputs
should be configured as analog inputs in their associated Port configuration register, and configured to be
skipped by the Crossbar (for details on Port configuration, see Section “20.6. Special Function Regis-
ters for Accessing and Conf iguring Port I/O” on page 131).
Figure 11.3. Co mparator Input Multiplexer Block Diagram
+
-
CP0 +
P0.0
CP0 -
CPT0MX
CMX0N3
CMX0N2
CMX0N1
CMX0N0
CMX0P3
CMX0P2
CMX0P1
CMX0P0
P0.2
P0.4
P0.6
P1.0
P1.2
P1.4
P1.6
P2.0*
P2.2*
P0.1
P0.3
P0.5
P0.7
P1.1
P1.3
P1.5
P1.7
P2.1*
P2.3*
GND
VDD
*P2.0-P2.3 Only available as
inputs on QFN24 Packaging
C8051F336/7/8/9
64 Rev.1.0
SFR Address = 0x9F
SFR Definition 11.3. CPT0MX: Comparator0 MUX Selection
Bit76543210
Name CMX0N[3:0] CMX0P[3:0]
Type R/W R/W
Reset 11111111
Bit Name Function
7:4 CMX0N[3:0] Comparator0 Negative Input MUX Selection .
0000: P0.1
0001: P0.3
0010: P0.5
0011: P0.7
0100: P1.1
0101: P1.3
0110: P1.5
0111: P1.7
1000: P2.1 (C8051F338/9 Only)
1001: P2.3 (C8051F338/9 Only)
1010-1111: None
3:0 CMX0P[3:0] Comparator0 Positive Input MUX Selection.
0000: P0.0
0001: P0.2
0010: P0.4
0011: P0.6
0100: P1.0
0101: P1.2
0110: P1.4
0111: P1.6
1000: P2.0 (C8051F338/9 Only)
1001: P2.2 (C8051F338/9 Only)
1010-1111: None
C8051F336/7/8/9
Rev.1.0 65
12. CIP-51 Microcontroller
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft-
ware. The MCU family has a superset of all the peripherals included with a standard 8051. The CIP-51
also includes on-chip deb ug hardware (see description in Section 26), and interfaces directly with the ana-
log and digit al subsystems providin g a complete dat a acquisitio n or control-system solution in a single inte-
grated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see Figure 12.1 for a block diagram).
The CIP-51 includes the following features:
Performance
The CIP-51 emplo ys a p ipeli ned architectu re tha t grea tly increases it s instr uction throug hput over the st an-
dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51
core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more
than eight system clock cycles.
Figure 12.1. CIP-51 Block Diagram
Fully Compatible with MCS-51 Instruction Set
25 MIPS Peak Throughput with 25 MHz Clock
0 to 25 MHz Clock Frequency
Extended Interrupt Handler
Reset Inpu t
Power Management Modes
On-chip Debug Logic
Program and Data Memory Security
DATA BUS
TMP1 TMP2
PRGM. ADDRESS REG.
PC INCREMENTER
ALU
PSW
DATA BUS
DATA BUS
MEMORY
INTERFACE
MEM_ADDRESS
D8
PIPELINE
BUFFER
DATA P OINTER
INTERRUPT
INTERFACE
SYSTEM_IRQs
EMULATION_IRQ
MEM_CONTROL
CONTROL
LOGIC
A16
PROGRAM COUNTER (PC)
STOP
CLOCK
RESET
IDLE POWER CONTROL
REGISTER
DATA BUS
SFR
BUS
INTERFACE
SFR_ADDRESS
SFR_CONTROL
SFR_WRITE_DATA
SFR_READ_DATA
D8
D8
B REGISTER
D8
D8
ACCUMULATOR
D8
D8
D8
D8
D8
D8
D8
D8
MEM_WRITE_DATA
MEM_READ_DATA
D8
SRAM
ADDRESS
REGISTER SRAM
D8
STACK POINTER
D8
C8051F336/7/8/9
66 Rev.1.0
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has
a total of 109 instructions. The table below shows the total number of instructions that require each execu-
tion time.
12.1. Instruction Set
The instruction set of the CIP-51 System Controller is fully compatible with the st and ard MCS-51 ™ instru c-
tion set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51
instructions are the binary and functional equivalent of their MCS-51™ counterparts, including opcodes,
addressing modes and effect on PSW flags. However, instruction timing is different than that of the stan-
dard 8051.
12.1.1. Instruction and CPU Timing
In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with
machine cycles varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based
solely on clock cycle timing. All instruction timings are specified in terms of clock cycles.
Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock
cycles as there are program bytes in the instruction. Conditional branch instructions take one less clock
cycle to complete when the branch is not taken as opposed to when the branch is taken. Table 12.1 is the
CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock
cycles for each instruction.
Clocks to Execute 1 22/333/444/55 8
Number of Instructions 26 50 5 14 7 3 1 2 1
C8051F336/7/8/9
Rev.1.0 67
Table 12.1. CIP-51 Instruction Set Summary
Mnemonic Description Bytes Clock
Cycles
Arithmetic Operations
ADD A, Rn Add register to A 1 1
ADD A, direct Add direct byte to A 2 2
ADD A, @Ri Add indirect RAM to A 1 2
ADD A, #data Add immediate to A 2 2
ADDC A, Rn Add register to A with carry 1 1
ADDC A, direct Add direct byte to A with carry 2 2
ADDC A, @Ri Add indirect RAM to A with carry 1 2
ADDC A, #data Add immediate to A with carry 2 2
SUBB A, Rn Subtract register from A with bo rrow 1 1
SUBB A, direct Subtract direct byte from A with borrow 2 2
SUBB A, @Ri Subtract indirect RAM from A with borrow 1 2
SUBB A, #data Subtract immediate from A with borrow 2 2
INC A Increment A 1 1
INC Rn Increment register 1 1
INC direct Increment direct byte 2 2
INC @Ri Increment indirect RAM 1 2
DEC A Decrement A 1 1
DEC Rn Decrement register 1 1
DEC direct Decrement direct byte 2 2
DEC @Ri Decrement indirect RAM 1 2
INC DPTR Increment Data Pointer 1 1
MUL AB Multiply A and B 1 4
DIV AB Divide A by B 1 8
DA A Decimal adjust A 1 1
Logical Operations
ANL A, Rn AND Register to A 1 1
ANL A, direct AND direct byte to A 2 2
ANL A, @Ri AND indirect RAM to A 1 2
ANL A, #data AND immediate to A 2 2
ANL direct, A AND A to direct byte 2 2
ANL direct, #data AND immediate to direct byte 3 3
ORL A, Rn OR Register to A 1 1
ORL A, direct OR direct byte to A 2 2
ORL A, @Ri OR indirect RAM to A 1 2
ORL A, #data OR immediate to A 2 2
ORL direct, A OR A to direct byte 2 2
ORL direct, #data OR imm ed iat e to dire ct byte 3 3
XRL A, Rn Exclusive-OR Register to A 1 1
XRL A, direct Exclusive-OR direct byte to A 2 2
XRL A, @Ri Exclusive-OR indirect RAM to A 1 2
XRL A, #data Exclusive-OR immediate to A 2 2
XRL direct, A Exclusive-OR A to direct byte 2 2
C8051F336/7/8/9
68 Rev.1.0
XRL direct, #data Exclusive-OR immediate to direct byte 3 3
CLR A Clear A 1 1
CPL A Complement A 1 1
RL A Rotate A left 1 1
RLC A Rotate A left through Carry 1 1
RR A Rotate A right 1 1
RRC A Rotate A right through Carry 1 1
SWAP A Swap nibbles of A 1 1
Data Transfer
MOV A, Rn Move Register to A 1 1
MOV A, direct Move direct byte to A 2 2
MOV A, @Ri Move indirect RAM to A 1 2
MOV A, #data Move immediate to A 2 2
MOV Rn, A Move A to Register 1 1
MOV Rn, direct Move direct byte to Register 2 2
MOV Rn, #data Move immediate to Register 2 2
MOV direct, A Move A to direct byte 2 2
MOV direct, Rn Move Register to direct byte 2 2
MOV direct, direct Move direct byte to direct byte 3 3
MOV direct, @Ri Move indirect RAM to direct byte 2 2
MOV direct, #data Move immediate to direct byte 3 3
MOV @Ri, A Move A to indirect RAM 1 2
MOV @Ri, direct Move direct byte to indirect RAM 2 2
MOV @Ri, #data Move immediate to indirect RAM 2 2
MOV DPTR, #data16 Load DPTR with 16-bit constant 3 3
MOVC A, @A+DPTR Move code byte relative DPTR to A 1 3
MOVC A, @A+PC Move code byte relative PC to A 1 3
MOVX A, @Ri Move external data (8-bit address) to A 1 3
MOVX @Ri, A Move A to external data (8-bit address) 1 3
MOVX A, @DPTR Move external data (16-bit address) to A 1 3
MOVX @DPTR, A Move A to external data (16-bit address) 1 3
PUSH direct Push direct byte onto stack 2 2
POP direct Pop direct byte from stack 2 2
XCH A, Rn Exchange Register with A 1 1
XCH A, direct Exchange direct byte with A 2 2
XCH A, @Ri Exchange indirect RAM with A 1 2
XCHD A, @Ri Exchange low nibble of indirect RAM with A 1 2
Boolean Manipulation
CLR C Clear Carry 1 1
CLR bit Clear direct bit 2 2
SETB C Set Carry 1 1
SETB bit Set direct bit 2 2
CPL C Complement Carry 1 1
CPL bit Complement direct bit 2 2
Table 12.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic Description Bytes Clock
Cycles
C8051F336/7/8/9
Rev.1.0 69
ANL C, bit AND direct bit to Carry 2 2
ANL C, /bit AND complement of direct bit to Carry 2 2
ORL C, bit OR direct bit to carry 2 2
ORL C, /bit OR complement of direct bit to Carry 2 2
MOV C, bit Move direct bit to Carry 2 2
MOV bit, C Move Carry to direct bit 2 2
JC rel Jump if Carry is set 2 2/3
JNC rel Jump if Carry is not set 2 2/3
JB bit, rel Jump if direct bit is set 3 3/4
JNB bit, rel Jump if direct bit is not set 3 3/4
JBC bit, rel Jump if direct bit is set and clear bit 3 3/4
Program Branching
ACALL addr11 Absolute subroutine call 2 3
LCALL addr16 L on g su br ou tin e ca ll 3 4
RET Return from subroutine 1 5
RETI Return from interrupt 1 5
AJMP addr11 Absolute jump 2 3
LJMP addr16 Long jump 3 4
SJMP rel Short jump (relative address) 2 3
JMP @A+DPTR Jump indirect relative to DPTR 1 3
JZ rel Jump if A equals zero 2 2/3
JNZ rel Jump if A does not equal zero 2 2/3
CJNE A, direct, rel Compare direct byte to A and jump if not equal 3 3/4
CJNE A, #data, rel Compare immediate to A and jump if not equal 3 3/4
CJNE Rn, #data, rel Compare immediate to Register and jump if not
equal 33/4
CJNE @Ri, #data, re l Compare immediate to indirect and jump if not
equal 34/5
DJNZ Rn, rel Decrement Register and jump if not zero 2 2/3
DJNZ direct, rel Decrement direct byt e and jum p if not zer o 3 3/4
NOP No operation 1 1
Table 12.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic Description Bytes Clock
Cycles
C8051F336/7/8/9
70 Rev.1.0
Notes on Registers, Oper ands and Addressing Modes:
Rn - Register R0–R7 of the currently selected register bank.
@Ri - Data RAM location addressed indirectly through R0 or R1.
rel - 8-bit, signed (twos complement) offset relative to the first byte of the following instruction. Used by
SJMP and all conditional jumps.
direct - 8-bit internal data location’s address. This could be a direct-access Data RAM location
(0x00–0x7F) or an SFR (0x80–0xFF).
#data - 8-bit constant
#data16 - 16-bit constant
bit - Direct-accessed bit in Data RAM or SFR
addr11 - 11-bit destination address used b y ACALL and AJMP. The destination must be within the same
2 kB page of program memory as the first byte of the following instruction.
addr16 - 16-bit d estination ad dress used b y LCALL and LJMP. The destination may b e anywher e with in
the 8 kB program memory space.
There is one unused opcode (0xA5) that performs the same function as NOP.
All mnemonics copyrighted © Intel Corporation 1980.
C8051F336/7/8/9
Rev.1.0 71
12.2. CIP-51 Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits
should always be written to the value indicated in the SFR description. Future product versions may use
these bits to implement new features in which case the reset value of the bit will be the indicated value,
selecting the feature's default state. Detailed descriptions of the remaining SFRs are included in the sec-
tions of the data sheet associated with their corresponding system function.
SFR Address = 0x82
SFR Address = 0x83
SFR Definition 12.1. DPL: Data Pointer Low Byte
Bit76543210
Name DPL[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 DPL[7:0] Data Pointer Low.
The DPL register is the low byte of the 16-bit DPTR.
SFR Definition 12.2. DPH: Data Pointer High Byte
Bit76543210
Name DPH[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 DPH[7:0] Data Pointer High.
The DPH register is the high byte of the 16-bit DPTR.
C8051F336/7/8/9
72 Rev.1.0
SFR Address = 0x81
SFR Address = 0xE0; Bit-Addressable
SFR Address = 0xF0; Bit-Addressable
SFR Definition 12.3. SP: Stack Pointer
Bit76543210
Name SP[7:0]
Type R/W
Reset 00000111
Bit Name Function
7:0 SP[7:0] Stack Pointer.
The S t ack Pointer holds the location of the top of the stack. The st ack pointer is incre-
mented before every PUSH operation. The SP register defaults to 0x07 after reset.
SFR Definition 12.4. ACC: Accumulator
Bit76543210
Name ACC[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 ACC[7:0] Accumulator.
This register is the accumulator for arithmetic operations.
SFR Definition 12.5. B: B Register
Bit76543210
Name B[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 B[7:0] B Register.
This register serves as a second accumulator for certain arithmetic operations.
C8051F336/7/8/9
Rev.1.0 73
SFR Address = 0xD0; Bit-Addressable
SFR Definition 12.6. PSW: Program Status Word
Bit76543210
Name CY AC F0 RS[1:0] OV F1 PARITY
Type R/W R/W R/W R/W R/W R/W R
Reset 00000000
Bit Name Function
7CY
Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a bor-
row (subtraction). It is cleared to logic 0 by all other arithmetic operations.
6AC
Auxiliary Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a
borrow from (subtraction) th e high order nibble. It is cleared to logic 0 by all other arith-
metic opera tions .
5F0
User Flag 0.
This is a bit-addres sable, general purpose flag for use under software control.
4:3 RS[1:0] Register Bank Select.
These bits select which register bank is used during register accesses.
00: Bank 0, Addresses 0x00-0x07
01: Bank 1, Addresses 0x08-0x0F
10: Bank 2, Addresses 0x10-0x17
11: Bank 3, Addresses 0x18-0x1F
2OV
Overflow Flag.
This bit is set to 1 under the following circumstances:
An ADD, ADDC, or SUBB instruction causes a sign-change overflow.
A MUL instruction results in an overflow (result is greater than 255).
A DIV instruction causes a divide- by-zero condition.
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all
other cases.
1F1
User Flag 1.
This is a bit-addres sable, general purpose flag for use under software control.
0PARITY
Parity Flag.
This bit is set to logic 1 if the sum of the eigh t bits in the accumulator is odd and cleared
if the sum is even.
C8051F336/7/8/9
Rev.1.0 74
13. Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types. The memory organization of the
C8051F336/7/8/9 device family is shown in Figure 13.1
Figure 13.1. C8051F336/7/8/9 Memory Map
PROGRAM/DATA MEMORY
(FLASH)
(Direct and Indirect
Addressing)
0x00
0x7F
Upper 128 RAM
(Indirect Addressing
Only)
0x80
0xFF Special Function
Register's
(Direct Addressing Only)
DATA MEMORY (RAM)
General Purpose
Registers
0x1F
0x20
0x2F Bit Addressable
Lower 128 RAM
(Direct and Indirect
Addressing)
0x30
INTERNAL DATA ADDRESS SPACE
EXTERNAL DATA ADDRESS SPACE
XRAM - 512 Bytes
(accessable using MOVX
instruction)
0x0000
0x01FF
Same 512 bytes as from
0x0000 to 0x01FF, wrapped
on 512-byte boundaries
0x0200
0xFFFF
16 K FLASH
(In-System
Programmable in 512
Byte Sectors)
0x0000
RESERVED
0x3E00
0x3DFF
C8051F336/7/8/9
75 Rev.1.0
13.1. Program Memory
The CIP-51 core has a 64 kB program memory sp ace. The C8051F336/7 /8/9 implement s 16 kB of this pro-
gram memory space as in-system, re-programmable Flash memory, organized in a contiguous block from
addresses 0x0000 to 0x3DFF. The address 0x3DFF serves as the security lock byte for the device, and
addresses ab ov e 0x 3DF F are res er ve d.
Figure 13.2. Flash Program Memory Map
13.1.1. MOVX Instruction and Program Memory
The MOVX instruction in an 8051 device is typically used to access external data memory. On the
C8051F336/7/8/9 devices, the MOVX instruction is normally used to read and write on-chip XRAM, but can
be re-configured to write and erase on-chip Flash memor y space. MOV C instructions are alwa ys used to
read Flash memory, while MOVX write instructions are used to erase and write Flash. This Flash access
feature provides a mechanism for the C8051F336/7/8/9 to update program code and use the program
memory space for non-volatile data storage. Refer to Section “16. Flash Memory” on p age 91 for further
details.
13.2. Data Memory
The C8051F336/7/8/9 device family includes 768 bytes of RAM data memory. 256 bytes of this memory is
mapped into the internal RAM space of the 8051. 512 bytes of this memory is on-chip “external” memory.
The data memory map is shown in Figure 13.1 for reference.
13.2.1. Internal RAM
There are 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The
lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either
direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00
through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight
byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as bytes or
as 128 bit locations accessible with the direct addressing mode.
The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the
same address space as the Special Function Registers (SFR) but is physically separate from the SFR
Lock Byte
0x0000
0x3DFF
0x3DFE
0x3E00
FLASH memory organized in
512-byte pages
0x3C00
Flash Memory Space
Lock Byte Page
0x3FFF
Reserved Area
C8051F336/7/8/9
Rev.1.0 76
space. The addressing mode used by an instruction when accessing locations above 0x7F determines
whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use
direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the
upper 128 bytes of data memory. Figure 13.1 illustrates the data memory organization of the
C8051F336/7/8/9.
13.2.1.1. General Purpose Registers
The lower 32 bytes of dat a memory, locations 0x00 through 0x1F, may be addressed as four banks of gen-
eral-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only
one of these banks may be enabled at a time. Two bits in th e progr am st atus wo rd , RS0 (PSW.3) and RS1
(PSW.4), select the active register bank (see description of the PSW in SFR Definition 12.6). This allows
fast context switching when entering subr outin es and interrupt se rvice routines. Indir ect addressin g modes
use registers R0 and R1 as index registers.
13.2.1.2. Bit Addressable Locations
In addition to direct access to d ata memory organized as bytes, the sixtee n d ata memory locations at 0x20
through 0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from
0x00 to 0x7F. Bit 0 of the byte at 0 x20 has bit addr ess 0x00 while bit7 of the byte at 0 x20 has bit addr ess
0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished from a full byte access by
the type of instruction used (bit source or destination operands as opposed to a byte source or destina-
tion).
The MCS-51™ assembly language allows an alternate notation for bit addressing of the form XX.B where
XX is the byte address and B is the bit position within the byte. For example, the instruction:
MOV C, 22.3h
moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag.
13.2.1.3. Stack
A programmer's stack can be located anywhere in the 256-byte data memory. The stack area is desig-
nated using the Stack Pointer (SP) SFR. The SP will point to the last location used. The next value pushed
on the stack is placed at SP+1 and then SP is incremented. A reset initializes the stack pointer to location
0x07. Therefore, the first value pushed on the stack is placed at location 0x08, which is also the first regis-
ter (R0) of register bank 1. Thus, if more than one register bank is to be used, the SP should be initialized
to a location in the data memory not being used for data storage. The stack depth can extend up to
256 bytes.
13.2.2. External RAM
There are 512 bytes of on-chip RAM mapped into the external data memory space. All of these address
locations may be accessed using the external move instruction (MOVX) and the data pointer (DPTR), or
using MOVX indirect addressing mode. If the MOVX instruction is used with an 8-bit address operand
(such as @R1), then the high byte of the 16-bit address is provided by the External Memory Interface Con-
trol Register (EMI0CN a s shown in SFR Definition 13 .1). Note: the MOVX instruction is also used for writes
to the Flash memory. See Section “16. Flash Memory” on page 91 for details. The MOVX instruction
accesses XRAM by default.
For a 16-bit MOVX operation (@DPTR), the upper 7 bits of the 16-bit external data memory address word
are "don't cares". As a result, the 512-byte RAM is mapped modulo style over the entire 64 k external data
memory address range. For example, the XRAM byte at address 0x0000 is shadowed at addresses
0x0200, 0x0400, 0x0600, 0 x080 0, etc. Th is is a useful fe atur e when pe rf or min g a linea r me mor y fill , a s the
address pointer doesn't have to be reset when reaching the RAM block boundary.
C8051F336/7/8/9
77 Rev.1.0
SFR Address = 0xAA
SFR Definition 13.1. EMI0CN: External Memory Interface Control
Bit76543210
Name PGSEL
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7:1 UNUSED Unused. Read = 0000000b; Write = Don’t Care
0 PGSEL XRAM Page Select.
The EMI0CN register provides the high byte of the 16-bit external data memory
address when using an 8-bit MOVX command, effectively selecting a 256-byte page
of RAM. Since the upper (unused) bits of the register are always zero, the PGSEL
determines which page of XRAM is accessed.
For Example: If EMI0CN = 0x01, addresses 0x0100 through 0x01FF will be
accessed.
C8051F336/7/8/9
Rev.1.0 78
14. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide co ntrol and data exchange with the C8051 F336/7/8/9's resources and per ipher-
als. The CIP-51 controller core duplicates the SFRs found in a typical 8051 implementation as well as
implementing additional SFRs used to configure and access the sub-systems unique to the
C8051F336/7/8/9. This allows the addition of new functionality wh ile retaining compatibility with the MCS-
51™ instruction set. Table 14.1 lists the SFRs implemented in the C8051F336/7/8/9 device family.
The SFR regist ers are access ed anytime the direct a ddressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with a ddresses ending in 0x0 or 0x8 (e.g. P0, TCON, SCON0, IE, etc.) are bit-
addressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied
addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate
effect and should be avoided. Refer to the corresponding pages of the data sheet, as indicated in
Table 14.2, for a detailed description of each register.
Table 14.1. Special Function Register (SFR) Memory Map
F8 SPI0CN PCA0L PCA0H PCA0CPL0 PCA0CPH0 P0MAT P0MASK VDM0CN
F0 B P0MDIN P1MDIN P2MDIN EIP1 PCA0PWM
E8 ADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2 P1MAT P1MASK RSTSRC
E0 ACC XBR0 XBR1 OSCLCN IT01CF EIE1 SMB0ADM
D8 PCA0CN PCA0MD PCA0CPM0PCA0CPM1PCA0CPM2
D0 PSW REF0CN P0SKIP P1SKIP P2SKIP SMB0ADR
C8 TMR2CN TMR2RLL TMR2RLH TMR2L TMR2H
C0 SMB0CN SMB0CF SMB0DAT ADC0GTL ADC0GTH ADC0LTL ADC0LTH
B8 IP IDA0CN AMX0N AMX0P ADC0CF ADC0L ADC0H
B0 OSCXCN OSCICN OSCICL FLSCL FLKEY
A8 IE CLKSEL EMI0CN
A0 P2 SPI0CFG SPI0CKR SPI0DAT P0MDOUT P1MDOUT P2MDOUT
98 SCON0 SBUF0 CPT0CN CPT0MD CPT0MX
90 P1 TMR3CN TMR3RLL TMR3RLH TMR3L TMR3H IDA0L IDA0H
88 TCON TMOD TL0 TL1 TH0 TH1 CKCON PSCTL
80 P0 SP DPL DPH PCON
0(8) 1(9) 2(A) 3(B) 4(C) 5(D) 6(E) 7(F)
Note: SFR Addresses ending in 0x0 or 0x8 are bit-addressable locations and can be used with bitwise instructions.
C8051F336/7/8/9
79 Rev.1.0
Table 14.2. Special Function Registers
SFRs are listed in alphab et ica l or d er. All undefin ed SFR locat ion s ar e re se rve d
Register Address Description Page
ACC 0xE0 Accumulator 72
ADC0CF 0xBC ADC0 Configuration 41
ADC0CN 0xE8 ADC0 Control 43
ADC0GTH 0xC4 ADC0 Gr ea te r- Th a n Co mpare High 44
ADC0GTL 0xC3 ADC 0 Grea te r- Th a n Co mpare Lo w 44
ADC0H 0xBE ADC0 High 42
ADC0L 0xBD ADC0 Low 42
ADC0LTH 0xC6 ADC0 Less-Than Compare Word High 45
ADC0LTL 0xC5 ADC0 Less-Than Compare Word Low 45
AMX0N 0xBA AMUX0 Negative Channel Select 50
AMX0P 0xBB AMUX0 Positive Channel Select 49
B0xF0 B Register 72
CKCON 0x8E Clock Control 181
CLKSEL 0xA9 Clock Select 110
CPT0CN 0x9B Comparator0 Control 61
CPT0MD 0x9D Comparator0 Mode Selection 62
CPT0MX 0x9F Comparator0 MUX Selection 64
DPH 0x83 Data Pointer High 71
DPL 0x82 Data Pointer Low 71
EIE1 0xE6 Extended Interrupt Enable 1 87
EIP1 0xF6 Extended Interrupt Priority 1 88
EMI0CN 0xAA External Memory Interface Control 77
FLKEY 0xB7 Flash Lock and Key 98
FLSCL 0xB6 Flash Scale 99
IDA0CN 0xB9 Current Mode DAC0 Control 54
IDA0H 0x97 Current Mode DAC0 High 55
IDA0L 0x96 Current Mode DAC0 Low 55
IE 0xA8 Interrupt Enable 85
IP 0xB8 Interrupt Priority 86
IT01CF 0xE4 INT0/INT1 Configuration 90
OSCICL 0xB3 Internal Oscillator Calibration 111
OSCICN 0xB2 Internal Oscillator Control 112
OSCLCN 0xE3 Low-Frequency Oscillator Control 113
C8051F336/7/8/9
Rev.1.0 80
OSCXCN 0xB1 External Oscillator Control 115
P0 0x80 Port 0 Latch 132
P0MASK 0xFE Port 0 Mask Configuration 129
P0MAT 0xFD Port 0 Match Configuration 130
P0MDIN 0xF1 Port 0 Input Mo de Con fig ur ation 132
P0MDOUT 0xA4 Port 0 Output Mode Configuration 133
P0SKIP 0xD4 Port 0 Skip 133
P1 0x90 Port 1 Latch 134
P1MASK 0xEE Port 1Mask Configuration 130
P1MAT 0xED Port 1 Match Configuration 131
P1MDIN 0xF2 Port 1 Input Mo de Con fig ur ation 134
P1MDOUT 0xA5 Port 1 Output Mode Configuration 135
P1SKIP 0xD5 Port 1 Skip 135
P2 0xA0 Port 2 Latch 136
P2MDIN 0xF3 Port 2 Input Mo de Con fig ur ation 136
P2MDOUT 0xA6 Port 2 Output Mode Configuration 137
P2SKIP 0xD6 Port 2 Skip 137
PCA0CN 0xD8 PCA Control 215
PCA0CPH0 0xFC PCA Capture 0 High 2 20
PCA0CPH1 0xEA PCA Capture 1 High 220
PCA0CPH2 0xEC PCA Capture 2 High 220
PCA0CPL0 0xFB PCA Captur e 0 Low 220
PCA0CPL1 0xE9 PCA Capture 1 Low 220
PCA0CPL2 0xEB PCA Ca pt ur e 2 Low 220
PCA0CPM0 0xDA PCA Module 0 Mode Register 218
PCA0CPM1 0xDB PCA Module 1 Mode Register 218
PCA0CPM2 0xDC PCA Module 2 Mode Register 218
PCA0H 0xFA PCA Counter High 219
PCA0L 0xF9 PCA Counter Lo w 219
PCA0MD 0xD9 PCA Mode 216
PCA0PWM 0xF7 PCA PWM Configurat ion 217
PCON 0x87 Power Control 108
PSCTL 0x8F Program Store R/W Control 97
PSW 0xD0 Program Status Word 73
Table 14.2. Special Function Registers (Continued)
SFRs are listed in alphab et ica l or d er. All undefin ed SFR locat ion s ar e re se rve d
Register Address Description Page
C8051F336/7/8/9
81 Rev.1.0
REF0CN 0xD1 Voltage Reference Control 57
RSTSRC 0xEF Reset Source Configuration/Status 105
SBUF0 0x99 UART0 Data Buffer 165
SCON0 0x98 UART0 Control 164
SMB0ADM 0xE7 SMBus Slave Address Mask 149
SMB0ADR 0xD7 SMBus Slave Address 148
SMB0CF 0xC1 SMBus Configuration 144
SMB0CN 0xC0 SMBus Control 146
SMB0DAT 0xC2 SMBus Data 150
SP 0x81 Stack Pointer 72
SPI0CFG 0xA1 SPI Configuration 174
SPI0CKR 0xA2 SPI Clock Rate Control 176
SPI0CN 0xF8 SPI Control 175
SPI0DAT 0xA3 SPI Data 176
TCON 0x88 Ti mer/Counter Control 186
TH0 0x8C Timer/Counter 0 High 189
TH1 0x8D Timer/Counter 1 High 189
TL0 0x8A Timer/Counter 0 Low 188
TL1 0x8B Timer/Counter 1 Low 188
TMOD 0x89 Timer/Counter Mode 187
TMR2CN 0xC8 Timer/Counter 2 Contro l 193
TMR2H 0xCD Timer/Counter 2 High 195
TMR2L 0xCC Timer/Counter 2 Low 194
TMR2RLH 0xCB Timer/Counter 2 Reload High 194
TMR2RLL 0xCA Timer/Counter 2 Reload Low 194
TMR3CN 0x91 Timer/Counter 3Control 19 9
TMR3H 0x95 Timer/Counter 3 High 201
TMR3L 0x94 Timer/Counter 3Low 200
TMR3RLH 0x93 Timer/Counter 3 Reload High 200
TMR3RLL 0x92 Timer/Counter 3 Reload Low 200
VDM0CN 0xFF VDD Monitor Control 103
XBR0 0xE1 Port I/O Crossbar Control 0 127
XBR1 0xE2 Port I/O Crossbar Control 1 128
Table 14.2. Special Function Registers (Continued)
SFRs are listed in alphab et ica l or d er. All undefin ed SFR locat ion s ar e re se rve d
Register Address Description Page
C8051F336/7/8/9
Rev.1.0 82
15. Interrupts
The C8051F336/7/8/9 includes an extended in terrupt syst em supporting a tot al of 14 interrupt sources with
two priority levels . The allocation of in terrupt source s between on-chip peripherals and ex ternal input pin s
varies according to the specific version of the device. Each interrupt source has one or more associated
interrupt-pending flag(s) located in an SFR. When a peripheral or external source meets a valid interrupt
condition, the associated interrupt-pending flag is set to logic 1.
If interrupt s are ena bled for the sour ce, an interrupt req uest is generated when the inter rupt-pending flag is
set. As soon as execution of the current instruction is complete, the CPU generates an LCALL to a prede-
termined address to begin executio n of an interrupt service routine ( ISR). Each ISR must end with an RETI
instruction, which returns program execution to the next instruction that would have been executed if the
interrupt requ est had not occurred. If inter rupt s are not enabled, the inter rupt-pending flag is ignored by the
hardware and program execution continues as normal. (The interrupt-pending flag is set to logic 1 regard-
less of the interrupt's enable/disable state.)
Each interrupt source can be individually enabled or disabled through the use of an associated interrupt
enable bit in an SFR (IE–EIE1). However, interrupts must first be globally enabled by setting the EA bit
(IE.7) to logic 1 before the individual interrup t enabl es are recognize d. Setting the EA b it to logic 0 disables
all interrupt sources regardless of the individual interrupt-enable settings.
Note: Any instruction that clears a bit to disable an interrupt should be imme d i at ely followed by an instruc-
tion that has two or more opcode bytes. Using EA (global interrupt enable) as an example:
// in 'C':
EA = 0; // clear EA bit.
EA = 0; // this is a dummy instruction with two-byte opcode.
; in assembly:
CLR EA ; clear EA bit.
CLR EA ; this is a dummy instruction with two-byte opcode.
For example, if an interrupt is posted during the execution phase of a "CLR EA" opcode (or any instruction
which clears a bit to disable an interrupt sour ce), and the instruction is followed by a single-cycle instruc-
tion, the interrupt may be taken. However, a read of the enable bit will return a '0' inside the interrupt ser-
vice routine. When the bit-clearing opcode is followed by a multi-cy cle instruction, the interrupt will not be
taken.
Some interrupt-pending flags ar e auto matically cleare d by the hardware when the CPU vectors to the ISR.
However, most are not cleared by the hardware and must be cleared by software before returning from the
ISR. If an interrupt-pending flag remains set after the CPU completes the return-from-interrupt (RETI)
instruction, a new interrupt request will be generated immediately and the CPU will re-enter the ISR after
the completion of the next instruction.
C8051F336/7/8/9
83 Rev.1.0
15.1. MCU Interrupt Sources and Vectors
The C8051F336/7/8/9 MCUs support 14 interrupt sources. Software can simulate an interrupt by setting
any interrupt-pending flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be gener-
ated and the CPU will vector to the ISR address associated with the interrupt-pending flag. MCU interrupt
sources, associated vector addresses, priority order and control bits are summarized in Table 15.1. Refer
to the datasheet section associated with a particular on-chip peripheral for information regarding valid
interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s) .
15.1.1. Interrupt Priorities
Each interrupt source can be in dividua lly prog ra mmed to one of two priority levels: low or high. A low prior-
ity interrupt service routine can be pree mpted by a high priority inte rrupt. A high priority interrupt cannot be
preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP or EIP1) used to configure
its priority level. Low priority is the defa ult. If two interrupt s are recognize d simultane ously, the interrupt with
the higher priority is serviced first. If both interrupts have the same priority level, a fixed priority order is
used to arbitrate, given in Table 15.1.
15.1.2. Interrupt Latency
Interrupt response time depen ds on the state of the CPU when the interrupt occurs. Pending interru pts are
sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 5
system clock cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the
ISR. If an interrupt is pending when a RETI is executed, a single instruction is executed before an LCALL
is made to serv ice the pendin g inte rrup t. Th eref ore, the maxim um r espo nse tim e for an int errupt (when no
other interrupt is currently being serviced or the ne w interrupt is of greater priority) occurs when the CPU is
performing an RETI instruction followed by a DIV as the next instruction. In this case, the response time is
18 system clock cycles: 1 clock cycle to detect the interrupt, 5 clock cycles to execute the RETI, 8 clock
cycles to complete the DIV instruction and 4 clock cycles to execut e the LCALL to the ISR. If the CPU is
executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until the
current ISR completes, including the RETI and following instruction.
C8051F336/7/8/9
Rev.1.0 84
15.2. Interrupt Register Descriptions
The SFRs used to enable the interrupt sources and set their priority level are described in this section.
Refer to the data sheet section associated with a particular on-chip peripheral for information regarding
valid interrupt conditions fo r the peripheral and the behavior of its interrupt-pending flag(s).
Table 15.1. Interrupt Summary
Interrupt Source Interrupt
Vector Priority
Order Pending Flag
Bit addressable?
Cleared by HW?
Enable
Flag Priority
Control
Reset 0x0000 Top None N/A N/A Always
Enabled Always
Highest
External Interrupt 0
(/INT0) 0x0003 0 IE0 (TCON.1) Y Y EX0 (IE.0) PX0 (IP.0)
Timer 0 Overflow 0x000B 1 TF0 (TCON.5) Y Y ET0 (IE.1) PT0 (IP.1)
External Interrupt 1
(/INT1) 0x0013 2 IE1 (TCON.3) Y Y EX1 (IE.2) PX1 (IP.2)
Timer 1 Overflow 0x001B 3 TF1 (TCON.7) Y Y ET1 (IE.3) PT1 (IP.3)
UART0 0x0023 4 RI0 (SCON0.0)
TI0 (SCON0.1) Y N ES0 (IE.4) PS0 (IP.4)
Timer 2 Overflow 0x002B 5 TF2H (TMR2CN.7)
TF2L (TMR2CN.6) Y N ET2 (IE.5) PT2 (IP.5)
SPI0 0x0033 6 SPIF (SPI0CN.7)
WCOL (SPI0CN.6)
MODF (SPI0CN.5)
RXOVRN (SPI0CN.4)
Y N ESPI0
(IE.6) PSPI0
(IP.6)
SMB0 0x003B 7 SI (SMB0CN.0) Y N ESMB0
(EIE1.0) PSMB0
(EIP1.0)
Port Match 0x0043 8 None N/A N/A EMAT
(EIE1.1) PMAT
(EIP1.1)
ADC0 Window Com-
pare 0x004B 9 AD0WINT
(ADC0CN.3) Y N EWADC0
(EIE1.2) PWADC0
(EIP1.2)
ADC0 Conversion
Complete 0x0053 10 AD0INT (ADC0CN.5) Y N EADC0
(EIE1.3) PADC0
(EIP1.3)
Programmable Coun-
ter Array 0x005B 11 CF (PCA0CN.7)
CCFn (PCA0CN.n)
COVF (PCA0PWM.6)
Y N EPCA0
(EIE1.4) PPCA0
(EIP1.4)
Comparato r0 0x0063 12 CP0FIF (CPT0CN.4)
CP0RIF (CPT0CN.5) NNECP0
(EIE1.5) PCP0
(EIP1.5)
RESERVED 0x006B 13 N/A N/A N/A N/A N/A
Timer 3 Overflow 0x0073 14 TF3H (TMR3CN.7)
TF3L (TMR3CN.6) NNET3
(EIE1.7) PT3
(EIP1.7)
C8051F336/7/8/9
85 Rev.1.0
SFR Address = 0xA8; Bit-Addressable
SFR Definition 15.1. IE: Interrupt Enable
Bit76543210
Name EA ESPI0 ET2 ES0 ET1 EX1 ET0 EX0
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7EA
Enable All Interrupts.
Globally enables/disables all interrupts. It overrides individual interrupt mask settings.
0: Disable all interrupt sources.
1: Enable each interrupt according to its individual mask setting.
6 ESPI0 Enable Serial Peripheral Interface (SPI0) Interrupt.
This bit set s the masking of the SPI0 interrupts.
0: Disable all SPI0 interrupts.
1: Enable interrupt requests generated by SPI0.
5ET2
Enable Timer 2 Interrupt.
This bit set s the masking of the Timer 2 interrupt.
0: Disable Timer 2 interrupt.
1: Enable interrupt requests generated by the TF2L or TF2H flags.
4 ES0 Enable UART0 Interrupt.
This bit sets the masking of the UART0 interrupt.
0: Disable UART0 interrupt.
1: Enable UART0 interrupt.
3ET1
Enable Timer 1 Interrupt.
This bit set s the masking of the Timer 1 interrupt.
0: Disable all Timer 1 interrupt.
1: Enable interrupt requests generated by the TF1 flag.
2 EX1 Enable External Interrupt 1.
This bit sets the masking of External Interrupt 1.
0: Disable external interrupt 1.
1: Enable interrupt requests generated by the /INT1 input.
1ET0
Enable Timer 0 Interrupt.
This bit set s the masking of the Timer 0 interrupt.
0: Disable all Timer 0 interrupt.
1: Enable interrupt requests generated by the TF0 flag.
0 EX0 Enable External Interrupt 0.
This bit sets the masking of External Interrupt 0.
0: Disable external interrupt 0.
1: Enable interrupt requests generated by the /INT0 input.
C8051F336/7/8/9
Rev.1.0 86
SFR Address = 0xB8; Bit-Addressable
SFR Definition 15.2. IP: Interrupt Priority
Bit76543210
Name PSPI0 PT2 PS0 PT1 PX1 PT0 PX0
Type R R/W R/W R/W R/W R/W R/W R/W
Reset 10000000
Bit Name Function
7 UNUSED Unused. Read = 1, Write = Don't Care.
6 PSPI0 Serial Peripheral Interface (SPI0) Interrupt Priority Control.
This bit sets the priority of the SPI0 interrupt.
0: SPI0 interrupt set to low priority level.
1: SPI0 interrupt set to high priority level.
5PT2
Timer 2 Interrupt Priority Control.
This bit sets the priority of th e Timer 2 interrupt.
0: Timer 2 interrupt set to low priority level.
1: Timer 2 interrupt set to high priority level.
4 PS0 UART0 Interrupt Priority Control.
This bit sets the priority of the UART0 interrupt.
0: UART0 interrupt set to low priority level.
1: UART0 interrupt se t to high priority level.
3PT1
Timer 1 Interrupt Priority Control.
This bit sets the priority of th e Timer 1 interrupt.
0: Timer 1 interrupt set to low priority level.
1: Timer 1 interrupt set to high priority level.
2 PX1 External Interrupt 1 Priority Control.
This bit sets the priority of the External Interrupt 1 interrupt.
0: External Interrupt 1 set to low priority level.
1: External Interrupt 1 set to high priority level.
1PT0
Timer 0 Interrupt Priority Control.
This bit sets the priority of th e Timer 0 interrupt.
0: Timer 0 interrupt set to low priority level.
1: Timer 0 interrupt set to high priority level.
0 PX0 External Interrupt 0 Priority Control.
This bit sets the priority of the External Interrupt 0 interrupt.
0: External Interrupt 0 set to low priority level.
1: External Interrupt 0 set to high priority level.
C8051F336/7/8/9
87 Rev.1.0
SFR Address = 0xE6
SFR Definition 15.3. EIE1: Extended Interrupt Enable 1
Bit76543210
Name ET3 Reserved ECP0 EPCA0 EADC0 EWADC0 EMAT ESMB0
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7ET3
Enable Timer 3 Interrupt.
This bit sets the masking of the Timer 3 interrupt.
0: Disable Timer 3 interrupts.
1: Enable interrupt requests generated by the TF3L or TF3H flags.
6 Reserved Reserved. Must Write 0.
5ECP0
Enable Comparator0 (CP0) Interrupt.
This bit sets the masking of the CP0 interrupt.
0: Disable CP0 interrupts.
1: Enable interrupt requests generated by the CP0RIF or CP0FIF flags.
4 EPCA0 Enable Programmable Counter Array (PCA0) Interrupt.
This bit sets the masking of the PCA0 interrupts.
0: Disable all PCA0 interrupts.
1: Enable interrupt requests generated by PCA0.
3 EADC0 Enable ADC0 Conversion Complete Interrupt.
This bit sets the masking of the ADC0 Conversion Complete interrupt.
0: Disable ADC0 Conversion Complete interrupt.
1: Enable interrupt requests generated by the AD0INT flag.
2EWADC0
Enable Window Comparison ADC0 Interrupt.
This bit sets the masking of ADC0 Window Comparison interrupt.
0: Disable ADC0 Window Comparison interrupt.
1: Enable interrupt requests generated by ADC0 Window Compare fla g (AD0WINT).
1EMAT
Enable Port Match Interrupts.
This bit sets the masking of the Port Match Event interrupt.
0: Disable all Port Match interrupts.
1: Enable interrupt requests generated by a Port Ma tch.
0 ESMB0 Enable SMBus (SMB0) Interrupt.
This bit sets the masking of the SMB0 interrupt.
0: Disable all SMB0 interrupts.
1: Enable interrupt requests generated by SMB0.
C8051F336/7/8/9
Rev.1.0 88
SFR Address = 0xF6
SFR Definition 15.4. EIP1: Extended Interrupt Priority 1
Bit76543210
Name PT3 Reserved PCP0 PPCA0 PADC0 PWADC0 PMAT PSMB0
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7PT3
Timer 3 Interrupt Priority Control.
This bit sets the priority of th e Timer 3 interrupt.
0: Timer 3 interrupts set to low priority level.
1: Timer 3 interrupts set to high priority level.
6 Reserved Reserved. Must Write 0.
5PCP0
Comparator0 (CP0) Interrupt Priority Control.
This bit sets the priority of the CP0 interrupt.
0: CP0 interrupt set to low priority level.
1: CP0 interrupt set to high priority level.
4 PPCA0 Programmable Counter Array (PCA0) Interrupt Priority Control.
This bit sets the priority of the PCA0 interrupt.
0: PCA0 interrupt set to low priority level.
1: PCA0 interrupt set to high priority level.
3 PADC0 ADC0 Conversion Complete Interrupt Priority Control.
This bit sets the priority of the ADC0 Conversion Complete interrupt.
0: ADC0 Conversion Complete interrupt set to low priority level.
1: ADC0 Conversion Complete interrupt set to high priority level.
2PWADC0
ADC0 Window Comparator Interrupt Priority Control.
This bit sets the priority of the ADC0 Window interrupt.
0: ADC0 Window interrupt set to low priority level.
1: ADC0 Window interrupt set to high priority level.
1PMAT
Port Match Interrupt Priority Control.
This bit sets the priority of the Port Match Event interrupt.
0: Port Match interrupt set to low priority level.
1: Port Match interrupt set to high priority level.
0 PSMB0 SMBus (SMB0) Interrupt Priority Control.
This bit sets the priority of the SMB0 interrupt.
0: SMB0 interrupt set to low priority level.
1: SMB0 interrupt set to high priority level.
C8051F336/7/8/9
89 Rev.1.0
15.3. External Interrupts /INT0 and /INT1
The /INT0 and /INT1 external interrupt sources are configurable as active high or low, edge or level sensi-
tive. The IN0PL (/INT0 Polarity) and IN1PL (/INT1 Polarity) bits in the IT01CF register select active high or
active low; the IT0 and IT 1 bits in TCON (Section “24.1. Timer 0 and Timer 1” on page 182) select level
or edge sensitive. The table below lists the possible configurations.
/INT0 and /INT1 are assigned to Port pins as defined in the IT01CF register (see SFR Definition 15.5).
Note that /INT0 and /INT0 Port pin assignments are independent of any Crossbar assignments. /INT0 and
/INT1 will monitor their assigned Port pins without disturbing the peripheral that was assigned the Port pin
via the Crossbar. To assign a Port pin only to /INT0 and/or /INT1, configure the Crossbar to skip the
selected pin(s). This is accomplished by setting the associated bit in register XBR0 (see Section
“20.3. Priority Crossbar Decoder” on page 124 for complete details on configuring the Crossbar).
IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flags for the /INT0 and /INT1 external
interrupts, respectively. If an /INT0 or /INT1 external interrupt is configured as edge-sensitive, the corre-
sponding interrup t-pending flag is automatically cle ared by the hardware whe n the CPU vectors to the ISR.
When configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as
defined by the corresponding polarity bit (IN0PL or IN1PL); the flag remains logic 0 while the input is inac-
tive. The external interrupt source must hold the input active until the interrupt request is recognized. It
must then deactivate the interrupt request before execution of the ISR completes or another interrupt
request will be generated.
IT0 IN0PL /INT0 Interrupt IT1 IN1PL /INT1 Interrupt
1 0 Active low, edge sensitive 1 0 Active low, edge sensitive
1 1 Active high, edge sensitive 1 1 Active high, edge sensitive
0 0 Active low, level sensitive 0 0 Active low, level sensitive
0 1 Active high, level sensitive 0 1 Active high, level sensitive
C8051F336/7/8/9
Rev.1.0 90
SFR Address = 0xE4
SFR Definition 15.5. IT01CF: INT0/INT1 Configuration
Bit76543210
Name IN1PL IN1SL[2:0] IN0PL IN0SL[2:0]
Type R/W R/W R/W R/W
Reset 00000001
Bit Name Function
7IN1PL
/INT1 Polarity.
0: /INT1 input is active low.
1: /INT1 input is active high.
6:4 IN1SL[2:0] /INT1 Port Pin Selection Bits.
These bits select which Port pin is assigned to /INT1. Note that this pin assignment is
independent of the Crossbar; /INT1 will monitor the assigned Port pin without disturb-
ing the peripheral that has been assigned the Port pin via the Crossbar. The Crossbar
will not assign the Port pin to a peripheral if it is configured to skip the selected pin.
000: Select P0.0
001: Select P0.1
010: Select P0.2
011: Select P0.3
100: Select P0.4
101: Select P0.5
110: Select P0.6
111: Select P0.7
3IN0PL
/INT0 Polarity.
0: /INT0 input is active low.
1: /INT0 input is active high.
2:0 IN0SL[2:0] /INT0 Port Pin Selection Bits.
These bits select which Port pin is assigned to /INT0. Note that this pin assignment is
independent of the Crossbar; /INT0 will monitor the assigned Port pin without disturb-
ing the peripheral that has been assigned the Port pin via the Crossbar. The Crossbar
will not assign the Port pin to a peripheral if it is configured to skip the selected pin.
000: Select P0.0
001: Select P0.1
010: Select P0.2
011: Select P0.3
100: Select P0.4
101: Select P0.5
110: Select P0.6
111: Select P0.7
C8051F336/7/8/9
Rev.1.0 91
16. Flash Memory
On-chip, re-programmable Flash memory is included for program code and non -volatile data storag e. The
Flash memory can be programmed in-system, a single byte at a time, through the C2 interface or by soft-
ware using the MOVX instruction. Once cleared to logic 0, a Flash bit must be erased to set it back to
logic 1. Flash bytes would typically be erased (set to 0xFF) before being reprogrammed. The write and
erase operations are automatically timed by hardware for proper execut ion; data polling to determine the
end of the write/erase operation is not required. Code execution is stalled during a Flash write/erase oper-
ation. Refer to Section “6. Electrical Characteristics” on page 27 for complete Flash memory electrical
characteristics.
16.1. Programming The Flash Memory
The simplest means of programming the Flash memory is through the C2 interface using programming
tools provided by Silicon Labs or a third party vendor. This is the only means for programming a non-initial-
ized device. For details on the C2 commands to program Flash memory, see Section “26. C2 Interface”
on page 221.
To ensure the integrity of Flash contents, it is strongly recommended that the on-chip VDD Monitor
be enabled in any system that includes code that writes and/or erases Flash memory from soft-
ware. See Section 16.4 for more details.
16.1.1. Flash Lock and Key Functions
Flash writes and erases by user software are protected with a lock and key function. The Flash Lock and
Key Register (FLKEY) must be written with the correct key codes, in sequence, before Flash operations
may be performed. The key codes are: 0xA5, 0xF1. The timing does not matter, but the codes must be
written in order. If the key codes are written out of order, or the wrong codes are written, Flash writes and
erases will be disabled until the next system reset. Flash writes and erases will also be disabled if a Flash
write or erase is attempted before the key codes have been written properly. The Flash lock resets after
each write or erase; the key codes must be written again before a following Flash operation can be per-
formed. The FLKEY register is detailed in SFR Definition 16.2.
16.1.2. Flash Erase Procedure
The Flash memory can be pr ogrammed by so ftware using the MOVX write instruction with the address and
data byte to be programmed provided as normal operands. Before writing to Flash memory using MOVX,
Flash write operations must be enabled by: (1) setting the PSWE Program Store Write Enable bit
(PSCTL.0) to logic 1 (this directs the MOVX writes to target Flash memory); and (2) Wr iting the Flash key
codes in sequence to the Flash Lock register (FLKEY). The PSWE bit remains set until cleared by soft-
ware.
A write to Flash memory can clear bits to logic 0 but cannot set them; only an erase operation can set bits
to logic 1 in Flash. A byte loc ation to be prog rammed should be erased befo re a new value is written.
The Flash memory is organized in 512-byte pages. The erase operation applies to an entire page (setting
all bytes in the page to 0xFF). To erase an entire 512-byte page, perform the following steps:
1. Disable interrupts (recommended).
2. Set thePSEE bit (register PSCTL).
3. Set the PSWE bit (register PSCTL).
4. Write the first key code to FLKEY: 0xA5.
5. Write the second key code to FLKEY: 0xF1.
6. Using the MOVX instruction, write a data byte to any location within the 512-byte page to be erased.
7. Clear the PSWE and PSEE bits.
C8051F336/7/8/9
92 Rev.1.0
16.1.3. Flash Write Procedure
Flash bytes are programmed by software with the following sequence:
1. Disable interrupts (recommended).
2. Erase the 512-byte Flash page containing the target location, as described in Section 16.1.2.
3. Set the PSWE bit (register PSCTL).
4. Clear the PSEE bit (register PSCTL).
5. Write the first key code to FLKEY: 0xA5.
6. Write the second key code to FLKEY: 0xF1.
7. Using the MOVX instruction, write a single data byte to the desired location within the 512-byte sector.
8. Clear the PSWE bit.
Steps 5–7 must b e repe at ed f or e ach b yt e t o be wr itte n . After Fl as h w rit es ar e co mp le te, PSWE should be
cleared so that MOVX instructions do not target program memory.
16.2. Non-volatile Data Storage
The Flash memory can be used for non-volatile data storage as well as program code. This allows data
such as calibration coefficients to be calculated and stored at run time. Data is written using the MOVX
write instruction and read using the MOVC instruction. Note: MOVX read instru ctions always t a rget XRAM.
C8051F336/7/8/9
Rev.1.0 93
16.3. Security Options
The CIP-51 provides security options to protect the Flash memory from inadvertent modification by soft-
ware as well as to prevent the viewing of proprietary program code and constants. The Program Store
Write Enable (bit PSWE in register PSCTL) and the Program Store Erase Enable (bit PSEE in register
PSCTL) bits protect the Flash memory from accidental modification by software. PSWE must be explicitly
set to ‘1’ before software can modify the Flash memory; both PSWE and PSEE must be set to ‘1’ before
software can erase Flash memory. Additional security features prevent proprietary program code and data
constants from being read or altered across the C2 interface.
A Security Lock Byte located in Flash user space offers protection of the Flash program memory from
access (reads, writes, or erases) by unprotected code or the C2 interface. See Section “13. Memory
Organization” on page 74 for the location of the security byte. The Flash security mechanism allows the
user to lock n 512-byte Flash pages, starting at page 0 (addresses 0x00 00 to 0x01 FF), where n is the 1’s
complement number represented by the Security Lock Byte. Note that the page containing the Flash
Security Lock Byte is unlocked when no other Flash pages are locked (all bits of the Lock Byte are
‘1’) and locked when any other Flash pages are locked (any bit of the Lock Byte is ‘0’). An example
is shown in Figure 16.1.
Figure 16.1. Security Byte Decoding
Security Lock Byte: 11111101b
1s Complement: 00000010b
Flash pages locked: 3 (First two Flash pages + Lock Byte Page)
C8051F336/7/8/9
94 Rev.1.0
The level of Flash security depends on the Flash access method. The three Flash access methods that
can be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing on
unlocked pages, an d user firmwar e executin g on lo cked pages. Table 16.1 summarizes th e Flash secur ity
features of the C8051F336/7/8/9 devices.
Table 16.1. Flash Security Summary
Action C2 Debug
Interface User Firmware executing fro m :
an unlocked page a locked page
Read, Write or Erase unlocked pages
(except page with Lock Byte) Permitted Permitted Permitted
Read, Write or Erase locked pages
(except page with Lock Byte) Not Permitted Flash Error Reset Permitted
Read or Write page containing Lock Byte
(if no pages are locked) Permitted Permitted Permitted
Read or Write page containing Lock Byte
(if any page is locked) Not Permitted Flash Error Reset Permitted
Read contents of Lock Byte
(if no pages are locked) Permitted Permitted Permitted
Read contents of Lock Byte
(if any page is locked) Not Permitted Flash Error Reset Permitted
Erase page containing Lock Byte
(if no pages are locked) Permitted Flash Error Reset Flash Error Reset
Erase page containing Lock Byte—Unlock all
pages (if any page is locked) C2 Device
Erase Only Flash Error Reset Flash Error Reset
Lock additional pages
(change '1's to '0's in the Lock Byte) Not Permitted Flash Error Reset Flash Error Reset
Unlock individual pages
(change '0's to '1's in the Lock Byte) Not Permitted Flash Error Reset Flash Error Reset
Read, Write or Erase Reserved Area Not Permitted Flash Error Reset Flash Error Reset
C2 Device Erase - Erases all Flash pages including the page containing the Lock Byte.
Flash Error Reset - Not permitted; Causes Flash Error Device Reset (FERROR bit in RSTSRC is '1' after
reset).
- All prohibited operations that are performed via the C2 interface are ignored (do not cause device reset).
- Locking any Flash page also locks the page containing the Lock Byte.
- Once written to, the Lock Byte cannot be modified except by performing a C2 Device Erase.
- If user code writes to the Lock Byte, the Lock does not take effect until the next device reset.
C8051F336/7/8/9
Rev.1.0 95
16.4. Flash Write and Erase Guidelines
Any system which contains routines which write or erase Flash memory from software involves some risk
that the write or erase routines will execute unintentionally if the CPU is operating outside its specified
operating ra nge of VDD, system clock frequency, or temperature. This accidental execution of Flash modi-
fying code can result in alteration of Flash memory contents causing a system failure that is only recover-
able by re-Flashing the code in the device.
The following guidelines are recommended for any system which contains routines which write or erase
Flash from code.
16.4.1. VDD Maintenance and the VDD monitor
1. If the system power supply is subject to voltage or current "spikes," add sufficient transient protection
devices to the power sup ply to ensure that the sup ply volt ag es listed in the Absolute M aximum Ratin gs
table are not exceeded.
2. Make certain that the minimum VDD rise time specification of 1 ms is met. If the system cannot meet
this rise time specification, then add an external VDD brownout circuit to the RST pin of the device that
holds the device in reset until VDD reaches 2.7 V and re-asserts RST if VDD drops below 2.7 V.
3. Enable the on-c hip VDD monitor and enable the VDD monitor as a reset source as early in code as
possible. This should be the first set of instructions executed after the Reset Vector. For 'C'-based
systems, this will involve modifying the startup code added by the 'C' compiler. See your compiler
documentatio n for more deta ils. Make certain th at there are no delays in sof tware between en abling the
VDD monitor and enabling the VDD monitor as a reset source. Code examples showing this can be
found in “AN201: Writing to Flash from Firmware", available from the Silicon Laboratories web site.
4. As an added precaution, explicitly enable the VDD monitor and enable the VDD monitor as a reset
source inside the functions that write and erase Flash memory. The VDD monitor enable instru ctions
should be placed just after the instruction to set PSWE to a '1', but before the Flash write or erase
operation instruction.
5. Make certain that all writes to the RSTSRC (Reset Sources) register use direct assignment operators
and explicitly DO NOT use the bit-wise operators (such as AND or OR). For exampl e, "RSTSRC =
0x02" is correct. "RSTSRC |= 0x02" is incorrect.
6. Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a ' 1'. Ar ea s to ch eck
are initialization code which enables other reset sources, such as the Missing Clock Detector or
Comparator , for example, and instructions which force a Software Reset. A global search on "RSTSRC"
can quickly verify this.
16.4.2. PSWE Maintenance
7. Reduce the number o f places in code where the PSWE bit (b0 in PSCTL) is set to a '1'. There should be
exactly one routine in code that sets PSWE to a '1' to write Flash bytes and one routine in code that
sets PSWE and PSEE both to a '1' to erase Flash pages.
8. Minimize the number of variable accesses while PSWE is set to a '1'. Handle pointer address updates
and loop variable main te na nc e ou tside the "PSWE = 1;... PS WE = 0;" area . Code exa m ple s showin g
this can be found in AN201, "Writing to Flash from Firmware", available from the Silicon Laboratories
web site.
9. Disable inter ru pts prior to set tin g PSWE to a '1' and leave them disabled until after PSWE has been
reset to '0'. Any interrupts posted during the Flash write or erase operation will be serviced in priority
order after the Flash operation has been completed and interrupts have been re-enabled by software.
10.Make certain th at the Flash write and erase pointer variables are not located in XRAM. See your
compiler documentation for instructions regarding how to explicitly locate variables in different memory
C8051F336/7/8/9
96 Rev.1.0
areas.
11.Add address boun ds checking to th e routines th at write or erase Flas h memory to ensu re that a r outine
called with an illegal address does not result in modification of the Flash.
16.4.3. System Clock
12.If operating from an external crystal, be advised that crystal performance is susceptible to electrical
interference and is sensitive to layout and to changes in temperature. If the system is oper ating in an
electrically noisy environment, use the internal oscillator or use an external CMOS clock.
13.If operating from the external oscillator, switch to the internal oscillator during Flash write or erase
operations. The external oscillator can continue to run, and the CPU can switch back to the external
oscillator after the Flash operation has completed.
Additional Flash recommendation s and example code ca n be found in AN201, "Writing to Flash from Firm-
ware", available from the Silicon Laboratories web site.
C8051F336/7/8/9
Rev.1.0 97
SFR Address = 0x8F
SFR Definition 16.1. PSCTL: Program Store R/W Control
Bit76543210
Name PSEE PSWE
Type RRRRRRR/WR/W
Reset 00000000
Bit Name Function
7:2 UNUSED Unused. Read = 000000b, Write = don’t care.
1 PSEE Program Store Erase Enable
Setting this bit (in combination with PSWE) allows an entire p age of Flash program
memory to be erased. If this bit is logic 1 and Flash writes are enabled (PSWE is logic
1), a write to Flash memory using the MOVX instruction will erase th e en tir e page that
conta ins the location addressed by the MOVX instruction. The value of the da ta byte
written does not matter.
0: Flash program memory erasure disabled.
1: Flash prog ra m memory eras ur e en ab le d.
0 PSWE Program Store Write Enable
Setting this bit allows writing a byte of data to the Flash program memory using the
MOVX write instruction. The Flash location should be erased before writing data.
0: Writes to Flash program memory disabled.
1: Writes to Flash program memory enabled; the MOVX write instruction targets Flash
memory.
C8051F336/7/8/9
98 Rev.1.0
SFR Address = 0xB7
SFR Definition 16.2. FLKEY: Flash Lock and Key
Bit76543210
Name FLKEY[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 FLKEY[7:0] Flash Lock and Key Register.
Write:
This register provides a lock and key function for Flash erasures and writes. Flash
writes and erases are enabled by writing 0xA5 followed by 0xF1 to the FLKEY regis-
ter. Flash writes and erases are automatically disable d after the next write or erase is
complete. If any writes to FLKEY are performed incorrectly, or if a Flash write or erase
operation is attempted while these operations are disabled, the Flash will be perma-
nently locked from writes or erasures until the next device reset. If an application
never writes to Flash, it can intentionally lock the Flash by writing a non-0xA5 value to
FLKEY from software.
Read:
When read, bits 1–0 indicate the current Flash lock state.
00: Flash is write/erase locked.
01: The first key code has been written (0xA5).
10: Flash is unlocked (writes/erases allowed).
11: Flash writ es /e ra se s disa ble d until th e ne xt re se t.
C8051F336/7/8/9
Rev.1.0 99
SFR Address = 0xB6
SFR Definition 16.3. FLSCL: Flash Scale
Bit76543210
Name FOSE Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 10000000
Bit Name Function
7FOSE
Flash One-shot Enable
This bit enables the Flash read one-shot (recommended). If the Flash one-shot is dis-
abled, the Flash sense amps are enabled for a full clock cycle during Flash reads,
increasing the device power consumption.
0: Flash one-sho t disabled.
1: Flash one-shot enabled.
6:0 Reserved Reserved. Must Write 0000000b.
C8051F336/7/8/9
Rev.1.0 100
17. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. Upon enterin g this
reset state, the following events occur:
CIP-51 halts program execution
Special Function Registers (SFRs) are initiali zed to their defined reset values
External Port pins are forced to a kn own state
Interrupts and timers are disabled.
All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal
data memory are unaffected during a reset; any previously stored data is preserved. However, since the
stack pointer SFR is reset, the stack is effectively lost, even though the data on the stack is not altered.
The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pullups are enabled
during and after the reset. For VDD Monitor an d power-on resets, the RST pin is driven low until the device
exits the re set state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the inter-
nal oscillator. The Watchdog Timer is enabled with the system clock divided by 12 as its clock source. Pro-
gram execution begins at location 0x0000.
Figure 17.1. Reset Sources
PCA
WDT
Missing
Clock
Detector
(one-
shot) (Software Reset)
System Reset
Reset
Funnel
Px.x
Px.x
EN SWRSF
System
Clock CIP-51
Microcontroller
Core
Extended Interrupt
Handler
EN
WDT
Enable
MCD
Enable
Errant
FLASH
Operation
/RST
(wired-OR)
Power On
Reset
'0'
+
-
Comparator 0
C0RSEF
VDD
+
-
Supply
Monitor
Enable
C8051F336/7/8/9
101 Rev.1.0
17.1. Power-On Reset
During power-up, the device is held in a reset state and the RST pin is driven low until VDD settles above
VRST. A delay occurs before the device is released from reset; the delay decreases as the VDD ramp time
increases (VDD ramp time is defined as how fast VDD ramps from 0 V to VRST). Figure 17.2. plots the
power-on and VDD monitor reset timing. The maximum VDD ramp time is 1 ms; slower ramp times may
cause the device to be released from reset before VDD reaches the VRST level. For ramp times less than
1 ms, the power-on reset delay (TPORDelay) is typically less than 0.3 ms.
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000) software can
read the PORSF flag to deter mine if a po we r- up wa s the cause of reset. The conten t of inter na l da ta mem-
ory should be assumed to be undefined after a power-on reset. The VDD monitor is enabled following a
power-on reset.
Figure 17.2. Power-On and VDD Monitor Reset Timing
Power-O n
Reset
VDD
Monitor
Reset
/RST
t
volts
1.0
2.0
Logic HIGH
Logic LOW TPORDelay
VDD
2.70
2.55 VRST
VDD
C8051F336/7/8/9
Rev.1.0 102
17.2. Power-Fail Reset / VDD Monitor
When a power-down transition or power irregularity causes VDD to drop below VRST, the power supply
monitor will drive the RST pin low and hold the CIP-51 in a re set stat e (see Figure 17.2). When VDD returns
to a level above VRST, the CIP-51 will be released from the reset state. Note that even though internal data
memory content s a re not altered by th e power-fail reset, it is impossible to determ ine if VDD dropped below
the level required for data retention. If the PORSF flag reads ‘1’, the data may no longer be valid. The VDD
monitor is enabled after power-on resets. Its defined state (enabled/disabled) is not altered by any other
reset source. For example, if the VDD monitor is disabled by code and a software reset is performed, the
VDD monitor will still be disabled after the reset.
Important Note: If the VDD monitor is being turned on from a disabled state, it should be enabled before it
is selected as a reset source. Selecting the VDD monitor as a reset source before it is enabled and stabi-
lized may cause a system reset. In some applications, this reset may be undesirable. If th is is not desirabl e
in the application, a delay should be introduced between enabling the monitor and selecting it as a reset
source. The procedure for enabling the VDD monitor and configuring it as a reset source from a disabled
state is shown below:
1. Enable the VDD monitor (VDMEN bit in VDM0CN = ‘1’).
2. If necessary, wait for the VDD monitor to stabilize.
3. Select the VDD monitor as a reset source (PORSF bit in RSTSRC = ‘1’).
See Figure 17.2 for VDD monitor timing; note that the power-on-reset delay is not incurred after a VDD
monitor reset. See Section “6. Electrical Characteristics” on page 27 for complete electrical character-
istics of the VDD monitor.
C8051F336/7/8/9
103 Rev.1.0
SFR Address = 0xFF
17.3. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-
ing an active-low signal on the RST pi n genera tes a reset; a n externa l pullup a nd/or de coupling o f th e RST
pin may be necessary to avoid erroneous noise-induced resets. See Section “6. Electrical Charac teris-
tics” on p age 27 for complete RST pin specifications. The PINRSF flag (RSTSRC.0) is set on exit from an
external rese t.
17.4. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is t riggered by the s yst em clock . If the syst em
clock remains high or low for more than 100 µs, the one-shot will time out and generate a reset. After a
MCD reset, the MCDRSF flag (RSTSRC.2) will read ‘1’, signifying the MCD as the reset source; otherwise,
this bit reads ‘0’. Writing a ‘1’ to the MCDRSF bit enables the Missing Clock Detector; writing a ‘0’ disables
it. The state of the RST pin is unaffected by this reset.
SFR Definition 17.1. VDM0CN: VDD Monitor Control
Bit7654321 0
Name VDMEN VDDSTAT
Type R/WRRRRRR R
Reset Varies Varies 0 0 0 0 0 0
Bit Name Function
7VDMEN
VDD Monitor Enable.
This bit turns the VDD monitor circuit on/off. The VDD Monitor cannot generate sys-
tem resets until it is also selected as a reset source in register RSTSRC (SFR Defi-
nition 17.2). Selecting the VDD monitor as a reset source before it has stabilized
may generate a system reset. In systems where this reset would be undesirable, a
delay should be introduced between enabling the VDD Monitor and selecting it as a
reset source.
0: VDD Monitor Disabled.
1: VDD Monitor Enabled.
6VDDSTAT
VDD Stat us .
This bit indicates the current power supply status (VDD Monitor output).
0: VDD is at or below the VDD monitor threshold.
1: VDD is above th e V DD monitor threshold.
5:0 UNUSED Unused. Read = 000000b; Write = Don’t care.
C8051F336/7/8/9
Rev.1.0 104
17.5. Comparator0 Reset
Comparator0 can be configured as a re set source by writing a ‘1’ to the C0RSEF flag (RSTSRC.5). Com-
parator0 should b e enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on chatter
on the output from gene rating an unwanted reset. The Comparator0 reset is active-low: if the non-inverting
input voltage (on CP0+) is less than the inverting input voltage (on CP0-), the device is put into the reset
state. Af ter a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read ‘1’ signifying Comparator0 as the
reset source; otherwise, this bit reads ‘0’. The state of the RST pin is unaffected by this reset.
17.6. PCA Watchdog Timer Reset
The programmable Watchdog Timer (WDT) function of the Programmable Counter Array (PCA) can be
used to prevent software from running out of control during a system malfunction. The PCA WDT function
can be enabled or disabled by software as described in Section “25.4. Watchdog Timer Mode” on
page 213; the WDT is enabled and clocked by SYSCLK / 12 following any reset. If a system malfunction
prevents user software from updating the WDT, a reset is generated and the WDTRSF bit (RSTSRC.5) is
set to ‘1’. The state of the RST pin is unaffected by this reset.
17.7. Flash Error Reset
If a Flash read/write/erase or program read targets an illegal address, a system reset is generated. This
may occur due to any of the following:
A Flash write or erase is attemp ted above u ser code sp ace. This occur s when PSWE is set to ‘1’ and a
MOVX write operation targets an address above address 0x3DFF.
A Flash read is attempted above user code space. This occurs when a MOVC operation targets an
address above address 0x3DFF.
A Program read is attempted above user code space. This occurs when user code attempts to branch
to an address above 0x3DFF.
A Flash read, write or erase attempt is restricted due to a Flash security setting (see Section
“16.3. Security Options” on page 93).
The FERROR bit (RSTSRC.6) is set following a Flash error reset. The st ate of the RST p in is unaf fected by
this reset.
17.8. Soft ware Reset
Software may force a reset by writing a ‘1’ to the SWRSF bit (RSTSRC.4). The SWRSF bit will read ‘1’ fol-
lowing a software forced reset. The st ate of the RST pin is unaffected by this reset.
C8051F336/7/8/9
105 Rev.1.0
SFR Address = 0xEF
SFR Definition 17.2. RSTSRC: Reset Source
Bit76543210
Name FERROR C0RSEF SWRSF WDTRSF MCDRSF PORSF PINRSF
Type R R R/W R/W R R/W R/W R
Reset 0 Varies Varies Varies Varies Varies Varies Varies
Bit Name Description Write Read
7 UNUSED Unused. Don’t care. 0
6FERROR
Flash Error Reset Flag. N/A Set to ‘1’ if Flash
read/write/erase error
caused the last reset.
5 C0RSEF C omparator0 Reset Enab le
and Flag. Writing a ‘1’ enables Com-
parator0 as a reset source
(active-low).
Set to ‘1’ if Comparator0
caused the last reset.
4SWRSF
Software Reset Force and
Flag. Writing a ‘1’ forces a sys-
tem reset. Set to ‘1’ if last reset was
caused by a write to
SWRSF.
3 WDTRSF Watchdog Timer Reset Flag. N/A Set to ‘1’ if Watchdog
T imer overflow caus ed the
last re set.
2 MCDRSF Missing Clock Detector
Enable and Flag. Writing a ‘1’ enables the
Missing Clock Detector.
The MCD triggers a reset
if a missing clock condition
is detected.
Set to ‘1’ if Missing Clock
Detector timeout caused
the last reset.
1PORSF
Power-On / VDD Monitor
Reset Flag, and VDD monitor
Reset Enable.
Writing a ‘1’ ena bles the
VDD monitor as a reset
source.
Writing ‘1’ to this bit
before the VDD monitor
is enabled and stabilized
may cause a system
reset.
Set to ‘1’ anytime a power-
on or VDD monitor reset
occurs.
When set to ‘1’ all other
RSTSRC flags are inde-
terminate.
0PINRSF
HW Pin Reset Fl ag . N/A Set to ‘1’ if RST pin
caused the last reset.
Note: Do not use read-modify-write operations on this register
C8051F336/7/8/9
Rev.1.0 106
18. Power Management Modes
The C8051 F336/7/8/ 9 device s have thr ee software pr ogrammab le power m anagem ent modes : Idle, Stop,
and Suspend. Idle mode and Stop mode are part of the standard 8051 architecture, while Suspend mode
is an enhanced power-saving mode implemented by the high-speed oscillator peripheral.
Idle mode halts the CPU while leaving the peripherals and clocks active. In Stop mode, the CPU is halted,
all interrupts and timers (except the Missing Clock Detector) are inactive, and the internal oscillator is
stopped (analog peripherals remain in their selected states; the external oscillator is not affected). Sus-
pend mode is similar to Stop mode in that the internal oscillator and CPU are halted, but the device can
wake on events such as a Port Mismatch, Comparator low output, or a Timer 3 overflow. Since clocks are
running in Idle mode, power consumption is dependent upon the system clock frequency and the number
of peripherals left in active mode before entering Idle. Stop mode and Suspend mode consume the least
power because the ma jority of the device is shut d own with no clocks active. SFR Definition 18.1 describes
the Power Control Register (PCON) used to control the C8051F336/7/8/9's Stop and Idle power manage-
ment modes. Suspend mode is controlled by the SUSPEND bit in the OSCICN register (SFR Definition
19.3).
Although the C8051F336/7/8 /9 has Idle, Stop, and Suspend modes available, more control over the device
power can be achieved by enabling/disabling individual peripherals as needed. Each analog peripheral
can be disabled when not in use and placed in low power mode. Digital peripherals, such as timers or
serial buses, draw little power when they are not in use. Tu rning off osc illators lowers power consumption
considerably, at the expense of reduced functionality.
18.1. Idle Mode
Setting the Idle Mode Select bit (PCON.0) causes the hardware to halt the CPU and enter Idle mode as
soon as the instruction that sets the bit completes execution. All internal registers and memory maintain
their original data. All analog and digital peripherals can remain active during Idle mode.
Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an
enabled interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume
operation. The pending interrupt will be serviced and the next instruction to be executed after the return
from interrupt (RETI) will be the instruction immediately following the one that set the Idle Mode Select bit.
If Idle mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence
and begins program execution at address 0x0000.
Note: If the instruction following the write of the IDLE bit is a single-byte instruction and an interrupt occurs
during the execution pha se of the instruction th at set s the IDLE bit, the CPU may not wake from Id le mod e
when a future interrupt occurs. Therefore, instructions that set the IDLE bit should be followed by an
instruction that has two or more opcode bytes, fo r example:
// in ‘C’:
PCON |= 0x01; // set IDLE bit
PCON = PCON; // ... followed by a 3-cycle dummy instruction
; in assembly:
ORL PCON, #01h ; set IDLE bit
MOV PCON, PCON ; ... followed by a 3-cycle dummy instruction
If enabled, the Watchdog T i mer (WDT) will eventually cause an internal watchdog reset and thereby termi-
nate the Idle mode. This featur e protect s the system from an unintended per manen t shut down in the event
of an inadvertent write to the PCON register. If this behavior is not desired, the WDT may be disabled by
C8051F336/7/8/9
107 Rev.1.0
softwar e prio r to en terin g th e Idle mo de if the WDT was initially configured to allow this operat ion. This pro-
vides the opportunity for additional power savings, allowing the system to remain in the Idle mode indefi-
nitely, waiting for an external stimulus to wake up the system. Refer to Section “17.6. PCA Watchdog
Timer Reset” o n page 1 04 for more information on the use and configuration of the WDT.
18.2. Stop Mode
Setting the Stop Mode Select bit (PCON.1) causes the controller core to enter Stop mode as soon as the
instruction that sets the bit completes execution. In Stop mode the internal oscillator, CPU, and all digital
peripherals are stopped; the state of the external oscillator circuit is not affected. Each analog peripheral
(including the external oscillator circuit) may be shut down individually prior to entering Stop Mode. Stop
mode can only be terminated by an internal or external reset. On reset, the device performs the normal
reset sequence and begins program execution at address 0x0000.
If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode.
The Missing Clock Dete ctor sho uld be d isabled if the CPU is to be put to in STOP mode for longer than th e
MCD timeout of 100 µs.
18.3. Suspend Mode
Setting the SUSPEND bit (OSCICN.5) causes the hardware to halt the CPU and the high-frequency inter-
nal oscillator, and go into Suspend mode as soon as the instruction that sets the bit completes execution.
All internal registers and memory maint ain their o riginal da t a. Most digit al p eriphera ls are n ot active in Sus-
pend mode. The exception to this is the Port Match feature and Timer 3, when it is run from an external
oscillator source or the internal low-frequency oscillator.
Suspend mode can be terminated by four types of events, a port match (described in Section “20.5. Port
Match” on page 129), a Timer 3 overflow (described in Section “24.3. Timer 3” on page 196), a Com-
parator low ou tp ut (i f enable d) , or a de vice r eset e vent. Note th at in or de r to run Timer 3 in Suspend mode,
the timer must be configured to clock from either the external clock source or the internal low-frequency
oscillator source. When Suspend mode is terminated, the device will continue execution on the instruction
following the one that set the SUSPEND bit. If the wake event (port match or Timer 3 overflow) was config-
ured to generate an interrupt, the interrupt will be serviced upon waking the device. If Suspend mode is ter-
minated by an internal or external reset, the CIP-51 performs a normal reset sequence and begins
program execution at address 0x0000.
C8051F336/7/8/9
Rev.1.0 108
SFR Address = 0x87
SFR Definition 18.1. PCON: Power Control
Bit76543210
Name GF[5:0] STOP IDLE
Type R/W R/W R/W
Reset 00000000
Bit Name Function
7:2 GF[5:0] General Purpose Flags 5–0.
These are general purpose flags for use under software control.
1STOP
Stop Mode Select.
Setting this bit will place the CIP-51 in Stop mode. This bit will always be read as 0.
1: CPU goes into Stop mode (internal oscillator stopped).
0IDLE
IDLE: Idle Mode Select.
Setting this bit will place the CIP-51 in Idle mode. This bit will always be read as 0.
1: CPU goes into Idle mode. (Shuts off clock to CPU, but clock to Timers, Interrupts,
Serial Ports, and Analog Peripherals are still active.)
C8051F336/7/8/9
Rev.1.0 109
19. Oscillators and Clock Selection
C8051F336/7/8/9 devices include a programmable internal high-frequency oscillator, a programmable
internal low-frequency oscillator, and an external oscillator drive circuit. The internal high-frequency oscilla-
tor can be enabled/disabled and calibrated using the OSCICN and OSCICL registers, as shown in
Figure 19.1. The internal low-frequency oscillator can be enabled/disabled and calibrated using the
OSCLCN register . The system clock can be sourced by the external oscillator circuit or either internal oscil-
lator. Both internal oscillators offer a selectable post-scaling feature.
Figure 19.1. Oscillator Options
19.1. System Clock Selection
The CLKSL[1:0] bits in register CLKSEL select which oscillator source is used as the system clock.
CLKSL[1:0] must be set to 01b for the system clock to run from the external oscillator; however the exter-
nal oscillator may still clock certain peripherals (timers, PCA) when the internal oscillator is selected as the
system clock. The system clock may be switched on-the-fly between the internal oscillator, external oscilla-
tor, and Clock Multiplier so long as the selected clock source is enabled and has settled.
The internal high-frequency and low-frequency oscillators require little start-up time and may be selected
as the system clock immediately fo llowing the register write which enables the oscillator. The external RC
and C modes also typically require no startup time.
External crystals and ceramic resonators however, t ypically require a start-up time befo re they are s ettled
and ready for use. The Crystal Valid Flag (XTLVLD in register OSCXCN) is set to '1' by hardware when the
external crystal or ceramic resonator is settled. In crystal mode, to avoid reading a false XTLVLD, soft-
ware should delay at least 1 ms between enabling the external oscillator and checking XTLVLD.
OSC
Programmable
Internal Clock
Generator
Input
Circuit
EN
SYSCLK
n
OSCICL OSCICN
IOSCEN
IFRDY
IFCN1
IFCN0
XTAL1
XTAL2
Option 2
VDD
XTAL2
Option 1
10MΩ
Option 3
XTAL2
Option 4
XTAL2
OSCXCN
XTLVLD
XOSCMD2
XOSCMD1
XOSCMD0
XFCN2
XFCN1
XFCN0
CLKSEL
SEL1
SEL0
OSCLCN
OSCLEN
OSCLRDY
OSCLF3
OSCLF2
OSCLF1
OSCLF0
OSCLD1
OSCLD0
Low Frequency
Oscillator
EN n
OSCLD
OSCLF
OSCLF OSCLD
C8051F336/7/8/9
110 Rev.1.0
SFR Address = 0xA9
SFR Definition 19.1. CLKSEL: Clock Select
Bit76543210
Name CLKSL[1:0]
Type RRRRRR R/W
Reset 00000000
Bit Name Function
7:2 UNUSED Unused. Read = 000000b; W rite = Don’t Care
1:0 CLKSL[1:0] Syst em Clo c k Sour c e Selec t Bits.
00: SYSCLK derived from the Internal High-Frequency Oscillator and scaled per the
IFCN bits in register OSCICN.
01: SYSCLK derived from the External Oscillator circuit.
10: SYSCLK derived from the Internal Low-Frequency Oscillator and scaled per the
OSCLD bits in register OSCLCN.
11: reserved.
C8051F336/7/8/9
Rev.1.0 111
19.2. Programmable Internal High-Frequency (H-F) Oscillator
All C8051F336/7/8/9 devices include a programmable internal high-frequency oscillator that defaults as
the system clock after a system reset. The internal oscillator period caPara1n be adjusted via the OSCICL
register as defined by SFR Definition 19.2.
On C8051F336/7/8/9 devices, OSCICL is factory calibrated to obtain a 24.5 MHz base frequency.
The system clock may be derived from the programmed internal oscillator divided by 1, 2, 4, or 8, as
defined by the IFCN bits in register OSCICN. The divide value defaults to 8 following a reset.
19.2.1. Internal Oscillator Suspend Mode
When software writes a logic 1 to SUSPEND (OSCICN.5), the internal oscillator is suspended. If the sys-
tem clock is derived from the internal oscillator, the input clock to the peripheral or CIP-51 will be stopped
until one of the following events occur:
Port 0 Match Even t.
Port 1 Match Even t.
Comparator 0 enabled and output is logic 0.
Timer3 Overflow Event.
When one of the oscillator awakening events occur, the internal oscillator, CIP-51, and affe cted peripherals
resume normal operation, regardless of whether the event also causes an interrupt. The CPU resumes
execution at the instruction following the write to SUSPEND.
SFR Address = 0xB3
SFR Definition 19.2. OSCICL: Internal H-F Oscillator Calibration
Bit76543210
Name OSCICL[6:0]
Type RR/W
Reset 0 Varies Varies Varies Varies Varies Varies Varies
Bit Name Function
7 Unused Unused. Read = 0; Write = Don’t Care
6:0 OSCICL[6:0] Internal Oscillator Calibration Bits.
These bits determine the internal oscillator period. When set to 0000000b, the H-F
oscillator operates at its fastest setting. When set to 1111111b, the H-F oscillator
operates at its slowest setting. The reset value is factory calibrated to generate an
internal oscillator frequency of 24.5 MHz.
C8051F336/7/8/9
112 Rev.1.0
SFR Address = 0xB2
SFR Definition 19.3. OSCICN: Internal H-F Oscillator Control
Bit765 43210
Name IOSCEN IFRDY SUSPEND STSYNC IFCN[1:0]
Type R/W R R/W R R R R/W
Reset 11000000
Bit Name Function
7IOSCEN
Internal H-F Oscillator Enab le Bit.
0: Internal H-F Oscillator Disabled.
1: Internal H-F Oscillator Enabled.
6IFRDY
Internal H-F Oscillator Frequency Ready Flag.
0: Internal H-F Oscillator is not running at programmed frequency.
1: Internal H-F Oscillator is running at programmed frequency.
5 SUSPEND Internal Oscillator Suspend Enable Bit.
Setting this bit to logic 1 places the internal oscillator in SUSPEND mode. The inter-
nal oscillator resumes operation when one of the SUSPEND mode awakening
events occurs.
4 STSYNC Suspend Timer Synchronization Bit.
This bit is used to indicate when it is safe to read and write the registers associated
with the suspend wake-up timer. If a suspend wake-up source other than the timer
has brought the oscillator out of suspend mode, it may take up to three timer clocks
before the timer can be read or written. When STSYNC r eads '1', reads a nd writes of
the timer register should not be performed. When STSYNC reads '0', it is safe to
read and write the timer registers.
3:2 Unused Unused. Read = 00b; Write = Don’t Care
1:0 IFCN[1:0] Internal H-F Oscillator Frequency Divider Control Bits.
00: SYSCLK derived from Internal H-F Oscillator divided by 8.
01: SYSCLK derived from Internal H-F Oscillator divided by 4.
10: SYSCLK derived from Internal H-F Oscillator divided by 2.
11: SYSCLK derived from Internal H-F Oscillator divided by 1.
C8051F336/7/8/9
Rev.1.0 113
19.3. Programmable Internal Low-Frequency (L-F) Oscillator
All C8051F336/7/8/9 devices include a programmable low-frequency internal oscillator, which is calibrated
to a nominal frequency of 80 kHz. The low-frequency oscillator circuit includes a divider that can be
changed to divide the clock by 1, 2, 4, or 8, using the OSCLD bits in the OSCLCN register (see SFR Defi-
nition 19.4). Additionally, the OSCLF[3:0] bits can be used to adjust the oscillator’s output frequency.
19.3.1. Calibrating the Internal L-F Oscillator
Timers 2 and 3 include capture functions that can be used to capture the oscillator frequency, when run-
ning from a known time base. When either Timer 2 or Timer 3 is configured for L-F Oscillator Capture
Mode, a falling edge (Timer 2) or rising edge (Timer 3) of the low-frequency oscillator’s output will cause a
capture event on the corresponding timer. As a capture event occurs, the current timer value
(TMRnH:TMRnL) is copied into the timer reload registers (TMRnRLH:TMRnRLL). By recording the diff er-
ence between two successive timer capture values, the low-frequency oscillator’s period can be calcu-
lated. The OSCLF bits can then be adjusted to produce the desired oscillator frequency.
SFR Address = 0xE3
SFR Definition 19.4. OSCLCN: Internal L-F Oscillator Control
Bit76543210
Name OSCLEN OSCLRDY OSCLF[3:0] OSCLD[1:0]
Type R/W R R.W R/W
Reset 0 0 Varies Varies Varies Varies 0 0
Bit Name Function
7OSCLEN
Internal L-F Oscillator Enable.
0: Internal L-F Oscillator Disabled.
1: Internal L-F Oscillator Enabled.
6OSCLRDY
Internal L-F Oscillator Ready.
0: Internal L-F Oscillator frequency not stabilized.
1: Internal L-F Oscillator frequency stabilized.
Note: OSCLRDY is only set back to 0 in the event of a device reset or a change to the
OSCLD[1:0] bits.
5:2 OSCLF[3:0] Internal L-F Oscillator Frequency Control Bits.
Fine-tune control bits for the Internal L-F oscillator frequency. When set to 0000b, the
L-F oscillator operates at its fastest setting. When set to 1111b, the L-F oscillator
operates at its slowest setting.
1:0 OSCLD[1:0] Internal L-F Oscillator Divider Select.
00: Divide by 8 selected.
01: Divide by 4 selected.
10: Divide by 2 selected.
11: Divide by 1 selected.
C8051F336/7/8/9
114 Rev.1.0
C8051F336/7/8/9
Rev.1.0 114
19.4. External Oscillator Drive Circuit
The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor, or RC network. A
CMOS clock may also provide a clock input. For a crystal or ceramic resonator configuration, the crys-
tal/resonator must be wired across the XTAL1 and XTAL2 pins as shown in Option 1 of Figure 19.1. A
10 MΩ resistor also must be wired across the XTAL2 and XTAL1 pins for the crystal/resonator configura-
tion. In RC, capacitor, or CMOS clock configuration, the clock source should be wired to the XTAL2 pin as
shown in Option 2, 3, or 4 of Figure 19.1. The type of external oscillator must be selected in the OSCX CN
register, and the frequency control bits (XFCN) must be selected appropriately (see SFR Definition 19.5).
Important Note on External Oscillator Usage: Port pins must be configured when using the external
oscillator circuit. When the external oscillator drive circuit is enabled in crystal/resonator mode, Port pins
P0.2 and P0.3 are used as XTAL1 and XTAL2 respectively. When the external oscillator drive circuit is
enabled in capacitor, RC, or CMOS clock mode, Port pin P0.3 is used as XTAL2. The Port I/O Crossbar
should be configured to skip the Port pins used by the oscillator circuit; see Section “20.3. Priority Cross-
bar Decoder” on page 124 for Crossbar configuration. Additionally, when using the external oscillator cir-
cuit in crystal/resonator, capacitor, or RC mode, the associated Port pins should be configured as analog
inputs. In CMOS clock mode, the associated pin should be configured as a digital input. See Section
“20.4. Port I/O Initialization” on page 126 for details on Port input mode selection.
C8051F336/7/8/9
115 Rev.1.0
SFR Address = 0xB1
SFR Definition 19.5. OSCXCN: External Oscillator Control
Bit76543210
Name XTLVLD XOSCMD[2:0] XFCN[2:0]
Type RR/WRR/W
Reset 00000000
Bit Name Function
7XTLVLD
Crystal Oscillator Valid Flag.
(Read only when XOSCMD = 11x.)
0: Crystal Oscillator is unused or not yet stable.
1: Crystal Oscillator is running and stable.
6:4 XOSCMD[2:0] External Oscillator Mode Select.
00x: External Oscillator circuit off.
010: External CMOS Clock Mode.
011: External CMOS Clock Mode with divide by 2 stage.
100: RC Oscillator Mode.
101: Capacitor Oscillator Mode.
110: Crystal Oscillator Mode.
111: Crystal Oscillator Mode with divide by 2 stage.
3 UNUSED Read = 0; Write = Don’t Care
2:0 XFCN[2:0] External Oscillator Frequency Control Bits.
Set according to the desired frequency for Crystal or RC mode.
Set according to the desired K Factor for C mo de.
XFCN Crystal Mode RC Mode C Mode
000 f ≤ 32 kHz f ≤ 25 kHz K Factor = 0.87
001 32 kHz < f ≤ 84 kHz 25 kHz < f ≤ 50 kHz K Factor = 2.6
010 84 kHz < f ≤ 225 kHz 50 kHz < f ≤ 100 kHz K Factor = 7.7
011 225 kHz < f ≤ 590 kHz 1 00 kHz < f ≤ 200 kHz K Factor = 22
100 590 kHz < f ≤ 1.5 MHz 200 kHz < f ≤ 400 kHz K Factor = 65
101 1.5 MHz < f ≤ 4 MHz 400 kHz < f ≤ 800 kHz K Factor = 180
110 4 MHz < f ≤ 10 MHz 800 kHz < f ≤ 1.6 MHz K Factor = 664
111 10 MHz < f ≤ 30 MHz 1.6 MHz < f ≤ 3.2 MHz K Factor = 1590
C8051F336/7/8/9
Rev.1.0 116
19.4.1. External Crysta l Example
If a crystal or ceramic resonator is used as an external oscillator source for the MCU, the circuit should be
configured as shown in Figure 19.1, Option 1. The External Oscillator Frequency Control value (XFCN)
should be chosen from the Crystal column of the table in SFR Definition 19.5 (OSCXCN register). For
example, an 11.0592 MHz crystal requires an XFCN setting of 111b and a 32.768 kHz Watch Crystal
requires an XFCN setting of 001b. After an external 32.768 kHz oscillator is stabilized, the XFCN setting
can be switched to 000 to save power. It is recommended to enable the missing clock detector before
switching the system clock to any external oscillator source.
When the crystal oscillator is first enabled, the oscillator amplitude detection circ uit requires a s ettling time
to achieve proper bias. Introducing a delay of 1 ms between enabling the oscillator and checking the
XTLVLD bit will prevent a premature switch to the external oscillator as the system clock. Switching to the
external oscillator before the crystal oscillator has stabilized can result in unpredictable behavior. The rec-
ommended procedure is:
1. Force XTAL1 and XTAL2 to a low state. This involves enabling the Crossbar and writing ‘0’ to the port
pins associated with XTAL1 and XTAL2.
2. Configure XTAL1 and XTAL2 as analog inputs using.
3. Enable the external oscillator.
4. Wait at least 1 ms.
5. Poll for XTLVLD => ‘1’.
6. Enable the Missing Cl oc k Dete ct or.
7. Switch the system clock to the external oscillator.
Important Note on External Crystals: Crystal oscillator circuits are quite sensitive to PCB layout. The
crystal should be placed as close as possible to the XTAL pins on the device. The traces should be as
short as possible and shielded with ground plane from any other traces which could introduce noise or
interference.
The capacitors shown in the external crystal configuration provide the load capacitance required by the
crystal for correct oscillation. These capacitors are "in series" as seen by the crystal and "in parallel" with
the stray capacitance of the XTAL1 and XTAL2 pins.
Note: The desired load capacitance depends upon the crystal and the manufacturer. Please refer to the
crystal data sheet when completing these calculations.
For examp le, a tun ing-fo rk crystal of 32 .768 kHz with a recommended load capacitance of 12.5 pF should
use the configuration shown in Figur e 19.1, Option 1. The to tal val ue of the cap acitors and the stray cap ac-
itance of the XTAL pins should equal 25 pF. With a stray capa citance of 3 pF per pin, the 22 pF capacitors
yield an equivalent capacitance of 12.5 pF across the crysta l, as shown in Figure 19.2.
C8051F336/7/8/9
117 Rev.1.0
Figure 19.2. External 32.768 kHz Quartz Cryst al Oscillator Connection Diagram
19.4.2. External RC Example
If an RC network is used as an external oscillator source for the MCU, the circ uit should be configured as
shown in Figure 19.1, Option 2. The capacitor should be no greater than 100 pF; however for very small
capacitors, the total capacitance may be dominated by parasitic capacitance in the PCB layout. To deter-
mine the required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, first
select the RC network value to produce the desired frequency of oscillation, according to Equation 19.1,
where f = the frequency of oscillation in MHz, C = the capacitor value in pF, and R = the pull-up resistor
value in kΩ.
Equation 19.1. RC Mode Oscillator Frequency
For example: If the frequency desired is 100 kHz, let R = 246 kΩ and C = 50 pF:
f = 1.23( 103 ) / RC = 1.23 ( 103 ) / [ 246 x 50 ] = 0.1 MHz = 100 kHz
Referring to the table in SFR Definition 19.5, the required XFCN setting is 010b.
XTAL1
XTAL2
10MΩ
22pF*22pF* 32.768 kHz
* Capacitor values depend on
crystal specification s
f1.23 103
×RC×()⁄=
C8051F336/7/8/9
Rev.1.0 118
19.4.3. External Capacitor Example
If a capacitor is used as an external oscillator for the MCU, the circuit should be configured as shown in
Figure 19.1, Option 3. The capacitor should be no greater than 100 pF; however for very small capacitors,
the total capacitance may be dominated by parasitic capacitance in the PCB layout. To determine the
required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, select the capaci-
tor to be used and find the frequency of oscillation ac cording to Equation 19.2, where f = the frequency of
oscillation in MHz, C = the capacitor value in pF, and VDD = the MCU power supply in Volts.
Equation 19.2. C Mode Oscillator Frequency
For example: Assume VDD = 3.0 V and f = 150 kHz:
f = KF / (C x VDD)
0.150 MHz = KF / (C x 3.0)
Since the frequency of roughly 150 kHz is d esired, select the K Factor from the tab le in SFR Definition 19.5
(OSCXCN) as KF = 22:
0.150 MHz = 22 / (C x 3.0)
C x 3.0 = 22 / 0.150 MHz
C = 146.6 / 3.0 pF = 48.8 pF
Therefore, the XFCN value to use in this example is 011b and C = 50 pF.
fKF()RV
DD
×()⁄=
C8051F336/7/8/9
Rev.1.0 119
20. Port Input/Output
Digital and analog resources are available through 17 (C8051F336/7) or 21 (C8051F3 38/9) I/O pins. Port
pins P0.0-P2.3 can be defined as general-purpose I/O (GPIO), assigned to one of the internal digital
resources, or assigned to an analog function as shown in Figure 20.4. Port pin P2.4 on the C8051F338/9
and P2.0 on the C8051F336/7 can be used as GPIO and are shared with the C2 Interface Data signal
(C2D). The desig ner has complete control over which functions are assigned, limited only by the number of
physical I/O pins. This resource assignment flexibility is achieved through the use of a Priority Crossbar
Decoder. Note that the state of a Port I/O pin can always be read in the corresponding Port latch, regard-
less of the Crossbar settings.
The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder
(Figure 20.4 and Figure 20.5). The registers XBR0 and XBR1, defined in SFR Definition 20.1 and SFR
Definition 20.2, are used to select internal digital functions.
All Port I/Os are 5 V tolerant (refer to Figure 20.2 for the Port cell circ uit ). T h e Por t I/ O c ells ar e c on fig ur ed
as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,1). Complete
Electrical Specif ica tio ns fo r Por t I/O are given in Section “6. Electrical Characteristics” on page 27.
Figure 20.1. Port I/O Functional Block Diagram
XBR0, XBR1,
PnSKIP Registers
Digital
Crossbar
Priority
Decoder
2
P0
I/O
Cells
P0.0
P0.7
8
Port M a tc h
P0MASK, P0MAT
P1MASK, P1MAT
UART
(Internal D igital S ignals)
Highest
Priority
Lowest
Priority
SYSCLK
2
SMBus
T0, T1 2
4
PCA
2
CP0
Outputs
SPI 4
P1
I/O
Cells
P1.0
8
(P o r t L atc h e s )
P0 (P0.0-P0.7)
(P1.0-P1.7)
8
8
P1
P2
I/O
Cell
P2 (P2.0-P2.3*)
4
4
PnMDOUT,
P n MD IN Regis te rs
P1.7
P2.0*
P2.3*
To Analog Peripherals
(ADC0, CP0, VREF, XTAL)
External Interrupts
EX0 and EX1
*P2.0-P2.3 are only available through
the crossbar on QFN 24 Packages.
C8051F336/7/8/9
120 Rev.1.0
20.1. Port I/O Modes of Operation
Port pins P0.0 - P2.3 use the Port I/O cell shown in Figure 20.2. Each Port I/O cell can be configured by
software for analog I/O or digital I/O using the PnMDIN registers. On reset, all Port I/O cells default to a
high impedance state with weak pull-ups enabled. Until the crossbar is enabled (XBARE = ‘1’), both the
high and low port I/O drive circuits are explicitly disabled on all crossbar pins.
20.1.1. Port Pins Configured for Analog I/O
Any pins to be used as Comparator or ADC input, external oscillator input/output, VREF, or IDAC output
should be configured for an alog I/O (PnMDIN.n = ‘1’). When a p in is configured for anal og I/O, its weak pul-
lup, digital driver, and digital receiver are disabled. Port pins configured for analog I/O will always read
back a value of ‘0’.
Configuring pins as analog I/O saves power and isolates the Port pin from digital interference. Port pins
configured as digital I/O may still be used by analog peripherals; however, this practice is not recom-
mended and may result in measurement errors.
20.1.2. Port Pins Configured For Digital I/O
Any pins to be used by digital peripherals (UART, SPI, SMBus, etc.), external event trigger fu nctions, or as
GPIO should be configured as digital I/O (PnMDIN.n = ‘1’). For digital I/O pins, one of two output modes
(push-pull or open-drain) must be selected using the PnMDOUT registers.
Push-pull outputs (PnMDOUT.n = ‘1’) drive the Port pad to the VDD or GND supply rails based on the out-
put logic value of the Port pin. Open-drain outputs have the high side driv er disabled; ther efore, they only
drive the Port pad to GND when the output logic value is ‘0’ and become high impedance inputs (b oth high
low drivers turned off) when the output logic value is ‘1’.
When a digit a l I/O cell is placed in th e hi gh imped an ce state, a weak pull-up transistor pulls the Port pad to
the VDD supply voltage to ensure the digital input is at a defined logic state. Weak pull-ups are disabled
when the I/O cell is driven to GND to minimize power consumption, and they may be globally disabled by
setting WEAKPUD to ‘1’. The user should ensure that digital I/O are always internally or externally pulled
or driven to a valid logic state to minimize power consumption. Port pins configured for digital I/O always
read back the logic state of the Port pad, regardless of the output logic value of the Port pin.
C8051F336/7/8/9
Rev.1.0 121
Figure 20.2. Port I/O Cell Block Diagram
20.1.3. Interfacing Port I/O to 5V Logic
All Port I/O configured for digit al, open-drain o peration are cap able of interfacing to digit al logic operating at
a supply voltage higher than VDD and less than 5.25V. An external pull-up resistor to the higher supply
voltage is typically required for most systems.
Import ant No te: In a multi-voltage interface, the external pull-up resistor should be sized to allow a current
of at least 150uA to flow into the Port pin when the supply voltage is between (VDD + 0.6V) and
(VDD + 1.0V). Once the Port pin voltage increases beyond this range, the current flowing into the Port pin
is minimal. Figure 20.3 shows the input current characteristics of port pins driven above VDD. The port pin
requires 150 µA peak overdrive current when its voltage reaches approximately (VDD + 0.7 V).
Figure 20.3. Port I/O Overdrive Current
GND
VDD VDD
(WEAK)
PORT
PAD
To/From Analog
Peripheral
PxMDIN.x
(1 for digital)
(0 for analog)
Px.x – Output
Logic Value
(Port Latch or
Crossbar)
XBARE
(Crossbar
Enable)
Px.x – Input Logic Value
(Reads 0 when pin is configured as an analog I/O)
PxMDOUT.x
(1 for push-pull)
(0 for open-drain)
WEAKPUD
(Weak Pull-Up Disable)
+
-Vtest
IVtest
VDD
IVtest
(µA)
Vtest (V)
0
-10
-150
VDD VDD+0.7
I/O
Cell
Port I/O Overdrive Current vs. VoltagePort I/O Overdrive Test Circuit
C8051F336/7/8/9
122 Rev.1.0
20.2. Assigning Port I/O Pins to Analog and Digital Functions
Port I/O pins P0.0 - P2.3 can be assigned to various analog, digital, and external interrupt functions. The
Port pins assigned to analog functions should be configured for analog I/O, and Port pins assigned to
digital or external interrupt functions should be config ured for digital I/O.
20.2.1. Assigning Port I/O Pins to Analog Functions
Table 20.1 shows all available analog functions that require Port I/O assignments. Port pins selected for
these analog functions should have their corresponding bit in PnSKIP set to ‘1’. This reserves the
pin for use by the analog function and does not allow it to be claimed by the Crossbar. Table 20.1 shows
the potential mapping of Port I/O to each analog function.
20.2.2. Assigning Port I/O Pins to Digital Functions
Any Port pins not assigned to analog functions may be assigned to digital functions or used as GPIO. Most
digital functions rely on the Crossbar for pin assignment; however, some digital functions bypass the
Crossbar in a manner similar to the analog functions listed above. Port pins used by these digital
functions and any Port pins selected for use as GPIO should have their corresponding bit in
PnSKIP set to ‘1’. Table 20.2 shows all available digital functions and the potential mapping of Port I/O to
each digital fu nction.
Table 20.1. Port I/O Assignment for Analog Functions
Analog Function Potentially Assignable
Port Pins SFR(s) used for
Assignment
ADC Input P0.0 - P2.3 AMX0P, AMX0N,
PnSKIP, PnMDIN
Comparator0 Input P0.0 - P2.3 CPT0MX, PnSKIP,
PnMDIN
Voltage Reference (VREF0) P0.0 REF0CN, PnSKIP,
PnMDIN
Current DAC Output (IDA0) P0.1 IDA0CN, PnSKIP,
PnMDIN
External Oscillator in Crystal Mode (XTAL1) P0.2 OSCXCN, PnSKIP,
PnMDIN
External Oscillator in RC, C, or Crystal Mode (XTAL2) P0.3 OSCXCN, PnSKIP,
PnMDIN
Table 20.2. Port I/O Assignment for Digital Functions
Digital Function Potentially Assignable Port Pins SFR(s) used for
Assignment
UART0, SPI0, SMBus, CP0,
CP0A, SYSCLK, PCA0
(CEX0-2 and ECI) , T0 or T1 .
Any Port pin available for assignment by the
Crossbar. This includes P0.0 - P2.3 pins which
have their PnSKIP bit set to ‘0’.
Note: The Crossbar will always assign UART0
pins to P0.4 and P0.5.
XBR0, XBR1
Any pin used for GPIO P0.0 - P2.4 P0SKIP, P1SKIP,
P2SKIP
C8051F336/7/8/9
Rev.1.0 123
20.2.3. Assigning Port I/O Pins to External Event Trigger Functions
External event trigger functions can be used to trigger an interrupt or wake the device from a low power
mode when a transition occurs on a digital I/O pin. The event trigger functions do not require dedicated
pins and will function on both GPIO pins (PnSKIP = ’1’) and pins in use by the Crossbar (PnSKIP = ‘0’).
External event trigger functions cannot be used on pins configured for analog I/O. Table 20.3 shows all
available external event trigger functions.
Table 20.3. Port I/O Assignment for External Event Trigger Functions
Event Trigger Function Potentially Assignable Port Pins SFR(s) used for
Assignment
External Interrupt 0 P0.0 - P0.7 IT01CF
External Interrupt 1 P0.0 - P0.7 IT01CF
Port Match P0.0 - P1.7 P0MASK, P0MAT
P1MASK, P1MAT
C8051F336/7/8/9
124 Rev.1.0
20.3. Priority Crossbar Decoder
The Priority Crossbar Decoder (Figure 20.4) assigns a priority to each I/O function, starting at the top with
UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that
resource (excluding UART0, which is always at pins 4 and 5). If a Port pin is assigned, the Crossbar skips
that pin when assigning the next selected resource. Additionally, the Crossbar will skip Port pins whose
associated bits in the PnSKIP registers are set. The PnSKIP registers allow software to skip Port pins that
are to be used for analog input, dedicated functions, or GPIO.
Important Note on Crossbar Configuration: If a Port pin is claimed by a peripheral without use of the
Crossbar, its corresponding PnSKIP bit should be set. This applies to P0.0 if VREF is used, P0.3 and/or
P0.2 if the external oscillator circuit is enabled, P0.6 if the ADC or IDAC is configur ed to use the external
conversion start signal (CNVSTR), and any selected ADC or Comparator inputs. The Crossbar skips
selected pins as if they were already assigned, and moves to the next unassigned pin.
Figure 20.4 shows all of the potential peripheral-to-pin assignments available to the crossbar. Note that
this does not mean any peripheral can always be assigned to the highlighted pins. The actual pin assign-
ments ar e determined by the priority of the en abled peripherals.
Figure 20.4. Crossbar Priority Decoder - Possible Pin Assignments
V
RE
F
IDA x1 x2 CNVSTR
01234567012345670
1
2
2
2
3
2
4
2
SYSCLK
CEX0
CEX1
CEX2
ECI
Notes:
1. NSS is only pinned out i n 4-wire S PI M ode
2. Pins P2.1-P2.4 onl y on QF N24 P ack age
3. Pin 2. 0 unavailabl e on cros sbar i n Q F N20 P ack age
SDA
SCL
P0 P1
S pecial F uncti on S i gnal s are not assigned by the cros sbar.
When these s i gnal s are enabled, the Cros sbar must be
manual l y c onfigured to skip thei r correspondi ng p ort pins.
P ort pi n pot ent i al l y ava il abl e t o peri pheral
SF Signals
T1
P2
P in n o t availabl e fo r cr o ssbar p eripher als.
CP0A
T0
TX0
CP0
RX0
SF Signals
PIN I/O
NSS1
SCK
MISO
MOSI
C8051F336/7/8/9
Rev.1.0 125
Registers XBR0 and XBR1 are used to assign the digital I/O resources to the physical I/O Port pins. Note
that when the SMBus is selected, the Crossbar assigns both pins associated with the SMBus (SDA and
SCL); when the UAR T is selected, the Crossbar assign s both pins associated with the UART (TX and RX).
UART0 pin assignments are fixed for bootloading purposes: UART TX0 is always assigned to P0.4; UART
RX0 is always assigned to P0.5. Standard Port I/Os appear contiguously after the prioritized functions
have been assigned.
Figure 20.5 shows an example of the resulting pin assignments of the device with UART0, SMBus, and
CEX0 enabled, th e XTAL 1 (P0.2) and XTAL2 (P0.3) pins skipp ed (P0SK IP = 0x0C). UART0 is the highest
priority and it will be assigned first. The UART can only appear on P0.4 and P0.5, so that is where it is
assigned. The next-highest enabled peripheral is the SMBus. P0.0 and P0.1 are free, so the SMBus takes
these two pins. Th e last periphe ral enable d is the PCA’s CEX0 pin. P0.0, P0.1, P0.4 and P0. 5 are alread y
occupied by higher-priority peripherals. Additionally, P0.2 and P0.3 are set to be skipped by the crossbar.
The CEX0 signal ends up getting routed to P0.6, as it is the next available pin. The other pins on the
device are available for use as general-purpose digital I/O or analog functions.
Figure 20.5. Crossbar Priority Decoder Example
Important Note: The SPI can be operated in either 3-wire or 4-wire modes, pending the state of the NSS-
MD1–NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not be
routed to a Port pin.
V
RE
F
IDA x1 x2 CNVSTR
01234567012345670
1
2
2
2
3
2
4
2
SYSCLK
CEX0
CEX1
CEX2
ECI
00110000000000000000
Notes:
1. NS S i s onl y pinned out in 4-wi re S PI M ode
2. P ins P2.1-P2.4 onl y on Q F N24 P acka ge
3. P in 2.0 unavail abl e on cros s bar i n Q F N20 P ackage
SCK
MISO
MOSI
P2
P i n n o t availabl e fo r c ro ssb ar p eripher als.
P2SKIP[0:3]
P0 P1
CP0
SDA
SCL
CP0A
RX0
SF Signa ls
PIN I/O
TX0
NSS1
T0
P1SKIP[0:7]
S peci al F unct ion Signal s are not assigned by the crossbar.
When these s i gnal s are enab l ed, the Cros sBar m ust b e
manua l ly c onfigured to s k i p t hei r corresp ondi ng port pins.
P ort pi n potenti al l y avail abl e to peripheral
SF Signa ls
T1
P0SKIP[0:7]
C8051F336/7/8/9
126 Rev.1.0
20.4. Port I/O Initialization
Port I/O initialization consists of the following steps:
1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode register (PnMDIN).
2. Select the output mode (open-drain or push-pull) for all Port pins, using the Port Output Mode register
(PnMDOUT).
3. Select any pins to be skipped by the I/O Crossbar using the Port Skip registers (PnSKIP).
4. Assign Port pins to desired peripherals.
5. Enable the Crossbar (XBARE = ‘1’).
All Port pins must be configured as either analog or digital inputs. Any pins to be used as Comparator or
ADC inputs should be configured as an analog inputs. When a pin is configured as an analog input, its
weak pullup, digital driver, and digital receiver are disabled. This process saves power and reduces noise
on the analog input. Pins configured as digital inputs may still be used by analog peripherals; however this
practice is not recommended.
Additionally, all analog input pins should be configured to be skipped by the Crossbar (accomplished by
setting the associated bits in PnSKIP). Port input mode is set in the PnMDIN register, where a ‘1’ indicates
a digital i nput, and a ‘0’ indicates an anal og input. All pins default to digit al input s on reset. See SFR Defini-
tion 20.8 for the PnMDIN register details.
The output driver characteristics of the I/O pins are defined using the Port Output Mode registers (PnMD-
OUT). Each Port Output driver can be configured as either open drain or push-pull. This selection is
required even for the digital resources selected in the XBRn registers, and is not automatic. The only
exception to this is the SMBus (SDA, SCL) pins, which are configured as open-drain regardless of the
PnMDOUT settings. When the WEAKPUD bit in XBR1 is ‘0’, a weak pullup is enabled for all Port I/O con-
figured as open-drain. WEAKPUD does not affect the push-pull Port I/O. Furthermore, the weak pullup is
turned off on an output that is driving a ‘0’ to avoid unnecessary power dissipation.
Registers XBR0 and XBR1 must be loaded with the appropriate values to select the digital I/O functions
required by the design. Setting the XBARE bit in XBR1 to ‘1’ enables the Crossbar. Until the Crossbar is
enabled, the external pins remain as standard Port I/O (in input mode), regardless of the XBRn Register
settings. For given XBRn Register settings, one can determine the I/O pin-out using the Priority Decode
Table; as an alternative, the Configuration Wizard utility of the Silicon Labs IDE software will determine the
Port I/O pin-assignments based on the XBRn Register settings.
The Crossbar must be enabled to use Port pins as standard Port I/O in output mode. Port output drivers
are disabled while the Crossbar is disabled.
C8051F336/7/8/9
Rev.1.0 127
SFR Address = 0xE1
SFR Definition 20.1. XBR0: Port I/O Crossbar Register 0
Bit76543210
Name CP0AE CP0E SYSCKE SMB0E SPI0E URT0E
Type R R R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7:6 UNUSED Unused. Read = 00b; Write = Don’t Care.
5CP0AE
Comparator0 Asynchronous Output Enable.
0: Asynchronous CP0 unavailable at Port pin.
1: Asynchronous CP0 routed to Port pin.
4CP0E
Comparator0 Output Enable.
0: CP0 unavailable at Port pin.
1: CP0 routed to Port pin.
3 SYSCKE /SYSCLK Output Enable.
0: /SYSCLK unavailable at Port pin.
1: /SYSCLK output routed to Port pin.
2SMB0E
SMBus I/O Enable.
0: SMBus I/O unavailable at Port pins.
1: SMBus I/O routed to Port pins.
1SPI0E
SPI I/O Enable.
0: SPI I/O unavailable at Port pins.
1: SPI I/O routed to Port pins. Note that the SPI can be assigned either 3 or 4 GPIO
pins.
0URT0E
UART I/O Output Enable.
0: UART I/O unavailable at Port pin.
1: UART TX0, RX0 routed to Port pins P0.4 and P0.5.
C8051F336/7/8/9
128 Rev.1.0
SFR Address = 0xE2
SFR Definition 20.2. XBR1: Port I/O Crossbar Register 1
Bit7 6543210
Name WEAKPUD XBARE T1E T0E ECIE PCA0ME[1:0]
Type R/W R/W R/W R/W R/W R R/W R/W
Reset 0 0000000
Bit Name Function
7 WEAKPUD Port I/O Weak Pullup Disable.
0: Weak Pullups enabled (except for Ports whose I/O are configured for analog
mode).
1: Weak Pullups disabled.
6 XBARE Crossbar Enable.
0: Crossbar disabled.
1: Crossbar enabled.
5T1E
T1 Enable.
0: T1 unavailable at Port pin.
1: T1 routed to Port pin.
4T0E
T0 Enable.
0: T0 unavailable at Port pin.
1: T0 routed to Port pin.
3ECIE
PCA0 External Counter Input Enable.
0: ECI unavailable at Port pin.
1: ECI routed to Port pin.
2 UNUSED Unused. Re ad = 0b; Write = Don’t Care.
1:0 PCA0ME[1:0] PCA Module I/O Enable Bits.
00: All PCA I/O unavailable at Port pins.
01: CEX0 routed to Port pin.
10: CEX0, CEX1 routed to Port pins.
11: CEX0, CEX1, CEX2 routed to Port pins.
C8051F336/7/8/9
Rev.1.0 129
20.5. Port Match
Port match functionality allows system events to be triggered by a logic value change on P0 or P1. A soft-
ware controlled value stored in th e PnMATCH registers specifies the expected or normal logic va lues of P0
and P1. A Port mismatch event occurs if the logic levels of the Port’s input pins no longer match the soft-
ware controlled value. This allows Software to be notified if a certain change or pattern occurs on P0 or P1
input pins regardless of the XBRn settings.
The PnMASK registers can be used to individually select which P0 and P1 pins should be compared
against the PnMATCH registers. A Port mismatch event is generated if (P0 & P0MASK) does not equal
(P0MATCH & P0MASK) or if (P1 & P1MASK) does not equal (P1MATCH & P1MASK).
A Port mismatch event may be used to generate an interrupt or wake the device from a low power mode,
such as IDLE or SUSPEND. See the Interrupts and Power Options chapters for more details on interrupt
and wake-up sources.
SFR Address = 0xFE
SFR Definition 20.3. P0MASK: Port 0 Mask Register
Bit76543210
Name P0MASK[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P0MASK[7:0] Port 0 Mask Value.
Selects P0 pins to be compared to the corresponding bits in P0MAT.
0: P0.n pin logic value is ignored and cannot cause a Port Mismatch event.
1: P0.n pin logic value is compared to P0MAT.n.
C8051F336/7/8/9
130 Rev.1.0
SFR Address = 0xFD
SFR Address = 0xEE
SFR Definition 20.4. P0MAT: Port 0 Match Register
Bit76543210
Name P0MAT[7:0]
Type R/W
Reset 11111111
Bit Name Function
7:0 P0MAT[7:0] Port 0 Mat ch Value.
Match comparison value used on Port 0 for bits in P0MASK which are set to ‘1’.
0: P0.n pin logic value is compared with logic LOW.
1: P0.n pin logic value is compared with logic HIGH.
SFR Definition 20.5. P1MASK: Port 1 Mask Register
Bit76543210
Name P1MASK[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P1MASK[7:0] Port 1 Mask Value.
Selects P1 pins to be compared to the corresponding bits in P1MAT.
0: P1.n pin logic value is ignored and cannot cause a Port Mismatch event.
1: P1.n pin logic value is compared to P1MAT.n.
C8051F336/7/8/9
Rev.1.0 131
SFR Address = 0xED
20.6. Special Function Registers for Accessing and Configuring Port I/O
All Port I/O are accessed through corresponding special function registers (SFRs) that are both byte
addressable and bit addressable. When writing to a Port, the value written to the SFR is latched to
maintain the output data value at each pin. When reading, the logic levels of the Port's input pins are
returned regardless of the XBRn settings (i.e., even when the pin is assigned to another signal by the
Crossbar, the Port register can always read its corresponding Port I/O pin). The exception to this is the
execution of the read-modify-write instructions that target a Port Latch register as the destination. The
read-modify-write instructions when operating on a Port SFR are the following: ANL, ORL, XRL, JBC, CPL,
INC, DEC, DJNZ and MOV, CLR or SETB, when the destination is an individual bit in a Port SFR. For
these instructions, the value of the latch register (not the pin) is read, modified, and written back to the
SFR.
Each Port has a corresponding PnSKIP register which allows its individual Port pins to be assigned to
digital functions or skipped by the Crossbar. All Port pins used for analog functions, GPIO, or dedicated
digital functions such as the EMIF should have their PnSKIP bit set to ‘1’.
The Port input mode of the I/O pins is defined using the Port Input Mode registers (PnMDIN). Each Port
cell can be configured for analog or digital I/O. This selection is required even for the digital resources
selected in the XBRn registers, and is not automatic. The only exception to this is P2.4, which can only be
used for digital I/O.
The output driver characteristics of the I/O pins are defined using the Port Output Mode registers (PnMD-
OUT). Each Port Output driver can be configured as either open drain or push-pull. This selection is
required even for the digital resources selected in the XBRn registers, and is not automatic. The only
exception to this is the SMBus (SDA, SCL) pins, which are configured as open-drain regardless of the
PnMDOUT settings.
SFR Definition 20.6. P1MAT: Port 1 Match Register
Bit76543210
Name P1MAT[7:0]
Type R/W
Reset 11111111
Bit Name Function
7:0 P1MAT[7:0] Port 1 Mat ch Value.
Match comparison value used on Port 1 for bits in P1MASK which are set to ‘1’.
0: P1.n pin logic value is compared with logic LOW.
1: P1.n pin logic value is compared with logic HIGH.
C8051F336/7/8/9
132 Rev.1.0
SFR Address = 0x80; Bit Addressable
SFR Address = 0xF1
SFR Definition 20.7. P0: Port 0
Bit76543210
Name P0[7:0]
Type R/W
Reset 11111111
Bit Name Description Write Read
7:0 P0[7:0] Port 0 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
0: P0.n Port pin is logic
LOW.
1: P0.n Port pin is logic
HIGH.
SFR Definition 20.8. P0MDIN: Port 0 Input Mode
Bit76543210
Name P0MDIN[7:0]
Type R/W
Reset 11111111
Bit Name Function
7:0 P0MDIN[7:0] Analog Configuration Bits for P0.7–P0.0 (respectively).
Port pins configured for analog mode have their weak pullup, digital driver, and
digital receiver disable d.
0: Corresponding P0.n pin is configured for analog mode.
1: Correspon din g P0.n pin is not conf igu re d fo r an alo g mode .
C8051F336/7/8/9
Rev.1.0 133
SFR Address = 0xA4
SFR Address = 0xD4
SFR Definition 20.9. P0MDOUT: Port 0 Output Mode
Bit76543210
Name P0MDOUT[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P0MDOUT[7:0] Output Configuration Bits for P0.7–P0.0 (respectively).
These bits are ignored if the corresponding bit in register P0MDIN is logic 0.
0: Corresponding P0.n Output is open-drain.
1: Correspon ding P0 .n Ou tp u t is push-p u ll.
SFR Definition 20.10. P0SKIP: Port 0 Skip
Bit76543210
Name P0SKIP[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P0SKIP[7:0] Port 0 Crossbar Skip Enable Bits.
These bits select Port 0 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P0.n pin is not skipped by the Crossbar.
1: Corresponding P0.n pin is skipped by the Crossbar.
C8051F336/7/8/9
134 Rev.1.0
SFR Address = 0x90; Bit Addressable
SFR Address = 0xF2
SFR Definition 20.11. P1: Port 1
Bit76543210
Name P1[7:0]
Type R/W
Reset 11111111
Bit Name Description Write Read
7:0 P1[7:0] Port 1 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
0: P1.n Port pin is logic
LOW.
1: P1.n Port pin is logic
HIGH.
SFR Definition 20.12. P1MDIN: Port 1 Input Mode
Bit76543210
Name P1MDIN[7:0]
Type R/W
Reset 11111111
Bit Name Function
7:0 P1MDIN[7:0] Analog Configuration Bits for P1.7–P1.0 (respectively).
Port pins configured for analog mode have their weak pullup, digital driver, and
digital receiver disable d.
0: Corresponding P1.n pin is configured for analog mode.
1: Correspon din g P1.n pin is not conf igu re d fo r an alo g mode .
C8051F336/7/8/9
Rev.1.0 135
SFR Address = 0xA5
SFR Address = 0xD5
SFR Definition 20.13. P1MDOUT: Port 1 Output Mode
Bit76543210
Name P1MDOUT[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P1MDOUT[7:0] Output Configuration Bits for P1.7–P1.0 (respectively).
These bits are ignored if the corresponding bit in register P1MDIN is logic 0.
0: Corresponding P1.n Output is open-drain.
1: Correspon ding P1 .n Ou tp u t is push-p u ll.
SFR Definition 20.14. P1SKIP: Port 1 Skip
Bit76543210
Name P1SKIP[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P1SKIP[7:0] Port 1 Crossbar Skip Enable Bits.
These bits select Port 1 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P1.n pin is not skipped by the Crossbar.
1: Corresponding P1.n pin is skipped by the Crossbar.
C8051F336/7/8/9
136 Rev.1.0
SFR Address = 0xA0; Bit Addressable
SFR Address = 0xF3
SFR Definition 20.15. P2: Port 2
Bit76543210
Name P2[4:0]
Type RRR R/W
Reset 00011111
Bit Name Description Write Read
7:5 UNUSED Unused. Don’t Care 000b
4:0 P2[4:0] Port 2 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
0: P2.n Port pin is logic
LOW.
1: P2.n Port pin is logic
HIGH.
Note: Pins P2.1-P2.4 are only available in QFN24-packaged devices.
SFR Definition 20.16. P2MDIN: Port 2 Input Mode
Bit76543210
Name P2MDIN[7:0]
Type RRRR R/W
Reset 00001111
Bit Name Function
7:4 UNUSED Unused. Read = 0000b; Write = Don’t Care
3:0 P2MDIN[3:0] Analog Configuration Bits for P2.3–P2.0 (respectively).
Port pins configured for analog mode have their weak pullup, digital driver, and
digital receiver disable d.
0: Corresponding P2.n pin is configured for analog mode.
1: Correspon din g P2.n pin is not conf igu re d fo r an alo g mode .
Note: Pins P2.1-P2.4 are only available in QFN24-packaged devices.
C8051F336/7/8/9
Rev.1.0 137
SFR Address = 0xA6
SFR Address = 0xD6
SFR Definition 20.17. P2MDOUT: Port 2 Output Mode
Bit76543210
Name P2MDOUT[4:0]
Type RRR R/W
Reset 00000000
Bit Name Function
7:5 UNUSED Unused. Read = 000b; Write = Don’t Care
4:0 P2MDOUT[4:0] Output Configuration Bits for P2.4–P2.0 (respectively).
These bits are ignored if the corresponding bit in register P2MDIN is logic 0.
0: Corresponding P2.n Output is open-drain.
1: Correspon ding P2 .n Ou tp u t is push-p u ll.
Note: P2.0 is not available for analog input in the QFN20-packaged devices, and P2.1-P2.4 are only available in the
QFN24-packaged devices.
SFR Definition 20.18. P2SKIP: Port 2 Skip
Bit76543210
Name P2SKIP[7:0]
Type RRRR R/W
Reset 00000000
Bit Name Function
7:4 UNUSED Unused. Read = 0000b; Write = Don’t Care
3:0 P2SKIP[3:0] Port 2 Crossbar Skip Enable Bits.
These bits select Port 2 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P2.n pin is not skipped by the Crossbar.
1: Corresponding P2.n pin is skipped by the Crossbar.
Note: P2.0 is not available for cros sba r pe riphe ra ls in the QFN20-packaged devices, and P2.1-P2.4 are only
available in the QFN24-packaged devices.
C8051F336/7/8/9
Rev.1.0 138
21. SMBus
The SMBus I/O interface is a two-wire, bi-directional serial bus. The SM Bus is compliant wit h the System
Management Bus Specification, version 1.1, and compatible with the I2C serial bus. Reads and writes to
the interface by the system controller are byte oriented with the SMBus interface autonomously controlling
the serial transfer of the data. Data can be transferred at up to 1/20th of the system clock as a master or
slave (this can be faster than allowed by the SMBus specification, dependin g on the system clock used). A
method of extending the clock-low duration is available to accommodate devices with different speed
capabilities on the same bus.
The SMBus interface m ay opera te as a ma ster an d/or slav e, and may function on a bus with multiple mas-
ters. The SMBus provides control of SDA (serial data), SCL (serial clock) generation and synchronization,
arbitration logic, and START/STOP control and generation. The SMBus peripheral can be fully driven by
software (i.e., sof tware accept s/r ejects slave addresses, and generates ACKs), or hardware slave address
recognition and automatic ACK generation can be enabled to minimize software overhead. A block dia-
gram of the SMBus peripheral and the associated SFRs is shown in Figure 21.1.
Figure 21.1. SMBus Block Diagram
Data Path
Control
SMBUS CONTROL LOGIC
C
R
O
S
S
B
A
R
SCL
FILTER
N
SDA
Control
SCL
Control
Interrupt
Request
Port I/O
SMB0CN
S
T
A
A
C
K
R
Q
A
R
B
L
O
S
T
A
C
K
S
I
T
X
M
O
D
E
M
A
S
T
E
R
S
T
O
01
00
10
11
T0 Overflow
T1 Overflow
TMR2H Overflow
TMR2L Overflow
SMB0CF
E
N
S
M
B
I
N
H
B
U
S
Y
E
X
T
H
O
L
D
S
M
B
T
O
E
S
M
B
F
T
E
S
M
B
C
S
1
S
M
B
C
S
0
01234567 SMB0DAT SDA
FILTER
N
SMB0ADR
S
L
V
4
S
L
V
2
S
L
V
1
S
L
V
0
G
C
S
L
V
5
S
L
V
6
S
L
V
3
SMB0ADM
S
L
V
M
4
S
L
V
M
2
S
L
V
M
1
S
L
V
M
0
E
H
A
C
K
S
L
V
M
5
S
L
V
M
6
S
L
V
M
3
Arbitration
SCL Synchronization
Hardware ACK Gener ation
SCL Generation (Master Mode)
SDA Control
Hardware Sla ve Address Recognition
IRQ Generati on
C8051F336/7/8/9
139 Rev.1.0
21.1. Supporting Documents
It is assumed the reader is familiar with or has access to the following supporting documents:
1. The I2C-Bus and How to Use It (including specifications), Philips Semiconductor.
2. The I2C-Bus Specification—Version 2.0, Philips Semiconductor.
3. System Management Bus Specification—Version 1.1, SBS Implementers Forum.
21.2. SMBus Configuration
Figure 21.2 shows a typical SMBus configuration. The SMBus specification allows any recessive voltage
between 3.0 V and 5.0 V; different devices on the bus may operate at di fferent voltage levels. The bi-d ire c-
tional SCL (serial clock) and SDA (serial data) lines must be connected to a positive power supply voltage
through a pullup resistor or similar circuit. Every device connected to the bus must have an open-drain or
open-collector output for both the SCL and SDA lines, so that both are pulled high (recessive state) when
the bus is free. The maximum number of devices on th e bus is limited only by the re quirem ent that the r ise
and fall times on the bus not exceed 300 ns and 1000 ns, respectively.
Figure 21.2. Typical SMBus Configuration
21.3. SMBus Operation
Two types of data transfers are possible: data transfers from a master transmitter to an addressed slave
receiver (WRITE), and data transfers from an addressed slave transmitter to a master receiver (READ).
The master device initiates both types of data transfers and provides the serial clock pulses on SCL. The
SMBus interface may operate as a master or a slave, and multiple master devices on the same bus are
supported. If two or more masters attempt to initiate a data transfer simultaneously, an arbitration scheme
is employed with a single master always winning the arbitration. Note that it is not n ecessary to specify one
device as the Master in a system; any device who transmits a START and a slave address becomes the
master for the duration of that transfer.
A typical SMBus transaction consists of a START condition followed by an address byte (Bits7–1: 7-bit
slave address; Bit0: R/W direction bit), one or more bytes of data, and a STOP condition. Bytes that are
received (by a master or slave) are acknowledged (ACK) with a low SDA during a high SCL (see
Figure 21.3). If the receiving device does not ACK, the transmitting device will read a NACK (not acknowl-
edge), which is a high SDA during a high SCL.
The direction bi t (R/W) occupies the least-significan t bit position of th e address byte. The di rection bit is set
to logic 1 to indicate a "READ" operation and cleared to logic 0 to indicate a "WRITE" operation.
VDD = 5V
Master
Device Slave
Device 1 Slave
Device 2
VDD = 3V VDD = 5V VDD = 3V
SDA
SCL
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All transactions are initiated by a master, with one or more addressed slave devices as the target. The
master generates the START condition and then transmits the slave address and direction bit. If the trans-
action is a WRITE operation from the master to the slave, the master transmits the data a byte at a time
waiting for an ACK from the slave at the end of each byte. For READ operations, the slave transmits the
data waiting for an ACK from the master at the end of each byte. At the end of the data transfer, the master
generates a STOP condition to terminate the transaction and free the bus. Figure 21.3 illustrates a typic al
SMBus transaction.
Figure 21.3. SMBus Transaction
21.3.1. Transmitter Vs. Receiver
On the SMBus communications interface, a device is the “transmitter” when it is sending an address or
data byte to another device on the bu s. A device is a “receiver” when an address or data byte is bein g sent
to it from another device on the bus. The transmitter controls the SDA line during the address or data byte.
After each byte of address or data information is sent by the transmitter, the receiver sends an ACK or
NACK bit during the ACK ph ase of the transfer, during which time the receiver controls the SDA line.
21.3.2. Arbitration
A master may star t a transfer on ly if the bus is free. The b us is free af ter a ST OP con dition or after the SCL
and SDA lines remain high for a specified time (see Section “21.3.5. SCL High (SMBus Free) Timeout” on
page 141). In the event that two or more devices attempt to begin a transfer at the same time, an arbitra-
tion scheme is employed to force one master to give up the bus. The master devices continue transmitting
until one attempts a HIGH while the other transmits a LOW. Since the bus is open-drain, the bus will be
pulled LOW. The master attempting the HIGH will detect a LOW SDA and lose the arbitration. The winning
master continues its transmission without interru ption; the losing master becomes a slave and receives the
rest of the transfer if addressed. This arbitration scheme is non-destructive: one device always wins, and
no data is lost.
21.3.3. Clock Low Extension
SMBus provides a clock synchronization mechanism, similar to I2C, which allows devices with different
speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow
slower slave devices to communicate with faster masters. The slave may temporarily hold the SCL line
LOW to extend the clock low period, effectively decreasing the serial clock frequency.
21.3.4. SCL Low Timeout
If the SCL line is held low b y a slave device on the bus, n o further communica tion is possible . Furthermore,
the master ca nnot for ce the SCL lin e high to co rrect th e error condition. To solve this problem, the SMBus
protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than
25 ms as a “timeout” condition. Devices that have detected the timeout condition must reset the communi-
cation no later than 10 ms after detecting the timeout condition.
SLA6
SDA SLA5-0 R/W D7 D6-0
SCL
Slave Address + R/W Data ByteSTART ACK NACK STOP
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When the S MBTOE bit in SM B0 CF is se t, Timer 3 is used to de tect SCL low tim e ou ts. Timer 3 is forced to
reload when SCL is high, and allowed to count when SCL is low. With Timer 3 enabled and configured to
overflow after 25 ms (and SMBTOE set), the T i mer 3 interrupt service routine ca n be used to reset ( disable
and re-enable) the SMBus in the event of an SCL low timeout.
21.3.5. SCL High (SMBus Free) Timeout
The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 µs, the bus
is designated as free. When the SMBFTE bit in SMB0CF is set, the bus will be considered free if SCL and
SDA remain high for more than 10 SMBus clock source periods (as defined by the timer configured for the
SMBus clock source). If the SMBus is waiting to generate a Master START, the START will be generated
following this timeout. A clock source is required for free timeout detection, even in a slave-only implemen-
tation.
21.4. Using the SMBus
The SMBus can operate in both Master and Slave modes. The interface provides timing and shifting con-
trol for serial transfers; higher level protocol is determined by user software. The SMBus interface provides
the following application-independent features:
Byte-wise serial data transfers
Clock signal generation on SCL (Master Mode only) and SDA data synchronization
Timeout/bus error recognition, as defined by the SMB0CF configuration register
START/STOP timing, detection, and generation
Bus arbitration
Interrupt generation
Status information
Optional hardware recognition of slave address and automatic acknowledgement of address/data
SMBus interrupts are generated for each data byte or slave address that is transferred. When hardware
acknowledgement is disabled, the point at which the interrupt is generated depends on whether the hard-
ware is acting as a data transmitter or receiver. When a transmitter (i.e., sending address/data, receiving
an ACK), this interrupt is generated after the ACK cycl e so that sof tware may read the receive d ACK value;
when receiving data (i.e., receiving address/data, sending an ACK), this interrupt is generated before the
ACK cycle so that software may define the outgoing ACK value. If hardware ackn owled gemen t is en able d,
these interrupts are always generated after the ACK cycle. See Section 21.5 for more details on transmis-
sion sequences.
Interrupts are also generated to indicate the beginning of a transfer when a master (START generated), or
the end of a transfer when a slave (STOP detected). Software should read the SMB0CN (SMBus Control
register) to find the cause of the SMBus interrupt. The SMB0CN register is described in Section 21.4.2;
Table 21.5 provides a quick SMB0CN decoding refe rence.
21.4.1. SMBus Configuration Re gi st er
The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes,
select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is
set, the SMBus is enabled for all master and slave events. Slave events may be disabled by setting the
INH bit. With slave events inhibited, the SMBus interface will still monitor the SCL and SDA pins; however,
the interface will NACK all received addresses and will not generate any slave interrupts. When the INH bit
is set, all slave events will be inhibited following the next START (interrupts will continue for the duration of
the current tra ns fe r) .
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The SMBCS1–0 bits select the SMBus clock source, which is used only when operating as a master or
when the Free Timeout detection is enabled. When operating as a master, overflows from the selected
source determine the absolute minimum SCL low and high times as de fined in Equation 21.1. Note that the
selected clock source may be shared by other peripherals so long as the timer is left running at all times.
For example, Timer 1 overflows may generate the SMBus and UART baud rates simultaneously. Timer
configuration is covered in Section “24. Timers” on page 180.
Equation 21.1. Minimum SCL High and Low Times
The selected clock source should be configured to establish the minimum SCL High and Low times as per
Equation 21.1. When the interface is operating as a master (and SCL is not driven or extended by any
other devices on the bus), the typical SMBus bit rate is approximated by Equation 21.2.
Equation 21.2. Typical SMBus Bit Rate
Figure 21.4 shows the typical SCL generation described by Equation 21.2. Notice that THIGH is typically
twice as large as TLOW. The actual SCL output may vary due to other devices on the bus (SCL may be
extended low by slower slave devices, or driven low by contending master devices). The bit rate when
operating as a master will never exceed the limits defined by equation Equation 21.1.
Figure 21.4. Typical SMBus SCL Generation
Setting the EXTHOLD bit ext ends the minimum setup and hold times for the SDA line. The minimum SDA
setup time defines the absolute minimum time that SDA is stable before SCL tran sitions from low- to-high.
The minimum SDA hold time defin es the absolute minimum time that the curre nt SDA value remains stabl e
Table 21.1. SMBus Clock Source Selection
SMBCS1 SMBCS0 SMBus Clock Source
0 0 Ti mer 0 Overflow
0 1 Ti mer 1 Overflow
1 0 Timer 2 High Byte Overflow
1 1 Timer 2 Low Byte Overflow
THighMin TLowMin 1
fClockSourceOverflow
----------------------------------------------
==
BitRate fClockSourceOverflow
3
----------------------------------------------
=
SCL
Timer Source
Overflows
SCL High TimeoutTLow THigh
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after SCL transitions from high-to-low. EXTHOLD should be set so that the minimum setup and hold times
meet the SMBus Specification requirements of 250 ns and 300 ns, respectively. Table 21.2 shows the min-
imum setup and hold times for the two EXTHOLD settings. Setup and hold time extensions are typically
necessary when SYSCLK is above 10 MHz.
With the SMBTOE bit set, Timer 3 should be configured to overflow after 25 ms in order to detect SCL low
timeouts (see Section “21.3.4. SCL Low Timeout” on page 140). The SMBus interface will force Timer 3 to
reload while SCL is hig h, and allow Timer 3 to count when SCL is low. The T imer 3 interrupt service routine
should be used to reset SMBus communication by disabling and re-enabling the SMBus.
SMBus Free T imeout detection can be enabled by setting the SMBFTE bit. When this bit is set, the bus will
be considered free if SDA and SCL remain high for more than 10 SMBus clock source periods (see
Figure 21.4).
Table 21.2. Minimum SDA Setup and Hold Times
EXTHOLD Minimum SDA Setup Time Minimum SDA Hold Time
0Tlow – 4 system clocks
or
1 system clock + s/w delay*3 system clocks
1 11 system clocks 12 system clocks
Note: Setup Time for ACK bit transmissions and the MSB of all data transfers. When using
software acknowledgement, the s/w delay occurs between the time SMB0DAT or
ACK is written and when SI is cleared. Note that if SI is cleared in the same write
that defines the outgoing ACK value, s/w delay is zero.
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SFR Address = 0xC1
SFR Definition 21.1. SMB0CF: SMBus Clock/Configuration
Bit76543210
Name ENSMB INH BUSY EXTHOLD SMBTOE SMBFTE SMBCS[1:0]
Type R/W R/W R R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7ENSMB
SMBus Enable.
This bit enables the SMBus interface when set to 1. When enabled, the interface
constantly monitors the SDA and SCL pins.
6INH
SMBus Slave Inhibit.
When this bit is set to logic 1, the SMBus does not gene rate an interrupt when slave
events occur. This effectively removes the SMBus slave from the bus. Master Mode
interrupts are not affected.
5BUSY
SMBus Busy Indicator.
This bit is set to logic 1 by hardware when a transfer is in progress. It is cleared to
logic 0 when a ST OP or free-timeout is sensed.
4 EXTHOLD SMBus Setup and Hold Time Extension Enable.
This bit controls the SDA setup and hold times according to Table 21.2.
0: SDA Extended Setup and Hold Times disabled.
1: SDA Extended Setup and Hold Times enabled.
3SMBTOE
SMBus SCL Timeout Detection Enable.
This bit enables SCL low timeout detection. If set to logic 1, the SMBus forces
T i mer 3 to reload wh ile SCL is high an d allows Timer 3 to count when SCL goes low.
If T ime r 3 is configured to Split Mode, only the High Byte of the timer is held in re load
while SCL is high. Timer 3 should be programmed to generate interrupts at 25 ms,
and the Timer 3 interrupt service routine should reset SMBus communication.
2SMBFTE
SMBus Free T imeout Detection Enable.
When this bit is set to logic 1, the bus will be considered free if SCL and SDA remain
high for more than 10 SMBus clock source periods.
1:0 SMBCS[1:0] SMBus Clock Source Selection.
These two bit s select th e SMBus clock sour ce, which is used to generate the SMBus
bit rate. The selected device should be configured according to Equation 21.1.
00: Timer 0 Overflow
01: Timer 1 Overflow
10: Timer 2 High Byte Overflow
11: Timer 2 Low Byte Overflow
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21.4.2. SMB0CN Control Regi st er
SMB0CN is used to control the interface and to provide status information (see SFR Definition 21.2). The
higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to
jump to service routines. MASTER indicates whether a device is the master or slave during the current
transfer. TXMODE indicates whether the device is transmitting or receiving data for the current byte.
STA and STO indicate that a START and/or STOP has been detected or generated since the last SMBus
interrupt. STA and STO are also used to gene ra te START and ST OP co ndition s when op erating as a ma s-
ter. Writing a 1 to STA will cause the SMBus interface to enter Master Mode and generate a START when
the bus be comes fr ee (STA is not c leared b y hardwa re after the START is generated). Writing a 1 to STO
while in Master Mode will cause the interface to generate a STOP and end the current transfer after the
next ACK cycle. If STO and STA are both set (while in Master Mode), a STOP followed by a START will be
generated.
The ARBLOST bit indicates that the interface has lost an arbitration. This may occur anytime the interface
is transmitting (master or slave). A lost arbitration while operating as a slave indicates a bus error condi-
tion. ARBLOST is cleared by hardware each time SI is cleared.
The SI bit (SMBus Interrupt Flag) is set at the beginn ing and end of each transfe r, after each byte frame, or
when an arbitration is lost; see Table 21.3 for more details.
Import ant Note About t he SI Bit : The SMBus interface is stalled while SI is set; thus SCL is held low, and
the bus is stalled until software clears SI.
21.4.2.1. Software ACK Generation
When the EHACK bit in register SMB0ADM is cleared to 0, the firmware on the device must detect incom-
ing slave addresses and ACK or NACK the slave address and incoming data bytes. As a receiver, writing
the ACK bit defines the outgoing ACK value; as a transmitter, reading the ACK bit indicates the value
received during the last ACK cycle. ACKRQ is set each time a byte is received, indicating that an outgoing
ACK value is needed. When ACKRQ is set, software should write the desired outgoing value to the ACK
bit before clearing SI. A NACK will be generated if software does not write the ACK bit before clearing SI.
SDA will reflect the defined ACK value immediately following a write to the ACK bit; however SCL will
remain low until SI is cleared. If a received slave address is not acknowledged, further slave events will be
ignored until the next START is detected.
21.4.2.2. Hardware ACK Generation
When the EHACK bit in register SMB0ADM is set to 1, automatic slave address recognition and ACK gen-
eration is enabled. More detail about automatic slave address recognition can be found in Section 21.4.3.
As a receiver, the value currently s pecified by the ACK bit will be automatically sent on the bus during the
ACK cycle of an incoming data byte. As a transmitter, reading the ACK bit indicates the value received on
the last ACK cycle. The ACKRQ bit is no t used when hardware ACK generation is enabled. If a received
slave address is NACKed by hardware, further slave events will be ignored until the next START is
detected, and no interrupt will be generated.
Table 21.3 lists all sources for hardware changes to the SMB0CN bits. Refer to Table 21.5 for SMBus sta-
tus decoding using the SMB0CN register.
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SFR Address = 0xC0; Bit-Addressable
SFR Definition 21.2. SMB0CN: SMBus Control
Bit76543210
Name MASTER TXMODE STA STO ACKRQ ARBLOST ACK SI
Type RRR/WR/WRRR/WR/W
Reset 00000000
Bit Name Description Read Write
7 MASTER SMBus Master/Slave
Indicator. This read-only bit
indicates when the SMBus is
operating as a master.
0: SMBus operating in
slave mode.
1: SMBus operating in
master mode.
N/A
6TXMODE
SMBus Transmit Mode
Indicator. This read-only bit
indicates when the SMBus is
operating as a tran smitter.
0: SMBus in Receiver
Mode.
1: SMBus in Transmitter
Mode.
N/A
5STA
SMBus Start Flag. 0: No Start or repeated
Start detected.
1: Start or repeated Start
detected.
0: No Start generated.
1: When Configured as a
Master, initiates a START
or repeated START.
4STO
SMBus Stop Flag. 0: No Stop condition
detected.
1: Stop condition detected
(if in Slave Mode) or pend-
ing (if in Master Mode).
0: No STOP condition is
transmitted.
1: When configured as a
Master, causes a STOP
condition to be transmit-
ted after the next ACK
cycle.
Cleared by Hardware.
3ACKRQ
SMBus Acknowledge
Request. 0: No Ack requested
1: ACK requested N/A
2ARBLOST
SMBus Arbitration Lost
Indicator. 0: No arbitration error.
1: Arbitration Lost N/A
1ACK
SMBus Acknowledge. 0: NACK received.
1: ACK received. 0: Send NACK
1: Send ACK
0SI
SMBus Interrupt Flag.
This bit is set by hardware
under the conditions listed in
Table 15.3. SI must be cleared
by software. While SI is set,
SCL is held low and the
SMBus is stalled.
0: No interrupt pending
1: Interrupt Pending 0: Clear interrupt, and initi-
ate next state machine
event.
1: Force interrupt.
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21.4.3. Hardware Slave Address Recognition
The SMBus hardware has the capa bility to automatically recognize incoming slave addresses and send an
ACK without software intervention. Automatic slave address recognition is enabled by setting the EHACK
bit in register SMB0ADM to 1. This will enable both automatic slave address recognition and automatic
hardware ACK generation for received bytes (as a master or slave). More detail on automatic hardware
ACK generation can be found in Section 21.4.2.2.
The registers used to define which address(es) are recognized by the hardware are the SMBus Slave
Address register (SFR Definition 21.3) and the SMBus Slave Address Mask register (SFR Definition 21.4).
A single address or range of addresses (including the General Call Address 0x00) can be specified using
these two registers. The most-significant seven bits of the two registers are used to define which
addresses will be ACKed. A 1 in bit positions of the slave address mask SLVM[6:0] enable a comparison
between the received slave address and the hardware’s slave address SLV[6:0] for those bits. A 0 in a bit
Table 21.3. Sources for Hardware Changes to SMB0CN
Bit Set by Hardware When: Cleared by Hardware When:
MASTER A START is generated. A STOP is generated.
Arbitration is lost.
TXMODE
START is generated.
SMB0DAT is written before the start of an
SMBus frame.
A START is detected.
Arbitration is lost.
SMB0DAT is not written before the
start of an SMBus frame.
STA A START followed by an address byte is
received. Must be cleared by software.
STO
A STOP is detected while addressed as a
slave.
Arbitration is lost due to a detected STOP.
A pending STOP is generated.
ACKRQ A byte has been received and an ACK
response value is needed (only when
hardware ACK is not enabled).
After each ACK cycle.
ARBLOST
A repeated START is detected as a
MASTER when STA is low (unwanted
repeated START).
SCL is sensed low while attempting to
generate a STOP or repeated START
condition.
SDA is sensed low while transmitting a 1
(excluding ACK bits).
Each time SI is cleared.
ACK The incoming ACK value is low
(ACKNOWLEDGE). The incoming ACK value is high
(NOT ACKNOWLEDGE).
SI
A START has been generated.
Lost arbitration.
A byte has been transmitted and an
ACK/NACK received.
A byte has been received.
A START or repeated START followed by a
slave address + R/W has been received.
A STOP has been received.
Must be cleared by software.
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of the slave address mask means that bit w ill be treated as a “don’t care” for comparison purposes. In this
case, either a 1 or a 0 value are acceptable on the incoming slave address. Additionally, if the GC bit in
register SMB0ADR is set to 1, hardware will recognize the General Call Address (0x00). Table 21.4 shows
some example parameter settings and the slave addresses that will be recognized by hardware under
those conditions.
SFR Address = 0xD7
Table 21.4. Hardware Address Recognition Examples (EHACK = 1)
Hardware Slave Address
SLV[6:0] Slave Address Mask
SLVM[6:0] GC bit Slave Addresses Recognized by
Hardware
0x34 0x7F 0 0x34
0x34 0x7F 1 0x34, 0x00 (General Call)
0x34 0x7E 0 0x34, 0x35
0x34 0x7E 1 0x34, 0x35, 0x00 (General Call)
0x70 0x73 0 0x70, 0x74, 0x78, 0x7C
SFR Definition 21.3. SMB0ADR: SMBus Slave Address
Bit76543210
Name SLV[6:0] GC
Type R/W R/W
Reset 00000000
Bit Name Function
7:1 SLV[6:0] SMBus Hardware Slave Address.
Defines the SMBus Slave Addr ess(es) for automatic hardware acknowledge ment.
Only address bits which have a 1 in the corresponding bit position in SLVM[6:0]
are checked again st the inc om in g ad dr es s. Th is allo ws mu ltip le addre sse s to be
recognized.
0GC
General Call Address Enable.
When hardware address recognition is enabled (EHACK = 1), this bit will deter-
mine whether the General Call Address (0x00) is also recognized by hardware.
0: General Call Address is ignored.
1: General Call Address is recognized.
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SFR Address = 0xE7
SFR Definition 21.4. SMB0ADM: SMBus Slave Address Mask
Bit76543210
Name SLVM[6:0] EHACK
Type R/W R/W
Reset 11111110
Bit Name Function
7:1 SLVM[6:0] SMBus Slave Address Mask.
Defines which bits of register SMB0ADR are compa red with an incoming address
byte, and which bits are ignored. Any bit set to 1 in SLVM[6:0] enables compari-
sons with the correspondin g bit in SL V[6:0]. Bit s set to 0 are ignored (can b e either
0 or 1 in the incoming address).
0EHACK
Hardware Acknowledge Enable.
Enables hardware acknowledgement of slave address and received data bytes.
0: Firmware must manually acknowledge all incoming address and data bytes.
1: Automatic Slave Address Recognition and Hardware Acknowledge is Ena bled.
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21.4.4. Data Register
The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been
received. Software may safely read or write to the dat a register when th e SI flag is set. Sof tware sho uld not
attempt to ac cess the SMB0DAT regis ter when th e SMBus is ena bled and th e SI flag is clear ed to logic 0,
as the interface may be in the process of shifting a byte of data into or out of the register.
Data in SMB0DAT is always s hifted ou t MSB first. After a byte has been received, the first bit of received
data is located at the MSB of SMB0DAT. While data is being shifted out, data on the bus is simultaneously
being shifted in. SMB0DAT always contains the last data byte pre sent on th e bus. In the even t of lost a rbi-
tration, the transition from master transmitter to slave receiver is made with the correct data or address in
SMB0DAT.
SFR Address = 0xC2
SFR Definition 21.5. SMB0DAT: SMBus Data
Bit76543210
Name SMB0DAT[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 SMB0DAT[7:0] SMBus Data.
The SMB0DAT register contain s a byte of data to be transmitted on the SMBus
serial interface or a byte th at has just been received on the SMBu s serial interface.
The CPU can read fr om or write to this re gister whenever the SI serial interrupt flag
(SMB0CN.0) is set to logic 1. The serial data in the register remains stable as long
as the SI flag is set. When the SI flag is not set, the system may be in the process
of shifting data in/out and the CPU should not attempt to access this register.
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21.5. SMBus Transfer Modes
The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be
operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or
Slave Receiver. The SMBus interface enters Master Mode a ny time a START is genera ted, an d rem ains i n
Master Mode until it loses an arbitration or generates a STOP. An SMBus interrupt is generated at the end
of all SMBus byte frames. Note that the position of the ACK interrupt when operating as a receiver
depends on whether hardware ACK generation is enabled. As a receiver, the inte rrupt for an ACK occurs
before the ACK with hardware ACK generation disabled, and after the ACK when hardware ACK genera-
tion is enabled. As a transm itter, interrupts occur after the ACK, regardless of whether hardware ACK gen-
eration is enabled or not.
21.5.1. Write Sequence (Master)
During a write sequence, an SMBus master writes data to a slave device. The master in this transfer will be
a transmitter during the ad dress byt e, and a tra nsmitte r during all data bytes. The SMBu s interfac e gener -
ates the START condition and transmits the first byte containing the address of the target slave and the
data direction bit. In this case the data direction bit (R/W) will be logic 0 (WRITE). The master then trans-
mits one or more bytes of serial data. After each byte is transmitted, an acknowledge bit is generated by
the slave. The transfer is ended when the STO bit is set and a STOP is generated. Note that the interface
will switch to Master Receiver Mode if SMB0DAT is not written following a Master Transmitter interrupt.
Figure 21.5 shows a typical master write sequence. Two transmit data bytes are shown, though any num-
ber of bytes may be transmitted. Notice that all of the “dat a byte transferred” interr upt s occur af ter the ACK
cycle in this mode, regardless of whether hardware ACK generation is enab led.
Figure 21.5. Typical Master Write Sequence
A AAS W PData Byte Data ByteSLA
S = START
P = STOP
A = ACK
W = WRITE
SLA = Slave Address
Received by SMBus
Interface
Tran smitted by
SMBus Interface
Interrupts with Hardware ACK Disabled (EHACK = 0 )
Interrupts with Hardware ACK Enabled (EHACK = 1)
C8051F336/7/8/9
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21.5.2. Read Sequence (Master)
During a read sequence, an SMBus master reads data from a slave device. The master in this transfer will
be a transmitter during the a ddress byte, and a receiver during all data bytes. The SMBus interface gener-
ates the START condition and transmits the first byte containing the address of the target slave and the
data direction bit. In this case the data direction bit (R/W) will be logic 1 (READ). Serial data is then
received from the slave o n SDA while th e SMBus outp ut s the seria l clock. The sla ve transmit s one o r more
bytes of serial data.
If hardware ACK generation is disabled, the ACKRQ is set to 1 and an interrupt is generated after each
received byte. Software must write the ACK bit at that time to ACK or NACK the received byte.
With hardware ACK generation enabled, the SMBus hardware will automatically generate the ACK/NACK,
and then post the interrupt. It is important to note that the appropriate ACK or NACK value should be
set up by the software prior to receiving the byte when hardware ACK generati on is enabled.
Writing a 1 to the ACK bit generates an ACK; writing a 0 generates a NACK. Software should write a 0 to
the ACK bit for the last data transfer, to transmit a NACK. The interface exits Master Receiver Mode after
the STO bit is set and a STOP is generated. The interface will switch to Master T r ansmitter Mode if SMB0-
DAT is written while an active Master Receiver. Figure 21.6 shows a typical master read sequence. Two
received data bytes are shown, though any number of bytes may be received. Notice that the ‘data byte
transferred’ interrupt s occur at diff erent places in the sequence, depend ing on whethe r hardware ACK gen-
eration is enabled. The interrupt occurs before the ACK with hardware ACK generation disabled, and after
the ACK when hardware ACK generation is enabled.
Figure 21.6. Typical Master Read Sequence
Data ByteData Byte A NAS R PSLA
S = START
P = STOP
A = ACK
N = NACK
R = READ
SLA = Slave Address
Received by SMBus
Interface
Transmitted by
SMBus Interface
Interrupts with Hardware ACK Disabled (EHACK = 0)
Interrupts with Hardware ACK Enabled (EHACK = 1)
C8051F336/7/8/9
153 Rev.1.0
21.5.3. Write Sequence (Slave)
During a write sequence, an SMBus master writes data to a slav e device. The slave in this transfer w ill be
a receiver during the address byte, and a receiver during all data bytes. When slave events are enabled
(INH = 0), the interface enters Slave Receiver Mode when a START followed by a slave address and dire c-
tion bit (WRITE in this case) is received. If hardware ACK generation is disabled, upon entering Slave
Receiver Mode, an interrupt is generated and the ACKRQ bit is set. The software must respond to the
received slave address with an ACK, or ignore the received slave address with a NACK. If hardware ACK
generation is enabled, the hardware will apply the ACK for a slave address which matches the criteria set
up by SMB0ADR and SMB0ADM. The interrupt will occur after the ACK cycle.
If the received slave address is ignored (by software or hardware), slave interrupts will be inhibited until the
next START is detected. If the received slave address is acknowledged, zero or more data bytes are
received.
If hardware ACK generation is disabled, the ACKRQ is set to 1 and an interrupt is generated after each
received byte. Software must write the ACK bit at that time to ACK or NACK the received byte.
With hardware ACK generation enabled, the SMBus hardware will automatically generate the ACK/NACK,
and then post the interrupt. It is important to note that the appropriate ACK or NACK value should be
set up by the software prior to receiving the byte when hardware ACK generati on is enabled.
The interface exits Slave Receiver Mode after receiving a ST OP. Note that the interface will switch to Slave
Transmitter Mode if SMB0DAT is written while an active Slave Receiver. Figure 21.7 shows a typical slave
write sequence. Two received data bytes are shown, though any number of bytes may be received. Notice
that the ‘data byte transferred’ interrupts occur at different places in the sequence, depending on whether
hardware ACK generation is enabled. The interrupt occurs before the ACK with hardware ACK generation
disabled, and after the ACK when hardware ACK generation is enabled.
Figure 21.7. Typical Slave Write Sequence
PWSLASData ByteData Byte A AA
S = START
P = STOP
A = ACK
W = WRITE
SLA = Slave Address
Received by SMBus
Interface
Tran smitted by
SMBus Interface
Interrupts with Hardware ACK Disabled (EHACK = 0)
Interrupts with Hardware ACK Enabled (EHACK = 1)
C8051F336/7/8/9
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21.5.4. Read Sequence (Slave)
During a read sequence, an SMBus master reads data from a slave device. The slave in this transfer will
be a receiver during the address byte, and a transmitter during all data bytes. When slave events are
enabled (INH = 0), the inter face enters Slave Receiver Mode (to receive the slave address) when a START
followed by a slave address and direction bit (READ in this case) is received. If hardware ACK g eneration
is disabled, upon entering Slave Receiver Mode, an interrupt is generated and the ACKRQ bit is set. The
software must respond to the received slave address with an ACK, or ignore the received slave address
with a NACK. If hardware ACK generation is enabled, the hardware will apply the ACK for a slave address
which matches the criteria set up by SMB0ADR and SMB0ADM. The interrupt will occur after the ACK
cycle.
If the received slave address is ignored (by software or hardware), slave interrupts will be inhibited until the
next START is detected. If the received sla ve ad dress is ackn owledged , zero or more dat a b ytes are tran s-
mitted. If the receiv ed sl ave ad dress is ac knowle dged, data should be writ ten to SMB0DAT to be transmit -
ted. The interfa ce ent ers slav e tran smitt er mo de, and tr ansm its one or more by tes of d ata. After each byte
is transmitted, the master sends an acknowledge bit; if the acknowledge bit is an ACK, SMB0DAT should
be written with the next data byte. If the acknowledge bit is a NACK, SMB0DAT should not be written to
before SI is cleared (an error condition may be generated if SMB0DAT is written following a received
NACK while in slave transmitter mode). T he in te rf ac e exits slave t ra ns mit te r m o de after re ce ivin g a STOP.
Note that the interface will switch to slave receiver mode if SMB0DAT is not written following a Slave
Transmitter interrupt. Figure 21.8 shows a typical slave read sequence. Two transmitted data bytes are
shown, though any number of bytes may be transmitted. Notice that all of the “data byte transferred” inter-
rupts occur after the ACK cycle in this mode, regardless of whether hardware ACK generation is e nabled.
Figure 21.8. Typical Slave Read Sequence
21.6. SMBus Status Decoding
The current SMBus status can be easily decoded using the SMB0CN register. The appropriate actions to
take in response to an SMBus event depend on whether hardware slave address recognition and ACK
generation is enabled or disabled. Table 21.5 describes the typical actions when hardware slave address
recognition and ACK generation is disabled. Table 21.6 describes the typical actions when hardware slave
address recognition and ACK generation is enabled. In the tables, STATUS VECTOR refers to the four
upper bits of SMB0CN: MASTER, TXMODE, STA, and STO. The shown response options a re only the typ-
ical responses; application-specific procedures are allowed as long as they conform to the SMBus specifi-
cation. Highlighted responses are allo wed by hardware but do not conform to the SMBus specification.
PRSLASData ByteData Byte A NA
S = START
P = STOP
N = NACK
R = READ
SLA = Slave Address
Received by SMBus
Interface
Tran smitted by
SMBus Interface
Interrupts with Hardware ACK Disabled (EHACK = 0)
Interrupts with Hardware ACK Enabled (EHACK = 1)
C8051F336/7/8/9
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Table 21.5. SMBus Status Decoding With Hardware ACK Generation Disabled
(EHACK = 0)
Mode
Values Read
Current SMbus State Typical Response Options
Values to
Write
Next Status
Vector Expected
Status
Vector
ACKRQ
ARBLOST
ACK
STA
STO
ACK
Master Transmitter
1110 0 0 X A master START was gener-
ated. Load slave address + R/W into
SMB0DAT. 00X1100
1100
000
A master dat a or ad dress byte
was transmitted; NACK
received.
Set STA to restart transfer. 1 0 X 1110
Abort transfer. 01X —
001
A master dat a or ad dress byte
was transmitted; ACK
received.
Load next data byte into
SMB0DAT. 00X1100
End transfer with STOP. 0 1 X —
End transfer with STOP and start
another transfer. 11X —
Send repeated START. 1 0 X 1110
Switch to Master Receiver Mode
(clear SI without writing new data
to SMB0DAT).
0 0 X 1000
Master Rece iv er
1000 1 0 X A master data byte was
received; ACK requ ested.
Acknowledge received byte;
Read SMB0DAT. 0 0 1 1000
Send NACK to indicate last by te,
and send STOP. 010 —
Send NACK to indicate last by te,
and send STOP followed by
START.
1101110
Send ACK followed by repeated
START. 1011110
Send NACK to indicate last by te,
and send repeated START. 1001110
Send ACK and switch to Master
Transmitter Mode (write to
SMB0DAT before clearing SI).
0 0 1 1100
Send NACK and switch to Mas-
ter Transmitter Mode (write to
SMB0DAT before clearing SI).
0 0 0 1100
C8051F336/7/8/9
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Slave Transmitter
0100
000
A slave byte was transmitted;
NACK received. No action required (expecting
STOP condition). 0 0 X 0001
001
A slave byte was transmitted;
ACK rece ived. Load SMB0DAT with next data
byte to transmit. 0 0 X 0100
01X
A Slave byte was transmitted;
error detected. No action required (expecting
Master to end transfer). 0 0 X 0001
0101 0 X X An illegal STOP or bus error
was detected while a Slave
Transmission was in progress. Clear STO. 00X —
Slave Receiver
0010
10X
A slave address + R/W was
received; ACK requ ested.
If Write, Acknowledge received
address 0 0 1 0000
If Read, Load SMB0DAT with
data byte; ACK re ceived addr ess 0 0 1 0100
NACK received address. 0 0 0 —
11X
Lost arbitra tio n as m ast er ;
slave address + R/W received;
ACK requested.
If Write, Acknowledge received
address 0 0 1 0000
If Read, Load SMB0DAT with
data byte; ACK re ceived addr ess 0 0 1 0100
NACK received address. 0 0 0 —
Reschedule failed transfer;
NACK received address. 1001110
0001 00X
A STOP was detected while
addres se d as a Slave Tr an s-
mitter or Slave Rec eiver. Clear STO. 00X —
11X
Lost arbitration while attempt-
ing a STOP. No action required (transfer
complete/aborted). 000 —
0000 1 0 X A slave byte was received;
ACK requested.
Acknowledge received byte;
Read SMB0DAT. 0 0 1 0000
NACK received byte. 0 0 0 —
Bus Error Condition
0010 0 1 X Lost arbitration while attempt-
ing a repeated START. Abort failed transfer. 0 0 X —
Reschedule failed transfer. 1 0 X 1110
0001 0 1 X L o st ar bit ra tio n du e to a
detected STOP. Abort failed transfer. 0 0 X —
Reschedule failed transfer. 1 0 X 1110
0000 1 1 X Lost arbitration while transmit-
ting a dat a byte as master. Abort failed transfer. 0 0 0 —
Reschedule failed transfer. 1001110
Table 21.5. SMBus Status Decoding With Hardware ACK Generation Disabled
(EHACK = 0) (Continued)
Mode
Values Read
Current SMbus State Typical Response Options
Values to
Write
Next Status
Vector Expected
Status
Vector
ACKRQ
ARBLOST
ACK
STA
STO
ACK
C8051F336/7/8/9
157 Rev.1.0
Table 21.6. SMBus Status Decoding With Hardware ACK Generation Enabled
(EHACK = 1)
Mode
Values Read
Current SMbus State Typical Response Options
Values to
Write
Next Status
Vector Expected
Status
Vector
ACKRQ
ARBLOST
ACK
STA
STO
ACK
Master Transmitter
1110 0 0 X A master START was gener-
ated. Load slave address + R/W into
SMB0DAT. 00X1100
1100
000
A master dat a or ad dress byte
was transmitted; NACK
received.
Set STA to restart transfer. 1 0 X 1110
Abort transfer. 01X —
001
A master dat a or ad dress byte
was transmitted; ACK
received.
Load next data byte into
SMB0DAT. 00X1100
End transfer with STOP. 0 1 X —
End transfer with STOP and start
another transfer. 11X —
Send repeated START. 1 0 X 1110
Switch to Master Receiver Mode
(clear SI without writing new data
to SMB0DAT). Set ACK for initial
data byte.
0 0 1 1000
Master Receiver
1000
001
A master data byte was
received; ACK sent.
Set ACK for next data byte;
Read SMB0DAT. 0 0 1 1000
Set NACK to indica te next dat a
byte as the last data byte;
Read SMB0DAT.
0 0 0 1000
Initiate repeated START. 1 0 0 1110
Switch to Master Transmitter
Mode (write to SMB0DAT before
clearing SI).
0 0 X 1100
000
A master data byte was
received; NACK sent (last
byte).
Read SMB0DAT; send STOP. 0 1 0 —
Read SMB0DAT; Send STOP
followed by START. 1101110
Initiate repeated START. 1 0 0 1110
Switch to Master Transmitter
Mode (write to SMB0DAT before
clearing SI).
0 0 X 1100
C8051F336/7/8/9
Rev.1.0 158
Slave Transmitter
0100
000
A slave byte was transmitted;
NACK received. No action required (expecting
STOP condition). 0 0 X 0001
001
A slave byte was transmitted;
ACK rece ived. Load SMB0DAT with next data
byte to transmit. 0 0 X 0100
01X
A Slave byte was transmitted;
error detected. No action required (expecting
Master to end transfer). 0 0 X 0001
0101 0 X X An illegal STOP or bus error
was detected while a Slave
Transmission was in progress. Clear STO. 00X —
Slave Receiver
0010
00X
A slave address + R/W was
received; ACK sent.
If Write, Set ACK for first data
byte. 0 0 1 0000
If Read, Load SMB0DAT with
data byte 0 0 X 0100
01X
Lost arbitra tio n as m ast er ;
slave address + R/W received;
ACK sent.
If Write, Set ACK for first data
byte. 0 0 1 0000
If Read, Load SMB0DAT with
data byte 0 0 X 0100
Reschedule failed transfer 1 0 X 1110
0001 00X
A STOP was detected while
addres se d as a Slave Tr an s-
mitter or Slave Rec eiver. Clear STO. 00X —
01X
Lost arbitration while attempt-
ing a STOP. No action required (transfer
complete/aborted). 000 —
0000 0 0 X A slave byte was received.
Set ACK for next data byte;
Read SMB0DAT. 0 0 1 0000
Set NACK for next data byte;
Read SMB0DAT. 0 0 0 0000
Bus Error Condition
0010 0 1 X Lost arbitration while attempt-
ing a repeated START. Abort failed transfer. 0 0 X —
Reschedule failed transfer. 1 0 X 1110
0001 0 1 X L o st ar bit ra tio n du e to a
detected STOP. Abort failed transfer. 0 0 X —
Reschedule failed transfer. 1 0 X 1110
0000 0 1 X Lost arbitration while transmit-
ting a dat a byte as master. Abort failed transfer. 0 0 X —
Reschedule failed transfer. 10X1110
Table 21.6. SMBus Status Decoding With Hardware ACK Generation Enabled
(EHACK = 1) (Continued)
Mode
Values Read
Current SMbus State Typical Response Options
Values to
Write
Next Status
Vector Expected
Status
Vector
ACKRQ
ARBLOST
ACK
STA
STO
ACK
C8051F336/7/8/9
Rev.1.0 159
22. UART0
UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART.
Enhanced baud ra te su pport allows a wide r ange of clock sour ces to gene rate standard baud rates (det ails
in Section “22.1. Enhanced Baud Rate Generation” on page 160). Received data buffering allows UART0
to start reception of a second incoming data byte before software has finished reading the previous data
byte.
UART0 has two associated SFRs: Serial Control Register 0 (SCON0) and Serial Data Buffer 0 (SBUF0).
The single SBUF0 location provides access to both transmit and receive registers. Writes to SBUF0
always access the Transmit register. Reads of SBUF0 always access t he buffe red Receive register;
it is not possible to read data from the Transmit register.
With UART0 interrupts enabled, an interrupt is generated each time a transmit is completed (TI0 is set in
SCON0), or a data byte has been received (RI0 is set in SCON0). The UART0 interrupt flags are not
cleared by hardwa re when the CPU vectors to the in terrupt ser vice routine. They must be cle ared manually
by software, allowing software to determine the cause of the UART0 interrup t (transmit comp lete or receive
complete).
Figure 22.1. UART0 Block Diagram
UART Baud
Rate Generator
RI
SCON
RI
TI
RB8
TB8
REN
MCE
SMODE
Tx Control
Tx Clock Send
SBUF
(TX Shift)
Start
Data
Write to
SBUF
Crossbar
TX
Shift
Zero Detector
Tx IRQ
SET
QD
CLR
Stop Bit
TB8
SFR Bus
Serial
Port
Interrupt
TI Port I/O
Rx Control
Start
Rx Clock
Load
SBUF
Shift 0x1FF RB8
Rx IRQ
Input Shift Register
(9 bits)
Load SBUF
Read
SBUF
SFR Bus Crossbar
RX
SBUF
(RX Latch)
C8051F336/7/8/9
160 Rev.1.0
22.1. Enhanced Baud Rate Generation
The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by
TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 22.2), which is not user-
accessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates.
The RX Timer runs when Timer 1 is enabled, and uses the same reload value (TH1). However, an
RX Timer reload is forced when a START condition is detected on the RX pin. This allows a receive to
begin any time a START is detected, independent of the TX Timer state.
Figure 22.2. UART0 Baud Rate Logic
Timer 1 should be configured for Mode 2, 8-bit auto-reload (see Section “24.1.3. Mode 2: 8-bit
Counter/Timer with Auto-Reload” on page 184). The Timer 1 reload value should be set so that overflows
will occur at two times the desired UART baud rate frequency. Note that Timer 1 may be clocked by one of
six sources: SYSCLK, SYSCLK /4, SYSCLK/12, S YSCLK/48, the external oscillator clock/8, or an external
input T1. For any given Timer 1 clock source, the UART0 baud rate is determined by Equation 22.1-A and
Equation 22.1-B.
Equation 22.1. UART0 Baud Rate
Where T1CLK is the frequency of the clock supplied to Timer 1, and T1H is the high byte of Timer 1 (reload
value). Timer 1 clock frequency is selected as described in Section “24. Timers” on page 180. A quick ref-
erence for typical baud rates and system clock frequencies is given in Table 22.1 through Table 22.2. The
internal oscillator may still generate the system clock when the external oscillator is driving Timer 1.
RX Timer
Start
Detected
Overflow
Overflow
TH1
TL1 TX Clock
2
RX Clock
2
Timer 1 UART
UartBaudRate 1
2
---T1_Overflow_Rate×=
T1_Overflow_Rate T1CLK
256 TH1–
--------------------------
=
A)
B)
C8051F336/7/8/9
Rev.1.0 161
22.2. Operational Modes
UART0 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is
selected by the S0MODE bit (SCON0.7). Typical UART connection options are shown in Figure 22.3.
Figure 22.3. UART Interconnect Diagram
22.2.1. 8-Bit UART
8-Bit UART mode uses a tot al of 10 bits per dat a byte: one st art bit, e ight dat a bit s (LSB first) , and one stop
bit. Data are transmitted LSB first from the TX0 pin and received at the RX0 pin. On receive, the eight data
bits are stored in SBUF0 and the stop bit goes into RB80 (SCON0.2).
Data transmission begins when software writes a data byte to the SBUF0 register. The TI0 Transmit Inter-
rupt Flag ( SCON0.1) is set at th e end of the transm ission (the beginning of the stop-bit time). Data recep-
tion can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to logic 1. After the stop bit is
received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met:
RI0 must be logic 0, and if MCE0 is logic 1, the stop bit must be logic 1. In the event of a receive data over-
run, the first received 8 bits are latched into the SBUF0 receive register and the following overrun data bits
are lost.
If these condition s ar e me t, the eight bits of data is stored in SBUF0, the stop bit is stored in RB80 and the
RI0 flag is set. If these conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not
be set. An interrupt will occur if enabled when either TI0 or RI0 is set.
Figure 22.4. 8-Bit UART Timing Diagram
OR
RS-232 C8051xxxx
RS-232
LEVEL
XLTR
TX
RX
C8051xxxx
RX
TX
MCU RX
TX
D1D0 D2 D3 D4 D5 D6 D7
START
BIT
MARK STOP
BIT
BIT TI MES
BIT SAMPLING
SPACE
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22.2.2. 9-Bit UART
9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programma-
ble ninth data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in TB80
(SCON0.3), which is assigned by user so f twa re. It ca n be assigned the value of the p ari ty flag (bit P in reg-
ister PSW) for error detection, or used in multiprocessor communications. On receive, the ninth data bit
goes into RB80 (SCON0.2) and the stop bit is ignored.
Data transmission begins when an instruction writes a data byte to the SBUF0 register. The TI0 Transmit
Interrupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data
reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to 1. After the stop bit is
received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met:
(1) RI0 must be logic 0, an d (2) if MCE0 is logic 1, the 9th bit must be logic 1 (when M CE0 is logic 0 , the
state of the ninth data bit is unimportant). If these conditions are met, the eight bits of data are stored in
SBUF0, the ninth bit is stored in RB80, and the RI0 flag is set to 1. If the above conditions are not met,
SBUF0 and RB80 will not be loaded and the RI0 flag will not be set to 1. A UART0 interrupt will occur if
enabled when either TI0 or RI0 is set to 1.
Figure 22.5. 9-Bit UART Timing Diagram
D1D0 D2 D3 D4 D5 D6 D7
START
BIT
MARK STOP
BIT
BIT TIMES
BIT SAMPLING
SPACE D8
C8051F336/7/8/9
Rev.1.0 163
22.3. Multiprocessor Communications
9-Bit UART mode supports multiprocessor communication between a master processor and one or more
slave processors by special use of the ninth dat a bit. When a master p rocessor wants to transmit to one or
more slaves, it first sends an address byte to select the target(s). An address byte differs from a data byte
in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0.
Setting the MCE0 bit (SCON0.5) of a slave processor configures its UART such that when a stop bit is
received, the UART will generate an interrupt only if the ninth bit is logic 1 (RB80 = 1) signifying an address
byte has been received. In the UART interrupt handler, software will compare the received address with
the slave's own assigned 8-bit address. If the addresses match, the slave will clear its MCE0 bit to enable
interrupts on the reception of the following data byte(s). Slaves that weren't addressed leave their MCE0
bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring the
data. Once the entire message is received, the addressed slave resets its MCE0 bit to ignore all transmis-
sions until it receives the next address byte.
Multiple addresses ca n be assigned to a single slave and/or a single address can be assigned to multiple
slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. The master
processor can be configured to receive all transmissions or a protocol can be implemented such that the
master/slave role is temporarily reversed to enable half-duplex transmission between the original master
and slave(s).
Figure 22.6. UART Multi-Processor Mode Interconnect Diagram
Master
Device Slave
Device
TXRX RX TX
Slave
Device
RX TX
Slave
Device
RX TX
V+
C8051F336/7/8/9
164 Rev.1.0
SFR Address = 0x98; Bit-Addressable
SFR Definition 22.1. SCON0: Serial Port 0 Control
Bit76543210
Name S0MODE MCE0 REN0 TB80 RB80 TI0 RI0
Type R/W R R/W R/W R/W R/W R/W R/W
Reset 01000000
Bit Name Function
7S0MODE
Serial Port 0 Operation Mode.
Selects the UART0 Operation Mode.
0: 8-bit UART with Variable Baud Rate.
1: 9-bit UART with Variable Baud Rate.
6 Unused Unused. Read = 1b, Write = Don’t Care.
5MCE0
Multiprocessor Communication Enable.
The function of this bit is dependent on the Serial Port 0 Operation Mode:
Mode 0: Checks for valid stop bit.
0: Logic level of stop bit is ignored.
1: RI0 will only be activated if stop bit is logic level 1.
Mode 1: Multiprocessor Communications Enable.
0: Logic level of ninth bit is ignored.
1: RI0 is set and an interrupt is generated only when the ninth bit is logic 1.
4REN0
Receive Enable.
0: UART0 reception disabled.
1: UART0 reception ena bled.
3TB80
Ninth Transmission Bit.
The logic level of this bit will be sent as the ninth transmission bit in 9-bit UART Mode
(Mode 1). Unused in 8-bit mode (Mode 0).
2RB80
Ninth Receive Bit.
RB80 is assigned the value of the STOP bit in Mode 0; it is assigned the value of the
9th data bit in Mode 1.
1TI0
Transmit Interrupt Flag.
Set by hardware when a byte of data has been transmitted by UART0 (after the 8th bit
in 8-bit UART Mode, or at the beginning of the STOP bit in 9-bit UART Mode). When
the UART0 in terrupt is enable d, setting this bit causes the CPU to vector to the UAR T0
interrupt se rvic e ro ut ine . This bit must be cleared manually by software.
0RI0
Receive Interrupt Flag.
Set to 1 by hardware when a byte of data has been received by UART0 (set at the
STOP bit sampling time). When the UART0 interrupt is enabled, setting this bit to 1
causes the CPU to vector to the UART0 interrupt service routine. This bit must be
cleared manually by software.
C8051F336/7/8/9
Rev.1.0 165
SFR Address = 0x99
SFR Definition 22.2. SBUF0: Serial (UART0) Port Data Buffer
Bit76543210
Name SBUF0[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 SBUF0[7:0] Serial Data Buffer Bits 7–0 (MSB–LSB).
This SFR accesses two registers; a transmit shift register a nd a receive latch reg ister .
When data is written to SBUF0, it goes to the transmit shift register and is held for
serial transmission. Writing a byte to SBUF0 initiates the transmission. A read of
SBUF0 returns the contents of the receive latch.
C8051F336/7/8/9
166 Rev.1.0
Table 22.1. Timer Settings for Standard Baud Rates
Using The Internal 24.5 MHz Oscillator
Frequency: 24.5 MHz
Target
Baud Rate
(bps)
Baud Rate
% Error Oscillator
Divide
Factor
Timer Clock
Source SCA1–SCA0
(pre-scale
select)1
T1M1Timer 1
Reload
Value (hex)
SYSCLK from
Internal Osc.
230400 –0.32% 106 SYSCLK XX21 0xCB
115200 –0.32% 212 SYSCLK XX 1 0x96
57600 0.15% 426 SYSCLK XX 1 0x2B
28800 –0.32% 848 SYSCLK/4 01 0 0x96
14400 0.15% 1704 SYSCLK/12 00 0 0xB9
9600 –0.32% 2544 SYSCLK/12 00 0 0x96
2400 –0.32% 10176 SYSCLK/48 10 0 0x96
1200 0.15% 20448 SYSCLK/48 10 0 0x2B
Notes:
1. SCA1–SCA0 and T1M bit definitions can be found in Section 24.1.
2. X = Don’t care.
Table 22.2. Timer Settings for Standard Baud Rates
Using an External 22.1184 MHz Oscillator
Frequency: 22.1184 MHz
Target
Baud Rate
(bps)
Baud Rate
% Error Oscillator
Divide
Factor
Timer Clock
Source SCA1–SCA0
(pre-scale
select)1
T1M1Timer 1
Reload
Value (hex)
SYSCLK from
External Osc.
230400 0.00% 96 SYSCLK XX210xD0
115200 0.00% 192 SYSCLK XX 1 0xA0
57600 0.00% 384 SYSCLK XX 1 0x40
28800 0.00% 768 SYSCLK / 12 00 0 0xE0
14400 0.00% 1536 SYSCLK / 12 00 0 0xC0
9600 0.00% 2304 SYSCLK / 12 00 0 0xA0
2400 0.00% 9216 SYSCLK / 48 10 0 0xA0
1200 0.00% 18432 SYSCLK / 48 10 0 0x40
SYSCLK from
Internal Osc.
230400 0.00% 96 EXTCLK / 8 11 0 0xFA
115200 0.00% 192 EXTCLK / 8 11 0 0xF4
57600 0.00% 384 EXTCLK / 8 11 0 0xE8
28800 0.00% 768 EXTCLK / 8 11 0 0xD0
14400 0.00% 1536 EXTCLK / 8 11 0 0xA0
9600 0.00% 2304 EXTCLK / 8 11 0 0x70
Notes:
1. SCA1–SCA0 and T1M bit definitions can be found in Section 24.1.
2. X = Don’t care.
C8051F336/7/8/9
Rev.1.0 167
23. Enhanced Serial Peripheral Interface (SPI0)
The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous
serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports mul-
tiple masters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input
to select SPI0 in slave mode, or to disable Master Mode operation in a multi-master environment, avoiding
contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can
also be conf igured as a ch ip-select ou tput in master mode, or disabled fo r 3-wire operation. Addi tional gen-
eral purpose port I/O pins can be used to select multiple slave devices in master mode.
Figure 23.1. SPI Block Diagram
SFR Bus
Data Path
Control
SFR Bus
Write
SPI0DAT
Receive Data Buffer
SPI0DAT
01234567 Shift Register
SPI CONTROL LOGIC
SPI0CKR
SCR7
SCR6
SCR5
SCR4
SCR3
SCR2
SCR1
SCR0
SPI0CFG SPI0CN
Pin Interface
Control
Pin
Control
Logic
C
R
O
S
S
B
A
R
Port I/O
Read
SPI0DAT
SPI IRQ
Tx Data
Rx Data
SCK
MOSI
MISO
NSS
Transmit Data Buffer
Clock Divide
Logic
SYSCLK
CKPHA
CKPOL
SLVSEL
NSSMD1
NSSMD0
SPIBSY
MSTEN
NSSIN
SRMT
RXBMT
SPIF
WCOL
MODF
RXOVRN
TXBMT
SPIEN
C8051F336/7/8/9
168 Rev.1.0
23.1. Signal Descriptions
The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below.
23.1.1. Master Out, Slave In (MOSI)
The master-out, slave-in (MOSI) signal is an output from a master d evice an d an in put to s lave d evices. I t
is used to serially trans fer data from the ma ster to th e slave. This signal is an output when SPI0 is operat-
ing as a master and an input when SPI0 is operating as a slave. Data is transferred most-significant bit
first. When configured as a master, MOSI is driven by the MSB of the shift register in both 3- and 4-wire
mode.
23.1.2. Master In, Slave Out (MISO)
The master-in, slave-out (MISO) signal is an output from a slave device and an input to the master device.
It is used to serially transfer data from the slave to the master. This signal is an input when SPI0 is operat-
ing as a master and an output when SPI0 is operating as a slave. Data is transferred most-sig nificant bit
first. The MISO pin is placed in a high-impeda nce sta te when the SPI module is di sabled and when th e SPI
operates in 4-wire mode as a slave that is not selected. When acting as a slave in 3-wire mode, MISO is
always driven by the MSB of the shift register.
23.1.3. Serial Clock (SCK)
The serial cl ock (SCK) signal is an outp ut from the ma ster device and an input to slave devices. It is used
to synchronize the transfer of data between the master and slave on the MOSI and MISO lines. SPI0 gen-
erates this signal when operating as a master. The SCK signal is ignored by a SPI slave when the slave is
not selected (NSS = 1) in 4-wire slave mode.
23.1.4. Slave Select (NSS)
The function of the slave-select (NSS) signal is dependent on the setting of the NSSMD1 and NSSMD0
bits in the SPI0CN register. There are three possible modes that can be selected with these bits:
1. NSSMD[1:0] = 00: 3-Wire Master or 3-Wire Slave Mode: SPI0 operates in 3-wire mode, and NSS is
disabled. When operating as a slave device, SPI0 is always selected in 3-wire mode. Since no select
signal is present, SPI0 must be the only slave on the bus in 3-wir e mode. This is intended for point-to-
point communication between a master and one slave.
2. NSSMD[1:0] = 01: 4-Wire Slave or Multi-Master Mode: SPI0 operates in 4-wire mode, and NSS is
enabled as an input. When operating as a slave, NSS selects the SPI0 device. When operating as a
master, a 1-to-0 transition of the NSS signal disables the master function of SPI0 so that multiple
master devices can be used on the same SPI bus.
3. NSSMD[1:0] = 1x: 4-Wire Master Mode: SPI0 operates in 4-wire mode, and NSS is enab led as an
output. The setting of NSSMD0 determines what logic level the NSS pin will output. This configuration
should only be used when operating SPI0 as a master device.
See Figure 23.2, Figure 23.3, and Figure 23.4 for typical connection diagrams of the various operational
modes. Note that the setting of NSSMD bits affect s the pinou t of the device. When in 3-wir e maste r or
3-wire slave mode, the NSS pin will not be mapped by the crossbar. In all other modes, the NSS signal will
be mapped to a pin on the device. See Section “20. Port Input/Output” on page 119 for general purpose
port I/O and crossbar information.
C8051F336/7/8/9
Rev.1.0 169
23.2. SPI0 Master Mode Operation
A SPI master device initiates all data transfe r s o n a SPI bu s. SPI0 is p lac ed in m ast er m od e by se ttin g the
Master Enable flag (MSTEN, SPI0CN.6). Writing a byte of data to the SPI0 data register (SPI0DAT) when
in master mode writes to the transmit buffer. If the SPI shift register is empty, the byte in the transmit buff er
is moved to the shift registe r, and a data transfer begins. The SPI0 master immediately shifts out the data
serially on the MOSI line while providing the serial clock on SCK. The SPIF (SPI0CN.7) flag is set to logic
1 at the end of the transfer. If interrupts are enabled, an interrupt request is generated when the SPIF flag
is set. While the SPI0 master transfers data to a slave on the MOSI line, the addressed SPI slave device
simultaneously transfer s the content s of it s sh if t register to the SPI master on the MISO line in a full-duplex
operation. Therefore, the SPIF flag serves as both a transmit-complete and receive-data-ready flag. The
data byte received from the slave is transferred MSB-first into the master's shift register. When a byte is
fully shifted into the register, it is moved to the receive buffer where it can be read by the processor by
reading SPI0DAT.
When configured as a master, SPI0 can operate in one of three dif ferent mode s: multi-master mode, 3-wir e
single-master mode, and 4-wire single-master mode. The default, multi-master mode is active when NSS-
MD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In this mode, NSS is an input to the device, and is
used to disable th e master SPI0 when anothe r master is accessing th e bus. When NSS is pulled low in this
mode, MSTEN (SPI0CN.6) and SPIEN (SPI0CN.0) are set to 0 to disable the SPI master device, and a
Mode Fault is generated (MODF, SPI0CN.5 = 1). Mode Fault will generate an interrupt if enabled. SPI0
must be manually re-enabled in software under these circumstances. In multi-master systems, devices will
typically default to being sla ve devices while th ey are not a cting as the system master device . In multi -mas-
ter mode, slave devices can be addressed individually (if needed) using general-purpose I/O pins.
Figure 23.2 shows a connection diagram between two master devices in multiple-master mode.
3-wire single-m aster mod e is active wh en NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. In this
mode, NSS is not used, an d is not mapped to an external por t pin through the crossbar. Any slave devices
that must be addressed in this mode should be selected using general-purpose I/O pins. Figure 23.3
shows a connection diagram between a master device in 3-wire master mode and a slave device.
4-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 1. In this mode, NSS is configured as an
output pin, and can be used as a slave-select signal for a single SPI device. In this mode, the output value
of NSS is controlled (in software) with the bit NSSMD0 (SPI0CN.2). Additional slave devices can be
addressed using gene ral-p urpose I/O p ins. Figur e 23.4 shows a con nection diag ram for a ma ster device i n
4-wire master mode and two slave devices.
Figure 23.2. Multiple-Master Mode Connection Diagram
Master
Device 2
Master
Device 1 MOSI
MISO
SCK
MISO
MOSI
SCK
NSS
GPIO NSS
GPIO
C8051F336/7/8/9
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Figure 23.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection
Diagram
Figure 23.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection
Diagram
23.3. SPI0 Slave Mode Operation
When SPI0 is enabled and not configured as a master, it will operate as a SPI slave. As a slave, bytes are
shifted in through the MOSI pin and out through the MISO pin by a master device controlling the SCK sig-
nal. A bit counte r in the SPI0 logic cou nts SCK edges. When 8 bits have been shif ted thro ugh the shif t reg-
ister, the SPIF flag is set to logic 1, and the byte is copied into the receive buffer. Data is read from the
receive buffer by reading SPI0DAT. A slave device cannot initiate transfers. Data to be transferred to the
master device is pre-loaded into the shift register by writing to SPI0DAT. Writes to SPI0DAT are double-
buffe red, and are placed in the transmit bu f fer first. If the shif t re gister is e mpty, the content s o f the tra nsmit
buffer will immediately be transferred into the shift register. When the shift register already contains data,
the SPI will load the shift register with the transmit buffer’s contents after the last SCK edge of the next (or
current) SPI transfer.
When configured as a slave, SPI0 can be configured for 4-wire or 3-wire operation. The default, 4-wire
slave mode, is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In 4- wire mode, the
NSS signal is routed to a port pin and configured as a digital input. SPI0 is enabled when NSS is logic 0,
and disabled when NSS is logic 1. The bit counter is reset on a falling edge of NSS. Note that the NSS sig-
nal must be driven low at least 2 system clocks before the first active edge of SCK for each byte transfer.
Figure 23.4 shows a connection diagram between two slave devices in 4-wire slave mode and a master
device.
Slave
Device
Master
Device MOSI
MISO
SCK
MISO
MOSI
SCK
Slave
Device
Master
Device MOSI
MISO
SCK
MISO
MOSI
SCK
NSS NSS
GPIO
Slave
Device
MOSI
MISO
SCK
NSS
C8051F336/7/8/9
Rev.1.0 171
3-wire slave mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. NSS is not
used in this mode, and is not mapped to an external port pin through the crossbar. Since there is no way of
uniquely addressing the device in 3-wire slave mode, SPI0 must be the only slave device present on the
bus. It is important to note that in 3-wire slave mode there is no external means of resetting the bit counter
that determines when a full byte has been received. The bit counter can only be reset by disabling and re-
enabling SPI0 with the SPIEN bit. Figure 23.3 shows a connection diagram between a slave device in 3-
wire slave mod e and a ma ster device.
23.4. SPI0 Interrupt Sources
When SPI0 interrupts are enabled, the following four flags will generate an interrupt when they are set to
logic 1:
All of the following bits must be cleared by software.
The SPI Interrupt Flag, SPIF (SPI0CN.7) is set to logic 1 at the end of each byte transfer. This flag can
occur in all SPI0 modes.
The Write Collision Flag, WCOL (SPI0CN.6) is set to logic 1 if a write to SPI0DAT is attempted when
the transmit buffer has not been emptied to the SPI shift register. When this occurs, the write to
SPI0DAT will be ignored, and the transmit buffer will not be written.This flag can occur in all SPI0
modes.
The Mode Fault Flag MODF (SPI0CN.5) is set to logic 1 when SPI0 is configured as a master, and for
multi-master mode and the NSS pin is pulled low. When a Mode Fault occurs, the MSTEN and SPIEN
bits in SPI0CN are set to logic 0 to disable SPI0 and allow another master device to access the bus.
The Receive Overrun Flag RXOVRN (SPI0CN.4) is set to logic 1 when configured as a slave, and a
transfer is completed and the receive buffer still holds an unread byte from a previous transfer. The new
byte is not transferred to the re ceive buffer, allowing the previously received data byte to be read. The
data byte which caused the overrun is lost.
23.5. Serial Clock Phase and Polarity
Four combinations of serial clock phase and polarity can be selected using the clock control bits in the
SPI0 Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.5) selects one of two clock phases
(edge used to latch the data). The CKPOL bit (SPI0CFG.4) selects between an active-high or active-low
clock. Both master and slave devices must be configured to use the same clock phase and polarity. SPI0
should be disabled (by clearing the SPIEN bit, SPI0CN.0) when changing the clock phase or polarity. The
clock and data line relationship s for master mode are shown in Figure 23.5. For slave mode, the clock and
data relationships are shown in Figure 23.6 and Figure 23.7. Note that CKPHA should be set to 0 on both
the master and slave SPI when communicating between two Silicon Labs C8051 devices.
The SPI0 Clock Rate Register (SPI0CKR) as shown in SFR Definition 23.3 controls the master mode
serial clock frequency. This register is ignored when operating in slave mode. When the SPI is configured
as a master, the maximum data transfe r rate (bit s/sec) is one-half the system clock frequency or 12.5 MHz,
whichever is slower. When the SPI is configured as a slave, the maximum data transfer rate (bits/sec) for
full-duplex operation is 1/10 the system clock frequency, provided that the master issues SCK, NSS (in 4-
wire slave mode), and the serial input data synchronously with the slave’s system clock. If the master
issues SCK, NSS, and the serial input data asynchronously, the maximum data transfer rate (bits/sec)
must be less than 1/10 the system clock frequency. In the special case where the master only wants to
transmit data to the slave and does no t need to receive data from the slave (i.e. half-duplex operation), the
SPI slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency.
This is provided that the master issues SCK, NSS, and the seri al input data synchronously with the slave’s
system clock.
C8051F336/7/8/9
172 Rev.1.0
Figure 23.5. Master Mode Data/Clock Timing
Figure 23.6. Slave Mode Data/Clock Timing (CKPHA = 0)
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=0)
SCK
(CKPOL=1, CKPHA=1)
MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MISO/MOSI
NSS (Must Remain High
in Multi-Master Mode)
MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MISO
NSS (4-Wire Mode)
MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MOSI
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=1, CKPHA=0)
C8051F336/7/8/9
Rev.1.0 173
Figure 23.7. Slave Mode Data/Clock Timing (CKPHA = 1)
23.6. SPI Special Function Registers
SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN
Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate
Register. The four special function registers related to the operation of the SPI0 Bus are described in the
following figures.
SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=1)
MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 B it 0MISO
NSS (4-Wire Mode)
MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MOSI
C8051F336/7/8/9
174 Rev.1.0
SFR Address = 0xA1
SFR Definition 23.1. SPI0CFG: SPI0 Configuration
Bit7654321 0
Name SPIBSY MSTEN CKPHA CKPOL SLVSEL NSSIN SRMT RXBMT
Type R R/W R/W R/W R R R R
Reset 0000011 1
Bit Name Function
7 SPIBSY SPI Busy.
This bit is set to logic 1 when a SPI transfer is in progress (master or slave mode).
6 MSTEN Master Mode Enable.
0: Disable master mo de . Op er at e in slave mode.
1: Enable master mode. Operate as a master.
5 CKPHA SPI0 Clock Phase.
0: Data centered on first edge of SCK period.*
1: Data centered on secon d edge of SCK period.*
4CKPOL
SPI0 Clock Polarity.
0: SCK line low in idle state.
1: SCK line high in idle state.
3 SLVSEL Slave Selected Flag.
This bit is set to logic 1 whenever th e NSS pin is low indicating SPI0 is the selected
slave. It is cleared to logic 0 when NSS is high (slave not selected). This bit does
not indicate the instantaneous value at the NSS pin, but rather a de-glitched ver-
sion of the pin input.
2 NSSIN NSS Inst antaneous Pin Input.
This bit mimics the instantaneous value that is present on the NSS port pin at the
time that the register is read. This input is not de-glitched.
1SRMT
Shift Register Empty (valid in slave mode only).
This bit will be set to logic 1 when all data has been transferred in/out of the shift
register, and there is no new information available to read from the transmit buffer
or write to the receive buffer. It returns to logic 0 when a data byte is transferred to
the shift re gister from the transmit buf fer or by a transition on SCK. SRMT = 1 when
in Master Mode.
0 RXBMT Receive Buffer Empty (valid in slave mode only).
This bit will be set to logic 1 when the receive buffer has been read and contains no
new information. If there is new information available in the receive buffer that has
not been read, this bit will return to logic 0. RXBMT = 1 when in Master Mode.
Note: In slave mode, data on MOSI is sampled in t he center of each data bit. In master mode, data on MISO is
sampled one SYSCLK before the end of each data bit, to provide maximum settling time for the slave device.
See Table 23.1 for timing parameters.
C8051F336/7/8/9
Rev.1.0 175
SFR Address = 0xF8; Bit-Addressable
SFR Definition 23.2. SPI0CN: SPI0 Control
Bit7654321 0
Name SPIF WCOL MODF RXOVRN NSSMD[1:0] TXBMT SPIEN
Type R/W R/W R/W R/W R/W R R/W
Reset 0000011 0
Bit Name Function
7 SPIF SPI0 Interrupt Flag.
This bit is set to logic 1 by hardware at the end of a data transfer. If SPI interrupts
are enabled, an interrupt will be generated. This bit is not automatically cleared by
hardware, and must be cleared by software.
6WCOL
Write Collision Flag.
This bit is set to logic 1 if a write to SPI0DAT is attempted when TXBMT is 0. When
this occurs, the write to SPI0DAT will be ignored, and the transmit buf f er will not be
written. If SPI interrupts are enabled, an interrupt will be generated. This bit is not
automatically cleared by hard ware, and must be cleared by software.
5MODF
Mode Fault Flag.
This bit is set to logic 1 by hardware when a master mode collision is detected
(NSS is low, MSTEN = 1, and NSSMD[1:0] = 01). If SPI interrupts are enabled, an
interrupt will be generated. This bit is not automatically cleared by hardware, and
must be cleared by software.
4 RXOVRN Receive Overrun Flag (valid in slave mode only).
This bit is set to logic 1 by hardware when the receive buffer still holds unread data
from a previous transfer and th e last bi t of the current transfer is shifted into the
SPI0 shift register. If SPI interrupts are enabled, an interrupt will be generated. This
bit is not automatic ally cleared by ha rd wa re , an d mu st be clear ed by software.
3:2 NSSMD[1:0] Slave Select Mode.
Selects be tween the following NSS operation modes:
(See Section 23.2 and Section 23.3).
00: 3-Wire Slave or 3-Wire Master Mode. NSS signal is no t routed to a port pin.
01: 4-Wire Slave or Multi-Master Mode (Default). NSS is an input to the device.
1x: 4-Wire Single-Master Mode. NSS signal is mapped as an output from the
device and will assume the value of NSSMD0.
1 TXBMT Transmit Buffer Empty.
This bit will be set to logic 0 when new data has been written to the transmit buf fer.
When data in the transmit buffer is transferred to the SPI shift register, this bit will
be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer.
0 SPIEN SPI0 Enable.
0: SPI disabled.
1: SPI enabled.
C8051F336/7/8/9
176 Rev.1.0
SFR Address = 0xA2
SFR Address = 0xA3
SFR Definition 23.3. SPI0CKR: SPI0 Clock Rate
Bit7654321 0
Name SCR[7:0]
Type R/W
Reset 0000000 0
Bit Name Function
7:0 SCR[7:0] SPI0 Clock Rate.
These bits determine the frequency of the SCK output when the SPI0 module is
configured for master mode operation. The SCK clock frequency is a divided ver-
sion of the system clock, and is given in the following equation, where SYSCLK is
the system clock frequency and SPI0CKR is the 8-bit value held in the SPI0CKR
register.
for 0 <= SPI0CKR <= 255
Example: If SYSCLK = 2 MHz and SPI0CKR = 0x04,
SFR Definition 23.4. SPI0DAT: SPI0 Data
Bit7654321 0
Name SPI0DAT[7:0]
Type R/W
Reset 0000000 0
Bit Name Function
7:0 SPI0DAT[7:0] SPI0 Transmit and Receive Data.
The SPI0DAT register is used to transmit and receive SPI0 data. Writing data to
SPI0DAT places the data into the transmit buffer and initiates a transfer when in
Master Mode. A read of SPI0DAT returns the contents of the receive buffer.
fSCK SYSCLK
2 SPI0CKR[7:0] 1+()×
-----------------------------------------------------------
=
fSCK 2000000
241+()×
--------------------------
=
fSCK 200kHz=
C8051F336/7/8/9
Rev.1.0 177
Figure 23.8. SPI Master Timing (CKPHA = 0)
Figure 23.9. SPI Master Timing (CKPHA = 1)
SCK*
TMCKH TMCKL
MOSI
TMIS
MISO
* SCK is shown for CKPOL = 0. SCK is the o pposite polarity for CKPOL = 1.
TMIH
SCK*
TMCKH TMCKL
MISO
TMIH
MOSI
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
TMIS
C8051F336/7/8/9
178 Rev.1.0
Figure 23.10. SPI Slave Timing (CKPHA = 0)
Figure 23.11. SPI Slave Timing (CKPHA = 1)
SCK*
TSE
NSS
TCKH
TCKL
MOSI
TSIS TSIH
MISO
TSD
TSOH
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
TSEZ TSDZ
SCK*
TSE
NSS
TCKH
TCKL
MOSI
TSIS TSIH
MISO
TSD
TSOH
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
TSLH
TSEZ TSDZ
C8051F336/7/8/9
Rev.1.0 179
Table 23.1. SPI Slave Ti ming Parameters
Parameter Description Min Max Units
Master Mode Timing (See Figure 23.8 and Figure 23.9)
TMCKH SCK High Time 1 x TSYSCLK —ns
TMCKL SCK Low Time 1 x TSYSCLK —ns
TMIS MISO Valid to SCK Shift Edge 1 x TSYSCLK + 20 — ns
TMIH SCK Shift Edge to MISO Change 0 — ns
Slave Mode Timing (See Figure 23.10 and Figure 23.11)
TSE NSS Falling to First SCK Edge 2 x TSYSCLK —ns
TSD Last SCK Edge to NSS Rising 2 x TSYSCLK —ns
TSEZ NSS Falling to MISO Valid — 4 x TSYSCLK ns
TSDZ NSS Rising to MISO High-Z — 4 x TSYSCLK ns
TCKH SCK High Time 5 x TSYSCLK —ns
TCKL SCK Low Time 5 x TSYSCLK —ns
TSIS MOSI Valid to SCK Sample Edge 2 x TSYSCLK —ns
TSIH SCK Sample Edge to MOSI Change 2 x TSYSCLK —ns
TSOH SCK Shift Edge to MISO Change — 4 x TSYSCLK ns
TSLH Last SCK Edge to MISO Change
(CKPHA = 1 ONLY) 6 x TSYSCLK 8 x TSYSCLK ns
Note: TSYSCLK is equal to one period of the device system clock (SYSCLK).
C8051F336/7/8/9
Rev.1.0 180
24. Timers
Each MCU includes four counter/timers: two are 16-bit counter/timers compatible with those found in the
standard 8051, and two are 16-bit auto-reload timer for use with the ADC, SMBus, or for general purpose
use. These timers can be used to measure time intervals, count external events and generate periodic
interrupt requests. Timer 0 and Timer 1 are nearly identical and have four primary modes of operation.
Timer 2 and Timer 3 offer 16-bit and split 8-bit timer functionality with auto-reload. Additionally, Timer 3
offers the ability to be clocked from the external oscillator while the device is in Suspend mode, and can be
used as a wake-up source. This allows for implementation of a very low-power system, including RTC
capability.
Timers 0 and 1 may be clocked by one of five sources, determined by the Timer Mode Select bits (T1M–
T0M) and the Clock Scale bits (SCA1–SCA0). The Clock Scale bits define a pre-scaled clock from which
Timer 0 and/or Timer 1 may be clocked (See SFR Definition 24.1 for pre-scaled clock selection).
Timer 0/1 may then be configured to use this pre-scaled clock signal or the system clock. Timer 2 and
Timer 3 may be clocked by the system clock, the system clock divided by 12, or the external oscillator
clock source divided by 8.
Timer 0 and Timer 1 may also be operated as counters. When functioning as a counter, a counter/timer
register is incr emented on each hi gh-to-low tran sition at the sele cted input pin ( T0 or T1). Event s with a fre-
quency of up to one-fourth the system clock frequency can be counted. The input signal need not be peri-
odic, but it should be held at a given level for at least two full system clock cycles to ensure the level is
properly sampled.
Timer 0 and Timer 1 Modes: Timer 2 Modes: Timer 3 Modes:
13-bit counter/timer 16-b it tim er with au to -r elo a d 16-bit timer with au to -r eloa d
16-bit counter/timer
8-bit counter/timer with auto-
reload Two 8-bit timers with auto-reload Two 8-bit timers with auto-reload
Two 8-bit counter/timers (Timer 0
only)
C8051F336/7/8/9
181 Rev.1.0
SFR Address = 0x8E
SFR Definition 24.1. CKCON: Clock Control
Bit76543210
Name T3MH T3ML T2MH T2ML T1M T0M SCA[1:0]
Type R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7T3MH
Timer 3 High Byte Clock Select.
Selects the clock supplied to the Timer 3 high byte (split 8-bit timer mode only).
0: Timer 3 high byte uses the clock defined by the T3XCLK bit in TMR3CN.
1: Timer 3 high byte uses the system clock.
6T3ML
Timer 3 Low Byte Clock Select.
Selects the clock supplied to Timer 3. Selects the clock supplied to the lower 8-bit timer
in split 8-bit timer mode.
0: Timer 3 low byte uses the clock defined by the T3XCLK bit in TMR3CN.
1: Timer 3 low byte uses the system clock.
5T2MH
Timer 2 High Byte Clock Select.
Selects the clock supplied to the Timer 2 high byte (split 8-bit timer mode only).
0: Timer 2 high byte uses the clock defined by the T2XCLK bit in TMR2CN.
1: Timer 2 high byte uses the system clock.
4T2ML
Timer 2 Low Byte Clock Select.
Selects the clock supplied to Timer 2. If Timer 2 is configured in split 8-bit timer mode,
this bit selects the clock supplied to the lower 8-bit timer.
0: Timer 2 low byte uses the clock defined by the T2XCLK bit in TMR2CN.
1: Timer 2 low byte uses the system clock.
3T1
Timer 1 Clock Select.
Selects the clock source supplied to Timer 1. Ignored when C/T1 is set to ’1’.
0: Timer 1 uses the clock defined by the prescale bits SCA[1:0].
1: Timer 1 uses the system clock.
2T0
Timer 0 Clock Select.
Selects the clock source supplied to Timer 0. Ignored when C/T0 is set to ’1’.
0: Counter/Timer 0 uses the clock defined by the prescale bits SCA[1:0].
1: Counter/Timer 0 uses the system clock.
1:0 SCA[1:0] Timer 0/1 Prescale Bits.
These bits control the Timer 0/1 Clock Prescaler :
00: System clock divided by 12
01: System clock divided by 4
10: System clock divided by 48
11: External clock divided by 8 (synchronized with the system clock)
C8051F336/7/8/9
Rev.1.0 182
24.1. Timer 0 and Timer 1
Each timer is implemented as a 16-bit register accessed as two separate bytes: a low byte (TL0 or TL1)
and a high byte (TH0 or TH1). The Counter/Timer Control register (TCON) is used to enable Timer 0 and
Tim er 1 as well as indica te status. Timer 0 interrupts can be enabled b y settin g the ET0 bit in the I E regis-
ter (Section “15.2. Interrupt Re gister Descriptio ns” on page 8 4); Time r 1 in terrupts can be enabled by set-
ting the ET1 bit in the IE register (Section “15.2. Interrupt Register Descriptions” on page 84). Both
counter/timers operate in on e of four primary modes selected by setting the Mode Select bits T1M1–T0M0
in the Counter/Timer Mode register (TMOD). Each timer can be configured independently. Each operating
mode is described below.
24.1.1. Mode 0: 13-bit Counter/Timer
Timer 0 and Timer 1 operate as 13-bit counter/timers in Mode 0. The following describes the configuration
and operation of Timer 0. However, both timers operate identically, and Timer 1 is configured in the same
manner as described for Timer 0.
The TH0 register holds the eight MSBs of the 13-bit counter/timer. TL0 holds the five LSBs in bit positions
TL0.4–TL0.0. The three upper bits of TL0 (TL0.7–TL0.5) are indeterminate and should be masked out or
ignored when reading. As the 13-bit timer register increments and overflows from 0x1FFF (all ones) to
0x0000, the timer overflow flag TF0 in TCON is set and an interrupt will occur if Timer 0 interrupts are
enabled.
The C/T0 bit in the TMOD register selects the counter/timer's clock source. When C/T0 is set to logic 1,
high-to-low tr ansitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to Section
“20.3. Priority Crossbar Decoder” on page 124 for information on selecting and configuring external I/O
pins). Clearing C/T selects the clock defined by the T0M bit in register CKCON. When T0M is set, Timer 0
is clocked by the system clock. When T0M is cleared, Timer 0 is clocked by the source selected by the
Clock Scale bits in CKCON (see SFR Definition 24.1).
Setting the TR0 bit (TCON.4) enables the timer when either GATE0 in the TMOD register is logic 0 or the
input signal INT0 is active as defined by bit IN0PL in register IT01CF (see SFR Definition 15.5). Setting
GATE0 to 1 allows the timer to be controlled by the external input signal INT0 (see Section “15.2. Interrupt
Register Descriptions” on page 84), facilitating pulse width measurements
Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial
value before the timer is enabled.
TL1 and TH1 form the 13-bit reg ister for Timer 1 in the same manner as described above fo r TL0 and TH0.
Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The
input signal INT0 is used with Timer 1; the /INT1 polarity is defined by bit IN1PL in register IT01CF (see
SFR Definition 15.5).
TR0 GATE0 INT0 Counter/Timer
0 X X Disabled
1 0 X Enabled
1 1 0 Disabled
1 1 1 Enabled
Note: X = Don't Care
C8051F336/7/8/9
183 Rev.1.0
Figure 24.1. T0 Mode 0 Block Diagram
24.1.2. Mode 1: 16-bit Counter/Timer
Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The
counter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0.
TCLK TL0
(5 bits) TH0
(8 bits)
TCON
TF0
TR0
TR1
TF1
IE1
IT1
IE0
IT0
Interrupt
TR0
0
1
0
1
SYSCLK
Pre-scaled Clock
TMOD
T
1
M
1
T
1
M
0
C
/
T
1
G
A
T
E
1
G
A
T
E
0
C
/
T
0
T
0
M
1
T
0
M
0
GATE0
/INT0
T0
Crossbar
IT01CF
I
N
1
S
L
1
I
N
1
S
L
0
I
N
1
S
L
2
I
N
1
P
L
I
N
0
P
L
I
N
0
S
L
2
I
N
0
S
L
1
I
N
0
S
L
0
IN0PL XOR
T0M
C8051F336/7/8/9
Rev.1.0 184
24.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload
Mode 2 configures T ime r 0 and T imer 1 to operate as 8-bit counter/timers with automatic reload of the start
value. TL0 holds the count and TH0 holds the reload value. When the counter in TL0 overflows from all
ones to 0x00, the timer overflow flag TF0 in the TCON register is set and the counter in TL0 is reloaded
from TH0. If Timer 0 interrupts are enabled, an interrupt will occur when the TF0 flag is set. The reload
value in TH0 is not changed. TL0 must be initialized to the desired value before enabling the timer for the
first count to be correct. When in Mode 2, Timer 1 operates identically to Timer 0.
Both counter/timers are enabled and configured in Mode 2 in the same manner as Mode 0. Setting the
TR0 bit (TC ON.4) e nables th e timer when either GATE0 in the TMOD register is logic 0 or when the input
signal INT0 is active as defined by bit IN0PL in register IT01CF (see Section “15.3. External Interrupts
/INT0 and /INT1” on page 89 for details on the external input signals INT0 and INT1).
Figure 24.2. T0 Mode 2 Block Diagram
TCLK
TMOD
T
1
M
1
T
1
M
0
C
/
T
1
G
A
T
E
1
G
A
T
E
0
C
/
T
0
T
0
M
1
T
0
M
0
TCON
TF0
TR0
TR1
TF1
IE1
IT1
IE0
IT0
Interrupt
TL0
(8 bits)
Reload
TH0
(8 bits)
0
1
0
1
SYSCLK
Pre-scaled Clock
IT01CF
I
N
1
S
L
1
I
N
1
S
L
0
I
N
1
S
L
2
I
N
1
P
L
I
N
0
P
L
I
N
0
S
L
2
I
N
0
S
L
1
I
N
0
S
L
0
TR0
GATE0
IN0PL XOR
/INT0
T0
Crossbar
T0M
C8051F336/7/8/9
185 Rev.1.0
24.1.4. Mode 3: Two 8-bit Counter/Timers (T imer 0 Only)
In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The
counter/timer in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD: TR0, C/T0,
GATE0 and TF0. TL0 can use either the system clock or an e xter nal input signal as its timebase. The TH0
register is restricted to a timer function sourced by the system clock or prescaled clock. TH0 is enabled
using the Timer 1 run control bit TR1. TH0 sets the Timer 1 overflow flag TF1 on overflow and thus controls
the Timer 1 interrupt.
Timer 1 is inactive in Mode 3. When Timer 0 is operating in Mode 3, Timer 1 can be operated in Modes 0,
1 or 2, but cannot be clocked by external signals nor set the TF1 flag and generate an interrupt. However,
the Timer 1 overflow can be used to generate baud rates for the SMBus and/or UART, and/or initiate ADC
conversions. While Timer 0 is operating in Mode 3, Timer 1 run control is handled through its mode set-
tings. To run Timer 1 while Timer 0 is in Mode 3, set the Timer 1 Mode as 0, 1, or 2. To disable Timer 1,
configure it for Mode 3.
Figure 24.3. T0 Mode 3 Block Diagram
TL0
(8 bits)
TMOD
0
1
TCON
TF0
TR0
TR1
TF1
IE1
IT1
IE0
IT0
Interrupt
Interrupt
0
1
SYSCLK
Pre-scaled Clock TR1 TH0
(8 bits)
T
1
M
1
T
1
M
0
C
/
T
1
G
A
T
E
1
G
A
T
E
0
C
/
T
0
T
0
M
1
T
0
M
0
TR0
GATE0
IN0PL XOR
/INT0
T0
Crossbar
T0M
C8051F336/7/8/9
Rev.1.0 186
SFR Address = 0x88; Bit-Addressable
SFR Definition 24.2. TCON: Timer Control
Bit76543210
Name TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7 TF1 Timer 1 Overflow Flag.
Set to 1 by hardware when Timer 1 overflows. This flag can be cleared by software
but is automatically cleared when the CPU vectors to the Timer 1 interrupt service
routine.
6TR1
Timer 1 Run Control.
Timer 1 is enabled by setting this bit to 1.
5 TF0 Timer 0 Overflow Flag.
Set to 1 by hardware when Timer 0 overflows. This flag can be cleared by software
but is automatically cleared when the CPU vectors to the Timer 0 interrupt service
routine.
4TR0
Timer 0 Run Control.
Timer 0 is enabled by setting this bit to 1.
3IE1
External Interru p t 1.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It
can be cleared by sof twa re but i s automa tically cleared when the CPU vectors to the
External Interrupt 1 service routine in edge- triggered mode.
2IT1
Interrupt 1 Type Select.
This bit selects whether the configured /INT1 interrupt will be edge or level sensitive.
/INT1 is configured active low or high by the IN1PL bit in the IT01CF register (see
SFR Definition 15.5).
0: /INT1 is level triggered.
1: /INT1 is edge triggered.
1IE0
External Interru p t 0.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It
can be cleared by sof twa re but i s automa tically cleared when the CPU vectors to the
External Interrupt 0 service routine in edge- triggered mode.
0IT0
Interrupt 0 Type Select.
This bit selects whether the configured INT0 interrupt will be edge or level sensitive.
INT0 is configured active low or high by the IN0PL bit in register IT01CF (see SFR
Definition 15.5).
0: INT0 is level triggered.
1: INT0 is edge triggered.
C8051F336/7/8/9
187 Rev.1.0
SFR Address = 0x89
SFR Definition 24.3. TMOD: Timer Mode
Bit76543210
Name GATE1 C/T1 T1M[1:0] GATE0 C/T0 T0M[1:0]
Type R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7GATE1
Timer 1 Gate Control.
0: Timer 1 enabled when TR1 = 1 irrespective of INT1 logic level.
1: Timer 1 enabled only when TR1 = 1 AND INT 1 is a ctive as de fined by bit IN1 PL in
register IT01CF (see SFR Definition 15.5).
6C/T1
Counter/Timer 1 Select.
0: Timer: Timer 1 incremented by clock defined by T1M bit in register CKCON.
1: Counter: Timer 1 incremented by high-to-low transitions on external pin (T1).
5:4 T1M[1:0] Timer 1 Mode Select.
These bits select the Timer 1 operation mode.
00: Mode 0, 13-bit Counter/Timer
01: Mode 1, 16-bit Counter/Timer
10: Mode 2, 8-bit Counter/Timer with Auto-Reload
11: Mode 3, Timer 1 Inactive
3GATE0
Timer 0 Gate Control.
0: Timer 0 enabled when TR0 = 1 irrespective of INT0 logic level.
1: Timer 0 enabled only when TR0 = 1 AND INT 0 is a ctive as de fined by bit IN0 PL in
register IT01CF (see SFR Definition 15.5).
2C/T0
Counter/Timer 0 Select.
0: Timer: Timer 0 incremented by clock defined by T0M bit in register CKCON.
1: Counter: Timer 0 incremented by high-to-low transitions on external pin (T0).
1:0 T0M[1:0] Timer 0 Mode Select.
These bits select the Timer 0 operation mode.
00: Mode 0, 13-bit Counter/Timer
01: Mode 1, 16-bit Counter/Timer
10: Mode 2, 8-bit Counter/Timer with Auto-Reload
11: Mod e 3, Tw o 8- bit Coun te r/ Timers
C8051F336/7/8/9
Rev.1.0 188
SFR Address = 0x8A
SFR Address = 0x8B
SFR Definition 24.4. TL0: Timer 0 Low Byte
Bit76543210
Name TL0[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TL0[7:0] Timer 0 Low Byte.
The TL0 register is the low byte of the 16-bit Timer 0.
SFR Definition 24.5. TL1: Timer 1 Low Byte
Bit76543210
Name TL1[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TL1[7:0] Timer 1 Low Byte.
The TL1 register is the low byte of the 16-bit Timer 1.
C8051F336/7/8/9
189 Rev.1.0
SFR Address = 0x8C
SFR Address = 0x8D
SFR Definition 24.6. TH0: Timer 0 High Byte
Bit76543210
Name TH0[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TH0[7:0] Timer 0 High Byte.
The TH0 register is the high byte of the 16-bit Timer 0.
SFR Definition 24.7. TH1: Timer 1 High Byte
Bit76543210
Name TH1[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TH1[7:0] Timer 1 High Byte.
The TH1 register is the high byte of the 16-bit Timer 1.
C8051F336/7/8/9
Rev.1.0 190
24.2. Timer 2
T imer 2 is a 16-bit timer formed by two 8-bit SFRs: TMR2L ( low byte) and T MR2H (high byte). Timer 2 may
operate in 16-bit auto-r eload mode or (split) 8-bit auto-reload mode. The T2SPLIT bit (TMR2CN.3) defines
the Timer 2 operation mode.
Timer 2 may be clocked by the system clock, the system clock divided by 12, or the external oscillator
source divided by 8. The external clock mode is ideal for real-time clock (RTC) functionality, where the
internal oscillator drives the sy stem clock while Timer 2 (and/or the PCA) is clocked by an external preci-
sion oscillator. Note that the external oscillator source divided by 8 is synchronized with the system clock.
24.2.1. 16-bit Timer with Auto-Reload
When T2SPLIT (TMR2CN.3) is zero, Timer 2 operates as a 16-bit timer with auto-reload. Timer 2 can be
clocked by SYSCLK, SYSCLK divided by 12, or the external oscillator clock source divided by 8. As the
16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 2
reload registers (TMR2RLH and TMR2RLL) is loaded into the Timer 2 register as shown in Figure 24.4,
and the Timer 2 High Byte Overflow Flag (TMR2CN.7) is set. If Timer 2 interrupts are enabled (if IE.5 is
set), an interrupt will be generated on each Timer 2 overflow. Additionally, if Timer 2 interrupts are enabled
and the TF2LEN bit is set (TMR2CN.5), an interrupt will be generated each time the lower 8 bits (TMR2L)
overflow fro m 0x FF to 0x00.
Figure 24.4. Timer 2 16-Bit Mode Block Diagram
Ex te rn a l Cloc k / 8
SYSCLK / 12
SYSCLK
TMR2L TMR2H
TMR2RLL TMR2RLH Reload
TCLK
0
1
TR2
TMR2CN
T2SPLIT
TF2CEN
TF2L
TF2H
T2XCLK
TR2
0
1
T2XCLK
Interrupt
TF2LEN
To ADC,
SMBus
To SMBus
TL2
Overflow
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
C8051F336/7/8/9
191 Rev.1.0
24.2.2. 8-bit Timers with Auto-Reload
When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers oper-
ate in auto-reload mode as shown in Figure 24.5. TMR2RLL holds the reload value for TMR2L; TMR2RLH
holds the reload value for TMR2H. The TR2 bit in TMR2CN handles the run control for TMR2H. TMR2L is
always running when configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, or the external oscillator clock
source divided by 8. The Timer 2 Clock Select bits (T2MH and T2ML in CKCON) select either SYSCLK or
the clock defined by the Timer 2 External Clock Select bit (T2XCLK in TMR2CN), as follows:
The TF2H bit is set when TMR2H overflows from 0xFF to 0x00; the TF2L bit is set when TMR2L overflows
from 0xFF to 0x00. When Timer 2 interrupts are enabled (IE.5), an interrupt is generated each time
TMR2H overflo ws. If Timer 2 interrupts are e nabled and TF2LEN (TMR2CN.5) is set, an inte rrupt is g ene r-
ated each time either TMR2L or TMR2H overflows. When TF2LEN is enabled, software must check the
TF2H and TF2L flags to determine the source of the Timer 2 interrupt. The TF2H and TF2L interrupt flags
are not cleared by hardware and must be manually cleared by software.
Figure 24.5. Timer 2 8-Bit Mode Block Diagram
T2MH T2XCLK TMR2H Clock Source T2ML T2XCLK TMR2L Clock Source
0 0 SYSCLK / 12 0 0 SYSCLK / 12
0 1 External Clock / 8 0 1 External Clock / 8
1 X SYSCLK 1 X SYSCLK
SYSCLK
TCLK
0
1TR2
External Clock / 8
SYSCLK / 12 0
1
T2XCLK
1
0
TMR2H
TMR2RLH Reload
Reload
TCLK TMR2L
TMR2RLL
Interrupt
TMR2CN
T2SPLIT
TF2CEN
TF2LEN
TF2L
TF2H
T2XCLK
TR2
To ADC,
SMBus
To SMBus
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
C8051F336/7/8/9
Rev.1.0 192
24.2.3. Low-Frequency Oscillator (LFO) Capture Mode
The Low-Frequency Oscillator Capture Mode allows the LFO clock to be measured against the system
clock or an external oscillator source. Timer 2 can be clocked from the system clock, the system clock
divided by 12, or the external oscillator divided by 8, depending on the T2ML (CKCON.4), and T2XCLK
settings.
Setting TF2CEN to 1 enables the LFO Capture Mode for Timer 2. In this mode, T2SPLIT should be set to
0, as the full 16-bit timer is used. Upon a falling edge of the low-frequency oscillator, the c ontents of Timer
2 (TMR2H:TMR2L) are loaded into the Timer 2 reload registers (TMR2RLH:TMR2RLL) and the TF2H flag
is set. By recording the difference between two successive timer capture values, the LFO clock frequency
can be determined with respect to the Timer 2 clock. The Timer 2 clock should be much faster than the
LFO to achieve an accurate reading.
Figure 24.6. Timer 2 Low-Frequency Oscillation Capture Mode Block Diagram
External Clock / 8
SYSCLK / 12
SYSCLK
0
1
0
1
T2XCLK
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
TMR2L TMR2H
TCLK
TR2
TMR2RLL TMR2RLH
Capture
Low-Frequency
Oscillator
TMR2CN
T2SPLIT
TF2CEN
TF2L
TF2H
T2XCLK
TR2
TF2LEN
TF2CEN Interrupt
C8051F336/7/8/9
193 Rev.1.0
SFR Address = 0xC8; Bit-Addressable
SFR Definition 24.8. TMR2CN: Timer 2 Control
Bit76543210
Name TF2H TF2L TF2LEN TF2CEN T2SPLIT TR2 T2XCLK
Type R/W R/W R/W R/W R/W R/W R R/W
Reset 00000000
Bit Name Function
7 TF2H Timer 2 High Byte Overflow Flag.
Set by hardware whe n the Timer 2 high byte overflow s fro m 0x FF to 0x00. In 16 bit
mode, this will occur when Timer 2 overflows from 0xFFFF to 0x0000. When the
Ti me r 2 interru pt is enab led, setting this bit causes th e CPU to vecto r to the Timer 2
interrupt service routine. This bit is not au to m at ically cleared by hardware .
6 TF2L Timer 2 Low Byte Overflow Flag.
Set by hardware when the Timer 2 low byte overflows from 0xFF to 0x00. TF2L will
be set when the low byte overflows regardless of the Timer 2 mode. This bit is not
automatically cleared by hardware.
5 TF2LEN Timer 2 Low Byte Interrupt Enable.
When set to 1, this bit enables Timer 2 Low Byte interrupts. If Timer 2 interrupts are
also enabled, an interrupt will be generated when the low byte of Timer 2 overflows.
4TF2CEN
Timer 2 Low-Frequency Oscillator Capture Enable.
When set to 1, this bit enables Timer 2 Low-Frequency Oscillator Capture Mode. If
TF2CEN is set and Timer 2 interrupts are enabled, an interrupt will be generated on
a falling edge of the low-frequency oscillator output, and the current 16-bit timer
value in TMR2H:TMR2L will be copied to TMR2RLH:TMR2RLL.
3 T2SPLIT Timer 2 Split Mode Enable.
When this bit is set, Timer 2 operates as two 8-bit timers with auto-reload.
0: Timer 2 operates in 16-bit auto-reload mode.
1: Timer 2 operates as two 8-bit auto-reload timers.
2TR2
Timer 2 Run Control.
Timer 2 is enabled by setting this bit to 1. In 8-bit mode, this bit enables/disables
TMR2H only; TMR2L is always enabled in split mod e .
1 Unused Unused. Read = 0b; Write = Don’t Care
0T2XCLK
Timer 2 External Clock Select.
This bit selects the external clock source for Timer 2. If Timer 2 is in 8-bit mode, this
bit selects the external oscillator clock source for both timer bytes. However, the
Timer 2 Clock Select bits (T2MH and T2ML in register CKCON) may still be used to
select between the external clock and the system clock for eithe r timer.
0: Timer 2 clock is the system clock divided by 12.
1: Timer 2 clock is the external clock divided by 8 (synchronized with SYSCLK).
C8051F336/7/8/9
Rev.1.0 194
SFR Address = 0xCA
SFR Address = 0xCB
SFR Address = 0xCC
SFR Definition 24.9. TMR2RLL: Timer 2 Reload Register Low Byte
Bit76543210
Name TMR2RLL[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR2RLL[7:0] Timer 2 Reload Register Low Byte.
TMR2RLL holds the low byte of the reload value for Timer 2.
SFR Definition 24.10. TMR2RLH: Timer 2 Reload Register High Byte
Bit76543210
Name TMR2RLH[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR2RLH[7:0] Timer 2 Reload Register High Byte.
TMR2RLH holds the high byte of the reload value for Timer 2.
SFR Definition 24.11. TMR2L: Timer 2 Low Byte
Bit76543210
Name TMR2L[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR2L[7:0] Timer 2 Low Byte.
In 16-bit mode, the TMR2L register contains the low byte of the 16-bit Timer 2. In 8-
bit mode, TMR2L contains the 8-bit low byte timer value.
C8051F336/7/8/9
195 Rev.1.0
SFR Address = 0xCD
SFR Definition 24.12. TMR2H Timer 2 High Byte
Bit76543210
Name TMR2H[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR2H[7:0] Timer 2 Low Byte.
In 16-bit mode, the TM R 2H re gis te r con tains the hig h by te of the 16- bit Timer 2. In 8-
bit mode, TMR2H contains the 8-bit high byte timer value.
C8051F336/7/8/9
Rev.1.0 196
24.3. Timer 3
T imer 3 is a 16-bit timer for med by two 8-bit SFRs: TMR3L (low byte) and TMR3H (high byte ). T i mer 3 may
operate in 16-bit auto-r eload mode or (split) 8-bit auto-reload mode. The T3SPLIT bit (TMR3CN.3) defines
the Timer 3 operation mode.
Timer 3 may be clocked by the system clock, the system clock divided by 12, the external oscillator source
divided by 8, or the internal low-frequency oscillator divided by 8. The external clock mode is ideal for real-
time clock (RTC) functionality, where the internal high-frequency oscillator drives the system clock while
T imer 3 is clocked by an external oscillator source. Note that the external oscillator source divided by 8 and
the LFO source divided by 8 are synchronized with the system clock when in all operating modes except
suspend. When the internal oscillator is placed in suspend mode, The external clock/8 signal or the LFO/8
output can directly drive the timer. This allows the use of an external clock or the LFO to wake up the
device from suspend mode. The timer will continue to run in suspend mode and count up. When the timer
overflow occurs, the device will wake from suspend mode, and begin executing code again. The timer
value may be set prior to entering suspe nd, to overflow in the desire d amount o f time (number o f clocks) to
wake the device. If a wake-up source other than the timer wakes the device from suspend mode, it may
take up to three timer clocks before the timer registers can be read or written. During this time, the
STSYNC bit in register OSCICN will be set to 1, to indicate that it is not safe to read or write the timer reg-
isters.
Important Note: In internal LFO/8 mode, the divider for the internal LFO must be set to 1 for proper
functionality. The timer will not operate if the LFO divider is not set to 1.
24.3.1. 16-bit Timer with Auto-Reload
When T3SPLIT (TMR3CN.3) is zero, Timer 3 operates as a 16-bit timer with auto-reload. Timer 3 can be
clocked by SYSCLK, SYSCLK divided by 12, or the external oscillator clock source divided by 8. As the
16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 3
reload registers (TMR3RLH and TMR3RLL) is loaded into the Timer 3 register as shown in Figure 24.7,
and the Timer 3 High Byte Overflow Flag (TMR3CN.7) is set. If Timer 3 interrupts are enabled (if EIE1.7 is
set), an interrupt will be generated on each Timer 3 overflow. Additionally, if Timer 3 interrupts are enabled
and the TF3LEN bit is set (TMR3CN.5), an interrupt will be generated each time the lower 8 bits (TMR3L)
overflow fro m 0x FF to 0x00.
Figure 24.7. Timer 3 16-Bit Mode Block Diagram
SYSCLK
TMR3L TMR3H
TMR3RLL TMR3RLH Reload
TCLK
0
1
TR3
TMR3CN
T3SPLIT
T3XCLK1
TF3CEN
TF3L
TF3H
T3XCLK0
TR3
Interrupt
TF3LEN
To ADC
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
Externa l Cloc k / 8
SYSCLK / 12 00
T3XCLK[1:0]
01
11
Inte rn a l LF O / 8
C8051F336/7/8/9
197 Rev.1.0
24.3.2. 8-bit Timers with Auto-Reload
When T3SPLIT is s et, Tim er 3 operates as two 8-bit timers (TMR3H and TMR3L). Both 8-bit timers oper-
ate in auto-reload mode as shown in Figure 24.8. TMR3RLL holds the reload value for TMR3L; TMR3RLH
holds the reload value for TMR3H. The TR3 bit in TMR3CN handles the run control for TMR3H. TMR3L is
always running when configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, the external oscillator clock
source divided by 8, or the internal Low-frequency Oscillator. The Timer 3 Clock Select bits (T3MH and
T3ML in CKCON) select either SYSCLK or the clock defined by the Timer 3 External Clock Select bits
(T3XCLK[1:0] in TMR3CN), as follows:
The TF3H bit is set when TMR3H overflows from 0xFF to 0x00; the TF3L bit is set when TMR3L overflows
from 0xFF to 0x00. When Timer 3 interrupt s are ena bled, an interru pt is generated each time TMR3H over-
flows. If Timer 3 interrupts are enabled and TF3LEN (TMR3CN.5) is set, an interrupt is generated each
time either TMR3L or TMR3H overflows. When TF3LEN is enabled, software must check the TF3H and
TF3L flags to determine the source of the Timer 3 interrupt. The TF3H and TF3L interrupt flags are not
cleared by hardware and must be manually cleared by software.
Figure 24.8. Timer 3 8-Bit Mode Block Diagram
T3MH T3XCLK[1:0] TMR3H Clock
Source T3ML T3XCLK[1:0] TMR3L Clock
Source
0 00 SYSCLK / 12 0 00 SYSCLK / 12
0 01 External Clock / 8 0 01 External Clock / 8
0 10 Reserved 0 10 Reserved
0 11 Internal LFO 0 11 Internal LFO
1 X SYSCLK 1 X SYSCLK
SYSCLK
TCLK
0
1TR3
1
0
TMR3H
TMR3RLH Reload
Reload
TCLK TMR3L
TMR3RLL
Interrupt
TMR3CN
T3SPLIT
T3XCLK1
TF3CEN
TF3LEN
TF3L
TF3H
T3XCLK0
TR3
To ADC
External Clock / 8
SYSCLK / 12 00
T3XCLK[1:0]
01
11
Internal LFO / 8
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
C8051F336/7/8/9
Rev.1.0 198
24.3.3. Low-Frequency Oscillator (LFO) Capture Mode
The Low-Frequency Oscillator Capture Mode allows the LFO clock to be measured against the system
clock or an external oscillator source. Timer 3 can be clocked from the system clock, the system clock
divided by 12, or the external oscillator divided by 8, depending on the T3ML (CKCON.6), and
T3XCLK[1:0] settings.
Setting TF3CEN to 1 enables the LFO Capture Mode for Timer 3. In this mode, T3SPLIT should be set to
0, as the full 16-bit timer is used. Upon a falling edge of the low-frequency oscillator, the contents of
Timer 3 (TMR3H:TMR3L) are loaded into the Timer 3 reload registers (TMR3RLH:TMR3RLL) and the
TF3H flag is set. By recording the difference between two successive timer capture values, the LFO clock
frequency can be determined with respect to the Timer 3 clock. The Timer 3 clock should be much faster
than the LFO to achieve an accurate reading. This means that the LFO/8 should not be selected as the
timer clock source in this mode.
Figure 24.9. Timer 3 Low-Frequency Oscillation Capture Mode Block Diagram
External Clock / 8
SYSCLK / 12
SYSCLK
0
1
00
01
T3XCLK[1:0]
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
TMR3L TMR3H
TCLK
TR3
TMR3RLL TMR3RLH
Capture
Low-Frequency
Oscillator
TMR3CN
T3SPLIT
T3XCLK1
TF3CEN
TF3L
TF3H
T3XCLK0
TR3
TF3LEN
TF3CEN Interrupt
C8051F336/7/8/9
199 Rev.1.0
SFR Address = 0x91
SFR Definition 24.13. TMR3CN: Timer 3 Control
Bit76543210
Name TF3H TF3L TF3LEN TF3CEN T3SPLIT TR3 T3XCLK[1:0]
Type R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7 TF3H Timer 3 High Byte Overflow Flag.
Set by hardware whe n the Timer 3 high byte overflow s fro m 0x FF to 0x00. In 16 bit
mode, this will occur when Timer 3 overflows from 0xFFFF to 0x0000. When the
Timer 3 interrupt is enabled, setting this bit causes the CPU to vector to the T i mer 3
interrupt service routine. This bit is not automatically cleared by hardware.
6 TF3L Timer 3 Low Byte Overflow Flag.
Set by hardware when the Timer 3 low byte overflows from 0xFF to 0x00. TF3L will
be set when the low byte overflows regardless of the Timer 3 mode. This bit is not
automatically cleared by hardware.
5 TF3LEN Timer 3 Low Byte Interrupt Enable.
When set to 1, this bit enables Timer 3 Low Byte interrupts. If Timer 3 interrupts are
also enabled, an interrupt will be generated when the low byte of Timer 3 overflows.
4TF3CEN
Timer 3 Low-Frequency Oscillator Capture Enable.
When set to 1, this bit enables Timer 3 Low-Frequency Oscillator Capture Mode. If
TF3CEN is set and Timer 3 interrupts are enabled, an interr upt will be genera ted on
a falling edge of the low-frequency oscillator output, and the current 16-bit timer
value in TMR3H:TMR3L will be copied to TMR3RLH:TMR3RLL.
3 T3SPLIT Timer 3 Split Mode Enable.
When this bit is set, Timer 3 operates as two 8-bit timers with auto-reload.
0: Timer 3 operates in 16-bit auto-reload mode.
1: Timer 3 operates as two 8-bit auto-reload timers.
2TR3
Timer 3 Run Control.
Timer 3 is enabled by setting this bit to 1. In 8-bit mode, this bit enables/disables
TMR3H only; TMR3L is always enabled in split mod e .
1:0 T3XCLK[1:0] Ti mer 3 External Clock Select.
This bit selects the “external” clock source for Timer 3. If T imer 3 is in 8-bit mode,
this bit selects the external oscillator clock source for both timer bytes. However , the
Timer 3 Clock Select bits (T3MH and T3ML in register CKCON) may still be used to
select between the external clock and the system clock for eithe r timer.
00: System clock divided by 12.
01: External clock divided by 8 (synchronized with SYSCLK when not in suspend).
10: Reserved.
11: Internal LFO/8 (synchronized with SYSCLK when not in suspend).
C8051F336/7/8/9
Rev.1.0 200
SFR Address = 0x92
SFR Address = 0x93
SFR Address = 0x94
SFR Definition 24.14. TMR3RLL: Timer 3 Reload Register Low Byte
Bit76543210
Name TMR3RLL[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR3RLL[7:0] Timer 3 Reload Register Low Byte.
TMR3RLL holds the low byte of the reload value for Timer 3.
SFR Definition 24.15. TMR3RLH: Timer 3 Reload Register High Byte
Bit76543210
Name TMR3RLH[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR3RLH[7:0] Timer 3 Reload Register High Byte.
TMR3RLH holds the high byte of the reload value for Timer 3.
SFR Definition 24.16. TMR3L: Timer 3 Low Byte
Bit76543210
Name TMR3L[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR3L[7:0] Timer 3 Low Byte.
In 16-bit mode, the TMR3L register contains the low byte of the 16-bit Timer 3. In
8-bit mode, TMR3L contains the 8-bit low byte timer value.
C8051F336/7/8/9
201 Rev.1.0
SFR Address = 0x95
SFR Definition 24.17. TMR3H Timer 3 High Byte
Bit76543210
Name TMR3H[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR3H[7:0] Timer 3 High Byte.
In 16-bit mode, the TMR3H register cont a ins the high byte o f th e 16-bit Timer 3. In
8-bit mode, TMR3H contains the 8-bit high byte timer value.
C8051F336/7/8/9
Rev.1.0 202
25. Programmable Counter Array
The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU
intervention than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer
and three 16-bit capture/compare modules. Each capture/compare module has its own associated I/O line
(CEXn) which is routed through the Crossbar to Port I/O when enabled. The counter/timer is driven by a
programmable timebase that can select between six sources: system clock, system clock divided by four,
system clock divided by twelve, the external oscillator clock source divided by 8, Timer 0 overflows, or an
external clock signal on the ECI input pin. Each capture/compare module may be configured to operate
independently in one of six modes: Edge-Triggered Capture, Software Timer, High-Speed Output, Fre-
quency Output, 8 to 11-Bit PWM, or 16-Bit PWM (each mode is described in Section
“25.3. Capture/Compare Modules” on page 205). The external oscillator clock option is ideal for real-time
clock (RTC) functionality, allowing the PCA to be cloc ked by a precision external oscillator while the inter-
nal oscillator drives the system clock. The PCA is configured and controlled through the system controller's
Special Function Registers. The PCA block diagram is shown in Figure 25.1
Import ant Note: The PCA Module 2 may be used as a watchdog timer (WDT), and is enabled in this mode
following a system reset. Access to certain PCA registers is restricted while WDT mode is enabled.
See Section 25 .4 fo r details.
Figure 25.1. PCA Block Diagram
Capture/Compare
Module 1
Capture/Compare
Module 0 Capture/Compare
Module 2 / WDT
CEX1
ECI
Crossbar
CEX2
CEX0
Port I/O
16-Bit Counter/Timer
PCA
CLOCK
MUX
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
SYSCLK
External Clock/8
C8051F336/7/8/9
203 Rev.1.0
25.1. PCA Counter/Timer
The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte
(MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches
the value of PCA0H into a “snapshot” register; the following PCA0H read accesses this “snapshot” register .
Reading the PCA0L Regist er first guaran tees an a ccurate r eading of the entire 16 -bit PCA0 cou nter.
Reading PCA0H or PCA0L does not disturb the counter operation. The CPS2–CPS0 bits in the PCA0MD
register select the timebase for the counter/timer as shown in Table 25.1.
When the counter/timer overflows from 0xFFFF to 0x0000, the Counter Overflow Flag (CF) in PCA0MD is
set to logic 1 and an interrupt request is generated if CF interrupts are enabled. Setting the ECF bit in
PCA0MD to logic 1 enables the CF flag to generate an interrupt request. The CF bit is not automatically
cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by soft-
ware. Clearing the CIDL bit in the PCA0MD register allows the PCA to continue normal operation while the
CPU is in Idle mode.
Figure 25.2. PCA Counter/Timer Block Diagram
Table 25.1. PCA Timebase Input Options
CPS2 CPS1 CPS0 Timebase
0 0 0 System clock divide d by 12
0 0 1 System clock divide d by 4
0 1 0 Timer 0 overflow
011
High-to-low transitions on ECI (max rate = system clock divided
by 4)
1 0 0 System clock
1 0 1 External oscillator source divided by 8*
1 1 x Reserved
Note: External oscillator source divided by 8 is synchronized with the system clock.
PCA0CN
C
FC
RC
C
F
0
C
C
F
2
C
C
F
1
PCA0MD
C
I
D
L
W
D
T
E
E
C
F
C
P
S
1
C
P
S
0
W
D
L
C
K
C
P
S
2
IDLE
0
1PCA0H PCA0L
Snapshot
Register
To SFR Bus
Overflow To PCA Interrupt System
CF
PCA0L
read
To PCA Modules
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
000
001
010
011
100
101
SYSCLK
External Clock/8
C8051F336/7/8/9
Rev.1.0 204
25.2. PCA0 Interrupt Sources
Figure 25.3 shows a diagram of the PCA interrupt tree. There are five independent event flags that can be
used to generate a PCA0 interrupt. They are: the main PCA counter overflow flag (CF), which is set upon
a 16-bit overflow of the PCA0 counter, an intermediate overflow flag (COVF ), which can b e set on an o ver-
flow from the 8th, 9th, 10th, or 11 th bit of the PCA0 counter, and the indiv idu al f lag s f or e ach PC A ch an n el
(CCF0, CCF1, and CCF2), which are set according to the operation mode of that module. These event
flags are always set when the trigger condition occurs. Each of these flags can be individually selected to
generate a PCA0 interrupt, using the corresponding interrupt enable flag (ECF for CF, ECOV for COVF,
and ECCFn for each CCFn). PCA0 interrupts must be globally enabled before any individual interrupt
sources are recognized by the processor. PCA0 interrupts are globally enabled by setting the EA bit and
the EPCA0 bit to logic 1.
Figure 25.3. PCA Interrupt Block Diagram
PCA0CN
C
FC
RC
C
F
0
C
C
F
2
C
C
F
1
PCA0MD
C
I
D
L
W
D
T
E
E
C
F
C
P
S
1
C
P
S
0
W
D
L
C
K
C
P
S
2
0
1
PCA Module 0
(CCF0)
PCA Module 1
(CCF1)
ECCF1
0
1
ECCF0
0
1
PCA Module 2
(CCF2)
ECCF2
PCA Counter/Timer 16-
bit Overflow 0
1
Interrupt
Priority
Decoder
EPCA0
0
1
EA
0
1
PCA0CPMn
(for n = 0 to 2)
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
PCA Counter/Timer 8, 9,
10 or 11-bit Overflow
0
1
Set 8, 9, 10, or 11 bit Operation
PCA0PWM
A
R
S
E
L
E
C
O
V
C
L
S
E
L
0
C
L
S
E
L
1
C
O
V
F
C8051F336/7/8/9
205 Rev.1.0
25.3. Capture/Compare Modules
Each module can be configured to operate independently in one of six operation modes: edge-triggered
capture, software timer, high-speed output, frequency output, 8 to 11-bit pulse width modulator, or 16-bit
pulse width modulator. Each module has Special Function Registers (SFRs) associated with it in the CIP-
51 system controller. These registers are used to exchange dat a with a module an d configure the mo dule's
mode of operation. Table 25.2 summarizes the bit settings in the PCA0CPMn and PCA0PWM registers
used to sele ct the PCA captur e/compare module’s operating mode. Note that all modules set to use 8, 9,
10, or 11-bit PWM mode must use the same cycle length (8–11 bits). Setting the ECCFn bit in a
PCA0CPMn register enables the module's CCFn interrupt.
Table 25.2. PCA0CPM and PCA0PWM Bit Settings for PCA Capture/Compare
Modules
Operational Mode PCA0CPMn PCA0PWM
Bit Number765432107654–21–0
Capture triggered by positive edge on CEXn XX10000A0XBXXXXX
Capture triggered by negative edge on CEXn XX01000A0XBXXXXX
Capture triggered by any transition on CEXn XX11000A0XBXXXXX
Software Timer XC00100A0XBXXXXX
High Speed Output XC00110A0XBXXXXX
Frequency Output XC00011A0XBXXXXX
8-Bit Pulse Width Mod ulator (Note 7) 0 C 0 0 E 0 1 A 0 X B XXX 00
9-Bit Pulse Width Mod ulator (Note 7) 0 C 0 0 E 0 1 A D X B XXX 01
10-Bit Pulse Width Modulator (Note 7) 0 C 0 0 E 0 1 A D X B XXX 10
11-Bit Pulse Width Modulator (Note 7) 0 C 0 0 E 0 1 A D X B XXX 11
16-Bit Pulse Width Modulator 1 C 0 0 E 0 1 A 0 X B XXX XX
Notes:
1. X = Don’t Care (no functional difference for individual module if 1 or 0).
2. A = Enable interrupts for this module (PCA interru pt triggered on CCFn set to 1).
3. B = Enable 8th, 9th, 10th or 11th bit ov erflow interrupt (Depends on setting of CLSEL[1:0]).
4. C = When set to 0, the digital comparator is off. For high speed and frequency output modes, the
associated pin will not toggle. In any of the PWM modes, this generates a 0% duty cycle (output = 0).
5. D = Selects whether the Capture/Compare register (0) or the Auto-Reload register (1) for the associated
channel is accessed via addresses PCA0CPHn and PCA0CPLn.
6. E = When set, a match event will cause the CCFn flag for the associated channel to be set.
7. All modules set to 8, 9, 10 or 11-bit PWM mode use the same cycle length setting.
C8051F336/7/8/9
Rev.1.0 206
25.3.1. Edge-triggered Capture Mode
In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA
counter/timer and load it in to the corr esponding mo dule 's 16- bit ca pture/co mpare register (PCA0CPLn and
PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn re giste r ar e u sed to sele ct th e type o f tr an si-
tion that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge),
or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag (CCFn)
in PCA0CN is set to logic 1. An interrupt request is generated if the CCFn interrupt for that module is
enabled. The CCFn bit is not automatica lly cleared by har dware wh en the CPU ve ctors to the interr upt ser-
vice routine, and must be cleared by software. If both CAPPn and CAPNn bits are set to logic 1, then the
state of the Port pin associated with CEXn can be read directly to determine whether a rising-edge or fall-
ing-edge caused the capture.
Figure 25.4. PCA Capture Mode Diagram
Note: The CEXn input signal must remain high or low for at least 2 system clock cycles to be recognized by the
hardware.
PCA0L
PCA0CPLn
PCA
Timebase
CEXn
CrossbarPort I/O
PCA0H
Capture
PCA0CPHn
0
1
0
1
(to CCFn)
PCA0CPMn
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
PCA0CN
C
FC
RC
C
F
0
C
C
F
2
C
C
F
1
PCA Interrupt
x 000xx
C8051F336/7/8/9
207 Rev.1.0
25.3.2. Software Timer (Compare) Mode
In Softwa re Timer mode, the PCA counter/timer value is compared to the module's 16-bit ca pture/ co mpare
register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in
PCA0CN is set to logic 1. An interrupt request is generated if the CCFn interrupt for that module is
enabled. The CCFn bit is not automatica lly cleared by har dware wh en the CPU ve ctors to the interr upt ser-
vice routine, and must be cleared b y sof t ware. Settin g the ECOMn and MATn bits in the PCA0CPMn reg is-
ter enables Software Timer mode.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Figure 25.5. PCA Software Timer Mode Diagram
Match
16-bit Comparator
PCA0H
PCA0CPHn
Enable
PCA0L
PCA
Timebase
PCA0CPLn
00 00
0
1
x
ENB
ENB
0
1
Write to
PCA0CPLn
Write to
PCA0CPHn
Reset
PCA0CPMn
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
x
PCA0CN
C
FC
RC
C
F
0
C
C
F
2
C
C
F
1
PCA Interrupt
C8051F336/7/8/9
Rev.1.0 208
25.3.3. High-Speed Output Mode
In High-Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs
between the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and
PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1. An
interrupt request is generated if the CCFn interrupt for that module is enabled. The CCFn bit is not auto-
matically clear ed by hard ware wh en the C PU vectors to the inte rrupt serv ice rout ine, and m ust be cle ared
by software. Setting the TOGn, MATn, and ECOMn bits in the PCA0CPMn register enables the High-
Speed Output mode. If ECOMn is cleared, the associated pin will retain its state, and not toggle on the next
match even t.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Figure 25.6. PCA High-Speed Output Mode Diagram
Match
16-bit Comparator
PCA0H
PCA0CPHn
Enable
PCA0L
PCA
Timebase
PCA0CPLn
0
1
00 0x
ENB
ENB
0
1
Write to
PCA0CPLn
Write to
PCA0CPHn
Reset
PCA0CPMn
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
x
CEXn Crossbar Port I/O
Toggle 0
1
TOGn
PCA0CN
C
FC
RC
C
F
0
C
C
F
2
C
C
F
1
PCA Interrupt
C8051F336/7/8/9
209 Rev.1.0
25.3.4. Frequency Output Mode
Frequency Output Mode produces a programmable-frequency square wave on the module’s associated
CEXn pin. The capture/compare module high byte holds the number of PCA clocks to count before the out-
put is toggled. The frequency of the square wave is then defined by Equation 25.1.
Equation 25.1. Square Wave Frequency Output
Where FPCA is the frequency of the clock selected by the CPS2–0 bits in the PCA mode register,
PCA0MD. The lower byte of the capture/compare module is compared to the PCA counter low byte; on a
match, CEXn is toggled and the offset held in the high byte is added to the mat ched value in PCA0CP Ln.
Frequency Output Mode is enabled by setting the ECOMn, TOGn, and PWMn bits in the PCA0CPMn reg-
ister. Note that the MATn bit should normally be set to 0 in this mode. If the MATn bit is set to 1, the CC Fn
flag for the channel will be set when the 16-bit PCA0 counter and the 16-bit capture/compare register for
the channel are equal.
Figure 25.7. PCA Frequency Output Mode
25.3.5. 8-bit, 9-bit, 10-bit and 11-bit Pulse Width Modulator Modes
Each module can be u sed inde pende ntly to gen erate a pulse width modulated (PWM) output on its associ-
ated CEXn pin. The frequency of the output is dependent on the timebase for the PCA counter/timer, and
the setting of the PWM cycle length (8, 9, 10 or 11-bits). For backwards-compatibility with the 8-bit PWM
mode available on other devices, the 8-bit PWM mode operates slightly different than 9, 10 and 11-bit
PWM modes. It is important to note that all channels configured for 8/9/10/11-bit PWM mode will use
the same cycle leng th. It is not possible to configure on e channel for 8- bit PWM mode and anothe r for 11-
bit mode (for exam p le) . Ho wever, other PCA channe ls ca n b e co nfig u red to P in Ca ptu r e, High -Speed Out-
put, Software Timer, Frequency Output, or 16-bit PWM mode independently.
FCEXn FPCA
2PCA0CPHn×
-----------------------------------------
=
Note: A value of 0x00 in the PCA0CPHn register is equal to 256 for this equation.
8-bit
Comparator
PCA0L
Enable
PCA Timebase
match
PCA0CPHn8-bit AdderPCA0CPLn
Adder
Enable
CEXn Crossbar Port I/O
Toggle 0
1
TOGn
000 x
PCA0CPMn
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
x
ENB
ENB
0
1
Write to
PCA0CPLn
Write to
PCA0CPHn
Reset
C8051F336/7/8/9
Rev.1.0 210
25.3.5.1. 8-bit Pulse Width Modulator Mode
The duty cycle of the PWM output signal in 8-bit PWM mode is varied using the module's PCA0CPLn cap-
ture/compare register. When the value in the low byte of the PCA counter/timer (PCA0L) is equal to the
value in PCA0CPLn, the output on th e CEXn pin will be set. When the count value in PCA0L overflows, the
CEXn output will be reset (see Figure 25.8). Also, when the counter/timer low byte (PCA0L) overflows from
0xFF to 0x00, PCA0CPLn is reloaded automatically with the value stored in the module’s capture/compare
high byte (PCA0CPHn) without software intervention. Setting the ECOMn and PWMn bits in the
PCA0CPMn register, and setting the CLSEL bits in register PCA0PWM to 00b enables 8-Bit Pulse Width
Modulator mode. If the MATn bit is set to 1, the CCFn flag for the module will be set each time an 8-bit
comparator match (r ising edge) occurs. The COVF flag in PCA0PWM can be used to dete ct the overflow
(falling edge), which will occur every 256 PCA clock cycles. The duty cycle for 8-Bit PWM Mode is given in
Equation 25.2.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Equation 25.2. 8-Bit PWM Duty Cycle
Using Equation 25.2, the largest duty cycle is 100% (PCA0CPHn = 0), and the smallest duty cycle is
0.39% (PCA0CPHn = 0xFF). A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
Figure 25.8. PCA 8-Bit PWM Mode Diagram
Duty Cycle 256 PCA0CPHn–()
256
---------------------------------------------------
=
8-bit
Comparator
PCA0L
PCA0CPLn
PCA0CPHn
CEXn Crossbar Port I/O
Enable
Overflow
PCA Timebase
00x0 x
Q
Q
SET
CLR
S
R
match
PCA0CPMn
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
0
PCA0PWM
A
R
S
E
L
E
C
O
V
C
L
S
E
L
0
C
L
S
E
L
1
C
O
V
F
x000
ENB
ENB
0
1
Write to
PCA0CPLn
Write to
PCA0CPHn
Reset
COVF
C8051F336/7/8/9
211 Rev.1.0
25.3.5.2. 9/10/11-bit Pulse Widt h Modulator Mode
The duty cycle of the PWM output signal in 9/10/11-bit PWM mode should be varied by writing to an “Auto-
Reload” Register, which is dual-mapped into the PCA0CPHn and PCA0CPLn register locations. The data
written to define the duty cycle should be right-justified in the registers. The auto-reload registers are
accessed (read or written) when the bit ARSEL in PCA0PWM is set to 1. The capture/compare registers
are accessed when ARSEL is set to 0.
When the least-significant N bits of the PCA0 counter match the value in the associated module’s cap-
ture/compare register (PCA0CPn), the output on CEXn is asserted high. When th e counter over flo ws fr om
the Nth bit, CEXn is asserted low (see Figure 25.9). Upon an overflo w from the Nth bit, the COVF flag is
set, and the value stored in the module’s auto-reload register is loaded into the capture/compare register.
The value of N is determined by th e CLS E L bits in register P CA0 PWM .
The 9, 10 or 11-bit PWM mode is selected by setting the ECOMn and PWMn bits in the PCA0CPMn regis-
ter, and setting the CLSEL bits in register PCA0PWM to the desired cycle length (other than 8-bits). If the
MATn bit is set to 1, the CCFn flag for the module will be set each time a comparator match (rising edge)
occurs. The COVF flag in PCA0PWM can be used to detect the overflow (falling edge), which will occur
every 512 (9-bit), 1024 (10-bit) or 2048 (11-bit) PCA clock cycles. The duty cycle for 9/10/11-Bit PWM
Mode is given in Equation 25.2, where N is the number of bits in the PWM cycle.
Important Note About PCA0CPHn and PCA0CPLn Registers: When writing a 16-bit value to the
PCA0CPn registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn
bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Equation 25.3. 9, 10, and 11-Bit PWM Duty Cycle
A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
Figure 25.9. PCA 9, 10 and 11-Bit PWM Mode Diagram
Duty Cycle 2NPCA0CPn–()
2N
--------------------------------------------
=
N-bit Comparator
PCA0H:L
(Capture/Compare)
PCA0CPH:Ln
(right-justified)
(Auto-Reload)
PCA0CPH:Ln
(right-justified)
CEXn Crossbar Port I/O
Enable
Overflow of Nth Bit
PCA Timebase
00x0 x
Q
Q
SET
CLR
S
R
match
PCA0CPMn
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
0
PCA0PWM
A
R
S
E
L
E
C
O
V
C
L
S
E
L
0
C
L
S
E
L
1
C
O
V
F
x
ENB
ENB
0
1
Write to
PCA0CPLn
Write to
PCA0CPHn
Reset R/W when
ARSEL = 1
R/W when
ARSEL = 0 Set “N” bits:
01 = 9 bits
10 = 10 bits
11 = 11 bits
C8051F336/7/8/9
Rev.1.0 212
25.3.6. 16-Bit Pulse Width Modulator Mode
A PCA module may also be operated in 16-Bit PWM mode. 16-bit PWM mode is independent of the other
(8/9/10/11-bit) PWM modes. In this mode, the 16-bit capture/compare module defines the number of PCA
clocks for the low time of the PWM signal. When the PCA counter matches the module contents, the out-
put on CEXn is asserted high; when the 16-bit counter overflows, CEXn is asserted low. To output a vary-
ing duty cycle, new value writes should be synchronized with PCA CCFn match interrupts. 16-Bit PWM
Mode is enabled by setting the ECOMn, PWMn, and PWM16n bits in the PCA0CPMn register. For a vary-
ing duty cycle, match interrupts should be enabled (ECCFn = 1 AND MATn = 1) to help synchronize the
capture/compare register writes. If the MATn bit is set to 1, the CCFn flag for the module will be set each
time a 16-bit comparator match (rising edge) occurs. The CF flag in PCA0CN can be used to detect the
overflow (falling edge). The duty cycle for 16-Bit PWM Mode is given by Equation 25.4.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Equation 25.4. 16-Bit PWM Duty Cycle
Using Equation 25.4, the largest duty cycle is 100% (PCA0CPn = 0), and the smallest duty cycle is
0.0015% (PCA0CPn = 0xFFFF). A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
Figure 25.10. PCA 16-Bit PWM Mode
Duty Cycle 65536 PCA0CPn–()
65536
-----------------------------------------------------
=
PCA0CPLnPCA0CPHn
Enable
PCA Timebase
00x0 x
PCA0CPMn
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
1
16-bit Comparator CEXn Crossbar Po r t I/O
Overflow
Q
Q
SET
CLR
S
R
match
PCA0H PCA0L
ENB
ENB
0
1
Write to
PCA0CPLn
Write to
PCA0CPHn
Reset
C8051F336/7/8/9
213 Rev.1.0
25.4. Watchdog Timer Mode
A programmable wa tchdog timer (WDT) function is avail able throu gh the PCA Module 2. The WDT is used
to generate a reset if the time between writes to the WDT up date register (PCA0CPH2 ) exceed a specified
limit. The WDT can be configured and en abled/disabled as needed by software.
With the WDTE bit set in the PCA0MD register, Module 2 operates as a watchdog timer (WDT). The Mod-
ule 2 high byte is compared to the PCA counter high byte; the Module 2 low byte holds the offset to be
used when WDT updates are performed. The Watchdog Timer is enabled on reset. Writes to some
PCA registers are restricted while the Watchdog Timer is enabled. The WDT will generate a reset
shortly after code begins execution. To avoid this reset, the WDT should be explicitly disabled (and option-
ally re-configured and re-enabled if it is used in the system).
25.4.1. Watchdog Timer Operation
While the WDT is enabled:
PCA counter is forced on.
Writes to PCA0L and PCA0H are not allowed.
PCA clock source bits (CPS2–CPS0) are frozen.
PCA Idle control bit (CIDL) is frozen.
Module 2 is forced into software timer mode.
Writes to the Module 2 mode register (PCA0CPM2) are disabled.
While the WDT is enabled, writes to the CR bit will not change the PCA counter state; the counter will run
until the WDT is disabled. The PCA counter run control bit (CR) will read zero if the WDT is enabled but
user software has not enabled the PCA counter. If a match occurs between PCA0CPH2 and PCA0H while
the WDT is enabled, a reset will be generated. To prevent a WDT reset, the WDT may be updated with a
write of any value to PCA0CPH2. Upon a PCA0CPH2 write, PCA0H plus the offset held in PCA0CPL2 is
loaded into PCA0CPH2 (See Figure 25.11).
Figure 25.11. PCA Module 2 with Watchdog Timer Enabled
PCA0H
Enable
PCA0L Overflow
Reset
PCA0CPL2 8-bit Adde r
PCA0CPH2
Adder
Enable
PCA0MD
C
I
D
L
W
D
T
E
E
C
F
C
P
S
1
C
P
S
0
W
D
L
C
K
C
P
S
2
Match
Write to
PCA0CPH2
8-bit
Comparator
C8051F336/7/8/9
Rev.1.0 214
The 8-bit offset held in PCA0CPH2 is compared to the upper byte of the 16-bit PCA counter. This offset
value is the number of PCA0L overflows before a reset. Up to 256 PCA clocks may pass before the first
PCA0L overflow occurs, dependin g on the value of the PCA0L when the update is performed. The to tal of f-
set is then given (in PCA clocks) by Equation 25.5, where PCA0L is the value of the PCA0L register at the
time of the update.
Equation 25.5. Watchdog Timer Offset in PCA Clocks
The WDT reset is generated when PCA0L overflows while there is a match between PCA0CPH2 and
PCA0H. Software may force a WDT reset by writing a 1 to the CCF2 flag (PCA0CN.2) while the WDT is
enabled.
25.4.2. Watchdog Timer Usage
To configure the WDT, perform the following tasks:
1. Disable the WDT by writing a 0 to the WDT E bit.
2. Select the desired PCA clock source (with the CPS2–CPS0 bits).
3. Load PCA0CPL2 with the desired WDT update offset value.
4. Configure the PCA Idle mode (set CIDL if the WDT should be suspende d while the CPU is in Idle
mode).
5. Enable the WDT by setting the WDTE bit to 1.
6. Reset the WDT timer by writing to PCA0CPH2.
The PCA clock source and Idle mode select cannot be changed while the WDT is enabled. The watchdog
timer is enabled by setting the WDTE or WDLCK bits in the PCA0MD register. When WDLCK is set, the
WDT cannot be disabled until the next system reset. If WDLCK is not set, the WDT is disabled by clearing
the WDTE bit.
The WDT is enabled following any reset. The PCA0 counter clock defaults to the system clock divided by
12, PCA0L defaults to 0x00, and PCA0CPL2 defaults to 0x00. Using Equation 25.5, this results in a WDT
timeout interval of 256 PCA clock cycles, or 3072 system clock cycles. Table 25.3 lists some example tim-
eout intervals for typical system clocks.
Table 25.3. Watchdog Timer Timeout Intervals1
System Clock (Hz) PCA0CPL2 Timeout Interval (ms)
24,500,000 255 32.1
24,500,000 128 16.2
24,500,000 32 4.1
3,062,5002255 257
3,062,5002128 129.5
3,062,500232 33.1
32,000 255 24576
32,000 128 12384
32,000 32 3168
Notes:
1. Assumes SYSCLK/12 as the PCA clock source, and a PCA0L value
of 0x00 at the update time.
2. Internal SYSCLK reset frequency = Internal Oscillator divided by 8.
Offset 256 PCA0CPL2×()256 PCA0L–()+=
C8051F336/7/8/9
215 Rev.1.0
25.5. Register Descriptions for PCA0
Following are detailed descriptions of the special function registers related to the operation of the PCA.
SFR Address = 0xD8; Bit-Addressable
SFR Definition 25.1. PCA0CN: PCA Control
Bit76543210
Name CF CR CCF2 CCF1 CCF0
Type R/W R/W R R R R/W R/W R/W
Reset 00000000
Bit Name Function
7CF
PCA Counter/Timer Overflow Flag.
Set by hardware when the PCA Counter/Timer overflows from 0xFFFF to 0x0000.
When the Counter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the
CPU to vector to th e PCA inte rrupt service r outin e. This b it is not au toma tically cleared
by hardware and must be cleared by software.
6CR
PCA Counter/Timer Run Control.
This bit enables/disables the PCA Counter/Timer.
0: PCA Counter/Timer disabled.
1: PCA Counter/Timer enabled.
5:3 Unused Unused. Read = 00 0b, Write = Don't care.
2 CCF2 PCA Module 2 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF2 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA interrupt service rou-
tine. This bit is not autom atically cleared by hardware an d must be cleared by sof tware.
1 CCF1 PCA Module 1 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF1 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA interrupt service rou-
tine. This bit is not autom atically cleared by hardware an d must be cleared by sof tware.
0 CCF0 PCA Module 0 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF0 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA interrupt service rou-
tine. This bit is not autom atically cleared by hardware an d must be cleared by sof tware.
C8051F336/7/8/9
Rev.1.0 216
SFR Address = 0xD9
SFR Definition 25.2. PCA0MD: PCA Mode
Bit76543210
Name CIDL WDTE WDLCK CPS2 CPS1 CPS0 ECF
Type R/W R/W R/W R R/W R/W R/W R/W
Reset 01000000
Bit Name Function
7CIDL
PCA Counter/Timer Idle Control.
Specifies PCA behavior when CPU is in Idle Mode.
0: PCA continues to function normally while the system controller is in Idle Mode.
1: PCA operation is suspended while the system controller is in Idle Mode.
6WDTE
Watchdog Timer Enable.
If this bit is set, PCA Module 2 is used as the watchdog timer.
0: Watchdog Timer disabled.
1: PCA Module 2 enabled as Watchdog Timer.
5 WDLCK Watchdog Timer Lock.
This bit locks/unlocks the Watchdog T imer Enab le. When WDLCK is se t, the W atchdog
Timer may not be disabled until the next system reset.
0: Watchdog Timer Enable unlocked.
1: Watchdog Timer Enable locked.
4 Unused Unused. Read = 0b, Write = Don't care.
3:1 CPS[2:0] PCA Counter/Timer Pulse Select.
These bits select the timebase source for the PCA counter
000: System clock divided by 12
001: System clock divided by 4
010: Timer 0 over flow
011: High-to-low transitions on ECI (max rate = system clo ck divided by 4)
100: System clock
101: External clock divided by 8 (synchronized with the system clock)
11x: Reserved
0ECF
PCA Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA Counter/Timer Overflow (CF) interrupt.
0: Disable the CF interrupt.
1: Enable a PCA Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is
set.
Note: When the WDTE bit is set to 1, the other bits in the PCA0MD register cannot be modified. To change the
contents of the PCA0MD register, the Watchdog Timer must first be disabled.
C8051F336/7/8/9
217 Rev.1.0
SFR Address = 0xF7
SFR Definition 25.3. PCA0PWM: PCA PWM Configuration
Bit76543210
Name ARSEL ECOV COVF CLSEL[1:0]
Type R/W R/W R/W R R R R/W
Reset 00000000
Bit Name Function
7ARSEL
Auto-Reload Register Select.
This bit selects whether to read and write the normal PCA capture/compare registers
(PCA0CPn), or the Auto-Reload registers at the same SFR addresses. This function
is used to define the reload value for 9, 10, and 11-bit PWM modes. In all other
modes, the Aut o- R e loa d re gis te rs ha ve no fu nc tion .
0: Read/Write Capture/Compare Registers at PCA0CPHn and PCA0CPLn.
1: Read/Write Auto-Reload Registers at PCA0CPHn and PCA0CPLn.
6ECOV
Cycle Overflow Interrupt Enable .
This bit sets the masking of the Cycle Overflow Flag (COVF) interrupt.
0: COVF will not generate PCA interrupts.
1: A PCA interrupt will be generated when COVF is set.
5COVF
Cycle Overflow Flag.
This bit indicates an overflow of the 8th, 9th , 10th, or 11th bit of the main PCA counter
(PCA0). The specific bit used for this flag depends on the setting of the Cycle Length
Select bits. The bit can be set by hardware or software, but must be cleared by soft-
ware.
0: No overflow has occurred since the last time this bit was clea red.
1: An overflow has occurred since the last time this bit was cleared.
4:2 Unused Unused. Read = 000b; Write = Don’t care.
1:0 CLSEL[1:0] Cycle Length Select.
When 16-bit PWM mode is not selected, these bits select the length of the PWM
cycle, between 8, 9, 10, or 11 bits. This affects all channels configured for PWM which
are not using 16-bit PWM mode. These bits are ignored for individual channels config-
ured to16-bit PWM mode.
00: 8 bits.
01: 9 bits.
10: 10 bits.
11: 11 bits.
C8051F336/7/8/9
Rev.1.0 218
SFR Addresses: PCA0CPM0 = 0xDA, PCA0CPM1 = 0xDB, PCA0CPM2 = 0xDC
SFR Definition 25.4. PCA0CPMn: PCA Capture/Compare Mode
Bit76543210
Name PWM16n ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7PWM16n
16-bit Pulse Width Modulation Enable.
This bit enables 16-bit mode when Pulse Width Modulation mode is enabled.
0: 8 to 11-bit PW M se lec te d.
1: 16-bit PWM selected.
6ECOMn
Comparator Function Enable.
This bit enables the compar ator function for PCA module n when set to 1.
5 CAPPn Capture Positive Function Enable.
This bit enables the positive edge capture for PCA module n when set to 1.
4 CAPNn Capture Negative Function Enable.
This bit enables the negative edge capture for PCA module n when set to 1.
3MATn
Match Function Enable.
This bit enables the match function for PCA module n when set to 1. When enabled,
matches of the PCA counter with a m odule's capture/comp are register cause the CCFn
bit in PCA0MD register to be set to logic 1.
2TOGn
Toggle Function Enable.
This bit enables the toggle function for PCA module n when set to 1. When enabled,
matches of the PCA counter with a module's capture/compare register cause the logic
level on the CEXn pin to toggle. If the PWMn bit is also set to logic 1, the module oper-
ates in Frequency Output Mode.
1PWMn
Pulse Width Modulation Mode Enable.
This bit enables the PWM function for PCA module n when set to 1. When enabled, a
pulse width modulated signal is output on the CEXn pin. 8 to 11-bit PWM is used if
PWM16n is cleared; 16-bit mo de is used if PWM16n is set to logic 1. If the TOGn bit is
also set, the module operate s in Frequency Output Mode.
0ECCFn
Capture/Compare Flag Interrupt Enable.
This bit sets the masking of the Capture/Compare Flag (CCFn) interrupt.
0: Disable CCFn interrupts.
1: Enable a Capture/Compare Flag interrupt request when CCFn is set.
Note: When the WDTE bit is set to 1, the PCA0CPM2 register cannot be modified, and module 2 acts as the
watchdog timer . To change the contents of the PCA0CPM2 register or the function of module 2, the Watchdog
Timer must be disabled.
C8051F336/7/8/9
219 Rev.1.0
SFR Address = 0xF9
SFR Address = 0xFA
SFR Definition 25.5. PCA0L: PCA Counter/Timer Low Byte
Bit76543210
Name PCA0[7:0]
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7:0 PCA0[7:0] PCA Counter/Timer Low Byte.
The PCA0L register holds the low byte (LSB) of the 16-bit PCA Counter/Timer.
Note: When the WDTE bit is set to 1, the PCA0L register cannot be modified by software. To change the contents of
the PCA0L register, the Watchdog Timer must first be disa bled.
SFR Definition 25.6. PCA0H: PCA Counter/Timer High Byte
Bit76543210
Name PCA0[15:8]
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7:0 PCA0[15:8] PCA Counter/Timer High Byte.
The PCA0H register holds the high byte (MSB) of the 16-bit PCA Counter/Timer.
Reads of this register will read the contents of a “snapshot ” register, whose contents
are updated only when the contents of PCA0L are read (see Section 25.1).
Note: When the WDTE bit is set to 1, the PCA0H register cannot be modified by software. To change the contents of
the PCA0H register, the Watchdog Timer must first be disabled.
C8051F336/7/8/9
Rev.1.0 220
SFR Addresses: PCA0CPL0 = 0xFB, PCA0CPL1 = 0xE9, PCA0CPL2 = 0xEB
SFR Addresses: PCA0CPH0 = 0xFC, PCA0CPH1 = 0xEA, PCA0CPH2 = 0xEC
SFR Definition 25.7. PCA0CPLn: PCA Capture Module Low Byte
Bit76543210
Name PCA0CPn[7:0]
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7:0 PCA0CPn[7:0] PCA Capture Module Low Byte.
The PCA0CPLn register holds the low byte (LSB) of the 16-bit capture module n.
This register address also allows access to the low byte of the corresponding
PCA channel’s auto-reload value for 9, 10, or 11-bit PWM mode. The ARSEL bit
in register PCA0PWM controls which register is accessed.
Note: A write to this regi ster will clear the modu l e’s ECO Mn bi t to a 0.
SFR Definition 25.8. PCA0CPHn: PCA Capture Module High Byte
Bit76543210
Name PCA0CPn[15:8]
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7:0 PCA0CPn[15:8] PCA Capture Module High Byte.
The PCA0CPHn register holds the high byte (MSB) of the 16-bit capture module n.
This register address also allows access to the high byte of the corresponding
PCA channel’ s auto-reload value for 9, 10, or 11-bit PWM mode. The ARSEL bit in
register PCA0PWM controls which register is accessed.
Note: A write to this register will set the module’s ECOMn bit to a 1.
C8051F336/7/8/9
Rev.1.0 221
26. C2 Interface
C8051F336/7/8/9 devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow Flash pro-
gramming and in-system debugging with the production part installed in the end application. The C2 inter-
face uses a clock signal (C2CK) and a bi-directional C2 data signal (C2D) to transfer information between
the device and a host system. See the C2 Interface Specification for details on the C2 protocol.
26.1. C2 Interface Registers
The following describes the C2 registers necessary to perform Flash programming through the C2 inter-
face. All C2 registers are accessed throug h the C2 interface as de scribed in the C2 Interface Specification.
C2 Register Definition 26.1. C2ADD: C2 Address
Bit76543210
Name C2ADD[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 C2ADD[7:0] C2 Address.
The C2ADD register is accessed via the C2 interface to select the target Data register
for C2 Data Read and Data Write commands.
Address Description
0x00 Selects the Device ID register for Data Read instructions
0x01 Selects the Revision ID register for Data Read instructions
0x02 Selects the C2 Fla sh Programming Control register for Data
Read/Write instructions
0xB4 Selects the C2 Flash Programming Data register for Data
Read/Write instructions
C8051F336/7/8/9
222 Rev.1.0
C2 Address: 0x00
C2 Address: 0x01
C2 Register Definition 26.2. DEVICEID: C2 Device ID
Bit76543210
Name DEVICEID[7:0]
Type R/W
Reset 00010100
Bit Name Function
7:0 DEVICEID[7:0] Device ID.
This read-only register returns the 8-bit device ID: 0x14 (C8051F336/7/8/9).
C2 Register Definition 26.3. REVID: C2 Revision ID
Bit76543210
Name REVID[7:0]
Type R/W
Reset Varies Varies Varies Varies Varies Varies Varies Varies
Bit Name Function
7:0 REVID[7:0] Revision ID.
This read-only register returns the 8-bit revision ID. For example: 0x00 = Revision A.
C8051F336/7/8/9
Rev.1.0 223
C2 Address: 0x02
C2 Address: 0xB4
C2 Register Definition 26.4. FPCTL: C2 Flash Programming Control
Bit76543210
Name FPCTL[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 FPCTL[7:0] Flash Programming Control Register.
This register is used to enable Flash programming via the C2 interface. To enable C2
Flash programming, the followin g codes must be written in order: 0x02, 0x01. Note
that once C2 Flash programming is enabled, a system reset must be issued to
resume normal operation.
C2 Register Definition 26.5. FPDAT: C2 Flash Programming Data
Bit76543210
Name FPDAT[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 FPDAT[7:0] C2 Flash Programming Data Register.
This register is used to pass Flash commands, addresses, and data during C2 Flash
accesses . Valid command s ar e lis te d be low.
Code Command
0x06 Flash Block Read
0x07 Flash Block Write
0x08 Flash Page Erase
0x03 Device Erase
C8051F336/7/8/9
224 Rev.1.0
26.2. C2 Pin Sharing
The C2 protocol allows the C2 pins to be shared with user functions so that in-system debugging and
Flash programming may be performed. This is possible because C2 communication is typically performed
when the device is in the halt state, where all on-chip peripherals and user software are stalled. In this
halted state, the C2 interface can safely ‘borrow’ the C2CK (RST) and C2D pins. In most applications,
external resistors are required to isolate C2 interface traffic from the user application. A typical isolation
configuration is shown in Figure 26.1.
Figure 26.1. Typical C2 Pin Sharing
The configuration in Figure 26.1 assumes the following:
1. The user input ( b) cannot change state while the target device is halted.
2. The RST pin on the target device is used as an input only.
Additional resistors may be necessary depending on the specific application.
C2D
C2CK
/Reset (a)
Input (b)
Output (c)
C2 Interface Master
C8051Fxxx
C8051F336/7/8/9
Rev.1.0 225
DOCUMENT CHANGE LIST
Revision 0.2 to Revision 1.0
Updated electrical specification tables based on test, characterization, and qualification data.
Corrected minor errors in figures and text.
Updated package information with JEDEC standard drawings for package and land pattern.
Disclaimer
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using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific
device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories
reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy
or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply
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