Vishay Siliconix
Si9110, Si9111
Document Number: 70004
S11-0975-Rev. I, 16-May-11
www.vishay.com
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
High-Voltage Switchmode Controllers
FEATURES
• 10 V to 120 V Input Range
• Current-Mode Control
• High-Speed, Source-Sink Output Drive
• High Efficiency Operation (> 80 %)
• Internal Start-Up Circuit
• Internal Oscillator (1 MHz)
• SHUTDOWN and RESET
• Reference Selection
Si9110 - ± 1 %
Si9111 - ± 10 %
DESCRIPTION
The Si9110/9111 are BiC/DMOS integrated circuits
designed for use as high-performance switchmode
controllers. A high-voltage DMOS input allows the controller
to work over a wide range of input voltages (10 to 120 VDC).
Current-mode PWM control circuitry is implemented in
CMOS to reduce internal power consumption to less than
10 mW.
A push-pull output driver provides high-speed switching for
MOSPOWER devices large enough to supply 50 W of output
power. When combined with an output MOSFET and
transformer, the Si9110/9111 can be used to implement
single-ended power converter topologies (i.e., flyback,
forward, and cuk).
The Si9110/9111 are available in both standard and lead
(Pb)-free 14-pin plastic DIP and SOIC packages which are
specified to operate over the industrial temperature range of
- 40 °C to 85 °C.
FUNCTIONAL BLOCK DIAGRAM
+
-
+
+
-
+
-
+
-
FB COMP DISCHARGE
OSC
14 13 9 8 7
2 V
Ref
Gen R
S
Q
R
S
Q
SENSE
3
5
4
11
12
Current-Mode
Comparator
C/L
1.2 V
Undervoltage
RESET
8.1 V
8.6 V
BIAS Current
Sources
To
Internal
Circuits
10
1
6
2
Comparator
Error
Amplifier
VREF
VCC
+VIN
VCC
SHUTDOWN
4 V
OSC
OUT
OSC
IN
-VIN
Pre-Regulator/Start-Up
OUTPUT
To
VCC
Comparator
Clock (1/2 fOSC)
-
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Document Number: 70004
S11-0975-Rev. I, 16-May-11
Vishay Siliconix
Si9110, Si9111
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Notes:
a. Device Mounted with all leads soldered or welded to PC board.
b. Derate 6 mW/°C above 25 °C.
c. Derate 7.2 mW/°C above 25 °C.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS
Parameter Limit Unit
Voltages Referenced to - VIN (Note: VCC < + VIN + 0.3 V)
VCC 15
V
+VIN 120
Logic Inputs (RESET, SHUTDOWN, OSC IN, OSC OUT) - 0.3 to VCC + 0.3
Linear Inputs (FEEDBACK, SENSE, BIAS, VREF) - 0.3 to VCC + 0.3
HV Pre-Regulator Input Current (continuous) 5 mA
Storage Temperature - 65 to 150
°C
Operating Temperature - 40 to 85
Junction Temperature (TJ)150
Power Dissipation (Package)a14-Pin Plastic DIP (J Suffix)b750 mW
14-Pin SOIC (Y Suffix)c900
Thermal Impedance (JA)14-Pin Plastic DIP 167 °C/W
14-Pin SOIC 140
RECOMMENDED OPERATING RANGE
Parameter Limit Unit
Voltages Referenced to - VIN
VCC 9.5 to 13.5 V
+ VIN 10 to 120
fOSC 40 kHzto 1 MHz
ROSC 25 kto 1 M
Linear Inputs 0 to VCC - 3 V
Digital Inputs 0 to VCC
SPECIFICATIONSa
Parameter Symbol
Test Conditions
Unless Otherwise Specified
DISCHARGE = - VIN = 0 V
VCC = 10 V, + VIN = 48 V
RBIAS = 390 k, ROSC = 330 k
D Suffix
- 40 °C to 85 °C
Unit Temp.b Min.dTyp.cMax.d
Reference
Output Voltage VR
OSC IN = - VIN
(OSC Disabled)
RL = 10 M
Si9110 Room 3.92 4.0 4.08
V
Si9111 Room 3.60 4.0 4.40
Si9110 Full 3.86 4.14
Si9111 Full 3.52 4.46
Output ImpedanceeZOUT Room 15 30 45 k
Short Circuit Current ISREF VREF = - VIN Room 70 100 130 µA
Temperature StabilityeTREF Full 0.5 1.0 mV/°C
Oscillator
Maximum FrequencyefMAX ROSC = 0 Room 1 3 MHz
Initial Accuracy fOSC
ROSC = 330 k, See Note f Room 80 100 120 kHz
ROSC = 150 k, See Note f Room 160 200 240
Voltage Stability f/f f/f = f(13.5 V) - f(9.5 V)/f(9.5 V) Room 10 15 %
Temperature CoefficienteTOSC Full 200 500 ppm/°C
Document Number: 70004
S11-0975-Rev. I, 16-May-11
www.vishay.com
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Vishay Siliconix
Si9110, Si9111
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Notes:
a. Refer to PROCESS OPTION FLOWCHART for additional information.
b. Room = 25 °C, Full = as determined by the operating temperature suffix.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.
e. Guaranteed by design, not subject to production test.
f. CSTRAY Pin 8 = 5 pF.
SPECIFICATIONSa
Parameter Symbol
Test Conditions
Unless Otherwise Specified
DISCHARGE = - VIN = 0 V
VCC = 10 V, + VIN = 48 V
RBIAS = 390 k, ROSC = 330 k
D Suffix
- 40 °C to 85 °C
Unit Temp.b Min.dTyp.cMax.d
Error Amplifier
Feedback Input Voltage VFB FB Tied to COMP
OSC IN = - VIN, (OSC Disabled)
Si9110 Room 3.96 4.00 4.04 V
Si9111 Room 3.60 4.00 4.40
Input BIAS Current IFB OSC IN = - VIN, VFB = 4 V Room 25 500 nA
Input OFFSET Voltage VOS
OSC IN = - VIN
(OSC Disabled)
Room ± 15 ± 40 mV
Open Loop Voltage GaineAVOL Room 60 80 dB
Unity Gain BandwidtheBW Room 1 1.3 MHz
Dynamic Output ImpedanceeZOUT Room 1000 2000
Output Current IOUT
Source (VFB = 3.4 V) Room - 2.0 - 1.4 mA
Sink (VFB = 4.5 V) Room 0.12 0.15
Power Supply Rejection PSRR 9.5 V VCC 13.5 V Room 50 70 dB
Current Limit
Threshold Voltage VSOURCE VFB = 0 Room 1.0 1.2 1.4 V
Delay to OutputetdVSENSE = 1.5 V, See Figure 1 Room 100 150 ns
Pre-Regulator/Start-Up
Input Voltage + VIN IIN = 10 µA Room 120 V
Input Leakage Current + IIN VCC 9.4 V Room 10 µA
Pre-Regulator Start-Up Current ISTART Pulse Width 300 µs, VCC = VULVO Room 8 15 mA
VCC Pre-Regulator Turn-Off
Threshold Voltage VREG IPRE-REGULATOR = 10 µA Room 7.8 8.6 9.4
V
Undervoltage Lockout VUVLO Room 7.0 8.1 8.9
VREG - VUVLO VDELTA Room 0.3 0.6
Supply
Supply Current ICC VLOAD 75 pF (Pin 4) Room 0.45 0.6 1.0 mA
Bias Current IBIAS Room 10 15 20 µA
Logic
SHUTDOWN DelayetSD CL = 500 pF, VSENSE = - VIN, See Figure 2 Room 50 100
ns
SHUTDOWN Pulse WidthetSW See Figure 3 Room 50
RESET Pulse WidthetRW Room 50
Latching Pulse Width
SHUTDOWN and RESET Lowe tLW See Figure 3 Room 25
Input Low Voltage VIL Room 2.0 V
Input High Voltage VIH Room 8.0
Input Current Input Voltage High IIH VIN = 10 V Room 1 5 µA
Input Current Input Voltage Low IIL VIN = 0 V Room - 35 - 25
Output
Output High Voltage VOH IOUT = - 10 mA Room
Full 9.7
9.5 V
Output Low Voltage VOL IOUT = 10 mA Room
Full 0.30
0.50
Output Resistance ROUT IOUT = 10 mA, Source or Sink Room
Full 20
25
30
50
Rise TimeetrCL = 500 pF Room 40 75 ns
Fall TimeetfRoom 40 75
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Document Number: 70004
S11-0975-Rev. I, 16-May-11
Vishay Siliconix
Si9110, Si9111
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TIMING WAVEFORMS
TYPICAL CHARACTERISTICS
Figure 1.
90 %
OUTPUT
SENSE
1.5 V -
50 %
0
td
tr 10 ns
VCC
0 -
≤
Figure 2.
90 %
OUTPUT
0 -
50 % tf 10 ns
VCC
VCC
tSD
SHUTDOWN
0 -
≤
Figure 3.
0 -
50 % 50 %
50 % 50 %
RESET
0 -
VCC
VCC
tSW
tLW
tRW
SHUTDOWN tr, tf 10 ns
50 %
t
≤
Figure 4. + VIN vs. + IIN at Start-Up
VCC = - VIN
+V (V)
140
120
100
80
60
40
20
0
10 15 20
+IIN (mA)
IN
Figure 5. Output Switching Frequency
vs. Oscillator Resistance
(Hz)
1 M
10 k
100 k
10 k
100 k 1 M
fOUT
r
OSC
(Ω)
Document Number: 70004
S11-0975-Rev. I, 16-May-11
www.vishay.com
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Vishay Siliconix
Si9110, Si9111
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
PIN CONFIGURATIONS AND ORDERING INFORMATION
DETAILED DESCRIPTION
Pre-Regulator/Start-Up Section
Due to the low quiescent current requirement of the Si9110/
9111 control circuitry, bias power can be supplied from the
unregulated input power source, from an external regulated
low-voltage supply, or from an auxiliary "bootstrap" winding
on the output inductor or transformer.
When power is first applied during start-up, + VIN (pin 2) will
draw a constant current. The magnitude of this current is
determined by a high-voltage depletion MOSFET device
which is connected between + VIN and VCC (pin 6). This
start-up circuitry provides initial power to the IC by charging
an external bypass capacitance connected to the VCC pin.
The constant current is disabled when VCC exceeds 8.6 V. If
VCC is not forced to exceed the 8.6 V threshold, then VCC will
be regulated to a nominal value of 8.6 V by the pre-regulator
circuit.
As the supply voltage rises toward the normal operating
conditions, an internal undervoltage (UV) lockout circuit
keeps the output driver disabled until VCC exceeds the
undervoltage lockout threshold (typically 8.1 V). This
guarantees that the control logic will be functioning properly
and that sufficient gate drive voltage is available before the
MOSFET turns on. The design of the IC is such that the
undervoltage lockout threshold will be at least 300 mV less
than the pre-regulator turn-off voltage. Power dissipation can
be minimized by providing an external power source to VCC
such that the constant current source is always disabled.
Note: During start-up or when VCC drops below 8.6 V the
start-up circuit is capable of sourcing up to 20 mA. This may
lead to a high level of power dissipation in the IC (for a 48 V
input, approximately 1 W). Excessive start-up time caused
by external loading of the VCC supply can result in device
damage. Figure 6 gives the typical pre-regulator current at
BiC/DMOS as a function of input voltage.
BIAS
To properly set the bias for the Si9110/9111, a 390 k
resistor should be tied from BIAS (pin 1) to - VIN (pin 5). This
determines the magnitude of bias current in all of the analog
sections and the pull-up current for the SHUDOWN and
RESET pins. The current flowing in the bias resistor is
nominally 15 µA.
Reference Section
The reference section of the Si9110 consists of a
temperature compensated buried zener and trimmable
divider network. The output of the reference section is
connected internally to the non-inverting input of the error
amplifier. Nominal reference output voltage is 4 V. The
trimming procedure that is used on the Si9110 brings the
output of the error amplifier (which is configured for unity gain
during trimming) to within ± 1 % of 4 V. This compensates for
input offset voltage in the error amplifier.
The output impedance of the reference section has been
purposely made high so that a low impedance external
voltage source can be used to override the internal voltage
source, if desired, without otherwise altering the
performance of the device.
Applications which use a separate external reference, such
as non-isolated converter topologies and circuits employing
optical coupling in the feedback loop, do not require a
trimmed voltage reference with 1 % accuracy. The Si9111
accommodates the requirements of these applications at a
lower cost, by leaving the reference voltage untrimmed. The
10 % accurate reference thus provided is sufficient to
establish a dc bias point for the error amplifier.
Error Amplifier
Closed-loop regulation is provided by the error amplifier,
which is intended for use with "around-the-amplifier"
compensation. A MOS differential input stage provides for
low input current. The noninverting input to the error amplifier
(VREF) is internally connected to the output of the reference
supply and should be bypassed with a small capacitor to
ground.
BIAS FB
+VIN COMP
SENSE RESET
OUTPUT SHUTDOWN
-V
IN VREF
VCC DISCHARGE
OSC OUT OSC IN
Dual-In-Line and SOIC
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Top View
ORDERING INFORMATION
Part Number Temperature Range Package
Si9110DY
- 40 °C to 85 °C
SOIC-14
Si9110DY-T1
Si9110DY-T1-E3
Si9111DY
Si9111DY-T1
Si9111DY-T1-E3
Si9110DJ
PDIP-14
Si9110DJ-E3
Si9111DJ
Si9111DJ-E3
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Document Number: 70004
S11-0975-Rev. I, 16-May-11
Vishay Siliconix
Si9110, Si9111
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
DETAILED DESCRIPTION (CONT’D)
Oscillator Section
The oscillator consists of a ring of CMOS inverters,
capacitors, and a capacitor discharge switch. Frequency is
set by an external resistor between the OSC IN and OSC
OUT pins. (See Figure 5 for details of resistor value vs.
frequency.) The DISCHARGE pin should be tied to - VIN for
normal internal oscillator operation. A frequency divider in
the logic section limits switch duty cycle to 50 % by locking
the switching frequency to one half of the oscillator
frequency.
Remote synchronization is accomplished by capacitive
coupling of a positive SYNC pulse into the OSC IN (pin 8)
terminal. For a 5 V pulse amplitude and 0.5 µs pulse width,
typical values would be 100 pF in series with 3 k to pin 8.
SHUTDOWN and RESET
SHUTDOWN (pin 11) and RESET (pin 12) are intended for
overriding the output MOSFET switch via external control
logic. The two inputs are fed through a latch preceding the
output switch. Depending on the logic state of RESET,
SHUTDOWN can be either a latched or unlatched input. The
output is off whenever SHUTDOWN is low. By
simultaneously having SHUTDOWN and RESET low, the
latch is set and SHUTDOWN has no effect until RESET goes
high. The truth table for these inputs is given in Table 1.
Table 1. Truth Table for the SHUTDOWN and RESET Pins
Both pins have internal current source pull-ups and should
be left disconnected when not in use. An added feature of the
current sources is the ability to connect a capacitor and an
open-collector driver to the SHUTDOWN or RESET pins to
provide variable shutdown time.
Output Driver
The push-pull driver output has a typical on-resistance of
20 . Maximum switching times are specified at 75 ns for a
500 pF load. This is sufficient to directly drive MOSFETs
such as the 2N7004, 2N7005, IRFD120 and IRFD220.
Larger devices can be driven, but switching times will be
longer, resulting in higher switching losses. In order to drive
large MOSPOWER devices, it is necessary to use an
external driver IC, such as the Vishay Siliconix D469A. The
D469A can switch very large devices such as the
SMM20N50 (500 V, 0.3 ) in approximately 100 ns.
APPLICATIONS
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?70004.
SHUTDOWN RESET Output
H H Normal Operation
H Normal Operation (No Change)
L H Off (Not Latched)
L L Off (Latched)
L Off (Latched, No Change)
Figure 6. 5 Watt Power Supply for Telecom Applications
Si9110
GND
FEEDBACK
- 48 V
240 k
390 k
13
14
6
10
1
59
2
8
7
4
3
150 k
3 k
100 pF
2N7004 18 k
12 k
1N5822
1N5819
1N4148
VCC
20 µ F0.1 µ F
0.022 µ F
0.1 µ F
1 µ F
220 µ F
47 µ F
OSC SYNC PULSE
(If Needed)
+ 5 V
at 0.75 A
- 5 V
at 0.25 A
To Pin 6 VCC
Feedback
To Pin 14
1 Ω
1/2 W
Ø
ALL LEADS
0.101 mm
0.004″
E
D
eBA1
A
H
L
C
0.25
(GAGE PLANE)
1234567
14 13 12 11 10 9 8
Package Information
Vishay Siliconix
Document Number: 72809
28-Jan-04
www.vishay.com
1
SOIC (NARROW): 14-LEAD (POWER IC ONLY)
MILLIMETERS INCHES
Dim Min Max Min Max
A1.35 1.75 0.053 0.069
A10.10 0.20 0.004 0.008
B0.38 0.51 0.015 0.020
C0.18 0.23 0.007 0.009
D8.55 8.75 0.336 0.344
E3.8 4.00 0.149 0.157
e1.27 BSC 0.050 BSC
H5.80 6.20 0.228 0.244
L0.50 0.93 0.020 0.037
Ø0_8_0_8_
ECN: S-40080—Rev. A, 02-Feb-04
DWG: 5914
E1E
Q1
A
L
A1
e1B
B1
S
C
eA
D
15°
MAX
1234567
14 13 12 11 10 9 8
Package Information
Vishay Siliconix
Document Number: 72814
28-Jan-04
www.vishay.com
1
PDIP: 14-LEAD (POWER IC ONLY)
MILLIMETERS INCHES
Dim Min Max Min Max
A3.81 5.08 0.150 0.200
A10.38 1.27 0.015 0.050
B0.38 0.51 0.015 0.020
B10.89 1.65 0.035 0.065
C0.20 0.30 0.008 0.012
D17.27 19.30 0.680 0.760
E7.62 8.26 0.300 0.325
E15.59 7.11 0.220 0.280
e12.29 2.79 0.090 0.110
eA7.37 7.87 0.290 0.310
L2.79 3.81 0.110 0.150
Q11.27 2.03 0.050 0.080
S1.02 2.03 0.040 0.080
ECN: S-40081—Rev. A, 02-Feb-04
DWG: 5919
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Revision: 02-Oct-12 1Document Number: 91000
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