36-Mbit (1M × 36/2M × 18) Pipelined SRAM
with NoBL™ Architecture (With ECC)
CY7C1460KV33
CY7C1460KVE33
CY7C1462KVE33
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-66680 Rev. *L Revised February 8, 2018
36-Mbit (1M × 36/2M × 18) Pipelined SRAM with NoBL™ Architecture (With ECC)
Features
■Pin-compatible and functionally equivalent to Zero Bus
Turnaround (ZBT™)
■Supports 250-MHz bus operations with zero wait states
❐Available speed grades are 250, 200, and 167 MHz
■Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
■Fully-registered (inputs and outputs) for pipelined operation
■Byte write capability
■3.3-V power supply
■3.3-V/2.5-V I/O power supply
■Fast clock-to-output time
❐2.5 ns (for 250-MHz device)
■Clock enable (CEN) pin to suspend operation
■Synchronous self-timed writes
■CY7C1460KV33, CY7C1460KVE33, CY7C1462KVE33
available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free
and non Pb-free 165-ball FBGA packages
■IEEE 1149.1 JTAG-compatible boundary scan
■Burst capability—linear or interleaved burst order
■“ZZ” sleep mode option
■On-chip Error Correction Code (ECC) to reduce Soft Error Rate
(SER)
Functional Description
The CY7C1460KV33/CY7C1460KVE33/CY7C1462KVE33 are
3.3 V, 1M × 36, and 2M × 18 synchronous pipelined burst SRAMs
with No Bus Latency™ (NoBL™) logic, respectively. They are
designed to support unlimited true back-to-back read/write
operations with no wait states. The
CY7C1460KV33/CY7C1460KVE33/CY7C1462KVE33 devices
are equipped with the advanced (NoBL) logic required to enable
consecutive read/write operations with data being transferred on
every clock cycle.
This feature dramatically improves the throughput of data in
systems that require frequent write and read transitions. The
CY7C1460KV33/CY7C1460KVE33/CY7C1462KVE33 devices
are pin-compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle.
Write operations are controlled by the byte write selects
(BWa–BWd for CY7C1460KV33/CY7C1460KVE33 and
BWa–BWb for CY7C1462KVE33) and a write enable (WE) input.
All writes are conducted with on-chip synchronous self-timed
write circuitry.
Three synchronous chip enables (CE1, CE2, and CE3) and an
asynchronous output enable (OE) enable easy bank selection
and output tristate control. To avoid bus contention, the output
drivers are synchronously tristated during the data portion of a
write sequence.
Selection Guide
Description 250 MHz 200 MHz 167 MHz Unit
Maximum access time 2.5 3.2 3.4 ns
Maximum operating current × 18 220 190 170 mA
× 36 240 210 190
Document Number: 001-66680 Rev. *L Page 2 of 31
CY7C1460KV33
CY7C1460KVE33
CY7C1462KVE33
A0, A1, A
C
MODE
BW
a
BW
b
WE
CE1
CE2
CE3
OE
READ LOGIC
DQ
s
DQ
P
a
DQ
P
b
DQ
P
c
DQ
P
d
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
MEMORY
ARRAY
E
E
INPUT
REGISTER 0
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC
A0'
A1'
D1
D0
Q1
Q0
A0
A1
C
ADV/LD
ADV/LD
E
INPUT
REGISTER 1
S
E
N
S
E
A
M
P
S
E
C
LK
C
EN
WRITE
DRIVERS
BW
c
BW
d
ZZ
SLEEP
CONTROL
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
Logic Block Diagram – CY7C1460KV33
Logic Block Diagram – CY7C1460KVE33
A0, A1, A
C
MODE
BW
A
BW
B
WE
CE1
CE2
CE3
OE READ LOGIC
DQs
DQP
A
DQP
B
DQP
C
DQP
D
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
MEMORY
ARRAY
E
E
INPUT
REGISTER 0
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC
A0'
A1'
D1
D0
Q1
Q0
A0
A1
C
ADV/LD
ADV/LD
E
INPUT
REGISTER 1
S
E
N
S
E
A
M
P
S
E
CLK
CEN
WRITE
DRIVERS
BW
C
BW
D
ZZ
SLEEP
CONTROL
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
ECC
ENCODER
E
C
C
D
E
C
O
D
E
R
Document Number: 001-66680 Rev. *L Page 3 of 31
CY7C1460KV33
CY7C1460KVE33
CY7C1462KVE33
Logic Block Diagram – CY7C1462KVE33
A0, A1, A
C
MODE
BW
A
BW
B
WE
CE1
CE2
CE3
OE
READ LOGIC
DQs
DQPA
DQPB
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
MEMORY
ARRAY
E
E
INPUT
REGISTER 0
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC
A0'
A1'
D1
D0
Q1
Q0
A0
A1
C
ADV/LD
ADV/LD
E
INPUT
REGISTER 1
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
CLK
CEN
WRITE
DRIVERS
ZZ
Sleep
Control
ECC
ENCODER
E
C
C
D
E
C
O
D
E
R
Document Number: 001-66680 Rev. *L Page 4 of 31
CY7C1460KV33
CY7C1460KVE33
CY7C1462KVE33
Contents
Pin Configurations ........................................................... 5
Pin Definitions .................................................................. 7
Functional Overview ........................................................ 8
Single Read Accesses ................................................ 8
Burst Read Accesses .................................................. 8
Single Write Accesses ................................................. 9
Burst Write Accesses .................................................. 9
Sleep Mode ................................................................. 9
On-Chip ECC .............................................................. 9
Interleaved Burst Address Table ...............................10
Linear Burst Address Table ....................................... 10
ZZ Mode Electrical Characteristics ............................10
Truth Table ...................................................................... 11
Partial Write Cycle Description ..................................... 12
Partial Write Cycle Description ..................................... 12
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13
Disabling the JTAG Feature ...................................... 13
Test Access Port (TAP) ............................................. 13
PERFORMING A TAP RESET .................................. 13
TAP REGISTERS ...................................................... 13
TAP Instruction Set ................................................... 14
TAP Controller State Diagram ....................................... 15
TAP Controller Block Diagram ...................................... 15
TAP Timing Diagram ...................................................... 15
TAP AC Switching Characteristics ...............................16
3.3 V TAP AC Test Conditions ....................................... 17
3.3 V TAP AC Output Load Equivalent ......................... 17
2.5 V TAP AC Test Conditions ....................................... 17
2.5 V TAP AC Output Load Equivalent ......................... 17
TAP DC Electrical Characteristics
and Operating Conditions ............................................. 17
Identification Register Definitions ................................ 18
Scan Register Sizes ....................................................... 18
Identification Codes ....................................................... 18
Boundary Scan Order .................................................... 19
Maximum Ratings ........................................................... 20
Operating Range ............................................................. 20
Neutron Soft Error Immunity ......................................... 20
Electrical Characteristics ............................................... 20
Capacitance .................................................................... 22
Thermal Resistance ........................................................ 22
AC Test Loads and Waveforms ..................................... 22
Switching Characteristics .............................................. 23
Switching Waveforms .................................................... 24
Ordering Information ...................................................... 26
Ordering Code Definitions ......................................... 26
Package Diagrams .......................................................... 27
Acronyms ........................................................................ 29
Document Conventions ................................................. 29
Units of Measure ....................................................... 29
Document History Page ................................................. 30
Sales, Solutions, and Legal Information ...................... 31
Worldwide Sales and Design Support ....................... 31
Products .................................................................... 31
PSoC® Solutions ...................................................... 31
Cypress Developer Community ................................. 31
Technical Support ..................................................... 31
Document Number: 001-66680 Rev. *L Page 5 of 31
CY7C1460KV33
CY7C1460KVE33
CY7C1462KVE33
Pin Configurations
Figure 1. 100-pin TQFP Pinout
A
A
A
A
A1
A0
VSS
VDD
A
A
A
A
A
A
VDDQ
VSS
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
VDD
DQa
DQa
VDDQ
VSS
DQa
DQa
VSS
VDDQ
VDDQ
VSS
DQc
DQc
VSS
VDDQ
DQc
VDD
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
VSS
VDDQ
A
A
CE1
CE2
BWa
CE3
VDD
VSS
CLK
WE
CEN
OE
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
ADV/LD
ZZ
CY7C1460KV33/CY7C1460KVE33
A
A
A
A
A1
A0
VSS
VDD
A
A
A
A
A
A
A
NC
NC
VDDQ
VSS
NC
DQPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
NC
VDD
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
NC
NC
NC
VDDQ
VSS
NC
NC
DQb
DQb
VSS
VDDQ
DQb
DQb
VDD
VSS
DQb
DQb
VDDQ
VSS
DQb
DQb
DQPb
NC
VSS
VDDQ
NC
NC
NC
A
A
CE1
CE2
NC
NC
BWb
BWa
CE3
VDD
VSS
CLK
WE
CEN
OE
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
ADV/LD
ZZ
MODE
CY7C1462KVE33
BWd
MODE
BWc
DQc
DQc
DQc
DQc
DQPc
DQd
DQd
DQd
DQPb
DQb
DQa
DQa
DQa
DQa
DQPa
DQb
DQb
(1M × 36) (2M × 18)
BWb
NC
NC
NC
DQc
NC
NC/288M
NC/144M
NC/72M
NC/288M
NC/144M
NC/72M
DQPd
A
A
A
A
Document Number: 001-66680 Rev. *L Page 6 of 31
CY7C1460KV33
CY7C1460KVE33
CY7C1462KVE33
Figure 2. 165-ball FBGA Pinout
Pin Configurations (continued)
234 5671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
TDO
NC/576M
NC/1G
DQPc
DQc
DQPd
NC
DQd
ACE1BWb CE3
BWcCEN
ACE2
DQc
DQd
DQd
MODE
NC
DQc
DQc
DQd
DQd
DQd
NC/72M
VDDQ
BWdBWaCLK WE
VSS VSS VSS VSS
VDDQ VSS
VDD VSS
VSS
VSS
NC
VSS
VSS
VSS
VSS
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
A
A
VDD VSS
VDD VSS VSS
VDDQ VDD
VSS
VDD
VSS
VDD VSS VSS
VSS
VDD
VDD VSS
VDD VSS VSS
NC
TCKA0
VSS
TDI
A
A
DQcVSS
DQcVSS
DQc
DQc
NC
VSS
VSS
VSS
VSS
NC
VSS
A1
DQd
DQd
NC/144M
NC
VDDQ
VSS
TMS
891011
NC/288M
AAADV/LD NC
OE AANC
VSS VDDQ NC DQPb
VDDQ
VDD DQb
DQb
DQb
NC
DQb
NC
DQa
DQa
VDD VDDQ
VDD VDDQ DQb
VDD
NC
VDD
DQa
VDD VDDQ DQa
VDDQ
VDD
VDD VDDQ
VDD VDDQ DQa
VDDQ
AA
VSS
A
A
A
DQb
DQb
DQb
ZZ
DQa
DQa
DQPa
DQa
A
VDDQ
A
CY7C1460KVE33 (1M × 36)
A
Document Number: 001-66680 Rev. *L Page 7 of 31
CY7C1460KV33
CY7C1460KVE33
CY7C1462KVE33
Pin Definitions
Pin Name I/O Type Pin Description
A0, A1, A Input-synchronous Address inputs used to select one of the address locations. Sampled at the rising edge
of the CLK.
BWa, BWb,
BWc, BWd
Input-synchronous Byte write select inputs, active LOW. Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and
DQPb, BWc controls DQc and DQPc, BWd controls DQd and DQPd.
WE Input-synchronous Write enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW.
This signal must be asserted LOW to initiate a write sequence.
ADV/LD Input-synchronous Advance/load input used to advance the on-chip address counter or load a new
address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced.
When LOW, a new address can be loaded into the device for an access. After being
deselected, ADV/LD should be driven LOW to load a new address.
CLK Input-clock Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN is active LOW.
CE1Input-synchronous Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE2 and CE3 to select/deselect the device.
CE2Input-synchronous Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE3 to select/deselect the device.
CE3Input-synchronous Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE2 to select/deselect the device.
OE Input-asynchronous Output enable, active LOW. Combined with the synchronous logic block inside the device to
control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.
When deasserted HIGH, I/O pins are tristated, and act as input data pins. OE is masked during
the data portion of a write sequence, during the first clock when emerging from a deselected
state and when the device has been deselected.
CEN Input-synchronous Clock enable input, active LOW. When asserted LOW the clock signal is recognized by the
SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not
deselect the device, CEN can be used to extend the previous cycle when required.
DQa,
DQb,
DQc,
DQd
I/O-synchronous Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by AX during the read cycle. The direction of the pins is controlled by OE and the
internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH,
DQa–DQd are placed in a tristate condition. The outputs are automatically tristated during the
data portion of a write sequence, during the first clock when emerging from a deselected state,
and when the device is deselected, regardless of the state of OE.
DQPa,DQPb,
DQPc,DQPd
I/O-synchronous Bidirectional data parity I/O lines. Functionally, these signals are identical to DQ[31:0]. During
write sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled
by BWc, and DQPd is controlled by BWd.
MODE Input strap pin Mode input. Selects the burst order of the device. Tied HIGH selects the interleaved burst
order. Pulled LOW selects the linear burst order. MODE should not change states during
operation. When left floating MODE defaults HIGH, to an interleaved burst order.
TDO JTAG serial output
synchronous
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
TDI JTAG serial input
synchronous
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK.
TMS Test mode select
synchronous
This pin controls the test access port state machine. Sampled on the rising edge of TCK.
TCK JTAG-clock Clock input to the JTAG circuitry.
Document Number: 001-66680 Rev. *L Page 8 of 31
CY7C1460KV33
CY7C1460KVE33
CY7C1462KVE33
Functional Overview
The CY7C1460KV33/CY7C1460KVE33/CY7C1462KVE33
devices are synchronous-pipelined burst NoBL SRAMs designed
specifically to eliminate wait states during write/read transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with the
clock enable input signal (CEN). If CEN is HIGH, the clock signal
is not recognized and all internal states are maintained. All
synchronous operations are qualified with CEN. All data outputs
pass through output registers controlled by the rising edge of the
clock. Maximum access delay from the clock rise (tCO) is 2.5 ns
(250-MHz device).
Accesses can be initiated by asserting all three chip enables
(CE1, CE2, and CE3) active at the rising edge of the clock. If clock
enable (CEN) is active LOW and ADV/LD is asserted LOW, the
address presented to the device is latched. The access can
either be a read or write operation, depending on the status of
the write enable (WE). BW[x] can be used to conduct byte write
operations.
Write operations are qualified by the write enable (WE). All writes
are simplified with on-chip synchronous self timed write circuitry.
Three synchronous chip enables (CE1, CE2, and CE3) and an
asynchronous output enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
should be driven LOW after the device has been deselected to
load a new address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise:
■CEN is asserted LOW
■CE1, CE2, and CE3 are all asserted active
■The write enable input signal WE is deasserted HIGH
■ADV/LD is asserted LOW
The address presented to the address inputs is latched into the
address register and presented to the memory core and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the input
of the output register. At the rising edge of the next clock, the
requested data is allowed to propagate through the output
register and on to the data bus within 2.5 ns (250-MHz device)
provided OE is active LOW. After the first clock of the read
access, the output buffers are controlled by OE and the internal
control logic. OE must be driven LOW for the device to drive out
the requested data. During the second clock, a subsequent
operation (read/write/deselect) can be initiated. Deselecting the
device is also pipelined. Therefore, when the SRAM is
deselected at clock rise by one of the chip enable signals, its
output tristates following the next clock rise.
Burst Read Accesses
The CY7C1460KV33/CY7C1460KVE33/CY7C1462KVE33 have
an on-chip burst counter that enables the user the ability to
supply a single address and conduct up to four reads without
reasserting the address inputs. ADV/LD must be driven LOW to
load a new address into the SRAM, as described in the Single
Read Accesses section earlier. The sequence of the burst
counter is determined by the MODE input signal. A LOW input
on MODE selects a linear burst mode, a HIGH selects an
interleaved burst sequence. Both burst counters use A0 and A1
in the burst sequence, and wrap around when incremented
sufficiently. A HIGH input on ADV/LD increments the internal
burst counter regardless of the state of chip enables inputs or
WE. WE is latched at the beginning of a burst cycle. Therefore,
the type of access (read or write) is maintained throughout the
burst sequence.
VDD Power supply Power supply inputs to the core of the device.
VDDQ I/O power supply Power supply for the I/O circuitry.
VSS Ground Ground for the device. Should be connected to ground of the system.
NC N/A No connects. This pin is not connected to the die.
NC/72M N/A Not connected to the die. Can be tied to any voltage level.
NC/144M N/A Not connected to the die. Can be tied to any voltage level.
NC/288M N/A Not connected to the die. Can be tied to any voltage level.
NC/576M N/A Not connected to the die. Can be tied to any voltage level.
NC/1G N/A Not connected to the die. Can be tied to any voltage level.
ZZ Input-asynchronous ZZ “sleep” input. This active HIGH input places the device in a non-time critical “sleep”
condition with data integrity preserved. During normal operation, this pin can be connected to
VSS or left floating. ZZ pin has an internal pull-down.
Pin Definitions (continued)
Pin Name I/O Type Pin Description
Document Number: 001-66680 Rev. *L Page 9 of 31
CY7C1460KV33
CY7C1460KVE33
CY7C1462KVE33
Single Write Accesses
Write accesses are initiated when the following conditions are
satisfied at clock rise:
■CEN is asserted LOW
■CE1, CE2, and CE3 are all asserted active
■The write signal WE is asserted LOW
The address presented to the address inputs is loaded into the
address register. The write signals are latched into the control
logic block.
On the subsequent clock rise, the data lines are automatically
tristated regardless of the state of the OE input signal. This
enables the external logic to present the data on DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1460KV33/CY7C1460KVE33 and
DQa,b/DQPa,b for CY7C1462KVE33). In addition, the address for
the subsequent access (read/write/deselect) is latched into the
address register (provided the appropriate control signals are
asserted).
On the next clock rise, the data presented to DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1460KV33/CY7C1460KVE33 and
DQa,b/DQPa,b for CY7C1462KVE33), or a subset for byte write
operations, see the Write Cycle Description table for details)
inputs is latched into the device and the write is complete.
The data written during the write operation is controlled by the
BW (BWa,b,c,d for CY7C1460KV33/CY7C1460KVE33 and BWa,b
for CY7C1462KVE33) signals. The
CY7C1460KV33/CY7C1460KVE33/CY7C1462KVE33 provides
byte-write capability that is described in the Write Cycle
Description table. Asserting the write enable input (WE) with the
selected byte write select (BW) input selectively writes to only the
desired bytes. Bytes not selected during a byte write operation
remains unaltered. A synchronous self timed write mechanism
has been provided to simplify the write operations. Byte write
capability has been included to simplify read/modify/write
sequences, which can be reduced to simple byte write opera-
tions.
Because the CY7C1460KV33/ CY7C1460KVE33/
CY7C1462KVE33 devices are common I/O devices, data should
not be driven into the device while the outputs are active. The
output enable (OE) can be deasserted HIGH before presenting
data to the DQ and DQP (DQa,b,c,d/DQPa,b,c,d for
CY7C1460KV33/CY7C1460KVE33 and DQa,b/DQPa,b for
CY7C1462KVE33) inputs. Doing so tristates the output drivers.
As a safety precaution, DQ and DQP (DQa,b,c,d/DQPa,b,c,d for
CY7C1460KV33/CY7C1460KVE33 and DQa,b/DQPa,b for
CY7C1462KVE33) are automatically tristated during the data
portion of a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1460KV33/CY7C1460KVE33/CY7C1462KVE33
devices have an on-chip burst counter that allows the user the
ability to supply a single address and conduct up to four WRITE
operations without reasserting the address inputs. ADV/LD must
be driven LOW to load the initial address, as described in the
Single Write Accesses section. When ADV/LD is driven HIGH on
the subsequent clock rise, the chip enables (CE1, CE2, and CE3)
and WE inputs are ignored and the burst counter is incremented.
The correct BW inputs (BWa,b,c,d for
CY7C1460KV33/CY7C1460KVE33 and BWa,b for
CY7C1462KVE33) must be driven in each cycle of the burst write
to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE1, CE2,
and CE3, must remain inactive for the duration of tZZREC after the
ZZ input returns LOW.
On-Chip ECC
CY7C1460KVE33/CY7C1462KVE33 SRAMs include an on-chip
ECC algorithm that detects and corrects all single-bit memory
errors, including Soft Error Upset (SEU) events induced by
cosmic rays, alpha particles, and so on. The resulting Soft Error
Rate (SER) of these devices is anticipated to be <0.01 FITs/Mb,
a 4-order-of-magnitude improvement over comparable SRAMs
with no on-chip ECC, which typically have an SER of 200
FITs/Mb or more.To protect the internal data, ECC parity bits
(invisible to the user) are used.
The ECC algorithm does not correct multi-bit errors. However,
Cypress SRAMs are designed in such a way that a single SER
event has a very low probability of causing a multi-bit error
across any data word. The extreme rarity of multi-bit errors
results in a SER of <0.01 FITs/Mb.
Document Number: 001-66680 Rev. *L Page 10 of 31
CY7C1460KV33
CY7C1460KVE33
CY7C1462KVE33
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Linear Burst Address Table
(MODE = GND)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min Max Unit
IDDZZ Sleep mode standby current ZZ VDD 0.2 V – 75 mA
tZZS Device operation to ZZ ZZVDD 0.2 V – 2tCYC ns
tZZREC ZZ recovery time ZZ 0.2 V 2tCYC –ns
tZZI ZZ active to sleep current This parameter is sampled – 2tCYC ns
tRZZI ZZ inactive to exit sleep current This parameter is sampled 0 – ns
Document Number: 001-66680 Rev. *L Page 11 of 31
CY7C1460KV33
CY7C1460KVE33
CY7C1462KVE33
Truth Table
The Truth Table for CY7C1460KV33/CY7C1460KVE33/CY7C1462KVE33 follows. [1, 2, 3, 4, 5, 6, 7]
Operation Address
Used CE ZZ ADV/LD WE BWxOE CEN CLK DQ
Deselect cycle None H L L X X X L L–H Tristate
Continue deselect cycle None X L H X X X L L-H Tristate
Read cycle
(begin burst) External L L L H X L L L–H Data out (Q)
Read cycle
(continue burst) Next X L H X X L L L–H Data out (Q)
NOP/dummy read
(begin burst) External L L L H X H L L–H Tristate
Dummy read
(continue burst) Next X L H X X H L L–H Tristate
Write cycle
(begin burst) External L L L L L X L L–H Data in (D)
Write cycle
(continue burst) Next X L H X L X L L–H Data in (D)
NOP/WRITE ABORT
(begin burst) None L L L L H X L L–H Tristate
WRITE ABORT
(continue burst) Next X L H X H X L L–H Tristate
IGNORE CLOCK EDGE
(stall) Current X L X X X X H L–H –
SLEEP MODE None X H X X X X X X Tristate
Notes
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for all chip enables active. BWx = L signifies at least one byte write select is active, BWx = valid signifies
that the desired byte write selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE and BWX. See Write Cycle Description table for details.
3. When a write cycle is detected, all I/Os are tristated, even during byte writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.
5. CEN = H inserts wait states.
6. Device powers up deselected and the I/Os in a tristate condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQs and DQPX = Tristate when OE is
inactive or when the device is deselected, and DQs=data when OE is active.
Document Number: 001-66680 Rev. *L Page 12 of 31
CY7C1460KV33
CY7C1460KVE33
CY7C1462KVE33
Partial Write Cycle Description
The Partial Write Cycle Description for CY7C1460KV33/CY7C1460KVE33 follows. [8, 9, 10, 11]
Function (CY7C1460KV33/CY7C1460KVE33) WE BWdBWcBWbBWa
Read H X X X X
Write – no bytes written L H H H H
Write byte a – (DQa and DQPa)LHHHL
Write byte b – (DQb and DQPb)LHHLH
Write bytes b, a L H H L L
Write byte c – (DQc and DQPc)LHLHH
Write bytes c, a L H L H L
Write bytes c, b L H LL L H
Write bytes c, b, a L H L L L
Write byte d – (DQd and DQPd)LLHHH
Write bytes d, a L L H H L
Write bytes d, b L L H L H
Write bytes d, b, a L L H L L
Write bytes d, c L L L H H
Write bytes d, c, a L L L H L
Write bytes d, c, b L L L L H
Write all bytes LLLLL
Partial Write Cycle Description
The Partial Write Cycle Description for CY7C1462KVE33 follows. [9, 11]
Function (CY7C1462KVE33)WE BWbBWa
Read H x x
Write – no bytes written L H H
Write byte a – (DQa and DQPa)LHL
Write byte b – (DQb and DQPb)LLH
Write both bytes L L L
Notes
8. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for all chip enables active. BWx = L signifies at least one byte write select is active, BWx = valid signifies
that the desired byte write selects are asserted, see Write Cycle Description table for details.
9. Write is defined by WE and BWX. See Write Cycle Description table for details.
10. When a write cycle is detected, all I/Os are tristated, even during byte writes.
11. Table only lists partial byte write combinations. Any combination of BW[a:d] is valid. Appropriate write is done based on which byte write is active.
Document Number: 001-66680 Rev. *L Page 13 of 31
CY7C1460KV33
CY7C1460KVE33
CY7C1462KVE33
IEEE 1149.1 Serial Boundary Scan (JTAG)
CY7C1460KVE33 incorporates a serial boundary scan test
access port (TAP). This part is fully compliant with 1149.1. The
TAP operates using JEDEC-standard 3.3-V or 2.5-V I/O logic
level.
The CY7C1460KVE33 contains a TAP controller, instruction
register, boundary scan register, bypass register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are pulled
up internally and may be unconnected. They may alternately be
connected to VDD through a pull-up resistor. TDO should be left
unconnected. Upon power-up, the device enters a reset state,
which does not interfere with the operation of the device.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this ball unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. TDI is pulled up
internally and can be unconnected if the TAP is unused in an
application. TDI is connected to the most significant bit (MSB) of
any register (see TAP Controller Block Diagram).
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine. The output changes on the falling edge
of TCK. TDO is connected to the least significant bit (LSB) of any
register (see TAP Controller State Diagram).
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a high-Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test circuitry.
Only one register can be selected at a time through the
instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling
edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram.
Upon power-up, the instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to enable
fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW (VSS)
when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM. The length of the boundary scan
register for the SRAM in different packages is listed in the Scan
Register Sizes table.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used to
capture the contents of the I/O ring.
The Boundary Scan Order on page 19 and show the order in
which the bits are connected. Each bit corresponds to one of the
bumps on the SRAM package. The MSB of the register is
connected to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the Identification Register Definitions on
page 18.
Document Number: 001-66680 Rev. *L Page 14 of 31
CY7C1460KV33
CY7C1460KVE33
CY7C1462KVE33
TAP Instruction Set
Overview
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the Instruction
Codes table. Three of these instructions are listed as
RESERVED and should not be used. The other five instructions
described in detail are as follows.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction after it is shifted in, the TAP controller needs to be
moved into the Update-IR state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a high-Z state until the next command is given
during the “Update IR” state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the input and output pins is captured
in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output undergoes a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the clock captured in the boundary scan register.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior
to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required – that is, while data captured
is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected on a board.
EXTEST
The EXTEST instruction enables the preloaded data to be driven
out through the system output pins. This instruction also selects
the boundary scan register to be connected for serial access
between the TDI and TDO in the shift-DR controller state.
EXTEST OUTPUT BUS TRISTATE
IEEE Standard 1149.1 mandates that the TAP controller must be
able to put the output bus into a tristate mode.
The boundary scan register has a special bit located at bit #89
(for the 165-ball FBGA package). When this scan cell, called the
“extest output bus tristate,” is latched into the preload register
during the “Update-DR” state in the TAP controller, it directly
controls the state of the output (Q-bus) pins, when the EXTEST
is entered as the current instruction. When HIGH, it enables the
output buffers to drive the output bus. When LOW, this bit places
the output bus in a high-Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the “Shift-DR” state. During “Update-DR,” the value
loaded into that shift-register cell latches into the preload
register. When the EXTEST instruction is entered, this bit directly
controls the output Q-bus pins. Note that this bit is preset HIGH
to enable the output when the device is powered-up, and also
when the TAP controller is in the “Test-Logic-Reset” state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document Number: 001-66680 Rev. *L Page 15 of 31
CY7C1460KV33
CY7C1460KVE33
CY7C1462KVE33
TAP Controller State Diagram
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
TAP Controller Block Diagram
TAP Timing Diagram
TEST-LOGIC
RESET
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
CAPTURE-DR
SHIFT-DR
CAPTURE-IR
SHIFT-IR
EXIT1-DR
PAUSE-DR
EXIT1-IR
PAUSE-IR
EXIT2-DR
UPDATE-DR
EXIT2-IR
UPDATE-IR
1
1
1
0
1 1
0 0
1 1
1
0
0
0
0 0
0
0
0 0
1
0
1
1
0
1
0
1
1
1
1 0
Bypass Register
0
Instruction Register
012
Identication Register
012293031 ...
Boundary Scan Register
012..x ...
Selection
Circuitry
TCK
TMS TAP CONTROLLER
TDI TDO
Selection
Circuitry
tTL
Test Clock
(TCK)
123456
T
est Mode Select
(TMS)
tTH
Test Data-Out
(TDO)
tCYC
Test Data-In
(TDI)
tTMSH
tTMSS
tTDIH
tTDIS
tTDOX
tTDOV
DON’T CARE UNDEFINED
Document Number: 001-66680 Rev. *L Page 16 of 31
CY7C1460KV33
CY7C1460KVE33
CY7C1462KVE33
TAP AC Switching Characteristics
Over the Operating Range
Parameter [12, 13] Description Min Max Unit
Clock
tTCYC TCK clock cycle time 50 –ns
tTF TCK clock frequency –20 MHz
tTH TCK clock HIGH time 20 –ns
tTL TCK clock LOW time 20 –ns
Output Times
tTDOV TCK clock LOW to TDO valid –10 ns
tTDOX TCK clock LOW to TDO invalid 0 – ns
Setup Times
tTMSS TMS setup to TCK clock rise 5 – ns
tTDIS TDI setup to TCK clock rise 5 – ns
tCS Capture setup to TCK rise 5 – ns
Hold Times
tTMSH TMS hold after TCK clock rise 5 – ns
tTDIH TDI hold after clock rise 5 – ns
tCH Capture hold after clock rise 5 – ns
Notes
12. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
13. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 2 V/ns (Slew Rate).
Document Number: 001-66680 Rev. *L Page 17 of 31
CY7C1460KV33
CY7C1460KVE33
CY7C1462KVE33
3.3 V TAP AC Test Conditions
Input pulse levels ...............................................VSS to 3.3 V
Input rise and fall times (Slew Rate) ........................... 2 V/ns
Input timing reference levels ......................................... 1.5 V
Output reference levels ................................................ 1.5 V
Test load termination supply voltage ............................ 1.5 V
3.3 V TAP AC Output Load Equivalent
2.5 V TAP AC Test Conditions
Input pulse levels ...............................................VSS to 2.5 V
Input rise and fall times (Slew Rate) ........................... 2 V/ns
Input timing reference levels ....................................... 1.25 V
Output reference levels .............................................. 1.25 V
Test load termination supply voltage .......................... 1.25 V
2.5 V TAP AC Output Load Equivalent
TDO
1.5V
20pF
Z = 50Ω
O
50Ω
TDO
1.25V
20pF
Z = 50Ω
O
50Ω
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < TA < +70 °C; VDD = 3.135 V to 3.6 V unless otherwise noted)
Parameter [14] Description Test Conditions Min Max Unit
VOH1 Output HIGH voltage IOH = –4.0 mA, VDDQ = 3.3 V 2.4 – V
IOH = –1.0 mA, VDDQ = 2.5 V 2.0 – V
VOH2 Output HIGH voltage IOH = –100 µA VDDQ = 3.3 V 2.9 – V
VDDQ = 2.5 V 2.1 – V
VOL1 Output LOW voltage IOL = 8.0 mA VDDQ = 3.3 V – 0.4 V
IOL = 1.0 mA VDDQ = 2.5 V – 0.4 V
VOL2 Output LOW voltage IOL = 100 µA VDDQ = 3.3 V – 0.2 V
VDDQ = 2.5 V – 0.2 V
VIH Input HIGH voltage – VDDQ = 3.3 V 2.0 VDD + 0.3 V
VDDQ = 2.5 V 1.7 VDD + 0.3 V
VIL Input LOW voltage – VDDQ = 3.3 V –0.3 0.8 V
VDDQ = 2.5 V –0.3 0.7 V
IXInput load current GND < VIN < VDDQ –5 5 µA
Notes
14. All voltages referenced to VSS (GND).
15. Bit #24 is “1” in the ID Register Definitions for both 2.5-V and 3.3-V versions of this device.
Document Number: 001-66680 Rev. *L Page 18 of 31
CY7C1460KV33
CY7C1460KVE33
CY7C1462KVE33
Identification Register Definitions
Instruction Field CY7C1460KVE33
(1M × 36) Description
Revision number (31:29) 000 Describes the version number.
Device depth (28:24) [15] 01011 Reserved for internal use
Architecture/memory type(23:18) 001000 Defines memory type and architecture
Bus width/density(17:12) 100111 Defines width and density
Cypress JEDEC ID code (11:1) 00000110100 Allows unique identification of SRAM vendor.
ID register presence indicator (0) 1 Indicates the presence of an ID register.
Scan Register Sizes
Register Name Bit Size (× 36)
Instruction 3
Bypass 1
ID 32
Boundary scan order (165-ball FBGA package) 89
Identification Codes
Instruction Code Description
EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces
all SRAM outputs to high Z state.
IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces
all SRAM output drivers to a high Z state.
RESERVED 011 Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does
not affect SRAM operation.
RESERVED 101 Do Not Use: This instruction is reserved for future use.
RESERVED 110 Do Not Use: This instruction is reserved for future use.
BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Document Number: 001-66680 Rev. *L Page 19 of 31
CY7C1460KV33
CY7C1460KVE33
CY7C1462KVE33
Boundary Scan Order
165-ball FBGA [16]
CY7C1460KVE33 (1M × 36)
Bit# ball ID Bit# ball ID Bit# ball ID Bit# ball ID
1N6 26E11 51A3 76N1
2N7 27D11 52A2 77N2
3 10N 28 G10 53 B2 78 P1
4P11 29F10 54C2 79R1
5 P8 30 E10 55 B1 80 R2
6 R8 31 D10 56 A1 81 P3
7R9 32C11 57C1 82R3
8P9 33A11 58D1 83P2
9P10 34B11 59E1 84R4
10 R10 35 A10 60 F1 85 P4
11 R11 36 B10 61 G1 86 N5
12H11 37A9 62D2 87P6
13 N11 38 B9 63 E2 88 R6
14 M11 39 C10 64 F2 89 Internal
15 L11 40 A8 65 G2
16 K11 41 B8 66 H1
17 J11 42 A7 67 H3
18 M10 43 B7 68 J1
19 L10 44 B6 69 K1
20 K10 45 A6 70 L1
21 J10 46 B5 71 M1
22 H9 47 A5 72 J2
23 H10 48 A4 73 K2
24 G11 49 B4 74 L2
25 F11 50 B3 75 M2
Note
16. Bit# 89 is preset HIGH.
Document Number: 001-66680 Rev. *L Page 20 of 31
CY7C1460KV33
CY7C1460KVE33
CY7C1462KVE33
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ................................. -65 °C to +150 °C
Ambient temperature with
power applied ........................................... -55 °C to +125 °C
Supply voltage on VDD relative to GND ....... -0.5 V to +4.6 V
Supply voltage on VDDQ relative to GND ....... -0.5 V to +VDD
DC to outputs in tri-state ....................-0.5 V to VDDQ + 0.5 V
DC input voltage ..................................-0.5 V to VDD + 0.5 V
Current into outputs (LOW) ........................................ 20 mA
Static discharge voltage
(per MIL-STD-883, method 3015) ......................... > 2001 V
Latch-up current ................................................... > 200 mA
Operating Range
Range Ambient
Temperature VDD VDDQ
Commercial 0 °C to +70 °C 3.3 V – 5% /
+ 10%
2.5 V – 5% to
VDD
Industrial –40 °C to +85 °C
Neutron Soft Error Immunity
Parameter Description Test
Conditions Typ Max* Unit
LSBU
(Device
without
ECC)
Logical
Single-Bit
Upsets
25 °C <5 5 FIT/
Mb
LSBU
(Device with
ECC)
0 0.01 FIT/
Mb
LMBU (All
Devices)
Logical
Multi-Bit
Upsets
25 °C 0 0.01 FIT/
Mb
SEL (All
Devices)
Single Event
Latch up
85 °C 0 0.1 FIT/
Dev
* No LMBU or SEL events occurred during testing; this column represents a
statistical 2, 95% confidence limit calculation. For more details refer to
Application Note AN 54908 “Accelerated Neutron SER Testing and Calculation of
Terrestrial Failure Rates”
Electrical Characteristics
Over the Operating Range
Parameter [17, 18] Description Test Conditions Min Max Unit
VDD Power supply voltage 3.135 3.6 V
VDDQ I/O supply voltage for 3.3 V I/O 3.135 VDD V
for 2.5 V I/O 2.375 2.625 V
VOH Output HIGH voltage for 3.3 V I/O, IOH =4.0 mA 2.4 – V
for 2.5 V I/O, IOH = 1.0 mA 2.0 – V
VOL Output LOW voltage for 3.3 V I/O, IOL =8.0 mA – 0.4 V
for 2.5 V I/O, IOL =1.0 mA – 0.4 V
VIH Input HIGH voltage[17] for 3.3 V I/O 2.0 VDD + 0.3 V V
for 2.5 V I/O 1.7 VDD + 0.3 V V
VIL Input LOW voltage[17] for 3.3 V I/O –0.3 0.8 V
for 2.5 V I/O –0.3 0.7 V
Notes
17. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC)> –2 V (Pulse width less than tCYC/2).
18. Tpower up: Assumes a linear ramp from 0 V to VDD (Min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document Number: 001-66680 Rev. *L Page 21 of 31
CY7C1460KV33
CY7C1460KVE33
CY7C1462KVE33
IXInput leakage current except ZZ
and MODE
GND VI VDDQ -5 5 A
Input current of MODE Input = VSS –30 – A
Input = VDD –5A
Input current of ZZ Input = VSS –5 – A
Input = VDD –30A
IOZ Output leakage current GND VI VDDQ, output disabled -5 5 A
IDD VDD operating supply VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
4-ns cycle,
250 MHz
× 18 – 220 mA
× 36 – 240
5-ns cycle,
200 MHz
× 18 – 190 mA
× 36 – 210
6-ns cycle,
167 MHz
× 18 – 170 mA
× 36 – 190
ISB1 Automatic CE power-down
current – TTL inputs
Max VDD,
device deselected,
VIN VIH or VIN VIL,
f = fMAX = 1/tCYC
4-ns cycle,
250 MHz
× 18 – 85 mA
× 36 – 90
5-ns cycle,
200 MHz
× 18 – 85 mA
× 36 – 90
6-ns cycle,
167 MHz
× 18 – 85 mA
× 36 – 90
ISB2 Automatic CE power-down
current – CMOS inputs
Max VDD,
device deselected,
VIN 0.3 V or
VIN > VDDQ 0.3 V,
f = 0
All speed
grades
× 18 – 75 mA
× 36 80
ISB3 Automatic CE power-down
current – CMOS inputs
Max VDD, device
deselected,
VIN 0.3 V or
VIN > VDDQ 0.3 V,
f = fMAX = 1/tCYC
4-ns cycle,
250 MHz
× 18 – 85 mA
× 36 90
5-ns cycle,
200 MHz
× 18 – 85
× 36 90 mA
6-ns cycle,
167 MHz
× 18 – 85
× 36 90 mA
ISB4 Automatic CE power-down
current – TTL inputs
Max VDD, device
deselected,
VIN VIH or VIN VIL,
f = 0
All speed
grades
× 18 – 75 mA
× 36 – 80
Electrical Characteristics (continued)
Over the Operating Range
Parameter [17, 18] Description Test Conditions Min Max Unit
Document Number: 001-66680 Rev. *L Page 22 of 31
CY7C1460KV33
CY7C1460KVE33
CY7C1462KVE33
Capacitance
Parameter [19] Description Test Conditions 100-pin TQFP
Max
165-ball FBGA
Max Unit
CIN Input capacitance TA = 25 C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 2.5 V
55pF
CCLK Clock input capacitance 5 5 pF
CI/O Input/output capacitance 5 5 pF
Thermal Resistance
Parameter [19] Description Test Conditions 100-pin TQFP
Package
165-ball FBGA
Package Unit
JA Thermal resistance
(junction to ambient)
Test conditions
follow standard test
methods and
procedures for
measuring thermal
impedance, per
EIA/JESD51.
With Still Air (0 m/s) 35.36 14.24 °C/W
With Air Flow (1 m/s) 31.30 12.47 °C/W
With Air Flow (3 m/s) 28.86 11.40 °C/W
JC Thermal resistance
(junction to case)
–7.523.92°C/W
JB Thermal resistance
(junction to board)
28.89 7.19 °C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
OUTPUT
R = 317
R = 351
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT
RL= 50
Z0= 50
V
T
= 1.5 V
3.3 V ALL INPUT PULSES
VDDQ
GND
90%
10%
90%
10%
2 V/ns 1 ns
(c)
3.3 V I/O Test Load
OUTPUT
R = 1667
R =1538
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT
RL= 50
Z0= 50
VT= 1.25 V
2.5 V ALL INPUT PULSES
VDDQ
GND
90%
10%
90%
10%
2 V/ns 1 ns
(c)
2.5 V I/O Test Load
Note
19. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-66680 Rev. *L Page 23 of 31
CY7C1460KV33
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Switching Characteristics
Over the Operating Range
Parameter [20, 21] Description –250 –200 –167 Unit
Min Max Min Max Min Max
tPower[22] VCC (typical) to the first access read or write 1 – 1 – 1 – ms
Clock
tCYC Clock cycle time 4.0 –5.0 –6.0 –ns
FMAX Maximum operating frequency –250 –200 –167 MHz
tCH Clock HIGH 1.5 –2.0 –2.4 –ns
tCL Clock LOW 1.5 –2.0 –2.4 –ns
Output Times
tCO Data output valid after CLK rise –2.5 –3.2 –3.4 ns
tEOV OE LOW to output valid –2.6 –3.0 –3.4 ns
tDOH Data output hold after CLK rise 1.0 –1.5 –1.5 –ns
tCHZ Clock to high Z[23, 24, 25] –2.6 –3.0 –3.4 ns
tCLZ Clock to low Z[23, 24, 25] 1.0 –1.3 –1.5 –ns
tEOHZ OE HIGH to output high Z[23, 24, 25] –2.6 –3.0 –3.4 ns
tEOLZ OE LOW to output low Z[23, 24, 25] 0 – 0 – 0 – ns
Setup Times
tAS Address setup before CLK rise 1.2 –1.4 –1.5 –ns
tDS Data input setup before CLK rise 1.2 –1.4 –1.5 –ns
tCENS CEN setup before CLK rise 1.2 –1.4 –1.5 –ns
tWES WE, BWx setup before CLK rise 1.2 –1.4 –1.5 –ns
tALS ADV/LD setup before CLK rise 1.2 –1.4 –1.5 –ns
tCES Chip select setup 1.2 –1.4 –1.5 –ns
Hold Times
tAH Address hold after CLK rise 0.3 –0.4 –0.5 –ns
tDH Data input hold after CLK rise 0.3 –0.4 –0.5 –ns
tCENH CEN hold after CLK rise 0.3 –0.4 –0.5 –ns
tWEH WE, BWx hold after CLK rise 0.3 –0.4 –0.5 –ns
tALH ADV/LD hold after CLK rise 0.3 –0.4 –0.5 –ns
tCEH Chip select hold after CLK rise 0.3 –0.4 –0.5 –ns
Notes
20. Timing reference is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.
21. Test conditions shown in (a) of Figure 3 on page 22 unless otherwise noted.
22. This part has a voltage regulator internally; tpower is the time power needs to be supplied above VDD minimum initially, before a Read or Write operation can be initiated.
23. tCHZ, tCLZ, tEOLZ, and tEOHZ are specified with AC test conditions shown in (b) of Figure 3 on page 22. Transition is measured ± 200 mV from steady-state voltage.
24. At any voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus.
These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve high
Z prior to low Z under the same system conditions.
25. This parameter is sampled and not 100% tested.
Document Number: 001-66680 Rev. *L Page 24 of 31
CY7C1460KV33
CY7C1460KVE33
CY7C1462KVE33
Switching Waveforms
Figure 4. Read/Write/Timing [26, 27, 28]
WRITE
D(A1)
123 456789
CLK
tCYC
t
CL
t
CH
10
CE
t
CEH
t
CES
WE
CEN
t
CENH
t
CENS
BW
x
ADV/LD
t
AH
t
AS
ADDRESS A1 A2 A3 A4 A5 A6 A7
t
DH
t
DS
Data
I
n-Out (DQ)
t
CLZ
D(A1) D(A2) D(A5)Q(A4)Q(A3)
D(A2+1)
t
DOH
t
CHZ
t
CO
WRITE
D(A2)
BURST
WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
BURST
READ
Q(A4+1)
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
OE
t
OEV
t
OELZ
t
OEHZ
t
DOH
DON’T CARE UNDEFINED
Q(A6)
Q(A4+1)
Notes
26. For this waveform ZZ is tied low.
27. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH,CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
28. Order of the burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document Number: 001-66680 Rev. *L Page 25 of 31
CY7C1460KV33
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Figure 5. NOP, STALL and DESELECT Cycles [29, 30, 31]
Figure 6. ZZ Mode Timing [32, 33]
Switching Waveforms (continued)
READ
Q(A3)
456 78910
CLK
CE
WE
CEN
BWx
ADV/LD
ADDRESS A3 A4 A5
D(A4)
Data
In-Out (DQ)
A1
Q(A5)
WRITE
D(A4)
STALLWRITE
D(A1)
123
READ
Q(A2)
STALL NOP READ
Q(A5)
DESELECT CONTINUE
DESELECT
DON’T CARE UNDEFINED
tCHZ
A2
D(A1) Q(A2) Q(A3)
tZZ
I
SUPPLY
CLK
ZZ
tZZREC
A
LL INPUTS
(except ZZ)
DON’T CARE
IDDZZ
tZZI
tRZZI
Outputs (Q)
High-Z
DESELECT or READ Only
Notes
29. For this waveform ZZ is tied low.
30. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH,CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
31. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.
32. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
33. I/Os are in high Z when exiting ZZ sleep mode.
Document Number: 001-66680 Rev. *L Page 26 of 31
CY7C1460KV33
CY7C1460KVE33
CY7C1462KVE33
Ordering Information
Table 1 lists the ordering codes. The table contains only the parts that are currently available. If you do not see what you are looking
for, contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the
product summary page at http://www.cypress.com/products.
Ordering Code Definitions
Table 1. Ordering Information
Speed
(MHz) Ordering Code
Package
Diagram Part and Package Type Operating
Range
250 CY7C1460KV33-250AXI 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free Industrial
200 CY7C1460KV33-200AXC Commercial
CY7C1460KVE33-200AXC
167 CY7C1460KV33-167AXC
CY7C1460KV33-167AXI Industrial
CY7C1460KVE33-167AXI
CY7C1460KVE33-167BZC 51-85195 165-ball FBGA (15 × 17 × 1.4 mm) Commercial
CY7C1460KV33-167BZC
CY7C1462KVE33-167AXC 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Temperature range: X = C or I
C = Commercial = 0 °C to +70 °C; I = Industrial = –40 °C to +85 °C
X = Pb-free; X Absent = Leaded
Package Type: XX = A or BZ
A = 100-pin TQFP
BZ = 165-ball FBGA
Speed Grade: XXX = 167 MHz or 200 MHz or 250 MHz
33 = 3.3 V VDD
E = Device with ECC; E Absent = Device without ECC
Process Technology: KV 65 nm
Part Identifier: 14XX = 1460 or 1462
1460 = PL, 1M × 36 (36-Mbit)
1462 = PL, 2M × 18 (36-Mbit)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
C 14XX -XXX X
XX
33 X
CY 7KV E
Document Number: 001-66680 Rev. *L Page 27 of 31
CY7C1460KV33
CY7C1460KVE33
CY7C1462KVE33
Package Diagrams
Figure 7. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
ș
ș1
ș2
NOTE:
3. JEDEC SPECIFICATION NO. REF: MS-026.
2. BODY LENGTH DIMENSION DOES NOT
MOLD PROTRUSION/END FLASH SHALL
1. ALL DIMENSIONS ARE IN MILLIMETERS.
BODY SIZE INCLUDING MOLD MISMATCH.
L11.00 REF
L
c
0.45 0.60 0.75
0.20
NOM.MIN.
D1
R2
E1
E
0°
0.08
D
2
A
A
1
A
1.35 1.40
SYMBOL MAX.
7°
0.20
1.45
1.60
0.15
ș
b0.22 0.30 0.38
e0.65 TYP
DIMENSIONS
1
R0.08
L20.25 BSC
0.05
0.20
INCLUDE MOLD PROTRUSION/END FLASH.
15.80 16.00 16.20
13.90 14.00 14.10 NOT EXCEED 0.0098 in (0.25 mm) PER SIDE.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC
21.80 22.00 22.20
19.90 20.00 20.10
L30.20
0°ș1
11° 13°ș212°
51-85050 *G
Document Number: 001-66680 Rev. *L Page 28 of 31
CY7C1460KV33
CY7C1460KVE33
CY7C1462KVE33
Figure 8. 165-ball FBGA (15 × 17 × 1.4 mm (0.5 Ball Diameter)) Package Outline, 51-85195
Package Diagrams (continued)
51-85195 *D
Document Number: 001-66680 Rev. *L Page 29 of 31
CY7C1460KV33
CY7C1460KVE33
CY7C1462KVE33
Acronyms Document Conventions
Units of Measure
Table 2. Acronyms Used in this Document
Acronym Description
CEN Clock Enable
CMOS Complementary Metal Oxide Semiconductor
FBGA Fine-Pitch Ball Grid Array
I/O Input/Output
JTAG Joint Test Action Group
NoBL No Bus Latency
OE Output Enable
SRAM Static Random Access Memory
TCK Test Clock
TDI Test Data-In
TDO Test Data-Out
TMS Test Mode Select
TQFP Thin Quad Flat Pack
WE Write Enable
Table 3. Units of Measure
Symbol Unit of Measure
°C degree Celsius
MHz megahertz
µA microampere
mA milliampere
mm millimeter
ms millisecond
ns nanosecond
% percent
pF picofarad
Vvolt
Wwatt
Document Number: 001-66680 Rev. *L Page 30 of 31
CY7C1460KV33
CY7C1460KVE33
CY7C1462KVE33
Document History Page
Document Title: CY7C1460KV33/CY7C1460KVE33/CY7C1462KVE33, 36-Mbit (1M × 36/2M × 18) Pipelined SRAM with
NoBL™ Architecture (With ECC)
Document Number: 001-66680
Revision ECN Orig. of
Change
Submission
Date Description of Change
*F 4682541 PRIT 03/16/2015 Changed status from Preliminary to Final.
*G 4680529 PRIT 04/10/2015 Updated Electrical Characteristics:
Updated details in “Max” column corresponding to ISB2 and ISB3 parameters.
Updated Package Diagrams:
spec 51-85195 – Changed revision from *C to *D.
Post to external web.
*H 4747474 DEVM 04/29/2015 Updated Functional Overview:
Updated ZZ Mode Electrical Characteristics:
Changed maximum value of IDDZZ parameter from 89 mA to 75 mA.
*I 5028596 PRIT 11/26/2015 Added Errata.
*J 5210861 DEVM 04/07/2016 Removed Errata.
Updated to new template.
Completing Sunset Review.
*K 5337537 PRIT 07/05/2016 Updated Neutron Soft Error Immunity:
Updated values in “Typ” and “Max” columns corresponding to LSBU (Device
without ECC) parameter.
*L 6063618 CNX 02/08/2018 Updated Package Diagrams:
spec 51-85050 – Changed revision from *E to *G.
Updated to new template.
Document Number: 001-66680 Rev. *L Revised February 8, 2018 Page 31 of 31
QDR® is the registered trademark and NoBL™ and No Bus Latency™ are trademarks of Cypress Semiconductor Corporation.
CY7C1460KV33
CY7C1460KVE33
CY7C1462KVE33
© Cypress Semiconductor Corporation, 2011-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
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