ATXMEGA32D4-AU - MICROCHIP TECHNOLOGY

8315N–AVR–04/2013

Features

zHigh-performance, low-power Atmel® AVR® XMEGA® 8/16-bit Microcontroller

zNonvolatile program and data memories

z16K - 128KBytes of in-system self-programmable flash

z4K - 8KBytes boot section

z1K - 2KBytes EEPROM

z2K - 8KBytes internal SRAM

zPeripheral Features

zFour-channel event system

zFour 16-bit timer/counters

zTwo timer/counters with 4 output compare or input capture channels

zTwo timer/counters with 2 output compare or input capture channels

zHigh-resolution extensions on all timer/counters

zAdvanced waveform extension (AWeX) on one timer/counter

zTwo USARTs with IrDA support for one USART

zTwo Two wire interfaces with dual address match (I2C and SMBus compatible)

zTwo serial peripheral interfaces (SPIs)

zCRC-16 (CRC-CCITT) and CRC-32 (IEEE 802.3) generator

z16-bit real time counter (RTC) with separate oscillator

zOne twelve-channel, 12-bit, 200ksps Analog to Digital Converter

zTwo Analog Comparators with window compare function, and current sources

zExternal interrupts on all general purpose I/O pins

zProgrammable watchdog timer with separate on-chip ultra low power oscillator

zQTouch® library support

zCapacitive touch buttons, sliders and wheels

zSpecial microcontroller features

zPower-on reset and programmable brown-out detection

zInternal and external clock options with PLL and prescaler

zProgrammable multilevel interrupt controller

zFive sleep modes

zProgramming and debug interfaces

zPDI (program and debug interface)

zI/O and packages

z34 Programmable I/O pins

z44 - lead TQFP

z44 - pad VQFN/QFN

z49 - ball VFBGA

zOperating voltage

z1.6 – 3.6V

zOperating frequency

z0 – 12MHz from 1.6V

z0 – 32MHz from 2.7V

8/16-bit Atmel XMEGA D4 Microcontroller

ATxmega128D4 / ATxmega64D4 /

ATxmega32D4 / ATxmega16D4

XMEGA D4 [DATASHEET]

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1. Ordering information

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information.

2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.

3. For packaging information see ”Packaging information” on page 64.

4. Tape and Reel

Typical Applications

Ordering Code

Flash

(Bytes)

EEPROM

(Bytes)

SRAM

(Bytes)

Speed

(MHz)

Power

Supply Package(1)(2)(3) Temp

ATxmega128D4-AU 128K + 8K 2K 8K

32 1.6 - 3.6V

44A

-40°C - 85°C

ATxmega128D4-AUR(4) 128K + 8K 2K 8K

ATxmega64D4-AU 64K + 4K 2K 4K

ATxmega64D4-AUR(4) 64K + 4K 2K 4K

ATxmega32D4-AU 32K + 4K 1K 4K

ATxmega32D4-AUR(4) 32K + 4K 1K 4K

ATxmega16D4-AU 16K + 4K 1K 2K

ATxmega16D4-AUR(4) 16K + 4K 1K 2K

ATxmega128D4-MH 128K + 8K 2K 8K

44M1

ATxmega128D4-MHR(4) 128K + 8K 2K 8K

ATxmega64D4-MH 64K + 4K 2K 4K

ATxmega64D4-MHR(4) 64K + 4K 2K 4K

ATxmega32D4-MH 32K + 4K 1K 4K

ATxmega32D4-MHR(4) 32K + 4K 1K 4K

ATxmega16D4-MH 16K + 4K 1K 2K

ATxmega16D4-MHR(4) 16K + 4K 1K 2K

ATxmega128D4-CU 128K + 8K 2K 8K

49C2

ATxmega128D4-CUR(4) 128K + 8K 2K 8K

ATxmega64D4-CU 64K + 4K 2K 4K

ATxmega64D4-CUR(4) 64K + 4K 2K 4K

ATxmega32D4-CU 32K + 4K 1K 4K

ATxmega32D4-CUR(4) 32K + 4K 1K 4K

ATxmega16D4-CU 16K + 4K 1K 2K

ATxmega16D4-CUR(4) 16K + 4K 1K 2K

Package type

44A 44-lead, 10x10mm body size, 1.0mm body thickness, 0.8mm lead pitch, thin profile plastic quad flat package (TQFP)

44M1 44-Pad, 7x7x1mm body, lead pitch 0.50mm, 5.20mm exposed pad, thermally enhanced plastic very thin quad no lead package (VQFN)

49C2 49-ball (7 x 7 Array), 0.65mm pitch, 5.0x5.0x1.0mm, very thin, fine-pitch ball grid array package (VFBGA)

Industrial control Climate control Low power battery applications

Factory automation RF and ZigBee®Power tools

Building control USB connectivity HVAC

Board control Sensor control Utility metering

White goods Optical Medical applications

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2. Pinout/Block diagram

Figure 2-1. Block diagram and QFN/TQFP pinout

Note: 1. For full details on pinout and pin functions refer to “Pinout and Pin Functions” on page 48.

PA0

PA1

PA2

PA3

PA4

PB0

PB1

PB3

PB2

PA7

PA6

PA5

GND

VCC

PC0

VCC

GND

PC1

PC2

PC3

PC4

PC5

PC6

PC7

PD0

PD1

PD2

PD3

PD4

PD5

PD6

VCC

GND

PD7

PE0

PE1

PE2

PE3

RESET/PDI

PDI

PR0

PR1

AVCC

GND

Power

Supervision

Port A

EVENT ROUTING NETWORK

BUS

matrix

SRAM

FLASH

ADC

AC0:1

OCD

Port EPort D

Prog/Debug

Interface

EEPROM

Port C

TC0:1

Event System

Controller

Watchdog

Timer

Watchdog

OSC/CLK

Control

Real Time

Counter

Interrupt

Controller

DATA BUS

Port R

USART0

TWI

SPI

TC0

USART0

SPI

TC0

TWI

Port B

AREF

Sleep

Controller

Reset

Controller

IRCOM

CRC

CPU

Internal

references

Internal

oscillators

XOSC TOSC

Digital function

Analog function / Oscillators

Programming, debug, test

External clock / Crystal pins

General Purpose I /O

Ground

Power

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Figure 2-2. VFBGA pinout

1 2 3 4 5 6 7

APA3 AVCC GND PR1 PR0 PDI PE3

BPA4 PA1 PA0 GND RESET/PDI_CLK PE2 VCC

CPA5 PA2 PA6 PA7 GND PE1 GND

DPB1 PB2 PB3 PB0 GND PD7 PE0

EGND GND PC3 GND PD4 PD5 PD6

FVCC PC0 PC4 PC6 PD0 PD1 PD3

GPC1 PC2 PC5 PC7 GND VCC PD2

1234567

7654321

Top view Bottom view

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3. Overview

The Atmel AVR XMEGA is a family of low power, high performance, and peripheral rich 8/16-bit microcontrollers based

on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the AVR XMEGA device

achieves throughputs CPU approaching one million instructions per second (MIPS) per megahertz, allowing the system

designer to optimize power consumption versus processing speed.

The AVR CPU combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly

connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in a single instruction,

executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs many times

faster than conventional single-accumulator or CISC based microcontrollers.

The AVR XMEGA D4 devices provide the following features: in-system programmable flash with read-while-write

capabilities; internal EEPROM and SRAM; four-channel event system and programmable multilevel interrupt controller,

34 general purpose I/O lines, 16-bit real-time counter (RTC); four flexible, 16-bit timer/counters with compare and PWM

channels; two USARTs; two two-wire serial interfaces (TWIs); two serial peripheral interfaces (SPIs); one twelve-

channel, 12-bit ADC with optional differential input with programmable gain; two analog comparators (ACs) with window

mode; programmable watchdog timer with separate internal oscillator; accurate internal oscillators with PLL and

prescaler; and programmable brown-out detection.

The program and debug interface (PDI), a fast, two-pin interface for programming and debugging, is available.

The XMEGA D4 devices have five software selectable power saving modes. The idle mode stops the CPU while allowing

the SRAM, event system, interrupt controller, and all peripherals to continue functioning. The power-down mode saves

the SRAM and register contents, but stops the oscillators, disabling all other functions until the next TWI, or pin-change

interrupt, or reset. In power-save mode, the asynchronous real-time counter continues to run, allowing the application to

maintain a timer base while the rest of the device is sleeping. In standby mode, the external crystal oscillator keeps

running while the rest of the device is sleeping. This allows very fast startup from the external crystal, combined with low

power consumption. In extended standby mode, both the main oscillator and the asynchronous timer continue to run. To

further reduce power consumption, the peripheral clock to each individual peripheral can optionally be stopped in active

mode and idle sleep mode.

Atmel offers a free QTouch library for embedding capacitive touch buttons, sliders and wheels functionality into AVR

microcontrollers.

The devices are manufactured using Atmel high-density, nonvolatile memory technology. The program flash memory can

be reprogrammed in-system through the PDI interface. A boot loader running in the device can use any interface to

download the application program to the flash memory. The boot loader software in the boot flash section will continue to

run while the application flash section is updated, providing true read-while-write operation. By combining an 8/16-bit

RISC CPU with in-system, self-programmable flash, the AVR XMEGA is a powerful microcontroller family that provides a

highly flexible and cost effective solution for many embedded applications.

All Atmel AVR XMEGA devices are supported with a full suite of program and system development tools, including C

compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits.

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3.1 Block Diagram

Figure 3-1. XMEGA D4 Block Diagram

Power

Supervision

POR/BOD &

RESET

PORT A (8)

PORT B (4)

SRAMADCA

ACA

OCD

Int. Refs.

PDI

PA[0..7]

PB[0..3]

Watchdog

Timer

Watchdog

Oscillator

Interrupt

Controller

DATA BUS

Prog/Debug

Controller

VCC

GND

Oscillator

Circuits/

Clock

Generation

Oscillator

Control

Real Time

Counter

Event System

Controller

AREFA

AREFB

PDI_DATA

RESET/

PDI_CLK

Sleep

Controller

CRC

PORT C (8)

PC[0..7]

TCC0:1

USARTC0

TWIC

SPIC

PD[0..7] PE[0..3]

PORT D (8)

TCD0

USARTD0

SPID

TCE0

TWIE

PORT E (4)

Tempref

VCC/10

PORT R (2)

XTAL/

TOSC1

XTAL2/

TOSC2

PR[0..1]

DATA BUS

NVM Controller

salF

IRCOM

BUS Matrix

CPU

TOSC1

TOSC2

To Clock

Generator

EVENT ROUTING NETWORK

Digital function

Analog function

Programming, debug, test

Oscillator/Crystal/Clock

General Purpose I/O

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4. Resources

A comprehensive set of development tools, application notes and datasheets are available for download on

http://www.atmel.com/avr.

4.1 Recommended reading

zAtmel AVR XMEGA D manual

zXMEGA application notes

This device data sheet only contains part specific information with a short description of each peripheral and module. The

XMEGA D manual describes the modules and peripherals in depth. The XMEGA application notes contain example code

and show applied use of the modules and peripherals.

All documentations are available from www.atmel.com/avr.

5. Capacitive touch sensing

The Atmel QTouch library provides a simple to use solution to realize touch sensitive interfaces on most Atmel AVR

microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully debounced

reporting of touch keys and includes Adjacent Key Suppression® (AKS®) technology for unambiguous detection of key

events. The QTouch library includes support for the QTouch and QMatrix acquisition methods.

Touch sensing can be added to any application by linking the appropriate Atmel QTouch library for the AVR

microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the

touch sensing API’s to retrieve the channel information and determine the touch sensor states.

The QTouch library is FREE and downloadable from the Atmel website at the following location:

http://www.atmel.com/tools/QTOUCHLIBRARY.aspx. For implementation details and other information, refer to the

QTouch library user guide - also available for download from the Atmel website.

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6. AVR CPU

6.1 Features

z8/16-bit, high-performance Atmel AVR RISC CPU

z137 instructions

zHardware multiplier

z32x8-bit registers directly connected to the ALU

zStack in RAM

zStack pointer accessible in I/O memory space

zDirect addressing of up to 16MB of program memory and 16MB of data memory

zTrue 16/24-bit access to 16/24-bit I/O registers

zEfficient support for 8-, 16-, and 32-bit arithmetic

zConfiguration change protection of system-critical features

6.2 Overview

All Atmel AVR XMEGA devices use the 8/16-bit AVR CPU. The main function of the CPU is to execute the code and

perform all calculations. The CPU is able to access memories, perform calculations, control peripherals, and execute the

program in the flash memory. Interrupt handling is described in a separate section, refer to “Interrupts and Programmable

Multilevel Interrupt Controller” on page 26.

6.3 Architectural Overview

In order to maximize performance and parallelism, the AVR CPU uses a Harvard architecture with separate memories

and buses for program and data. Instructions in the program memory are executed with single-level pipelining. While one

instruction is being executed, the next instruction is pre-fetched from the program memory. This enables instructions to

be executed on every clock cycle. For details of all AVR instructions, refer to http://www.atmel.com/avr.

Figure 6-1. Block diagram of the AVR CPU architecture.

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The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a

register. Single-register operations can also be executed in the ALU. After an arithmetic operation, the status register is

updated to reflect information about the result of the operation.

The ALU is directly connected to the fast-access register file. The 32 x 8-bit general purpose working registers all have

single clock cycle access time allowing single-cycle arithmetic logic unit (ALU) operation between registers or between a

space addressing, enabling efficient address calculations.

The memory spaces are linear. The data memory space and the program memory space are two different memory

spaces.

The data memory space is divided into I/O registers, SRAM, and external RAM. In addition, the EEPROM can be

memory mapped in the data memory.

All I/O status and control registers reside in the lowest 4KB addresses of the data memory. This is referred to as the I/O

memory space. The lowest 64 addresses can be accessed directly, or as the data space locations from 0x00 to 0x3F.

The rest is the extended I/O memory space, ranging from 0x0040 to 0x0FFF. I/O registers here must be accessed as

data space locations using load (LD/LDS/LDD) and store (ST/STS/STD) instructions.

The SRAM holds data. Code execution from SRAM is not supported. It can easily be accessed through the five different

addressing modes supported in the AVR architecture. The first SRAM address is 0x2000.

Data addresses 0x1000 to 0x1FFF are reserved for memory mapping of EEPROM.

The program memory is divided in two sections, the application program section and the boot program section. Both

sections have dedicated lock bits for write and read/write protection. The SPM instruction that is used for self-

programming of the application flash memory must reside in the boot program section. The application section contains

an application table section with separate lock bits for write and read/write protection. The application table section can

be used for safe storing of nonvolatile data in the program memory.

6.4 ALU - Arithmetic Logic Unit

The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a

purpose registers. In a single clock cycle, arithmetic operations between general purpose registers or between a register

and an immediate are executed and the result is stored in the register file. After an arithmetic or logic operation, the

status register is updated to reflect information about the result of the operation.

ALU operations are divided into three main categories – arithmetic, logical, and bit functions. Both 8- and 16-bit

arithmetic is supported, and the instruction set allows for efficient implementation of 32-bit aritmetic. The hardware

multiplier supports signed and unsigned multiplication and fractional format.

6.4.1 Hardware Multiplier

The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware multiplier supports different

variations of signed and unsigned integer and fractional numbers:

zMultiplication of unsigned integers

zMultiplication of signed integers

zMultiplication of a signed integer with an unsigned integer

zMultiplication of unsigned fractional numbers

zMultiplication of signed fractional numbers

zMultiplication of a signed fractional number with an unsigned one

A multiplication takes two CPU clock cycles.

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6.5 Program Flow

After reset, the CPU starts to execute instructions from the lowest address in the flash programmemory ‘0.’ The program

counter (PC) addresses the next instruction to be fetched.

Program flow is provided by conditional and unconditional jump and call instructions capable of addressing the whole

address space directly. Most AVR instructions use a 16-bit word format, while a limited number use a 32-bit format.

During interrupts and subroutine calls, the return address PC is stored on the stack. The stack is allocated in the general

data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. After

reset, the stack pointer (SP) points to the highest address in the internal SRAM. The SP is read/write accessible in the

I/O memory space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can easily be

accessed through the five different addressing modes supported in the AVR CPU.

6.6 Status Register

The status register (SREG) contains information about the result of the most recently executed arithmetic or logic

instruction. This information can be used for altering program flow in order to perform conditional operations. Note that

the status register is updated after all ALU operations, as specified in the instruction set reference. This will in many

cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.

The status register is not automatically stored when entering an interrupt routine nor restored when returning from an

interrupt. This must be handled by software.

The status register is accessible in the I/O memory space.

6.7 Stack and Stack Pointer

The stack is used for storing return addresses after interrupts and subroutine calls. It can also be used for storing

temporary data. The stack pointer (SP) register always points to the top of the stack. It is implemented as two 8-bit

registers that are accessible in the I/O memory space. Data are pushed and popped from the stack using the PUSH and

POP instructions. The stack grows from a higher memory location to a lower memory location. This implies that pushing

data onto the stack decreases the SP, and popping data off the stack increases the SP. The SP is automatically loaded

after reset, and the initial value is the highest address of the internal SRAM. If the SP is changed, it must be set to point

above address 0x2000, and it must be defined before any subroutine calls are executed or before interrupts are enabled.

During interrupts or subroutine calls, the return address is automatically pushed on the stack. The return address can be

two or three bytes, depending on program memory size of the device. For devices with 128KB or less of program

memory, the return address is two bytes, and hence the stack pointer is decremented/incremented by two. For devices

with more than 128KB of program memory, the return address is three bytes, and hence the SP is

decremented/incremented by three. The return address is popped off the stack when returning from interrupts using the

RETI instruction, and from subroutine calls using the RET instruction.

The SP is decremented by one when data are pushed on the stack with the PUSH instruction, and incremented by one

when data is popped off the stack using the POP instruction.

To prevent corruption when updating the stack pointer from software, a write to SPL will automatically disable interrupts

for up to four instructions or until the next I/O memory write.

After reset the stack pointer is initialized to the highest address of the SRAM. See Figure 7-2 on page 14.

6.8 Register File

The register file consists of 32 x 8-bit general purpose working registers with single clock cycle access time. The register

file supports the following input/output schemes:

zOne 8-bit output operand and one 8-bit result input

zTwo 8-bit output operands and one 8-bit result input

zTwo 8-bit output operands and one 16-bit result input

zOne 16-bit output operand and one 16-bit result input

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Six of the 32 registers can be used as three 16-bit address register pointers for data space addressing, enabling efficient

address calculations. One of these address pointers can also be used as an address pointer for lookup tables in flash

program memory.

7. Memories

7.1 Features

zFlash program memory

zOne linear address space

zIn-system programmable

zSelf-programming and boot loader support

zApplication section for application code

zApplication table section for application code or data storage

zBoot section for application code or boot loader code

zSeparate read/write protection lock bits for all sections

zBuilt in fast CRC check of a selectable flash program memory section

zData memory

zOne linear address space

zSingle-cycle access from CPU

zSRAM

zEEPROM

zByte and page accessible

zOptional memory mapping for direct load and store

zI/O memory

zConfiguration and status registers for all peripherals and modules

z16 bit-accessible general purpose registers for global variables or flags

zProduction signature row memory for factory programmed data

zID for each microcontroller device type

zSerial number for each device

zCalibration bytes for factory calibrated peripherals

zUser signature row

zOne flash page in size

zCan be read and written from software

zContent is kept after chip erase

7.2 Overview

The Atmel AVR architecture has two main memory spaces, the program memory and the data memory. Executable code

can reside only in the program memory, while data can be stored in the program memory and the data memory. The data

memory includes the internal SRAM, and EEPROM for nonvolatile data storage. All memory spaces are linear and

require no memory bank switching. Nonvolatile memory (NVM) spaces can be locked for further write and read/write

operations. This prevents unrestricted access to the application software.

A separate memory section contains the fuse bytes. These are used for configuring important system functions, and can

only be written by an external programmer.

The available memory size configurations are shown in “Ordering information” on page 2. In addition, each device has a

Flash memory signature row for calibration data, device identification, serial number etc.

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7.3 Flash Program Memory

The Atmel AVR XMEGA devices contain on-chip, in-system reprogrammable flash memory for program storage. The

flash memory can be accessed for read and write from an external programmer through the PDI or from application

software running in the device.

All AVR CPU instructions are 16 or 32 bits wide, and each flash location is 16 bits wide. The flash memory is organized

in two main sections, the application section and the boot loader section. The sizes of the different sections are fixed, but

device-dependent. These two sections have separate lock bits, and can have different levels of protection. The store

program memory (SPM) instruction, which is used to write to the flash from the application software, will only operate

when executed from the boot loader section.

The application section contains an application table section with separate lock settings. This enables safe storage of

nonvolatile data in the program memory.

Figure 7-1. Flash program memory (Hexadecimal address).

7.3.1 Application Section

The Application section is the section of the flash that is used for storing the executable application code. The protection

level for the application section can be selected by the boot lock bits for this section. The application section can not store

any boot loader code since the SPM instruction cannot be executed from the application section.

7.3.2 Application Table Section

The application table section is a part of the application section of the flash memory that can be used for storing data.

The size is identical to the boot loader section. The protection level for the application table section can be selected by

the boot lock bits for this section. The possibilities for different protection levels on the application section and the

application table section enable safe parameter storage in the program memory. If this section is not used for data,

application code can reside here.

7.3.3 Boot Loader Section

While the application section is used for storing the application code, the boot loader software must be located in the boot

loader section because the SPM instruction can only initiate programming when executing from this section. The SPM

instruction can access the entire flash, including the boot loader section itself. The protection level for the boot loader

section can be selected by the boot loader lock bits. If this section is not used for boot loader software, application code

can be stored here.

Word address

ATxmega128D4 ATxmega64D4 ATxmega32D4 ATxmega16D4

0 0 0 0 Application section

(128K/64K/32K/16K)

...

EFFF /77FF /37FF /17FF

F000 /7800 /3800 /1800 Application table section

(4K/4K/4K/4K)

FFFF /7FFF /3FFF /1FFF

10000 /8000 /4000 /2000 Boot section

(8K/4K/4K/4K)

10FFF /87FF /47FF /27FF

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7.3.4 Production Signature Row

The production signature row is a separate memory section for factory programmed data. It contains calibration data for

functions such as oscillators and analog modules. Some of the calibration values will be automatically loaded to the

corresponding module or peripheral unit during reset. Other values must be loaded from the signature row and written to

the corresponding peripheral registers from software. For details on calibration conditions, refer to “Electrical

Characteristics” on page 63.

The production signature row also contains an ID that identifies each microcontroller device type and a serial number for

each manufactured device. The serial number consists of the production lot number, wafer number, and wafer

coordinates for the device. The device ID for the available devices is shown in Table 7-1 on page 13.

The production signature row cannot be written or erased, but it can be read from application software and external

programmers.

Table 7-1. Device ID bytes for Atmel AVR XMEGA D4 devices.

7.3.5 User Signature Row

The user signature row is a separate memory section that is fully accessible (read and write) from application software

and external programmers. It is one flash page in size, and is meant for static user parameter storage, such as calibration

data, custom serial number, identification numbers, random number seeds, etc. This section is not erased by chip erase

commands that erase the flash, and requires a dedicated erase command. This ensures parameter storage during

multiple program/erase operations and on-chip debug sessions.

7.4 Fuses and Lock bits

The fuses are used to configure important system functions, and can only be written from an external programmer. The

application software can read the fuses. The fuses are used to configure reset sources such as brownout detector and

watchdog, startup configuration, JTAG enable, and JTAG user ID.

The lock bits are used to set protection levels for the different flash sections (that is, if read and/or write access should be

blocked). Lock bits can be written by external programmers and application software, but only to stricter protection levels.

Chip erase is the only way to erase the lock bits. To ensure that flash contents are protected even during chip erase, the

lock bits are erased after the rest of the flash memory has been erased.

An unprogrammed fuse or lock bit will have the value one, while a programmed fuse or lock bit will have the value zero.

Both fuses and lock bits are reprogrammable like the flash program memory.

7.5 Data Memory

The data memory contains the I/O memory, internal SRAM, optionally memory mapped EEPROM, and external memory

if available. The data memory is organized as one continuous memory section, see Figure 7-2 on page 14. To simplify

development, I/O Memory, EEPROM and SRAM will always have the same start addresses for all Atmel AVR XMEGA

devices.

Device Device ID bytes

Byte 2 Byte 1 Byte 0

ATxmega16D4 42 94 1E

ATxmega32D4 42 95 1E

ATxmega64D4 47 96 1E

ATxmega128D4 47 97 1E

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Figure 7-2. Data memory map (hexadecimal address).

7.6 EEPROM

XMEGA D devices have EEPROM for nonvolatile data storage. It is either addressable in a separate data space (default)

or memory mapped and accessed in normal data space. The EEPROM supports both byte and page access. Memory

mapped EEPROM allows highly efficient EEPROM reading and EEPROM buffer loading. When doing this, EEPROM is

accessible using load and store instructions. Memory mapped EEPROM will always start at hexadecimal address

0x1000.

7.7 I/O Memory

The status and configuration registers for peripherals and modules, including the CPU, are addressable through I/O

memory locations. All I/O locations can be accessed by the load (LD/LDS/LDD) and store (ST/STS/STD) instructions,

which are used to transfer data between the 32 registers in the register file and the I/O memory. The IN and OUT

instructions can address I/O memory locations in the range of 0x00 to 0x3F directly. In the address range 0x00 - 0x1F,

single-cycle instructions for manipulation and checking of individual bits are available.

The I/O memory address for all peripherals and modules in XMEGA D4 is shown in the “Peripheral Module Address Map”

on page 53.

7.7.1 General Purpose I/O Registers

The lowest 16 I/O memory addresses are reserved as general purpose I/O registers. These registers can be used for

storing global variables and flags, as they are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.

Byte address ATxmega64D4 Byte address ATxmega32D4 Byte address ATxmega16D4

I/O Registers (4K)

FFF FFF FFF

1000

EEPROM (2K)

1000

EEPROM (1K)

1000

EEPROM (1K)

17FF 13FF 13FF

RESERVED RESERVED RESERVED

2000

Internal SRAM (4K)

2000

Internal SRAM (4K)

2000

Internal SRAM (2K)

2FFF 2FFF 27FF

Byte address ATxmega128D4

I/O Registers (4K)

FFF

1000

EEPROM (2K)

17FF

RESERVED

2000

Internal SRAM (8K)

3FFF

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7.8 Data Memory and Bus Arbitration

Since the data memory is organized as four separate sets of memories, the bus masters (CPU, etc.) can access different

memory sections at the same time.

7.9 Memory Timing

Read and write access to the I/O memory takes one CPU clock cycle. A write to SRAM takes one cycle, and a read from

SRAM takes two cycles. EEPROM page load (write) takes one cycle, and three cycles are required for read. For burst

read, new data are available every second cycle. Refer to the instruction summary for more details on instructions and

instruction timing.

7.10 Device ID and Revision

Each device has a three-byte device ID. This ID identifies Atmel as the manufacturer of the device and the device type. A

separate register contains the revision number of the device.

7.11 I/O Memory Protection

Some features in the device are regarded as critical for safety in some applications. Due to this, it is possible to lock the

I/O register related to the clock system, the event system, and the advanced waveform extensions. As long as the lock is

enabled, all related I/O registers are locked and they can not be written from the application software. The lock registers

themselves are protected by the configuration change protection mechanism.

7.12 Flash and EEPROM Page Size

The flash program memory and EEPROM data memory are organized in pages. The pages are word accessible for the

flash and byte accessible for the EEPROM.

Table 7-2 on page 15 shows the Flash Program Memory organization and Program Counter (PC) size. Flash write and

erase operations are performed on one page at a time, while reading the Flash is done one byte at a time. For Flash

access the Z-pointer (Z[m:n]) is used for addressing. The most significant bits in the address (FPAGE) give the page

number and the least significant address bits (FWORD) give the word in the page.

Table 7-2. Number of words and Pages in the Flash.

Table 7-3 on page 16 shows EEPROM memory organization for the Atmel AVR XMEGA D4 devices. EEEPROM write

and erase operations can be performed one page or one byte at a time, while reading the EEPROM is done one byte at

a time. For EEPROM access the NVM address register (ADDR[m:n]) is used for addressing. The most significant bits in

the address (E2PAGE) give the page number and the least significant address bits (E2BYTE) give the byte in the page.

Devices PC size Flash size Page Size FWORD FPAGE Application Boot

bits bytes words Size No of pages Size No of pages

ATxmega16D4 14 16K + 4K 128 Z[7:1] Z[13:8] 16K 64 4K 16

ATxmega32D4 15 32K + 4K 128 Z[7:1] Z[14:8] 32K 128 4K 16

ATxmega64D4 16 64K + 4K 128 Z[7:1] Z[15:8] 64K 256 4K 16

ATxmega128D4 17 128K + 8K 128 Z[9:1] Z[16:8] 128K 512 8K 32

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Table 7-3. Number of Bytes and Pages in the EEPROM.

Devices EEPROM Page Size E2BYTE E2PAGE No of Pages

Size bytes

ATxmega16D4 1K 32 ADDR[4:0] ADDR[10:5] 32

ATxmega32D4 1K 32 ADDR[4:0] ADDR[10:5] 32

ATxmega64D4 2K 32 ADDR[4:0] ADDR[10:5] 64

ATxmega128D4 2K 32 ADDR[4:0] ADDR[10:5] 64

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8. Event System

8.1 Features

zSystem for direct peripheral-to-peripheral communication and signaling

zPeripherals can directly send, receive, and react to peripheral events

zCPU independent operation

z100% predictable signal timing

zShort and guaranteed response time

zFour event channels for up to four different and parallel signal routing configurations

zEvents can be sent and/or used by most peripherals, clock system, and software

zAdditional functions include

zQuadrature decoders

zDigital filtering of I/O pin state

zWorks in active mode and idle sleep mode

8.2 Overview

The event system enables direct peripheral-to-peripheral communication and signaling. It allows a change in one

peripheral’s state to automatically trigger actions in other peripherals. It is designed to provide a predictable system for

short and predictable response times between peripherals. It allows for autonomous peripheral control and interaction

without the use of interrupts, CPU, and is thus a powerful tool for reducing the complexity, size and execution time of

application code. It also allows for synchronized timing of actions in several peripheral modules.

A change in a peripheral’s state is referred to as an event, and usually corresponds to the peripheral’s interrupt

conditions. Events can be directly passed to other peripherals using a dedicated routing network called the event routing

network. How events are routed and used by the peripherals is configured in software.

Figure 8-1 shows a basic diagram of all connected peripherals. The event system can directly connect together analog to

digital converter, analog comparators, I/O port pins, the real-time counter, timer/counters, and IR communication module

(IRCOM). Events can also be generated from software and the peripheral clock.

Figure 8-1. Event system overview and connected peripherals.

The event routing network consists of four software-configurable multiplexers that control how events are routed and

used. These are called event channels, and allow for up to four parallel event routing configurations. The maximum

routing latency is two peripheral clock cycles. The event system works in both active mode and idle sleep mode.

Timer /

Counters

ADC

Real Time

Counter

Port pins

CPU /

Software

IRCOM

Event Routing Network

Event

System

Controller

clk

PER

Prescaler

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9. System Clock and Clock options

9.1 Features

zFast start-up time

zSafe run-time clock switching

zInternal oscillators:

z32MHz run-time calibrated and tuneable oscillator

z2MHz run-time calibrated oscillator

z32.768kHz calibrated oscillator

z32kHz ultra low power (ULP) oscillator with 1kHz output

zExternal clock options

z0.4MHz - 16MHz crystal oscillator

z32.768kHz crystal oscillator

zExternal clock

zPLL with 20MHz - 128MHz output frequency

zInternal and external clock options and 1x to 31x multiplication

zLock detector

zClock prescalers with 1x to 2048x division

zFast peripheral clocks running at two and four times the CPU clock

zAutomatic run-time calibration of internal oscillators

zExternal oscillator and PLL lock failure detection with optional non-maskable interrupt

9.2 Overview

Atmel AVR XMEGA D4 devices have a flexible clock system supporting a large number of clock sources. It incorporates

both accurate internal oscillators and external crystal oscillator and resonator support. A high-frequency phase locked

loop (PLL) and clock prescalers can be used to generate a wide range of clock frequencies. A calibration feature (DFLL)

is available, and can be used for automatic run-time calibration of the internal oscillators to remove frequency drift over

voltage and temperature. An oscillator failure monitor can be enabled to issue a non-maskable interrupt and switch to the

internal oscillator if the external oscillator or PLL fails.

When a reset occurs, all clock sources except the 32kHz ultra low power oscillator are disabled. After reset, the device

will always start up running from the 2MHz internal oscillator. During normal operation, the system clock source and

prescalers can be changed from software at any time.

Figure 9-1 on page 19 presents the principal clock system in the XMEGA D4 family of devices. Not all of the clocks need

to be active at a given time. The clocks for the CPU and peripherals can be stopped using sleep modes and power

reduction registers, as described in “Power Management and Sleep Modes” on page 21.

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Figure 9-1. The clock system, clock sources and clock distribution.

9.3 Clock Sources

The clock sources are divided in two main groups: internal oscillators and external clock sources. Most of the clock

sources can be directly enabled and disabled from software, while others are automatically enabled or disabled,

depending on peripheral settings. After reset, the device starts up running from the 2MHz internal oscillator. The other

clock sources, DFLLs and PLL, are turned off by default.

The internal oscillators do not require any external components to run. For details on characteristics and accuracy of the

internal oscillators, refer to the device datasheet.

9.3.1 32kHz Ultra Low Power Internal Oscillator

This oscillator provides an approximate 32kHz clock. The 32kHz ultra low power (ULP) internal oscillator is a very low

power clock source, and it is not designed for high accuracy. The oscillator employs a built-in prescaler that provides a

Real Time

Counter Peripherals RAM AVR CPU Non-Volatile

Memory

Watchdog

Timer

Brown-out

Detector

System Clock Prescalers

System Clock Multiplexer

(SCLKSEL)

PLLSRC

RTCSRC

DIV32

32 kHz

Int. ULP

32.768 kHz

Int. OSC

32.768 kHz

TOSC

2 MHz

Int. Osc

32 MHz

Int. Osc

0.4 – 16 MHz

XTAL

DIV32

DIV4

XOSCSEL

PLL

TOSC1

TOSC2

XTAL1

XTAL2

clkSYS

clkRTC

clkPER2

clkPER

clkCPU

clkPER4

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1kHz output. The oscillator is automatically enabled/disabled when it is used as clock source for any part of the device.

This oscillator can be selected as the clock source for the RTC.

9.3.2 32.768kHz Calibrated Internal Oscillator

This oscillator provides an approximate 32.768kHz clock. It is calibrated during production to provide a default frequency

close to its nominal frequency. The calibration register can also be written from software for run-time calibration of the

oscillator frequency. The oscillator employs a built-in prescaler, which provides both a 32.768kHz output and a 1.024kHz

output.

9.3.3 32.768kHz Crystal Oscillator

A 32.768kHz crystal oscillator can be connected between the TOSC1 and TOSC2 pins and enables a dedicated low

frequency oscillator input circuit. A low power mode with reduced voltage swing on TOSC2 is available. This oscillator

can be used as a clock source for the system clock and RTC, and as the DFLL reference clock.

9.3.4 0.4 - 16MHz Crystal Oscillator

This oscillator can operate in four different modes optimized for different frequency ranges, all within 0.4 - 16MHz.

9.3.5 2MHz Run-time Calibrated Internal Oscillator

The 2MHz run-time calibrated internal oscillator is the default system clock source after reset. It is calibrated during

production to provide a default frequency close to its nominal frequency. A DFLL can be enabled for automatic run-time

calibration of the oscillator to compensate for temperature and voltage drift and optimize the oscillator accuracy.

9.3.6 32MHz Run-time Calibrated Internal Oscillator

The 32MHz run-time calibrated internal oscillator is a high-frequency oscillator. It is calibrated during production to

provide a default frequency close to its nominal frequency. A digital frequency looked loop (DFLL) can be enabled for

automatic run-time calibration of the oscillator to compensate for temperature and voltage drift and optimize the oscillator

accuracy. This oscillator can also be adjusted and calibrated to any frequency between 30MHz and 55MHz.

9.3.7 External Clock Sources

The XTAL1 and XTAL2 pins can be used to drive an external oscillator, either a quartz crystal or a ceramic resonator.

XTAL1 can be used as input for an external clock signal. The TOSC1 and TOSC2 pins is dedicated to driving a

32.768kHz crystal oscillator.

9.3.8 PLL with 1x-31x Multiplication Factor

The built-in phase locked loop (PLL) can be used to generate a high-frequency system clock. The PLL has a user-

selectable multiplication factor of from 1 to 31. In combination with the prescalers, this gives a wide range of output

frequencies from all clock sources.

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10. Power Management and Sleep Modes

10.1 Features

zPower management for adjusting power consumption and functions

zFive sleep modes

zIdle

zPower down

zPower save

zStandby

zExtended standby

zPower reduction register to disable clock and turn off unused peripherals in active and idle modes

10.2 Overview

Various sleep modes and clock gating are provided in order to tailor power consumption to application requirements.

This enables the Atmel AVR XMEGA microcontroller to stop unused modules to save power.

All sleep modes are available and can be entered from active mode. In active mode, the CPU is executing application

code. When the device enters sleep mode, program execution is stopped and interrupts or a reset is used to wake the

device again. The application code decides which sleep mode to enter and when. Interrupts from enabled peripherals

and all enabled reset sources can restore the microcontroller from sleep to active mode.

In addition, power reduction registers provide a method to stop the clock to individual peripherals from software. When

this is done, the current state of the peripheral is frozen, and there is no power consumption from that peripheral. This

reduces the power consumption in active mode and idle sleep modes and enables much more fine-tuned power

management than sleep modes alone.

10.3 Sleep Modes

Sleep modes are used to shut down modules and clock domains in the microcontroller in order to save power. XMEGA

microcontrollers have five different sleep modes tuned to match the typical functional stages during application

execution. A dedicated sleep instruction (SLEEP) is available to enter sleep mode. Interrupts are used to wake the

device from sleep, and the available interrupt wake-up sources are dependent on the configured sleep mode. When an

enabled interrupt occurs, the device will wake up and execute the interrupt service routine before continuing normal

program execution from the first instruction after the SLEEP instruction. If other, higher priority interrupts are pending

when the wake-up occurs, their interrupt service routines will be executed according to their priority before the interrupt

service routine for the wake-up interrupt is executed. After wake-up, the CPU is halted for four cycles before execution

starts.

The content of the register file, SRAM and registers are kept during sleep. If a reset occurs during sleep, the device will

reset, start up, and execute from the reset vector.

10.3.1 Idle Mode

In idle mode the CPU and nonvolatile memory are stopped (note that any ongoing programming will be completed), but

all peripherals, including the interrupt controller, and event system are kept running. Any enabled interrupt will wake the

device.

10.3.2 Power-down Mode

In power-down mode, all clocks, including the real-time counter clock source, are stopped. This allows operation only of

asynchronous modules that do not require a running clock. The only interrupts that can wake up the MCU are the two-

wire interface address match interrupt, and asynchronous port interrupts.

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10.3.3 Power-save Mode

Power-save mode is identical to power down, with one exception. If the real-time counter (RTC) is enabled, it will keep

running during sleep, and the device can also wake up from either an RTC overflow or compare match interrupt.

10.3.4 Standby Mode

Standby mode is identical to power down, with the exception that the enabled system clock sources are kept running

while the CPU, peripheral, and RTC clocks are stopped. This reduces the wake-up time.

10.3.5 Extended Standby Mode

Extended standby mode is identical to power-save mode, with the exception that the enabled system clock sources are

kept running while the CPU and peripheral clocks are stopped. This reduces the wake-up time.

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11. System Control and Reset

11.1 Features

zReset the microcontroller and set it to initial state when a reset source goes active

zMultiple reset sources that cover different situations

zPower-on reset

zExternal reset

zWatchdog reset

zBrownout reset

zPDI reset

zSoftware reset

zAsynchronous operation

zNo running system clock in the device is required for reset

zReset status register for reading the reset source from the application code

11.2 Overview

The reset system issues a microcontroller reset and sets the device to its initial state. This is for situations where

operation should not start or continue, such as when the microcontroller operates below its power supply rating. If a reset

source goes active, the device enters and is kept in reset until all reset sources have released their reset. The I/O pins

are immediately tri-stated. The program counter is set to the reset vector location, and all I/O registers are set to their

initial values. The SRAM content is kept. However, if the device accesses the SRAM when a reset occurs, the content of

the accessed location can not be guaranteed.

After reset is released from all reset sources, the default oscillator is started and calibrated before the device starts

running from the reset vector address. By default, this is the lowest program memory address, 0, but it is possible to

move the reset vector to the lowest address in the boot section.

The reset functionality is asynchronous, and so no running system clock is required to reset the device. The software

reset feature makes it possible to issue a controlled system reset from the user software.

The reset status register has individual status flags for each reset source. It is cleared at power-on reset, and shows

which sources have issued a reset since the last power-on.

11.3 Reset Sequence

A reset request from any reset source will immediately reset the device and keep it in reset as long as the request is

active. When all reset requests are released, the device will go through three stages before the device starts running

again:

zReset counter delay

zOscillator startup

zOscillator calibration

If another reset requests occurs during this process, the reset sequence will start over again.

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11.4 Reset Sources

11.4.1 Power-on Reset

A power-on reset (POR) is generated by an on-chip detection circuit. The POR is activated when the VCC rises and

reaches the POR threshold voltage (VPOT), and this will start the reset sequence.

The POR is also activated to power down the device properly when the VCC falls and drops below the VPOT level.

The VPOT level is higher for falling VCC than for rising VCC. Consult the datasheet for POR characteristics data.

11.4.2 Brownout Detection

The on-chip brownout detection (BOD) circuit monitors the VCC level during operation by comparing it to a fixed,

programmable level that is selected by the BODLEVEL fuses. If disabled, BOD is forced on at the lowest level during chip

erase and when the PDI is enabled.

11.4.3 External Reset

The external reset circuit is connected to the external RESET pin. The external reset will trigger when the RESET pin is

driven below the RESET pin threshold voltage, VRST, for longer than the minimum pulse period, tEXT. The reset will be

held as long as the pin is kept low. The RESET pin includes an internal pull-up resistor.

11.4.4 Watchdog Reset

The watchdog timer (WDT) is a system function for monitoring correct program operation. If the WDT is not reset from

the software within a programmable timeout period, a watchdog reset will be given. The watchdog reset is active for one

to two clock cycles of the 2MHz internal oscillator. For more details see “WDT – Watchdog Timer” on page 25.

11.4.5 Software Reset

The software reset makes it possible to issue a system reset from software by writing to the software reset bit in the reset

control register.The reset will be issued within two CPU clock cycles after writing the bit. It is not possible to execute any

instruction from when a software reset is requested until it is issued.

11.4.6 Program and Debug Interface Reset

The program and debug interface reset contains a separate reset source that is used to reset the device during external

programming and debugging. This reset source is accessible only from external debuggers and programmers.

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12. WDT – Watchdog Timer

12.1 Features

zIssues a device reset if the timer is not reset before its timeout period

zAsynchronous operation from dedicated oscillator

z1kHz output of the 32kHz ultra low power oscillator

z11 selectable timeout periods, from 8ms to 8s

zTwo operation modes:

zNormal mode

zWindow mode

zConfiguration lock to prevent unwanted changes

12.2 Overview

The watchdog timer (WDT) is a system function for monitoring correct program operation. It makes it possible to recover

from error situations such as runaway or deadlocked code. The WDT is a timer, configured to a predefined timeout

period, and is constantly running when enabled. If the WDT is not reset within the timeout period, it will issue a

microcontroller reset. The WDT is reset by executing the WDR (watchdog timer reset) instruction from the application

code.

The window mode makes it possible to define a time slot or window inside the total timeout period during which WDT

must be reset. If the WDT is reset outside this window, either too early or too late, a system reset will be issued.

Compared to the normal mode, this can also catch situations where a code error causes constant WDR execution.

The WDT will run in active mode and all sleep modes, if enabled. It is asynchronous, runs from a CPU-independent clock

source, and will continue to operate to issue a system reset even if the main clocks fail.

The configuration change protection mechanism ensures that the WDT settings cannot be changed by accident. For

increased safety, a fuse for locking the WDT settings is also available.

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13. Interrupts and Programmable Multilevel Interrupt Controller

13.1 Features

zShort and predictable interrupt response time

zSeparate interrupt configuration and vector address for each interrupt

zProgrammable multilevel interrupt controller

zInterrupt prioritizing according to level and vector address

zThree selectable interrupt levels for all interrupts: low, medium and high

zSelectable, round-robin priority scheme within low-level interrupts

zNon-maskable interrupts for critical functions

zInterrupt vectors optionally placed in the application section or the boot loader section

13.2 Overview

Interrupts signal a change of state in peripherals, and this can be used to alter program execution. Peripherals can have

one or more interrupts, and all are individually enabled and configured. When an interrupt is enabled and configured, it

will generate an interrupt request when the interrupt condition is present. The programmable multilevel interrupt

controller (PMIC) controls the handling and prioritizing of interrupt requests. When an interrupt request is acknowledged

by the PMIC, the program counter is set to point to the interrupt vector, and the interrupt handler can be executed.

All peripherals can select between three different priority levels for their interrupts: low, medium, and high. Interrupts are

prioritized according to their level and their interrupt vector address. Medium-level interrupts will interrupt low-level

interrupt handlers. High-level interrupts will interrupt both medium- and low-level interrupt handlers. Within each level, the

interrupt priority is decided from the interrupt vector address, where the lowest interrupt vector address has the highest

interrupt priority. Low-level interrupts have an optional round-robin scheduling scheme to ensure that all interrupts are

serviced within a certain amount of time.

Non-maskable interrupts (NMI) are also supported, and can be used for system critical functions.

13.3 Interrupt vectors

The interrupt vector is the sum of the peripheral’s base interrupt address and the offset address for specific interrupts in

each peripheral. The base addresses for the Atmel AVR XMEGA D4 devices are shown in Table 13-1 on page 27. Offset

addresses for each interrupt available in the peripheral are described for each peripheral in the XMEGA D manual. For

peripherals or modules that have only one interrupt, the interrupt vector is shown in Table 13-1 on page 27. The program

address is the word address.

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Table 13-1. Reset and interrupt vectors.

Program Address

(Base Address) Source Interrupt Description

0x000 RESET

0x002 OSCF_INT_vect Crystal Oscillator Failure Interrupt vector (NMI)

0x004 PORTC_INT_base Port C Interrupt base

0x008 PORTR_INT_base Port R Interrupt base

0x014 RTC_INT_base Real Time Counter Interrupt base

0x018 TWIC_INT_base Two-Wire Interface on Port C Interrupt base

0x01C TCC0_INT_base Timer/Counter 0 on port C Interrupt base

0x028 TCC1_INT_base Timer/Counter 1 on port C Interrupt base

0x030 SPIC_INT_vect SPI on port C Interrupt vector

0x032 USARTC0_INT_base USART 0 on port C Interrupt base

0x040 NVM_INT_base Non-Volatile Memory Interrupt base

0x044 PORTB_INT_base Port B Interrupt base

0x056 PORTE_INT_base Port E Interrupt base

0x05A TWIE_INT_base Two-Wire Interface on Port E Interrupt base

0x05E TCE0_INT_base Timer/Counter 0 on port E Interrupt base

0x080 PORTD_INT_base Port D Interrupt base

0x084 PORTA_INT_base Port A Interrupt base

0x088 ACA_INT_base Analog Comparator on Port A Interrupt base

0x08E ADCA_INT_base Analog to Digital Converter on Port A Interrupt base

0x09A TCD0_INT_base Timer/Counter 0 on port D Interrupt base

0x0AE SPID_INT_vector SPI on port D Interrupt vector

0x0B0 USARTD0_INT_base USART 0 on port D Interrupt base

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14. I/O Ports

14.1 Features

z34 general purpose input and output pins with individual configuration

zOutput driver with configurable driver and pull settings:

zTotem-pole

zWired-AND

zWired-OR

zBus-keeper

zInverted I/O

zInput with synchronous and/or asynchronous sensing with interrupts and events

zSense both edges

zSense rising edges

zSense falling edges

zSense low level

zOptional pull-up and pull-down resistor on input and Wired-OR/AND configurations

zAsynchronous pin change sensing that can wake the device from all sleep modes

zTwo port interrupts with pin masking per I/O port

zEfficient and safe access to port pins

zHardware read-modify-write through dedicated toggle/clear/set registers

zConfiguration of multiple pins in a single operation

zMapping of port registers into bit-accessible I/O memory space

zPeripheral clocks output on port pin

zReal-time counter clock output to port pin

zEvent channels can be output on port pin

zRemapping of digital peripheral pin functions

zSelectable USART, SPI, and timer/counter input/output pin locations

14.2 Overview

One port consists of up to eight port pins: pin 0 to 7. Each port pin can be configured as input or output with configurable

driver and pull settings. They also implement synchronous and asynchronous input sensing with interrupts and events for

selectable pin change conditions. Asynchronous pin-change sensing means that a pin change can wake the device from

all sleep modes, included the modes where no clocks are running.

All functions are individual and configurable per pin, but several pins can be configured in a single operation. The pins

have hardware read-modify-write (RMW) functionality for safe and correct change of drive value and/or pull resistor

configuration. The direction of one port pin can be changed without unintentionally changing the direction of any other

pin.

The port pin configuration also controls input and output selection of other device functions. It is possible to have both the

peripheral clock and the real-time clock output to a port pin, and available for external use. The same applies to events

from the event system that can be used to synchronize and control external functions. Other digital peripherals, such as

USART, SPI, and timer/counters, can be remapped to selectable pin locations in order to optimize pin-out versus

application needs.

The notation of the ports are PORTA, PORTB, PORTC, PORTD, PORTE, and PORTR.

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14.3 Output Driver

All port pins (Pxn) have programmable output configuration.

14.3.1 Push-pull

Figure 14-1. I/O configuration - Totem-pole.

14.3.2 Pull-down

Figure 14-2. I/O configuration - Totem-pole with pull-down (on input).

14.3.3 Pull-up

Figure 14-3. I/O configuration - Totem-pole with pull-up (on input).

14.3.4 Bus-keeper

The bus-keeper’s weak output produces the same logical level as the last output level. It acts as a pull-up if the last level

was ‘1’, and pull-down if the last level was ‘0’.

INxn

OUTxn

DIRxn

Pxn

INxn

OUTxn

DIRxn

Pxn

INxn

OUTxn

DIRxn

Pxn

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Figure 14-4. I/O configuration - Totem-pole with bus-keeper.

14.3.5 Others

Figure 14-5. Output configuration - Wired-OR with optional pull-down.

Figure 14-6. I/O configuration - Wired-AND with optional pull-up.

14.4 Input sensing

Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is

shown in Figure 14-7.

INxn

OUTxn

DIRxn

Pxn

INxn

OUTxn

Pxn

INxn

OUTxn

Pxn

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Figure 14-7. Input sensing system overview.

When a pin is configured with inverted I/O, the pin value is inverted before the input sensing.

14.5 Alternate Port Functions

Most port pins have alternate pin functions in addition to being a general purpose I/O pin. When an alternate function is

enabled, it might override the normal port pin function or pin value. This happens when other peripherals that require pins

are enabled or configured to use pins. If and how a peripheral will override and use pins is described in the section for

that peripheral. “Pinout and Pin Functions” on page 48 shows which modules on peripherals that enable alternate

functions on a pin, and which alternate functions that are available on a pin.

INVERTED I/O

Interrupt

Control

Pxn Synchronizer

INn EDGE

DETECT

Synchronous sensing

EDGE

DETECT

Asynchronous sensing

IRQ

Synchronous

Events

Asynchronous

Events

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15. TC0/1 – 16-bit Timer/Counter Type 0 and 1

15.1 Features

zFour 16-bit timer/counters

zThree timer/counters of type 0

zOne timer/counter of type 1

z32-bit timer/counter support by cascading two timer/counters

zUp to four compare or capture (CC) channels

zFour CC channels for timer/counters of type 0

zTwo CC channels for timer/counters of type 1

zDouble buffered timer period setting

zDouble buffered capture or compare channels

zWaveform generation:

zFrequency generation

zSingle-slope pulse width modulation

zDual-slope pulse width modulation

zInput capture:

zInput capture with noise cancelling

zFrequency capture

zPulse width capture

z32-bit input capture

zTimer overflow and error interrupts/events

zOne compare match or input capture interrupt/event per CC channel

zCan be used with event system for:

zQuadrature decoding

zCount and direction control

zCapture

zHigh-resolution extension

zIncreases frequency and waveform resolution by 4x (2-bit) or 8x (3-bit)

zAdvanced waveform extension:

zLow- and high-side output with programmable dead-time insertion (DTI)

zEvent controlled fault protection for safe disabling of drivers

15.2 Overview

Atmel AVR XMEGA devices have a set of four flexible 16-bit Timer/Counters (TC). Their capabilities include accurate

program execution timing, frequency and waveform generation, and input capture with time and frequency measurement

of digital signals. Two timer/counters can be cascaded to create a 32-bit timer/counter with optional 32-bit capture.

A timer/counter consists of a base counter and a set of compare or capture (CC) channels. The base counter can be

used to count clock cycles or events. It has direction control and period setting that can be used for timing. The CC

channels can be used together with the base counter to do compare match control, frequency generation, and pulse

width waveform modulation, as well as various input capture operations. A timer/counter can be configured for either

capture or compare functions, but cannot perform both at the same time.

A timer/counter can be clocked and timed from the peripheral clock with optional prescaling or from the event system.

The event system can also be used for direction control and capture trigger or to synchronize operations.

There are two differences between timer/counter type 0 and type 1. Timer/counter 0 has four CC channels, and

timer/counter 1 has two CC channels. All information related to CC channels 3 and 4 is valid only for timer/counter 0.

Only Timer/Counter 0 has the split mode feature that split it into two 8-bit Timer/Counters with four compare channels

each.

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Some timer/counters have extensions to enable more specialized waveform and frequency generation. The advanced

waveform extension (AWeX) is intended for motor control and other power control applications. It enables low- and high-

side output with dead-time insertion, as well as fault protection for disabling and shutting down external drivers. It can

also generate a synchronized bit pattern across the port pins.

The advanced waveform extension can be enabled to provide extra and more advanced features for the Timer/Counter.

This are only available for Timer/Counter 0. See “AWeX – Advanced Waveform Extension” on page 35 for more details.

The high-resolution (hi-res) extension can be used to increase the waveform output resolution by four or eight times by

using an internal clock source running up to four times faster than the peripheral clock. See “Hi-Res – High Resolution

Extension” on page 36 for more details.

Figure 15-1. Overview of a Timer/Counter and closely related peripherals.

PORTC has one Timer/Counter 0 and one Timer/Counter1. PORTD and PORTE each has one Timer/Conter0. Notation

of these are TCC0 (Time/Counter C0), TCC1, TCD0 and TCE0, respectively.

AWeX

Compare/Capture Channel D

Compare/Capture Channel C

Compare/Capture Channel B

Compare/Capture Channel A

Waveform

Generation

Buffer

Comparator

Hi-Res

Fault

Protection

Capture

Control

Base Counter

Counter

Control Logic

Timer Period

Prescaler

Dead-Time

Insertion

Pattern

Generation

clkPER4

PORT

Event

System

clkPER

Timer/Counter

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16. TC2 Timer/Counter Type 2

16.1 Features

zSix eight-bit timer/counters

zThree Low-byte timer/counter

zThree High-byte timer/counter

zUp to eight compare channels in each Timer/Counter 2

zFour compare channels for the low-byte timer/counter

zFour compare channels for the high-byte timer/counter

zWaveform generation

zSingle slope pulse width modulation

zTimer underflow interrupts/events

zOne compare match interrupt/event per compare channel for the low-byte timer/counter

zCan be used with the event system for count control

16.2 Overview

There are three Timer/Counter 2. These are realized when a Timer/Counter 0 is set in split mode. It is then a system of

two eight-bit timer/counters, each with four compare channels. This results in eight configurable pulse width modulation

(PWM) channels with individually controlled duty cycles, and is intended for applications that require a high number of

PWM channels.

The two eight-bit timer/counters in this system are referred to as the low-byte timer/counter and high-byte timer/counter,

respectively. The difference between them is that only the low-byte timer/counter can be used to generate compare

match interrupts and events. The two eight-bit timer/counters have a shared clock source and separate period and

compare settings. They can be clocked and timed from the peripheral clock, with optional prescaling, or from the event

system. The counters are always counting down.

PORTC, PORTD and PORTE each has one Timer/Counter 2. Notation of these are TCC2 (Time/Counter C2), TCD2 and

TCE2, respectively.

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17. AWeX – Advanced Waveform Extension

17.1 Features

zWaveform output with complementary output from each compare channel

zFour dead-time insertion (DTI) units

z8-bit resolution

zSeparate high and low side dead-time setting

zDouble buffered dead time

zOptionally halts timer during dead-time insertion

zPattern generation unit creating synchronised bit pattern across the port pins

zDouble buffered pattern generation

zOptional distribution of one compare channel output across the port pins

zEvent controlled fault protection for instant and predictable fault triggering

17.2 Overview

The advanced waveform extension (AWeX) provides extra functions to the timer/counter in waveform generation (WG)

modes. It is primarily intended for use with different types of motor control and other power control applications. It

enables low- and high side output with dead-time insertion and fault protection for disabling and shutting down external

drivers. It can also generate a synchronized bit pattern across the port pins.

Each of the waveform generator outputs from the timer/counter 0 are split into a complimentary pair of outputs when any

AWeX features are enabled. These output pairs go through a dead-time insertion (DTI) unit that generates the non-

inverted low side (LS) and inverted high side (HS) of the WG output with dead-time insertion between LS and HS

switching. The DTI output will override the normal port value according to the port override setting.

The pattern generation unit can be used to generate a synchronized bit pattern on the port it is connected to. In addition,

the WG output from compare channel A can be distributed to and override all the port pins. When the pattern generator

unit is enabled, the DTI unit is bypassed.

The fault protection unit is connected to the event system, enabling any event to trigger a fault condition that will disable

the AWeX output. The event system ensures predictable and instant fault reaction, and gives flexibility in the selection of

fault triggers.

The AWeX is available for TCC0. The notation of this is AWEXC.

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18. Hi-Res – High Resolution Extension

18.1 Features

zIncreases waveform generator resolution up to 8x (three bits)

zSupports frequency, single-slope PWM, and dual-slope PWM generation

zSupports the AWeX when this is used for the same timer/counter

18.2 Overview

The high-resolution (hi-res) extension can be used to increase the resolution of the waveform generation output from a

timer/counter by four or eight. It can be used for a timer/counter doing frequency, single-slope PWM, or dual-slope PWM

generation. It can also be used with the AWeX if this is used for the same timer/counter.

The hi-res extension uses the peripheral 4x clock (ClkPER4). The system clock prescalers must be configured so the

peripheral 4x clock frequency is four times higher than the peripheral and CPU clock frequency when the hi-res extension

is enabled.

There is one hi-res extension that can be enabled for each timer/counter on PORTC. The notation of this is HIRESC.

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19. RTC – 16-bit Real-Time Counter

19.1 Features

z16-bit resolution

zSelectable clock source

z32.768kHz external crystal

zExternal clock

z32.768kHz internal oscillator

z32kHz internal ULP oscillator

zProgrammable 10-bit clock prescaling

zOne compare register

zOne period register

zClear counter on period overflow

zOptional interrupt/event on overflow and compare match

19.2 Overview

The 16-bit real-time counter (RTC) is a counter that typically runs continuously, including in low-power sleep modes, to

keep track of time. It can wake up the device from sleep modes and/or interrupt the device at regular intervals.

The reference clock is typically the 1.024kHz output from a high-accuracy crystal of 32.768kHz, and this is the

configuration most optimized for low power consumption. The faster 32.768kHz output can be selected if the RTC needs

a resolution higher than 1ms. The RTC can also be clocked from an external clock signal, the 32.768kHz internal

oscillator or the 32kHz internal ULP oscillator.

The RTC includes a 10-bit programmable prescaler that can scale down the reference clock before it reaches the

counter. A wide range of resolutions and time-out periods can be configured. With a 32.768kHz clock source, the

maximum resolution is 30.5µs, and time-out periods can range up to 2000 seconds. With a resolution of 1s, the

maximum timeout period is more than18 hours (65536 seconds). The RTC can give a compare interrupt and/or event

when the counter equals the compare register value, and an overflow interrupt and/or event when it equals the period

Figure 19-1. Real-time counter overview.

32.768kHz Crystal Osc

32.768kHz Int. Osc

TOSC1

TOSC2

External Clock

DIV32

32kHz int ULP (DIV32)

RTCSRC

10-bit

prescaler

clkRTC

CNT

PER

COMP

”match”/

Compare

TOP/

Overflow

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20. TWI – Two-Wire Interface

20.1 Features

zTwo identical two-wire interface peripherals

zBidirectional, two-wire communication interface

zPhillips I2C compatible

zSystem Management Bus (SMBus) compatible

zBus master and slave operation supported

zSlave operation

zSingle bus master operation

zBus master in multi-master bus environment

zMulti-master arbitration

zFlexible slave address match functions

z7-bit and general call address recognition in hardware

z10-bit addressing supported

zAddress mask register for dual address match or address range masking

zOptional software address recognition for unlimited number of addresses

zSlave can operate in all sleep modes, including power-down

zSlave address match can wake device from all sleep modes

z100kHz and 400kHz bus frequency support

zSlew-rate limited output drivers

zInput filter for bus noise and spike suppression

zSupport arbitration between start/repeated start and data bit (SMBus)

zSlave arbitration allows support for address resolve protocol (ARP) (SMBus)

20.2 Overview

The two-wire interface (TWI) is a bidirectional, two-wire communication interface. It is I2C and System Management Bus

(SMBus) compatible. The only external hardware needed to implement the bus is one pull-up resistor on each bus line.

A device connected to the bus must act as a master or a slave. The master initiates a data transaction by addressing a

slave on the bus and telling whether it wants to transmit or receive data. One bus can have many slaves and one or

several masters that can take control of the bus. An arbitration process handles priority if more than one master tries to

transmit data at the same time. Mechanisms for resolving bus contention are inherent in the protocol.

The TWI module supports master and slave functionality. The master and slave functionality are separated from each

other, and can be enabled and configured separately. The master module supports multi-master bus operation and

arbitration. It contains the baud rate generator. Both 100kHz and 400kHz bus frequency is supported. Quick command

and smart mode can be enabled to auto-trigger operations and reduce software complexity.

The slave module implements 7-bit address match and general address call recognition in hardware. 10-bit addressing is

also supported. A dedicated address mask register can act as a second address match register or as a register for

address range masking. The slave continues to operate in all sleep modes, including power-down mode. This enables

the slave to wake up the device from all sleep modes on TWI address match. It is possible to disable the address

matching to let this be handled in software instead.

The TWI module will detect START and STOP conditions, bus collisions, and bus errors. Arbitration lost, errors, collision,

and clock hold on the bus are also detected and indicated in separate status flags available in both master and slave

modes.

It is possible to disable the TWI drivers in the device, and enable a four-wire digital interface for connecting to an external

TWI bus driver. This can be used for applications where the device operates from a different VCC voltage than used by

the TWI bus.

PORTC and PORTE each has one TWI. Notation of these peripherals are TWIC and TWIE.

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21. SPI – Serial Peripheral Interface

21.1 Features

zTwo identical SPI peripherals

zFull-duplex, three-wire synchronous data transfer

zMaster or slave operation

zLsb first or msb first data transfer

zEight programmable bit rates

zInterrupt flag at the end of transmission

zWrite collision flag to indicate data collision

zWake up from idle sleep mode

zDouble speed master mode

21.2 Overview

The Serial Peripheral Interface (SPI) is a high-speed synchronous data transfer interface using three or four pins. It

allows fast communication between an Atmel AVR XMEGA device and peripheral devices or between several

microcontrollers. The SPI supports full-duplex communication.

A device connected to the bus must act as a master or slave. The master initiates and controls all data transactions.

PORTC and PORTD each has one SPI. Notation of these peripherals are SPIC and SPID.

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22. USART

22.1 Features

zTwo identical USART peripherals

zFull-duplex operation

zAsynchronous or synchronous operation

zSynchronous clock rates up to 1/2 of the device clock frequency

zAsynchronous clock rates up to 1/8 of the device clock frequency

zSupports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits

zFractional baud rate generator

zCan generate desired baud rate from any system clock frequency

zNo need for external oscillator with certain frequencies

zBuilt-in error detection and correction schemes

zOdd or even parity generation and parity check

zData overrun and framing error detection

zNoise filtering includes false start bit detection and digital low-pass filter

zSeparate interrupts for

zTransmit complete

zTransmit data register empty

zReceive complete

zMultiprocessor communication mode

zAddressing scheme to address a specific devices on a multidevice bus

zEnable unaddressed devices to automatically ignore all frames

zMaster SPI mode

zDouble buffered operation

zOperation up to 1/2 of the peripheral clock frequency

zIRCOM module for IrDA compliant pulse modulation/demodulation

22.2 Overview

The universal synchronous and asynchronous serial receiver and transmitter (USART) is a fast and flexible serial

communication module. The USART supports full-duplex communication and asynchronous and synchronous operation.

The USART can be configured to operate in SPI master mode and used for SPI communication.

Communication is frame based, and the frame format can be customized to support a wide range of standards. The

USART is buffered in both directions, enabling continued data transmission without any delay between frames. Separate

interrupts for receive and transmit complete enable fully interrupt driven communication. Frame error and buffer overflow

are detected in hardware and indicated with separate status flags. Even or odd parity generation and parity check can

also be enabled.

The clock generator includes a fractional baud rate generator that is able to generate a wide range of USART baud rates

from any system clock frequencies. This removes the need to use an external crystal oscillator with a specific frequency

to achieve a required baud rate. It also supports external clock input in synchronous slave operation.

When the USART is set in master SPI mode, all USART-specific logic is disabled, leaving the transmit and receive

buffers, shift registers, and baud rate generator enabled. Pin control and interrupt generation are identical in both modes.

The registers are used in both modes, but their functionality differs for some control settings.

An IRCOM module can be enabled for one USART to support IrDA 1.4 physical compliant pulse modulation and

demodulation for baud rates up to 115.2kbps.

PORTC and PORTD each has one USART. Notation of these peripherals are USARTC0 and USARTD0 respectively.

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23. IRCOM – IR Communication Module

23.1 Features

zPulse modulation/demodulation for infrared communication

zIrDA compatible for baud rates up to 115.2kbps

zSelectable pulse modulation scheme

z3/16 of the baud rate period

zFixed pulse period, 8-bit programmable

zPulse modulation disabled

zBuilt-in filtering

zCan be connected to and used by any USART

23.2 Overview

Atmel AVR XMEGA devices contain an infrared communication module (IRCOM) that is IrDA compatible for baud rates

up to 115.2Kbps. It can be connected to any USART to enable infrared pulse encoding/decoding for that USART.

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24. CRC – Cyclic Redundancy Check Generator

24.1 Features

zCyclic redundancy check (CRC) generation and checking for

zCommunication data

zProgram or data in flash memory

zData in SRAM and I/O memory space

zIntegrated with flash memory and CPU

zAutomatic CRC of the complete or a selectable range of the flash memory

zCPU can load data to the CRC generator through the I/O interface

zCRC polynomial software selectable to

zCRC-16 (CRC-CCITT)

zCRC-32 (IEEE 802.3)

zZero remainder detection

24.2 Overview

A cyclic redundancy check (CRC) is an error detection technique test algorithm used to find accidental errors in data, and

it is commonly used to determine the correctness of a data transmission, and data present in the data and program

memories. A CRC takes a data stream or a block of data as input and generates a 16- or 32-bit output that can be

appended to the data and used as a checksum. When the same data are later received or read, the device or application

repeats the calculation. If the new CRC result does not match the one calculated earlier, the block contains a data error.

The application will then detect this and may take a corrective action, such as requesting the data to be sent again or

simply not using the incorrect data.

Typically, an n-bit CRC applied to a data block of arbitrary length will detect any single error burst not longer than n bits

(any single alteration that spans no more than n bits of the data), and will detect the fraction 1-2-n of all longer error

bursts. The CRC module in Atmel AVR XMEGA devices supports two commonly used CRC polynomials; CRC-16 (CRC-

CCITT) and CRC-32 (IEEE 802.3).

zCRC-16:

zCRC-32:

Polynomial: x16+x12+x5+1

Hex value: 0x1021

Polynomial: x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1

Hex value: 0x04C11DB7

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25. ADC – 12-bit Analog to Digital Converter

25.1 Features

zOne Analog to Digital Converters (ADC)

z12-bit resolution

zUp to 200 thousand samples per second

zDown to 3.6µs conversion time with 8-bit resolution

zDown to 5.0µs conversion time with 12-bit resolution

zDifferential and single-ended input

zUp to 12 single-ended inputs

z12x4 differential inputs without gain

z12x4 differential input with gain

zBuilt-in differential gain stage

z1/2x, 1x, 2x, 4x, 8x, 16x, 32x, and 64x gain options

zSingle, continuous and scan conversion options

zThree internal inputs

zInternal temperature sensor

zVCC voltage divided by 10

z1.1V bandgap voltage

zInternal and external reference options

zCompare function for accurate monitoring of user defined thresholds

zOptional event triggered conversion for accurate timing

zOptional interrupt/event on compare result

25.2 Overview

The ADC converts analog signals to digital values. The ADC has 12-bit resolution and is capable of converting up to 200

thousand samples per second (ksps). The input selection is flexible, and both single-ended and differential

measurements can be done. For differential measurements, an optional gain stage is available to increase the dynamic

range. In addition, several internal signal inputs are available. The ADC can provide both signed and unsigned results.

The ADC measurements can either be started by application software or an incoming event from another peripheral in

the device. The ADC measurements can be started with predictable timing, and without software intervention.

Both internal and external reference voltages can be used. An integrated temperature sensor is available for use with the

ADC. The VCC/10 and the bandgap voltage can also be measured by the ADC.

The ADC has a compare function for accurate monitoring of user defined thresholds with minimum software intervention

required.

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Figure 25-1. ADC overview.

The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (propagation delay) from 5.0µs

for 12-bit to 3.6µs for 8-bit result.

ADC conversion results are provided left- or right adjusted with optional ‘1’ or ‘0’ padding. This eases calculation when

the result is represented as a signed integer (signed 16-bit number).

Notation of this peripheral is ADCA. The PORTA has ADCA inputs 0..7 and PORTB has ADCA inputs 8..11.

CH0 Result

Compare

>Threshold

(Int Req)

Internal 1.00V

Internal VCC/1.6V

AREFA

AREFB

VINP

VINN

Internal

signals

Internal VCC/2

ADC0

ADC11

•

ADC0

ADC7

•

Reference

Voltage

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26. AC – Analog Comparator

26.1 Features

zTwo Analog Comparators (ACs)

zSelectable hysteresis

zNo

zSmall

zLarge

zAnalog comparator output available on pin

zFlexible input selection

zAll pins on the port

zBandgap reference voltage

zA 64-level programmable voltage scaler of the internal VCC voltage

zInterrupt and event generation on:

zRising edge

zFalling edge

zToggle

zWindow function interrupt and event generation on:

zSignal above window

zSignal inside window

zSignal below window

zConstant current source with configurable output pin selection

26.2 Overview

The analog comparator (AC) compares the voltage levels on two inputs and gives a digital output based on this

comparison. The analog comparator may be configured to generate interrupt requests and/or events upon several

different combinations of input change.

The important property of the analog comparator’s dynamic behavior is the hysteresis. It can be adjusted in order to

achieve the optimal operation for each application.

The input selection includes analog port pins, several internal signals, and a 64-level programmable voltage scaler. The

analog comparator output state can also be output on a pin for use by external devices.

A constant current source can be enabled and output on a selectable pin. This can be used to replace, for example,

external resistors used to charge capacitors in capacitive touch sensing applications.

The analog comparators are always grouped in pairs on each port. These are called analog comparator 0 (AC0) and

analog comparator 1 (AC1). They have identical behavior, but separate control registers. Used as pair, they can be set in

window mode to compare a signal to a voltage range instead of a voltage level.

PORTA has one AC pair. Notation is ACA.

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Figure 26-1. Analog comparator overview.

The window function is realized by connecting the external inputs of the two analog comparators in a pair as shown in

Figure 26-2.

Figure 26-2. Analog comparator window function.

ACnMUXCTRL ACnCTRL

Interrupt

Mode

Enable

Hysteresis

AC1OUT

WINCTRL

Interrupt

Sensititivity

Control

Window

Function

Events

Interrupts

AC0OUT

Pin Input

Voltage

Scaler

Bandgap

AC0

AC1

Input signal

Upper limit of window

Lower limit of window

Interrupt

sensitivity

control

Interrupts

Events

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27. Programming and Debugging

27.1 Features

zProgramming

zExternal programming through PDI interface

zMinimal protocol overhead for fast operation

zBuilt-in error detection and handling for reliable operation

zBoot loader support for programming through any communication interface

zDebugging

zNonintrusive, real-time, on-chip debug system

zNo software or hardware resources required from device except pin connection

zProgram flow control

zGo, Stop, Reset, Step Into, Step Over, Step Out, Run-to-Cursor

zUnlimited number of user program breakpoints

zUnlimited number of user data breakpoints, break on:

zData location read, write, or both read and write

zData location content equal or not equal to a value

zData location content is greater or smaller than a value

zData location content is within or outside a range

zNo limitation on device clock frequency

zProgram and Debug Interface (PDI)

zTwo-pin interface for external programming and debugging

zUses the Reset pin and a dedicated pin

zNo I/O pins required during programming or debugging

27.2 Overview

The Program and Debug Interface (PDI) is an Atmel proprietary interface for external programming and on-chip

debugging of a device.

The PDI supports fast programming of nonvolatile memory (NVM) spaces; flash, EEPOM, fuses, lock bits, and the user

signature row.

Debug is supported through an on-chip debug system that offers nonintrusive, real-time debug. It does not require any

software or hardware resources except for the device pin connection. Using the Atmel tool chain, it offers complete

program flow control and support for an unlimited number of program and complex data breakpoints. Application debug

can be done from a C or other high-level language source code level, as well as from an assembler and disassembler

level.

Programming and debugging can be done through the PDI physical layer. This is a two-pin interface that uses the Reset

pin for the clock input (PDI_CLK) and one other dedicated pin for data input and output (PDI_DATA). Any external

programmer or on-chip debugger/emulator can be directly connected to this interface.

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28. Pinout and Pin Functions

The device pinout is shown in ”Pinout/Block Diagram” on page 3. In addition to general purpose I/O functionality, each

pin can have several alternate functions. This will depend on which peripheral is enabled and connected to the actual pin.

Only one of the pin functions can be used at time.

28.1 Alternate Pin Function Description

The tables below show the notation for all pin functions available and describe its function.

28.1.1 Operation/Power Supply

28.1.2 Port Interrupt functions

28.1.3 Analog functions

28.1.4 Timer/Counter and AWEX functions

28.1.5 Communication functions

VCC Digital supply voltage

AVCC Analog supply voltage

GND Ground

SYNC Port pin with full synchronous and limited asynchronous interrupt function

ASYNC Port pin with full synchronous and full asynchronous interrupt function

ACn Analog Comparator input pin n

ACnOUT Analog Comparator n Output

ADCn Analog to Digital Converter input pin n

AREF Analog reference input pin

OCnxLS Output Compare Channel x Low Side for Timer/Counter n

OCnxHS Output Compare Channel x High Side for Timer/Counter n

SCL Serial Clock for TWI

SDA Serial Data for TWI

XCKn Transfer Clock for USART n

RXDn Receiver Data for USART n

TXDn Transmitter Data for USART n

SS Slave Select for SPI

MOSI Master Out Slave In for SPI

MISO Master In Slave Out for SPI

SCK Serial Clock for SPI

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28.1.6 Oscillators, Clock and Event

28.1.7 Debug/System functions

TOSCn Timer Oscillator pin n

XTALn Input/Output for Oscillator pin n

CLKOUT Peripheral Clock Output

EVOUT Event Channel Output

RTCOUT RTC Clock Source Output

RESET Reset pin

PDI_CLK Program and Debug Interface Clock pin

PDI_DATA Program and Debug Interface Data pin

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28.2 Alternate Pin Functions

The tables below show the primary/default function for each pin on a port in the first column, the pin number in the

second column, and then all alternate pin functions in the remaining columns. The head row shows what peripheral that

enable and use the alternate pin functions.

For better flexibility, some alternate functions also have selectable pin locations for their functions, this is noted under the

first table where this apply.

Table 28-1. Port A - alternate functions.

Table 28-2. Port B - alternate functions.

PORT A PIN# INTERRUPT

ADCA

POS/GAINPOS

ADCA

NEG

ADCA

GAINNEG ACAPOS ACANEG ACAOUT REFA

GND 38

AVCC 39

PA0 40 SYNC ADC0 ADC0 AC0 AC0 AREF

PA1 41 SYNC ADC1 ADC1 AC1 AC1

PA2 42 SYNC/ASYNC ADC2 ADC2 AC2

PA3 43 SYNC ADC3 ADC3 AC3 AC3

PA4 44 SYNC ADC4 ADC4 AC4

PA5 1SYNC ADC5 ADC5 AC5 AC5

PA6 2SYNC ADC6 ADC6 AC6

PA7 3SYNC ADC7 ADC7 AC7 AC0OUT

PORT B PIN# INTERRUPT ADCAPOS/GAINPOS REFB

PB0 4SYNC ADC8 AREF

PB1 5SYNC ADC9

PB2 6SYNC/ASYNC ADC10

PB3 7SYNC ADC11

XMEGA D4 [DATASHEET]

8315N–AVR–04/2013

Table 28-3. Port C - alternate functions.

Notes: 1. Pin mapping of all TC0 can optionally be moved to high nibble of port

2. If TC0 is configured as TC2 all eight pins can be used for PWM output.

3. Pin mapping of all USART0 can optionally be moved to high nibble of port.

4. Pins MOSI and SCK for all SPI can optionally be swapped.

5. CLKOUT can optionally be moved between port C, D and E and between pin 4 and 7.

6. EVOUT can optionally be moved between port C, D and E and between pin 4 and 7.

Table 28-4. Port D - alternate functions.

Table 28-5. Port E - alternate functions.

PORT C PIN# INTERRUPT TCC0(1)(2) AWEXC TCC1 USARTC0(3) SPIC(4) TWIC CLOCKOUT(5) EVENTOUT(6)

GND 8

VCC 9

PC0 10 SYNC OC0A OC0ALS SDA

PC1 11 SYNC OC0B OC0AHS XCK0 SCL

PC2 12 SYNC/ASYNC OC0C OC0BLS RXD0

PC3 13 SYNC OC0D OC0BHS TXD0

PC4 14 SYNC OC0CLS OC1A SS

PC5 15 SYNC OC0CHS OC1B MOSI

PC6 16 SYNC OC0DLS MISO clkRTC

PC7 17 SYNC OC0DHS SCK clkPER EVOUT

PORT D PIN # INTERRUPT TCD0 USARTD0 SPID CLOCKOUT EVENTOUT

GND 18

VCC 19

PD0 20 SYNC OC0A

PD1 21 SYNC OC0B XCK0

PD2 22 SYNC/ASYNC OC0C RXD0

PD3 23 SYNC OC0D TXD0

PD4 24 SYNC SS

PD5 25 SYNC MOSI

PD6 26 SYNC MISO

PD7 27 SYNC SCK clkPER EVOUT

PORT E PIN # INTERRUPT TCE0 TWIE

PE0 28 SYNC OC0A SDA

PE1 29 SYNC OC0B SCL

GND 30

XMEGA D4 [DATASHEET]

8315N–AVR–04/2013

Table 28-6. Port F - alternate functions.

Note: 1. TOSC pins can optionally be moved to PE2/PE3

VCC 31

PE2 32 SYNC/ASYNC OC0C

PE3 33 SYNC OC0D

PORT R PIN # INTERRUPT PDI XTAL TOSC(1)

PDI 34 PDI_DATA

RESET 35 PDI_CLOCK

PRO 36 SYNC XTAL2 TOSC2

PR1 37 SYNC XTAL1 TOSC1

PORT E PIN # INTERRUPT TCE0 TWIE

XMEGA D4 [DATASHEET]

8315N–AVR–04/2013

29. Peripheral Module Address Map

The address maps show the base address for each peripheral and module in Atmel AVR XMEGA D4. For complete

Table 29-1. Peripheral module address map.

Base address Name Description

0x0000 GPIO General purpose IO registers

0x0010 VPORT0 Virtual Port 0

0x0014 VPORT1 Virtual Port 1

0x0018 VPORT2 Virtual Port 2

0x001C VPORT3 Virtual Port 2

0x0030 CPU CPU

0x0040 CLK Clock control

0x0048 SLEEP Sleep controller

0x0050 OSC Oscillator control

0x0060 DFLLRC32M DFLL for the 32 MHz internal RC oscillator

0x0068 DFLLRC2M DFLL for the 2 MHz RC oscillator

0x0070 PR Power reduction

0x0078 RST Reset controller

0x0080 WDT Watch-dog timer

0x0090 MCU MCU control

0x00A0 PMIC Programmable multilevel interrupt controller

0x00B0 PORTCFG Port configuration

0x0180 EVSYS Event system

0x00D0 CRC CRC module

0x01C0 NVM Nonvolatile memory (NVM) controller

0x0200 ADCA Analog to digital converter on port A

0x0380 ACA Analog comparator pair on port A

0x0400 RTC Real time counter

0x0480 TWIC Two wire interface on port C

0x04A0 TWIE Two wire interface on port E

0x0600 PORTA Port A

0x0620 PORTB Port B

0x0640 PORTC Port C

0x0660 PORTD Port D

XMEGA D4 [DATASHEET]

8315N–AVR–04/2013

0x0680 PORTE Port E

0x07E0 PORTR Port R

0x0800 TCC0 Timer/counter 0 on port C

0x0840 TCC1 Timer/counter 1 on port C

0x0880 AWEXC Advanced waveform extension on port C

0x0890 HIRESC High resolution extension on port C

0x08A0 USARTC0 USART 0 on port C

0x08C0 SPIC Serial peripheral interface on port C

0x08F8 IRCOM Infrared communication module

0x0900 TCD0 Timer/counter 0 on port D

0x09A0 USARTD0 USART 0 on port D

0x09C0 SPID Serial peripheral interface on port D

0x0A00 TCE0 Timer/counter 0 on port E

Base address Name Description

XMEGA D4 [DATASHEET]

8315N–AVR–04/2013

30. Instruction Set Summary

Mnemonics Operands Description Operation Flags #Clocks

Arithmetic and Logic Instructions

ADD Rd, Rr Add without Carry Rd ←Rd + Rr Z,C,N,V,S,H 1

ADC Rd, Rr Add with Carry Rd ←Rd + Rr + C Z,C,N,V,S,H 1

ADIW Rd, K Add Immediate to Word Rd ←Rd + 1:Rd + K Z,C,N,V,S 2

SUB Rd, Rr Subtract without Carry Rd ←Rd - Rr Z,C,N,V,S,H 1

SUBI Rd, K Subtract Immediate Rd ←Rd - K Z,C,N,V,S,H 1

SBC Rd, Rr Subtract with Carry Rd ←Rd - Rr - C Z,C,N,V,S,H 1

SBCI Rd, K Subtract Immediate with Carry Rd ←Rd - K - C Z,C,N,V,S,H 1

SBIW Rd, K Subtract Immediate from Word Rd + 1:Rd ←Rd + 1:Rd - K Z,C,N,V,S 2

AND Rd, Rr Logical AND Rd ←Rd • Rr Z,N,V,S 1

ANDI Rd, K Logical AND with Immediate Rd ←Rd • K Z,N,V,S 1

OR Rd, Rr Logical OR Rd ←Rd v Rr Z,N,V,S 1

ORI Rd, K Logical OR with Immediate Rd ←Rd v K Z,N,V,S 1

EOR Rd, Rr Exclusive OR Rd ←Rd ⊕ Rr Z,N,V,S 1

COM Rd One’s Complement Rd ←$FF - Rd Z,C,N,V,S 1

NEG Rd Two’s Complement Rd ←$00 - Rd Z,C,N,V,S,H 1

SBR Rd,K Set Bit(s) in Register Rd ←Rd v K Z,N,V,S 1

CBR Rd,K Clear Bit(s) in Register Rd ←Rd • ($FFh - K) Z,N,V,S 1

INC Rd Increment Rd ←Rd + 1 Z,N,V,S 1

DEC Rd Decrement Rd ←Rd - 1 Z,N,V,S 1

TST Rd Test for Zero or Minus Rd ←Rd • Rd Z,N,V,S 1

CLR Rd Clear Register Rd ←Rd ⊕ Rd Z,N,V,S 1

SER Rd Set Register Rd ←$FF None 1

MUL Rd,Rr Multiply Unsigned R1:R0 ←Rd x Rr (UU) Z,C 2

MULS Rd,Rr Multiply Signed R1:R0 ←Rd x Rr (SS) Z,C 2

MULSU Rd,Rr Multiply Signed with Unsigned R1:R0 ←Rd x Rr (SU) Z,C 2

FMUL Rd,Rr Fractional Multiply Unsigned R1:R0 ←Rd x Rr<<1 (UU) Z,C 2

FMULS Rd,Rr Fractional Multiply Signed R1:R0 ←Rd x Rr<<1 (SS) Z,C 2

FMULSU Rd,Rr Fractional Multiply Signed with Unsigned R1:R0 ←Rd x Rr<<1 (SU) Z,C 2

DES KData Encryption if (H = 0) then R15:R0

else if (H = 1) then R15:R0

←

Encrypt(R15:R0, K)

Decrypt(R15:R0, K)

1/2

Branch instructions

RJMP kRelative Jump PC ←PC + k + 1 None 2

IJMP Indirect Jump to (Z) PC(15:0)

PC(21:16)

←

None 2

EIJMP Extended Indirect Jump to (Z) PC(15:0)

PC(21:16)

←

EIND

None 2

JMP kJump PC ←kNone 3

XMEGA D4 [DATASHEET]

8315N–AVR–04/2013

RCALL kRelative Call Subroutine PC ←PC + k + 1 None 2 / 3(1)

ICALL Indirect Call to (Z) PC(15:0)

PC(21:16)

←

None 2 / 3(1)

EICALL Extended Indirect Call to (Z) PC(15:0)

PC(21:16)

←

EIND

None 3(1)

CALL kcall Subroutine PC ←kNone 3 / 4(1)

RET Subroutine Return PC ←STACK None 4 / 5(1)

RETI Interrupt Return PC ←STACK I4 / 5(1)

CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ←PC + 2 or 3 None 1 / 2 / 3

CP Rd,Rr Compare Rd - Rr Z,C,N,V,S,H 1

CPC Rd,Rr Compare with Carry Rd - Rr - C Z,C,N,V,S,H 1

CPI Rd,K Compare with Immediate Rd - K Z,C,N,V,S,H 1

SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b) = 0) PC ←PC + 2 or 3 None 1 / 2 / 3

SBRS Rr, b Skip if Bit in Register Set if (Rr(b) = 1) PC ←PC + 2 or 3 None 1 / 2 / 3

SBIC A, b Skip if Bit in I/O Register Cleared if (I/O(A,b) = 0) PC ←PC + 2 or 3 None 2 / 3 / 4

SBIS A, b Skip if Bit in I/O Register Set If (I/O(A,b) =1) PC ←PC + 2 or 3 None 2 / 3 / 4

BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC ←PC + k + 1 None 1 / 2

BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC ←PC + k + 1 None 1 / 2

BREQ k Branch if Equal if (Z = 1) then PC ←PC + k + 1 None 1 / 2

BRNE k Branch if Not Equal if (Z = 0) then PC ←PC + k + 1 None 1 / 2

BRCS k Branch if Carry Set if (C = 1) then PC ←PC + k + 1 None 1 / 2

BRCC k Branch if Carry Cleared if (C = 0) then PC ←PC + k + 1 None 1 / 2

BRSH k Branch if Same or Higher if (C = 0) then PC ←PC + k + 1 None 1 / 2

BRLO k Branch if Lower if (C = 1) then PC ←PC + k + 1 None 1 / 2

BRMI k Branch if Minus if (N = 1) then PC ←PC + k + 1 None 1 / 2

BRPL k Branch if Plus if (N = 0) then PC ←PC + k + 1 None 1 / 2

BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ←PC + k + 1 None 1 / 2

BRLT k Branch if Less Than, Signed if (N ⊕ V= 1) then PC ←PC + k + 1 None 1 / 2

BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ←PC + k + 1 None 1 / 2

BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ←PC + k + 1 None 1 / 2

BRTS k Branch if T Flag Set if (T = 1) then PC ←PC + k + 1 None 1 / 2

BRTC k Branch if T Flag Cleared if (T = 0) then PC ←PC + k + 1 None 1 / 2

BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ←PC + k + 1 None 1 / 2

BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ←PC + k + 1 None 1 / 2

BRIE k Branch if Interrupt Enabled if (I = 1) then PC ←PC + k + 1 None 1 / 2

BRID k Branch if Interrupt Disabled if (I = 0) then PC ←PC + k + 1 None 1 / 2

Data transfer instructions

MOV Rd, Rr Copy Register Rd ←Rr None 1

MOVW Rd, Rr Copy Register Pair Rd+1:Rd ←Rr+1:Rr None 1

Mnemonics Operands Description Operation Flags #Clocks

XMEGA D4 [DATASHEET]

8315N–AVR–04/2013

LDI Rd, K Load Immediate Rd ←KNone 1

LDS Rd, k Load Direct from data space Rd ←(k) None 2(1)(2)

LD Rd, X Load Indirect Rd ←(X) None 1(1)(2)

LD Rd, X+ Load Indirect and Post-Increment Rd

←

(X)

X + 1

None 1(1)(2)

LD Rd, -X Load Indirect and Pre-Decrement X ← X - 1,

Rd ← (X)

←

X - 1

(X)

None 2(1)(2)

LD Rd, Y Load Indirect Rd ← (Y) ←(Y) None 1(1)(2)

LD Rd, Y+ Load Indirect and Post-Increment Rd

←

(Y)

Y + 1

None 1(1)(2)

LD Rd, -Y Load Indirect and Pre-Decrement Y

←

Y - 1

(Y)

None 2(1)(2)

LDD Rd, Y+q Load Indirect with Displacement Rd ←(Y + q) None 2(1)(2)

LD Rd, Z Load Indirect Rd ←(Z) None 1(1)(2)

LD Rd, Z+ Load Indirect and Post-Increment Rd

←

(Z),

Z+1

None 1(1)(2)

LD Rd, -Z Load Indirect and Pre-Decrement Z

←

Z - 1,

(Z)

None 2(1)(2)

LDD Rd, Z+q Load Indirect with Displacement Rd ←(Z + q) None 2(1)(2)

STS k, Rr Store Direct to Data Space (k) ←Rd None 2(1)

ST X, Rr Store Indirect (X) ←Rr None 1(1)

ST X+, Rr Store Indirect and Post-Increment (X)

←

Rr,

X + 1

None 1(1)

ST -X, Rr Store Indirect and Pre-Decrement X

(X)

←

X - 1,

None 2(1)

ST Y, R r Store Indirect (Y) ←Rr None 1(1)

ST Y+, Rr Store Indirect and Post-Increment (Y)

←

Rr,

Y + 1

None 1(1)

ST -Y, Rr Store Indirect and Pre-Decrement Y

(Y)

←

Y - 1,

None 2(1)

STD Y+q, Rr Store Indirect with Displacement (Y + q) ←Rr None 2(1)

ST Z, Rr Store Indirect (Z) ←Rr None 1(1)

ST Z+, Rr Store Indirect and Post-Increment (Z)

←

Z + 1

None 1(1)

ST -Z, Rr Store Indirect and Pre-Decrement Z←Z - 1 None 2(1)

STD Z+q,Rr Store Indirect with Displacement (Z + q) ←Rr None 2(1)

LPM Load Program Memory R0 ←(Z) None 3

LPM Rd, Z Load Program Memory Rd ←(Z) None 3

LPM Rd, Z+ Load Program Memory and Post-Increment Rd

←

(Z),

Z + 1

None 3

ELPM Extended Load Program Memory R0 ←(RAMPZ:Z) None 3

ELPM Rd, Z Extended Load Program Memory Rd ←(RAMPZ:Z) None 3

ELPM Rd, Z+ Extended Load Program Memory and Post-

Increment

←

(RAMPZ:Z),

Z + 1

None 3

SPM Store Program Memory (RAMPZ:Z) ←R1:R0 None -

Mnemonics Operands Description Operation Flags #Clocks

XMEGA D4 [DATASHEET]

8315N–AVR–04/2013

SPM Z+ Store Program Memory and Post-Increment

by 2

(RAMPZ:Z)

←

R1:R0,

Z + 2

None -

IN Rd, A In From I/O Location Rd ←I/O(A) None 1

OUT A, Rr Out To I/O Location I/O(A) ←Rr None 1

PUSH Rr Push Register on Stack STACK ←Rr None 1(1)

POP Rd Pop Register from Stack Rd ←STACK None 2(1)

XCH Z, Rd Exchange RAM location Temp

(Z)

←

Rd,

(Z),

Tem p

None 2

LAS Z, Rd Load and Set RAM location Tem p

(Z)

←

Rd,

(Z),

Tem p v (Z )

None 2

LAC Z, Rd Load and Clear RAM location Temp

(Z)

←

Rd,

(Z),

($FFh – Rd) z (Z)

None 2

LAT Z, Rd Load and Toggle RAM location Tem p

(Z)

←

Rd,

(Z),

Tem p ⊕ (Z)

None 2

Bit and bit-test instructions

LSL Rd Logical Shift Left Rd(n+1)

Rd(0)

←

Rd(n),

Rd(7)

Z,C,N,V,H 1

LSR Rd Logical Shift Right Rd(n)

Rd(7)

←

Rd(n+1),

Rd(0)

Z,C,N,V 1

ROL Rd Rotate Left Through Carry Rd(0)

Rd(n+1)

←

Rd(n),

Rd(7)

Z,C,N,V,H 1

ROR Rd Rotate Right Through Carry Rd(7)

Rd(n)

←

Rd(n+1),

Rd(0)

Z,C,N,V 1

ASR Rd Arithmetic Shift Right Rd(n) ←Rd(n+1), n=0..6 Z,C,N,V 1

SWAP Rd Swap Nibbles Rd(3..0) ↔Rd(7..4) None 1

BSET sFlag Set SREG(s) ←1SREG(s) 1

BCLR sFlag Clear SREG(s) ←0SREG(s) 1

SBI A, b Set Bit in I/O Register I/O(A, b) ←1None 1

CBI A, b Clear Bit in I/O Register I/O(A, b) ←0None 1

BST Rr, b Bit Store from Register to T T←Rr(b) T 1

BLD Rd, b Bit load from T to Register Rd(b) ←TNone 1

SEC Set Carry C←1 C 1

CLC Clear Carry C←0 C 1

SEN Set Negative Flag N←1 N 1

CLN Clear Negative Flag N←0 N 1

SEZ Set Zero Flag Z←1 Z 1

CLZ Clear Zero Flag Z←0 Z 1

SEI Global Interrupt Enable I←1 I 1

CLI Global Interrupt Disable I←0 I 1

Mnemonics Operands Description Operation Flags #Clocks

XMEGA D4 [DATASHEET]

8315N–AVR–04/2013

Notes: 1. Cycle times for data memory accesses assume internal memory accesses, and are not valid for accesses via the external RAM interface.

2. One extra cycle must be added when accessing internal SRAM.

SES Set Signed Test Flag S←1 S 1

CLS Clear Signed Test Flag S←0 S 1

SEV Set Two’s Complement Overflow V←1 V 1

CLV Clear Two’s Complement Overflow V←0 V 1

SET Set T in SREG T←1 T 1

CLT Clear T in SREG T←0 T 1

SEH Set Half Carry Flag in SREG H←1 H 1

CLH Clear Half Carry Flag in SREG H←0 H 1

MCU control instructions

BREAK Break (See specific descr. for BREAK) None 1

NOP No Operation None 1

SLEEP Sleep (see specific descr. for Sleep) None 1

WDR Watchdog Reset (see specific descr. for WDR) None 1

Mnemonics Operands Description Operation Flags #Clocks

XMEGA D4 [DATASHEET]

8315N–AVR–04/2013

31. Packaging information

31.1 44A

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

44A, 44-lead, 10 x 10mm body size, 1.0mm body thickness,

0.8 mm lead pitch, thin profile plastic quad flat package (TQFP) C

44A

2010-10-20

PIN 1 IDENTIFIER

0°~7°

PIN 1

A1 A2 A

E1 E

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

Notes:

1. This package conforms to JEDEC reference MS-026, Variation ACB.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable

protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum

plastic body size dimensions including mold mismatch.

3. Lead coplanarity is 0.10mm maximum.

A – – 1.20

A1 0.05 – 0.15

A2 0.95 1.00 1.05

D 11.75 12.00 12.25

D1 9.90 10.00 10.10 Note 2

E 11.75 12.00 12.25

E1 9.90 10.00 10.10 Note 2

B 0.30 – 0.45

C 0.09 – 0.20

L 0.45 – 0.75

e 0.80 TYP

XMEGA D4 [DATASHEET]

8315N–AVR–04/2013

31.2 44M1

TITLE DRAWING NO.GPC REV.

Package Drawing Contact:

packagedrawings@atmel.com 44M1ZWS H

44M1, 44-pad, 7 x 7 x 1.0mm body, lead

pitch 0.50mm, 5.20mm exposed pad, thermally

enhanced plastic very thin quad flat no

lead package (VQFN)

9/26/08

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A 0.80 0.90 1.00

A1 – 0.02 0.05

A3 0.20 REF

b 0.18 0.23 0.30

D2 5.00 5.20 5.40

6.90 7.00 7.10

E2 5.00 5.20 5.40

e 0.50 BSC

L 0.59 0.64 0.69

K 0.20 0.26 0.41

Note: JEDEC Standard MO-220, Fig. 1 (SAW Singulation) VKKD-3.

TOP VIEW

SIDE VIEW

BOTTOM VIEW

Marked Pin# 1 ID

Pin #1 Corner

SEATING PLANE

Pin #1

Triangle

Pin #1

Chamfer

(C 0.30)

Option A

Option B

Pin #1

Notch

(0.20 R)

Option C

XMEGA D4 [DATASHEET]

8315N–AVR–04/2013

31.3 49C2

TITLE DRAWING NO. GPC REV.

Package Drawing Contact:

packagedrawings@atmel.com 49C2 CBD A

49C2, 49-ball (7 x 7 array), 0.65mm pitch,

5.0 x 5.0 x 1.0mm, very thin, fine-pitch

ball grid array package (VFBGA)

3/14/08

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A – – 1.00

A1 0.20 – –

A2 0.65 – –

D 4.90 5.00 5.10

D1 3.90 BSC

E 4.90 5.00 5.10

E1 3.90 BSC

b 0.30 0.35 0.40

e 0.65 BSC

TOP VIEW

SIDE VIEW

A1 BALL ID

1 2 3 4 5 6 7

0.10

49 - Ø0.35 ±0.05

A1 BALL CORNER

BOTTOM VIEW

b e

XMEGA D4 [DATASHEET]

8315N–AVR–04/2013

32. Electrical Characteristics

All typical values are measured at T = 25°C unless other temperature condition is given. All minimum and maximum

values are valid across operating temperature and voltage unless other conditions are given.

32.1 ATxmega16D4

32.1.1 Absolute Maximum Ratings

Stresses beyond those listed in Table 32-1 under may cause permanent damage to the device. This is a stress rating

only and functional operation of the device at these or other conditions beyond those indicated in the operational sections

of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

Table 32-1. Absolute maximum ratings.

32.1.2 General Operating Ratings

The device must operate within the ratings listed in Table 32-2 in order for all other electrical characteristics and typical

characteristics of the device to be valid.

Table 32-2. General operating conditions.

Table 32-3. Operating voltage and frequency.

Symbol Parameter Condition Min. Typ. Max. Units

VCC Power supply voltage -0.3 4 V

IVCC Current into a VCC pin 200

IGND Current out of a Gnd pin 200

VPIN Pin voltage with respect to Gnd and VCC -0.5 VCC+0.5 V

IPIN I/O pin sink/source current -25 25 mA

TAStorage temperature -65 150

°C

TjJunction temperature 150

Symbol Parameter Condition Min. Typ. Max. Units

VCC Power supply voltage 1.60 3.6

AVCC Analog supply voltage 1.60 3.6

TATemperature range -40 85

°C

TjJunction temperature -40 105

Symbol Parameter Condition Min. Typ. Max. Units

ClkCPU CPU clock frequency

VCC = 1.6V 012

MHz

VCC = 1.8V 012

VCC = 2.7V 032

VCC = 3.6V 032

XMEGA D4 [DATASHEET]

8315N–AVR–04/2013

The maximum CPU clock frequency depends on VCC. As shown in Figure 32-15 the Frequency vs. VCC curve is linear

between 1.8V < VCC <2.7V.

Figure 32-1. Maximum Frequency vs. VCC.

1.8

MHz

2.7 3.6

1.6

Safe Operating Area

XMEGA D4 [DATASHEET]

8315N–AVR–04/2013

32.1.3 Current consumption

Table 32-4. Current consumption for Active mode and sleep modes.

Notes: 1. All Power Reduction Registers set.

2. Maximum limits are based on characterization, and not tested in production.

Symbol Parameter Condition Min. Typ. Max. Units

ICC

Active power

consumption(1)

32kHz, Ext. Clk

VCC = 1.8V 40

µA

VCC = 3.0V 80

1MHz, Ext. Clk

VCC = 1.8V 200

VCC = 3.0V 410

2MHz, Ext. Clk

VCC = 1.8V 350 600

VCC = 3.0V

0.75 1.4

32MHz, Ext. Clk 7.5 12

Idle power

consumption(1)

32kHz, Ext. Clk

VCC = 1.8V 2.0

µA

VCC = 3.0V 2.8

1MHz, Ext. Clk

VCC = 1.8V 42

VCC = 3.0V 85

2MHz, Ext. Clk

VCC = 1.8V 85 225

VCC = 3.0V

170 350

32MHz, Ext. Clk 2.7 5.5 mA

Power-down power

consumption

T=25°C

VCC = 3.0V

0.1 1.0

µA

T=85°C 2.0 4.5

WDT and sampled BOD enabled,

T=25°C

VCC = 3.0V

1.4 3.0

WDT and sampled BOD enabled,

T = 85°C 3.0 6.0

Power-save power

consumption(2)

RTC from ULP clock, WDT and

sampled BOD enabled, T = 25°C

VCC = 1.8V 1.5

VCC = 3.0V 1.5

RTC from 1.024kHz low power

32.768kHz TOSC, T = 25°C

VCC = 1.8V 0.6 2.0

VCC = 3.0V 0.7 2.0

RTC from low power 32.768kHz

TOSC, T = 25°C

VCC = 1.8V 0.8 3.0

VCC = 3.0V 1.0 3.0

Reset power consumption Current through RESET pin

substracted VCC = 3.0V 300

XMEGA D4 [DATASHEET]

8315N–AVR–04/2013

Table 32-5. Current consumption for modules and peripherals.

Note: 1. All parameters measured as the difference in current consumption between module enabled and disabled. All data at VCC = 3.0V, ClkSYS = 1MHz external clock

without prescaling, T = 25°C unless other conditions are given.

Symbol Parameter Condition(1) Min. Typ. Max. Units

ICC

ULP oscillator 0.8

µA

32.768kHz int. oscillator 29

2MHz int. oscillator

DFLL enabled with 32.768kHz int. osc. as reference 115

32MHz int. oscillator

245

DFLL enabled with 32.768kHz int. osc. as reference 410

PLL 20x multiplication factor,

32MHz int. osc. DIV4 as reference 290

Watchdog timer 1.0

BOD

Continuous mode 138

Sampled mode, includes ULP oscillator 1.2

Internal 1.0V reference 175

Temperature sensor 170

ADC

16ksps

VREF = Ext ref

1.2

CURRLIMIT = LOW 1.0

CURRLIMIT = MEDIUM 0.9

CURRLIMIT = HIGH 0.8

75ksps

VREF = Ext ref CURRLIMIT = LOW 1.7

200ksps

VREF = Ext ref 3.1

USART Rx and Tx enabled, 9600 BAUD 11 µA

Flash memory and EEPROM programming 4mA

XMEGA D4 [DATASHEET]

8315N–AVR–04/2013

32.1.4 Wake-up time from sleep modes

Table 32-6. Device wake-up time from sleep modes with various system clock sources.

Note: 1. The wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see Figure 32-2. All peripherals and modules start

execution from the first clock cycle, expect the CPU that is halted for four clock cycles before program execution starts.

Figure 32-2. Wake-up time definition.

Symbol Parameter Condition Min. Typ.(1) Max. Units

twakeup

Wake-up time from idle,

standby, and extended standby

mode

External 2MHz clock 2.0

µs

32.768kHz internal oscillator 120

2MHz internal oscillator 2.0

32MHz internal oscillator 0.2

Wake-up time from power-save

and power-down mode

External 2MHz clock 5.0

32.768kHz internal oscillator 320

2MHz internal oscillator 9.0

32MHz internal oscillator 5.0

Wakeup request

Clock output

Wakeup time

XMEGA D4 [DATASHEET]

8315N–AVR–04/2013

32.1.5 I/O Pin Characteristics

The I/O pins complies with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output

voltage limits reflect or exceed this specification.

Table 32-7. I/O pin characteristics.

Notes: 1. The sum of all IOH for PORTA and PORTB must not exceed 100mA.

The sum of all IOH for PORTC, PORTD, PORTE must for each port not exceed 200mA.

The sum of all IOH for pins PF[0-5] on PORTF must not exceed 200mA.

The sum of all IOL for pins PF[6-7] on PORTF, PORTR and PDI must not exceed 100mA.

2. The sum of all IOL for PORTA and PORTB must not exceed 100mA.

The sum of all IOL for PORTC, PORTD, PORTE must for each port not exceed 200mA.

The sum of all IOL for pins PF[0-5] on PORTF must not exceed 200mA.

The sum of all IOL for pins PF[6-7] on PORTF, PORTR and PDI must not exceed 100mA.

Symbol Parameter Condition Min. Typ. Max. Units

IOH (1)/

IOL (2) I/O pin source/sink current -20 20 mA

VIH High level input voltage

VCC = 2.4 - 3.6V 0.7*Vcc VCC+0.5

VCC = 1.6 - 2.4V 0.8*VCC VCC+0.5

VIL Low level input voltage

VCC = 2.4- 3.6V -0.5 0.3*VCC

VCC = 1.6 - 2.4V -0.5 0.2*VCC

VOH High level output voltage

VCC = 3.3V IOH = -4mA 2.6 2.9

VCC = 3.0V IOH = -3mA 2.1 2.7

VCC = 1.8V IOH = -1mA 1.4 1.6

VOL Low level output voltage

VCC = 3.3V IOL = 8mA 0.4 0.76

VCC = 3.0V IOL = 5mA 0.3 0.64

VCC = 1.8V IOL = 3mA 0.2 0.46

IIN Input leakage current I/O pin T = 25°C <0.01 1µA

RPPull/buss keeper resistor 25 kΩ

XMEGA D4 [DATASHEET]

8315N–AVR–04/2013

32.1.6 ADC characteristics

Table 32-8. Power supply, reference and input range.

Table 32-9. Clock and timing.

Symbol Parameter Condition Min. Typ. Max. Units

AVCC Analog supply voltage VCC- 0.3 VCC+ 0.3

VREF Reference voltage 1AVCC- 0.6

Rin Input resistance Switched 4.5 kΩ

Cin Input capacitance Switched 5pF

RAREF Reference input resistance (leakage only) >10 MΩ

CAREF Reference input capacitance Static load 7pF

Vin

Input range 0 VREF

VConversion range Differential mode, Vinp - Vinn -VREF VREF

Conversion range Single ended unsigned mode, Vinp -ΔV VREF-ΔV

Symbol Parameter Condition Min. Typ. Max. Units

ClkADC ADC clock frequency

Maximum is 1/4 of peripheral clock

frequency 100 1800

kHz

Measuring internal signals 125

fClkADC Sample rate

300

ksps

fADC Sample rate

Current limitation (CURRLIMIT) off 300

CURRLIMIT = LOW 250

CURRLIMIT = MEDIUM 150

CURRLIMIT = HIGH 50

Sampling time Configurable in steps of 1/2 ClkADC cycles

up to 32 ClkADC cycles 0.28 320 µs

Conversion time (latency) (RES+1)/2 + GAIN

RES (Resolution) = 8 or 12, GAIN=0 to 3 4.5 10

ClkADC

cyclesStart-up time ADC clock cycles 12 24

ADC settling time After changing reference or input mode 7 7

XMEGA D4 [DATASHEET]

8315N–AVR–04/2013

Table 32-10. Accuracy characteristics.

Notes: 1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range.

2. Unless otherwise noted all linearity, offset and gain error numbers are valid under the condition that external VREF is used.

Symbol Parameter Condition(2) Min. Typ. Max. Units

RES Resolution 12-bit resolution

Differential 812 12

BitsSingle ended signed 711 11

Single ended unsigned 812 12

INL(1) Integral non-linearity

Differential mode

16ksps, VREF = 3V 0.5 1

lsb

16ksps, all VREF 0.8 2

200ksps, VREF = 3V 0.6 1

200ksps, all VREF 1 2

Single ended

unsigned mode

16ksps, VREF = 3.0V 0.5 1

16ksps, all VREF 1.3 2

DNL(1) Differential non-linearity

Differential mode

16ksps, VREF = 3V 0.3 1

16ksps, all VREF 0.5 1

200ksps, VREF = 3V 0.35 1

200ksps, all VREF 0.5 1

Single ended

unsigned mode

16ksps, VREF = 3.0V 0.6 1

16ksps, all VREF 0.6 1

Offset Error Differential mode

8mV

Temperature drift 0.01 mV/K

Operating voltage drift 0.25 mV/V

Gain Error

Differential mode

External reference -5

AVCC/1.6 -5

AVCC/2.0 -6

Bandgap ±10

Temperature drift 0.02 mV/K

Operating voltage drift 2mV/V

Single ended

unsigned mode

External reference -8

AVCC/1.6 -8

AVCC/2.0 -8

Bandgap ±10

Temperature drift 0.03 mV/K

Operating voltage drift 2mV/V

XMEGA D4 [DATASHEET]

8315N–AVR–04/2013

Table 32-11. Gain stage characteristics.

32.1.7 Analog Comparator Characteristics

Table 32-12. Analog Comparator characteristics.

Rin Input resistance Switched in normal mode 4.0 kΩ

Csample Input capacitance Switched in normal mode 4.4 pF

Signal range Gain stage output 0AVCC- 0.6 V

Propagation delay ADC conversion rate 1/2 1 3 ClkADC

cycles

Clock frequency Same as ADC 100 1800 kHz

Gain Error

0.5x gain, normal mode -1

1x gain, normal mode -1

8x gain, normal mode -1

64x gain, normal mode 10

Offset Error,

input referred

0.5x gain, normal mode 10

1x gain, normal mode 5

8x gain, normal mode -20

64x gain, normal mode -150

Symbol Parameter Condition Min. Typ. Max. Units

Voff Input offset voltage VCC=1.6V - 3.6V <±10 mV

Ilk Input leakage current VCC=1.6V - 3.6V <1 nA

Input voltage range -0.1 AVCC V

AC startup time 100 µs

Vhys1 Hysteresis, none VCC=1.6V - 3.6V 0

mVVhys2 Hysteresis, small VCC=1.6V - 3.6V 11

Vhys3 Hysteresis, large VCC=1.6V - 3.6V 26

tdelay Propagation delay

VCC = 3.0V, T= 85°C 16 90

VCC=1.6V - 3.6V 16

64-level voltage scaler Integral non-linearity (INL) 0.3 0.5 lsb

XMEGA D4 [DATASHEET]

8315N–AVR–04/2013

32.1.8 Bandgap and Internal 1.0V Reference Characteristics

Table 32-13. Bandgap and Internal 1.0V reference characteristics.

32.1.9 Brownout Detection Characteristics

Table 32-14. Brownout detection characteristics(1).

Note: 1. BOD is calibrated at 85°C within BOD level 0 values, and BOD level 0 is the default level.

32.1.10 External Reset Characteristics

Table 32-15. External reset characteristics.

Symbol Parameter Condition Min. Typ. Max. Units

Startup time

As reference for ADC 1 ClkPER + 2.5µs

µs

As input voltage to ADC and AC 1.5

Bandgap voltage 1.1

INT1V Internal 1.00V reference T= 85°C, after calibration 0.98 11.02

Variation over voltage and temperature Calibrated at T= 85°C, VCC = 3.0V ±1.0 %

Symbol Parameter Condition Min. Typ. Max. Units

VBOT

BOD level 0 falling VCC 1.50 1.62 1.75

BOD level 1 falling VCC 1.8

BOD level 2 falling VCC 2.0

BOD level 3 falling VCC 2.2

BOD level 4 falling VCC 2.4

BOD level 5 falling VCC 2.6

BOD level 6 falling VCC 2.8

BOD level 7 falling VCC 3.0

tBOD Detection time

Continuous mode 0.4

µs

Sampled mode 1000

VHYST Hysteresis 1.2 %

Symbol Parameter Condition Min. Typ. Max. Units

tEXT Minimum reset pulse width 1000 90 ns

VRST

Reset threshold voltage (VIH)

VCC = 2.7 - 3.6V 0.6*VCC

VCC = 1.6 - 2.7V 0.6*VCC

Reset threshold voltage (VIL)

VCC = 2.7 - 3.6V 0.5*VCC

VCC = 1.6 - 2.7V 0.4*VCC

RRST Reset pin pull-up resistor 25 kΩ

XMEGA D4 [DATASHEET]

8315N–AVR–04/2013

32.1.11 Power-on Reset Characteristics

Table 32-16. Power-on reset characteristics.

Note: 1. VPOT- values are only valid when BOD is disabled. When BOD is enabled VPOT- = VPOT+.

32.1.12 Flash and EEPROM Memory Characteristics

Table 32-17. Endurance and data retention.

Table 32-18. Programming time.

Notes: 1. Programming is timed from the 2MHz internal oscillator.

2. EEPROM is not erased if the EESAVE fuse is programmed.

Symbol Parameter Condition Min. Typ. Max. Units

VPOT- (1) POR threshold voltage falling VCC

VCC falls faster than 1V/ms 0.4 1.0

VVCC falls at 1V/ms or slower 0.8 1.0

VPOT+ POR threshold voltage rising VCC 1.3 1.59

Symbol Parameter Condition Min. Typ. Max. Units

Flash

Write/Erase cycles

25°C 10K

Cycle

85°C 10K

Data retention

25°C 100

Year

55°C 25

EEPROM

Write/Erase cycles

25°C 100K

Cycle

85°C 100K

Data retention

25°C 100

Year

55°C 25

Symbol Parameter Condition Min. Typ.(1) Max. Units

Chip erase(2) 16KB Flash, EEPROM 45

Flash

Page erase 4

Page write 4

Atomic page erase and write 8

EEPROM

Page erase 4

Page write 4

Atomic page erase and write 8

XMEGA D4 [DATASHEET]

8315N–AVR–04/2013

32.1.13 Clock and Oscillator Characteristics

32.1.13.1 Calibrated 32.768kHz Internal Oscillator characteristics

Table 32-19. 32.768kHz internal oscillator characteristics.

32.1.13.2 Calibrated 2MHz RC Internal Oscillator characteristics

Table 32-20. 2MHz internal oscillator characteristics.

32.1.13.3 Calibrated and tunable 32MHz internal oscillator characteristics

Table 32-21. 32MHz internal oscillator characteristics.

32.1.13.4 32kHz Internal ULP Oscillator characteristics

Table 32-22. 32kHz internal ULP oscillator characteristics.

Symbol Parameter Condition Min. Typ. Max. Units

Frequency 32.768 kHz

Factory calibration accuracy T = 85°C, VCC = 3.0V -0.5 0.5

User calibration accuracy -0.5 0.5

Symbol Parameter Condition Min. Typ. Max. Units

Frequency range DFLL can tune to this frequency over

voltage and temperature 1.8 2.2

MHz

Factory calibrated frequency 2.0

Factory calibration accuracy T = 85°C, VCC= 3.0V -1.5 1.5

%User calibration accuracy -0.2 0.2

DFLL calibration stepsize 0.18

Symbol Parameter Condition Min. Typ. Max. Units

Frequency range DFLL can tune to this frequency over

voltage and temperature 30 32 55

MHz

Factory calibrated frequency 32

Factory calibration accuracy T = 85°C, VCC= 3.0V -1.5 1.5

%User calibration accuracy -0.2 0.2

DFLL calibration step size 0.19

Symbol Parameter Condition Min. Typ. Max. Units

Factory calibrated frequency 32 kHz

Factory calibration accuracy T = 85°C, VCC= 3.0V -12 12

Accuracy -30 30

XMEGA D4 [DATASHEET]

8315N–AVR–04/2013

32.1.13.5 Internal Phase Locked Loop (PLL) characteristics

Table 32-23. Internal PLL characteristics.

Note: 1. The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency.

32.1.13.6 External clock characteristics

Figure 32-3. External clock drive waveform.

Table 32-24. External clock(1).

Notes: 1. System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded.

2. The maximum frequency vs. supply voltage is linear between 1.8V and 2.7V, and the same applies for all other parameters with supply voltage conditions.

Symbol Parameter Condition Min. Typ. Max. Units

fIN Input frequency Output frequency must be within fOUT 0.4 64

MHz

fOUT Output frequency (1) VCC= 1.6 - 1.8V 20 48

VCC= 2.7 - 3.6V 20 128

Start-up time 25

µs

Re-lock time 25

tCH

tCL

tCK

tCH

VIL1

VIH1

tCR tCF

Symbol Parameter Condition Min. Typ. Max. Units

1/tCK Clock frequency(2) VCC = 1.6 - 1.8V 090

MHz

VCC = 2.7 - 3.6V 0142

tCK Clock period

VCC = 1.6 - 1.8V 11

VCC = 2.7 - 3.6V 7.0

tCH/CL Clock high/low time

VCC = 1.6 - 1.8V 4.5

VCC = 2.7 - 3.6V 2.4

VIL/IH Low/high level input voltage See Table 32-7 on page 68 V

ΔtCK

Reduction in period time from one

clock cycle to the next 10 %

XMEGA D4 [DATASHEET]

8315N–AVR–04/2013

32.1.13.7 External 16MHz crystal oscillator and XOSC characteristics

Table 32-25. .External 16MHz crystal oscillator and XOSC characteristics.

Symbol Parameter Condition Min. Typ. Max. Units

Cycle to cycle jitter

XOSCPWR=0

FRQRANGE=0 0

FRQRANGE=1, 2, or 3 0

XOSCPWR=1 0

Long term jitter

XOSCPWR=0

FRQRANGE=0 0

FRQRANGE=1, 2, or 3 0

XOSCPWR=1 0

Frequency error

XOSCPWR=0

FRQRANGE=0 0.03

FRQRANGE=1 0.03

FRQRANGE=2 or 3 0.03

XOSCPWR=1 0.003

Duty cycle

XOSCPWR=0

FRQRANGE=0 50

FRQRANGE=1 50

FRQRANGE=2 or 3 50

XOSCPWR=1 50

RQNegative impedance

XOSCPWR=0,

FRQRANGE=0

0.4MHz resonator,

CL=100pF 44k

1MHz crystal, CL=20pF 67k

2MHz crystal, CL=20pF 67k

XOSCPWR=0,

FRQRANGE=1,

CL=20pF

2MHz crystal 82k

8MHz crystal 1500

9MHz crystal 1500

XOSCPWR=0,

FRQRANGE=2,

CL=20pF

8MHz crystal 2700

9MHz crystal 2700

12MHz crystal 1000

XOSCPWR=0,

FRQRANGE=3,

CL=20pF

9MHz crystal 3600

12MHz crystal 1300

16MHz crystal 590

XOSCPWR=1,

FRQRANGE=0,

CL=20pF

9MHz crystal 390

12MHz crystal 50

16MHz crystal 10

XMEGA D4 [DATASHEET]

8315N–AVR–04/2013

32.1.13.8 External 32.768kHz crystal oscillator and TOSC characteristics

Table 32-26. External 32.768kHz crystal oscillator and TOSC characteristics.

Note: See Figure 32-4 for definition.

RQNegative impedance

XOSCPWR=1,

FRQRANGE=1,

CL=20pF

9MHz crystal 1500

12MHz crystal 650

16MHz crystal 270

XOSCPWR=1,

FRQRANGE=2,

CL=20pF

12MHz crystal 1000

16MHz crystal 440

XOSCPWR=1,

FRQRANGE=3,

CL=20pF

12MHz crystal 1300

16MHz crystal 590

ESR SF = safety factor min(RQ)/SF kΩ

Start-up time

XOSCPWR=0,

FRQRANGE=0

0.4MHz resonator,

CL=100pF 1.0

XOSCPWR=0,

FRQRANGE=1 2MHz crystal, CL=20pF 2.6

XOSCPWR=0,

FRQRANGE=2 8MHz crystal, CL=20pF 0.8

XOSCPWR=0,

FRQRANGE=3 12MHz crystal, CL=20pF 1.0

XOSCPWR=1,

FRQRANGE=3 16MHz crystal, CL=20pF 1.4

CXTAL1

Parasitic capacitance

XTAL1 pin 5.9

CXTAL2

Parasitic capacitance

XTAL2 pin 8.3

CLOAD Parasitic capacitance load 3.5

Symbol Parameter Condition Min. Typ. Max. Units

ESR/R1 Recommended crystal equivalent

series resistance (ESR)

Crystal load capacitance 6.5pF 60

kΩ

Crystal load capacitance 9.0pF 35

Crystal load capacitance 12pF 28

CTOSC1 Parasitic capacitance TOSC1 pin 3.5

CTOSC2 Parasitic capacitance TOSC2 pin 3.5

Recommended safety factor capacitance load matched to

crystal specification 3

XMEGA D4 [DATASHEET]

8315N–AVR–04/2013

Figure 32-4. TOSC input capacitance.

The parasitic capacitance between the TOSC pins is CL1 + CL2 in series as seen from the crystal when oscillating without

external capacitors.

32.1.14 SPI Characteristics

Figure 32-5. SPI timing requirements in master mode.

2CS

TDevice internal

External

32.768kHz crystal

MSB LSB

BSLBSM

MOS

MIS

MIH

SCKW

SCK

MOH

SCKF

SCKR

SCKW

MOSI

(Data Output)

MISO

(Data Input)

SCK

(CPOL = 1)

SCK

(CPOL = 0)

XMEGA D4 [DATASHEET]

8315N–AVR–04/2013

Figure 32-6. SPI timing requirements in slave mode.

MSB LSB

BSLBSM

SIS

SIH

SSCKW

SSCK

SSH

SOSSH

SCKR

SCKF

SOS

SSS

SOSSS

MISO

(Data Output)

MOSI

(Data Input)

SCK

(CPOL = 1)

SCK

(CPOL = 0)

XMEGA D4 [DATASHEET]

8315N–AVR–04/2013

Table 32-27. SPI timing characteristics and requirements.

32.1.15 Two-Wire Interface Characteristics

Table 32-28 describes the requirements for devices connected to the Two-Wire Interface Bus. The Atmel AVR XMEGA

Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 32-

21.

Figure 32-7. Two-wire interface bus timing.

Symbol Parameter Condition Min. Typ. Max. Units

tSCK SCK period Master (See Table 20-3 in

XMEGA C Manual)

tSCKW SCK high/low width Master 0.5*SCK

tSCKR SCK rise time Master 2.7

tSCKF SCK fall time Master 2.7

tMIS MISO setup to SCK Master 10

tMIH MISO hold after SCK Master 10

tMOS MOSI setup SCK Master 0.5*SCK

tMOH MOSI hold after SCK Master 1

tSSCK Slave SCK Period Slave 4*t ClkPER

tSSCKW SCK high/low width Slave 2*t ClkPER

tSSCKR SCK rise time Slave 1600

tSSCKF SCK fall time Slave 1600

tSIS MOSI setup to SCK Slave 3

tSIH MOSI hold after SCK Slave tClk

PER

tSSS SS setup to SCK Slave 21

tSSH SS hold after SCK Slave 20

tSOS MISO setup SCK Slave 8

tSOH MISO hold after SCK Slave 13

tSOSS MISO setup after SS low Slave 11

tSOSH MISO hold after SS high Slave 8

HD;STA

SDA

SCL

LOW

HIGH

SU;STA

BUF

HD;DAT

SU;DAT

SU;STO

XMEGA D4 [DATASHEET]

8315N–AVR–04/2013

Table 32-28. Two-wire interface characteristics.

Notes: 1. Required only for fSCL > 100kHz.

2. Cb = Capacitance of one bus line in pF.

3. fPER = Peripheral clock frequency.

Symbol Parameter Condition Min. Typ. Max. Units

VIH Input high voltage 0.7VCC VCC+0.5

VIL Input low voltage -0.5 0.3VCC

Vhys Hysteresis of Schmitt trigger inputs 0.05VCC (1)

VOL Output low voltage 3mA, sink current 00.4

trRise time for both SDA and SCL 20+0.1Cb (1)(2) 300

nstof Output fall time from VIHmin to VILmax 10pF < Cb < 400pF (2) 20+0.1Cb (1)(2) 250

tSP Spikes suppressed by input filter 050

IIInput current for each I/O Pin 0.1VCC < VI < 0.9VCC -10 10 µA

CICapacitance for each I/O Pin 10 pF

fSCL SCL clock frequency fPER (3)>max(10fSCL, 250kHz) 0400 kHz

RPValue of pull-up resistor

fSCL ≤ 100kHz

fSCL > 100kHz

tHD;STA Hold time (repeated) START condition

fSCL ≤ 100kHz 4.0

µs

fSCL > 100kHz 0.6

tLOW Low period of SCL clock

fSCL ≤ 100kHz 4.7

fSCL > 100kHz 1.3

tHIGH High period of SCL clock

fSCL ≤ 100kHz 4.0

fSCL > 100kHz 0.6

tSU;STA

Set-up time for a repeated START

condition

fSCL ≤ 100kHz 4.7

fSCL > 100kHz 0.6

tHD;DAT Data hold time

fSCL ≤ 100kHz 03.45

µs

fSCL > 100kHz 00.9

tSU;DAT Data setup time

fSCL ≤ 100kHz 250

fSCL > 100kHz 100

tSU;STO Setup time for STOP condition

fSCL ≤ 100kHz 4.0

fSCL > 100kHz 0.6

tBUF

Bus free time between a STOP and

START condition

fSCL ≤ 100kHz 4.7

fSCL > 100kHz 1.3

VCC 0.4V–

3mA

----------------------------

100ns

---------------

300ns

---------------

XMEGA D4 [DATASHEET]

8315N–AVR–04/2013

32.2 ATxmega32D4

32.2.1 Absolute Maximum Ratings

Stresses beyond those listed in Table 32-29 under may cause permanent damage to the device. This is a stress rating

only and functional operation of the device at these or other conditions beyond those indicated in the operational sections

of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

Table 32-29. Absolute maximum ratings.

32.2.2 General Operating Ratings

The device must operate within the ratings listed in Table 32-30 in order for all other electrical characteristics and typical

characteristics of the device to be valid.

Table 32-30. General operating conditions.

Table 32-31. Operating voltage and frequency.

The maximum CPU clock frequency depends on VCC. As shown in Figure 32-8 the Frequency vs. VCC curve is linear

between 1.8V < VCC <2.7V.

Symbol Parameter Condition Min. Typ. Max. Units

VCC Power supply voltage -0.3 4 V

IVCC Current into a VCC pin 200

IGND Current out of a Gnd pin 200

VPIN

Pin voltage with respect to Gnd

and VCC

-0.5 VCC+0.5 V

IPIN I/O pin sink/source current -25 25 mA

TAStorage temperature -65 150

°C

TjJunction temperature 150

Symbol Parameter Condition Min. Typ. Max. Units

VCC Power supply voltage 1.60 3.6

AVCC Analog supply voltage 1.60 3.6

TATemperature range -40 85

°C

TjJunction temperature -40 105

Symbol Parameter Condition Min. Typ. Max. Units

ClkCPU CPU clock frequency

VCC = 1.6V 012

MHz

VCC = 1.8V 012

VCC = 2.7V 032

VCC = 3.6V 032

XMEGA D4 [DATASHEET]

8315N–AVR–04/2013

Figure 32-8. Maximum Frequency vs. VCC.

1.8

MHz

2.7 3.6

1.6

Safe Operating Area

XMEGA D4 [DATASHEET]

8315N–AVR–04/2013

32.2.3 Current consumption

Table 32-32. Current consumption for Active mode and sleep modes.

Notes: 1. All Power Reduction Registers set.

2. Maximum limits are based on characterization, and not tested in production.

Symbol Parameter Condition Min. Typ. Max. Units

ICC

Active power

consumption(1)

32kHz, Ext. Clk

VCC = 1.8V 40

µA

VCC = 3.0V 80

1MHz, Ext. Clk

VCC = 1.8V 200

VCC = 3.0V 410

2MHz, Ext. Clk

VCC = 1.8V 350 600

VCC = 3.0V

0.75 1.4

32MHz, Ext. Clk 7.5 12

Idle power

consumption(1)

32kHz, Ext. Clk

VCC = 1.8V 2.0

µA

VCC = 3.0V 2.8

1MHz, Ext. Clk

VCC = 1.8V 42

VCC = 3.0V 85

2MHz, Ext. Clk

VCC = 1.8V 85 225

VCC = 3.0V

170 350

32MHz, Ext. Clk 2.7 5.5 mA

Power-down power

consumption

T=25°C

VCC = 3.0V

0.1 1.0

µA

T=85°C 2.0 4.5

WDT and sampled BOD enabled,

T=25°C

VCC = 3.0V

1.4 3.0

WDT and sampled BOD enabled,

T = 85°C 3.0 6.0

Power-save power

consumption(2)

RTC from ULP clock, WDT and

sampled BOD enabled, T = 25°C

VCC = 1.8V 1.5

VCC = 3.0V 1.5

RTC from 1.024kHz low power

32.768kHz TOSC, T = 25°C

VCC = 1.8V 0.6 2.0

VCC = 3.0V 0.7 2.0

RTC from low power 32.768kHz

TOSC, T = 25°C

VCC = 1.8V 0.8 3.0

VCC = 3.0V 1.0 3.0

Reset power consumption Current through RESET pin

substracted VCC = 3.0V 300

XMEGA D4 [DATASHEET]

8315N–AVR–04/2013

Table 32-33. Current consumption for modules and peripherals.

Note: 1. All parameters measured as the difference in current consumption between module enabled and disabled. All data at VCC = 3.0V, ClkSYS = 1MHz external clock

without prescaling, T = 25°C unless other conditions are given.

Symbol Parameter Condition(1) Min. Typ. Max. Units

ICC

ULP oscillator 0.8

µA

32.768kHz int. oscillator 29

2MHz int. oscillator

DFLL enabled with 32.768kHz int. osc. as reference 115

32MHz int. oscillator

245

DFLL enabled with 32.768kHz int. osc. as reference 410

PLL 20x multiplication factor,

32MHz int. osc. DIV4 as reference 290

Watchdog timer 1.0

BOD

Continuous mode 138

Sampled mode, includes ULP oscillator 1.2

Internal 1.0V reference 175

Temperature sensor 170

ADC

16ksps

VREF = Ext ref

1.2

CURRLIMIT = LOW 1.0

CURRLIMIT = MEDIUM 0.9

CURRLIMIT = HIGH 0.8

75ksps

VREF = Ext ref CURRLIMIT = LOW 1.7

200ksps

VREF = Ext ref 3.1

USART Rx and Tx enabled, 9600 BAUD 11 µA

Flash memory and EEPROM programming 4mA

XMEGA D4 [DATASHEET]

8315N–AVR–04/2013

32.2.4 Wake-up time from sleep modes

Table 32-34. Device wake-up time from sleep modes with various system clock sources.

Note: 1. The wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see Figure 32-9. All peripherals and modules start

execution from the first clock cycle, expect the CPU that is halted for four clock cycles before program execution starts.

Figure 32-9. Wake-up time definition.

Symbol Parameter Condition Min. Typ. (1) Max. Units

twakeup

Wake-up time from idle,

standby, and extended standby

mode

External 2MHz clock 2.0

µs

32.768kHz internal oscillator 120

2MHz internal oscillator 2.0

32MHz internal oscillator 0.2

Wake-up time from power-save

and power-down mode

External 2MHz clock 5.0

32.768kHz internal oscillator 320

2MHz internal oscillator 9.0

32MHz internal oscillator 5.0

Wakeup request

Clock output

Wakeup time

XMEGA D4 [DATASHEET]

8315N–AVR–04/2013

32.2.5 I/O Pin Characteristics

The I/O pins complies with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output

voltage limits reflect or exceed this specification.

Table 32-35. I/O pin characteristics.