33 × 17, 3.2 Gbps
Digital Crosspoint Switch
AD8151
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
FEATURES
Low cost
33 × 17, fully differential, nonblocking array
3.2 Gbps per port NRZ data rate
Wide power supply range: +3.3 V, –3.3 V
Low power
425 mA (outputs enabled)
35 mA (outputs disabled)
LV PECL- and LV ECL-compatible
CMOS/TTL-level control inputs: 3 V to 5 V
Low jitter
No heat sinks required
Drives a backplane directly
Programmable output current
Optimize termination impedance
User-controlled voltage at the load
Minimize power dissipation
Individual output disable for busing and reducing power
Double row latch
Buffered inputs
184-lead LQFP package
APPLICATIONS
High speed serial backplane routing to Sonet OC-48
applications with FEC
Fiber optic network switching
Fiber channel
LVDS
FUNCTIONAL BLOCK DIAGRAM
OUTP
OUTN
INP INN
CS
RE
WE
D
A
UPDATE
RESET
FIRST
RANK
17
×
7-BIT
LATCH
SECOND
RANK
17
×
7-BIT
LATCH
INPUT
DECODERS
OUTPUT
ADDRESS
DECODER
33
×
17
DIFFERENTIAL
SWITCH
MATRIX
17
17
33 33
7
5
AD8151
02169-001
Figure 1.
.
GENERAL DESCRIPTION
The AD81511 is a member of the Xstream line of products,
offering a breakthrough in digital switching and a large switch
array (33 × 17) on very little power—typically less than 1.5 W.
It also operates at data rates in excess of 3.2 Gbps per port,
making it suitable for Sonet OC-48 applications with
8/10-bit forward-error correction (FEC). Furthermore, the
price of the AD8151 makes it affordable enough to be used for
lower data rates. The AD8151’s flexible supply voltages allow
the user to operate with either emitter-coupled logic (ECL) or
positive emitter-coupled logic (PECL) data levels, and with 3.3
V for further power reduction. The control interface is CMOS-
/TTL-compatible (3 V to 5 V).
Its fully differential signal path reduces jitter and crosstalk,
while allowing the use of smaller, single-ended voltage swings.
The AD8151 is offered in a 184-lead LQFP package that
operates over the extended commercial temperature range
of 0°C to 85°C.
02169-002
70ps/DIV
150mV/DIV
Figure 2. Eye Pattern, 3.2 Gbps, PRBS 23
1 Patent pending.
AD8151
Rev. B | Page 2 of 40
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Maximum Power Dissipation ..................................................... 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Typical Performance Characteristics ............................................. 9
Control Interface Truth Tables...................................................... 13
Control Interface Timing Diagrams ............................................ 14
Control Interface Programming Example .............................. 16
Control Interface ............................................................................ 17
Control Pin Description............................................................ 17
Control Interface Translators.................................................... 18
Circuit Description......................................................................... 19
Applications..................................................................................... 23
Input and Output Busing .......................................................... 23
Evaluation Board........................................................................ 23
Power Supplies............................................................................ 24
Configuration Programming.................................................... 25
Software Installation .................................................................. 25
Software Operation.................................................................... 26
Outline Dimensions ....................................................................... 38
Ordering Guide .......................................................................... 38
REVISION HISTORY
12/05—Rev. A to Rev. B
Changes to Table 1............................................................................ 3
Changes to Figure 4.......................................................................... 5
Changes to Table 3............................................................................ 6
Changes to Table 4.......................................................................... 13
Changes to Figure 51...................................................................... 35
Changes to Ordering Guide .......................................................... 38
9/05—Rev. 0 to Rev. A
Updated Format..............................................................Universal
Change to Figure 51 ................................................................... 34
Change to Ordering Guide........................................................ 37
4/01—Revision 0: Initial Version
AD8151
Rev. B | Page 3 of 40
SPECIFICATIONS
@ 25°C, VCC = 3.3 V to 5 V, VEE = 0 V, RL = 50 Ω (see Figure 26), IOUT = 16 mA, unless otherwise noted.
Table 1.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
Max Data Rate/Channel (NRZ) 2.5 3.2 Gbps
Channel Jitter Data rate = 3.2 Gbps 52 ps p-p
RMS Channel Jitter 8 ps
Propagation Delay Input to output 650 ps
Propagation Delay Match See Figure 23 ±50 ±100 ps
Output Rise/Fall Time 20% to 80% 100 ps
INPUT CHARACTERISTICS
Input Voltage Swing Single-ended (see Figure 18) 200 1000 mV p-p
Input Bias Current 2 μA
Input Capacitance 2 pF
Input VIN High VCC − 1.2 V
CC V
Input VIN Low VCC − 2.4 VCC − 1.4 V
OUTPUT CHARACTERISTICS
Output Voltage Swing Differential 800 mV p-p
Output Voltage Range (See Figure 19) VCC − 1.8 V
CC V
Output Current 5 25 mA
Output Capacitance 2 pF
Output VOUT High VCC − 1.8 V
Output VOUT Low VCC V
POWER SUPPLY
Operating Range
PECL, VCC V
EE = 0 V 3.0 5.25 V
ECL, VEE V
CC = 0 V –5.25 –3.0 V
VDD 3 5 V
VSS 0 V
Quiescent Current
VDD 2 mA
VEE All outputs enabled, IOUT = 16 mA 425 mA
T
MIN to TMAX 450 mA
All outputs disabled 35 mA
THERMAL CHARACTERISTICS
Operating Temperature Range 0 85 °C
θJA 30 °C/W
LOGIC INPUT CHARACTERISTICS VDD = 3 V dc to 5 V dc
Input VIN High 1.9 VDD V
Input VIN Low 0 0.9 V
AD8151
Rev. B | Page 4 of 40
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 2.
Parameter Rating
Supply Voltage
VDD − VEE 10.5 V
VCC − VEE 5.5 V
VDD − VSS 5.5 V
VSS − VEE 5.5 V
VSS − VCC 5.5 V
VDD − VCC 5.5 V
Internal Power Dissipation
184-Lead LQFP (ST-184) 4.2 W
Differential Input Voltage 2.0 V
Storage Temperature Range –65°C to +125°C
Lead Temperature (Soldering 10 sec) 300°C
Junction Temperature, θJA 30°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the
AD8151 is limited by the associated rise in junction
temperature. The maximum safe junction temperature for
plastic encapsulated devices is determined by the glass
transition temperature of the plastic, approximately 150°C.
Temporarily exceeding this limit may cause a shift in
parametric performance due to a change in the stresses exerted
on the die by the package. Exceeding a junction temperature of
175°C for an extended period can result in device failure. To
ensure proper operation, it is necessary to observe the
maximum power derating curves shown in Figure 3.
6
1
2
3
4
5
–10 9080706050403020100
02169-003
AMBIENT TEMPERATURE (°C)
MAXIMUM POWER DISSIPATION (W)
T
J
= 150°C
Figure 3.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD8151
Rev. B | Page 5 of 40
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
184
183
182
181
180
179
178
177
176
175
174
173
171
170
169
168
167
166
165
164
163
162
172
161
160
159
157
156
155
154
153
152
158
151
150
149
147
146
145
144
143
142
141
140
139
148
59
60
61
62
63
64
65
66
67
68
47
48
49
50
51
52
53
54
55
56
57
58
69
70
71
72
74
75
76
77
78
73
79
80
81
82
84
85
86
87
83
88
89
90
91
92
5
4
3
2
7
6
9
8
1
14
13
12
11
16
15
17
10
19
18
23
22
21
20
25
24
27
26
29
28
32
31
30
34
33
36
35
40
39
38
37
41
43
42
45
44
46
IN20P
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
A0
V
EE
A1
V
CC
V
EE
IN19N
IN19P
IN18N
IN18P
IN17N
IN17P
IN16N
IN16P
RESET
CS
RE
WE
UPDATE
A0
A1
A2
A3
A4
D0
D1
D2
D3
D4
D5
D6
REF
IN15N
IN15P
IN14N
IN14P
IN13N
IN13P
V
EE
V
EE
V
EE
V
EE
V
EE
V
SS
V
CC
V
EE
V
EE
V
EE
V
EE
V
EE
REF
V
CC
V
DD
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
A16
V
CC
IN20N
IN21P
IN21N
IN22P
IN22N
IN23P
IN23N
IN24P
IN24N
IN25P
IN25N
IN26P
IN26N
IN27P
IN27N
IN28P
IN28N
IN29P
IN29N
IN30P
IN30N
IN31P
IN31N
IN32P
IN32N
OUT16N
OUT16P
IN12N
IN12P
IN11N
IN11P
IN10N
IN10P
IN09N
IN09P
IN08N
IN08P
IN07N
IN07P
IN06N
IN06P
IN05N
IN05P
IN04N
IN04P
IN03N
IN03P
IN02N
IN02P
IN01N
IN01P
IN00N
IN00P
OUT00P
OUT00N
122
137
138
132
133
134
135
130
131
129
136
127
128
123
124
125
126
120
121
118
119
116
117
113
114
115
111
112
109
110
108
105
106
107
104
102
103
100
101
95
96
97
98
99
93
94
PIN 1
INDICATOR
AD8151
184L LQFP
TOP VIEW
(Not to Scale)
OUT15N
OUT15P
OUT14N
OUT14P
OUT13N
OUT13P
OUT12N
OUT12P
OUT11N
OUT11P
OUT10N
OUT10P
OUT09N
OUT09P
OUT08N
OUT08P
OUT07N
OUT07P
OUT06N
OUT06P
OUT05N
OUT05P
OUT04N
OUT04P
OUT03N
OUT03P
OUT02N
OUT02P
OUT01N
OUT01P
V
EE
V
EE
A15
V
EE
A14
V
EE
A13
V
EE
A12
V
EE
A11
V
EE
A10
V
EE
A9
V
EE
A8
V
EE
A7
V
EE
A6
V
EE
A5
V
EE
A4
V
EE
A3
V
EE
A2
V
EE
02169-004
Figure 4. Pin Configuration
AD8151
Rev. B | Page 6 of 40
Table 3. Pin Function Descriptions
Pin No. Mnemonic Type Description
1, 4, 7, 10, 13, 16, 19, 22, 25, 28, 31,
34, 37, 40, 42, 46, 47, 92, 93, 99,
102, 105, 108, 111, 114, 117, 120,
123, 126, 129, 132, 135, 138, 139,
142, 145, 148, 172, 175, 178, 181,
184
VEE Power Supply Most Negative PECL Supply (Common with Other Points Labeled
VEE)
2 IN20P PECL/ECL High Speed Input
3 IN20N PECL/ECL High Speed Input Complement
5 IN21P PECL/ECL High Speed Input
6 IN21N PECL/ECL High Speed Input Complement
8 IN22P PECL/ECL High Speed Input
9 IN22N PECL/ECL High Speed Input Complement
11 IN23P PECL/ECL High Speed Input
12 IN23N PECL/ECL High Speed Input Complement
14 IN24P PECL/ECL High Speed Input
15 IN24N PECL/ECL High Speed Input Complement
17 IN25P PECL/ECL High Speed Input
18 IN25N PECL/ECL High Speed Input Complement
20 IN26P PECL/ECL High Speed Input
21 IN26N PECL/ECL High Speed Input Complement
23 IN27P PECL/ECL High Speed Input
24 IN27N PECL/ECL High Speed Input Complement
26 IN28P PECL/ECL High Speed Input
27 IN28N PECL/ECL High Speed Input Complement
29 IN29P PECL/ECL High Speed Input
30 IN29N PECL/ECL High Speed Input Complement
32 IN30P PECL/ECL High Speed Input
33 IN30N PECL/ECL High Speed Input Complement
35 IN31P PECL/ECL High Speed Input
36 IN31N PECL/ECL High Speed Input Complement
38 IN32P PECL/ECL High Speed Input
39 IN32N PECL/ECL High Speed Input Complement
41, 98, 149, 171 VCC Power Supply Most Positive PECL Supply (Common with Other Points Labeled VCC)
43 OUT16N PECL/ECL High Speed Output Complement
44 OUT16P PECL/ECL High Speed Output
45 VEEA16 Power Supply Most Negative PECL Supply (Unique to this Output)
48 OUT15N PECL/ECL High Speed Output Complement
49 OUT15P PECL/ECL High Speed Output
50 VEEA15 Power Supply Most Negative PECL Supply (Unique to this Output)
51 OUT14N PECL/ECL High Speed Output Complement
52 OUT14P PECL/ECL High Speed Output
53 VEEA14 Power Supply Most Negative PECL Supply (Unique to this Output)
54 OUT13N PECL/ECL High Speed Output Complement
55 OUT13P PECL/ECL High Speed Output
56 VEEA13 Power Supply Most Negative PECL Supply (Unique to this Output)
57 OUT12N PECL/ECL High Speed Output Complement
58 OUT12P PECL/ECL High Speed Output
59 VEEA12 Power Supply Most Negative PECL Supply (Unique to this Output)
60 OUT11N PECL/ECL High speed Output Complement
61 OUT11P PECL/ECL High speed Output
62 VEEA11 Power Supply Most Negative PECL Supply (Unique to this Output)
63 OUT10N PECL/ECL High Speed Output Complement
AD8151
Rev. B | Page 7 of 40
Pin No. Mnemonic Type Description
64 OUT10P PECL/ECL High Speed Output
65 VEEA10 Power Supply Most Negative PECL Supply (Unique to this Output)
66 OUT09N PECL/ECL High Speed Output Complement
67 OUT09P PECL/ECL High Speed Output
68 VEEA9 Power Supply Most Negative PECL Supply (Unique to this Output)
69 OUT08N PECL/ECL High speed Output Complement
70 OUT08P PECL/ECL High Speed Output
71 VEEA8 Power Supply Most Negative PECL Supply (Unique to this Output)
72 OUT07N PECL/ECL High Speed Output Complement
73 OUT07P PECL/ECL High Speed Output
74 VEEA7 Power Supply Most Negative PECL Supply (Unique to this Output)
75 OUT06N PECL/ECL High Speed Output Complement
76 OUT06P PECL/ECL High Speed Output
77 VEEA6 Power Supply Most Negative PECL Supply (Unique to this Output)
78 OUT05N PECL/ECL High Speed Output Complement
79 OUT05P PECL/ECL High Speed Output
80 VEEA5 Power Supply Most Negative PECL Supply (Unique to this Output)
81 OUT04N PECL/ECL High Speed Output Complement
82 OUT04P PECL/ECL High Speed Output
83 VEEA4 Power Supply Most Negative PECL Supply (Unique to this Output)
84 OUT03N PECL/ECL High Speed Output Complement
85 OUT03P PECL/ECL High Speed Output
86 VEEA3 Power Supply Most Negative PECL Supply (Unique to this Output)
87 OUT02N PECL/ECL High Speed Output Complement
88 OUT02P PECL/ECL High Speed Output
89 VEEA2 Power Supply Most Negative PECL Supply (Unique to this Output)
90 OUT01N PECL/ECL High Speed Output Complement
91 OUT01 P PECL/ECL High Speed Output
94 VEEA1 Power Supply Most Negative PECL Supply (Unique to this Output)
95 OUT00N PECL/ECL High Speed Output Complement
96 OUT00P PECL/ECL High Speed Output
97 VEEA0 Power Supply Most Negative PECL Supply (Unique to this Output)
100 IN00P PECL/ECL High Speed Input
101 IN00N PECL/ECL High Speed Input Complement
103 IN01P PECL/ECL High Speed Input
104 IN01N PECL/ECL High Speed Input Complement
106 IN02P PECL/ECL High Speed Input
107 IN02N PECL/ECL High Speed Input Complement
109 IN03P PECL/ECL High Speed Input
110 IN03N PECL/ECL High Speed Input Complement
112 IN04P PECL/ECL High Speed Input
113 IN04N PECL/ECL High Speed Input Complement
115 IN05P PECL/ECL High Speed Input
116 IN05N PECL/ECL High Speed Input Complement
118 IN06P PECL/ECL High Speed Input
119 IN06N PECL/ECL High Speed Input Complement
121 IN07P PECL/ECL High Speed Input
122 IN07N PECL/ECL High Speed Input Complement
124 IN08P PECL/ECL High Speed Input
125 IN08N PECL/ECL High Speed Input Complement
127 IN09P PECL/ECL High Speed Input
128 IN09N PECL/ECL High Speed Input Complement
AD8151
Rev. B | Page 8 of 40
Pin No. Mnemonic Type Description
130 IN10P PECL/ECL High Speed Input
131 IN10N PECL/ECL High Speed Input Complement
133 IN11P PECL/ECL High Speed Input
134 IN11N PECL/ECL High Speed Input Complement
136 IN12P PECL/ECL High Speed Input
137 IN12N PECL/ECL High Speed Input Complement
140 IN13P PECL/ECL High Speed Input
141 IN13N PECL/ECL High Speed Input Complement
143 IN14P PECL/ECL High Speed Input
144 IN14N PECL/ECL High Speed Input Complement
146 IN15P PECL/ECL High Speed Input
147 IN15N PECL/ECL High Speed Input Complement
150 VEEREF R Program Connection Point for Output Logic Pull-Down Programming Resistor
(Must be Connected to VEE)
151 REF R Program Connection Point for Output Logic Pull-Down Programming Resistor
152 VSS Power Supply Most Negative Control Logic Supply
153 D6 TTL Enable/Disable Output
154 D5 TTL Bit 32—MSB Input Select
155 D4 TTL Bit 16
156 D3 TTL Bit 8
157 D2 TTL Bit 4
158 D1 TTL Bit 2
159 D0 TTL Bit 1—LSB Input Select
160 A4 TTL Bit 16—MSB Output Select
161 A3 TTL Bit 8
162 A2 TTL Bit 4
163 A1 TTL Bit 2
164 A0 TTL Bit 1—LSB Output Select
165 UPDATE TTL Second Rank Program
166 WE TTL First Rank Program
167 RE TTL Enable Readback
168 CS TTL Enable Chip to Accept Programming
169 RESET TTL Disable All Outputs (Hi-Z)
170 VDD Power Supply Most Positive Control Logic Supply
173 IN16P PECL/ECL High Speed Input
174 IN16N PECL/ECL High Speed Input Complement
176 IN17P PECL/ECL High Speed Input
177 IN17N PECL/ECL High Speed Input Complement
179 IN18P PECL/ECL High Speed Input
180 IN18N PECL/ECL High Speed Input Complement
182 IN19P PECL/ECL High Speed Input
183 IN19N PECL/ECL High Speed Input Complement
AD8151
Rev. B | Page 9 of 40
TYPICAL PERFORMANCE CHARACTERISTICS
02169-005
100ps/DIV
150mV/DIV
Figure 5. Eye Pattern 2.5 Gbps, PRBS 23
02169-006
20ps/DIV
150mV/DIV
p-p = 43ps
STD DEV = 8ps
Figure 6. Jitter @ 2.5 Gbps, PRBS 23
100
90
80
70
60
50
40
30
20
10
0
0.5 3.53.02.52.01.51.0
02169-007
DATA RATE (Gbps)
EYE WIDTH (%)
% EYE WIDTH =
×
100
(CLOCK PERIOD – JITTER p-p)
CLOCK PERIOD
Figure 7. Eye Width vs. Data Rate, PRBS 23
02169-008
70ps/DIV
150mV/DIV
Figure 8. Eye Pattern 3.2 Gbps, PRBS 23
02169-009
20ps/DIV
150mV/DIV
p-p = 53ps
STD DEV = 8ps
Figure 9. Jitter @ 3.2 Gbps, PRBS 23
100
90
80
70
60
50
40
30
20
10
0
0.5 3.53.02.52.01.51.0
02169-010
DATA RATE (Gbps)
EYE HEIGHT (%)
% EYE HEIGHT =
×
100
(V
OUT
@ DATA RATE)
V
OUT
@ 0.5Gbps
Figure 10. Eye Height vs. Data Rate, PRBS 23
AD8151
Rev. B | Page 10 of 40
100
90
80
70
60
50
40
30
20
10
0
1.0 3.53.02.52.01.5
02169-011
DATA RATE (Gbps)
JITTER (ps)
PEAK-PEAK
JITTER
STANDARD DEVIATION
Figure 11. Jitter vs. Data Rate, PRBS 23
02169-012
100ps/DIV
150mV/DIV
p-p = 38ps
STD DEV = 7.7ps
Figure 12. Crosstalk, 2.5 Gbps, PRBS 23, Attack Signal Is Off
02169-013
100ps/DIV
150mV/DIV
p-p = 70ps
STD DEV = 8ps
Figure 13. Crosstalk, 2.5 Gbps, PRBS 23, Attack Signal Is On
100
90
80
70
60
50
40
30
20
10
0098070605040302010
02169-014
TEMPERATURE (
°
C)
JITTER (ps)
0
2.5Gbps STD DEV
3.2Gbps STD DEV
2.5Gbps JITTER
3.2Gbps JITTER
Figure 14. Jitter vs. Temperature, PRBS 23
02169-015
75ps/DIV
150mV/DIV
p-p = 32ps
STD DEV = 4.7ps
Figure 15. Crosstalk, 3.2 Gbps, PRBS 23, Attack Signal Is Off
02169-016
75ps/DIV
150mV/DIV
p-p = 70ps
STD DEV = 9ps
Figure 16. Crosstalk, 3.2 Gbps, PRBS 23, Attack Signal Is On
AD8151
Rev. B | Page 11 of 40
02169-017
1.4ns/DIV
150mV/DIV
p-p = 43ps
STD DEV = 8ps
Figure 17. Response, 2.5 Gbps,
32-Bit Pattern 1111 1111 0000 0000 0101 0101 0011 0011
2.5Gbps JITTER
3.2Gbps JITTER
100
90
80
70
60
50
40
30
20
10
0
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
02169-018
INPUT AMPLITUDE (V)
PEAK-TO-PEAK JITTER (ps)
Figure 18. Jitter vs. Single-Ended Input Amplitude, PRBS 23
3.2Gbps
2.5Gbps
100
90
80
70
60
50
40
30
20
10
0
–1.6 –1.4 –1.2 –1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6
02169-019
V
IH
(V)
PEAK-TO-PEAK JITTER (ps)
Figure 19. Jitter vs. VIH, PRBS 23
02169-020
1.1ns/DIV
150mV/DIV
p-p = 43ps
STD DEV = 8ps
Figure 20. Response, 3.2 Gbps,
32-Bit Pattern 1111 1111 0000 0000 0101 0101 0011 0011
3.2Gbps
2.5Gbps
100
90
80
70
60
50
40
30
20
10
0
–5.0 –4.8 –4.6 –4.4 –4.2 –4.0 –3.8 –3.6 –3.4 –3.2 –3.0
02169-021
V
EE
(V)
PEAK-TO-PEAK JITTER (ps)
Figure 21. Jitter vs. Supply, PRBS 23
100
90
80
70
60
50
40
30
20
10
0
–1.4 –1.2 –1.0 –0.8 –0.6 –0.4 –0.2 0 0.2
02169-022
V
OH
(V)
PEAK-TO-PEAK JITTER (ps)
3.2Gbps
2.5Gbps
Figure 22. Jitter vs. VOH, PRBS 23, Output Amplitude = 0.4 V Single-Ended
AD8151
Rev. B | Page 12 of 40
200
–200
–150
–100
–50
0
50
100
150
–100 –80 –60 –40 –20 0 20 40 60 80 100
02169-025
NORMALIZED TEMPERATURE (°C)
PROPAGATION DELAY (ps)
100
90
80
70
60
50
40
30
20
10
0550 570 590 610 630 650 670 690 710 730
02169-023
PROPAGATION DELAY (ps)
FREQUENCY
Figure 23. Variation in Channel-to-Channel Delay, All 561 Points Figure 25. Propagation Delay, Normalized at 25°C vs. Temperature
2.5Gbps
3.2Gbps
100
90
80
70
60
50
40
30
20
10
05 1015202
02169-024
OUTPUT CURRENT (mA)
PEAK-TO-PEAK JITTER (ps)
02169-026
1.65kΩ49.9Ω
49.9Ω
50Ω
50Ω
V
CC
V
CC
V
TT
1.65kΩ
105Ω
PRBS
GENERATOR HIGH SPEED
SAMPLING
OSCILLOSCOPE
AD8151
IN OUT
P
N
P
DATA OUT
DATA OUT
–6dB
N
–6dB
V
EE
V
EE
V
TT
V
CC
= 0V, V
EE
= –3.3V, V
TT
= –1.6V, V
DD
= 5V, V
SS
= 0V
R
SET
= 1.54kΩ, I
OUT
= 16mA, V
OH
= –0.8V, V
OL
= –1.2V
V
IN
= 0.8V p-p EXCEPT AS NOTED
5
Figure 24. Jitter vs. IOUT, PRBS 23 Figure 26. Test Circuit
AD8151
Rev. B | Page 13 of 40
CONTROL INTERFACE TRUTH TABLES
Table 4. Basic Control Functions
Control Pins1
RESET CS WE RE UPDATE Function
0 X X X X Global Reset. Reset all second rank enable bits to zero (disable all outputs).
1 1 X X X Control Disable. Ignore all logic (but the signal matrix still functions as programmed). D [6:0]
are high impedance.
1 0 0 1 1 Single Output Preprogram. Write input configuration data from Data Bus D [6:0] into first rank
of latches for the output selected by the Output Address Bus A [4:0].
1 0 1 0 1 Single Output Readback. Readback input configuration data from second rank of latches onto
Data Bus D [6:0] for the single output selected by the Output Address Bus A [4:0].
1 0 1 1 0 Global Update. Copy input configuration data from all 17 first rank latches into second rank of
latches, updating signal matrix connections for all outputs.
1 0 0 1 0 Transparent Write and Update. It is possible to write data directly onto rank two. This simplifies
logic when synchronous signal matrix updating is not necessary.
1 X means don’t care.
Table 5. Address/Data Examples
Output Address Pins
MSB–LSB
Enable
Bit1
Input Address Pins MSB–LSB1
A4 A3 A2 A1 A0 D6/E D5 D4 D3 D2 D1 D0 Function
0 0 0 0 0 X 0 0 0 0 0 0 Lower Address/Data Range. Connect Output 00
(A[4:0] = 00000) to Input 00 (D[5:0] = 000000).
1 0 0 0 0 X 1 0 0 0 0 0 Upper Address/Data Range. Connect Output 16
(A[4:0] = 10000) to Input 32 (D[5:0] = 100000).
Binary Output Number 2 1 Binary Input Number Enable Output. Connect Selected Output (A[4:0] = 0 to 16) to
Designated Input (D[5:0] = 0 to 32) and Enable Output
(D6 = 1).
Binary Output Number20 X X X X X X Disable Output. Disable Specified Output (D6 = 0).
1 0 0 0 1 X Binary Input Number Broadcast Connection. Connect all 17 outputs to same
designated input and set all 17 enable bits to D6. Readback is
not possible with the broadcast address.
1 0 0 1 0 X 1 0 0 0 0 1 Reserved. Any address or data code greater or equal to these
are reserved for future expansion or factory testing.
1 X means don’t care.
2 The binary output number can also be the broadcast connection designator, 10001.
AD8151
Rev. B | Page 14 of 40
CONTROL INTERFACE TIMING DIAGRAMS
02169-027
A[4:0] INPUTS
t
CSW
t
ASW
t
WP
t
DSW
t
DHW
t
AHW
t
CHW
CS INPUTS
WE INPUTS
D[6:0] INPUTS
Figure 27. First Rank Write Cycle
Table 6. First Rank Write Cycle
Parameter Mnemonic Description Conditions Min Typ Max Unit
Setup Time tCSW Chip select to write enable TA = 25°C 0 ns
t
ASW Address to write enable VDD = 5 V 0 ns
t
DSW Data to write enable VCC = 3.3 V 15 ns
Hold Time tCHW Chip select from write enable 0 ns
t
AHW Address from write enable 0 ns
t
DHW Data from write enable 0 ns
Enable Pulse tWP Width of write enable pulse 15 ns
02169-028
CS INPUTS
ENABLING
OUT[0:16][N:P]
OUTPUTS
TOGGLE
OUT[0:16][N:P]
OUTPUTS
DISABLING
OUT[0:16][N:P]
OUTPUTS
DATA FROM RANK 1
PREVIOUS RANK 2 DATA
DATA FROM RANK 2
DATA FROM RANK 1
UPDATE INPUTS
tCHU
tUW
tUOT
tUOD
tUOE
tCSU
Figure 28. Second Rank Update Cycle
Table 7. Second Rank Update Cycle
Parameter Mnemonic Function Conditions Min Typ Max Unit
Setup Time tCSU Chip select to update TA = 25°C 0 ns
Hold Time tCHU Chip select from update VDD = 5 V ns
Output Enable Times tUOE Update to output enable VCC = 3.3 V 25 40 ns
Output Toggle Times tUOT Update to output reprogram 25 40 ns
Output Disable Times tUOD Update to output disabled 25 30 ns
Update Pulse tUW Width of update pulse 15 ns
AD8151
Rev. B | Page 15 of 40
02169-029
CS INPUTS
ENABLING
OUT[0:16][N:P]
OUTPUTS INPUT {DATA 2}INPUT {DATA 1}
INPUT {DATA 1}INPUT {DATA 0}
DISABLING
OUT[0:16][N:P]
OUTPUTS
UPDATE INPUTS
WE INPUTS
t
CSU
t
UOT
t
WOT
t
WOD
t
WHU
t
CHU
t
UOE
t
UW
Figure 29. First Rank Write Cycle and Second Rank Update Cycle
Table 8. First Rank Write Cycle and Second Rank Update Cycle
Parameter Mnemonic Function Conditions Min Typ Max Unit
Setup Time tCSU Chip select to update TA = 25°C 0 ns
Hold Time tCHU Chip select from update VDD = 5 V 0 ns
Output Enable Times tUOE Update to output enable VCC = 3.3 V 25 40 ns
t
WOE Write enable to output enable 25 40 ns
Output Toggle Times tUOT Update to output reprogram 25 30 ns
t
WOT Write enable to output reprogram 25 30 ns
Output Disable Times tUODD
1Update to output disabled 25 30 ns
t
WOD Write enable to output disabled 25 30 ns
Setup Time tWHU Write enable to update 10 ns
Update Pulse tUW Width of update pulse 15 ns
1 Not shown.
02169-030
D[6:0]
OUTPUTS
ADDR 1 ADDR 2
DATA
{ADDR 1} DATA
{ADDR 2}
CS INPUTS
RE INPUTS
A[4:0]
INPUTS
t
CSR
t
RDE
t
AA
t
RHA
t
CHR
t
RDD
Figure 30. Second Rank Readback Cycle
Table 9. Second Rank Readback Cycle
Parameter Mnemonic Function Conditions Min Typ Max Unit
Setup Time tCSR Chip select to read enable TA = 25°C 0 ns
Hold Time tCHR Chip select from read enable VDD = 5 V 0 ns
Read Enable tRHA Address from read enable VCC = 3.3 V 5 ns
Enable Time tRDE Data from read enable 10 kΩ 15 ns
Access Time tAA Data from address 20 pF on D[6:0] 15 ns
Release Time tRDD Data from read enable Bus 15 30 ns
AD8151
Rev. B | Page 16 of 40
02169-031
RESET INPUTS
DISABLING
OUT[0:16][N:P]
OUTPUTS
t
TOD
t
TW
Figure 31. Asynchronous Reset
Table 10. Asynchronous Reset
Parameter Mnemonic Function Conditions Min Typ Max Unit
Disable Time tTOD Output disable from reset TA = 25°C 25 30 ns
Width of Reset Pulse tTW VDD = 5 V 15 ns
V
CC = 3.3 V
CONTROL INTERFACE PROGRAMMING EXAMPLE
The following conservative pattern connects all outputs to Input 7, except Output 16, which is connected to Input 32. The vector clock
period t0 is 15 ns. It is possible to accelerate the execution of this pattern by deleting Vectors 1, 4, 7, and 9.
Table 11. Basic Test Pattern
Vector No. RESET CS WE RE UPDATE A[4:0] D[6:0] Comments
0 0 1 1 1 1 xxxxx xxxxxxx Disable all outputs
1 1 1 1 1 1 xxxxx xxxxxxx
2 1 0 1 1 1 10001 1000111 All outputs connected to Input 7
3 1 0 0 1 1 10001 1000111 Write to first rank
4 1 0 1 1 1 10001 1000111
5 1 0 1 1 1 10000 1100000 Connects Output 16 to Input 32
6 1 0 0 1 1 10000 1100000 Write to first rank
7 1 0 1 1 1 10000 1100000
8 1 0 1 1 0 xxxxx xxxxxxx Transfer to second rank
9 1 0 1 1 1 xxxxx xxxxxxx
10 1 1 1 1 1 xxxxx xxxxxxx Disable interface
AD8151
Rev. B | Page 17 of 40
CONTROL INTERFACE
0
2169-031
UPDATE
7
0
1
2
16
33
1 OF 17 DECODE RS
WE
D[0:6]
A[0:4]
RANK 1 RANK 2
17 ROWS OF 7- BIT
LATCHES
RESET
733
733
733
7
7
7
7
0
1
2
16
7
7
7
7
7
7
7
7
7
TO 17
×
33
SWITCH
MATRIX
1 OF 33
DECODERS
RE
Figure 32. Control Interface (Simplified Schematic)
The AD8151 control interface receives and stores the desired
connection matrix for the 33 input and 17 output signal pairs.
The interface consists of 17 rows of double-rank 7-bit latches,
1 row for each output. The 7-bit data-word stored in each of
these latches indicates to which (if any) of the 33 inputs the
output is connected.
One output at a time can be preprogrammed by addressing the
output and writing the desired connection data into the first
rank of latches. This process can be repeated until each of the
desired output changes has been preprogrammed. All output
connections can then be programmed at once by passing the
data from the first rank of latches into the second rank. The
output connections always reflect the data programmed into the
second rank of latches and do not change until the first rank of
data is passed into the second rank.
If necessary for system verification, the data in the second rank
of latches can be read back from the control interface.
At any time, a reset pulse can be applied to the control interface
to globally reset the appropriate second rank data bits, disabling
all 17 signal output pairs. This feature can be used to avoid
output bus contention on system startup. The contents of the
first rank remain unchanged.
The control interface pins are connected via logic-level trans-
lators. These translators allow programming and readback of
the control interface using logic levels different from those in
the signal matrix.
To facilitate multiple chip address decoding, there is a chip-
select pin. All logic signals except the reset pulse are ignored
unless the chip select pin is active. The chip select pin disables
only the control logic interface and does not change the
operation of the signal matrix. The chip select pin does not
power down any of the latches, so any data programmed in the
latches is preserved.
All control pins are level-sensitive, not edge-triggered.
CONTROL PIN DESCRIPTION
A[4:0] Inputs
Output address pins. The binary encoded address applied to
these 5 input pins determines which one of the 17 outputs is
being programmed (or being read back). The most significant
bit (MSB) is A4.
D[6:0] Inputs/Outputs
Input configuration data pins. In write mode, the binary
encoded data applied to the D pins [6:0] determines which of
33 inputs is to be connected to the output specified with the
A pins [4:0]. The MSB is D5 and the least significant bit (LSB) is
D0. Bit D6 is the enable bit, setting the specified output signal
pair to an enabled state if D6 is logic high or disabled to a high
impedance state if D6 is logic low. In readback mode, the
D pins [6:0] are low impedance outputs, indicating the data-
word stored in the second rank for the output specified with the
A pins [4:0]. The readback drivers are designed to drive high
impedances only, so external drivers connected to the D
pins [6:0] should be disabled during readback mode.
WE Input
First Rank Write Enable. Forcing this pin to logic low allows the
data on the D pins [6:0] to be stored in the first rank latch for
the output specified by the A pins [4:0]. The WE pin must be
returned to a logic high state after a write cycle to avoid
overwriting the first rank data.
UPDATE Input
Second Rank Write Enable. Forcing this pin to logic low allows
the data stored in all 17 first rank latches to be transferred to the
second rank latches. The signal connection matrix is repro-
grammed when the second rank data is changed. This is a
global pin, transferring all 17 rows of data at once. It is not
necessary to program the address pins. It should be noted that
after the initial power-up of the device, the first rank data is
undefined. It may be desirable to preprogram all 17 outputs
before performing the first update cycle.
AD8151
Rev. B | Page 18 of 40
RE Input
Second Rank Read-Enable. Forcing this pin to logic low enables
the output drivers on the bidirectional D pins [6:0], entering
the readback mode of operation. By selecting an output address
with the A pins [4:0] and forcing RE to logic low, the 7-bit
data stored in the second rank latch for that output address is
written to the D pins [6:0]. Data should not be written to the
D pins [6:0] externally while in readback mode.
The RE and WE pins are not exclusive, and can be used at the
same time, but data should not be written to the D pins [6:0]
from external sources while in readback mode.
CS Input
Chip-Select. This pin must be forced to logic low to program or
receive data from the logic interface, with the exception of the
RESET pin, described in the next section. This pin has no
effect on the signal pairs and does not alter any of the stored
control data.
RESET Input
Global Output Disable Pin. Forcing the RESET pin to logic low
resets the enable bit, D6, in all 17 second rank latches,
regardless of the state of any of the other pins. This has the
effect of immediately disabling the 17 output signal pairs in the
matrix.
It is useful to momentarily hold RESET at a logic low state when
powering up the AD8151 in a system that has multiple output
signal pairs connected together. Failure to do this can result in
several signal outputs contending after power-up. The RESET
pin is not gated by the state of the chip-select pin, CS. It should
be noted that the RESET pin does not program the first rank,
which contains undefined data after power-up.
CONTROL INTERFACE TRANSLATORS
The AD8151 control interface has two supply pins, VDD and VSS.
The potential between the positive logic supply, VDD, and the
negative logic supply, VSS, must be at least 3 V and no more than
5 V. Regardless of supply, the logic threshold is approximately
1.6 V above VSS, allowing the interface to be used with most
CMOS and TTL logic drivers. The signal matrix supplies, VCC
and VEE, can be set independently of the voltage on VDD and VSS,
with the constraints that (VDD − VEE) ≤ 10 V. These constraints
allow operation of the control interface on 3 V or 5 V, while the
signal matrix is operated on 3.3 V or 5 V PECL or –3.3 V or
–5 V ECL.
AD8151
Rev. B | Page 19 of 40
CIRCUIT DESCRIPTION
The AD8151 is a high speed 33 × 17 differential crosspoint
switch designed for data rates up to 3.2 Gbps per channel. The
AD8151 supports PECL-compatible input and output levels
when operated from a 5 V supply (VCC = 5 V, VEE = GND), or
ECL-compatible levels when operated from a –5 V supply
(VCC = GND, VEE = –5 V). To save power, the AD8151 can run
from a +3.3 V supply to interface with low voltage PECL
circuits or a –3.3 V supply to interface with low voltage ECL
circuits. The AD8151 utilizes differential current-mode outputs
with an individual disable control, which facilitates busing the
outputs of multiple AD8151s together to assemble larger switch
arrays. This feature also reduces system crosstalk and can
greatly reduce power dissipation in a large switch array. A single
external resistor programs the current for all enabled output
stages, allowing user control over output levels with different
output termination schemes and transmission line
characteristic impedances.
High Speed Data Inputs (INxxP, INxxN)
The AD8151 has 33 pairs of differential voltage-mode inputs.
The common-mode input range extends from the positive
supply voltage (VCC) down to include standard ECL or PECL
input levels (VCC – 2 V). The minimum differential input
voltage is 200 mV. Unused inputs may be connected directly to
any level within the allowed common-mode input range. A
simplified schematic of the input circuit is shown in Figure 33.
02169-033
V
CC
V
EE
INxxP INxxN
Figure 33. Simplified Input Circuit
To maintain signal fidelity at the high data rates supported by
the AD8151, the input transmission lines should be terminated
as close to the input pins as possible. The preferred input
termination structure depends primarily on the application and
the output circuit of the data source. Standard ECL components
have open emitter outputs that require pull-down resistors.
Three input termination networks suitable for this type of
source are shown in Figure 34. The characteristic impedance of
the transmission line is shown as ZO. The resistors, R1 and R2,
in the Thevenin termination are chosen to synthesize a VTT
source with an output resistance of ZO and an open-circuit
output voltage equal to VCC – 2 V. The load resistors (RL) in the
differential termination scheme are needed to bias the emitter
followers of the ECL source.
02169-034
(b)
INxxP
INxxN
ZO
ZO
R2 R2
R1
R1
ECL SOURCE
V
CC
V
CC
– 2V
V
EE
(a)
INxxP
INxxN
ECL SOURCE
V
CC
V
TT
= V
CC
– 2V
Z
O
Z
O
Z
O
Z
O
(c)
INxxP
INxxN
ECL SOURCE
V
CC
V
EE
R
L
R
L
Z
O
Z
O
2Z
O
Figure 34. AD8151 Input Termination from ECL/PECL Sources: (a) Parallel
Termination Using VTT Supply, (b) Thevenin Equivalent Termination,
and (c) Differential Termination
If the AD8151 is driven from a current-mode output stage such
as another AD8151, the input termination should be chosen to
accommodate that type of source, as explained in the following
section.
High speed Data Outputs (OUTyyP, OUTyyN)
The AD8151 has 17 pairs of differential current-mode outputs.
The output circuit, shown in Figure 35, is an open-collector
NPN current switch with resistor-programmable tail current
and output compliance extending from the positive supply
voltage (VCC) down to standard ECL or PECL output levels
(VCC − 2 V). The outputs can be disabled individually to permit
outputs from multiple AD8151s to be connected directly. Since
the output currents of multiple enabled output stages sum when
directly connected, care should be taken to ensure that the
output compliance limit is not exceeded at any time by disabling
the active output driver before enabling an inactive driver.
02169-035
V
CC
V
EE
V
CC
– 2V
I
OUT
V
EE
DISABLE
OUTyyP OUTyyN
Figure 35. Simplified Output Circuit
AD8151
Rev. B | Page 20 of 40
To ensure proper operation, all outputs (including unused
output) must be pulled high using external pull-up networks to
a level within the output compliance range. If outputs from
multiple AD8151s are wired together, a single pull-up network
can be used for each output bus. The pull-up network should be
chosen to keep the output voltage levels within the output
compliance range at all times. Recommended pull-up networks
to produce PECL/ECL 100 kΩ and 10 kΩ compatible outputs
are shown in Figure 36. Alternatively, a separate supply can be
used to provide VCOM, making RCOM and DCOM unnecessary.
02169-036
OUTyyN
OUTyyP
AD8151
OUTyyN
OUTyyP
AD8151
V
CC
R
L
R
L
R
L
V
CC
R
L
V
COM
R
COM
V
COM
D
COM
Figure 36. Output Pull-Up Networks for PECL/ECL: a) 100 kΩ and b) 10kΩ
The output levels are
VOH = VCOM
VOL = VCOM – IOUTRL
VSWING = VOH − VOL = IOUTRL
VCOM = VCC – IOUTRCOM (100 kΩ mode)
VCOM = VCC – V(DCOM) (10 kΩ mode)
The common-mode adjustment element (RCOM or DCOM) can be
omitted if the input range of the receiver includes the positive
supply voltage. The bypass capacitors reduce common-mode
perturbations by providing an ac short from the common nodes
(VCOM) to ground. When busing together the outputs of
multiple AD8151s or when running at high data rates, double
termination of its outputs is recommended to mitigate the
impact of reflections due to open transmission line stubs and
the lumped capacitance of the AD8151 output pins. A possible
connection is shown in Figure 37; the bypass capacitors provide
an ac short from the common nodes of the termination resistors
to ground. To maintain signal fidelity at high data rates, the
stubs connecting the output pins to the output transmission
lines or load resistors should be as short as possible.
02169-037
R
L
R
L
R
L
R
L
Z
O
Z
O
Z
O
Z
O
V
CC
R
COM
V
COM
OUTyyN
OUTyyP
AD8151
OUTyyN
OUTyyP
AD8151
RECEIVER
Figure 37. Double Termination of AD8151 Outputs
In this case, the output levels are
VOH = VCOM – (¼)IOUTRL
VOL = VCOM – (¾)IOUTRL
VSWING = VOH – VOL = (½)IOUTRL
Output Current Set Pin (REF)
A simplified schematic of the reference circuit is shown in
Figure 38. A single external resistor connected between the REF
pin and VEE determines the output current for all output stages.
This feature allows a choice of pull-up networks and trans-
mission line characteristic impedances while still achieving a
nominal output swing of 800 mV. At low data rates, substantial
power savings can be achieved by using lower output swings
and higher load resistances.
02169-038
R
SET
V
EE
V
CC
I
OUT
/20
AD8151
REF
1.2V
Figure 38. Simplified Reference Circuit
The nominal output current is given by the following:
⎟
⎠
⎞
⎜
⎝
⎛
=
SETR
V2.1
20
OUTI
The minimum set resistor is RSET, MIN = 960 Ω resulting in
IOUT, MAX = 25 mA. The maximum set resistor is RSET, MAX = 4.8 kΩ
resulting in IOUT, MIN = 5 mA. Nominal 800 mV differential
output swing can be achieved in a 50 Ω load using RSET = 1.5 kΩ
(IOUT = 16 mA), or in a doubly terminated 75 Ω load using
RSET = 1.13 kΩ (IOUT = 21.3 mA). To minimize stray capacitance
and avoid the pickup of unwanted signals, the external set
resistor should be located close to the REF pin. Bypassing the
set resistor is not recommended.
Power Supplies
There are several options for the power supply voltages for the
AD8151, as there are two separate sections of the chip that
require power supplies. These are the control logic and the high
speed data paths. Depending on the system architecture, the
voltage levels of these supplies can vary.
Logic Supplies
The control (programming) logic is CMOS and is designed to
interface with any of the standard single-ended logic families
(CMOS or TTL). Its supply voltage pins are VDD (Pin 170, logic
positive) and VSS (Pin 152, logic ground). In all cases the logic
ground should be connected to the system digital ground. VDD
should be supplied at between 3.3 V to 5 V to match the supply
voltage of the logic family that is used to drive the logic inputs.
VDD should be bypassed to ground with a 0.1 μF ceramic capa-
citor. The absolute maximum voltage from VDD to VSS is 5.5 V.
AD8151
Rev. B | Page 21 of 40
Data Path Supplies
The data path supplies have more options for their voltage levels.
The choices here affect several other areas, such as power
dissipation, bypassing, and common-mode levels of the inputs
and outputs. The more positive voltage supply for the data paths
is VCC (Pin 41, Pin 98, Pin 149, and Pin 171). The more negative
supply is VEE, which appears on many pins that are not listed here.
The maximum allowable voltage across these supplies is 5.5 V.
The first choice in the data path power supplies is to decide
whether to run the device as ECL or PECL. For ECL operation,
VCC is at ground potential, while VEE is at a negative supply
between –3.3 V to –5 V. This makes the common-mode voltage
of the inputs and outputs a negative voltage (see Figure 39).
02169-039
V
CC
V
DD
V
EE
V
SS
DATA
PATHS
CONTROL
LOGIC
+3.3V TO +5V
–3.3V TO –5V
GND
GND
0.1μF
0.1μF
(ONE FOR EVERY TWO V
EE
PINS)
AD8151
Figure 39. Power Supplies and Bypassing for ECL Operation
The proper way to run the device is to dc-couple the data paths
to other ECL logic devices that use ground as the most positive
supply and use a negative voltage for VEE. However, if the part is
to be ac-coupled, it is not necessary to have the input/output
common mode at the same level as the other system circuits,
but it is probably more convenient to use the same supply rails
for all devices. For PECL operation, VEE is at ground potential
and VCC is a positive voltage from 3.3 V to 5 V. Thus, the
common mode of the inputs and outputs is at a positive voltage.
These can then be dc-coupled to other PECL operated devices.
If the data paths are ac-coupled, then the common-mode levels
do not matter (see Figure 40).
02169-040
DATA
PATHS
CONTROL
LOGIC
V
CC
V
DD
V
EE
V
SS
0.1μF0.1μF
(ONE FOR EACH V
CC
PIN,
4 REQUIRED)
+3.3V TO +5V +3.3V TO +5V
GND GND
AD8151
Figure 40. Power Supplies and Bypassing for PECL Operation
POWER DISSIPATION
For analysis, the power dissipation of the AD8151 can be
divided into three separate parts. These are the control logic,
the data path circuits, and the (ECL or PECL) outputs, which
are part of the data path circuits but can be dealt with
separately. The control logic is CMOS technology and does not
dissipate a significant amount of power. This power is, of
course, greater when the logic supply is 5 V rather than 3 V, but
overall it is not a significant amount of power and can be
ignored for thermal analysis.
02169-041
DATA
PATHS
CONTROL
LOGIC
V
CC
V
DD
V
EE
I
OUT
R
OUT
V
OUT
LOW – V
EE
V
SS
GND GND
AD8151
I, DATA PATH
LOGIC
Figure 41. Major Power Consumption Paths
The data path circuits operate between the supplies VCC and
VEE. As described in the power supply section, this voltage can
range from 3.3 V to 5 V. The current consumed by this section
is constant, so operating at a lower voltage can decrease power
dissipation by about 35 percent. The power dissipated in the
data path outputs is affected by several factors. The first is
whether the outputs are enabled or disabled. The worst case
occurs when all of the outputs are enabled. The current
consumed by the data path logic can be approximated by
ICC = 35 mA + [IOUT/20 mA × 3 mA)] × (no. of outputs enabled)
This equation states that a minimum ICC of 35 mA always flows.
ICC increases by a factor that is proportional to both the number
of enabled outputs and the programmed output current.
The power dissipated in this circuit section is simply the voltage
of this section (VCC – VEE) times the current. To calculate the
worst case, assume that VCC – VEE is 5.0 V, all outputs are
enabled, and the programmed output current is 25 mA. The
power dissipated by the data path logic is
P = 5.0 V {35 mA + [4.5 mA + (25 mA/20 mA × 3 mA)] × 17} = 876 mW
The power dissipated by the output current depends on several
factors. These are the programmed output current, the voltage
drop from a logic low output to VEE, and the number of enabled
outputs. A simplifying assumption is that one of each (enabled)
differential output pair is low and draws the full output current
(and dissipates most of the power for that output), while the
complementary output of the pair is high and draws insignifi-
cant current.
AD8151
Rev. B | Page 22 of 40
Thus, the power dissipation of the high output can be ignored and
the output power dissipation for each output can be assumed to
occur in a single static low output that sinks the full output pro-
grammed current. The voltage across which this current flows can
also vary, depending on the output circuit design and the supplies
that are used for the data path circuitry. In general, however, there
is a voltage difference between a logic low signal and VEE. This is
the drop across which the output current flows. For a worst case,
this voltage can be as high as 3.5 V. Thus, for all outputs enabled
and the programmed output current set to 25 mA, the power
dissipated by the outputs is
P = 3.5 V (25 mA) × 17 = 1.49 W
Heat Sinking
Depending on several factors in its operation, the AD8151 can
dissipate upwards of 2 W or more. The part is designed to
operate without the need for an explicit external heat sink.
However, the package design offers enhanced heat removal via
some of the package pins to the PC board traces. The VEE pins
on the input sides of the package (Pin 1 to Pin 46 and Pin 93 to
Pin 138) have finger extensions inside the package that connect
to the paddle upon which the IC chip is mounted. These pins
provide a lower thermal resistance from the IC to the VEE pins
than other pins that just have a bond wire. As a result, these
pins can be used to enhance the heat removal process from the
IC to the circuit board and ultimately to the ambient. The VEE
pins described earlier should be connected to a large area of
circuit board trace material to take the most advantage of their
lower thermal resistance. If there is a large area available on an
inner layer that is at VEE potential, then vias can be provided
from the package pin traces to this layer.
There should be no thermal-relief pattern when connecting the
vias to the inner layers for these VEE pins. Additional vias in
parallel and close to the pin leads can provide an even lower
thermal resistive path. If possible, use 2 oz copper foil to
provide better heat removal than 1 oz copper foil. The AD8151
package has a specified thermal impedance θJA of 30°C/W. This
is the worst case still-air value that can be expected when the
circuit board does not significantly enhance the heat removal
from the package. By using the concept described earlier or by
using forced-air circulation, the thermal impedance can be
lowered.
For an extreme worst case analysis, the junction temperature
increase above the ambient can be calculated assuming 2 W of
power dissipation and a θJA of 30°C/W to yield a 60°C rise above
the ambient. There are many techniques described earlier that
can mitigate this situation. Most actual circuits do not result in
this high an increase of the junction temperature above the
ambient.
AD8151
Rev. B | Page 23 of 40
APPLICATIONS
INPUT AND OUTPUT BUSING
Although the AD8151 is a digital part, in any application that
runs at high speed, analog design details have to be given very
careful consideration. At high data rates, the design of the signal
channels have a strong influence on data integrity and its
associated jitter and ultimately bit error rate (BER).
While it might be considered very helpful to have a suggested
circuit board layout for any particular system configuration, this
is not something that can be practically realized. Systems come
in all shapes, sizes, speeds, performance criteria, and cost con-
straints. Therefore, some general design guidelines are pre-
sented that can be used for all systems and judiciously modified
where appropriate.
High speed signals travel best, that is, they maintain their
integrity when they are carried by a uniform transmission line
that is properly terminated at either end. Any abrupt mis-
matches in impedance or improper termination creates
reflections that add to or subtract from parts of the desired
signal. Small amounts of this effect are unavoidable, but too
much distorts the signal to the point that the channel
BER increases. It is difficult to fully quantify these effects
because they are influenced by many factors in the overall
system design.
A constant-impedance transmission line is characterized by
having a uniform cross-section profile over its entire length. In
particular, there should be no stubs, which are branches that
intersect the main run of the transmission line. These can have
an electrical appearance that is approximated by a lumped
element, such as a capacitor, or if long enough, by another
transmission line. If stubs are unavoidable in a design, their
effect can be minimized by making them as short as possible
and as high an impedance as possible.
Figure 37 shows a differential transmission line that connects
two differential outputs from the AD8151 to a generic receiver.
A more generalized system can have more outputs bused and
more receivers on the same bus, but the same concepts apply.
The inputs of the AD8151 can also be considered as a receiver.
The transmission lines that bus the devices together are shown
with terminations at each end.
The individual outputs of the AD8151 are stubs that intersect
the main transmission line. Ideally, their current source outputs
would be infinite impedance, and they would have no effect on
signals that propagate along the transmission line. In reality,
each external pin of the AD8151 projects into the package and
has a bond wire connected to the chip inside. On-chip wiring
then connects to the collectors of the output transistors and to
ESD protection diodes.
Unlike some other high speed digital components, the AD8151
does not have on-chip terminations. While this location would
be closer to the actual end of the transmission line for some
architectures, this concept can limit system design options. In
particular, it is not possible to bus more than two inputs or
outputs on the same transmission line and it is also not possible
to change the value of these terminations to use for different
impedance transmission lines. The AD8151, with the added
ability to disable its outputs, is much more versatile in these
types of architectures.
If the external traces are kept to a bare minimum, then the
output presents a mostly lumped capacitive load of about 2 pF.
A single stub of 2 pF does not adversely affect signal integrity to
a large extent for most transmission lines, but the more of these
stubs, the greater their adverse influence.
One way to mitigate this effect is to locally reduce the capa-
citance of the main transmission line near the point of stub
intersection. Some practical means for doing this are to narrow
the PC board traces in the region of the stub and/or to remove
some of the ground plane(s) near this intersection. The effect of
these techniques is to locally lower the capacitance of the main
transmission line at these points, while the added capacitance of
the AD8151 outputs compensate for this reduction in capaci-
tance. The overall intent is to create as uniform a transmission
line as possible.
In selecting the location of the termination resistors, it is
important to keep in mind that, as their name implies, they
should be placed at either end of the line. There should be
minimal or no projection of the transmission line beyond the
point where it connects to the termination resistors.
EVALUATION BOARD
An evaluation board has been designed and is available to
rapidly test the main features of the AD8151. This board allows
the user to analyze the analog performance of the AD8151
channels and easily control the configuration of the board with
a PC. The board has limited numbers of differential input/
output pairs. Each differential pair of microstrips is connected
to either top mount or side launch SMA connectors. The top
mount SMA connectors are drilled and stubbed for superior
performance. The FR4 type board contains a total of nine
outputs (all even numbered outputs) and 20 inputs (0, 2, 4, 6, 8,
10, 12, 13, 14, 15, 16, 17, 18, 20, 22, 24, 26, 28, 30, 32). It is
important to note that the shells of the SMA connectors are
attached to VCC. This makes only ECL or negative level swings
possible during testing.
AD8151
Rev. B | Page 24 of 40
POWER SUPPLIES
The AD8151 is designed to work with standard ECL logic
levels. This means that VCC is at ground and VEE is at a negative
supply. The shells of the I/O SMA connectors are at VCC
potential. Thus, when operating in the standard ECL
configuration, test equipment can be directly connected to the
board, since the test equipment also has its connector shells at
ground potential.
Operating in PECL mode requires VCC to be at a positive
voltage while VEE is at ground. Since this generates a positive
voltage at the shells of the I/O connectors, it can cause problems
when directly connecting to test equipment. Some equipment,
such as battery-operated oscilloscopes, can be floated from
ground, but care should be taken with line-powered equipment
to avoid creating a dangerous situation. Refer to the manual of
the test equipment that is being used.
The voltage difference from VCC to VEE can range from 3 V to
5 V. Power savings can be realized by operating at a lower
voltage without any compromise in performance.
A separate connection is provided for VTT, the termination
potential of the outputs. This can be at a voltage as high as VCC,
but power savings can be realized if VTT is at a voltage that is
somewhat lower.
As a practical matter, current on the evaluation board flows
from the VTT supply through the termination resistors into the
multiple outputs of the AD8151 and to the VEE supply. When
running in ECL mode, VTT should be at a negative supply.
Most power supplies do not allow a simultaneous ground
connection to VCC and a negative supply at VTT, because it
would force the source current to originate from a negative
supply, which wants to flow to the more-negative VEE. In this
case, the source current does not then return to the ground
terminal of the VTT supply. Thus, VTT should be referenced to
VEE when running in ECL mode or a true bipolar supply should
be used.
The digital supply is provided to the AD8151 by the VDD and
VSS pins. VSS should always be at ground potential to make it
compatible with standard CMOS or TTL logic. VDD can range
from 3 V to 5 V, and should be matched to the supply voltage of
the logic used to control the AD8151. However, since PCs use
5 V logic on their parallel port, VDD should be 5 V when using a
PC to program the AD8151.
Bypassing
Most of the board’s bypass capacitors are opposite the DUT on
the solder side and are connected between VCC and VEE. This is
where they are most effective. For low inductance, use 0.01 μF
ceramic chip capacitors.
There are additional higher value capacitors elsewhere on the
board for bypassing at lower frequencies. The location of these
capacitors is not as critical.
Input and Output Considerations
Each input contains a 100 Ω differential termination. Although
differential termination eases board layout due to its compact
nature, it can cause problems with the driving generator. A typical
pulse or pattern generator wants to see 50 Ω to ground (or to –2 V
in some cases). High speed probing of the input has shown that if
this type of termination is not present, input amplitudes can be
slightly off. The dc input levels can be even more affected.
Depending on the generator used, these levels can be off as much as
800 mV in either direction. A correction for this problem is to
attach a 6 dB attenuator to each P and N input. Because the
AD8151 has a large common-mode voltage range on its input
stage, it is not significantly affected by dc level errors.
On this evaluation board, all unused inputs are tied to VCC
(GND). All outputs, whether attached to connectors or not, are
tied to VTT through a 49.9 Ω resistor. The AD8151 device is on
the component side of the board, while input terminations and
output back terminations are on the circuit side. The input
signals from the circuit side transit through via holes to the
DUT’s pads. The component-side output signals connect to via
holes and to circuit-side 49.9 Ω termination resistors.
Board Construction
For this board, FR4 material was chosen over more exotic board
materials. Tests show exotic materials are unnecessary. This is a
4-layer board, so power is bused on both external and internal
layers. Test structures show microstrip performance is unaf-
fected by the dc bias levels on the plane beneath it.
The board manufacturing process should ensure a controlled
impedance board. The board stack consists of a 5-mil-thick
layer between external and internal layers. This allows the use of
an 8-mil-wide microstrip trace running from the SMA con-
nector to the DUT’s pads. The narrow trace eliminates the need
to reduce the trace width as the DUT’s pads are approached and
helps to control the microstrip trace impedance. The thin 5-mil
dielectric also reduces crosstalk by confining the electromag-
netic fields between the trace and the plane below.
AD8151
Rev. B | Page 25 of 40
CONFIGURATION PROGRAMMING
The board is configurable by one of two methods. For ease of
use, custom software is provided that controls the AD8151
programming via the parallel port of a PC. This requires a
standard printer cable that has a DB-25 connector at one end
(parallel-port or printer-port interface) and a Centronix
connector at the other, which connects to P2 of the AD8151
evaluation board. The programming with this setup is serial, so
it is not the fastest way to configure the AD8151 matrix.
However, the user interface makes it very convenient to use this
programming method.
If a high speed programming interface is desired, the AD8151
address and data buses are directly available on P3. The source
of the program signals can be a piece of test equipment such as
the Tektronix HFS-9000 digital test generator or other hardware
that generates programming signals. When using the PC inter-
face, the jumper at W1 should be installed and no connections
should be made to P3. When using the P3 interface, no jumper
is installed at W1. There are locations for termination resistors
for the address and data signals, if needed.
SOFTWARE INSTALLATION
The software to operate the AD8151 is provided on two 3.5"
floppy disks. To install the software on a PC:
1. Insert Disk 1 into the floppy disk drive.
2. Run the setup.exe program. This program routinely installs
the software.
3. Insert Disk 2 when prompted.
4. Select a program directory when prompted.
After running the software, the user is prompted to identify
which of three software drivers is used with the PC parallel
port. The default is LPT1, which is most commonly used.
However, some laptops commonly use the PRN driver. It is also
possible that some systems are configured with the LPT2 driver.
If it is not known which driver is used, it is best to select LPT1
and proceed to the next screen, which displays the buttons that
allow the connection of inputs to outputs of the AD8151. All of
the outputs should be in the output off state after the program
starts running. Any of the active buttons can be selected by
clicking the mouse, which sends out a burst of programming
data.
After the software driver has been selected, the user can
generate a steady stream of programming signals out of the
parallel port by holding down the left or right arrow key on the
keyboard. The clock test point on the AD8151 evaluation board
can be monitored with an oscilloscope for any activity (a user-
supplied printer cable must be connected). If there is a square-
wave present, the proper software driver is selected for the PC’s
parallel port.
If there is no signal present, select another driver by clicking
Parallel Port on the File menu. Select a different software
driver and carry out the test described previously until signal
activity is present at the clock test point.
AD8151
Rev. B | Page 26 of 40
SOFTWARE OPERATION This sends out the proper program data and returns to the main
screen with a full column of buttons selected under the chosen
input.
Click any button in the matrix to program the input to output
connection. This sends the proper programming sequence out
the PC parallel port. Since only one input can be programmed
to a given output at one time, clicking a button in a horizontal
row cancels the other selection that is already selected in that
row. However, any number of outputs can share the same input.
The Off column can be used to disable the desired output. To
disable all outputs, click Global Reset. This button selects a full
column of Off buttons.
Two scratch pad memories (Memory 1 and Memory 2) are
provided to conveniently save a particular configuration.
However, these registers are erased when the program is
terminated. For long term storage of configurations, the disk
storage memory should be used. The Save and Load selections
can be accessed from the File menu.
A shortcut for programming all outputs to the same input is to
use the broadcast feature. Click Broadcast Connection and a
screen appears that prompts the user to select which input
should be connected to all outputs. Type in an integer from 0 to
32 and then click OK.
02169-042
AD8151
Figure 42. Evaluation Board Controller
AD8151
Rev. B | Page 27 of 40
02169-043
Figure 43. Component Side
AD8151
Rev. B | Page 28 of 40
02169-044
Figure 44. Circuit Side
AD8151
Rev. B | Page 29 of 40
02169-045
Figure 45. Silkscreen Top
AD8151
Rev. B | Page 30 of 40
02169-046
Figure 46. Solder Mask Top
AD8151
Rev. B | Page 31 of 40
02169-047
Figure 47. Silkscreen Bottom
AD8151
Rev. B | Page 32 of 40
02169-048
Figure 48. Solder Mask Bottom
AD8151
Rev. B | Page 33 of 40
02169-049
Figure 49. INT1 (VEE)
AD8151
Rev. B | Page 34 of 40
02169-050
Figure 50. INT2 (VCC)
AD8151
Rev. B | Page 35 of 40
184
183
182
181
180
179
178
177
176
175
174
173
171
170
169
168
167
166
165
164
163
162
172
161
160
159
157
156
155
154
153
152
158
151
150
149
147
146
145
144
143
142
141
140
139
148
59
60
61
62
63
64
65
66
67
68
47
48
49
50
51
52
53
54
55
56
57
58
69
70
71
72
74
75
76
77
78
73
79
80
81
82
84
85
86
87
83
88
89
90
91
92
5
4
3
2
7
6
9
8
1
14
13
12
11
16
15
17
10
19
18
23
22
21
20
25
24
27
26
29
28
32
31
30
34
33
36
35
40
39
38
37
41
43
42
45
44
46
IN20P
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
A16
V
CC
IN20N
IN21P
IN21N
IN22P
IN22N
IN23P
IN23N
IN24P
IN24N
IN25P
IN25N
IN26P
IN26N
IN27P
IN27N
IN28P
IN28N
IN29P
IN29N
IN30P
IN30N
IN31P
IN31N
IN32P
IN32N
OUT16N
OUT16P
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
A0
V
EE
A1
V
CC
V
EE
IN12N
IN12P
IN11N
IN11P
IN10N
IN10P
IN09N
IN09P
IN08N
IN08P
IN07N
IN07P
IN06N
IN06P
IN05N
IN05P
IN04N
IN04P
IN03N
IN03P
IN02N
IN02P
IN01N
IN01P
IN00N
IN00P
OUT00P
OUT00N
122
137
138
132
133
134
135
130
131
129
136
127
128
123
124
125
126
120
121
118
119
116
117
113
114
115
111
112
109
110
108
105
106
107
104
102
103
100
101
95
96
97
98
99
93
94
PIN 1
INDICATOR
AD8151
184L LQFP
TOP VIEW
(Not to Scale)
IN19N
IN19P
IN18N
IN18P
IN17N
IN17P
IN16N
IN16P
RESET
CS
RE
WE
UPDATE
A0
A1
A2
A3
A4
D0
D1
D2
D3
D4
D5
D6
IN15N
IN15P
IN14N
IN14P
IN13N
IN13P
V
EE
V
EE
V
EE
V
EE
V
EE
V
SS
V
C
C
V
EE
V
EE
V
EE
V
EE
V
EE
REF
REF
V
CC
V
DD
OUT15N
OUT15P
OUT14N
OUT14P
OUT13N
OUT13P
OUT12N
OUT12P
OUT11N
OUT11P
OUT10N
OUT10P
OUT09N
OUT09P
OUT08N
OUT08P
OUT07N
OUT07P
OUT06N
OUT06P
OUT05N
OUT05P
OUT04N
OUT04P
OUT03N
OUT03P
OUT02N
OUT02P
OUT01N
OUT01P
V
EE
V
EE
A15
V
EE
A14
V
EE
A13
V
EE
A12
V
EE
A11
V
EE
A10
V
EE
A9
V
EE
A8
V
EE
A7
V
EE
A6
V
EE
A5
V
EE
A4
V
EE
A3
V
EE
A2
V
EE
02169-051
V
CC
C31
0.01μF
V
CC
C32
0.01μF
V
CC
C29
0.01μF
V
CC
C4
0.01μF
V
CC
C5
0.01μF
V
EE
C12
0.01μF
V
DD
C14
0.01μF
V
CC
C6
0.01μF
V
CC
C7
0.01μF
V
EE
C13
0.01μFV
CC
C30
0.01μF
V
CC
C10
0.01μF
V
CC
C9
0.01μF
V
CC
C8
0.01μF
V
EE
C11
0.01μFV
EE
C60
0.01μF
V
CC
C15
0.01μF
R203
1.5kΩ
Figure 51. Bypassing Schematic
AD8151
Rev. B | Page 36 of 40
P52
P53
R93
IN24P
IN24N
R94
R92
P16
P17
R39
IN06P
IN06N
R40
R38
VCC
VEE VEE VEE VEE
VEE
VEE VEE
VCC VCC
VCC
VCC VCC VCC
P4
P5
R20
IN00P
IN00N
R19
105Ω
1.65kΩ
1.65kΩ
105Ω
1.65kΩ
1.65kΩ
105Ω
1.65kΩ
1.65kΩ
105Ω
1.65kΩ
1.65kΩ
105Ω
1.65kΩ
1.65kΩ
105Ω
1.65kΩ
1.65kΩ
R21
VCC
VEE VEE VEE VEE
VEE
VEE VEE
VCC VCC
VCC
VCC VCC VCC
VCC
VEE VEE VEE VEE
VEE
VEE
VCC VCC
VCC VCC
VCC VCC
P28
P29
R57
IN12P
IN12N
R58
R56
P40
P41
R90
IN18P
IN18N
R89
R91
P64
P65
R117
IN30P
IN30N
R116
R118
P56
P57
R99
IN26P
IN26N
R98
R100
P20
P21
R45
IN08P
IN08N
R44
R46
P8
P9
R27
IN02P
IN02N
R28
R26
P32
P33
R63
IN14P
IN14N
R62
R64
P44
P45
R84
IN20P
IN20N
R85
R83
P68
P69
R111
IN32P
IN32N
R112
R110
P60
P61
R105
IN28P
IN28N
R104
R106
P24
P25
R51
IN10P
IN10N
R50
R52
P12
P13
R33
IN04P
IN04N
R34
R32
P36
P37
R69
IN16P
IN16N
R68
R70
P48
P49
R78
IN22P
IN22N
R79
R77
P30
P31
R60
IN13P
IN13N
R59
R61
105Ω
1.65kΩ
1.65kΩ
105Ω
1.65kΩ
1.65kΩ
105Ω
1.65kΩ
1.65kΩ
105Ω
1.65kΩ
1.65kΩ
105Ω
1.65kΩ
1.65kΩ
105Ω
1.65kΩ
1.65kΩ
105Ω
1.65kΩ
1.65kΩ
105Ω
1.65kΩ
1.65kΩ
105Ω
1.65kΩ
1.65kΩ
105Ω
1.65kΩ
1.65kΩ
105Ω
1.65kΩ
1.65kΩ
105Ω
1.65kΩ
1.65kΩ
105Ω
1.65kΩ
1.65kΩ
105Ω
1.65kΩ
1.65kΩ
P34
P35
R66
IN15P
IN15N
R65
R67
P38
P39
R72
IN17P
IN17N
R71
R73
P
N
IN01, IN03, IN05, IN07,
IN09, IN11, IN19, IN21,
IN23, IN25, IN27, IN29, IN31
P103
P102
R121
OUT00N R122
OUT00P
P87
R160
OUT08N R162
VTT
VTT 49.9Ω
49.9Ω
49.9Ω
49.9Ω
VTT
VTT 49.9Ω
49.9Ω
49.9Ω
49.9Ω
VTT
VTT 49.9Ω
49.9Ω
49.9Ω
49.9Ω
VTT
VTT 49.9Ω
49.9Ω
49.9Ω
49.9Ω
VTT
VTT 49.9Ω
49.9Ω
49.9Ω
49.9Ω
VTT
VTT 49.9Ω
49.9Ω
49.9Ω
49.9Ω
VTT
VTT 49.9Ω
49.9Ω
49.9Ω
49.9Ω
VTT
VTT 49.9Ω
49.9Ω
49.9Ω
49.9Ω
P86
OUT08P
VCC
VTT
C16
0.01μF
0.01μF
0.01μF
VCC
VTT
C82
VCC
VTT
C83
P71
R200
49.9Ω
OUT16N R198
49.9ΩP70
OUT16P VTT
OUT15N
OUT15P R190
R192 OUT07N
OUT07P R155
R153
P91
R150
OUT06N R152
P90
OUT06P
P75
R195
OUT14N R193
P74
OUT14P
R180
OUT13N R182
OUT13P R145
OUT05N R143
OUT05P
P95
R140
OUT04N R142
P94
OUT04P
P79
R185
OUT12N R183
P78
OUT12P
R170
OUT11N R172
OUT11P R135
OUT03N R133
OUT03P
P99
R130
OUT02N R132
P98
OUT02P
P83
R175
OUT10N R173
P82
OUT10P
R165
OUT09N R163
OUT09P R125
OUT01N R127
OUT01P
02169-052
Figure 52. Evaluation Board Input/Output Schematic
AD8151
Rev. B | Page 37 of 40
+
P1 6
P1 1
P1 2
P1 3
P1 4
P1 7
P1 5
+
+C2
10μF
C1
10μF
C3
10μF
P104
P105
OUT_EN
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
GND
10
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
20
19
18
17
16
15
14
13
12
CLK 11
READ P2 7
RESET P2 3
WRITE P2 8
UPDATE P2 4
CHIP_SELECT P2 2
WRITE P3 13
RESET P3 7
READ P3 11
D0 P3 27
A4 P3 25
A3 P3 23
A2 P3 21
A1 P3 19
A0 P3 17
D6 P3 39
D5 P3 37
D4 P3 35
D3 P3 33
D2
D1 P3 29
UPDATE P3 15
CHIP_SELECT P3 9
V
DD
P3 5
V
SS
V
DD
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
P3 14
P3 8
P3 12
P3 28
P3 26
P3 24
P3 22
P3 20
P3 18
P3 40
P3 38
P3 36
A2
DAT
A
P2 5
CLK P2 6
CLK
DATA
P2 25
R7
49Ω
R8
49Ω
R9
49Ω
R10
49Ω
R11
49Ω
R12
49Ω
R13
49Ω
R14
49Ω
R15
49Ω
R16
49Ω
R17
49Ω
R18
49Ω
R1
20kΩ
OUT_EN
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
GND
10
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
20
19
18
17
16
15
14
13
12
CLK 11
P3 31
A4
P3 34
P3 32
P3 30
P3 16
P3 10
P3 6
A3
TP5
TP4
TP6
TP7
TP8
CHIP_SELECT
168
UPDATE
165
WRITE
166
RESET
169
READ
167
A4
74HC132
74HC132
1
24
5
W1
74HC14
A1
74HC14
A1
74HC14
A1
12
3456
74HC74 74HC74
160A4
161A3
162A2
163A1
164A0
TP9
TP10
TP11
TP12
TP13
TP20
TP14
TP15
TP16
TP17
TP18
TP19
153D6
154D5
155D4
156D3
157D2
158D1
159D0
9
10 8
A4
A1
11 10
A1
13 12
12
13 11
A4
74HC14
A1
98
74HC14
74HC14
74HC132
74HC132
36
V
SS
V
SS
V
DD
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
DD
V
SS
V
DD
V
CC
V
CC
V
DD
V
TT
V
CC
V
TT
V
TT
V
CC
V
CC
V
EE
V
EE
V
DD
V
SS
A1, 4 PIN 14 IS TIED TO V
DD
.
A1, 4 PIN 7 IS TIED TO V
SS
.
C86
0.1μFC87
0.1μFC88
0.1μFC89
0.1μF
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
EE
V
DD
V
SS
V
DD
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
R2
49kΩ
R3
49kΩ
R4
49kΩ
R5
49kΩ
R6
49kΩ
02169-053
Figure 53. Evaluation Board Logic Controls
AD8151
Rev. B | Page 38 of 40
OUTLINE DIMENSIONS
139
138
47
46 92
93
184
TOP VIEW
(PINS DOWN)
1
0.40
BSC
LEAD PITCH
0.23
0.18
0.13
1.60
MAX
0.75
0.60
0.45
VIEW A
PIN 1
1.45
1.40
1.35
0.15
0.05
0.20
0.09
0.08 MAX
COPLANARITY
VIEW A
ROTATED 90° CCW
SEATING
PLANE
7°
3.5°
0°
22.20
22.00 SQ
21.80
20.20
20.00 SQ
19.80
Figure 54. 184-Lead Low Profile Quad Flat Package [LQFP]
(ST-184)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD8151AST 0°C to 85°C 184-Lead LQFP ST-184
AD8151ASTZ10°C to 85°C 184-Lead LQFP ST-184
AD8151-EVAL Evaluation Board
1 Z = Pb-free part.
AD8151
Rev. B | Page 39 of 40
NOTES
AD8151
Rev. B | Page 40 of 40
NOTES
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C02169-0-12/05(B)
