www.gennum.com
GS1535 HD-LINX II™
Multi-Rate SDI
Automatic Reclocker
GS1535 Data Sheet
18557 - 8 February 2005 1 of 22
Key Features
• SMPTE 292M, 259M and 344M compliant
• Supports data rates of 143, 177, 270, 360, 540,
1483.5, 1485 Mb/s
• Supports DVB-ASI at 270Mb/s
• Auto and Manual Modes for rate selection
• Standards indication in Auto Mode
• 4:1 input multiplexor
• Lock Detect Output
• On-chip Input and Output Termination
• Differential inputs and outputs
• Configuarble automatic Mute or Bypass when not
locked
• Manual Bypass function
• SD/HD indication output to control GS1528 Dual
Slew-Rate Cable Driver
• Pb-free and Green
• Single 3.3V power supply
• Operating temperature range: 0°C to 70°C
Applications
• SMPTE 292M, SMPTE 259M and SMPTE 344M
Serial Digital Interfaces
Description
The GS1535 Multi-Rate Serial Digital Reclocker is
designed to automatically recover the embedded clock
signal and re-time the data from a SMPTE 292M,
SMPTE 259M or SMPTE 344M compliant digital video
signal.
The device removes the high frequency jitter
components from the bit-serial stream. Input
termination is on-chip for seamless matching to 50Ω
transmission lines. An LVPECL compliant output
interfaces seamlessly to the GS1528 Cable Driver
The GS1535 can operate in either auto or manual rate
selection mode. In Auto mode the GS1535
automatically detects and locks onto an incoming
SMPTE SDI data signal from 143 Mb/s to 1.485 Gb/s.
For single rate data systems, the GS1535 can be
configured to operate in manual mode. In both modes,
the GS1535 requires only one external crystal to set the
VCO frequency when not locked and provides
adjustment free operation. In systems which require
passing non-SMPTE data rates, the GS1535 will
automatically or manually enter a bypass mode in order
to pass the signal without reclocking.
The ASI/177 input pin allows for manual selection of
support of either 177Mb/s or DVB-ASI inputs.
GS1535 Functional Block Diagram
XTAL+ XTAL-
XTAL
OUT-
XTAL
OUT+
DDI_SEL[1:0]
DDI 1
DDI 2
DDI 3
DDI 0
LF+LF- KBB
DDO_MUTE
DDO/DDO
AUTOBYPASS BYPASS
LD
AUTO/MAN
SS[2:0] ASI/177
XTAL
OSC BUFFER
DATA BUFFER
VCO
BYPASS
LOGIC
DIVIDE BY
2,4,6,8,12,16
PHASE
FREQUENCY
DETECTOR
DIVIDE BY
152, 160, 208
CONTROL LOGIC
CHARGE
PUMP
M
U
X
D
A
T
A
M
U
X
M
U
X
RE-TIMER
PHASE
DETECTOR
GS1535 Data Sheet
18557 - 8 February 2005 2 of 22
Contents
Key Features.................................................................................................................1
Applications...................................................................................................................1
Description ....................................................................................................................1
1. Pin Out ......................................................................................................................3
1.1 Pin Assignment ...............................................................................................3
1.2 Pin Descriptions ..............................................................................................4
2. Electrical Characteristics...........................................................................................7
2.1 Absolute Maximum Ratings ............................................................................7
2.2 DC Electrical Characteristics ..........................................................................7
2.3 AC Electrical Characteristics ...........................................................................8
2.4 Input/Output Circuits .....................................................................................10
3. Detailed Description ................................................................................................13
3.1 Slew Rate Phase Lock Loop (S-PLL) ...........................................................13
3.2 VCO ..............................................................................................................14
3.3 Charge Pump ................................................................................................14
3.4 Frequency Acquisition Loop —The Phase-Frequency Detector ...................14
3.5 Phase Acquisition Loop — The Phase Detector ...........................................15
3.6 4:1 Input Mux ................................................................................................15
3.7 Automatic And Manual Data Rate Selection .................................................16
3.8 Bypass Mode ................................................................................................17
3.9 DVB/ASI Operation .......................................................................................17
3.10 LOCK ..........................................................................................................17
3.11 Output Drivers .............................................................................................18
3.12 Output Mute ................................................................................................18
4. Application Reference Design.................................................................................19
4.1 Typical Application Circuit .............................................................................19
5. References..............................................................................................................20
6. Package & Ordering Information.............................................................................20
6.1 Package Dimensions ....................................................................................20
6.2 Packaging Data .............................................................................................21
6.3 Ordering Information .....................................................................................21
7. Revision History ......................................................................................................22
GS1535 Data Sheet
18557 - 8 February 2005 3 of 22
1. Pin Out
1.1 Pin Assignment
P
XTAL_OUT-
XTAL_OUT+
GND
VEE_DDO
VCC_DDO
DDO
DDO_VTT
GND
VCC_INT
VEE_INT
RSVD
RSVD
GND
GND
KBB
DDI_SEL0
DDI_SEL1
BYPASS
AUTOBYPASS
VCC_VCO
VEE_VCO
SS0
SS1
SS2
LD
RSVD
VCC_DIG
VEE_DIG
GND
DDI0
DDI0_VTT
GND
DDI1_VTT
GND
DDI1
DDI2_VTT
GND
DDI2
DDI3_VTT
GND
DDI3
GND
LF-
LF+
VCC_CP
VEE_CP
RSVD
RSVD
VCC
RSVD
VCC
GND
XTAL-
XTAL+
GS1535
64 PIN LQFP
TOP VIEW
DDI3
DDI2
DDI1
DDI0
AUTO/MAN
SD/HD
DDO_MUTE
RSVD
DDO
ASI/177
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49505152535455565758596061626364
GS1535 Data Sheet
18557 - 8 February 2005 4 of 22
1.2 Pin Descriptions
Table 1-1: Pin Descriptions
Pin
Number
Name Type Description
1, 3 DDI0, DDI0 INPUT Serial digital differential input 0.
2 DDI0_VTT PASSIVE Center tap of two 50Ω on-chip termination resistors between DDI0 and DDI0.
5, 7 DDI1,DDI1 INPUT Serial digital differential input 1.
6 DDI1_VTT PASSIVE Center tap of two 50Ω on-chip termination resistors between DDI1 and DDI1.
9, 11 DDI2, DDI2 INPUT Serial digital differential input 2.
10 DDI2_VTT PASSIVE Center tap of two 50Ω on-chip termination resistors between DDI2 and DDI2.
13, 15 DDI3, DDI3 INPUT Serial digital differential input 3 .
14 DDI3_VTT PASSIVE Center tap of two 50Ω on-chip termination resistors between DDI3 and DDI3.
17, 18 DDI_SEL[1:0] LOGIC INPUT Serial digital input select.
19 BYPASS LOGIC INPUT Bypasses the reclocker stage (Active HIGH). When BYPASS is HIGH, it
overwrites the AUTOBYPASS setting.
20 AUTOBYPASS LOGIC INPUT Automatically bypasses the reclocker stage when the PLL is not locked
(Active HIGH).
21 AUTO/MAN LOGIC INPUT When active, the standard is automatically detected from the input data rate.
DDI_SEL1 DDI_SEL0 INPUT
SELECTED
00 DDI0
01 DDI1
10 DDI2
11 DDI3
GS1535 Data Sheet
18557 - 8 February 2005 5 of 22
24, 25, 26 SS[2:0] BIDIRECTIONAL When AUTO/MAN is HIGH, SS[0:2] are outputs, displaying the data rate to
which the PLL has locked.
When AUTO/MAN is LOW, SS[0:2] are inputs, forcing the PLL to lock only to a
selected data rate.
27 ASI/177 LOGIC INPUT Disables 177Mbps data rate in the AUTO data rate detection circuit. This
prevents a FALSE LOCK to 177Mbps when using DVB/ASI.
28 LD OUTPUT LOCK DETECT. HIGH when the PLL is locked.
29 RSVD RESERVED DO NOT CONNECT.
33 SD/HD OUTPUT This signal is LOW when the reclocker has locked to 1.485Gbps or
1.485/1.001Gbps, and HIGH when the reclocker has locked to 143Mbps,
177Mbps, 270Mbps, 360Mbps, or 540Mbps.
34 KBB ANALOG INPUT Controls the loop bandwidth of the PLL. Leave this pin floating for serial
reclocking applications.
36 DDO_MUTE LOGIC INPUT Mutes the DDO/DDO outputs, when not in bypass mode.
44, 46 DDO, DDO OUTPUT Differential Serial Digital Outputs.
45 DDO_VTT PASSIVE Center tap of two 50Ω on-chip termination resistors between DDO and DDO..
50, 51 XTAL_OUT+,
XTAL_OUT-
OUTPUT Differential buffered outputs of the reference oscillator.
52, 53 XTAL+, XTAL- INPUT Reference crystal input. Connect to the GO1535.
62, 63 LF+, LF- PASSIVE Loop filter capacitor connection. (CLF = 47nF).
4, 8, 12,16,
32, 35, 37,
43, 49, 54, 64
GND PASSIVE Recommended connect to GND.
43 GND_DRV PASSIVE Recommended connect to GND.
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name Type Description
SS2 SS1 SS0 DATA RATE
SELECTED/FORCED (Mb/s)
0 0 0 143
0 0 1 177
0 1 0 270
0 1 1 360
1 0 0 540
1 0 1 1483.5/1485
GS1535 Data Sheet
18557 - 8 February 2005 6 of 22
55, 57 VCC PASSIVE Recommend connect to 3.3V.
22 VCC_VCO POWER Most positive power supply connection for the internal VCO section.
Connect to 3.3V.
30 VCC_DIG POWER Most positive power supply connection for the internal glue logic.
Connect to 3.3V.
41 VCC_INT POWER Most positive power supply connection. Connect to 3.3V.
47 VCC_DDO POWER Most positive power supply connection for the DDO/DDO output driver.
Connect to 3.3V.
61 VCC_CP POWER Most positive power supply connection for the internal charge pump.
Connect to 3.3V.
23 VEE_VCO POWER Most negative power supply connection for the internal VCO section.
Connect to ground.
31 VEE_DIG POWER Most negative power supply connection for the internal glue logic.
Connect to ground.
42 VEE_INT POWER Most negative power supply connection. Connect to ground.
48 VEE_DDO POWER Most negative power supply connection for the DDO/DDO output driver.
Connect to ground.
60 VEE_CP POWER Most negative power supply connection for the internal charge pump.
Connect to ground.
38, 39, 40,
56, 58, 59
RSVD RESERVED Do not Connect.
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name Type Description
GS1535 Data Sheet
18557 - 8 February 2005 7 of 22
2. Electrical Characteristics
2.1 Absolute Maximum Ratings
2.2 DC Electrical Characteristics
Table 2-1: Absolute Maximum Ratings
Parameter Value
Supply Voltage +3.6 VDC
Input ESD Voltage 500V
Storage Temperature Range -50°C< Ts < 125°C
Inputs VCC + 0.5V
Table 2-2: DC Electrical Characteristics
Vcc = 3.3V, TA = 0°C to 70°C, unless otherwise shown
Parameter Conditions Symbol Min Typ Max Units Test
Levels
Supply Voltage Operating
Range
VCC 3.135 3.3 3.465 V 3
Power
Consumption
TA=25°C 408 600 849 mW 5
Supply Current TA=25°C ICC 130 182 245 mA 1
Logic Inputs
DDI_SEL[1:0],
BYPASS,
AUTOBYPASS,
AUTO/MAN,
ASI/177,
SDO_MUTE
High VIH 2.0 - - V 3
Low VIL --0.8V3
Logic Outputs
SD/HD and LD
250µA Load VOH 3.2 - - V 3
VOL --0.6V3
Bi-Directional Pins
SS[2:0],
AUTO/MAN = 0
(Manual Mode)
High VIH 2.0 - - V 3
Low VIL --0.8V3
Bi-Directional Pins
SS[2:0],
AUTO/MAN = 1
(AUTO Mode)
High VOH 2.6 - V 1
Low VOL --0.6V1
GS1535 Data Sheet
18557 - 8 February 2005 8 of 22
2.3 AC Electrical Characteristics
XTAL_OUT+,
XTAL_OUT-
High VOH -V
CC -V7
Low VOL -V
CC - 0.285 - V 7
Serial Input
Voltage
Common
mode
1.65 +
(VSID/2)
-V
CC - (VSID/2) V 1
Output Voltage
SDO, SDO
Common
mode
-V
CC - VOD/2 - V 1
Test Levels
1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges.
2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using
correlated test.
3. Production test at room temperature and nominal supply voltage.
4. QA sample test.
5. Calculated result based on Level 1, 2, or 3.
6. Not tested. Guaranteed by design simulations.
7. Not tested. Based on characterization of nominal parts.
8. Not tested. Based on existing design/characterization data of similar product.
9. Indirect test.
Table 2-2: DC Electrical Characteristics
Vcc = 3.3V, TA = 0°C to 70°C, unless otherwise shown
Parameter Conditions Symbol Min Typ Max Units Test
Levels
Table 2-3: AC Electrical Characteristics
Vcc = 3.3V, TA = 0°C to 70°C, unless otherwise shown
Parameter Symbol Conditions Min Typ Max Units Test
Levels
Serial Input Data Rate 143 - 1485 Mb/s 3
Serial Input Jitter Tolerance Worst case modulation
Eg. Square wave modulation
143, 270, 360, 1485 Mb/s
0.8 - - UI 1
PLL Lock Time -
Asynchronous
tALOCK - 5 10 ms 6,7
PLL Lock Time - Synchronous tSLOCK CLF=47nF SD/HD=0 0.29 - - µs6,7
SD/HD=1 0.16 - - µs6,7
Serial Output Rise/Fall Time
(20% - 80%)
trSDO 50Ω load (on chip) - 114 - ps 6,7
tfSDO - 106 - ps
Serial Input - Signal Swing VSID 50Ω load (on chip) 100 - 800 mVp-p 6,7
Serial Output - Signal Swing VOD Differential (across 100Ω). 1400 - 2000 mVp-p
GS1535 Data Sheet
18557 - 8 February 2005 9 of 22
Serial Output Jitter
(additive)
tIJ KBB=Float,
PRN, 223-1
143Mb/s - 0.02 - UI 1
177Mbs - 0.02 - UI 1
270Mb/s - 0.02 0.09 UI 1
360Mbs - 0.03 - UI 1
540Mbs - 0.03 0.09 UI 1
1485Mb/s - 0.06 0.13 UI 1
BYPASS - 0.06 0.13 UI 1
Loop Bandwidth BWLOOP 1.485 Gb/s
KBB = FLOAT
-1.5-MHz6,7
1.485 Gb/s
KBB = GND
<0.1dB
Peaking
-3.5-MHz6,7
270 Mb/s
KBB = FLOAT
- 520 - KHz 6,7
270 Mb/s
KBB = GND
- 1000 - KHz 6,7
Test Levels
1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges.
2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using
correlated test.
3. Production test at room temperature and nominal supply voltage.
4. QA sample test.
5. Calculated result based on Level 1, 2, or 3.
6. Not tested. Guaranteed by design simulations.
7. Not tested. Based on characterization of nominal parts.
8. Not tested. Based on existing design/characterization data of similar product.
9. Indirect test.
Table 2-3: AC Electrical Characteristics
Vcc = 3.3V, TA = 0°C to 70°C, unless otherwise shown
Parameter Symbol Conditions Min Typ Max Units Test
Levels
GS1535 Data Sheet
18557 - 8 February 2005 10 of 22
2.4 Input/Output Circuits
Figure 2-1: TTL Inputs
Figure 2-2: Crystal Input
Figure 2-3: Serial Data Outputs
VREF
5K
10p
250R 250R
5K
XTAL+
XTAL-
50
SDO SDO
50
GS1535 Data Sheet
18557 - 8 February 2005 11 of 22
Figure 2-4: Loop Filter
Figure 2-5: Crystal Ouput Buffer
Figure 2-6: KBB
LF+ LF-
1K
1K
XTAL OUT-
XTAL OUT+
500R
V
REF
KBB
GS1535 Data Sheet
18557 - 8 February 2005 12 of 22
Figure 2-7: Indicator Outputs: HD/SD, LD
Figure 2-8: Serial Data Inputs
Figure 2-9: Standard Select/Indication Bi-directional pins
25K
50
DDI[3:0]
DDI[3:0]
1k 1k
50
DDI_VTT
v
REF
SS[2:0]
GS1535 Data Sheet
18557 - 8 February 2005 13 of 22
3. Detailed Description
The GS1535 is a multi-standard retimer for serial digital SDTV signals at 143, 177,
270, 360 and 540 Mb/s, and HDTV signals at 1.485 Gb/s and 1.485/1.001 Gb/s.
3.1 Slew Rate Phase Lock Loop (S-PLL)
The term “slew” refers to the output phase of the PLL in response to a step change
at the input. Linear PLLs have an output phase response characterized by an
exponential response whereas an S-PLL’s output is a ramp response (See
Figure 3-1). Because of this non-linear response characteristic, traditional small
signal analysis is not possible with an S-PLL.
Figure 3-1: PLL Characteristics
The S-PLL offers several advantages over the linear PLL. The Loop Bandwidth of
an S-PLL is independant of the transition density of the input data. Pseudo-random
data has a transition density of 0.5 verses a pathological signal which has a
transition density of 0.05. The loop bandwidth of a linear PLL will change
proportionally with this change in transition density. With an S-PLL, the loop
bandwidth is defined by the jitter at the data input. This translates to infinite loop
bandwidth with a zero jitter input signal. This allows the loop to correct for small
variations in the input jitter quickly, resulting in very low output jitter. The loop
bandwidth of the GS1535’s PLL is defined at 0.2UI of input jitter.
The GS1535’s PLL consists of two acquisition loops. First is the Frequency
Acquisiton (FA) loop. This loop is active when the device is not locked and is used
to achieve lock to the supported data rates. Second is the phase acquisition (PA)
loop. Once locked, the PA loop tracks the incomming data and makes phased
corrections to produce a re-clocked output.
0.2
0.1
0.0
INPUT
OUTPUT
SLEW PLL RESPONSE
PHASE (UI)
0.2
0.1
0.0
INPUT
OUTPUT
LINEAR (CONVENTIONAL) PLL RESPONSE
PHASE (UI)
GS1535 Data Sheet
18557 - 8 February 2005 14 of 22
3.2 VCO
The internal VCO of the GS1535 is a ring oscillator. It is trimmed at the time of
manufacture to capture all SD and HD data rates over temperature, and operation
voltage ranges.
Integrated into the VCO is a series of programmable dividers, to achieve all serial
data rates, as well as additional dividers for the frequency acquisition loop.
3.3 Charge Pump
A common charge pump is used for the GS1535’s PLL.
During frequency acquisition, the charge pump has two states, “pump-up” and
“pump-down” which is produced by a leading or lagging phase difference between
the input and the VCO frequency.
During phase acquisition, there are two levels of “pump-up” and two levels of
“pump down” produced for leading and lagging phase difference between the input
and VCO frequency. This is to allow for greater precision of VCO control.
The charge pump produces these signals by holding the integrated frequency
information on the external loop-filter capacitor, CLF.. The instantaneous
frequency information is the result of the current flowing through an internal resistor
connected to the loop-filter capacitor.
3.4 Frequency Acquisition Loop —The Phase-Frequency Detector
An external crystal of 14.140 MHz is used as a reference to keep the VCO centered
at the last known data rate. This allows the GS1535 to achieve a fast synchronous
lock, especially in cases where a known data rate is interrupted. The crystal
reference is also used to clock internal timers and counters. To keep the optimal
performance of the reclocker over all operating conditions, the crystal frequency
must be 14.140 MHz, +/-50ppm. The GO1535 meets this specification and is
available from GENNUM.
The VCO is divided by a selected ratio which is dependant on the input data rate.
The resultant is then compared to the crystal frequency. If the divided VCO
frequency and the crystal frequency are within 1% of each other, the PLL is
considered to be locked to the input data rate.
GS1535 Data Sheet
18557 - 8 February 2005 15 of 22
3.5 Phase Acquisition Loop — The Phase Detector
The phase detector is a digital quadrature phase detector. It indicates whether the
input data is leading or lagging with respect to a clock that is in phase with the VCO
(I-clk) and a quadrature clock (Q-clk). When the phase acquisition loop (PA loop)
is locked, the input data transition is aligned to the falling edge of I-clk and the
output data is re-timed on the rising edge of I-clk. During high input jitter conditions
(>0.25UI), Q-clk will sample a different value than I-clk. In this condition, two extra
phase correction signals will be generated which instructs the charge pump to
create larger frequency corrections for the VCO.
Figure 3-2: Phase Detector Characteristics.
When the PA loop is active, the crystal frequency and the incomming data rate are
compared. If the resultant is more that 2%, the PLL is considered to be unlocked
and the system jumps to the FA loop.
3.6 4:1 Input Mux
The 4:1 input mux allows the connection of four independent streams of video/data.
These are differential inputs (DDI[3:0] and DDI[3:0]). The active channel can be
selected via the DDI_SEL[1:0] pins. Table 3-1 shows the input selected for a given
state at DDI_SEL[1:0].
i-PHASE ALIGNMENT
EDGE
DATA RE-TIMING
EDGE
q-PHASE ALIGNMENT
EDGE
0.25UI 0.8UI
I-clk
q-clk
INPUT DATA
WITH JITTER
RE-TIMED
OUTPUT DATA
Table 3-1: Bit Pattern for Input Select
DDI_SEL1:0] Selected Input
00 DDI0
01 DDI1
10 DDI2
11 DDI3
GS1535 Data Sheet
18557 - 8 February 2005 16 of 22
The DDI inputs are designed to be DC interfaced with the output of the GS1524
Cable Equalizer. There are on chip 50Ω termination resistors which come to a
common point at the DDI_VT pins. Connect a 10nF capacitor to this pin and
connect the other end of the capacitor to ground. This end-terminates the
transmission line at the inputs for optimum performance.
If only one input pair is used, connect the unused positive inputs to +3.3V and leave
the unused negative inputs floating. This helps to eliminate crosstalk from potential
noise that would couple to the unused input pair.
3.7 Automatic And Manual Data Rate Selection
The GS1535 can be configured to manually lock to a specific data rate or
automatically search for and lock to the incoming data rate. The AUTO_MAN pin
selects Automatic data rate detection mode (AUTO mode) when HIGH and manual
data rate selection mode (MANUAL mode) when LOW.
In AUTO mode, the SS[2:0] bi-directional pins become outputs and the bit pattern
indicates the data rate that the PLL is locked to (or previously locked to). The
"search algorithm" cycles through the data rates (see Figure 3-3) and starts over if
that data rate is not found.
Figure 3-3: Data Rate Search Pattern
NOTE: When the device is in AUTO mode, the SD/HD output will toggle when the
reclocker is not locked, (LD=LOW). The logic level of SD/HD will depend on the
current state of the search algorithm. If the device is also in bypass mode, and the
SD/HD signal is used to set the slew rate of the GS1528 Cable Driver, that slew
rate will change dynamically when the reclocker is not locked.
In MANUAL mode, the SS[2:0] pins become inputs and the data rate can be
programmed. In this mode, the search algorithm is disabled and the GS1535's PLL
will only lock to this data rate.
Table 3-2 shows the bit pattern at SS[2:0] for the data rate selected (in MANUAL
mode) or the data rate that the PLL has locked to (in AUTO mode).
143 Mb\s 177 Mb\s 270Mb\s 360 Mb\s
540 Mb\s1.485Mb\s
POWER-UP
GS1535 Data Sheet
18557 - 8 February 2005 17 of 22
3.8 Bypass Mode
In bypass mode, the GS1535 passes the data at the inputs, directly to the outputs.
There are two pins that control the bypass function: BYPASS and AUTOBYPASS.
The BYPASS pin is an active high signal which forces the GS1535 into bypass
mode for as long as a HIGH is asserted at this pin.
The AUTOBYPASS pin is an active high signal which places the GS1535 into
bypass mode only when the PLL has not locked to a data rate. Note that if
BYPASS is HIGH, this will overwrite the AUTOBYPASS functionallity.
When the GS1535’s PLL is not locked and BYPASS = LOW and AUTOBYPASS =
LOW, the serial digital output DDO/DDO will produce invalid data.
3.9 DVB/ASI Operation
The GS1535 is designed to re-clock DVB/ASI at 270 Mb/s. There is a harmonic
present in idle patterns (K28.5) which is very close the 177 Mb/s data rate (EIC
1179). The ASI/177 pin, when HIGH will disable the 177 Mb/s search in AUTO
mode. In this mode, the GS1535 will not lock to 177 Mb/s.
3.10 LOCK
The LOCK DETECT signal, LD, is an active high output which indicates when the
PLL is locked.
The lock logic with the GS1535 includes a system which monitors the Frequency
Acquisition Loop and the Phase Acquisition Loop as well as a monitor to detect
harmonic lock.
Table 3-2: Data Rate Indication/Selection Bit Pattern
SS[2:0] Data Rate (Mb/s)
000 143
001 177
010 270
011 360
100 540
101 1485/1483.5
GS1535 Data Sheet
18557 - 8 February 2005 18 of 22
3.11 Output Drivers
The GS1535’s serial digital data outputs (DDO/DDO) have a nominal voltage of
800mv single ended or 1600mV differential when terminated into 50Ω.
The DDO_VTT pin is the common point of two 50Ω termination resistors from the
DDO and DDO. This pin can be left open if the termination exists on the receiving
device.
3.12 Output Mute
The DDO_MUTE pin is provided to allow muting of the retimed output.
When the GS1535’s PLL is locked and the device is reclocking, setting
DDO_MUTE = LOW will force the serial digital outputs DDO/DDO to mute.
However, if the GS1535 is in bypass mode, (AUTOBYPASS = HIGH and/or
BYPASS = HIGH), DDO_MUTE will have no effect on the output.
GS1535 Data Sheet
18557 - 8 February 2005 19 of 22
4. Application Reference Design
4.1 Typical Application Circuit
Figure 4-1: Typical Application Circuit
ASI_177
DDI_SEL1
SDO_MUTE
DDI_SEL0
LD
SD/HD
3.3V
3.3V
3.3V
3.3V
10n
10n
10n
10n
47n
GS1535
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
DDI0
DDI0_VT
DDI0
GND
DDI1
DDI1_VT
DDI1
GND
DDI2
DDI2_VT
DDI2
GND
DDI3
DDI3_VT
DDI3
GND
DDI_SEL0
DDI_SEL1
BYPASS
AUTOBYPASS
AUTO/MAN
VCC_VCO
VEE_VC0
SS0
SS1
SS2
ASI/177
LD
RSVD
VCC_DIG
VEE_DIG
GND
SD/HD
KBB
GND
DDO_MUTE
GND
RSVD
RSVD
RSVD
VCC_INT
VEE_INT
GND
DDO
DDO_VTT
DDO
VCC_DDO
VEE_DDO
GND
XTAL_OUT+
XTAL_OUT-
XTAL+
XTAL-
GND
VCC
RSVD
VCC
RSVD
RSVD
VEE_CP
VCC_CP
LF+
LF-
GND
10n
65
10n
(14.140MHz)
10n
10n
10n
DATA INPUT 1
DATA INPUT 0
DATA INPUT 3
DATA INPUT 2
DATA OUTPUT
Zo = 50
Zo = 50
Zo = 50
Zo = 50
Zo = 50
3.3V
3.3V
10n
56
GO1535
Note: All resistors in ohms and all capacitors in Farads.
GS1535 Data Sheet
18557 - 8 February 2005 20 of 22
5. References
Compliant with SMPTE 292M, SMPTE 259M and SMPTE344M.
6. Package & Ordering Information
6.1 Package Dimensions
0
0
0
0
Table X
TOLERANCES OF FORM AND POSITION
SYMBOL
MIN NOM MAX MIN NOM MAX
MILLIMETER INCH
64L
b
e
aaa
ccc
bbb
D2
E2
0.17
0.50 BSC 0.020 BSC
7.50
0.20
0.20
0.08
0.008
0.008
0.003
0.295
0.2957.50
0.20 0.27 0.007 0.008 0.011
NOTE:
Diagram shown is representative only.
Table X is fixed for all pin sizes, and
Table Y is specific to the 64-pin package.
Table Y
GS1535 Data Sheet
18557 - 8 February 2005 21 of 22
6.2 Packaging Data
6.3 Ordering Information
Parameter Value
Package Type 10mm x 10mm 64-pin LQFP
Package Drawing Reference JEDEC MS026
Moisture Saturation Level 3
Junction to Case Thermal Resistance, θj-c 14.9°C/W
Junction to Air Thermal Resistance, θj-a (at zero airflow) 45.4°C/W
Psi 0.9°C/W
Pb-free and Green Yes
Part Number Package Temperature Range Pb-Free And Green
GS1535-CFU 64 pin LQFP 0°C to 70°C No
GS1535-CFUE3 64 pin LQFP 0°C to 70°C Yes
CAUTION
ELECTROSTATIC SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE
EXCEPT AT A STATIC-FREE WORKSTATION
GENNUM CORPORATION
Mailing Address: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Shipping Address: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946
GENNUM JAPAN CORPORATION
Shinjuku Green Tower Building 27F, 6-14-1, Nishi Shinjuku, Shinjuku-ku, Tokyo, 160-0023 Japan
Tel. +81 (03) 3349-5501, Fax. +81 (03) 3349-5505
GENNUM UK LIMITED
25 Long Garden Walk, Farnham, Surrey, England GU9 7HX
Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523
Gennum Corporation assumes no liability for any errors or omissions in this document, or for the use of the
circuits or devices described herein. The sale of the circuit or device described herein does not imply any
patent license, and Gennum makes no representation that the circuit or device is free from patent infringement.
GENNUM and the G logo are registered trademarks of Gennum Corporation.
© Copyright 2002 Gennum Corporation. All rights reserved. Printed in Canada.
www.gennum.com
GS1535 Data Sheet
18557 - 8 February 2005
22
22 of 22
DOCUMENT IDENTIFICATION
DATA SHEET
The product is in production. Gennum reserves the right to make
changes to the product at any time without notice to improve reliability,
function or design, in order to provide the best product possible.
7. Revision History
Version ECR Date Changes and / or Modifications
7 134667 November 2004 Corrected TAC pinout for pins 50, 51. Added
packaging data section. Updated pins 62 and 63 on
the typical application circuit. Converted to new
document template.
8 135363 January 2005 Corrected block diagram and pin description table to
reflect mute functionality of the device.
