HD68000/HD68HCOO0O MPU (Micro Processing Unit) HD68000 The HD68000 is the first in a family of advanced micropro- cessors from Hitachi. Utilizing VLSI technology, the HD68000 is a fully-implemented 16-bit microprocessor with 32-bit registers, a rich basic instruction set, and versatile addressing modes. The HD68000 possesses an asynchronous bus structure with a 24-bit address bus and a 16-bit data bus. FEATURES 32-Bit Data and Address Registers 16 Megabyte Direct Addressing Range 56 Powerful Instruction Types Operations of Five Main Data Types Memory Mapped, 1/0 14 Addressing Modes HD68HC000 The HD68HC000 is a 16-bit microprocessor of HD68000 family, which is exactly compatible with the conventional HD68000. The HD68HC000 is a complete CMOS device and the power dissipation is extremely low. FEATURES Instruction Compatible with NMOS HD68000 @ Pin Compatible with NMOS HD68000 HD68000-8, HD68000-10, HD68000-12 HD68HC000-8, HD68HC000-10, HD68HC000- 12 (0C-64) HD68000Y-8, HD68000Y-10, HD68000Y-12 HD68HCOO0Y-8, HD68HCO00Y-10, HD68HCO00Y-12 (PGA-68) HD68000P-8 HD&8HCOOOP-8, HD68HCO00P-10, HD68HCOO0P-12 @ AC Timing Compatible with NMOS HD68000 @ Low Power Dissipation (icc typ = 20 mA, icc max =35 mA at f = 12.5 MHz) (DP-64) HD68000PS-8 HD68HCOO0PS-8, HD6BHCO00PS-10, HO68HCOOOPS- 12 (DP-64S) HD68000CP-8 HD68HCOO0CP-8, HD68HCO00CP-10, HD68HCOO0CP-12 @ HITACHI Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300 907HD68000/HD68HCO000 = TYPE OF PRODUCTS Type No. Process Crock ency Package HD68000-8 8.0 HD68000-10 10.0 DC-64 HO68000-12, 125 HD68000YS 8.0 HD68000V-10 NMOS 10.0 PGA-68 HD68000vI2~=s| 12.5 HD68000RE8 8.0 DP-64 HD6s000PSss is 8.0 DP-64S HD68000CR8 | 8.0 CP-68 HO68HC000-8 | 8.0 HD68HC000-10 10.0 HD68HC000-12 12.5 DC-64 HD6BHCO00S 8.0 HD6BHCOOOY-10_ | 10.0 PGA-68 HD68HCODO0Y-12 12.5 HD68HCOOORS 8.0 HDG8HCOOOP10 | CMOS 70.0 DP-64 HD6S8HCOOOR12 125 HD68HCOO0OPSss 8.0 HOG8HCOO0PS10 70.0 DP-64S HD6BHCOOOPS12 | 12.5 HD68HCO00CRB 8.0 HD68HCO00CR10 10.0 CP-68 HDG8HCOOOCRI2 | 12.5 {Note} HD68000 refers to the NMOS version 68000, and HD68HCO000 refers to the CMOS version 68000. 68000 stands for NMOS and CMOS version. @ HITACHI 908 Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300@ PIN ARRANGEMENT DC-64, DP-64, DP-64S @ PGA-68 HD62000/HD68HC000 (Top View) 1 PIN (Top View) (Bottom View) $2 53 54 5B 57 58 i] eo 61 62 63 oe LJ Ld 67 Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300 e@ CP-68 BBB sssassaassaae ARABIA AAA RAB DYACKOO] D3 wo = vet as CLK! Vss (6 Aa Ves C22] CSadA2 n/cO PEA Vcc RES CEDIA io VAL Pas eR CABAL, weno PAD As PABA rota Fa, HRARER RR ERR BREE Begg gdte@EIeIZFcE (Top View) @ HITACHI 909HD68000/HD68HC000 ABSOLUTE MAXIMUM RATINGS Item Symbol HD68000 HO6BHCO0O Unit Value Value Supply Voltage Vec* 0.3 ~ +7.0 -0.3 ~ +6.5 Vv input Voltage Vin* 0.3 ~ +7.0 0.3 ~ +6.5 Vv Operating Temperature Range Topr O~ +70 O~ +70 C Storage Temperature Tstg 55 ~ +150 55 ~ +150 "Cc *With respect to Vsg (SYSTEM GND) (NOTE) Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating conditions. If these conditions are exceeded, it could affect reliability of LSI. Since the HDG8HCO000 is a C-MOS device, users are expected to be cautious on latch-up problem caused by voltage fracturations. = RECOMMENDED OPERATING CONDITIONS HD68000 HD68HCO00 . Item Symboi - - Unit min typ max min typ max Supply Voltage Vec* 4.75 5.0 5.25 4.75 5.0 .25 v CLK 2.8 - Vec * 2.0 - Ve Vv Input Voltage Other Inputs Vin ce 2.0 - Vcc All inputs Vin* -0.3 - 0.8 0.3 ~ 0.8 Vv Operating Temperature Topr 0 25 70 0 25 70 c * With respect to Vgg (SYSTEM GND) @ HITACHI 910 Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300HD68000/HD68HC000 @ ELECTRICAL CHARACTERISTICS DC CHARACTERISTICS (Voc = SV + B%, Veg = OV, Ta = 0 ~ +70C, Fig. 1, unless otherwise noted.) HD6 HD68HCO00 Item Symbol | Test Condition - 8000 8 Unit min max min max CLK 28 Veco High Vol A Input High Voltage Other Inputs Vin 2.0 Vee 20 Vor v Input Low Voltage Vir Vss-0.3| 0.8 | Vss-0.3| 0.8 Vv BERR, BACK OR DTACK, Input Leakage Current IPL; VPA, CLK ' @6.26V oe oo oe A put beaxeg ~ RES in {[2{| - | 2 | * AS, Ai~ A23, De Do ~ Dis Three-State (Off State)| go, ~ FC, LDS, R/W, UDS, | Irs, | @2avioav| - | 20| - | 20 | HA Input Current VMA IX Ai ~ Ary BG ,Dg~ : Output High Voltage FCo * ~ FC, LDS, R/W, uot Vou lon =-400uA 2.4 - |Vec-076| - Vv VMA, E E* Vec-075| HALT loL=1.6 mA - 0.5 - 05 Ay ~A23, BG, FCy ~ FC toy 23.2 MA - 0.5 ~ 0.5 Output Low Volt Vv Utput ow MoNege RES OL T75-50mA} - | 05] | 05 V AS, D, Dis, LDS, R/W, E, UDS. aK loL_=5.3 mA - 0.5 - 0.5 =6MHz J CERAMIC PACKAGE = 8 MHz - 15 ae = 10 MHz Power Dissipation Pp f= 12.5 MHz - 1.75 - - Ww f=8MH PLASTIC PACKAGE Vee = SV, _ | o9 Ta = 25C f= 8 MHz - = - 25 Current Dissipation Ip** f= 10 MHz - = - 30 mA f= 12.5 MHz - _ - 35 Capacitance (Package Type Dependent) C; Vin = OV. pacitance (Package Type mere in | Ta= 28C, - |200| - | 200 | pF t= 1MHz *With external pull up resistor of 1.1 k2. ** Without load. +5V +5V +5V 12074(@0 = 7402 or 9102 29k P. est Equivatent RES HALT a 182074 (H) T 70pF 4 Equivalent 4 C, = 130 pF (Includes all Parasitics} R= 60k for AS, A, ~A,,, 8G, D,~D,,, FC,~FC,, LDS, R/W. UDS, VMA *R = 1.22 k2 for A, ~A,,, BG, FC, ~FC, Figure 1 Test Loads @ HITACHI Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300 911HD68000/HD68HCO000 @ AC CHARACTERISTICS (Veg = 5V + 5%, Veg = OV, Ta = 0 ~ +70C, unless otherwise noted.) CLOCK TIMING 8 MHz 10 MHz 12.5 MHz Item Symbol | Test Condition - - - Unit min max min max min max Frequency of Operation f 4.0 8.0 4.0 | 10.0) 40} 12.5 MHz Cycle Time teyc 125 | 250} 100! 250 80 | 250 ns ; tor Fig. 2 55 | 125 45 | 125 35] 125 ns Clock Pulse Width tcH 55| 125| 45| 125] 36 / 125 ns Ri Fall Ti ter - 10 = 10 - 5 ns ise and Falt Times ter ~ 10 _ 10 _ 5 ns teye je te, r ecg wf NO - \_ tc, _~| e pt_- ter (NOTE) Timing measurements are referenced to and from a low voltage of 0.8 volt and high a voltage of 2.0 volts, untess otherwise noted. The voltage swing through this range should start outside and pass through the range such that the rise or fall will be tinear between 0.8 volt and 2.0 voits. Figure 2 Clock input Timing @ HITACHI 912 Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300HD68000/HD68HC000 READ AND WRITE CYCLES Test 8 MHz 10 MHz | 12.6 MHz Num. Item Symbol condition! min! max| min] max] min| max Unit 1 Clock Period teye 126 | 250; 100/ 260| 80 | 250) ns 2 | Clock Width Low teL 66 | 125] 46 | 126) 36 | 125] ns 3 Clock Width High tou 65 | 126| 45 | 126] 35 | 126] ns 4 Clock Fall Time tet - | 10} |{ 10] 5] ons 5 Clock Rise Time ter - 10; {| 10] 5} ons 6 Clock Low to Address Valid tcLav ~ | 70; - | 60] | 55| ns 6A | Clock High to FC Valid tcHFCV - | 70; -| 6) - 55; ns 7 Clock High to Address, Data Bus High Impedance (Maximum) tcHanz - | 80} - 70; | 60! os 8 Clock High to Address, FC Invalid (Minimum) | tonari o|-| 0 -j{ 0 - ns 9' | Clock High to AS, OS Low tous. _| oO | 60; 0 | 55/ 0 | 55 | ns 112. | Address Valid to AS, DS Low (Read)/ AS Low (Write) tAVSL 30; 20; - 0 - ns 11A2 | FC Valid to AS, DS Low (Read)/ AS Low (Write) tFcCvVSL 60; - 50; - 40; - ns 121 | Clock Low to AS, DS High ters _| Fig. 3, | - | 70| | 55) | 50] ns 132 | AS, DS High to Address/FC Invalid tsuari | Fig. 4 30| | 20) | 10] | ns 142 | AS, DS Width Low (Read)/AS Low (Write) ts 240/ | 195} }160| - | ns 14A2 | DS Width Low (Write) tose_| 115] | 95] | 80] | ns 152 | AS, DS Width High toy 150; | 105] | 65| -j ns 16 Clock High to Control Bus High Impedance tcncz - 80; 70} - 60| ns 172 | AS, OS High to R/W High (Read) tsHRH 40| | 20] - | 10] | ns 181 | Clock High to R/W High TCHRH o | 70| 0 | 60} 0 | 60] ns 201 | Clock High to R/W Low (Write) tCHRL ~ | 70] } 60} | 60] ns 20A8 | AS Low to R/W Valid (Write) tasrv ~ | 20/ | 20] - | 20] ns 212 | Address Valid to R/W Low (Write) tAVAL 20; -} o| | Oo} -]| as 212 | FC Valid to R/W Low (Write) tecvAL 60; | 50] { 30] | ns 222 | RAW Low to DS Low (Write) MRLSL 80} | 50] | 30] | ns 23 Clock Low to Data Out Valid (Write) tcLDo - 70) - 55] 55} ns 252 | AS, DS High to Data Out Invalid (Write) tsHpol | 3o| - | 20] - | 15| -| ns 262 | Data Out Valid to DS Low (Write) tposi. 30| | 20} - | 15] | ns 278 Data In to Clock Low (Setup Time on Read) toicn_| 15} 10| 10{ ns 282 | AS, DS High to DTACK High tsHDAH 0 | 245] 0 | 190] 0 | 150] ns 29 | AS, DS High to Data In Invalid (Hold Time on Read) tsHoU 0 - 0 - 0 - ns 30 | AS, DS High to BERR High tSHBEH o}/-|oj-|{ oj] -| ns 312.5) BTACK Low to Data In (Setup Time) toavol | 90] | 65) | 50! ns 32 | HALT and RESET Input Transition Time tr, t 0 | 200} 0 | 200} 0 | 200] ns 33 | Clock High to BG Low tCHGL - {| 70! | 60} - | 50! ns 34 | Clock High to BG High tCHGH | 70} | 60] | 50] ns 90 70 35 | BR Lowto BG Low tBRLGL 1.5 43 1.5 +5 15 as Clk. * 67 for HDG8HC000 @ HITACHI Hitachi America, Ltd. e Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300 913HD68000/HD68HC000 READ AND WRITE CYCLES (CONTINUED) Test 8 MHz 10 MHz 12.5 MHz Num. Item Symbol ve Unit " y Condition | min| max | min| max | min| max 7 BBL Baw 90ns 80ns 70ns 36 BR High to BG High IBRHGH 1.5 $3.5 15 +35 1.5 +35 Cik.Per. RW / + Tire 86 e@ DTACK OT _ Data Out b} I tte =I @ BERR/EA @ (Note 2) i= @ HALT/RESET Asynchronous ~~ r@ inputs (Note 1) NOTES: 1. Timing measurements are referenced to and from a tow voltage of 0.8 volt and a high voltage of 2.0 voits, unless otherwise noted. The voltage swing through this range should start outside and pass through the range such that the rise or fal! will be linear between 0.8 volt and 2.0 volts. 2, Because of loading variations, R/W may be valid after AS even though both are initiated by the rising edge of S2 (Specification 20A). Figure 4. Write Cycle Timing @ HITACHI 916 Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300HD68000/HD68HC000 @ HMCS6800 TIMING Test 6 MHz 8 MHz 10 MHz | 12.5 MHz Num. Item Symbol . Unit Condition| min | max| min{ max} min} max{ min | max 12 | Clock Low to AS, DS High tcLsH {| soi | 70} | 55} | 50] ns 18 Clock High to R/W High tCHRH 0 80; 0 70; 0 60) 0 60| ns 20 | Clock High to R/W Low (Write) tCHAL ~ | 80} | 70] | 60] - |; 60/ ns 23 Clock Low to Data Out Valid (Write) tcLDo - 80; 70| 56, 5| ns 27 Data In to Clock Low (Setup Time on Read) tore 25) 15] - 10} 10| - ns 29 | AS, DS High to Data in Invalid (Hold Time on Read) ISHDI! Fig. 5, | O}| } O|] -]| O -| 0 - ns 40 | Clock Low to VMA Low tcLvm_| Fig.6 | | 80) | 70; |] 70] | 70) ns 41 Clock Low to E Transition tCLET {| 35} | 70] ]| 55] | 45] ans 42 E Output Rise and Fall Time ter _ | - 25| 25/ - 25{ 25] ns 43 | VMA Low to E High tVMLEH 240; | 200] | 150] - } 90; ns 44 KS. BS High to VPA High tsHVPH 0 | 160} O | 120; 0 90] 0 70| ns 45 E Low to Contro!, Address Bus Invalid tELCAl 35; - 30; - 10} 10| - ns (Address Hold Time) 47 Asynchronous Input Setup Time tas! 25; | 20] - 20! ~j}| 20] - ns 49' | AS, DS High to E Low tSHEL 80; |-70| 70] -55| 55] -45) 45] ns 50 E Width High ten 600); | 450; | 350) | 280) ns 51 | E Width Low TEL 900/ | 700] ~ | 650] | 440/ - | ns 54 Low to Data Out Invalid tELDol 40} - 30; | 20] - 16] - ns NOTE: 1. The falling edge of S6 triggers both the negation of the strobes (AS and xDS) and the falling edge of E. Either of these events can occur first, depending upon the loading on each signal. Specification #49 indicates the absolute maximum skew that will occur between the rising edge of the strobes and the falling edge of the E clock. SO $1 $253 S4 ww www www w w w w SS S6 S7 SO CLK @ @ NOTE: This timing diagram is included for those who wish to design their own circuit to generate VMA. it shows the best case possibly attainable. Figure 5. HD6800 TimingBest Case @ HITACHI Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300 917HD68000/HD68HC000 SO S1S2 S3S4 ww wwww ww ww www www w www ww ww ww w w S$6S6 S750 CLK A1-Az RW Date Out @ Data tn NOTE: This timing diagram is included for those who wish to design their own circuit to generate VMA. It shows the worst case possibly attainable. Figure 6. HD6800 TimingWorst Case BUS ARBITRATION Test 8 MHz 10 MHz | 12.5 MHz Num. Item Symbol , Unit Condition! min{ max |min | max | min| max 7 Clock High to Address, Data Bus High Impedance tcHADZ - 80 | - 70) - 60} ns 16 Clock High to Control Bus High Impedance tcHcz -}] 80/ - |; 70] - 60| ns 33 | Clock High to BG Low tcHGL - | 70} - ; 60] | SO] ns 34 | Clock High to BG High tcHGH ~ | 70} - | 60; | 50] as a5 BR | 901 80: 7 35 | BA Low to BG Low teRLGL 1.5 | 2s) 1.5 | 2005) 1.5) 70S Per 361 | BR High to BG High tBaHGH 1.5 | 2005) 1.5 | BONS 1.51 708SIch Per ae Fig. 7~ 90ns 80ns 70ns 37 BGACK Low to BG High tGALGH Fig. 9 15 43.5 1.5 43.5 1.5 43.5 Ck. Per. 37A2 | BGACK Low to BR High tGALARH 20 | oh 541 20 bie) 20 [ofS ns 38 | BG Low to Control, Address, Data _ _ _ Bus High Impedance (AS High) teLz 80 70 60 | ns 39 BG Width High ten 15); - $1.5; - | 1.5] |OkPer. 46 BGACK Width Low IGAL 1.6; - |1.5; - 7 1.5] |Chk.Per. 47 Asynchronous Input Setup Time tast 20; ~ |}20 | - | 20] - ns 57 BGACK High to Control! Bus Driven tcaBD 16) [15] - | 1.5] |Clk-Per 581! | BG High to Control Bus Driven tcHap 15] - |1.5] | 1.5] (Chk.Per. NOTES: 1. The processor will negate BG and begin driving the bus again if external arbitration logic negates BR before asserting BGACK. 2. The minimum vatue must be met to guarantee proper operation. !f the maximum value is exceeded, BG may be reasserted. @ HITACHI 918 Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300Figures 7, 8, and 9 depict the three bus arbitration cases that can arise. Figure 7 shows the timing where AS is negated when the processor asserts BG (Idle Bus Case). Figure 8 shows the timing where AS is asserted when the processor asserts BG (Active Bus Case). Figure 9 shows the timing where more than one bus master are requesting the bus. Refer to Bus Arbitration for a complete discussion of bus arbitration. CLK BGACK AS Ups/0Ds VMA RW FCoFC2 A1Ag3a DoDis HD68000/HD68HC000 The waveforms shown in Figures 7, 8, and 9 should only be referenced in regard to the edge-to-edge measurement of the timing specifications. They are not intended as a functional description of the input and output signals. Refer to other func- tional descriptions and their related diagrams for device opera- tion. Figure 7. Bus Arbitration Timing Diagram Idle Bus Case @ HITACHI Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300 919HD68000/HD68HC000 RW FCo-FC, Al-Ag Do-D1s so Si S2 -@ > - > Figure 8. Bus Arbitration Timing Diagram Active Bus Case cLK @ aR A A A @! p+ 1+ 4 e| 8 e-~ BG \ -_ oS @ oe @ _ 8, 3 GACK ry pb @--+ @| tos/uos 4 VA 4, aw 4, FCo-FC, 4 Ai-An 4 Oo-Dys 4 Figure 9. Bus Arbitration Timing Diagram Multiple Bus Requests 920 @ HITACHI Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300 INTRODUCTION As shown in the programming model, the 68000 offers seven- HD68000/HD68HCO000 Programming Model 1 1 teen 32-bit registers in addition to the 32-bit program counter r 1s = St S50 and a 16-bit status register. The first eight registers (DO ~ D7) - | | o1 are used as data registers for byte (8-bit), word (16-bit), and ~ \ t o2 long word (32-bit) data operations. The second set of seven - ' Hos Eight registers (AO ~ AG) and the system stack pointer may be used \ | 7 Date as software stack pointers and base address registers. In addi- = ! I 404 Frogisters tion, these registers may be used for word and long word L | ! a address operations. All 17 registers may be used as index regis- L | 6 ters. i i D7 The status register contains the interrupt mask (eight levels 31 1615 0 available) as well as the condition codes; extend (X), negative ' AO (N), zero (Z), overflow (V), and carry (C). Additional status a Ja bits indicate that the processor is in a trace (T) mode and/or \ Ta2 seven in a supervisor (S) state. - | |. Address a | _JA3 Registers Status Register | ! 4 ' _|45 i AG User Byte System Byte (Condition Code Register) fn YN \ User Stack Pointer 1, 7 Two Stack 15 4.3.2, 10 ' Supervisor Stack Pointer } Pointers PI: TE PEP] ARE _. Trace Mode | Extend beececes 15 87 0 Counter Supervisor Negative Aauter State Interrupt Zero Mask Overflow Table 1 Addressing Modes Carry Unused, read as zero. Mode Generation Register Direct Addressing Data Regifter Diredt EA=Dn DATA TYPES AND ADDRESSING MODES Address Register Direct EA=An Five basic data types are supported. These data types are: Absolute Data Addressing (i) Bits Absolute Short = (Next Word) (2) BCD Digits (4 bits) Absolute Long = (Next Two Words) (3) Bytes (8 bits) Program Counter Relative Addressing (4) Word (16 bits) Relative with Offset = (PC) + dis (5) Long Words (32 bits) Relative with Index and Offset = (PC) + (Xn) + de In addition, operations on other data types such as memory Register indirect Addressing address, status word data, etc., are provided for in the instruc- Register indirect = (An) tion set. Postincrement Register Indirect = {AN}, An FFFF LW. 7 Absolute Not Instruction Short NOT.L $2000 owt . OWL +2 EXAMPLE COMMENTS @ EA = (Next Word) MPU MEMORY 16-Bit Word is Sign Extended $1000 1234 Machine Level Coing <>} MOVE $1000, $2000 $2000 13a 2 0011 0001 1111 1000 Move Absolute lor: { Short Absolute Short OWL OWL +2 OWL +4 MOVE $1000, $2000 HITACHI 930 Hitachi America, Ltd. * Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 * (415) 589-8300Absolute Long Address This address mode requires two words of extension. The address of the operand is developed by the concatenation of the extension words. The high-order part of the address is the HD68000/HD68HC000 first extension word; the low-order part of the address is the second extension word. The reference is classified as a data reference with the exception of the jump and jump to sub- routine instructions. EXAMPLE COMMENTS EA = (Next Two Words) MPU MEMORY 1 $14000 | 0001 ~ FFFF @ Machine Level Coding NEG $014000 Q100 0100 0111 1001 bE NEG "7 Absolute OU Instruction Long OWL +2 NEG $014000 OWL OWL +4 Program Counter With Displacement This address mode requires one word of extension. The address of the operand is the sum of the address in the program counter and the sign-extended 16-bit displacement integer in the extension word. The value in the program counter is the ad- dress of the extension word. The reference is classified as a pro- gram reference. EXAMPLE COMMENTS @ EA = (PC) + dic MPU MEMORY @ dig is Sign Extended @ Machine Level Coding I MOVE (LABEL), 90 XXXXABCD] DO 0011 0000 0011 1010 PC with $8000 303A Move Data Displacement Word = Register $8002 1000 Direct MOVE (LABEL), DO ADDRESS CALCULATION: PC = 00008002 L d = 00001000 eK A 90009002 LABEL > $9002 BCD a @ HITACHI Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300 931HD68000/HD68HC000 Program Counter With Index This address mode requires one word of extension. This address is the sum of the address in the program counter, the Sign-extended displacement integer in the lower eight bits of the extension word, and the contents of the index register. The value in the program counter is the address of the extension word. This reference is classified as a program reference. EA = (PC) + (Rx) +d, Instruction m~_ ~~ PC Value (NOTE) Extension Word 1 14 13 121110 9 8 7 6 5 4 3 21 0 pial Register [we] 0 | 0 | 0 | Displacement Integer | DIA : Data Register = 0, Address Register = 1 | PC +d, # Data Table Register : Index Register Number 932 pxa W/t : Sign-extented, low order Word integer able i i Desired Data in Index Register = 0 Location in Table } PC +d, + Rx Long Word in Index Register = 1 EXAMPLE COMMENTS @ EA = (PC) + (Rx) + ds MPU MEMORY Where PC Current Program Counter a, Rxe Designated Index Register {Either Data or Address Register) d. e8-Bit Displacement XXXXI456] DO $8000 3038 # Rx and dy are Sign Extended $8002 8010 @ Rx may be Word or Long Word (00001010) AO Long Word is Designated with Rx.L. @ Machine Level Coding