NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no respon-
sibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
Recommended Substitutions:
Automotive DMOS Microstepping Driver with Translator
A3980
For existing customer transition, and for new customers or new appli-
cations, refer to the A3981.
Date of status change: November 17, 2011
These parts are in production but have been determined to be
NOT FOR NEW DESIGN. This classification indicates that sale of
this device is currently restricted to existing customer applications.
The device should not be purchased for new design applications
because obsolescence in the near future is probable. Samples are no
longer available.
Not for New Design
Description
The A3980 is a complete microstepping motor driver with
built-in translator for easy operation. It is designed to operate
bipolar stepper motors in full-, half-, eighth-, and sixteenth-
step modes, at up to 35 V and ±1 A. The A3980 includes a
fixed off-time current regulator which has the ability to operate
in slow, fast, or mixed decay modes. This results in reduced
audible motor noise, increased step accuracy, and reduced
power dissipation.
The translator is the key to the easy implementation of the
A3980. Simply inputting one pulse on the step input drives
the motor one microstep. There are no phase sequence tables,
high frequency control lines, or complex interfaces to program.
The A3980 interface is an ideal fit for applications where a
complex P is unavailable or overburdened.
Internal synchronous rectification control circuitry is provided
to improve power dissipation during PWM operation.
Internal circuit protection includes: thermal shutdown with
hysteresis, overvoltage lockout (OVLO), undervoltage lockout
(UVLO), and crossover current protection. Special power-up
sequencing is not required. In addition, two diagnostic fault flags
provide indication of shorts or opens on the motor windings.
The A3980 is supplied in a low-profile (1.1 mm) 28L TSSOP
with exposed thermal pad. This device is lead (Pb) free, with
100% matte tin leadframe plating.
26184.26H
Features and Benefits
Typical application up to ±1 A, 35 V output rating
Low RDS(ON) outputs, 0.67 source, 0.54 sink typical
Automatic current decay mode detection/selection
3.0 V to 5.5 V logic supply voltage range
Mixed, fast, and slow current decay modes
Synchronous rectification for low power dissipation
Internal OVLO, UVLO, and thermal shutdown circuitry
Crossover current protection
Short to supply/ground and short/low load current
diagnostics
Automotive DMOS Microstepping Driver with Translator
Package: 28 pin TSSOP with exposed
thermal pad (suffix LP)
Typical Application
Approximate Size
A3980
Automotive DMOS Microstepping Driver
with Translator
A3980
2
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Selection Guide
Part Number Packing
A3980KLPTR-T 4000 pieces per reel
Absolute Maximum Ratings
Characteristic Symbol Notes Rating Units
Load Supply Voltage VBB 500 ms 50 V
Logic Supply Voltage VDD 7.0 V
Logic Input Voltage VIN
–0.3 to VDD + 0.3 V
(tW < 30 ns) –1.0 to VDD + 1 V
Sense Voltage VSENSE 0.5 V
Reference Voltage VREF 0 to VDD V
Operating Ambient Temperature TARange K –40 to 125 °C
Maximum Junction Temperature TJ(max) 150 °C
Storage Temperature Tstg
–55 to 150 °C
ESD Rating - Human Body Model AEC-Q100-002, all pins
2.0 kV
ESD Rating - Charged Device Model AEC-Q100-011, all pins
1.0 kV
Thermal Ratings
Characteristic Symbol Test Conditions* Value Units
Package Thermal Resistance RJA
2-layer PCB with 3.8 in.2 of copper area each side
connected by thermal vias 32 ºC/W
4-layer PCB based on JEDEC standards 28 ºC/W
*Additional thermal information available on Allegro Web site.
Automotive DMOS Microstepping Driver
with Translator
A3980
3
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Functional Block Diagram
SENSE1
SENSE2
VREG
VCP
CP1
AGND
Control
Logic
PFD
VBATT
5 V
DAC
VREF
VDD
PWM Latch
Blanking
Mixed Decay
RT2 CT2
RC2
SR
SLEEP
ENABLE
DAC
STEP
DIR
MS1
MS2
PWM Latch
Blanking
Mixed Decay
RC1
RT1 CT1
SENSE 1
SENSE 2
REF
Voltage
Regulator
CP2
Charge
Pump
CCP
RS1
RS2
VBB1
OUT1A
OUT1B
VBB2
OUT2A
OUT2B
CCS
PGND
VDD
VCP
VBB
OUT2A/2B
SENSE1
SENSE2
OVLO
UVLO
OVERTEMP
SHORT SENSE
OPEN SENSE
FF1 FF2
OUT1A/1B
VREF
Translator
Gate
Drive DMOS Full Bridge
DMOS Full Bridge
Automotive DMOS Microstepping Driver
with Translator
A3980
4
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
ELECTRICAL CHARACTERISTICS at TJ = –40°C to +150ºC, VBB = 14 V, VDD = 3.0 to 5.5 V (unless otherwise noted)
Characteristics Symbol Test Conditions Min. Typ.1Max. Units
Output Drivers
Load Supply Voltage Range VBB
Driving
Operating
Sleep mode
8
7
0
–
VOVB
50
35
V
Output Leakage Current2IDSS
VOUT = VBB
VOUT = 0 V –< 1.0
< 1.0
20
–20 μA
Output-On Resistance RDSON
Source driver, IOUT = –1 A, TA < 25ºC
Sink driver, IOUT = 1 A, TA < 25ºC –0.51
0.45
0.86
0.65
Source driver, IOUT = –1 A, TA < 125ºC
Sink driver, IOUT = 1 A, TA < 125ºC –0.87
0.72
1.06
0.83
Body Diode Forward Voltage VF
Source diode, IF = –1 A
Sink diode, IF = 1 A ––
1.4
1.4 V
Motor Supply Current IBB
fPWM < 50 kHz
Operating, outputs disabled
Sleep mode
––
8
6
20
mA
mA
μA
Logic Supply Current IDD
fPWM < 50 kHz
Outputs off
Sleep mode
––
12
10
20
mA
mA
μA
Logic Interface
Logic Supply Voltage Range VDD Operating 3.0 5.0 5.5 V
Input Low Voltage VIL –––
0.3 VDD V
Input High Voltage VIH –0.7 VDD ––
V
Input Hysteresis VIHYS –200 300 500 mV
Input Current2IIN ––20 < ±1 20 μA
Output Low Voltage VOL IO = 3 mA ––
0.4 V
Output High Voltage VOH IO = –200 μA 2.8 ––
V
STEP Pin Low tSTPL –1––
μs
STEP Pin High tSTPH –1––
μs
Setup Time for Input Change to STEP tSU MS1, MS2, DIR 200 ––
ns
Hold Time for Input Change from STEP tHMS1, MS2, DIR 200 ––
ns
Wake-Up Time from SLEEP tEN –––
1ms
Continued on next page
Automotive DMOS Microstepping Driver
with Translator
A3980
5
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Characteristics Symbol Test Conditions Min. Typ.1Max. Units
Current Control
Blank Time tBLANK RT = 56 K , CT = 680 pF 700 950 1200 ns
Fixed Off Time tOFF RT = 56 K , CT = 680 pF 30 38 46 μs
Mixed Decay Trip Points PFDH
PFDL––
0.60 VDD
0.21 VDD –V
Crossover Dead Time tDT –100 475 800 ns
Recommended Reference Input Voltage VREF –0.8 –4V
Reference Input Current2IREF ––3 0 3 μA
Current Trip-Level Error3errI
2 V < VREF < 4 V, %ITripMAX = 38%
2 V < VREF < 4 V, %ITripMAX = 70%
2 V < VREF < 4 V, %ITripMAX = 100%
––
±15
±10
±5
%
Thermal Protection
Thermal Shutdown TSD –160 170 180 ºC
Thermal Shutdown Hysteresis TSDH ––
15 –ºC
Diagnostics
Max VDS on High-Side Bridge FETs VDSHT Sampled after tBLANK + tSCT –1.5 –V
Max VDS on Low-Side Bridge FETs VDSLT Sampled after tBLANK + tSCT –1.5 –V
VDS Fault Measurement Delay tSCT ––
700 –ns
Minimum Load Current IOC w.r.t. ITRIPMAX at Home position –35 –%
VBB Overvoltage Lockout VOVB VBB rising 32 34 36 V
VBB Overvoltage Lockout Hysteresis VOVBH –2–4V
VREG Undervoltage Lockout VUVR VREG falling 5.3 5.7 6.0 V
VDD Enable Threshold VUVD VDD rising 2.45 2.7 2.95 V
VDD Enable Threshold Hysteresis VUVDH –50 100 –mV
ELECTRICAL CHARACTERISTICS (continued) at TJ = –40°C to +150ºC, VBB = 14 V, VDD = 3.0 to 5.5 V (unless otherwise noted)
1Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary
for individual units, within the specifi ed maximum and minimum limits.
2Negative current is defi ned as coming out of (sourcing from) the specifi ed device pin.
3errI = (ITrip – IProg
) ⁄ IProg
, where IProg = %ITripMAX× I TripMAX.
Automotive DMOS Microstepping Driver
with Translator
A3980
6
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Logic Interface Timing Diagram
STEP
tSTPL
tSTPH
tH
tSU
SLEEP
tEN
MS1, MS2,
or DIR
MS1 MS2 Microstep Resolution
L L Full Step
H L Half Step
L H Eighth Step
H H Sixteenth Step
Table 1. Microstep Resolution Truth Table
FF1 FF2 Fault
LLUVLO, OVLO, Overtemperature,
Low Load Current, or Shorted Load
H L Short to Ground
L H Short to Supply
H H None
Table 2. Fault Report by Fault Flags
Automotive DMOS Microstepping Driver
with Translator
A3980
7
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Table 3. Step Sequencing Settings
Home microstep position at Step Angle 45º; DIR = H
Full
Step
#
Half
Step
#
1/8
Step
#
1/16
Step
#
Phase 1
Current
[% ItripMax]
(%)
Phase 2
Current
[% ItripMax]
(%)
Step
Angle
(º)
Full
Step
#
Half
Step
#
1/8
Step
#
1/16
Step
#
Phase 1
Current
[% ItripMax]
(%)
Phase 2
Current
[% ItripMax]
(%)
Step
Angle
(º)
1 1 1 100.00 0.00 0.0 5 17 33 –100.00 0.00 180.0
2 99.52 9.80 5.6 34 –99.52 –9.80 185.6
2 3 98.08 19.51 11.3 18 35 –98.08 –19.51 191.3
4 95.69 29.03 16.9 36 –95.69 –29.03 196.9
3 5 92.39 38.27 22.5 19 37 –92.39 –38.27 202.5
6 88.19 47.14 28.1 38 –88.19 –47.14 208.1
4 7 83.15 55.56 33.8 20 39 –83.15 –55.56 213.8
8 77.30 63.44 39.4 40 –77.30 –63.44 219.4
1 2 5 9 70.71 70.71 45.0 3 6 21 41 –70.71 –70.71 225.0
10 63.44 77.30 50.6 42 –63.44 –77.30 230.6
6 11 55.56 83.15 56.3 22 43 –55.56 –83.15 236.3
12 47.14 88.19 61.9 44 –47.14 –88.19 241.9
7 13 38.27 92.39 67.5 23 45 –38.27 –92.39 247.5
14 29.03 95.69 73.1 46 –29.03 –95.69 253.1
8 15 19.51 98.08 78.8 24 47 –19.51 –98.08 258.8
16 9.80 99.52 84.4 48 –9.80 –99.52 264.4
3 9 17 0.00 100.00 90.0 7 25 49 0.00 –100.00 270.0
18 –9.80 99.52 95.6 50 9.80 –99.52 275.6
10 19 –19.51 98.08 101.3 26 51 19.51 –98.08 281.3
20 –29.03 95.69 106.9 52 29.03 –95.69 286.9
11 21 –38.27 92.39 112.5 27 53 38.27 –92.39 292.5
22 –47.14 88.19 118.1 54 47.14 –88.19 298.1
12 23 –55.56 83.15 123.8 28 55 55.56 –83.15 303.8
24 –63.44 77.30 129.4 56 63.44 –77.30 309.4
2 4 13 25 –70.71 70.71 135.0 4 8 29 57 70.71 –70.71 315.0
26 –77.30 63.44 140.6 58 77.30 –63.44 320.6
14 27 –83.15 55.56 146.3 30 59 83.15 –55.56 326.3
28 –88.19 47.14 151.9 60 88.19 –47.14 331.9
15 29 –92.39 38.27 157.5 31 61 92.39 –38.27 337.5
30 –95.69 29.03 163.1 62 95.69 –29.03 343.1
16 31 –98.08 19.51 168.8 32 63 98.08 –19.51 348.8
32 –99.52 9.80 174.4 64 99.52 –9.80 354.4
Automotive DMOS Microstepping Driver
with Translator
A3980
8
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Mixed Mixed
Slow Slow
Mixed Slow Mixed Slow
0.00
100.00
92.39
70.71
55.56
–55.56
83.15
–83.15
38.27
19.51
–19.51
–38.27
–70.71
–92.39
–100.00
0.00
100.00
92.39
70.71
55.56
–55.56
83.15
–83.15
38.27
19.51
–19.51
–38.27
–70.71
–92.39
–100.00
Phase 2
I
OUT2B
Direction = H
(%)
Phase 1
I
OUT1B
Direction = H
(%)
Home Microstep Position
STEP
100.00
70.71
–70.71
–100.00
100.00
70.71
–70.71
–100.00
Phase 2
I
OUT2B
Direction = H
(%)
Phase 1
I
OUT1B
Direction = H
(%)
Home Microstep Position
100.00
70.71
–70.71
–100.00
100.00
70.71
–70.71
–100.00
Phase 2
I
OUT2B
Direction = H
(%)
Phase 1
I
OUT1B
Direction = H
(%)
Home Microstep Position
Figure 6. Half Step
Figure 7. Eighth Step
Figure 5. Full Step
Automotive DMOS Microstepping Driver
with Translator
A3980
9
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Figure 8. Sixteenth Steps
MixedSlow MixedSlow
MixedSlow Slow
Slow
100.00
95.69
88.19
83.15
–83.15
77.30
70.71
63.44
55.56
47.14
38.27
29.03
19.51
9.8
0.00
–100.00
–95.69
–88.19
–77.30
–70.71
–63.44
–55.56
–47.14
–38.27
–29.03
–19.51
–9.8
100.00
95.69
88.19
83.15
–83.15
77.30
70.71
63.44
55.56
47.14
38.27
29.03
19.51
9.8
0.00
–100.00
–95.69
–88.19
–77.30
–70.71
–63.44
–55.56
–47.14
–38.27
–29.03
–19.51
–9.8
Phase 2
I
OUT2B
Direction = H
(%)
Phase 1
I
OUT1B
Direction = H
(%)
Home Microstep Position
Mixed
STEP
Automotive DMOS Microstepping Driver
with Translator
A3980
10
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Device Operation. The A3980 is a complete microstep-
ping motor driver with a built-in translator for easy operation
with minimal control lines. It is designed to operate bipolar
stepper motors in full-, half-, eighth-, and sixteenth-step
modes. The currents in each of the two output full-bridges
and all of the N-channel DMOS FETs are regulated with
fi xed off-time PMW (pulse width modulated) control cir-
cuitry. At each step, the current for each full-bridge is set by
the value of its external current-sense resistor (RS1 or RS2), a
reference voltage (VREF), and the output voltage of its DAC
(which in turn is controlled by the output of the translator).
At power-up, the translator resets to the Home state, in which
the motor is driven to the Home microstep position, where
both phase currents are set to +70%. Then the translator sets
the voltage regulator to mixed decay mode for both phases.
When a step command signal occurs on the STEP input, the
translator automatically sequences the DACs to the next
level and current polarity. (See table 3 for the current-level
sequence.) The microstep resolution is set by the combined
effect of inputs MS1 and MS2, as shown in table 1.
When stepping, if the new output levels of the DACs are
lower than their previous output levels, then the decay mode
(fast, slow, or mixed decay) for the active full-bridge is set
by the PFD input. If the new output levels of the DACs are
higher than or equal to their previous levels, then the decay
mode for the active full-bridge is set to slow decay. This
automatic current decay selection improves microstepping
performance by reducing the distortion of the current wave-
form that results from the back EMF of the motor.
Home Microstep Position. At power-up, or after
a UVLO (undervoltage lockout) condition caused by low
voltage on VDD, the translator in the A3980 resets the motor
to the Home microstep position. This corresponds to the 45°
position, which is the step where both phase currents are
+70%. Referring to table 3, for full-step mode this is step
1, for half-step this is step 2, for eighth-step this is step 5,
and for sixteenth-step this is step 9. In table 3 and fi gures 5
through 8, the Home microstep position is indicated.
Step Input (STEP). A low-to-high transition on the STEP
input sequences the translator and advances the motor one
increment. The translator controls the input to the DACs and
the direction of current fl ow in each winding. The size of
the increment is determined by the combined state of inputs
MS1 and MS2.
Microstep Select (MS1 and MS2). Selects the micro-
stepping format, as shown in table 1. Any changes made to
these inputs do not take effect until the next STEP rising edge.
Direction Input (DIR). This determines the direction of
rotation of the motor. When low, the direction will be clock-
wise and when high, counterclockwise. Changes to this input
do not take effect until the next STEP rising edge.
Internal PWM Current Control. Each full-bridge is
controlled by a fi xed off-time PWM current control circuit
that limits the load current to a desired value, ITRIP. Initially,
a diagonal pair of source and sink DMOS FETs are enabled
and current fl ows through the motor winding and the current
sense resistor, RS. When the voltage across RS equals the
DAC output voltage, the current sense comparator resets the
PWM latch. The latch then turns off either the source DMOS
(when in slow decay mode) or the sink and source DMOSs
(when in fast or mixed decay modes).
The transconductance function is approximated by the maxi-
mum value of current limiting, ITripMAX (A), which is set by
ITripMAX = VREF ⁄ (8
R S)
where RS is the resistance of the sense resistor () and VREF
is the input voltage on the REF pin (V).
The DAC output reduces the VREF output to the current
sense comparator in precise steps, such that
Itrip = (%ITripMAX ⁄ 100) × ITripMAX
(See table 3 for %ITripMAX at each step.)
It is critical that the maximum rating (0.5 V) on the SENSE
pin is not exceeded. For full-step mode, VREF can be applied
up to the maximum rating of VDD, because the peak sense
value is 70% of maximum:
VREF × (0.707 ⁄ 8)
Functional Description
Automotive DMOS Microstepping Driver
with Translator
A3980
11
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
as shown in table 3. In all other modes, VREF should not be
allowed to exceed 4 V, because the peak sense value can
reach VREF ⁄ 8, or 100%.
Fixed Off-Time. The internal PWM current control
circuitry uses a one-shot circuit to control the duration of
time that the DMOS FETs remain off. The one shot off-time,
tOFF, is determined for each of the two phases by the combi-
nation of an external resistor (RT) and a capacitor (CT). One
combination is connected from the timing terminal RC1 to
ground, and the other similarly connected to RC2 . tOFF (ns)
is approximated by
tOFF = RT × CT
over a range of values from CT= 470 pF to 1500 pF and from
RT = 12 k to 100 k.
RC Blanking. In addition to the fi xed off-time of the
PWM control circuit, the CT component sets the comparator
blanking time. This function blanks the output of the current
sense comparators when the outputs are switched by the
internal current control circuitry. The comparator outputs are
blanked to prevent false overcurrent detection due to reverse
recovery currents of the clamp diodes, and switching tran-
sients related to the capacitance of the load. The blank time,
tBLANK (ns), can be approximated by
tBLANK = 1400
× CT
where CT is the value of the capacitor CT (nF).
The blank time should be as short as possible, without caus-
ing a false fault detection, to ensure that power dissipation
during a fault condition is minimized. The blank time also
defi nes the minimum duration of time that the full-bridge
DMOS outputs cause the load current to rise. To ensure
correct detection of motor faults, the minimum on-time is
extended by an additional fault sampling time, tSCT. The
minimum on-time, tMINON is then
tMINON = tBLANK + tSCT
Charge Pump (CP1 and CP2). The charge pump is
used to generate a gate supply greater than that of VBB for
driving the source-side DMOS gates. A 100 nF ceramic
capacitor (CCP), capable of withstanding the battery volt-
age VBATT, should be connected between CP1 and CP2.
In addition, a 100 nF ceramic capacitor (CCS)is required
between VCP and VBB, to act as a reservoir for operating
the high-side DMOS devices. The voltage on CCS is limited to
the charge pump voltage, which is always less than 10 V.
VREG (VREG). This internally-generated voltage is used
to operate the sink-side DMOS FETs. The VREG terminal
must be decoupled with a 220 nF (10V) capacitor to ground.
VREG is internally monitored. In the case of a fault condi-
tion, the DMOS outputs of the A3980 are disabled.
Enable Input (ENABLE). This input simply turns off all
of the DMOS outputs. When set to a logic high, the outputs
are disabled. When set to a logic low, the internal control
enables the outputs as required. The translator inputs (STEP,
DIR, MS1, and MS2), as well as the internal sequencing
logic, all remain active, independent of the ENABLE input
state.
Sleep Mode (SLEEP). To minimize power consumption
when the motor is not in use, this input disables much of the
internal circuitry including the output DMOS FETs, voltage
regulator, and charge pump. A logic low on the SLEEP termi-
nal puts the A3980 into Sleep mode. A logic high allows nor-
mal operation, as well as start-up (at which time the A3980
drives the motor to the Home microstep position). If the
A3980 comes out of Sleep mode when VBB is greater than
VOVB – VOVBH and less than VOVB
, the A3980 will remain
in safety mode until VBB is reduced below VOVB - VOVBH.
Percent Fast Decay Input (PFD). When a STEP input
signal commands an output current level that is lower than
that of the previous step, it switches the output current decay
to slow, fast, or mixed decay mode, depending on the voltage
level at the PFD input, as shown in the following table.
Lower PFD Input
Voltage Level Decay Mode
VPFD > (0.6 × VDD )Slow
(0.21 × VDD ) VPFD (0.6 × VDD ) Mixed
VPFD < (0.21 × VDD) Fast
Automotive DMOS Microstepping Driver
with Translator
A3980
12
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Mixed Decay Operation. Depending on the step
sequence, if the voltage on the PFD pin is between
0.6 × VDD and 0.21 × VDD, the full-bridge can operate
in mixed decay mode, as shown in fi gures 5 through 8.
As the trip point is reached, the A3980 goes into fast
decay mode until the voltage on the RC pin decays to
the same level as the voltage applied to the PFD pin. The
duration of time that the bridge operates in fast decay
mode, tFD (ns), is estimated by
tFD = RT × CT × ln[0.6 (VDD ⁄ VPFD)]
over a range of values from CT= 470 pF to 1500 pF and
from RT = 12 k to 100 k.
After this fast decay period, the A3980 switches to slow
decay mode for the remainder of the fi xed off-time
period.
Synchronous Rectifi cation. When a PWM-off
cycle is triggered by an internal fi xed-off-time cycle,
load current recirculates according to the decay mode
selected by the control logic. The synchronous rectifi ca-
tion feature turns on the appropriate FETs during current
decay, and effectively shorts out the body diodes with
the low DMOS RDSON. This reduces power dissipa-
tion signifi cantly, and eliminates the need for external
Schottky diodes. Synchronous rectifi cation has two
modes: Active mode and Disabled mode (described below).
Active Mode. When the input on the SR terminal
is set at logic low, Active mode is enabled. This mode
allows synchronous rectifi cation to occur, but when a
zero current level is detected, it also prevents reversal of
the load current by turning off synchronous rectifi cation.
This prevents the motor winding from conducting in the
reverse direction.
Disabled Mode. When the input on the SR terminal
is set at logic high, Disabled mode takes effect. This
mode disables synchronous rectifi cation. This mode
is typically used when external diodes are required to
transfer power dissipation from the A3980 package to
the external diodes.
Shutdown. In the event of an overtemperature fault
or an undervoltage fault on VREG, the DMOS outputs
of the A3980 are disabled until the fault condition is
removed. In the case of an overvoltage fault, the sink
DMOS FETs are switched on, and the source FETs off.
At power-up, and in the event of low VDD, the UVLO
circuit disables the DMOS outputs until VDD reaches the
minimum level. Once VDD is above the minimum level,
the translator resets to the Home state and the DMOS
outputs are re-enabled.
Thermal Protection. All drivers are turned off
when the junction temperature reaches the thermal
shutdown value, typically 170C. This is intended only
to protect the A3980 from failures due to excessive junc-
tion temperatures. Thermal protection will not protect
the A3980 from continuous short circuits, and additional
fault diagnostics are integrated for this purpose. Thermal
shutdown has a hysteresis of approximately 15C.
Diagnostic Features. The A3980 includes moni-
tor circuits that can detect shorts to VBB, shorts to
ground, and shorted or open circuit load. Short circuits
are detected by monitoring the voltage across the driving
DMOS FETs and the open load is detected by monitor-
ing the phase current when the motor is in the Home
microstep position. All fault detection takes place fol-
lowing a delay after the blank time.
Short to VBB. A short from any of the motor connec-
tions to the battery or VBB connection is detected by
monitoring the voltage across the bottom FETs in each
full-bridge. When the FET is on, the voltage should be
no greater than the VDSLT value defi ned in the Electrical
Characteristics table.
Short to Ground. A short from any of the motor con-
nections to ground is detected by monitoring the voltage
across the top FETs in each full-bridge. When the FET
is turned on, the voltage should be no greater than the
VDSHT value defi ned in the Electrical Characteristics
table.
Automotive DMOS Microstepping Driver
with Translator
A3980
13
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Shorted Load. A short across the load is detected by moni-
toring the voltage across both the top and bottom FETs in each
full-bridge.
Short Fault Operation. Because motor capacitance may
cause the measured voltages to show a fault as the full-bridge
switches, voltages are not sampled until after the blank time plus
an internally-generated delay, tSCT. Once a short circuit has been
detected, all outputs for the faulty phase are disabled until the
next step command. At the next step command, the outputs are
re-enabled and the voltage across the FET is resampled.
While the fault persists, the A3980 continues this cycle at each
step command: enabling the outputs for a short period, and then
disabling the outputs. This allows the A3980 to handle a continu-
ous short circuit without damage. If, while stepping rapidly, a
short circuit appears and no action is taken, the repeated short-cir-
cuit current pulses eventually cause the temperature of the A3980
to rise and an overtemperature fault occurs.
Low Load Current Fault Operation. A low load current is
detected by monitoring the measured phase current in each output
while driving the motor in the Home microstep position. At the
Home microstep position, each phase current should reach 70%
of ITripMax. If either phase current does not exceed half of this
expected value (more than 35% of ITripMax) while in the Home
microstep position, then a low load current condition is reported
on the next rising edge of the STEP input. If the measured cur-
rent in both phases exceeds 35% of ITripMax) then no fault will be
generated on the next rising edge of the STEP input.
If an open load condition appears while stepping, then it is
detected after the translator cycles through the Home state.
Although the A3980 continues to drive the DMOS outputs during
an open load condition, it does not clear the fault fl ags until the
next Home state occurs.
There are two conditions that can cause a low load current. The
fi rst is an open circuit on either or both motor phase connections.
In this condition, current can never fl ow through the phase so a
low load current will always be fl agged. The second condition is
where the back EMF of the motor limits the phase current to less
than the low load current trip level. This will happen when the
stepper motor is running close to its limiting speed. To confi rm an
open load condition when a low load current is fl agged, the step
rate should be reduced to a level below half the maximum step
rate. If the low load current fl ag remains active at the lower step
rate, after completing the number of steps required to pass the
home condition, then an open circuit condition is confi rmed.
To allow immediate detection of an open load condition at power
up or after coming out of sleep mode, the A3980 translator is
reset to the Home microstep position and the low load current
fault fl ags are set. If no open load condition exists then the fault
fl ags will be reset on the next rising edge of the STEP input.
Supply Monitors. External and internal supplies are moni-
tored to ensure that they are within the correct operating range.
If the main supply exceeds the overvoltage limit, VOVB, the fault
fl ags are set and the A3980 enters a safety mode in which all low-
side DMOS FETs are enabled and all high-side DMOS FETs are
disabled. This allows the A3980 to survive a load dump transient
condition that has up to 50 V on VBATT and a duration of up
to 500 ms. If the internal regulator VREG or the logic supply VDD go
below their respective undervoltage limits (VUVR or VUVD), then: the
fault fl ags are set, the DMOS outputs are disabled, and the internal
logic is reset to the power-on state (the translator is set to the Home
state).
Diagnostic Fault Flags (FF1, FF2). Diagnostic fault con-
ditions are reported using the two fault fl ag outputs (open drain).
These are active-low outputs which are coded as shown in table
2 to discriminate between the fault conditions. When both fault
fl ags are high, no fault exists.
Automotive DMOS Microstepping Driver
with Translator
A3980
14
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Application Information
The A3980 is a power circuit, therefore careful consider-
ation must be given to power dissipation and the effects
of high currents on interconnect and supply wiring.
Power Dissipation. A fi rst order approximation of
the power dissipation in the A3980 can be determined
by examining the power dissipation in each of the
two full-bridges during each of the operation modes.
When synchronous rectifi cation is used, current fl ow
most of the time through the DMOS FETs that are
switched on. When synchronous rectifi cation is not
used, the current fl ows through the body diode of
the DMOS FETs during the decay phase. The use of
fast or slow decay also affects the dissipation. All the
above combinations can be calculated from fi ve basic
DMOS output states, shown in the following illustrations.
M
+Drive Current Ramp
Diagonally opposite DMOS
output transistors are on. Cur-
rent fl ows from positive supply
through load to ground. Used in
all combinations.
Dissipation is I2R losses in the
DMOS transistors:
PD = I2 (RDSONH
+ RDSONL)
Synchronous Slow Decay
Both low-side DMOS output
transistors are on. Current circu-
lates through both transistors and
the load.
Dissipation is I2R losses in the
DMOS transistors:
PSS = I2 (2 × RDSONL)
Synchronous Fast Decay
Diagonally opposite DMOS output
transistors are on. Current fl ows
from ground through load to posi-
tive supply.
Dissipation is I2R losses in the
DMOS transistors:
PSF = I2
(RDSONH + RDSONL)
Non-Synchronous Slow Decay
One low-side DMOS output tran-
sistor and one body diode conduct-
ing. Current circulates through the
diode, the transistor, and the load.
Dissipation is I2R losses in the
DMOS transistors plus IV loss in
the diode:
PNS = (I2 × RDSONL) + (I × VF)
Non-Synchronous Fast Decay
Diagonally opposite body diodes
conducting. Current fl ows from
ground through load to positive
supply.
Dissipation is IV losses in the
diodes:
PNF = I (VFH + VFl)
M
+
M
+
M
+
M
+
Automotive DMOS Microstepping Driver
with Translator
A3980
15
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
150 125 100 75 50 25
5
4
3
2
1
0
The total dissipation for each of the four decay modes is the
average power for the current ramp and the current decay
portions of the PWM cycle.
For slow decay, the current is rising for approximately 20%
of the cycle and decaying for approximately 80%. For fast
decay, the ratio is approximately 50% for each. Note that
these are approximate fi gures, and they vary slightly depend-
ing on the motor characteristics and the use of synchronous
rectifi cation.
The power dissipation, PTOT, in each decay mode can be
calculated as shown in the following formulas.
Synchronous slow decay mode:
P
TO T = (0.2 × P
D ) + (0.8 × P
SS )
P
TOT = [0.2 × I2 (RDSONH + RDSONL)] + [0.8 × I2 (2 × RDSONL)]
Non-synchronous slow decay mode:
P
TO T = (0.2 × P
D ) + (0.8 × P
NS )
P
TOT = [0.2
× I2 (RDSONH
+ RDSONL)] + {0.8
× [I2 R DSONL + (I
× VF)]}
Synchronous fast decay mode:
PTOT = (0.5 × PD ) + (0.5 × PSF )
PTOT = I2 (RDSONH + RDSONL)
Non-synchronous fast decay mode:
PTOT = (0.5 × PD ) + (0.5 × PNF )
P
TOT = [0.5 × I2 (RDSONH + RDSONL)] + (0.5 × I2 × RDSONL)
An approximation of the total dissipation can be calculated
by summing the total power dissipated in both full-bridges
and adding the control circuit power due to VBB × IBB and
VDD × IDD. The total power at the required ambient tempera-
ture can then be compared to the allowable power dissipation,
shown in the Allowable Package Power Dissipation chart.
For critical applications, where the fi rst order power estimate
is close to the allowable dissipation, the power calculation
should take several other parameters into account including:
motor parameters, dead time, and switching losses in the
controller.
Layout. The printed circuit board should use a heavy
ground plane. For optimum electrical and thermal perfor-
mance, the A3980 should be soldered directly onto the board.
The load supply terminal, VBB, should be decoupled with
an electrolytic capacitor (> 47 F is recommended), placed
as close to the A3980 as possible. To avoid problems due to
capacitive coupling of the high dv/dt switching transients,
route the full-bridge output traces away from the sensitive
logic input traces. Always drive the logic inputs with a low
source impedance to increase noise immunity.
Grounding. A star ground system located close to the
A3980 is recommended. On the 28-lead TSSOP package, the
analog ground (lead 7) and the power ground (lead 21) must
be connected together externally. The copper ground plane
located under the exposed thermal pad is typically used as
the star ground point.
Allowable Package Power Dissipation
1RθJA at 28ºC/ W measured on a JEDEC-standard
“High-K” 4-layer PCB.
2RθJA at 38ºC/ W measured on a typical 2-sided PCB
with 3 in.
2
(1935 mm2) copper ground area.
Ambient Temperature (°C)
Power Dissipation (W)
2RθJA = 38ºC/W
1RθJA = 28ºC/W
Automotive DMOS Microstepping Driver
with Translator
A3980
16
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Current Sensing. To minimize inaccuracies caused by
ground-trace IR drops in sensing the output current level,
the current-sense resistors (RS1 and RS2) should have an
independent ground return to the star ground point. This path
should be as short as possible. For low-value sense resistors,
the IR drops in the printed circuit board sense resistor traces
can be signifi cant and should be taken into account. The use
of sockets should be avoided as they can introduce variation
in RS due to their contact resistance.
The recommended value of the sense resistor, RS (), is
given by
RS = 0.5 / ITripMAX
up to a maximum of 1 for ITripMAX of 0.5 A. Below 0.5 A,
RS should be 1 , and VREF reduced accordingly, as shown
in the following table.
IMAX (A)
Recommended
RS(Ω)V
REF
(V)
0.1 1.00 0.8
0.2 1.00 1.6
0.3 1.00 2.4
0.4 1.00 3.2
0.5 1.00 4.0
0.6 0.83 4.0
0.7 0.71 4.0
0.8 0.63 4.0
0.9 0.56 4.0
1.0 0.50 4.0
Automotive DMOS Microstepping Driver
with Translator
A3980
17
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Terminal List Table
Name Description Number
SENSE1 Sense resistor for full-bridge 1 1
SR Enable synchronous rectifi cation 2
DIR Logic input 3
OUT1A Output A for for full-bridge 1 4
PFD Mixed decay setting 5
RC1 Analog input for fi xed off-time for full-bridge 1 6
AGND Analog ground 7
REF Current trip reference voltage input 8
RC2 Analog input for fi xed off-time for full-bridge 2 9
VDD Logic supply voltage 10
OUT2A Output A for for full-bridge 2 11
MS2 Logic input 12
MS1 Logic input 13
SENSE2 Sense resistor for full-bridge 2 14
VBB2 Load supply 2 15
FF1 Fault fl ag 1 16
FF2 Fault fl ag 2 17
OUT2B Output B for for full-bridge 2 18
STEP Logic input 19
VREG Regulator decoupling 20
PGND Power ground 21
VCP Reservoir capacitor 22
CP1 Charge pump capacitor 1 23
CP2 Charge pump capacitor 2 24
OUT1B Output B for for full-bridge 1 25
ENABLE Logic input 26
SLEEP Logic input 27
VBB1 Load supply 1 28
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Translator
& Control Logic
PWM
Timer
Reg
Charge
Pump
÷8
VDD
VBB1
VBB2
SENSE1
S
R
DI
R
OUT1
A
PFD
RC1
AGND
REF
RC2
VDD
OUT2
A
MS2
MS1
SENSE2
VBB1
SLEEP
ENABLE
OUT1B
CP2
CP1
VCP
PGND
VREG
STEP
OUT2B
FF2
FF1
VBB2
Pin-out Diagram
Automotive DMOS Microstepping Driver
with Translator
A3980
18
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Pacakge LP, 28-Pin TSSOP with Exposed Thermal Pad
1.20 MAX
0.10 MAX
C
SEATING
PLANE
C0.10
28X
6.10
0.65
0.45
1.65
3.00
3.00
5.1
5.1
0.25
0.65
21
28
GAUGE PLANE
SEATING PLANE
B
A
28
21
ATerminal #1 mark area
B
For reference only
(reference JEDEC MO-153 AET)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
Reference land pattern layout (reference IPC7351 SOP65P640X120-29CM);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
PCB Layout Reference View
Exposed thermal pad (bottom surface)
4.40 ±0.10 6.40 ±0.20
(1.00)
9.70 ±0.10
C
C
0.60 ±0.15
4° ±4
0.15 +0.05
–0.06
0.25 +0.05
–0.06
Copyright ©2003-2010, Allegro MicroSystems, Inc.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-
mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;
nor for any in fringe ment of patents or other rights of third parties which may result from its use.
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