1
FEATURES
RGVPACKAGE
(TOP VIEW)
5678
9
10
11
12
13
14
1516
1
2
3
4
A1
A2
P0
A0
P4
P7
SCL
SDA
VCC
RESET
P6
P1
GND
P3
P2
P5
D,DB,DGV,ORPWPACKAGE
(TOP VIEW)
5
6
7
8 9
10
11
12
13
14
15
16
1
2
3
4
P1
A1
A2
P0
A0
GND
SCL
SDA
VCC
P4
P7
RESET
P3
P6
P2
P5
RGYPACKAGE
(TOP VIEW)
5
6
7 10
11
12
13
14
15
16
1
2
3
4
SDA
SCL
VCC
A1
A2
P0
A0
P1 8 9
GND
P2
P4
P7
RESET
P6
P3
P5
DESCRIPTION/ORDERING INFORMATION
PCA9557
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.................................................................................................................................................... SCPS133I DECEMBER 2005 REVISED JUNE 2008
REMOTE 8-BIT I
2
C AND SMBus LOW-POWER I/O EXPANDERWITH RESET AND CONFIGURATION REGISTERS
Low Standby Current Consumption of Internal Power-On Reset1µA Max
High-Impedance Open Drain on P0I
2
C to Parallel Port Expander
Power Up With All Channels Configured asOperating Power-Supply Voltage Range of Inputs2.3 V to 5.5 V
No Glitch on Power Up5-V Tolerant I/O Ports
Noise Filter on SCL/SDA Inputs400-kHz Fast I
2
C Bus
Latched Outputs With High Current DriveThree Hardware Address Pins Allow for Use of Maximum Capability for Directly Driving LEDsup to Eight Devices on I
2
C/SMBus
Latch-Up Performance Exceeds 100 mA PerLower-Voltage Higher-Performance Migration JESD 78, Class IIPath for PCA9556
ESD Protection Exceeds JESD 22Input/Output Configuration Register
2000-V Human-Body Model (A114-A)Polarity Inversion Register
200-V Machine Model (A115-A)Active-Low Reset Input
1000-V Charged-Device Model (C101)
This 8-bit I/O expander for the two-line bidirectional bus (I
2
C) is designed for 2.3-V to 5.5-V V
CC
operation. Thedevice provides general-purpose remote I/O expansion for most microcontroller families via the I
2
C interface[serial clock (SCL) and serial data (SDA)].
The PCA9557 consists of one 8-bit configuration (input or output selection), input port, output port, and polarityinversion (active-high) registers. At power on, the I/Os are configured as inputs. However, the system master canenable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input oroutput is kept in the corresponding input or output register. The polarity of the input port register can be invertedwith the polarity inversion register. All registers can be read by the system master.
The device outputs (latched) have high-current drive capability for directly driving LEDs. The device has lowcurrent consumption.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
PCA9557
SCPS133I DECEMBER 2005 REVISED JUNE 2008 ....................................................................................................................................................
www.ti.com
The system master can reset the PCA9557 in the event of a timeout or other improper operation by asserting alow in the active-low reset ( RESET) input. The power-on reset puts the registers in their default state andinitializes the I
2
C/SMBus state machine. Asserting RESET causes the same reset/initialization to occur withoutdepowering the part.
Three hardware pins (A0, A1, and A2) are used to program and vary the fixed I
2
C address, allowing up to eightdevices to share the same I
2
C bus or SMBus.
ORDERING INFORMATION
T
A
PACKAGE
(1) (2)
ORDERABLE PART NUMBER TOP-SIDE MARKING
QFN RGV Reel of 2000 PCA9557RGVR PD557QFN RGY Reel of 1000 PCA9557RGYR PD557Reel of 2500 PCA9557DRSOIC D Reel of 250 PCA9557DT PCA9557Tube of 40 PCA9557D 40 ° C to 85 ° C Reel of 2000 PCA9557DBRSSOP DB PD557Tube of 80 PCA9557DBReel of 2000 PCA9557PWRTSSOP PW Reel of 250 PCA9557PWT PD557Tube of 90 PCA9557PWTVSOP DGV Reel of 2000 PCA9557DGVR PD557
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging .(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com .
TERMINAL FUNCTIONS
NO.
QFN (RGY)
SOIC (D),
NAME DESCRIPTIONSSOP (DB),
QFN (RGV)TSSOP (PW),
ANDTVSOP (DGV)
1 15 SCL Serial clock bus. Connect to V
CC
through a pullup resistor.2 16 SDA Serial data bus. Connect to V
CC
through a pullup resistor.3 1 A0 Address input. Connect directly to V
CC
or ground.4 2 A1 Address input. Connect directly to V
CC
or ground.5 3 A2 Address input. Connect directly to V
CC
or ground.P-port input/output. High impedance open-drain design structure. Connect to V
CC6 4 P0
through a pullup resistor.7 5 P1 P-port input/output. Push-pull design structure.8 6 GND Ground9 7 P2 P-port input/output. Push-pull design structure.10 8 P3 P-port input/output. Push-pull design structure.11 9 P4 P-port input/output. Push-pull design structure.12 10 P5 P-port input/output. Push-pull design structure.13 11 P6 P-port input/output. Push-pull design structure.14 12 P7 P-port input/output. Push-pull design structure.Active-low reset input. Connect to V
CC
through a pullup resistor if no active15 13 RESET
connection is used.16 14 V
CC
Supply voltage
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1
I/O
Port
Shift
Register 8 Bits
Input
Filter
2
Power-On
Reset
Read Pulse
Write Pulse
5
4
3
16
8
GND
VCC
SDA
SCL
A2
A1
A0
I2C-Bus
Control
P7−P0
RESET 15
PCA9557
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.................................................................................................................................................... SCPS133I DECEMBER 2005 REVISED JUNE 2008
LOGIC DIAGRAM (POSITIVE LOGIC)
A. Pin numbers shown are for the D, DB, DGV, PW, and RGY packages.B. All I/Os are set to inputs at reset.
Copyright © 2005 2008, Texas Instruments Incorporated Submit Documentation Feedback 3
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D
FF
Q
D Q
FF
D Q
FF
D Q
FF
Data From
Shift Register
Data From
Shift Register
Write Configuration
Pulse
Write Pulse
Read Pulse
Data From
Shift Register
Write Polarity Pulse
CKQ
CKQ
CKQ
CKQ
Polarity
Inversion
Register
Input
Port
Register
Output
Port
Register
Configuration
Register
GND
Input Port
Register Data
Polarity
Register Data
ESD Protection Diode
P0
Output Port
Register Data
PCA9557
SCPS133I DECEMBER 2005 REVISED JUNE 2008 ....................................................................................................................................................
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SIMPLIFIED SCHEMATIC DIAGRAM OF P0
A. On power up or reset, all registers return to default values.
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D
FF
Q
D Q
FF
D Q
FF
D Q
FF
Data From
Shift Register
Data From
Shift Register
Write Configuration
Pulse
Write Pulse
Read Pulse
Data From
Shift Register
Write Polarity Pulse
CKQ
CKQ
CKQ
CKQ
Polarity
Inversion
Register
Input
Port
Register
Output
Port
Register
Configuration
Register VCC
GND
Input Port
Register Data
Polarity
Register Data
ESD Protection Diode
P7−P1
Output Port
Register Data
I
2
C Interface
PCA9557
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.................................................................................................................................................... SCPS133I DECEMBER 2005 REVISED JUNE 2008
SIMPLIFIED SCHEMATIC DIAGRAM OF P7 P1
A. On power up or reset, all registers return to default values.
The bidirectional I
2
C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must beconnected to a positive supply through a pullup resistor when connected to the output stages of a device. Datatransfer may be initiated only when the bus is not busy.
I
2
C communication with this device is initiated by a master sending a start condition, a high-to-low transition onthe SDA input/output while the SCL input is high (see Figure 1 ). After the start condition, the device address byteis sent, most-significant bit (MSB) first, including the data direction bit (R/ W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDAinput/output during the high of the ACK-related clock pulse. The address (A2 A0) inputs of the slave device mustnot be changed between the start and the stop conditions.
On the I
2
C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remainstable during the high pulse of the clock period, as changes in the data line at this time are interpreted as controlcommands (start or stop) (see Figure 2 ).
A stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by themaster (see Figure 1 ).
Any number of data bytes can be transferred from the transmitter to the receiver between the Start and the Stopconditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line beforethe receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACKclock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period (seeFigure 3 ). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly,the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and holdtimes must be met to ensure proper operation.
Copyright © 2005 2008, Texas Instruments Incorporated Submit Documentation Feedback 5
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SDA
SCL S P
Start Condition Stop Condition
SDA
SCL Data Line Change
Data Output
by Transmitter
SCL From
Master
Start
Condition
S
1 2 8 9
Data Output
by Receiver
Clock Pulse for
Acknowledgment
NACK
ACK
PCA9557
SCPS133I DECEMBER 2005 REVISED JUNE 2008 ....................................................................................................................................................
www.ti.com
A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) afterthe last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high.In this event, the transmitter must release the data line to enable the master to generate a stop condition.
Figure 1. Definition of Start and Stop Conditions
Figure 2. Bit Transfer
Figure 3. Acknowledgment on the I
2
C Bus
Interface Definition
BITBYTE
7 (MSB) 6 5 4 3 2 1 0 (LSB)
I
2
C slave address L L H H A2 A1 A0 R/ WPx I/O data bus P7 P6 P5 P4 P3 P2 P1 P0
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Device Address
0
Slave Address
0 1 1 A2 A1 A0 R/W
Fixed Programmable
Control Register and Command Byte
PCA9557
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.................................................................................................................................................... SCPS133I DECEMBER 2005 REVISED JUNE 2008
The address of the PCA9557 is shown in Figure 4 .
Figure 4. PCA9557 Address
Address Reference
INPUTS
I
2
C BUS SLAVE ADDRESSA2 A1 A0
L L L 24 (decimal), 18 (hexadecimal)L L H 25 (decimal), 19 (hexadecimal)L H L 26 (decimal), 1A (hexadecimal)L H H 27 (decimal), 1B (hexadecimal)H L L 28 (decimal), 1C (hexadecimal)H L H 29 (decimal), 1D (hexadecimal)H H L 30 (decimal), 1E (hexadecimal)H H H 31 (decimal), 1F (hexadecimal)
The last bit of the slave address defines the operation (read or write) to be performed. A high (1) selects a readoperation, while a low (0) selects a write operation.
Following the successful acknowledgment of the address byte, the bus master sends a command byte that isstored in the control register in the PCA9557. Two bits of this data byte state the operation (read or write) andthe internal registers (input, output, polarity inversion or configuration) that will be affected. This register can bewritten or read through the I
2
C bus. The command byte is sent only during a write transmission.
Once a new command byte has been sent, the register that was addressed continues to be accessed by readsuntil a new command byte has been sent.
Figure 5. Control Register Bits
Command Byte
CONTROL REGISTER BITS
COMMAND BYTE POWER-UPREGISTER PROTOCOL(HEX) DEFAULTB1 B0
0 0 0x00 Input Port Read byte xxxx xxxx0 1 0x01 Output Port Read/write byte 0000 00001 0 0x02 Polarity Inversion Read/write byte 1111 00001 1 0x03 Configuration Read/write byte 1111 1111
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Register Descriptions
Power-On Reset
RESET
PCA9557
SCPS133I DECEMBER 2005 REVISED JUNE 2008 ....................................................................................................................................................
www.ti.com
The input port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin isdefined as an input or an output by the configuration register. It only acts on read operation. Writes to theseregisters have no effect. The default value, X, is determined by the externally applied logic level.
Before a read operation, a write transmission is sent with the command byte to signal the I
2
C device that theinput port register will be accessed next.
Register 0 (Input Port Register)
BIT I7 I6 I5 I4 I3 I2 I1 I0
DEFAULT XXXXXXXX
The output port register (register 1) shows the outgoing logic levels of the pins defined as outputs by theconfiguration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from thisregister reflect the value that is in the flip-flop controlling the output selection, not the actual pin value.
Register 1 (Output Port Register)
BIT O7 O6 O5 O4 O3 O2 O1 O0
DEFAULT 00000000
The polarity inversion register (register 2) allows polarity inversion of pins defined as inputs by the configurationregister. If a bit in this register is set (written with 1), the corresponding port pin ' s polarity is inverted. If a bit in thisregister is cleared (written with a 0), the corresponding port pin ' s original polarity is retained.
Register 2 (Polarity Inversion Register)
BIT N7 N6 N5 N4 N3 N2 N1 N0
DEFAULT 11110000
The configuration register (register 3) configures the directions of the I/O pins. If a bit in this register is set to 1,the corresponding port pin is enabled as an input with high impedance output driver. If a bit in this register iscleared to 0, the corresponding port pin is enabled as an output.
Register 3 (Configuration Register)
BIT C7 C6 C5 C4 C3 C2 C1 C0
DEFAULT 11111111
When power (from 0 V) is applied to V
CC
, an internal power-on reset holds the PCA9557 in a reset condition untilV
CC
has reached V
POR
. At that time, the reset condition is released, and the PCA9557 registers and I
2
C/SMBusstate machine initialize to their default states. After that, V
CC
must be lowered to below 0.2 V and back up to theoperating voltage for a power-reset cycle. The RESET input can be asserted to reset the system, while keepingthe V
CC
at its operating level.
A reset can be accomplished by holding the RESET pin low for a minimum of t
W
. The PCA9557 registers andI
2
C/SMBus state machine are held in their default states until RESET again is high. This input requires a pullupresistor to V
CC
if no active connection is used.
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Bus Transactions
Writes
SCL
Start Condition
Data 1 Valid
SDA
Write to Port
Data Out
From Port
R/W ACK From Slave ACK From Slave ACK From Slave
1 98765432
Data 11A2
00S 11 A1 A0 0 A 0000000 A A P
tpv
Data to PortCommand ByteSlave Address
1/0A20 0S 11 A1 A0 0 A 0000000 A A P
SCL
SDA
Start Condition R/W ACK From Slave ACK From Slave ACK From Slave
19
8765432
Data to RegisterCommand ByteSlave Address
Data
PCA9557
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.................................................................................................................................................... SCPS133I DECEMBER 2005 REVISED JUNE 2008
Data is exchanged between the master and PCA9557 through write and read commands.
Data is transmitted to the PCA9557 by sending the device address and setting the least-significant bit (LSB) to alogic 0 (see Figure 4 for device address). The command byte is sent after the address and determines whichregister receives the data that follows the command byte. There is no limitation on the number of data bytes sentin one write transmission (see Figure 6 and Figure 7 ).
Figure 6. Write to Output Port Register
< br/ >
Figure 7. Write to Configuration or Polarity Inversion Registers
Copyright © 2005 2008, Texas Instruments Incorporated Submit Documentation Feedback 9
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Reads
A20 0S 11 A1 A0 0 A A
Data from Register
Slave Address
Slave Address
R/W
ACK From
Slave
Command Byte S A20 0 11 A1 A0
R/W
1 A Data A
Data
Data from Register
NA P
Last Byte
At this moment, master-transmitter
becomes master-receiver, and
slave-receiver becomes
slave-transmitter
ACK From
Slave ACK From
Slave ACK From
Master
NACK From
Master
First Byte
SCL
SDA
Start
Condition R/W
Read From
Port
Data Into
Port
Stop
Condition
ACK From
Master NACK From
Master
ACK From
Slave
Data From Port
Slave Address Data From Port
1 98765432
A20 0S 11 A1 A0 1 A Data 1 Data 4A NA P
Data 2 Data 3 Data 4
tph tps
Data 5
PCA9557
SCPS133I DECEMBER 2005 REVISED JUNE 2008 ....................................................................................................................................................
www.ti.com
The bus master first must send the PCA9557 address with the LSB set to a logic 0 (see Figure 4 for deviceaddress). The command byte is sent after the address and determines which register is accessed. After a restart,the device address is sent again but, this time, the LSB is set to a logic 1. Data from the register defined by thecommand byte then is sent by the PCA9557 (see Figure 8 and Figure 9 ). After a restart, the value of the registerdefined by the command byte matches the register being accessed when the restart occurred. Data is clockedinto the register on the rising edge of the ACK clock pulse. There is no limitation on the number of data bytesreceived in one read transmission, but when the final byte is received, the bus master must not acknowledge thedata.
Figure 8. Read From Register
< br/ >
A. This figure assumes the command byte has been previously programmed with 00h.B. Transfer of data can be stopped at any moment by a stop condition. When this occurs, data present at the lastacknowledge phase is valid (output mode). Input data is lost.C. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave addresscall and actual data transfer from the P port (see Figure 8 ).
Figure 9. Read Input Port Register
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ABSOLUTE MAXIMUM RATINGS
(1)
RECOMMENDED OPERATING CONDITIONS
PCA9557
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.................................................................................................................................................... SCPS133I DECEMBER 2005 REVISED JUNE 2008
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage range 0.5 6 VV
I
Input voltage range
(2)
0.5 6 VV
O
Output voltage range
(2)
0.5 6 VI
IK
Input clamp current V
I
< 0 20 mAI
OK
Output clamp current V
O
< 0 20 mAI
IOK
Input/output clamp current V
O
< 0 or V
O
> V
CC
20 µAI
OL
Continuous output low current V
O
= 0 to V
CC
50 mAI
OH
Continuous output high current V
O
= 0 to V
CC
50 mAContinuous current through GND 250I
CC
mAContinuous current through V
CC
160D package 73DB package 82DGV package 120θ
JA
Package thermal impedance
(3)
° C/WPW package 108RGV package 51RGY package 47T
stg
Storage temperature range 65 150 ° C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.(3) The package thermal impedance is calculated in accordance with JESD 51-7.
MIN MAX UNIT
V
CC
Supply voltage 2.3 5.5 VSCL, SDA 0.7 × V
CC
5.5V
IH
High-level input voltage VA2 A0, P7 P0, RESET 2 5.5SCL, SDA 0.5 0.3 × V
CCV
IL
Low-level input voltage VA2 A0, P7 P0, RESET 0.5 0.8I
OH
High-level output current P7 P1 10 mAI
OL
Low-level output current P7 P0 25 mAT
A
Operating free-air temperature 40 85 ° C
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ELECTRICAL CHARACTERISTICS
PCA9557
SCPS133I DECEMBER 2005 REVISED JUNE 2008 ....................................................................................................................................................
www.ti.com
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP
(1)
MAX UNIT
V
IK
Input diode clamp voltage I
I
= 18 mA 2.3 V to 5.5 V 1.2 VV
POR
Power-on reset voltage V
I
= V
CC
or GND, I
O
= 0 V
POR
1.65 2.1 V2.3 V 1.83 V 2.6I
OH
= 8 mA
4.5 V 34.75 V 4.1V
OH
P-port high-level output voltage
(2)
V2.3 V 1.53 V 2.5I
OH
= 10 mA
4.5 V 34.75 V 4SDA V
OL
= 0.4 V 2.3 V to 5.5 V 3V
OL
= 0.5 V 8 20I
OL
mAP port
(3)
V
OL
= 0.55 V 2.3 V to 5.5 V 8 20V
OL
= 0.7 V 10 24P port, except for P0
(3)
V
OH
= 2.3 V 2.3 V to 5.5 V 4 mAI
OH
V
OH
= 4.6 V 4.6 V to 5.5 V 1P0
(3)
µAV
OH
= 3.3 V 3.3 V to 5.5 V 1SCL, SDA ± 1I
I
V
I
= V
CC
or GND 2.3 V to 5.5 V µAA2 A0, RESET ± 1I
IH
P port V
I
= V
CC
2.3 V to 5.5 V 1 µAI
IL
P port V
I
= GND 2.3 V to 5.5 V 1 µA5.5 V 19 25V
I
= V
CC
or GND, I
O
= 0,
3.6 V 12 22I/O = inputs, f
SCL
= 400 kHz
2.7 V 8 20Operating mode
5.5 V 1.5 5V
I
= V
CC
or GND, I
O
= 0,I
CC
3.6 V 1 4 µAI/O = inputs, f
SCL
= 100 kHz
2.7 V 0.6 35.5 V 0.25 1V
I
= V
CC
or GND, I
O
= 0,Standby mode 3.6 V 0.25 0.9I/O = inputs, f
SCL
= 0 kHz
2.7 V 0.2 0.8One input at V
CC
0.6 V,
2.3 V to 5.5 V 0.2Other inputs at V
CC
or GNDΔI
CC
Additional current in Standby mode mAEvery LED I/O at V
I
= 4.3 V,
5.5 V 0.4f
SCL
= 0 kHzC
I
SCL V
I
= V
CC
or GND 2.3 V to 5.5 V 4 6 pFSDA 5.5 8C
io
V
IO
= V
CC
or GND 2.3 V to 5.5 V pFP port 7.5 9.5
(1) All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V V
CC
) and T
A
= 25 ° C.(2) The total current sourced by all I/Os must be limited to 85 mA per bit.(3) Each I/O must be externally limited to a maximum of 25 mA, and the P port (P7 P0) must be limited to a maximum current of 200 mA.
12 Submit Documentation Feedback Copyright © 2005 2008, Texas Instruments Incorporated
Product Folder Link(s): PCA9557
I
2
C INTERFACE TIMING REQUIREMENTS
RESET TIMING REQUIREMENTS
SWITCHING CHARACTERISTICS
PCA9557
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.................................................................................................................................................... SCPS133I DECEMBER 2005 REVISED JUNE 2008
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 10 )
STANDARD MODE FAST MODEI
2
C BUS I
2
C BUS
UNITMIN MAX MIN MAX
f
scl
I
2
C clock frequency 0 100 0 400 kHzt
sch
I
2
C clock high time 4 0.6 µst
scl
I
2
C clock low time 4.7 1.3 µst
sp
I
2
C spike time 50 50 nst
sds
I
2
C serial data setup time 250 100 nst
sdh
I
2
C serial data hold time 0 0 nst
icr
I
2
C input rise time 1000 20 + 0.1C
b
(1)
300 nst
icf
I
2
C input fall time 300 20 + 0.1C
b
(1)
300 nst
ocf
I
2
C output fall time, 10-pF to 400-pF bus 300 20 + 0.1C
b
(1)
300 nst
buf
I
2
C bus free time between Stop and Start 4.7 1.3 µst
sts
I
2
C Start or repeated Start condition setup time 4.7 0.6 µst
sth
I
2
C Start or repeated Start condition hold time 4 0.6 µst
sps
I
2
C Stop condition setup time 4 0.6 µst
vd(data)
Valid data time, SCL low to SDA output valid 1 0.9 µsValid data time of ACK condition, ACK signal from SCL low tot
vd(ack)
1 0.9 µsSDA (out) lowC
b
I
2
C bus capacitive load 400 400 pF
(1) C
b
= total capacitance of one bus line in pF
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 13 )
STANDARD MODE FAST MODEI
2
C BUS I
2
C BUS
UNITMIN MAX MIN MAX
t
W
Reset pulse duration
(1)
16 16 nst
REC
Reset recovery time 0 0 nst
RESET
Time to reset
(2)
400 400 ns
(1) A pulse duration of 16 ns minimum must be applied to RESET to return the PCA9557 to its default state.(2) The PCA9557 requires a minimum of 400 ns to be reset.
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 10 )
STANDARD MODE FAST MODEI
2
C BUS I
2
C BUSPARAMETER FROM TO UNITMIN MAX MIN MAX
SCL P0 250 250t
pv
Output data valid nsSCL P1 P7 200 200t
ps
Input data setup time P port SCL 0 0 nst
ph
Input data hold time P port SCL 200 200 ns
Copyright © 2005 2008, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): PCA9557
TYPICAL CHARACTERISTICS
0
5
10
15
20
25
30
35
40
45
50
55
60
-50 -25 0 25 50 75 100
TA- Free-Air Temperature - °C
ICC - Supply Current - µA
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
fSCL = 400 kHz
I/Os unloaded
0
5
10
15
20
-50 -25 0 25 50 75 100
TA- Free-Air Temperature - °C
ICC - Standby Supply Current - nA
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
SCL = VCC
0
10
20
30
40
50
60
70
2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
VCC Supply Voltage V
ICC Supply Current µA
fSCL = 400 kHz
I/Os unloaded
0
5
10
15
20
25
30
0.0 0.1 0.2 0.3 0.4 0.5 0.6
VOL Output Low Voltage V
ISINK I/O Sink Current mA
TA= –40°C
VCC = 2.5 V
TA= 25°C
TA= 85°C
0
5
10
15
20
25
30
35
40
45
50
0.0 0.1 0.2 0.3 0.4 0.5 0.6
VOL Output Low Voltage V
ISINK I/O Sink Current mA
TA= –40°C
VCC = 5 V
TA= 25°C
TA= 85°C
0
5
10
15
20
25
30
35
40
0.0 0.1 0.2 0.3 0.4 0.5 0.6
VOL Output Low Voltage V
ISINK I/O Sink Current mA
TA= –40°C
VCC = 3.3 V
TA= 25°C
TA= 85°C
0
5
10
15
20
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
(VCC VOH) Output High Voltage V
ISOURCE I/O Source Current mA
TA= –40°C
VCC = 2.5 V
TA= 25°C
TA= 85°C
0
5
10
15
20
25
30
35
40
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
(VCC VOH) Output High Voltage V
ISOURCE I/O Source Current mA
TA= –40°C
VCC = 5 V
TA= 25°C
TA= 85°C
0
5
10
15
20
25
30
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
(VCC VOH) Output High Voltage V
ISOURCE I/O Source Current mA
TA= –40°C
VCC = 3.3 V
TA= 25°C
TA= 85°C
PCA9557
SCPS133I DECEMBER 2005 REVISED JUNE 2008 ....................................................................................................................................................
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SUPPLY CURRENT STANDBY SUPPLY CURRENT SUPPLY CURRENTvs vs vsTEMPERATURE TEMPERATURE SUPPLY VOLTAGE
I/O SINK CURRENT I/O SINK CURRENT I/O SINK CURRENTvs vs vsOUTPUT LOW VOLTAGE OUTPUT LOW VOLTAGE OUTPUT LOW VOLTAGE
I/O SOURCE CURRENT I/O SOURCE CURRENT I/O SOURCE CURRENTvs vs vsOUTPUT HIGH VOLTAGE OUTPUT HIGH VOLTAGE OUTPUT HIGH VOLTAGE(P7 P1) (P7 P1) (P7 P1)
14 Submit Documentation Feedback Copyright © 2005 2008, Texas Instruments Incorporated
Product Folder Link(s): PCA9557
0
50
100
150
200
250
300
350
400
450
500
550
600
-50 -25 0 25 50 75 100
TA Free-Air Temperature °C
(VCC VOH ) Output High Voltage mV
VCC = 5 V, ISOURCE = 10
VCC = 2.5 V, ISOURCE = 10
VCC = 2.5 V, ISOURCE = 1 mA
VCC = 5 V, ISOURCE = 1 mA
0
1
2
3
4
5
6
2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
VCC Supply Voltage V
VOH Output High Voltage V
IOH = 10 mA
IOH = 8 mA
TA= 25°C
IOH = 4 mA
0
25
50
75
100
125
150
175
200
225
250
275
300
-50 -25 0 25 50 75 100
TA Free-Air Temperature °C
VOL Output Low Voltage mV
VCC = 5 V, ISINK = 10 mA
VCC = 2.5 V, ISINK = 10 mA
VCC = 2.5 V, ISINK = 1 mA
VCC = 5 V, ISINK = 1 mA
PCA9557
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.................................................................................................................................................... SCPS133I DECEMBER 2005 REVISED JUNE 2008
TYPICAL CHARACTERISTICS (continued)
OUTPUT HIGH VOLTAGE OUTPUT HIGH VOLTAGEvs vs OUTPUT LOW VOLTAGESUPPLY VOLTAGE TEMPERATURE vs(P7 P1) (P7 P1) TEMPERATURE
Copyright © 2005 2008, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): PCA9557
PARAMETER MEASUREMENT INFORMATION
RL = 1 k
VCC
CL = 50 pF
(see Note A)
tbuf
ticr
tsth tsds
tsdh
ticf
ticr
tscl tsch
tsts
tPHL
tPLH
0.3 × VCC
Stop
Condition
tsps
Repeat
Start
Condition
Start or
Repeat
Start
Condition
SCL
SDA
Start
Condition
(S)
Address
Bit 7
(MSB)
Data
Bit 10
(LSB)
Stop
Condition
(P)
Three Bytes for Complete
Device Programming
SDA LOAD CONFIGURATION
VOLTAGE WAVEFORMS
ticf
Stop
Condition
(P)
tsp
DUT SDA
0.7 × VCC
0.3 × VCC
0.7 × VCC
R/W
Bit 0
(LSB)
ACK
(A)
Data
Bit 07
(MSB)
Address
Bit 1
Address
Bit 6
BYTE DESCRIPTION
1 I2C address
2, 3 P-port data
PCA9557
SCPS133I DECEMBER 2005 REVISED JUNE 2008 ....................................................................................................................................................
www.ti.com
A. C
L
includes probe and jig capacitance.B. All inputs are supplied by generators having the following characteristics: PRR 10 MHz, Z
O
= 50 , t
r
/t
f
30 ns.C. All parameters and waveforms are not applicable to all devices.
Figure 10. I
2
C Interface Load Circuit and Voltage Waveforms
16 Submit Documentation Feedback Copyright © 2005 2008, Texas Instruments Incorporated
Product Folder Link(s): PCA9557
A
A
A
A
S 0 0 1 1 A1A2 A0 1 Data 1 1 PData 2
Start
Condition 8 Bits
(One Data Bytes)
From Port Data From PortSlave Address R/W
87654321
tir
tir
tsps
tiv
Address Data 1 Data 2
INT
Data
Into
Port
B
B
A
A
Pn INT
R/W A
tir
0.7 × VCC
0.3 × VCC
0.7 × VCC
0.3 × VCC
0.7 × VCC
0.3 × VCC
0.7 × VCC
0.3 × VCC
INT SCL
View B−BView A−A
tiv
RL = 4.7 k
VCC
CL = 100 pF
(see Note A)
INTERRUPT LOAD CONFIGURATION
DUT INT
ACK
From Slave ACK
From Slave
1.5 V
PCA9557
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.................................................................................................................................................... SCPS133I DECEMBER 2005 REVISED JUNE 2008
PARAMETER MEASUREMENT INFORMATION (continued)
A. C
L
includes probe and jig capacitance.B. All inputs are supplied by generators having the following characteristics: PRR 10 MHz, Z
O
= 50 , t
r
/t
f
30 ns.C. All parameters and waveforms are not applicable to all devices.
Figure 11. Interrupt Load Circuit and Voltage Waveforms
Copyright © 2005 2008, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): PCA9557