PIC16F1829LIN 20-Pin, 8-bit Flash LIN/J2602 Microcontroller Cross-Referenced Material: Special Microcontroller Features: This data sheet refers heavily on the following Microchip data sheets: * Self-Programmable under Software Control * Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) * Programmable Brown-out Reset (BOR) * Extended Watchdog Timer (WDT) * In-Circuit Serial ProgrammingTM (ICSPTM) via Two Pins * In-Circuit Debug (ICD) via Two Pins * Enhanced Low-Voltage Programming (LVP) * Operating Voltage Range of the Microcontroller: - 2.3V-5.5V * Programmable Code Protection * Power-Saving Sleep mode * "PIC16(L)F1825/1829 Data Sheet" (DS41440) * "MCP2021A/2A, LIN Transceiver with Voltage Regulator Data Sheet" (DS22298) Please have these documents available when reading this device specification. Only deviations from the data sheets listed above will be noted. High-Performance RISC CPU: * Only 49 Instructions to Learn: - All single-cycle instructions except branches * Operating Speed: - DC - 32 MHz oscillator/clock input - DC - 125 ns instruction cycle * 16 Kbytes Linear Program Memory Addressing * 1024 bytes Linear Data Memory Addressing * Interrupt Capability with Automatic Context Saving * 16-Level Deep Hardware Stack with Optional Overflow/Underflow Reset * Direct, Indirect and Relative Addressing modes: - Two full 16-bit File Select Registers (FSRs) - FSRs can read Program and Data memory Flexible Oscillator Structure: * Precision 32 MHz Internal Oscillator Block: - Factory calibrated to 1%, typical - Software selectable frequencies range of 31 kHz to 32 MHz * Four Crystal modes up to 32 MHz * Three External Clock modes up to 32 MHz * 4x Phase Lock Loop (PLL) * Fail-Safe Clock Monitor: - Allows for safe shutdown if peripheral clock stops * Two-Speed Oscillator Start-up * Reference Clock Module: - Programmable clock output frequency and duty-cycle 2012 Microchip Technology Inc. Analog Features: * Analog-to-Digital Converter (ADC) Module: - 10-bit resolution - Nine analog input channels - Conversion available during Sleep * Analog Comparator Module: - Two rail-to-rail analog comparators - Power mode control - Software controllable hysteresis * Voltage Reference Module: - Fixed Voltage Reference (FVR) with multiple output levels - 5-bit rail-to-rail resistive DAC with positive and negative reference selection Peripheral Features: * 12 Digital I/O Pins and one Input-only Pin: - High current sink/source 25 mA/25 mA - Individually programmable weak pull-ups - Individually programmable Interrupt-on-change pins * Timer0: 8-Bit Timer/Counter with 8-Bit Prescaler * Enhanced Timer1: - 16-bit timer/counter with prescaler - External Gate Input mode - Dedicated, low-power 32 kHz oscillator driver * Three Timer2 types: 8-Bit Timer/Counter with 8-Bit Period Register, Prescaler and Postscaler * Two Capture, Compare, PWM (CCP) Modules (one is internal only) * Two Enhanced CCP (ECCP) Modules: - Software-selectable time bases - Auto-shutdown and auto-restart - PWM steering Preliminary DS41673A-page 1 PIC16F1829LIN Peripheral Features: (Continued) * Internal Bus Transceiver compliant with LIN Bus Specifications 1.3, 2.0 and 2.1, and compliant to SAE J2602: - Support Baud Rates up to 20 Kbaud - 43V load dump protected - Very low EMI meets stringent OEM requirements - Wide supply voltage, 7.0V-30.0V continuous - Internal bus pull-up resistor and diode - Protected against ground shorts - Protected against loss of ground - High current drive - Automatic thermal shutdown * Extended Temperature Range: -40 to +125C * Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) Module: - Supports LIN 2.1 and J2602 - Auto-Baud Detect - Auto Wake-up on BREAK character * mTouchTM Sensing Oscillator Module: - Up to 12 input channels * Data Signal Modulator Module: - Selectable modulator and carrier sources * SR Latch: - Multiple Set/Reset input options - Emulates 555 Timer applications * On-board Voltage Regulator: - Output voltage of 5.0V with tolerances of 2% over temperature range - Maximum continuous input voltage of 30V - Internal thermal overload protection - Internal short circuit current limit - External components limited to filter capacitor only and load capacitor - Automatic thermal shutdown Note 1: 2: 3: Timers (8/16-bit) EUSART(2) ECCP (Full-Bridge) ECCP (Half-Bridge) 256 13 9 12 2 4/1 1 1 1 Other Features Comparators 1024 SR Latch Cap Sense (ch) Data EEPROM (bytes) 8K CCP 10-bit ADC (ch) SRAM (bytes) PIC16F1829LIN Data Memory Words Device Program Memory I/Os(1) PIC16F1829LIN Device Overview 1(3) Yes LIN/J2602 Transceiver, Voltage Regulator One pin is input-only. EUSART dedicated to LIN communications. One CCP only available internally. DS41673A-page 2 Preliminary 2012 Microchip Technology Inc. 20-PIN DIAGRAM FOR PIC16F1829LIN SSOP VDD CCP2(1)/P2A(1)/T1CKI/T1OSI/OSC1/CLKIN/RA5 T1G(1)/P2B(1)/CLKR/T1OSO/CLKOUT/OSC2/CPS3/AN3/RA4 20 VSS 2 19 RA0/AN0/CPS0/C1IN+/VREF-/DACOUT/ICSPDAT/ICDDAT 3 18 RA1/AN1/CPS1/C12IN0-/VREF+/SRI/ICSPCLK/ICDCLK MCLR/VPP/T1G(1)/RA3 4 MDCIN2/DT(1)/P1A/CCP1/RC5 5 MDOUT/P1B/SRNQ/C2OUT/RC4 6 MDMIN/P2A(1)/CCP2(1)/P1C(1)/C12IN3-/CPS7/AN7/RC3 7 LINVSS LBUS VREG Preliminary Note 1: 1 PIC16F1829LIN 2012 Microchip Technology Inc. FIGURE 1: 17 RA2/AN2/CPS2/T0CKI/INT/C1OUT/SRQ/CCP3/FLT0 16 RC0/AN4/CPS4/C2IN+/P1D(1) 15 RC1/AN5/CPS5/C12IN1-/P1C(1) 14 RC2/AN6/CPS6/C12IN2-/P1D(1)/P2B(1)/MDCIN1 8 13 RB4/AN10/CPS10 9 12 FAULT/TXE 10 11 VBAT Pin function is selectable via the APFCON0 or APFCON1 register. PIC16F1829LIN DS41673A-page 3 PIC16F1829LIN 20-Pin SSOP A/D Reference Cap Sense Comparator SR Latch Timers CCP EUSART Interrupt Modulator Pull-up Basic PIC16F1829LIN PIN SUMMARY I/O TABLE 1-1: RA0 19 AN0 VREFDACOUT CPS0 C1IN+ -- -- -- -- IOC -- Y ICSPDAT/ ICDDAT RA1 18 AN1 VREF+ CPS1 C12IN0- SRI -- -- -- IOC -- Y ICSPCLK/ ICDCLK RA2 17 AN2 -- CPS2 C1OUT SRQ T0CKI CCP3 FLT0 -- INT/ IOC -- Y -- RA3 4 -- -- -- -- -- T1G(1) -- -- IOC -- Y(4) MCLR VPP RA4 3 AN3 -- CPS3 -- -- T1G(1) T1OSO P2B(1) -- IOC -- Y OSC2 CLKOUT CLKR RA5 2 -- -- -- -- -- T1CKI T1OSI CCP2(1) P2A(1) -- IOC -- Y OSC1 CLKIN RB4 13 AN10 -- CPS10 -- -- -- -- -- IOC -- Y -- RB5 (2) -- -- -- -- -- -- -- RX(1) -- -- Y -- RB6 (2) -- -- -- -- -- -- -- -- -- -- Y CS/LWAKE RB7 (2) -- -- -- -- -- -- -- TX(1) -- -- Y -- -- -- -- Y -- RC0 16 AN4 -- CPS4 C2IN+ -- -- P1D(1) RC1 15 AN5 -- CPS5 C12IN1- -- -- P1C(1) -- -- -- Y -- RC2 14 AN6 -- CPS6 C12IN2- -- -- P1D(1) P2B(1) -- -- MDCIN1 Y -- RC3 7 AN7 -- CPS7 C12IN3- -- -- P1C(1) CCP2(1) P2A(1) -- -- MDMIN Y -- RC4 6 -- -- -- C2OUT SRNQ -- P1B -- -- MDOUT Y -- RC5 5 -- -- -- -- -- -- CCP1 P1A -- -- MDCIN2 Y -- RC6 -- -- -- -- -- -- -- -- -- -- -- -- No connection RC7 (2) -- -- -- -- -- -- -- -- -- -- Y POWERGOOD input from Voltage Regulator FAULT /TXE 12 -- -- -- -- -- -- -- -- -- -- -- -- -- VBAT 11 -- -- -- -- -- -- -- -- -- -- -- VREG 10 -- -- -- -- -- -- -- -- -- -- -- -- LBUS 9 -- -- -- -- -- -- -- -- -- -- -- -- VDD VDD 1 -- -- -- -- -- -- -- -- -- -- -- Vss 20 -- -- -- -- -- -- -- -- -- -- -- VSS Vss 8 -- -- -- -- -- -- -- -- -- -- -- LIN VSS Note 1: 2: Pin function is selectable via the APFCON0 or APFCON1 register. Internal connection. No associated external pin. DS41673A-page 4 Preliminary 2012 Microchip Technology Inc. PIC16F1829LIN Table of Contents 1.0 Device Overview ............................................................................................................................................................................. 7 2.0 Using the PIC16F1829LIN in LIN Bus Applications ...................................................................................................................... 13 3.0 Enhanced Mid-range CPU ............................................................................................................................................................. 19 4.0 Memory Organization.................................................................................................................................................................... 21 5.0 I/O Ports ........................................................................................................................................................................................ 38 6.0 Analog-to-Digital Converter (ADC) Module .................................................................................................................................... 48 7.0 Master Synchronous Serial Port (MSSP1 and MSSP2) Module ................................................................................................... 51 8.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) .................................................................... 52 9.0 Consideration of Split Power Supplies and During Debug ............................................................................................................ 57 10.0 Electrical Specifications .............................................................................................................................................................. 58 11.0 Packaging Information ................................................................................................................................................................ 64 Appendix A: Data Sheet Revision History ........................................................................................................................................... 67 The Microchip Web Site ...................................................................................................................................................................... 70 Customer Change Notification Service ............................................................................................................................................... 70 Customer Support ............................................................................................................................................................................... 70 Reader Response ............................................................................................................................................................................... 71 Product Identification System ............................................................................................................................................................. 72 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. 2012 Microchip Technology Inc. Preliminary DS41673A-page 5 PIC16F1829LIN NOTES: DS41673A-page 6 Preliminary 2012 Microchip Technology Inc. PIC16F1829LIN 1.0 DEVICE OVERVIEW The PIC16F1829LIN is described within sheet. It is available in 20-pin SSOP Figure 1-1 shows a block diagram PIC16F1829LIN device. Tables 1-1 and 1-2 pinout description. this data package. of the show the Refer to Table 1-1 for peripherals available per device. DEVICE PERIPHERAL SUMMARY PIC16F1829LIN TABLE 1-1: Peripheral ADC Capacitive Sensing (CPS) Module Data EEPROM Digital-to-Analog Converter (DAC) Digital Signal Modulator (DSM) EUSART Fixed Voltage Reference (FVR) SR Latch Capture/Compare/PWM Modules ECCP1 ECCP2 CCP3 C1 C2 Timer0 Timer1 Timer2 Timer4 Timer6 Comparators Timers 2012 Microchip Technology Inc. Preliminary DS41673A-page 7 PIC16F1829LIN PIC16F1829LIN BLOCK DIAGRAM(1) FIGURE 1-1: Program Flash Memory CLKR OSC2/CLKOUT EEPROM RAM Clock Reference Timing Generation OSC1/CLKIN PORTA INTRC Oscillator CPU PORTB(2) MCLR PORTC(3) ADC 10-Bit Timer0 Timer1 Timer2 Timer4 SR Latch ECCP1 ECCP2 CCP3 CCP4 Timer6 EUSART Comparators LIN XCVR Voltage Regulator Note 1: 2: 3: DS41673A-page 8 LBUS FAULT/TXE VBAT VREG See applicable chapters for more information on peripherals. All PORTB pins (except RB4) are internal connections only. RC6 - no connection, RC7 internally connected to PWRGOOD. Preliminary 2012 Microchip Technology Inc. PIC16F1829LIN TABLE 1-2: PIC16F1829LIN PINOUT DESCRIPTION Name RA0/AN0/CPS0/C1IN+/VREF-/ DACOUT/ICSPDAT/ICDDAT RA1/AN1/CPS1/C12IN0-/VREF+/ SRI/ICSPCLK/ICDCLK RA2/AN2/CPS2/T0CKI/INT/ C1OUT/SRQ/CCP3/FLT0 RA3/T1G(1)/VPP/MCLR RA4/AN3/CPS3/OSC2/ CLKOUT/T1OSO/CLKR P2B(1)/T1G(1,2) Function Input Type RA0 TTL AN0 AN Output Type Description CMOS General purpose I/O. -- A/D Channel 0 input. CPS0 AN -- Capacitive sensing input 0. C1IN+ AN -- Comparator C1 positive input. VREF- AN -- A/D and DAC Negative Voltage Reference input. DACOUT -- AN Digital-to-Analog Converter output. ICSPDAT ST CMOS ICSPTM Data I/O. ICDDAT ST CMOS In-Circuit Data I/O. RA1 TTL CMOS General purpose I/O. AN1 AN -- A/D Channel 1 input. CPS1 AN -- Capacitive sensing input 1. C12IN0- AN -- Comparator C1 or C2 negative input. VREF+ AN -- A/D and DAC Positive Voltage Reference input. SRI ST -- SR latch input. ICSPCLK ST -- Serial Programming Clock. ICDCLK ST -- In-Circuit Debug Clock. RA2 ST AN2 AN CMOS General purpose I/O. -- A/D Channel 2 input. CPS2 AN -- Capacitive sensing input 2. T0CKI ST -- Timer0 clock input. INT ST -- External interrupt. C1OUT -- CMOS Comparator C1 output. SRQ -- CMOS SR latch non-inverting output. CCP3 ST CMOS Capture/Compare/PWM 3. FLT0 ST -- ECCP Auto-Shutdown Fault input. RA3 TTL -- General purpose input. T1G ST -- Timer1 gate input. VPP HV -- Programming voltage. -- Master Clear with internal pull-up. MCLR ST RA4 TTL CMOS General purpose I/O. AN3 AN -- A/D Channel 3 input. CPS3 AN -- Capacitive sensing input 3. OSC2 -- CMOS Comparator C2 output. CLKOUT -- CMOS FOSC/4 output. T1OSO XTAL CLKR -- CMOS Clock Reference output. P2B -- CMOS PWM output. T1G ST XTAL -- Timer1 oscillator connection. Timer1 gate input. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2CTM = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be moved using the APFCON0 or APFCON1 register. 2: Default function location. 3: Internal Connection. No associated external pin. 2012 Microchip Technology Inc. Preliminary DS41673A-page 9 PIC16F1829LIN TABLE 1-2: PIC16F1829LIN PINOUT DESCRIPTION (CONTINUED) Name RA5/CLKIN/OSC1/T1OSI/ T1CKI/P2A(1)/CCP2(1) RB4/AN10/CPS10 Function Input Type RA5 TTL CLKIN CMOS -- OSC1 XTAL -- T1OSI XTAL XTAL T1CKI ST -- External clock input (EC mode). Crystal/Resonator (LP, XT, HS modes). Timer1 oscillator connection. Timer1 clock input. -- CMOS PWM output. ST CMOS Capture/Compare/PWM 2. RB4 TTL CMOS General purpose I/O. AN10 AN AN RB5 TTL RX ST RB6(3)/CS/LWAKE RB6 TTL CS/ LWAKE TTL RB7(3)/TX(1,2) RB7 TTL TX -- RC0/AN4/CPS4/C2IN+/P1D(1) RC0 TTL RC3/AN7/CPS7/C12IN3-/ P2A(1,2)/CCP2(1,2)/P1C(1,2)/ MDMIN CMOS General purpose I/O. P2A CPS10 RC2/AN6/CPS6/C12IN2-/ P1D(1,2)/P2B(1,2)/MDCIN1 Description CCP2 RB5(3)/RX(1,2)/ RC1/AN5/CPS5/C12IN1-/P1C(1) Output Type -- A/D Channel 10 input. -- Capacitive sensing input 10. CMOS General purpose I/O. -- USART asynchronous input. CMOS General purpose I/O. OD LIN Transceiver Chip Select and Wake-up. CMOS General purpose I/O. CMOS USART asynchronous transmit. CMOS General purpose I/O. AN4 AN -- A/D Channel 4 input. CPS4 AN -- Capacitive sensing input 4. C2IN+ AN -- Comparator C2 positive input. P1D -- RC1 TTL AN5 AN CMOS PWM output. CMOS General purpose I/O. -- A/D Channel 5 input. CPS5 AN -- Capacitive sensing input 5. C12IN1- AN -- Comparator C1 or C2 negative input. P1C -- RC2 TTL CMOS PWM output. CMOS General purpose I/O. AN6 AN -- CPS6 AN -- Capacitive sensing input 6. C12IN2- AN -- Comparator C1 or C2 negative input. P1D -- CMOS PWM output. CMOS PWM output. P2B -- MDCIN1 ST RC3 TTL AN7 AN -- A/D Channel 6 input. Modulator Carrier Input 1. CMOS General purpose I/O. -- A/D Channel 7 input. CPS7 AN -- Capacitive sensing input 7. C12IN3- AN -- Comparator C1 or C2 negative input. P2A -- CCP2 AN P1C -- MDMIN ST CMOS PWM output. -- Capacitive sensing input 2. CMOS PWM output. -- Modulator source input. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2CTM = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be moved using the APFCON0 or APFCON1 register. 2: Default function location. 3: Internal Connection. No associated external pin. DS41673A-page 10 Preliminary 2012 Microchip Technology Inc. PIC16F1829LIN TABLE 1-2: PIC16F1829LIN PINOUT DESCRIPTION (CONTINUED) Name RC4/C2OUT/SRNQ/P1B/ MDOUT RC5/P1A/CCP1// MDCIN2 Function Input Type RC4 TTL Output Type Description CMOS General purpose I/O. C2OUT -- CMOS Comparator C2 output. SRNQ -- CMOS SR latch inverting output. P1B -- CMOS PWM output. MDOUT -- CMOS Modulator output. RC5 TTL P1A -- CMOS PWM output. CCP1 ST CMOS Capture/Compare/PWM 1. MDCIN2 ST CMOS General purpose I/O. -- Modulator Carrier Input 2. RC6 RC6 -- -- No connection. RC7/POWERGOOD RC7 TTL -- POWERGOOD input from voltage regulator. -- TTL OD LIN Fault Indicator and Transmitter Enable. VBAT Battery Supply Power -- Battery voltage input to the LIN Transceiver and the voltage regulator. VREG Regulator Output -- Power LBUS Network Bus HV HV LIN/J2602 bus network connection. FAULT/TXE Regulated 5.0V output. VDD VDD Power -- Positive supply. VSS VSS Power -- Ground reference. LIN VSS VSS Power -- Ground reference for voltage regulator and LIN bus. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2CTM = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be moved using the APFCON0 or APFCON1 register. 2: Default function location. 3: Internal Connection. No associated external pin. 2012 Microchip Technology Inc. Preliminary DS41673A-page 11 PIC16F1829LIN NOTES: DS41673A-page 12 Preliminary 2012 Microchip Technology Inc. PIC16F1829LIN 2.0 USING THE PIC16F1829LIN IN LIN BUS APPLICATIONS Note: 2.1 Failure to follow the recommended setup and initialization may result in improper or unknown LIN operation. Hardware The PIC16F1829LIN internal connections are optimized to reduce the number of components in a typical LIN/J2602 node in a LIN bus system. Some features and modules of the stand-alone PIC16F1829 are no longer available or their functionality has changed. FIGURE 2-1: TYPICAL LIN NETWORK CONFIGURATION 40m + Return LIN bus VBB 1 k LIN bus MCP202X LIN bus MCP202X Slave 1 C LIN bus PIC16F1829LIN LIN bus MCP202X Slave 2 C Slave n <23 C Master C For this reason, the following figure (Figure 2-2) is a recommended block diagram. Note that the microcontroller is powered by the internal voltage regulator and an external connection must be made between VREG and VBB along with a load capacitor. FAULT/TXE can be monitored or controlled by any I/O pin. 2012 Microchip Technology Inc. Preliminary DS41673A-page 13 PIC16F1829LIN FIGURE 2-2: TYPICAL PIC16F1829LIN APPLICATION +12 RTP(3) 43V(3) CF (1) VBB CG VREG Master Node Only +12 VDD FAULT/TXE I/O 1 k LIN Bus LBUS 27V (2) VSS VSS Note 1: CF is the filter capacitor for the external voltage supply. 2: Transient suppressor diode. VCLAMP L = 27V. 3: These components are required for additional load dump protection above 43V. 2.2 Software Please refer to the sections of this data sheet to determine what facilities have changed and what register values need to be properly initialized. Failure to follow these guidelines may result in improper operation. DS41673A-page 14 Preliminary 2012 Microchip Technology Inc. PIC16F1829LIN 2.2.1 TYPICAL INITIALIZATION CODE InitialiseIOports banksel ANSELH MOVLW 0x04 ANDWF ANSELH,f banksel TRISB MOVLW 0xC0 IORWF TRISB,f MOVLW 0xCF ANDWF TRISB,f MOVLW 0x80 IORWF TRISC,f banksel LATB BSF LINCS RETURN SetupLINUSART banksel MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF CLRF MOVLW MOVWF banksel BSF RCSTA B'10010000' RCSTA B'00000100' TXSTA B'00001000' BAUDCON SPBRGH 0x31 SPBRG LATB LINCS ;disable AN8:9,11 ;PORTB7:6 must be inputs ;PORTB5:4 must be outputs ;PORTC7 is an input ;Chip Select Transceiver ;UART enabled,8-bit,continuous receive ;8-bit, asynchronous, high-baudrate ;16-bit Baud Rate Generator ;setup initially for 20KBaud @ 4.0MHz, BRGH=1, BRG16=1 ;to enable transceiver RETURN 2.2.2 SAMPLE TRANSMIT SOFTWARE This routine is called when PIR1<TXIF> = 1: PutDATAbyte banksel MOVF MOVWF INCF DECFSZ TXREG INDF0,w TXREG FSR0, f MESSAGE_COUNTER, f ; copy data byte into w-register ; point to next location ; decrement Message Counter by one RETURN 2012 Microchip Technology Inc. Preliminary DS41673A-page 15 PIC16F1829LIN 2.2.3 SAMPLE RECEIVE SOFTWARE The following routines are called when PIR1<RCIF> = 1: GetBREAK banksel BTFSS GOTO MOVF BTFSS GOTO DECF banksel BTFSS GOTO banksel BSF RETURN BadBREAKchar MOVF RETURN RCSTA RCSTA,FERR ; BadBREAKchar ; RCREG,w ; STATUS,Z BadBREAKchar ; MESSAGE_COUNTER PORTB LINRX $-2 BAUDCTL BAUDCTL,ABDEN ; RCREG,w was BREAK character longer than 8 bits? no, not a valid BREAK, too short dump break character, reset RCIF and FERR no, not a valid BREAK, not zero enable AutoBaud ; dump break character, reset RCIF and FERR GetSYNC banksel BTFSC GOTO BTFSC GOTO DECF MOVF DECF RETURN BadSYNCchar BCF MOVLW MOVWF RETURN GetDATAbyte banksel MOVF MOVWF MOVWF INCF DECF RETURN DS41673A-page 16 BAUDCTL BAUDCTL,ABDOVF; did baud rate generator overflow? BadSYNCchar; yes, bad sync character RCSTA,FERR; was there a Framing Error? BadSYNCchar; yes, bad sync character SPBRG RCREG,w ; dump sync character, reset RCIF MESSAGE_COUNTER BAUDCTL,ABDOVF; clear the overflow condition .12 ; reset the state machine MESSAGE_COUNTER RCREG RCREG,w ; RXTX_REG ; INDF0 ; FSR0, f ; MESSAGE_COUNTER, get character, reset RCIF and FERR copy data into w-register copy data into data area point to next location f ; decrement number of bytes to receive by one Preliminary 2012 Microchip Technology Inc. PIC16F1829LIN 2.3 Routing CCP4 to a Pin Normally, CCP4 uses RC6 as an output pin. This pin is not available on the PIC16F1829LIN. This output function can be re-routed to RC4, through the Data Signal Modulator (DSM), as shown below. ; Setup CCP4 banksel PR2 movlw 0xFF ; set PWM for highest resolution movwf PR2 banksel CCP4CON movlw b'00001100'; set for PWM mode movwf CCP4CON movlw 0x80 ; preload the duty cycle with a value movwf CCPR4L banksel CCPTMRS movlw 0x00 ; set Timer2 as clock source movwf CCPTMRS banksel PIR1 bcf PIR1,TMR2IF; clear timer overflow flag movlw b'00000101'; clock prescaler = 4 movwf T2CON bsf T2CON,TMR2ON; turn on Timer 2 ; Setup DSM to route CCP4 to RC4 banksel MDCON movlw b'11000000'; enable DSM, enable output pin movwf MDCON movlw 0x00 ; modulation controlled by MCBIT movwf MDSRC movlw 0x87 ; select CCP4 as carrier frequency and disable RC6 movwf MDCARL movwf MDCARH ; modulation source does not matter because high and low carriers are the ; same. 2012 Microchip Technology Inc. Preliminary DS41673A-page 17 PIC16F1829LIN NOTES: DS41673A-page 18 Preliminary 2012 Microchip Technology Inc. PIC16F1829LIN 3.0 ENHANCED MID-RANGE CPU See "PIC16(L)F1825/1829 Data Sheet" (DS41440) for description of the enhanced mid-range 8-bit CPU core. FIGURE 3-1: CORE BLOCK DIAGRAM 15 Configuration 15 MUX Flash Program Memory Program Bus 16-Level 8 Level Stack Stack (13-bit) (15-bit) 14 Instruction Instruction Reg reg 8 Data Bus Program Counter RAM Program Memory Read (PMR) 12 RAM Addr Addr MUX Indirect Addr 12 12 Direct Addr 7 5 BSR FSR Reg reg 15 FSR0reg Reg FSR FSR1 Reg FSR reg 15 STATUS Reg reg STATUS 8 3 Power-up Timer OSC1/CLKIN OSC2/CLKOUT Instruction Decodeand & Decode Control Timing Generation Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset MUX ALU 8 W Reg Internal Oscillator Block VDD 2012 Microchip Technology Inc. VSS Preliminary DS41673A-page 19 PIC16F1829LIN NOTES: DS41673A-page 20 Preliminary 2012 Microchip Technology Inc. PIC16F1829LIN 4.0 MEMORY ORGANIZATION See "PIC16(L)F1825/1829 Data Sheet" (DS41440) for descriptions of Program memory, Data RAM and Data EEPROM. 2012 Microchip Technology Inc. Preliminary DS41673A-page 21 PIC16F1829LIN MEMORY MAP, BANKS 0-7 BANK 0 Preliminary 000h 001h 002h 003h 004h 005h 006h 007h 008h 009h 00Ah 00Bh 00Ch 00Dh 00Eh 00Fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh 020h 2012 Microchip Technology Inc. 06Fh 070h BANK 1 BANK 2 07Fh Note 1: BANK 4 080h 081h 082h 083h 084h 085h 086h 087h 088h 089h 08Ah 08Bh 08Ch 08Dh 08Eh 08Fh 090h 091h 092h 093h 094h 095h 096h 097h 098h 099h 09Ah 09Bh 09Ch INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON TRISA TRISB TRISC -- -- PIE1 PIE2 -- -- OPTION_REG PCON WDTCON OSCTUNE OSCCON OSCSTAT ADRESL ADRESH 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON LATA LATB LATC -- -- CM1CON0 CM1CON1 CM2CON0 CM2CON1 CMOUT BORCON FVRCON DACCON0 DACCON1 SRCON0 SRCON1 -- 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON ANSELA ANSELB ANSELC -- -- EEADRL EEADRH EEDATL EEDATH EECON1 EECON2 -- -- RCREG TXREG SPBRGL SPBRGH 200h 201h 202h 203h 204h 205h 206h 207h 208h 209h 20Ah 20Bh 20Ch 20Dh 20Eh 20Fh 210h 211h 212h 213h 214h 215h 216h 217h 218h 219h 21Ah 21Bh 21Ch -- CPSCON0 CPSCON1 09Dh 09Eh 09Fh 0A0h ADCON0 ADCON1 -- 11Dh 11Eh 11Fh 120h APFCON0 APFCON1 -- 19Dh 19Eh 19Fh 1A0h RCSTA TXSTA BAUDCON 21Dh 21Eh 21Fh 220h General Purpose Register 96 Bytes General Purpose Register 80 Bytes 0EFh 0F0h General Purpose Register 80 Bytes 16Fh 170h Accesses 70h - 7Fh Legend: BANK 3 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON PORTA PORTB PORTC -- -- PIR1 PIR2 -- -- TMR0 TMR1L TMR1H T1CON T1GCON TMR2 PR2 T2CON 0FFh General Purpose Register 80 Bytes 1EFh 1F0h Accesses 70h - 7Fh 17Fh BANK 5 280h 281h 282h 283h 284h 285h 286h 287h 288h 289h 28Ah 28Bh 28Ch 28Dh 28Eh 28Fh 290h 291h 292h 293h 294h 295h 296h 297h 298h 299h 29Ah 29Bh 29Ch 29Dh 29Eh 29Fh 2A0h General Purpose Register 80 Bytes 26Fh 270h Accesses 70h - 7Fh 1FFh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON WPUA WPUB WPUC -- -- SSP1BUF SSP1ADD SSP1MSK SSP1STAT SSP1CON SSP1CON2 SSP1CON3 -- SSP2BUF SSP2ADD SSP2MSK SSP2STAT SSP2CON SSP2CON2 SSP2CON3 27Fh Registers in bold have functional differences. Please refer to the appropriate chapters for details. BANK 6 300h 301h 302h 303h 304h 305h 306h 307h 308h 309h 30Ah 30Bh 30Ch 30Dh 30Eh 30Fh 310h 311h 312h 313h 314h 315h 316h 317h 318h 319h 31Ah 31Bh 31Ch 31Dh 31Eh 31Fh 320h General Purpose Register 80 Bytes BANK 7 380h 381h 382h 383h 384h 385h 386h 387h 388h 389h 38Ah 38Bh 38Ch 38Dh 38Eh 38Fh 390h 391h 392h 393h 394h 395h 396h 397h 398h 399h 39Ah 39Bh 39Ch 39Dh 39Eh 39Fh 3A0h General Purpose Register 80 Bytes Accesses 70h - 7Fh 2FFh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- CCPR3L CCPR3H CCP3CON -- -- -- -- CCPR4L CCPR4H CCP4CON -- -- -- -- -- IOCBP IOCBN IOCBF -- -- -- CLKRCON -- MDCON MDSRC MDCARL MDCARH General Purpose Register 80 Bytes Accesses 70h - 7Fh 37Fh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON INLVLA INLVLB INLVLC -- -- IOCAP IOCAN IOCAF 3EFh 3F0h 36Fh 370h 2EFh 2F0h Accesses 70h - 7Fh = Unimplemented data memory locations, read as `0' INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- CCPR1L CCPR1H CCP1CON PWM1CON CCP1AS PSTR1CON -- CCPR2L CCPR2H CCP2CON PWM2CON CCP2AS PSTR2CON CCPTMRS -- Accesses 70h - 7Fh 3FFh PIC16F1829LIN DS41673A-page 22 TABLE 4-1: 2012 Microchip Technology Inc. TABLE 4-2: PIC16F1829LIN MEMORY MAP, BANKS 8-15 BANK 8 Preliminary INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- TMR4 PR4 T4CON -- -- -- -- TMR6 PR6 T6CON -- BANK 9 480h 481h 482h 483h 484h 485h 486h 487h 488h 489h 48Ah 48Bh 48Ch 48Dh 48Eh 48Fh 490h 491h 492h 493h 494h 495h 496h 497h 498h 499h 49Ah 49Bh 49Ch 49Dh 49Eh 49Fh 4A0h General Purpose Register 80 Bytes 46Fh 470h DS41673A-page 23 Legend: Note 1: BANK 10 500h 501h 502h 503h 504h 505h 506h 507h 508h 509h 50Ah 50Bh 50Ch 50Dh 50Eh 50Fh 510h 511h 512h 513h 514h 515h 516h 517h 518h 519h 51Ah 51Bh 51Ch 51Dh 51Eh 51Fh 520h General Purpose Register 80 Bytes 4EFh 4F0h Accesses 70h - 7Fh 47Fh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BANK 11 580h 581h 582h 583h 584h 585h 586h 587h 588h 589h 58Ah 58Bh 58Ch 58Dh 58Eh 58Fh 590h 591h 592h 593h 594h 595h 596h 597h 598h 599h 59Ah 59Bh 59Ch 59Dh 59Eh 59Fh 5A0h General Purpose Register 80 Bytes 56Fh 570h Accesses 70h - 7Fh 4FFh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- General Purpose Register 80 Bytes 5EFh 5F0h Accesses 70h - 7Fh 57Fh BANK 12 600h INDF0 601h INDF1 602h PCL 603h STATUS 604h FSR0L 605h FSR0H 606h FSR1L 607h FSR1H 608h BSR 609h WREG 60Ah PCLATH 60Bh INTCON 60Ch -- 60Dh -- 60Eh -- 60Fh -- 610h -- 611h -- 612h -- 613h -- 614h -- 615h -- 616h -- 617h -- 618h -- 619h -- 61Ah -- 61Bh -- 61Ch -- 61Dh -- 61Eh -- 61Fh -- 620h General Purpose Register 48 Bytes 64Fh 650h Unimplemented Read as `0' 66Fh 670h Accesses 70h - 7Fh 5FFh BANK 13 680h 681h 682h 683h 684h 685h 686h 687h 688h 689h 68Ah 68Bh 68Ch 68Dh 68Eh 68Fh 690h 691h 692h 693h 694h 695h 696h 697h 698h 699h 69Ah 69Bh 69Ch 69Dh 69Eh 69Fh 6A0h = Unimplemented data memory locations, read as `0' Registers in bold have functional differences. Please refer to the appropriate chapters for details. BANK 14 700h 701h 702h 703h 704h 705h 706h 707h 708h 709h 70Ah 70Bh 70Ch 70Dh 70Eh 70Fh 710h 711h 712h 713h 714h 715h 716h 717h 718h 719h 71Ah 71Bh 71Ch 71Dh 71Eh 71Fh 720h Unimplemented Read as `0' 6EFh 6F0h Accesses 70h - 7Fh 67Fh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BANK 15 780h 781h 782h 783h 784h 785h 786h 787h 788h 789h 78Ah 78Bh 78Ch 78Dh 78Eh 78Fh 790h 791h 792h 793h 794h 795h 796h 797h 798h 799h 79Ah 79Bh 79Ch 79Dh 79Eh 79Fh 7A0h Unimplemented Read as `0' 76Fh 770h Accesses 70h - 7Fh 6FFh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unimplemented Read as `0' 7EFh 7F0h Accesses 70h - 7Fh 77Fh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Accesses 70h - 7Fh 7FFh PIC16F1829LIN 400h 401h 402h 403h 404h 405h 406h 407h 408h 409h 40Ah 40Bh 40Ch 40Dh 40Eh 40Fh 410h 411h 412h 413h 414h 415h 416h 417h 418h 419h 41Ah 41Bh 41Ch 41Dh 41Eh 41Fh 420h PIC16F1829LIN MEMORY MAP, BANKS 16-23 BANK 16 Preliminary 800h 801h 802h 803h 804h 805h 806h 807h 808h 809h 80Ah 80Bh 80Ch 80Dh 80Eh 80Fh 810h 811h 812h 813h 814h 815h 816h 817h 818h 819h 81Ah 81Bh 81Ch 81Dh 81Eh 81Fh 820h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BANK 17 880h 881h 882h 883h 884h 885h 886h 887h 888h 889h 88Ah 88Bh 88Ch 88Dh 88Eh 88Fh 890h 891h 892h 893h 894h 895h 896h 897h 898h 899h 89Ah 89Bh 89Ch 89Dh 89Eh 89Fh 8A0h 2012 Microchip Technology Inc. Unimplemented Read as `0' 86Fh 870h Note 1: BANK 18 900h 901h 902h 903h 904h 905h 906h 907h 908h 909h 90Ah 90Bh 90Ch 90Dh 90Eh 90Fh 910h 911h 912h 913h 914h 915h 916h 917h 918h 919h 91Ah 91Bh 91Ch 91Dh 91Eh 91Fh 920h Unimplemented Read as `0' 8EFh 8F0h Accesses 70h - 7Fh 87Fh Legend: INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unimplemented Read as `0' INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Accesses 70h - 7Fh 8FFh 97Fh = Unimplemented data memory locations, read as `0'. BANK 20 A00h A01h A02h A03h A04h A05h A06h A07h A08h A09h A0Ah A0Bh A0Ch A0Dh A0Eh A0Fh A10h A11h A12h A13h A14h A15h A16h A17h A18h A19h A1Ah A1Bh A1Ch A1Dh A1Eh A1Fh A20h Unimplemented Read as `0' 9EFh 9F0h 96Fh 970h Accesses 70h - 7Fh BANK 19 980h 981h 982h 983h 984h 985h 986h 987h 988h 989h 98Ah 98Bh 98Ch 98Dh 98Eh 98Fh 990h 991h 992h 993h 994h 995h 996h 997h 998h 999h 99Ah 99Bh 99Ch 99Dh 99Eh 99Fh 9A0h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unimplemented Read as `0' Accesses 70h - 7Fh Registers in bold have functional differences. Please refer to the appropriate chapters for details. BANK 22 B00h B01h B02h B03h B04h B05h B06h B07h B08h B09h B0Ah B0Bh B0Ch B0Dh B0Eh B0Fh B10h B11h B12h B13h B14h B15h B16h B17h B18h B19h B1Ah B1Bh B1Ch B1Dh B1Eh B1Fh B20h Unimplemented Read as `0' Accesses 70h - 7Fh A7Fh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- AEFh AF0h A6Fh A70h 9FFh BANK 21 A80h A81h A82h A83h A84h A85h A86h A87h A88h A89h A8Ah A8Bh A8Ch A8Dh A8Eh A8Fh A90h A91h A92h A93h A94h A95h A96h A97h A98h A99h A9Ah A9Bh A9Ch A9Dh A9Eh A9Fh AA0h BANK 23 B80h B81h B82h B83h B84h B85h B86h B87h B88h B89h B8Ah B8Bh B8Ch B8Dh B8Eh B8Fh B90h B91h B92h B93h B94h B95h B96h B97h B98h B99h B9Ah B9Bh B9Ch B9Dh B9Eh B9Fh BA0h Unimplemented Read as `0' Unimplemented Read as `0' Accesses 70h - 7Fh B7Fh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BEFh BF0h B6Fh B70h Accesses 70h - 7Fh AFFh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Accesses 70h - 7Fh BFFh PIC16F1829LIN DS41673A-page 24 TABLE 4-3: 2012 Microchip Technology Inc. TABLE 4-4: PIC16F1829LIN MEMORY MAP, BANKS 24-31 BANK 24 Preliminary INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BANK 25 C80h C81h C82h C83h C84h C85h C86h C87h C88h C89h C8Ah C8Bh C8Ch C8Dh C8Eh C8Fh C90h C91h C92h C93h C94h C95h C96h C97h C98h C99h C9Ah C9Bh C9Ch C9Dh C9Eh C9Fh CA0h Unimplemented Read as `0' DS41673A-page 25 C6Fh C70h CFFh BANK 26 D00h D01h D02h D03h D04h D05h D06h D07h D08h D09h D0Ah D0Bh D0Ch D0Dh D0Eh D0Fh D10h D11h D12h D13h D14h D15h D16h D17h D18h D19h D1Ah D1Bh D1Ch D1Dh D1Eh D1Fh D20h Unimplemented Read as `0' CEFh CF0h Accesses 70h - 7Fh Legend: INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BANK 27 D80h D81h D82h D83h D84h D85h D86h D87h D88h D89h D8Ah D8Bh D8Ch D8Dh D8Eh D8Fh D90h D91h D92h D93h D94h D95h D96h D97h D98h D99h D9Ah D9Bh D9Ch D9Dh D9Eh D9Fh DA0h Unimplemented Read as `0' D6Fh D70h Accesses 70h - 7Fh CFFh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unimplemented Read as `0' DEFh DF0h Accesses 70h - 7Fh D7Fh = Unimplemented data memory locations, read as `0'. BANK 28 E00h E01h E02h E03h E04h E05h E06h E07h E08h E09h E0Ah E0Bh E0Ch E0Dh E0Eh E0Fh E10h E11h E12h E13h E14h E15h E16h E17h E18h E19h E1Ah E1Bh E1Ch E1Dh E1Eh E1Fh E20h BANK 29 E80h E81h E82h E83h E84h E85h E86h E87h E88h E89h E8Ah E8Bh E8Ch E8Dh E8Eh E8Fh E90h E91h E92h E93h E94h E95h E96h E97h E98h E99h E9Ah E9Bh E9Ch E9Dh E9Eh E9Fh EA0h Unimplemented Read as `0' E6Fh E70h Accesses 70h - 7Fh DFFh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BANK 30 F00h F01h F02h F03h F04h F05h F06h F07h F08h F09h F0Ah F0Bh F0Ch F0Dh F0Eh F0Fh F10h F11h F12h F13h F14h F15h F16h F17h F18h F19h F1Ah F1Bh F1Ch F1Dh F1Eh F1Fh F20h Unimplemented Read as `0' EEFh EF0h Accesses 70h - 7Fh E7Fh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BANK 31 F80h INDF0 F81h INDF1 F82h PCL F83h STATUS F84h FSR0L F85h FSR0H F86h FSR1L F87h FSR1H F88h BSR F89h WREG F8Ah PCLATH F8Bh INTCON F8Ch F8Dh F8Eh F8Fh F90h F91h F92h F93h F94h F95h F96h F97h See Table 4-5 for F98h register mapping F99h details F9Ah F9Bh F9Ch F9Dh F9Eh F9Fh FA0h Unimplemented Read as `0' F6Fh F70h Accesses 70h - 7Fh EFFh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- FEFh FF0h Accesses 70h - 7Fh F7Fh Accesses 70h - 7Fh FFFh PIC16F1829LIN C00h C01h C02h C03h C04h C05h C06h C07h C08h C09h C0Ah C0Bh C0Ch C0Dh C0Eh C0Fh C10h C11h C12h C13h C14h C15h C16h C17h C18h C19h C1Ah C1Bh C1Ch C1Dh C1Eh C1Fh C20h PIC16F1829LIN TABLE 4-5: PIC16F1829LIN MEMORY MAP, BANK 31 Bank 31 F8Ch Unimplemented Read as `0' FE3h FE4h FE5h FE6h FE7h FE8h FE9h FEAh FEBh FECh FEDh FEEh FEFh Legend: STATUS_SHAD WREG_SHAD BSR_SHAD PCLATH_SHAD FSR0L_SHAD FSR0H_SHAD FSR1L_SHAD FSR1H_SHAD -- STKPTR TOSL TOSH = Unimplemented data memory locations, read as `0'. DS41673A-page 26 Preliminary 2012 Microchip Technology Inc. PIC16F1829LIN TABLE 4-6: Address Name SPECIAL FUNCTION REGISTER SUMMARY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 0 000h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 001h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 002h(1) PCL Program Counter (PC) Least Significant Byte 003h(1) STATUS 004h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 005h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 006h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 007h(1) FSR1H Indirect Data Memory Address 1 High Pointer 008h(1) BSR 009h(1) WREG 00Ah(1) PCLATH -- 00Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000 00Ch PORTA -- -- RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --xx xxxx 00Dh(2) PORTB LINTX LINCS LINRX RB4 -- -- -- -- xxxx ---- xxxx ---- 00Eh(2) PORTC PWRGD -- RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx xxxx xxxx 00Fh -- Unimplemented -- -- 010h -- Unimplemented -- -- 011h PIR1 TMR1GIF ADIF 012h PIR2 OSFIF C2IF C1IF 013h PIR3 -- -- CCP4IF 014h PIR4 -- -- -- -- 015h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu 016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 018h T1CON TMR1CS1 TMR1CS0 019h T1GCON TMR1GE T1GPOL 01Ah TMR2 Timer2 Module Register 01Bh PR2 Timer2 Period Register 01Ch T2CON -- -- -- -- -- 0000 0000 0000 0000 TO PD Z DC C ---1 1000 ---q quuu 0000 0000 0000 0000 -- BSR<4:0> ---0 0000 ---0 0000 Working Register 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter -- RCIF TXIF SSP1IF CCP1IF EEIF BCL1IF CCP3IF TMR6IF -- T1CKPS<1:0> T1GTM -000 0000 -000 0000 T1GSPM TMR2IF TMR1IF 0000 0000 0000 0000 -- -- CCP2IF 0000 0--0 0000 0--0 -- TMR4IF -- --00 0-0- --00 0-0- -- BCL2IF SSP2IF ---- --00 ---- --00 xxxx xxxx uuuu uuuu T1OSCEN T1SYNC T1GGO/ DONE T1GVAL -- TMR1ON T1GSS<1:0> 0000 00-0 uuuu uu-u 0000 0x00 uuuu uxuu 0000 0000 0000 0000 1111 1111 1111 1111 T2OUTPS<3:0> 01Dh -- 01Eh CPSCON0 CPSON CPSRM -- -- 01Fh CPSCON1 -- -- -- -- TMR2ON T2CKPS<1:0> Unimplemented -000 0000 -000 0000 -- CPSRNG<1:0> CPSOUT T0XCS CPSCH<3:0> ---- 0000 ---- 0000 Legend: Note x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. 1: These registers can be addressed from any bank. 2: Registers in bold have functional differences. Please refer to the appropriate chapters in the data sheet for details. 2012 Microchip Technology Inc. Preliminary -- 00-- 0000 00-- 0000 DS41673A-page 27 PIC16F1829LIN TABLE 4-6: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 1 080h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 081h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 082h(1) PCL Program Counter (PC) Least Significant Byte 083h(1) STATUS 084h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 085h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 086h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 087h(1) FSR1H Indirect Data Memory Address 1 High Pointer 088h(1) BSR 089h(1) WREG 08Ah(1) PCLATH -- 08Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000 08Ch TRISA -- -- TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 08Dh(2) TRISB TRISB7 TRISB6 TRISB5 TRISB4 -- -- -- -- 1111 ---- 1111 ---- 08Eh(2) TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111 -- -- -- -- 0000 0000 0000 0000 -- TO PD Z DC C ---1 1000 ---q quuu 0000 0000 0000 0000 -- BSR<4:0> ---0 0000 ---0 0000 Working Register 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 08Fh -- Unimplemented -- -- 090h -- Unimplemented -- -- 091h(2) PIE1 TMR1GIE ADIE 092h PIE2 OSFIE C2IE C1IE 093h PIE3 -- -- CCP4IE 094h(2) PIE4 -- -- -- 095h OPTION_REG WPUEN INTEDG STKOVF STKUNF -- -- -- 096h PCON 097h WDTCON 098h OSCTUNE -- 099h OSCCON SPLLEN 09Ah OSCSTAT T1OSCR 09Bh ADRESL A/D Result Register Low 09Ch ADRESH A/D Result Register High 09Dh ADCON0 -- 09Eh ADCON1 ADFM 09Fh -- RCIE TXIE SSP1IE CCP1IE EEIE BCL1IE CCP3IE TMR6IE -- -- TMR0CS TMR0SE PSA -- -- TMR1IE 0000 0000 0000 0000 -- -- CCP2IE 0000 0--0 0000 0--0 -- TMR4IE -- --00 0-0- --00 0-0- -- BCL2IE SSP2IE PS<2:0> RMCLR RI POR WDTPS<4:0> OSTS HFIOFR BOR 00-- 11qq qq-- qquu SWDTEN --01 0110 --01 0110 --00 0000 --00 0000 -- HFIOFL ---- --00 ---- --00 1111 1111 1111 1111 TUN<5:0> IRCF<3:0> PLLR TMR2IE MFIOFR SCS<1:0> LFIOFR HFIOFS 0011 1-00 0011 1-00 10q0 0q00 qqqq qq0q xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CHS<4:0> ADCS<2:0> GO/DONE -- ADNREF ADON ADPREF<1:0> Unimplemented -000 0000 -000 0000 0000 -000 0000 -000 -- Legend: Note x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. 1: These registers can be addressed from any bank. 2: Registers in bold have functional differences. Please refer to the appropriate chapters in the data sheet for details. DS41673A-page 28 Preliminary 2012 Microchip Technology Inc. -- PIC16F1829LIN TABLE 4-6: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 2 100h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 101h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 102h(1) PCL Program Counter (PC) Least Significant Byte 103h(1) STATUS 104h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 105h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 106h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 107h(1) FSR1H Indirect Data Memory Address 1 High Pointer 108h(1) BSR 109h(1) WREG 10Ah(1) PCLATH -- 10Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000 10Ch LATA -- -- LATA5 LATA4 -- LATA2 LATA1 LATA0 --xx -xxx --uu -uuu 10Dh(2) LATB LATB7 LATB6 LATB5 LATB4 -- -- -- -- xxxx ---- xxxx ---- 10Eh(2) LATC PWRGD -- LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx uuuu uuuu -- -- -- -- 0000 0000 0000 0000 -- TO PD Z DC C ---1 1000 ---q quuu 0000 0000 0000 0000 -- BSR<4:0> ---0 0000 ---0 0000 Working Register 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 10Fh -- Unimplemented -- -- 110h -- Unimplemented -- -- 111h CM1CON0 C1ON C1OUT C1OE C1POL 112h CM1CON1 C1INTP C1INTN 113h CM2CON0 C2ON C2OUT 114h CM2CON1 C2INTP C2INTN 115h CMOUT -- -- -- -- 116h BORCON SBOREN -- -- -- -- C1PCH<1:0> C2OE C2POL C2PCH<1:0> C1SP C1HYS -- -- C1NCH1 C1NCH0 0000 ---0 0000 ---0 -- C2SP C2HYS C2SYNC 0000 -100 0000 -100 -- -- -- -- -- -- 117h FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> 118h DACCON0 DACEN DACLPS DACOE -- DACPSS<1:0> 119h DACCON1 -- -- -- 11Ah SRCON0 SRLEN 11Bh SRCON1 SRSPE 11Ch -- 11Dh(2) APFCON0 11Eh(2) APFCON1 11Fh -- C2NCH<1:0> MC2OUT -- ---- --00 ---- --00 BORRDY 1--- ---q u--- ---u ADFVR<1:0> -- 0000 -100 0000 -100 0000 --00 0000 --00 MC1OUT 0q00 0000 0q00 0000 DACNSS DACR<4:0> SRCLK<2:0> SRSCKE C1SYNC 000- 00-0 000- 00-0 ---0 0000 ---0 0000 SRQEN SRNQEN SRPS SRPR 0000 0000 0000 0000 SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E 0000 0000 0000 0000 -- 000- 0000 000- 0000 Unimplemented -- RXDTSEL -- -- -- T1GSEL TXCKSEL -- -- -- -- -- P1DSEL P1CSEL P2BSEL CCP2SEL --00 0000 --00 0000 Unimplemented -- Legend: Note x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. 1: These registers can be addressed from any bank. 2: Registers in bold have functional differences. Please refer to the appropriate chapters in the data sheet for details. 2012 Microchip Technology Inc. Preliminary -- DS41673A-page 29 -- PIC16F1829LIN TABLE 4-6: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 3 180h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 181h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 182h(1) PCL Program Counter (PC) Least Significant Byte 183h(1) STATUS 184h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 185h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 186h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 187h(1) FSR1H Indirect Data Memory Address 1 High Pointer 188h(1) BSR 189h(1) WREG 18Ah(1) PCLATH -- 18Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000 18Ch ANSELA -- -- -- ANSA4 -- ANSA2 ANSA1 ANSA0 ---1 -111 ---1 -111 18Dh(2) ANSELB ANSB7 ANSB6 ANSB5 ANSB4 -- -- -- -- 1111 ---- 1111 ---- 18Eh(2) ANSELC ANSC7 -- -- -- ANSC3 ANSC2 ANSC1 ANSC0 11-- 1111 11-- 1111 -- -- -- 0000 0000 0000 0000 -- -- TO PD Z DC C ---1 1000 ---q quuu 0000 0000 0000 0000 -- BSR<4:0> ---0 0000 ---0 0000 Working Register 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 18Fh -- Unimplemented -- -- 190h -- Unimplemented -- -- 191h EEADRL 192h EEADRH 193h EEDATL 194h EEDATH 195h EECON1 196h EECON2 EEPROM / Program Memory Address Register Low Byte -- 0000 0000 0000 0000 EEPROM / Program Memory Address Register High Byte -000 0000 -000 0000 EEPROM / Program Memory Read Data Register Low Byte -- -- EEPGD CFGS xxxx xxxx uuuu uuuu EEPROM / Program Memory Read Data Register High Byte LWLO FREE WRERR WREN WR --xx xxxx --uu uuuu RD EEPROM control register 2 0000 x000 0000 q000 0000 0000 0000 0000 197h -- Unimplemented -- -- 198h -- Unimplemented -- -- 199h RCREG EUSART Receive Data Register 0000 0000 0000 0000 19Ah TXREG EUSART Transmit Data Register 0000 0000 0000 0000 19Bh SPBRGL BRG<7:0> 0000 0000 0000 0000 19Ch SPBRGH BRG<15:8> 19Dh RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 19Eh TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 19Fh(2) BAUDCON ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 01-0 0-00 01-0 0-00 0000 0000 0000 0000 Legend: Note x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. 1: These registers can be addressed from any bank. 2: Registers in bold have functional differences. Please refer to the appropriate chapters in the data sheet for details. DS41673A-page 30 Preliminary 2012 Microchip Technology Inc. PIC16F1829LIN TABLE 4-6: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 4 200h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 201h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 202h(1) PCL Program Counter (PC) Least Significant Byte 203h(1) STATUS 204h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 205h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 206h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 207h(1) FSR1H Indirect Data Memory Address 1 High Pointer 208h(1) BSR 209h(1) WREG 20Ah(1) PCLATH -- 20Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000 20Ch WPUA -- -- WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 --11 1111 --11 1111 20Dh(2) WPUB WPUB7 WPUB6 WPUB5 WPUB4 -- -- -- -- 1111 ---- 1111 ---- 20Eh(2) WPUC WPUC7 WPUC6 WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 1111 1111 1111 1111 -- -- -- -- -- 0000 0000 0000 0000 TO PD Z DC C ---1 1000 ---q quuu 0000 0000 0000 0000 -- BSR<4:0> ---0 0000 ---0 0000 Working Register 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 20Fh -- Unimplemented -- -- 210h -- Unimplemented -- -- 211h(2) SSP1BUF 212h(2) 213h(2) 214h(2) SSP1STAT 0 0 0 0 215h(2) SSP1CON1 0 0 0 0 216h(2) SSP1CON2 0 0 0 0 0 217h(2) SSP1CON3 0 0 0 0 0 218h Don't care xxxx xxxx uuuu uuuu SSP1ADD Don't care 0000 0000 0000 0000 SSP1MSK Don't care -- 1111 1111 1111 1111 0 0 0 0 0 0 0 0000 0000 0000 0000 0 0 0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Unimplemented -- 219h(2) SSP2BUF 21Ah(2) 21Bh(2) 21Ch(2) SSP2STAT 0 0 0 0 21Dh(2) SSP2CON1 0 0 0 0 21Eh(2) SSP2CON2 0 0 0 0 0 21Fh(2) SSP2CON3 0 0 0 0 0 xxxx xxxx uuuu uuuu SSP2ADD Don't care 0000 0000 0000 0000 SSP2MSK Don't care 1111 1111 1111 1111 0 0 0 0 0 0 0 0000 0000 0000 0000 0 0 0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Legend: Note -- Don't care x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. 1: These registers can be addressed from any bank. 2: Registers in bold have functional differences. Please refer to the appropriate chapters in the data sheet for details. 2012 Microchip Technology Inc. Preliminary DS41673A-page 31 PIC16F1829LIN TABLE 4-6: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 5 280h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 281h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 282h(1) PCL Program Counter (PC) Least Significant Byte 283h(1) STATUS 284h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 285h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 286h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 287h(1) FSR1H Indirect Data Memory Address 1 High Pointer 288h(1) BSR 289h(1) WREG 28Ah(1) PCLATH -- 28Bh(1) INTCON GIE -- -- -- -- -- 0000 0000 0000 0000 TO PD Z DC C ---1 1000 ---q quuu 0000 0000 0000 0000 -- BSR<4:0> ---0 0000 ---0 0000 Working Register 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE -000 0000 -000 0000 TMR0IF INTF IOCIF 0000 0000 0000 0000 28Ch -- Unimplemented -- -- 28Dh -- Unimplemented -- -- 28Eh -- Unimplemented -- -- 28Fh -- Unimplemented -- -- 290h -- Unimplemented -- -- 291h CCPR1L Capture/Compare/PWM Register 1 (LSB) 292h CCPR1H Capture/Compare/PWM Register 1 (MSB) 293h CCP1CON 294h PWM1CON 295h CCP1AS 296h PSTR1CON P1M<1:0> xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu DC1B<1:0> P1RSEN CCP1M<3:0> 0000 0000 0000 0000 P1DC<6:0> CCP1ASE CCP1AS<2:0> -- -- -- 0000 0000 0000 0000 PSS1AC<1:0> STR1SYNC STR1D STR1C PSS1BD<1:0> STR1B STR1A 0000 0000 0000 0000 ---0 0001 ---0 0001 297h -- 298h CCPR2L Capture/Compare/PWM Register 2 (LSB) 299h CCPR2H Capture/Compare/PWM Register 2 (MSB) 29Ah CCP2CON P2M1 P2M0 DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 0000 0000 0000 0000 29Bh PWM2CON P2RSEN P2DC6 P2DC5 P2DC4 P2DC3 P2DC2 P2DC1 P2DC0 0000 0000 0000 0000 29Ch CCP2AS CCP2ASE CCP2AS2 CCP2AS1 CCP2AS0 PSS2AC1 PSS2AC0 PSS2BD1 29Dh PSTR2CON -- -- -- STR2SYNC STR2D STR2C STR2B 29Eh(2) CCPTMRS 0 C4TSEL0 C3TSEL1 C3TSEL0 C2TSEL1 C2TSEL0 C1TSEL1 29Fh -- Unimplemented -- xxxx xxxx uuuu uuuu PSS2BD0 0000 0000 0000 0000 STR2A ---0 0001 ---0 0001 C1TSEL0 0000 0000 0000 0000 Unimplemented -- Legend: Note x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. 1: These registers can be addressed from any bank. 2: Registers in bold have functional differences. Please refer to the appropriate chapters in the data sheet for details. DS41673A-page 32 -- xxxx xxxx uuuu uuuu Preliminary 2012 Microchip Technology Inc. -- PIC16F1829LIN TABLE 4-6: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 6 300h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 301h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 302h(1) PCL Program Counter (PC) Least Significant Byte 303h(1) STATUS 304h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 305h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 306h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 307h(1) FSR1H Indirect Data Memory Address 1 High Pointer 308h(1) BSR 309h(1) WREG 30Ah(1) PCLATH -- 30Bh(1) INTCON GIE -- -- -- -- -- 0000 0000 0000 0000 TO PD Z DC C ---1 1000 ---q quuu 0000 0000 0000 0000 -- BSR<4:0> ---0 0000 ---0 0000 Working Register 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE -000 0000 -000 0000 TMR0IF INTF IOCIF 0000 0000 0000 0000 30Ch -- Unimplemented -- -- 30Dh -- Unimplemented -- -- 30Eh -- Unimplemented -- -- 30Fh -- Unimplemented -- -- 310h -- Unimplemented -- -- 311h CCPR3L Capture/Compare/PWM Register 3 (LSB) 312h CCPR3H Capture/Compare/PWM Register 3 (MSB) 313h CCP3CON -- -- DC3B1 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu DC3B0 CCP3M3 CCP3M2 CCP3M1 CCP3M0 --00 0000 --00 0000 314h -- Unimplemented -- -- 315h -- Unimplemented -- -- 316h -- Unimplemented -- -- 317h -- Unimplemented -- -- 318h CCPR4L Capture/Compare/PWM Register 4 (LSB) 319h CCPR4H Capture/Compare/PWM Register 4 (MSB) 31Ah CCP4CON P4M1 P4M0 DC4B1 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 --00 0000 --00 0000 31Bh -- Unimplemented -- -- 31Ch -- Unimplemented -- -- 31Dh -- Unimplemented -- -- 31Eh -- Unimplemented -- -- 31Fh -- Unimplemented -- -- Legend: Note x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. 1: These registers can be addressed from any bank. 2: Registers in bold have functional differences. Please refer to the appropriate chapters in the data sheet for details. 2012 Microchip Technology Inc. Preliminary DS41673A-page 33 PIC16F1829LIN TABLE 4-6: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 7 380h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 381h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 382h(1) PCL Program Counter (PC) Least Significant Byte 383h(1) STATUS 384h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 385h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 386h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 387h(1) FSR1H Indirect Data Memory Address 1 High Pointer 388h(1) BSR 389h(1) WREG 38Ah(1) PCLATH -- 38Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000 38Ch INLVLA -- -- INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 --00 0100 --00 0100 -- -- -- -- -- 0000 0000 0000 0000 TO PD Z DC C ---1 1000 ---q quuu 0000 0000 0000 0000 -- BSR<4:0> ---0 0000 ---0 0000 Working Register 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 38Dh INLVLB INLVLB7 INLVLB6 INLVLB5 INLVLB4 -- -- -- -- 0000 ---- 0000 ---- 38Eh INLVLC INLVLC7 INLVLC6 INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 11xx xxxx 11xx xxxx 38Fh -- Unimplemented -- -- 390h -- Unimplemented -- -- 391h IOCAP -- -- IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 --00 0000 --00 0000 392h IOCAN -- -- IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 --00 0000 --00 0000 393h IOCAF -- -- IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 --00 0000 --00 0000 394h IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 -- -- -- -- 0000 ---- 0000 ---- 395h IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 -- -- -- -- 0000 ---- 0000 ---- 396h IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 -- -- -- -- 0000 ---- 0000 ---- 397h -- Unimplemented -- -- 398h -- Unimplemented -- -- 399h -- Unimplemented -- -- 39Ah CLKRCON CLKREN 39Bh -- 39Ch MDCON MDEN 39Dh MDSRC MDMSODIS 39Eh MDCARL MDCLODIS 39Fh MDCARH MDCHODIS CLKROE CLKRSLR CLKRDC<1:0> CLKRDIV<2:0> 0011 0000 0011 0000 Unimplemented -- MDOE MDOUT MDOPOL -- -- -- MDMS<3:0> x--- xxxx u--- uuuu MDCLPOL MDCLSYNC -- MDCL<3:0> xxx- xxxx uuu- uuuu MDCHPOL MDCHSYNC -- MDCH<3:0> xxx- xxxx uuu- uuuu -- -- MDBIT 0010 ---0 0010 ---0 Legend: Note x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. 1: These registers can be addressed from any bank. 2: Registers in bold have functional differences. Please refer to the appropriate chapters in the data sheet for details. DS41673A-page 34 -- MDSLR Preliminary 2012 Microchip Technology Inc. PIC16F1829LIN TABLE 4-6: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 8 400h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 401h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 402h(1) PCL Program Counter (PC) Least Significant Byte 403h(1) STATUS 404h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 405h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 406h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 407h(1) FSR1H Indirect Data Memory Address 1 High Pointer 408h(1) BSR 409h(1) WREG 40Ah(1) PCLATH -- 40Bh(1) INTCON GIE -- -- -- -- -- 0000 0000 0000 0000 TO PD Z DC C ---1 1000 ---q quuu 0000 0000 0000 0000 -- BSR<4:0> ---0 0000 ---0 0000 Working Register 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE -000 0000 -000 0000 TMR0IF INTF IOCIF 0000 0000 0000 0000 40Ch -- Unimplemented -- -- 40Dh -- Unimplemented -- -- 40Eh -- Unimplemented -- -- 40Fh -- Unimplemented -- -- 410h -- Unimplemented -- -- 411h -- Unimplemented -- -- 412h -- Unimplemented -- -- 413h -- Unimplemented -- -- 414h -- Unimplemented -- -- 415h TMR4 Timer4 Module Register 416h PR4 Timer4 Period Register 417h T4CON 418h -- Unimplemented -- -- 419h -- Unimplemented -- -- 41Ah -- Unimplemented -- -- 41Bh -- Unimplemented -- -- 41Ch -- TMR6 Timer6 Module Register 41Dh PR6 Timer6 Period Register 41Eh T6CON 41Fh -- -- 0000 0000 0000 0000 1111 1111 1111 1111 T4OUTPS<3:0> TMR4ON T4CKPS<1:0> -000 0000 -000 0000 0000 0000 0000 0000 1111 1111 1111 1111 T6OUTPS<3:0> TMR6ON T6CKPS<1:0> Unimplemented -000 0000 -000 0000 -- Legend: Note x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. 1: These registers can be addressed from any bank. 2: Registers in bold have functional differences. Please refer to the appropriate chapters in the data sheet for details. 2012 Microchip Technology Inc. Preliminary DS41673A-page 35 -- PIC16F1829LIN TABLE 4-6: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Banks 9-30 x00h/ x80h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx x00h/ x81h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx x02h/ x82h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 x03h/ x83h(1) STATUS x04h/ x84h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu x05h/ x85h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 x06h/ x86h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu x07h/ x87h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000 x08h/ x88h(1) BSR x09h/ x89h(1) WREG x0Ah/ x8Ah(1) PCLATH -- x0Bh/ x8Bh(1) INTCON GIE -- -- -- x0Ch/ x8Ch -- x1Fh/ x9Fh -- -- -- TO PD -- Z DC C BSR<4:0> ---1 1000 ---q quuu ---0 0000 ---0 0000 Working Register 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE -000 0000 -000 0000 TMR0IF INTF IOCIF Unimplemented 0000 0000 0000 0000 -- Legend: Note x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. 1: These registers can be addressed from any bank. 2: Registers in bold have functional differences. Please refer to the appropriate chapters in the data sheet for details. DS41673A-page 36 Preliminary 2012 Microchip Technology Inc. -- PIC16F1829LIN TABLE 4-6: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 31 F80h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx F81h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx F82h(1) PCL Program Counter (PC) Least Significant Byte F83h(1) STATUS F84h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu F85h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 F86h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu F87h(1) FSR1H Indirect Data Memory Address 1 High Pointer F88h(1) BSR F89h(1) WREG F8Ah(1) PCLATH -- F8Bh(1) INTCON GIE F8Ch -- FE3h -- -- -- FE4h -- STATUS_ -- -- 0000 0000 0000 0000 TO PD Z DC C 0000 0000 0000 0000 -- BSR<4:0> ---0 0000 ---0 0000 Working Register 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE -000 0000 -000 0000 TMR0IF INTF IOCIF Unimplemented -- ---1 1000 ---q quuu 0000 0000 0000 0000 -- -- -- -- -- Z_SHAD DC_SHAD C_SHAD -- ---- -xxx ---- -uuu SHAD FE5h WREG_ Working Register Shadow 0000 0000 uuuu uuuu SHAD FE6h BSR_ -- -- -- Bank Select Register Shadow ---x xxxx ---u uuuu SHAD FE7h PCLATH_ -- Program Counter Latch High Register Shadow -xxx xxxx uuuu uuuu SHAD FE8h FSR0L_ Indirect Data Memory Address 0 Low Pointer Shadow xxxx xxxx uuuu uuuu Indirect Data Memory Address 0 High Pointer Shadow xxxx xxxx uuuu uuuu Indirect Data Memory Address 1 Low Pointer Shadow xxxx xxxx uuuu uuuu Indirect Data Memory Address 1 High Pointer Shadow xxxx xxxx uuuu uuuu SHAD FE9h FSR0H_ SHAD FEAh FSR1L_ SHAD FEBh FSR1H_ SHAD FECh -- FEDh STKPTR FEEh TOSL FEFh TOSH Unimplemented -- -- -- -- Current Stack pointer Top-of-Stack Low byte -- xxxx xxxx uuuu uuuu Top-of-Stack High byte -xxx xxxx -uuu uuuu Legend: Note x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. 1: These registers can be addressed from any bank. 2: Registers in bold have functional differences. Please refer to the appropriate chapters in the data sheet for details. 2012 Microchip Technology Inc. -- ---1 1111 ---1 1111 Preliminary DS41673A-page 37 PIC16F1829LIN 5.0 I/O PORTS 5.1 Alternate Pin Function The Alternate Pin Function Control 0 (APFCON0) and Alternate Pin Function Control 1 (APFCON1) registers are used to steer specific peripheral input and output functions between different pins. It functions the same as described in the "PIC16(L)F1825/1829 Data Sheet" (DS41440) with the differences described below. The APFCON0 and APFCON1 registers are shown in Register 5-1 and Register 5-2. For this device family, the following functions can be moved between different pins. * * * * RX/DT/TX/CK T1G P1B/P1C/P1D/P2B CCP1/P1A/CCP2 These bits have no effect on the values of any TRIS register. PORT and TRIS overrides will be routed to the correct pin. The unselected pin will be unaffected. Register Definitions: Alternate Pin Function Control REGISTER 5-1: R/W-0/0 APFCON0: ALTERNATE PIN FUNCTION CONTROL REGISTER 0 R/W-0/0 RXDTSEL -- R/W-0/0 -- U-0 R/W-0/0 R/W-0/0 U-0 U-0 -- T1GSEL TXCKSEL -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 RXDTSEL: Pin Selection bit 0 = RX/DT function is on RB5 1 = Do not use bit 6-4 Unimplemented: Read as `0' bit 3 T1GSEL: Pin Selection bit 0 = T1G function is on RA4 1 = T1G function is on RA3 bit 2 TXCKSEL: Pin Selection bit 0 = TX/CK function is on RB7 1 = TX/CK function is on RC4 bit 1-0 Unimplemented: Read as `0' DS41673A-page 38 Preliminary 2012 Microchip Technology Inc. PIC16F1829LIN REGISTER 5-2: U-0 APFCON1: ALTERNATE PIN FUNCTION CONTROL REGISTER 1 U-0 -- -- R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 -- P1DSEL P1CSEL P2BSEL CCP2SEL -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 Unimplemented: Read as `0' bit 3 P1DSEL: Pin Selection bit 0 = P1D function is on RC2 1 = P1D function is on RC0 bit 2 P1CSEL: Pin Selection bit 0 = P1C function is on RC3 1 = P1C function is on RC1 bit 1 P2BSEL: Pin Selection bit 0 = P2B function is on RC2 1 = P2B function is on RA4 bit 0 CCP2SEL: Pin Selection bit 0 = CCP2 function is on RC3 1 = CCP2 function is on RA5 2012 Microchip Technology Inc. Preliminary DS41673A-page 39 PIC16F1829LIN 5.2 PORTB Registers PORTB is a 4-bit wide, bidirectional port. It functions the same as described in the "PIC16(L)F1825/1829 Data Sheet" (DS41440) with the following differences: * Three bits are dedicated to the LIN transceiver. No pins are associated with this function. Only RB4 is available on a pin. The corresponding data direction register is TRISB. The TRISB bits must be set as `001x 0000'. * The PORTB Data Latch register (LATB) is also memory-mapped. Read-modify-write operations on the LATB register read and write the latched output value for PORTB. EXAMPLE 5-1: banksel PORTB MOVLW 0C0h MOVWF PORTB banksel LATB CLRF LATB banksel TRISB MOVLW 030h MOVWF Note: 5.2.1 TRISB INITIALIZING PORTB ; ; ; ; ; set LINCS and LINTX high Initialize PORTB by clearing output data latches ; Alternate method ; to clear output ; data latches ; ; ; ; ; Value used to initialize data direction Set RB<7:6> as outputs and RB<5:4> as inputs On a Power-on Reset, RB<5:4> are configured as analog inputs by default and read as `0'. ANSELB REGISTER The ANSELB register (Register 5-6) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELB bit high will cause all digital reads on the pin to be read as `0' and allow analog functions on the pin to operate correctly. The state of the ANSELB bits has no effect on digital output functions. A pin with TRIS clear and ANSELB set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing READ-MODIFY-WRITE instructions on the affected port. Note: The ANSELB bits default to the Analog mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to `0' by user software. DS41673A-page 40 Preliminary 2012 Microchip Technology Inc. PIC16F1829LIN REGISTER 5-3: PORTB: PORTB REGISTER R/W-x R/W-x R/W-x R/W-x U-0 U-0 U-0 U-0 LINTX LINCS LINRX RB4 -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 LINTX: Dedicated the LIN Transceiver Transmit Function bit 6 LINCS: Dedicated the LIN Transceiver Chip Select Function bit 5 LINRX: Dedicated the LIN Transceiver Receive Function bit 4 RB4: Port I/O pin bit bit 3-0 Unimplemented: Read as `0' REGISTER 5-4: x = Bit is unknown TRISB: PORTB TRI-STATE REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 U-0 U-0 U-0 U-0 TRISB7 TRISB6 TRISB5 TRISB4 -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 TRISB7: Must be set to `0', Dedicated the LIN Transceiver Transmit Function bit 6 TRISB6: Must be set to '0', Dedicated the LIN Transceiver Chip Select Function bit 5 TRISB5: Must be set to '1', Dedicated the LIN Transceiver Receive Function bit 4 TRISB4: PORTB4 Tri-State Control bits 1 = PORTB pin configured as an input (tri-stated) 0 = PORTB pin configured as an output bit 3-0 Unimplemented: Read as `0' 2012 Microchip Technology Inc. Preliminary DS41673A-page 41 PIC16F1829LIN REGISTER 5-5: LATB: PORTB DATA LATCH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u U-0 U-0 U-0 U-0 LATB7 LATB6 LATB5 LATB4 -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-5 LATB<7:5>: Dedicated the LIN Transceiver Transmit Function(1) bit 4 LATB4: RB4 Port I/O Output Latch Register bit(1) bit 3-0 Unimplemented: Read as `0' Note 1: Writes to PORTB are actually written to the corresponding LATB register. Reads from the PORTB register actually return the I/O pin values. REGISTER 5-6: ANSELB: PORTB ANALOG SELECT REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 U-0 U-0 U-0 U-0 ANSB7 ANSB6 ANSB5 ANSB4 -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-5 ANSB<7:5>: Analog Select between Analog or Digital Function on Pins RB<7:5> 0 = Must be set to `0'. Digital I/O. Pin is assigned to port or digital special function. 1 = Not used bit 4 ANSB4: Analog Select between Analog or Digital Function on Pin RB4 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer is disabled. bit 3-0 Unimplemented: Read as `0' Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. DS41673A-page 42 Preliminary 2012 Microchip Technology Inc. PIC16F1829LIN REGISTER 5-7: WPUB: WEAK PULL-UP PORTB REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 U-0 U-0 U-0 U-0 WPUB7 WPUB6 WPUB5 WPUB4 -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 WPUB<7:4>: Weak Pull-up Register bits 1 = Pull-up enabled 0 = Pull-up disabled bit 3-0 Unimplemented: Read as `0' Note 1: 2: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled. The weak pull-up device is automatically disabled if the pin is configured as an output. REGISTER 5-8: INLVLB: PORTB INPUT LEVEL CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 INLVLB7 INLVLB6 INLVLB5 INLVLB4 -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 INLVLB<7:4>: PORTB Input Level Select bits For RB<7:4> pins, respectively 1 = ST input used for PORT reads and Interrupt-on-Change 0 = TTL input used for PORT reads and Interrupt-on-Change bit 3-0 Unimplemented: Read as `0' TABLE 5-1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELB ANSB74 ANSB6 ANSB5 ANSB4 -- -- -- -- 42 INLVLB INLVLB7 INLVLB6 INLVLB5 INLVLB4 -- -- -- -- 43 LATB7 LATB6 LATB5 LATB4 -- -- -- -- 42 Name LATB PORTB LINTX LINCS LINRX RB4 -- -- -- -- 41 TRISB TRISB7 TRISB6 TRISB5 TRISB4 -- -- -- -- 41 WPUB7 WPUB6 WPUB5 WPUB4 -- -- -- -- 43 WPUB Legend: x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTB. 2012 Microchip Technology Inc. Preliminary DS41673A-page 43 PIC16F1829LIN 5.3 PORTC Registers 5.3.2 PORTC is an 8-bit wide, bidirectional port. It functions the same as described in the "PIC16(L)F1825/1829 Data Sheet" (DS41440) with the following differences: * One bit is dedicated to the LIN transceiver and one bit is not available. No pins are associated with this function. Only RC<5:0> are available on pins. The corresponding data direction register is TRISC. The TRISC bits must be set as `1xxx xxxx'. * The PORTC Data Latch register (LATC) is also memory mapped. Read-modify-write operations on the LATC register read and write the latched output value for PORTC. Note: On a Power-on Reset, RC<7:6> and RC<3:0> are configured as analog inputs and read as `0'. EXAMPLE 5-2: banksel PORTC CLRF PORTC banksel LATC CLRF LATC banksel TRISC MOVLW 0FFh 5.3.1 PORTC FUNCTIONS AND OUTPUT PRIORITIES Each PORTC pin is multiplexed with other functions. The pins, their combined functions and their output priorities are briefly described here. For additional information, please refer to Table 1-1 and Table 1-2. When multiple outputs are enabled, the actual pin control goes to the peripheral with the lowest number in the following lists. Analog input and some digital input functions are not included in the list below (see Table 5-2). These input functions can remain active when the pin is configured as an output. Certain digital input functions override other port functions and are included in the priority list. TABLE 5-2: Pin Name INITIALIZING PORTC ; Initialize PORTC by ; clearing output ; data latches ; Alternate method ; to clear output ; data latches P1D(2) RC1 P1C(2) RC2 P1D(2) P2B(2) RC3 CCP2(2) P1C(2) P2A(2) RC4 MDOUT SRNQ C2OUT P1B The ANSELC register (Register 5-12) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELC bit high will cause all digital reads on the pin to be read as `0' and allow analog functions on the pin to operate correctly. CCP1/P1A RC6(3) Not available RC7(3) PWRGD Note 1: 2: ANSELC REGISTER Function Priority(1) RC0 RC5 ; Value used to ; initialize data ; direction PORTC OUTPUT PRIORITY 3: Priority listed from highest to lowest. Pin function is selectable via the APFCON0 or APFCON1 register. RC6 is not available to a pin. RC7 is internally connected to the PWRGD signal from the LIN transceiver. The state of the ANSELC bits has no effect on digital output functions. A pin with TRIS clear and ANSELC set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing READ-MODIFY-WRITE instructions on the affected port. Note: The ANSELC bits default to the Analog mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to `0' by user software. DS41673A-page 44 Preliminary 2012 Microchip Technology Inc. PIC16F1829LIN REGISTER 5-9: PORTC: PORTC REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u PWRGD -- RC5 RC4 RC3 RC2 RC1 RC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 PWRGD: Power Good Signal from Voltage Regulator 1 = Voltage Regulator is stable and within operating limits 0 = Voltage Regulator is not stable bit 6 No Function bit 5-0 RC<5:0>: PORTC General Purpose I/O Pin bits 1 = Port pin is > VIH 0 = Port pin is < VIL REGISTER 5-10: TRISC: PORTC TRI-STATE REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 TRISC7 -- TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 TRISC7: PORTC Tri-State Control bit 1 = PORTC pin configured as PWRGD input (tri-stated) 0 = Do not use to avoid internal contention bit 6 Don't Care bit 5-0 TRISC<5:0>: PORTC Tri-State Control bits 1 = PORTC pin configured as an input (tri-stated) 0 = PORTC pin configured as an output 2012 Microchip Technology Inc. Preliminary DS41673A-page 45 PIC16F1829LIN REGISTER 5-11: LATC: PORTC DATA LATCH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u PWRGD -- LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 PWRGD: Configured as an Input Value; Don't Care bit 6 Don't Care bit 5-0 LATC<7:0>: PORTC Output Latch Value bits(1) Note 1: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is return of actual I/O pin values. REGISTER 5-12: ANSELC: PORTC ANALOG SELECT REGISTER R/W-1/1 R/W-1/1 U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 ANSC7 -- -- -- ANSC3 ANSC2 ANSC1 ANSC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 ANSC7: Analog Select between Analog or Digital Function on Pin RC7 0 = Set for PWRGD input 1 = Do not use bit 6-4 Unimplemented: Read as `0' bit 3-0 ANSC<3:0>: Analog Select between Analog or Digital Function on Pins RC<3:0> 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. DS41673A-page 46 Preliminary 2012 Microchip Technology Inc. PIC16F1829LIN REGISTER 5-13: WPUC: WEAK PULL-UP PORTC REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 WPUC7 WPUC6 WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared WPUC<7:0>: Weak Pull-up Register bits(1, 2) 1 = Pull-up enabled 0 = Pull-up disabled bit 7-0 Note 1: 2: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled. The weak pull-up device is automatically disabled if the pin is configured as an output. REGISTER 5-14: INLVLC: PORTC INPUT LEVEL CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-1/1 R/W-0/0 R/W-0/0 INLVLC7 INLVLC6 INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 TABLE 5-3: Name ANSELC INLVLC<7:0>: PORTC Input Level Select bits For RC<7:0> pins: 1 = ST input used for port reads and Interrupt-on-change 0 = TTL input used for port reads and Interrupt-on-change SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSC7 -- -- -- ANSC3 ANSC2 ANSC1 ANSC0 46 INLVLC INLVLC7 INLVLC6 INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 47 LATC PWRGD -- LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 46 PORTC PWRGD -- RC5 RC4 RC3 RC2 RC1 RC0 45 TRISC TRISC7 -- TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 45 WPUC WPUC7 WPUC6 WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 47 Legend: x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTC. 2012 Microchip Technology Inc. Preliminary DS41673A-page 47 PIC16F1829LIN 6.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. It functions the same as described in the "PIC16(L)F1825/1829 Data Sheet" (DS41440) with the differences shown in Figure 6-1. FIGURE 6-1: ADC BLOCK DIAGRAM ADNREF = 1 VREF- ADNREF = 0 VDD VSS ADPREF = 00 ADPREF = 11 VREF+ AN0 00000 AN1 00001 AN2 00010 AN3 00011 AN4 00100 AN5 00101 AN6 00110 AN7 00111 Reserved 01000 Reserved 01001 AN10 01010 Reserved 01011 ADPREF = 10 ADC 10 GO/DONE ADFM 0 = Left Justify 1 = Right Justify ADON(1) Temp Indicator 11101 DAC 11110 FVR Buffer1 11111 16 VSS ADRESH ADRESL CHS<4:0> Note 1: DS41673A-page 48 When ADON = 0, all multiplexer inputs are disconnected. Preliminary 2012 Microchip Technology Inc. PIC16F1829LIN 6.1 ADC Register Definitions The following registers are used to control the operation of the ADC. Register Definitions: ADC Control REGISTER 6-1: U-0 ADCON0: A/D CONTROL REGISTER 0 R/W-0/0 R/W-0/0 -- R/W-0/0 R/W-0/0 CHS<4:0> R/W-0/0 R/W-0/0 R/W-0/0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 Unimplemented: Read as `0' bit 6-2 CHS<4:0>: Analog Channel Select bits 00000 = AN0 00001 = AN1 00010 = AN2 00011 = AN3 00100 = AN4 00101 = AN5 00110 = AN6 00111 = AN7 01000 = Reserved 01001 = Reserved 01010 = AN10 01011 = Reserved 01100 = Reserved. No channel connected. * * * 11100 = Reserved. No channel connected. 11101 = Temperature Indicator(3) 11110 = DAC output(1) 11111 = FVR (Fixed Voltage Reference) Buffer 1 Output(2) bit 1 GO/DONE: A/D Conversion Status bit 1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. This bit is automatically cleared by hardware when the A/D conversion has completed. 0 = A/D conversion completed/not in progress bit 0 ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current Note 1: 2: 3: See Section 17.0 "Digital-to-Analog Converter (DAC) Module" of the "PIC16(L)F1825/1829 Data Sheet" (DS41440) for more information. See Section 14.0 "Fixed Voltage Reference (FVR)" of the "PIC16(L)F1825/1829 Data Sheet" (DS41440) for more information. See Section 15.0 "Temperature Indicator Module" of the "PIC16(L)F1825/1829 Data Sheet" (DS41440) for more information. 2012 Microchip Technology Inc. Preliminary DS41673A-page 49 PIC16F1829LIN TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH ADC Name Bit 7 ADCON0 ADCON1 Bit 6 Bit 5 -- Bit 3 Bit 2 CHS<4:0> ADFM ADCS<2:0> ADRESH A/D Result Register High ADRESL A/D Result Register Low ANSELA Bit 4 -- ADNREF Bit 1 Bit 0 Register on Page GO/DONE ADON 49 ADPREF<1:0> -- -- -- -- -- -- ANSA4 -- ANSA2 ANSA1 ANSA0 -- ANSELB(1) ANSB7 ANSB6 ANSB5 ANSB4 -- -- -- -- 42 ANSELC ANSC7 -- -- -- ANSC3 ANSC2 ANSC1 ANSC0 46 P4M1 P4M0 DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 -- CCP4CON INLVLA -- -- INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 -- INLVLB7 INLVLB6 INLVLB5 INLVLB4 -- -- -- -- 43 INLVLC INLVLC7(1) INLVLC6(1) INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 47 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF -- PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE -- PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF -- INLVLB(1) TRISA -- -- TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 -- TRISB7 TRISB6 TRISB5 TRISB4 -- -- -- -- 41 TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 45 FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> DACCON0 DACEN DACLPS DACOE -- DACPSS<1:0> DACCON1 -- -- -- TRISB(1) TRISC Legend: Note 1: DACR<4:0> ADFVR<1:0> -- DACNSS -- -- -- x = unknown, u = unchanged, -- = unimplemented read as `0', q = value depends on condition. Shaded cells are not used for ADC module. TRISC6 is not used as the signal does not come out to a pin. TRISC7 must be set to `1'. TRISB bits should be set as described in Register 5-4. DS41673A-page 50 Preliminary 2012 Microchip Technology Inc. PIC16F1829LIN 7.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP1 AND MSSP2) MODULE 7.1 Master SSPx (MSSPx) Module Overview The Master Synchronous Serial Port (MSSPx) module is not to be used as its operation conflicts with LIN pin functions. TABLE 7-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH MSSP OPERATION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELA -- -- -- ANSA4 -- ANSA2 ANSA1 ANSA0 -- ANSELB ANSB7 ANSB6 ANSB5 ANSB4 -- -- -- -- 42 ANSELC ANSC7 -- -- -- ANSC3 ANSC2 ANSC1 ANSC0 46 APFCON0 RXDTSEL -- -- -- T1GSEL TXCKSEL -- -- 38 APFCON1 -- -- -- -- P1DSEL P1CSEL P2BSEL CCP2SEL 39 INLVLA -- -- INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 -- INLVLB INLVLB7 INLVLB6 INLVLB5 INLVLB4 -- -- -- -- 43 INLVLC INLVLC7 INLVLC6 INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 47 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF -- PIE1 INTCON TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE -- PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF SSP1BUF Don't care -- -- SSP1CON1 0 0 0 0 0 0 0 0 -- SSP1CON3 0 0 0 0 0 0 0 0 -- SSP1STAT 0 0 0 0 0 0 0 0 -- TRISA -- -- TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 -- TRISB TRISB7 TRISB6 TRISB5 TRISB4 -- -- -- -- 41 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 45 Legend: -- = Unimplemented location, read as `0'. Shaded cells are not used by the MSSP1 in SPI mode. 2012 Microchip Technology Inc. Preliminary DS41673A-page 51 PIC16F1829LIN 8.0 ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) 8.1 1. The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is a serial I/O communications peripheral. It functions the same as described in the "PIC16(L)F1825/1829 Data Sheet" (DS41440) with the following differences: 2. 3. * The 9-bit character length and Address detection should not be used. * Programmable clock and data polarity should not be used. 4. 5. 6. 7. 8. TABLE 8-1: Asynchronous Transmission Setup Initialize the SPBRGH, SPBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 26.3, EUSART Baud Rate Generator (BRG) in the "PIC16(L)F1825/1829 Data Sheet" (DS41440)). Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. TX9 control bit should always be `0' for LIN transmission. Set the SCKP bit if inverted transmit is desired. Enable the transmission by setting the TXEN control bit. This will cause the TXIF interrupt bit to be set. If interrupts are desired, set the TXIE interrupt enable bit of the PIE1 register. An interrupt will occur immediately, provided that the GIE and PEIE bits of the INTCON register are also set. If 9-bit transmission is selected, the ninth bit should be loaded into the TX9D data bit. Load 8-bit data into the TXREG register. This will start the transmission. SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Name Bit 7 Bit 6 Bit 5 Bit 4 APFCON0 RXDTSEL -- -- -- BAUDCON ABDOVF RCIDL -- SCKP -- -- INLVLA Bit 3 BRG16 INLVLA5 INLVLA4 INLVLA3 INLVLB7 INLVLB6 INLVLB5 INLVLB4 INLVLC INLVLC7 INLVLC6 INLVLC5 INLVLC4 INLVLC3 INTCON GIE PEIE TMR0IE INTE PIE1 TMR1GIE ADIE RCIE PIR1 TMR1GIF ADIF RCIF SPEN RX9 SREN SPBRGL Bit 0 Register on Page -- -- 38 -- WUE ABDEN 56 INLVLA2 INLVLA1 INLVLA0 -- T1GSEL TXCKSEL INLVLB RCSTA Bit 1 Bit 2 -- -- -- -- 43 INLVLC2 INLVLC1 INLVLC0 47 IOCIE TMR0IF INTF IOCIF -- TXIE SSP1IE CCP1IE TMR2IE TMR1IE -- TXIF SSP1IF CCP1IF TMR2IF TMR1IF -- CREN ADDEN FERR OERR RX9D 55 BRG<7:0> SPBRGH 52* BRG<15:8> 52* TRISA -- -- TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 -- TRISB TRISB7 TRISB6 TRISB5 TRISB4 -- -- -- -- 41 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 45 TXREG TXSTA EUSART Transmit Data Register CSRC TX9 TXEN 52* SYNC SENDB BRGH TRMT TX9D 54 Legend: -- = unimplemented location, read as `0'. Shaded cells are not used for Asynchronous Transmission. * Page provides register information. DS41673A-page 52 Preliminary 2012 Microchip Technology Inc. PIC16F1829LIN 8.2 1. 2. 3. 4. 5. Asynchronous Reception Setup 6. 7. Enable reception by setting the CREN bit. The RCIF interrupt flag bit will be set when a character is transferred from the RSR to the receive buffer. An interrupt will be generated if the RCIE interrupt enable bit was also set. 8. Read the RCSTA register to get the error flags and, if 9-bit data reception is enabled, the ninth data bit. 9. Get the received eight Least Significant data bits from the receive buffer by reading the RCREG register. 10. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. Initialize the SPBRGH, SPBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 26.3, EUSART Baud Rate Generator (BRG) in the "PIC16(L)F1825/1829 Data Sheet" (DS41440)). Clear the ANSEL bit for the RX pin (if applicable). Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. If 9-bit reception is desired, set the RX9 bit. TABLE 8-2: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page APFCON0 RXDTSEL -- -- -- T1GSEL TXCKSEL -- -- 38 BAUDCON ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 56 Name INLVLA -- -- INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 -- INLVLB INLVLB7 INLVLB6 INLVLB5 INLVLB4 -- -- -- -- 43 INLVLC INLVLC7 INLVLC6 INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 47 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF -- PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE -- PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF RCREG RCSTA EUSART Receive Data Register SPEN RX9 SREN CREN ADDEN -- 53* FERR OERR RX9D 55 SPBRGL BRG<7:0> 52, 53* SPBRGH BRG<15:8> 52, 53* TRISA -- -- TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 -- TRISB TRISB7 TRISB6 TRISB5 TRISB4 -- -- -- -- 41 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 45 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 54 Legend: * -- = unimplemented location, read as `0'. Shaded cells are not used for Asynchronous Reception. Page provides register information. 2012 Microchip Technology Inc. Preliminary DS41673A-page 53 PIC16F1829LIN REGISTER 8-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-1/1 R/W-0/0 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 CSRC: Must be `0' bit 6 TX9: Must be `0' bit 5 TXEN: Transmit Enable bit 1 = Transmit enabled 0 = Transmit disabled bit 4 SYNC: Must be `0' bit 3 SENDB: Send BREAK Character bit 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed bit 2 BRGH: High Baud Rate Select bit 1 = High speed 0 = Low speed bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: Must be `0' DS41673A-page 54 Preliminary 2012 Microchip Technology Inc. PIC16F1829LIN REGISTER 8-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-x/x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) bit 6 RX9: Must be `0' bit 5 SREN: Don't Care bit 4 CREN: Continuous Receive Enable bit 1 = Enables receiver 0 = Disables receiver bit 3 ADDEN: Must be `0' bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receive next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: Must be `0' 2012 Microchip Technology Inc. Preliminary DS41673A-page 55 PIC16F1829LIN REGISTER 8-3: BAUDCON: BAUD RATE CONTROL REGISTER R-0/0 R-1/1 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto-baud timer did not overflow Synchronous mode: Don't care bit 6 RCIDL: Receive Idle Flag bit Asynchronous mode: 1 = Receiver is Idle 0 = Start bit has been received and the receiver is receiving Synchronous mode: Don't care bit 5 Unimplemented: Read as `0' bit 4 SCKP: Must be `0' bit 3 BRG16: 16-bit Baud Rate Generator bit 1 = 16-bit Baud Rate Generator is used 0 = 8-bit Baud Rate Generator is used bit 2 Unimplemented: Read as `0' bit 1 WUE: Wake-up Enable bit 1 = Receiver is waiting for a falling edge. No character will be received, byte RCIF will be set. WUE will automatically clear after RCIF is set. 0 = Receiver is operating normally bit 0 ABDEN: Auto-Baud Detect Enable bit 1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete) 0 = Auto-Baud Detect mode is disabled DS41673A-page 56 Preliminary 2012 Microchip Technology Inc. PIC16F1829LIN 9.0 CONSIDERATION OF SPLIT POWER SUPPLIES AND DURING DEBUG When the microcontroller is powered by a source other than the LIN Voltage Regulator, the following should be observed. This also applies when debugging and power the microcontroller from the emulator. Leaving RB7/TX or RB6/LINCS outputs in a high state (`1') will source current into the internal voltage regulator and prevent the RESET circuit from detecting a Power-on-event. Always drive RB7/TX low when putting the transceiver into Power-Down mode by controlling RB6/CS = 0. If the microcontroller is supplied by the debugging tool, be aware that the VBAT must be applied to the VBAT pin for the transceiver to operate. 2012 Microchip Technology Inc. Preliminary DS41673A-page 57 PIC16F1829LIN 10.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings() Ambient temperature under bias.............................................................................................................-40C to +125C Storage temperature............................................................................................................................... -65C to +150C Voltage on VDD with respect to VSS.......................................................................................................... -0.3V to +6.5V Voltage on MCLR with respect to Vss.......................................................................................................-0.3V to +9.0V Voltage on all other logic level pins with respect to VSS..................................................................-0.3V to (VDD + 0.3V) Total power dissipation (Note 5)...........................................................................................................................800 mW Maximum current out of VSS pin, -40C TA +125C for extended..................................................................... 35 mA Maximum current into VDD pin, -40C TA +125C for extended........................................................................ 30 mA Clamp current, IK (VPIN < 0 or VPIN > VDD)..........................................................................................................20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin.....................................................................................................25 mA VBB Battery Voltage, non-operating (LIN bus recessive, no regulator load, t < 60s)..................................... -0.3 to +43V VBB Battery Voltage, transient ISO 7637 Test 1 ..................................................................................................... -200V VBB Battery Voltage, transient ISO 7637 Test 2a ...................................................................................................+150V VBB Battery Voltage, transient ISO 7637 Test 3a ................................................................................................... -300V VBB Battery Voltage, transient ISO 7637 Test 3b ...................................................................................................+200V VBB Battery Voltage, continuous ................................................................................................................... -0.3 to +30V VLBUS Bus Voltage, continuous ...................................................................................................................... -18 to +30V VLBUS Bus Voltage, transient (Note 1) ........................................................................................................... -27 to +43V ILBUS Bus Short Circuit Current Limit ....................................................................................................................200 mA ESD protection on LIN, VBB (IEC 61000-4-2, 330 Ohm, 150 pF) (Note 3) .............................................. Minimum 9 kV ESD protection on LIN, VBB (Charge Device Model) (Note 2) ..............................................................................1500V ESD protection on LIN, VBB (Human Body Model, 1 kOhm, 100 pF) (Note 4) .......................................................8 kV ESD protection on LIN, VBB (Machine Model) (Note 2) ..........................................................................................800V ESD protection on all other pins (Human Body Model) (Note 2) ............................................................................> 4 kV Maximum Junction Temperature ............................................................................................................................. 150C Storage Temperature...................................................................................................................................-55 to +150C Note 1: ISO 7637/1 load dump compliant (t < 500 ms). 2: According to JESD22-A114-B. 3: According to IBEE, without bus filter. 4: Limited by Test Equipment. 5: Power dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOl x IOL). NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. DS41673A-page 58 Preliminary 2012 Microchip Technology Inc. PIC16F1829LIN PIC16F1829LIN VOLTAGE FREQUENCY GRAPH, -40C TA +125C FIGURE 10-1: VDD (V) 5.5 2.5 2.3 0 4 10 16 32 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency of the microcontroller only. When powered by the internal voltage regulator, the microcontroller is operated only in the 4.5-5.5V range. 2: Refer to Table 30-1 in the "PIC16(L)F1825/1829 Data Sheet" (DS41440) for each Oscillator mode's supported frequen- HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE FIGURE 10-2: 125 5% Temperature (C) 85 3% 60 2% 25 0 -20 -40 1.8 5% 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) 2012 Microchip Technology Inc. Preliminary DS41673A-page 59 PIC16F1829LIN 10.1 DC Characteristics: PIC16F1829LIN-E (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C for extended PIC16F1829LIN Param. No. Sym. Characteristic Min. Typ Max. Units 2.3 -- 5.5 V Conditions Supply Voltage D001 VDD PIC16F1829LIN FOSC 32 MHz (Note 1) * Note These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 1: PLL required for 32 MHz operation. 10.2 DC Characteristics: PIC16F1829LIN-E (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C for extended PIC16F1829LIN Param. No. Symbol Device Characteristics Min. Typ Max. Units Conditions VDD Note Current for Transceiver and Voltage Regulator(1) TBD IBBQ VBB Quiescent Operating Current -- 115 210 A 5.0 IOUT = 0 mA, LBUS recessive TBD IBBTO VBB Transmitter-off Current -- 90 190 A 5.0 With VREG on, transmitter off, receiver on, FAULT/TXE = VIL, CS = VIH TBD IBBPD VBB Power-down Current -- 16 26 A 5.0 With VREG powered-off, receiver on and transmitter off, FAULT/TXE = VIH, TXD = VIH, CS = VIL) TBD IBBNO-GND VBB Current with VSS Floating -1 -- 1 mA 5.0 VBB = 12V, GND to VBB, VLIN = 0-18V -- 5.5 15 A 1.8 -- 7.8 18 A 3.0 FOSC = 32 kHz LP Oscillator -- 20 55 A 1.8 -- 25 60 A 3.0 -- 27 65 A 5.0 Supply Current (IDD)(2, 3) D010 D010 * FOSC = 32 kHz LP Oscillator These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. TBD = To be determined Note 1: 2: 3: 4: 5: 6: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Maximum values should be used when calculating total current consumption. The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 8 MHz internal RC oscillator with 4x PLL enabled. 8 MHz crystal oscillator with 4x PLL enabled. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k. DS41673A-page 60 Preliminary 2012 Microchip Technology Inc. PIC16F1829LIN 10.2 DC Characteristics: PIC16F1829LIN-E (Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C for extended PIC16F1829LIN Param. No. Device Characteristics Min. Conditions Typ Max. Units -- 83 140 A 1.8 -- 130 230 A 3.0 -- 105 160 A 1.8 -- 160 250 A 3.0 -- 230 320 A 5.0 D012 -- 220 310 A 1.8 -- 378 540 A 3.0 D012 -- 240 300 A 1.8 -- 400 500 A 3.0 -- 500 760 A 5.0 -- 46 160 A 1.8 -- 90 230 A 3.0 -- 70 180 A 1.8 -- 120 240 A 3.0 -- 190 320 A 5.0 Symbol VDD Note Supply Current (IDD)(2, 3) D011 D011 D013 D013 * FOSC = 1 MHz XT Oscillator FOSC = 1 MHz XT Oscillator FOSC = 4 MHz XT Oscillator FOSC = 4 MHz XT Oscillator FOSC = 1 MHz EC Oscillator Medium-Power mode FOSC = 1 MHz EC Oscillator Medium-Power mode These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. TBD = To be determined Note 1: 2: 3: 4: 5: 6: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Maximum values should be used when calculating total current consumption. The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 8 MHz internal RC oscillator with 4x PLL enabled. 8 MHz crystal oscillator with 4x PLL enabled. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k. 2012 Microchip Technology Inc. Preliminary DS41673A-page 61 PIC16F1829LIN 10.2 DC Characteristics: PIC16F1829LIN-E (Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C for extended PIC16F1829LIN Param. No. Symbol Device Characteristics Conditions Min. Typ Max. Units -- 192 250 A 1.8 -- 336 430 A 3.0 -- 210 275 A 1.8 -- 356 450 A 3.0 -- 430 650 A 5.0 -- 6.5 18 A 1.8 -- 9.0 20 A 3.0 -- 20 60 A 1.8 -- 25 65 A 3.0 VDD Note Supply Current (IDD)(2, 3) D014 D014 D015 D015 D016 D016 D017* D017* D018 D018 * -- 27 70 A 5.0 -- 110 170 A 1.8 -- 130 200 A 3.0 -- 125 180 A 1.8 -- 155 250 A 3.0 -- 160 280 A 5.0 -- 0.6 0.85 mA 1.8 -- 0.9 1.25 mA 3.0 -- 0.6 0.85 mA 1.8 -- 0.96 1.35 mA 3.0 -- 1.03 1.55 mA 5.0 -- 0.9 1.2 mA 1.8 -- 1.4 1.95 mA 3.0 -- 0.92 1.2 mA 1.8 -- 1.49 1.9 mA 3.0 -- 1.58 2.4 mA 5.0 FOSC = 4 MHz EC Oscillator Medium-Power mode FOSC = 4 MHz EC Oscillator Medium-Power mode FOSC = 31 kHz LFINTOSC FOSC = 31 kHz LFINTOSC FOSC = 500 kHz MFINTOSC FOSC = 500 kHz MFINTOSC FOSC = 8 MHz HFINTOSC FOSC = 8 MHz HFINTOSC FOSC = 16 MHz HFINTOSC FOSC = 16 MHz HFINTOSC These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. TBD = To be determined Note 1: 2: 3: 4: 5: 6: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Maximum values should be used when calculating total current consumption. The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 8 MHz internal RC oscillator with 4x PLL enabled. 8 MHz crystal oscillator with 4x PLL enabled. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k. DS41673A-page 62 Preliminary 2012 Microchip Technology Inc. PIC16F1829LIN 10.2 DC Characteristics: PIC16F1829LIN-E (Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C for extended PIC16F1829LIN Param. No. Symbol Device Characteristics Conditions Min. Typ Max. Units -- 2.8 3.6 mA 3.0 -- 3.4 3.9 mA 3.6 -- 2.8 4.0 mA 3.0 -- 3.0 4.5 mA 5.0 -- 2.7 3.6 mA 3.0 -- 3.2 4.2 mA 3.6 -- 2.7 4.0 mA 3.0 -- 3.2 4.3 mA 5.0 -- 222 350 A 1.8 -- 400 690 A 3.0 -- 240 500 A 1.8 -- 416 800 A 3.0 -- 497 900 A 5.0 VDD Note Supply Current (IDD)(2, 3) D019 D019 D020 D020 D021 D021 * FOSC = 32 MHz HFINTOSC (Note 4) FOSC = 32 MHz HFINTOSC (Note 4) FOSC = 32 MHz HS Oscillator (Note 5) FOSC = 32 MHz HS Oscillator (Note 5) FOSC = 4 MHz EXTRC (Note 6) FOSC = 4 MHz EXTRC (Note 6) These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. TBD = To be determined Note 1: 2: 3: 4: 5: 6: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Maximum values should be used when calculating total current consumption. The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 8 MHz internal RC oscillator with 4x PLL enabled. 8 MHz crystal oscillator with 4x PLL enabled. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k. 2012 Microchip Technology Inc. Preliminary DS41673A-page 63 PIC16F1829LIN 11.0 PACKAGING INFORMATION 11.1 Package Marking Information 20-Lead SSOP (5.30 mm) Example PIC16F 1829LIN 1243017 Legend: XX...X Y YY WW NNN e3 * Note: * Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Standard PIC(R) device marking consists of Microchip part number, year code, week code, and traceability code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. DS41673A-page 64 Preliminary 2012 Microchip Technology Inc. PIC16F1829LIN 11.2 Package Details The following sections give the technical details of the packages. /HDG3ODVWLF6KULQN6PDOO2XWOLQH 66 PP%RG\>6623@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ D N E E1 NOTE 1 1 2 e b c A2 A A1 L1 8QLWV 'LPHQVLRQ/LPLWV 1XPEHURI3LQV L 0,//,0(7(56 0,1 1 120 0$; 3LWFK H 2YHUDOO+HLJKW $ %6& 0ROGHG3DFNDJH7KLFNQHVV $ 6WDQGRII $ 2YHUDOO:LGWK ( 0ROGHG3DFNDJH:LGWK ( 2YHUDOO/HQJWK ' )RRW/HQJWK / )RRWSULQW / 5() /HDG7KLFNQHVV F )RRW$QJOH /HDG:LGWK E 1RWHV 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD 'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0 %6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV 5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &% 2012 Microchip Technology Inc. Preliminary DS41673A-page 65 PIC16F1829LIN Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41673A-page 66 Preliminary 2012 Microchip Technology Inc. PIC16F1829LIN APPENDIX A: DATA SHEET REVISION HISTORY Revision A (12/2012) Initial release. 2012 Microchip Technology Inc. Preliminary DS41673A-page 67 PIC16F1829LIN INDEX A Absolute Maximum Ratings ................................................ 55 ADC..................................................................................... 45 Associated Registers .................................................. 47 Block Diagram............................................................. 45 ADCON0 Register......................................................... 25, 46 ADCON1 Register............................................................... 25 ADRESH Register............................................................... 25 Alternate Pin Function......................................................... 35 Analog Features.................................................................... 1 Analog-to-Digital Converter. See ADC ANSELB Register................................................................ 39 ANSELC Register ............................................................... 43 APFCON0 Register............................................................. 35 APFCON1 Register............................................................. 36 Asynchronous Reception Setup.......................................... 50 Asynchronous Transmission Setup..................................... 49 B BAUDCON Register............................................................ 53 Block Diagrams ADC ............................................................................ 45 PIC16F1829LIN ...................................................... 7, 17 C CCP1CON Register ...................................................... 29, 30 CCPR1H Register ......................................................... 29, 30 CCPR1L Register.......................................................... 29, 30 Code Examples Initializing PORTB ....................................................... 37 Initializing PORTC....................................................... 41 Cross-Referenced Material ................................................... 1 Customer Change Notification Service ............................... 67 Customer Notification Service............................................. 67 Customer Support ............................................................... 67 D DC Characteristics Extended ..................................................................... 57 Device Overview ................................................................... 6 E Electrical Specifications ...................................................... 55 Enhanced Mid-range CPU .................................................. 17 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)................................. 49 Errata .................................................................................... 5 EUSART.............................................................................. 49 Asynchronous Mode Associated Registers Receive ....................................................... 50 Transmit ...................................................... 49 F Flexible Oscillator Structure .................................................. 1 FSR Register........... 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34 H Hardware............................................................................. 11 High-Performance RISC CPU............................................... 1 I I/O Ports .............................................................................. 35 INDF Register ......... 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34 DS41673A-page 68 INLVLB Register ................................................................. 40 INLVLC Register................................................................. 44 Internet Address ................................................................. 67 L LATA Register .................................................................... 43 LATB Register .................................................................... 39 M Master SSPx (MSSPx) Module Overview........................... 48 Master Synchronous Serial Port. See MSSPx Memory Organization ......................................................... 18 Microchip Internet Web Site................................................ 67 MSSPx................................................................................ 48 P Packaging SSOP.......................................................................... 62 Packaging Information ........................................................ 61 PCL Register .......... 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34 PCLATH Register ... 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34 PCON Register ................................................................... 25 Peripheral Features .............................................................. 1 PIE1 Register...................................................................... 25 PIE2 Register...................................................................... 25 PIE3 Register...................................................................... 25 PIE4 Register...................................................................... 25 Pinout Descriptions PIC16F1829LIN ............................................................ 8 PIR1 Register ..................................................................... 24 PIR2 Register ..................................................................... 24 PIR3 Register ..................................................................... 24 PIR4 Register ..................................................................... 24 PORTA LATA Register ............................................................ 26 PORTA Register ......................................................... 24 PORTB ANSELB Register ....................................................... 37 Associated Registers .................................................. 40 LATB Register ............................................................ 26 PORTB Register ......................................................... 24 PORTB Register ................................................................. 38 PORTB Registers ............................................................... 37 PORTC ANSELC Register ....................................................... 41 Associated Registers .................................................. 44 LATC Register ............................................................ 26 PORTC Functions and Output Priorities..................... 41 PORTC Register......................................................... 24 PORTC Register................................................................. 42 PORTC Registers ............................................................... 41 PR2 Register ...................................................................... 24 PR4 Register ...................................................................... 32 PR6 Register ...................................................................... 32 R RCREG Register ................................................................ 27 RCSTA Register ........................................................... 27, 52 Reader Response............................................................... 68 Registers ADCON0 (ADC Control 0) .......................................... 46 ANSELB (PORTB Analog Select)............................... 39 ANSELC (PORTC Analog Select) .............................. 43 APFCON0 (Alternate Pin Function Control 0) ............ 35 Preliminary 2012 Microchip Technology Inc. PIC16F1829LIN APFCON1 (Alternate Pin Function Control 1)............. 36 BAUDCON (Baud Rate Control) ................................. 53 INLVLB (Input Level Control PORTB)......................... 40 INLVLC (Input Level Control PORTC) ........................ 44 LATB (Data Latch PORTB)......................................... 39 LATC (Data Latch PORTC) ........................................ 43 PORTB........................................................................ 38 PORTC ....................................................................... 42 RCSTA (Receive Status and Control)......................... 52 Special Function, Summary ........................................ 24 TRISB (Tri-State PORTB)........................................... 38 TRISC (Tri-State PORTC) .......................................... 42 TXSTA (Transmit Status and Control) ........................ 51 WPUB (Weak Pull-up PORTB) ................................... 40 WPUC (Weak Pull-up PORTC)................................... 44 Revision History .................................................................. 64 Routing CCP4 to a Pin ........................................................ 15 S Software .............................................................................. 12 SPBRG Register ................................................................. 27 Special Function Registers (SFRs) ..................................... 24 Special Microcontroller Features .......................................... 1 SPI Mode (MSSPx) Associated Registers .................................................. 48 SSP1ADD Register ............................................................. 28 SSP1BUF Register ............................................................. 28 SSP1CON Register ............................................................ 28 SSP1CON2 Register .......................................................... 28 SSP1CON3 Register .......................................................... 28 SSP1MSK Register............................................................. 28 SSP1STAT Register ........................................................... 28 SSP2ADD Register ............................................................. 28 SSP2BUF Register ............................................................. 28 SSP2CON Register ............................................................ 28 SSP2CON2 Register .......................................................... 28 SSP2CON3 Register .......................................................... 28 SSP2MSK Register............................................................. 28 SSP2STAT Register ........................................................... 28 T T1CON Register ................................................................. 24 T2CON Register ................................................................. 24 T4CON Register ................................................................. 32 T6CON Register ................................................................. 32 TMR0 Register .................................................................... 24 TMR1H Register ................................................................. 24 TMR1L Register .................................................................. 24 TMR2 Register .................................................................... 24 TMR4 Register .................................................................... 32 TMR6 Register .................................................................... 32 TRISA Register ................................................................... 25 TRISB Register ............................................................. 25, 38 TRISC Register ............................................................. 25, 42 TXREG Register ................................................................. 27 TXSTA Register ............................................................ 27, 51 U Using the PIC16F1829LIN in LIN Bus Applications ............ 11 W WPUB Register ................................................................... 40 WPUC Register................................................................... 44 WWW Address.................................................................... 67 WWW, On-Line Support ....................................................... 5 2012 Microchip Technology Inc. Preliminary DS41673A-page 69 PIC16F1829LIN THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: Users of Microchip products can receive assistance through several channels: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives * * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://microchip.com/support CUSTOMER CHANGE NOTIFICATION SERVICE Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under "Support", click on "Customer Change Notification" and follow the registration instructions. DS41673A-page 70 Preliminary 2012 Microchip Technology Inc. PIC16F1829LIN READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: Technical Publications Manager RE: Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC16F1829LIN Literature Number: DS41673A Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? 2012 Microchip Technology Inc. Preliminary DS41673A-page 71 PIC16F1829LIN PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. [X](1) PART NO. Device - X Tape and Reel Temperature Option Range /XX XXX Package Pattern Device: PIC16F1829LIN Tape and Reel Option: Blank T = Standard packaging (tube or tray) = Tape and Reel(1) Temperature Range: E = -40C to +125C Package:(2) SS Pattern: QTP, SQTP, Code or Special Requirements (blank otherwise) = Examples: a) PIC16F1829LIN - E/SS Extended temperature, SSOP package (Extended) SSOP Note 1: 2: DS41673A-page 72 Preliminary Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. For other small form-factor package availability and marking information, please visit www.microchip.com/packaging or contact your local sales office. 2012 Microchip Technology Inc. PIC16F1829LIN Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MTP, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. Analog-for-the-Digital Age, Application Maestro, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. & KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. (c) 2012, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 9781620768204 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2012 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. Preliminary DS41673A-page 73 Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.com Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Japan - Osaka Tel: 81-6-6152-7160 Fax: 81-6-6152-9310 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8569-7000 Fax: 86-10-8528-2104 Japan - Tokyo Tel: 81-3-6880- 3770 Fax: 81-3-6880-3771 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 China - Chongqing Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 China - Hangzhou Tel: 86-571-2819-3187 Fax: 86-571-2819-3189 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 China - Hong Kong SAR Tel: 852-2943-5100 Fax: 852-2401-3431 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 Taiwan - Hsin Chu Tel: 886-3-5778-366 Fax: 886-3-5770-955 China - Shenzhen Tel: 86-755-8864-2200 Fax: 86-755-8203-1760 Taiwan - Kaohsiung Tel: 886-7-213-7828 Fax: 886-7-330-9305 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 Taiwan - Taipei Tel: 886-2-2508-8600 Fax: 886-2-2508-0102 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 DS41673A-page 74 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 11/29/12 Preliminary 2012 Microchip Technology Inc.