December 2007 Rev 8 1/25
1
M41T56
Serial real-time clock with 56 bytes NVRAM
Features
■Counters for seconds, minutes, hours, day,
date, month, years, and century
■32KHz crystal oscillator integrating load
capacitance (12.5pF) providing exceptional
oscillator stability and high crystal series
resistance operation
■Serial interface supports I2C bus (100kHz
protocol)
■Ultra-low battery supply current of 450nA
(typ at 3V)
■5V ±10% supply voltage
■Timekeeping down to 2.5V
■Automatic power-fail detect and switch circuitry
■56 bytes of general purpose RAM
■Software clock calibration to compensate
crystal deviation due to temperature
■Automatic leap year compensation
■Operating temperature of –40°C to 85°C
■Available in an 8-lead, 150mil, plastic SOIC
(SO8)
■RoHS compliant
– Lead-free second level interconnect
8
1
SO8 (M) 150mil width
www.st.com
Contents M41T56
2/25
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.1 Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.2 Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.3 Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.4 Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.5 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 Write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 Output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3 Initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
M41T56 List of tables
3/25
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 6. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 7. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 8. Crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 9. Power down/up mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 10. Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 11. SO8 – 8-pin plastic small outline, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . 21
Table 12. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 13. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
List of figures M41T56
4/25
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. 8-pin SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. Acknowledge sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. Bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. Slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 8. Read mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 9. Alternative read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 10. Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 11. Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 12. Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 13. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 14. Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 15. SO8 – 8-pin plastic small package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
M41T56 Description
5/25
1 Description
The M41T56 is a low power, serial real-time clock with 56 bytes of NVRAM. A built-in
32,768Hz oscillator (external crystal controlled) and the first 8 bytes of the RAM are used for
the clock/calendar function and are configured in binary coded decimal (BCD) format.
Addresses and data are transferred serially via a two-line, bidirectional bus. The built-in
address register is incremented automatically after each WRITE or READ data byte.
The M41T56 clock has a built-in power sense circuit which detects power failures and
automatically switches to the battery supply during power failures. The energy needed to
sustain the RAM and clock operations can be supplied from a small lithium coin cell.
Typical data retention time is in excess of 10 years with a 50mAh, 3V lithium cell. The
M41T56 is supplied in an 8-lead plastic SOIC package.
Figure 1. Logic diagram
AI02304B
OSCI
VCC
M41T56
VSS
SCL
OSCO
SDA
FT/OUT
VBAT
Description M41T56
6/25
Figure 2. 8-pin SOIC connections
Figure 3. Block diagram
Table 1. Signal names
OSCI Oscillator input
OCSO Oscillator output
FT/OUT Frequency test / output driver (open drain)
SDA Serial data address input / output
SCL Serial clock
VBAT Battery supply voltage
VCC Supply voltage
VSS Ground
1
SDAVSS
SCL
FT/OUTOSCO
OSCI VCC
VBAT
AI02306B
M41T56
2
3
4
8
7
6
5
AI02566
SECONDS
OSCILLATOR
32.768 kHz
VOLTAGE
SENSE
and
SWITCH
CIRCUITRY
SERIAL
BUS
INTERFACE
DIVIDER
CONTROL
LOGIC
ADDRESS
REGISTER
MINUTES
CENTURY/HOURS
DAY
DATE
MONTH
YEAR
CONTROL
RAM
(56 x 8)
OSCI
OSCO
FT/OUT
VCC
VSS
VBAT
SCL
SDA
1 Hz
M41T56 Operation
7/25
2 Operation
The M41T56 clock operates as a slave device on the serial bus. Access is obtained by
implementing a start condition followed by the correct slave address (D0h). The 64 bytes
contained in the device can then be accessed sequentially in the following order:
1. Seconds register
2. Minutes register
3. Century/hours register
4. Day register
5. Date register
6. Month register
7. Years register
8. Control register
9. RAM
The clock continually monitors VCC for an out of tolerance condition. Should VCC fall below
VPFD, the device terminates an access in progress and resets the device address counter.
Inputs to the device will not be recognized at this time to prevent erroneous data from being
written to the device from an out of tolerance system. When VCC falls below VBAT
, the device
automatically switches over to the battery and powers down into an ultra low current mode
of operation to conserve battery life. Upon power-up, the device switches from battery to
VCC at VBAT and recognizes inputs when VCC goes above VPFD volts.
2.1 2-wire bus characteristics
This bus is intended for communication between different ICs. It consists of two lines: one
bidirectional for data signals (SDA) and one for clock signals (SCL). Both the SDA and the
SCL lines must be connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
●Data transfer may be initiated only when the bus is not busy.
●During data transfer, the data line must remain stable whenever the clock line is High.
●Changes in the data line while the clock line is High will be interpreted as control
signals.
Accordingly, the following bus conditions have been defined:
2.1.1 Bus not busy
Both data and clock lines remain High.
2.1.2 Start data transfer
A change in the state of the data line, from High to Low, while the clock is High, defines the
START condition.
Operation M41T56
8/25
2.1.3 Stop data transfer
A change in the state of the data line, from Low to High, while the clock is High, defines the
STOP condition.
2.1.4 Data valid
The state of the data line represents valid data when after a start condition, the data line is
stable for the duration of the High period of the clock signal. The data on the line may be
changed during the Low period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a start condition and terminated with a stop condition.
The number of data bytes transferred between the start and stop conditions is not limited.
The information is transmitted byte-wide and each receiver acknowledges with a ninth bit.
By definition, a device that gives out a message is called “transmitter,” the receiving device
that gets the message is called “receiver.” The device that controls the message is called
“master.” The devices that are controlled by the master are called “slaves.”
2.1.5 Acknowledge
Each byte of eight bits is followed by one Acknowledge Bit. This Acknowledge Bit is a low
level put on the bus by the receiver, whereas the master generates an extra acknowledge
related clock pulse.
A slave receiver which is addressed is obliged to generate an acknowledge after the
reception of each byte. Also, a master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the slave transmitter.
The device that acknowledges has to pull down the SDA line during the acknowledge clock
pulse in such a way that the SDA line is a stable Low during the High period of the
acknowledge related clock pulse. Of course, setup and hold times must be taken into
account. A master receiver must signal an end-of-data to the slave transmitter by not
generating an acknowledge on the last byte that has been clocked out of the slave. In this
case, the transmitter must leave the data line High to enable the master to generate the
STOP condition.
Figure 4. Serial bus data transfer sequence
AI00587
DATA
CLOCK
DATA LINE
STABLE
DATA VALID
START
CONDITION
CHANGE OF
DATA ALLOWED
STOP
CONDITION
M41T56 Operation
9/25
Figure 5. Acknowledge sequence
Figure 6. Bus timing requirements sequence
AI00601
DATA OUTPUT
BY RECEIVER
DATA OUTPUT
BY TRANSMITTER
SCLK FROM
MASTER
START
CLOCK PULSE FOR
ACKNOWLEDGEMENT
12 89
MSB LSB
AI00589
SDA
P
tSU:STOtSU:STA
tHD:STA
SR
SCL
tSU:DAT
tF
tHD:DAT
tR
tHIGH
tLOW
tHD:STAtBUF
SP
Operation M41T56
10/25
2.2 Read mode
In this mode, the master reads the M41T56 slave after setting the slave address (see
Figure 7 on page 11 and Figure 8 on page 11). Following the WRITE Mode Control Bit (R/W
= 0) and the Acknowledge Bit, the word address An is written to the on-chip address pointer.
Next the START condition and slave address are repeated, followed by the READ Mode
Control Bit (R/W = 1). At this point, the master transmitter becomes the master receiver. The
data byte which was addressed will be transmitted and the master receiver will send an
Acknowledge Bit to the slave transmitter. The address pointer is only incremented on
reception of an Acknowledge Bit. The M41T56 slave transmitter will now place the data byte
at address An + 1 on the bus. The master receiver reads and acknowledges the new byte
and the address pointer is incremented to An + 2. This cycle of reading consecutive
addresses will continue until the master receiver sends a STOP condition to the slave
transmitter.
An alternate READ mode may also be implemented, whereby the master reads the M41T56
slave without first writing to the (volatile) address pointer. The first address that is read is the
last one stored in the pointer, see Figure 9 on page 11.
Table 2. AC characteristics
Symbol Parameter(1)
1. Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 4.5 to 5.5V (except where noted).
Min Max Unit
fSCL SCL clock frequency 0 100 kHz
tLOW Clock low period 4.7 µs
tHIGH Clock high period 4 µs
tRSDA and SCL rise time 1 µs
tFSDA and SCL fall time 300 ns
tHD:STA
START condition hold time
(after this period the first clock pulse is generated) 4µs
tSU:STA
START condition setup time
(only relevant for a repeated start condition) 4.7 µs
tSU:DAT Data setup time 250 ns
tHD:DAT(2)
2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max.) of the falling
edge of SCL.
Data hold time 0 µs
tSU:STO STOP condition setup time 4.7 µs
tBUF
Time the bus must be free before a new
transmission can start 4.7 µs
M41T56 Operation
11/25
Figure 7. Slave address location
Figure 8. Read mode sequence
Figure 9. Alternative read mode sequence
AI00602
R/W
SLAVE ADDRESS
START A
0100011
MSB
LSB
AI00899
BUS ACTIVITY:
ACK
S
ACK
ACK
ACK
NO ACK STOP
START
P
SDA LINE
BUS ACTIVITY:
MASTER
R/W
DATA n DATA n+1
DATA n+X
WORD
ADDRESS (n)
SLAVE
ADDRESS
S
START
R/W
SLAVE
ADDRESS
ACK
AI00895
BUS ACTIVITY:
ACK
S
ACK
ACK
ACK
NO ACK STOP
START
PSDA LINE
BUS ACTIVITY:
MASTER
R/W
DATA n DATA n+1 DATA n+X
SLAVE
ADDRESS
Operation M41T56
12/25
2.3 Write mode
In this mode the master transmitter transmits to the M41T56 slave receiver. Bus protocol is
shown in Figure 10 on page 12. Following the START condition and slave address, a logic '0'
(R/W = 0) is placed on the bus and indicates to the addressed device that word address An
will follow and is to be written to the on-chip address pointer. The data word to be written to
the memory is strobed in next and the internal address pointer is incremented to the next
memory location within the RAM on the reception of an acknowledge clock. The M41T56
slave receiver will send an acknowledge clock to the master transmitter after it has received
the slave address and again after it has received the word address and each data byte (see
Figure 7 on page 11).
2.4 Data retention mode
With valid VCC applied, the M41T56 can be accessed as described above with READ or
WRITE cycles. Should the supply voltage decay, the M41T56 will automatically deselect,
write protecting itself when VCC falls between VPFD (max) and VPFD (min). This is
accomplished by internally inhibiting access to the clock registers and SRAM. When VCC
falls below the Battery Back-up Switchover Voltage (VSO), power input is switched from the
VCC pin to the battery and the clock registers and SRAM are maintained from the attached
battery supply.
All outputs become high impedance. On power up, when VCC returns to a nominal value,
write protection continues for tREC.
For a further more detailed review of battery lifetime calculations, please see Application
Note AN1012.
Figure 10. Write mode sequence
AI00591
BUS ACTIVITY:
ACK
S
ACK
ACK
ACK
ACK STOP
START
PSDA LINE
BUS ACTIVITY:
MASTER
R/W
DATA n DATA n+1 DATA n+X
WORD
ADDRESS (n)
SLAVE
ADDRESS
M41T56 Clock operation
13/25
3 Clock operation
The eight byte clock register (see Ta b l e 3 ) is used to both set the clock and to read the date
and time from the clock, in a binary coded decimal format. Seconds, Minutes, and Hours are
contained within the first three registers. Bits D6 and D7 of Clock Register 2 (Hours
Register) contain the CENTURY ENABLE Bit (CEB) and the CENTURY Bit (CB). Setting
CEB to a '1' will cause CB to toggle, either from '0' to '1' or from '1' to '0' at the turn of the
century (depending upon its initial state). If CEB is set to a '0,' CB will not toggle. Bits D0
through D2 of Register 3 contain the Day (day of week). Registers 4, 5, and 6 contain the
Date (day of month), Month, and Years. The final register is the Control Register (this is
described in the Clock Calibration section). Bit D7 of Register 0 contains the STOP Bit (ST).
Setting this bit to a '1' will cause the oscillator to stop.
If the device is expected to spend a significant amount of time on the shelf, the oscillator
may be stopped to reduce current drain. When reset to a '0' the oscillator restarts within one
second.
The seven Clock Registers may be read one byte at a time, or in a sequential block. The
Control Register (Address location 7) may be accessed independently. Provision has been
made to assure that a clock update does not occur while any of the seven clock addresses
are being read. If a clock address is being read, an update of the clock registers will be
delayed by 250ms to allow the READ to be completed before the update occurs. This will
prevent a transition of data during the READ.
Note: This 250ms delay affects only the clock register update and does not alter the actual clock
time.
Table 3. Register map(1)
1. Keys:
S = Sign bit
FT = Frequency test bit
ST = Stop bit
OUT = Output level
X = Don't care
CEB = Century enable bit
CB = Century bit
Address
Data Function/range
BCD format
D7 D6 D5 D4 D3 D2 D1 D0
0 ST 10 Seconds Seconds Seconds 00-59
1 X 10 Minutes Minutes Minutes 00-59
2CEB
(2)
2. When CEB is set to '1,' CB toggles from '0' to '1' or from '1' to '0' every 100 years (dependent upon the
initial value set). When CEB is set to '0,' CB does not toggle.
CB 10 hours Hours Century/hours 0-1/00-23
3XXXXX Day Day01-07
4 X X 10 date Date Date 01-31
5 X X X 10 M. Month Month 01-12
6 10 years Years Year 00-99
7 OUT FT S Calibration Control
Clock operation M41T56
14/25
3.1 Clock calibration
The M41T56 is driven by a quartz-controlled oscillator with a nominal frequency of
32,768Hz. The devices are tested not to exceed 35 ppm (parts per million) oscillator
frequency error at 25°C, which equates to about ±1.53 minutes per month. With the
calibration bits properly set, the accuracy of each M41T56 improves to better than ±2 ppm
at 25°C.
The oscillation rate of any crystal changes with temperature (see Figure 11 on page 15).
Most clock chips compensate for crystal frequency and temperature shift error with
cumbersome “trim” capacitors. The M41T56 design, however, employs periodic counter
correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit
at the divide by 256 stage, as shown in Figure 11 on page 15. The number of times pulses
are blanked (subtracted, negative calibration) or split (added, positive calibration) depends
upon the value loaded into the five-bit Calibration Byte found in the Control Register. Adding
counts speeds the clock up, subtracting counts slows the clock down.
The Calibration Byte occupies the five lower order bits (D4-D0) in the Control Register (Addr
7). This byte can be set to represent any value between 0 and 31 in binary form. Bit D5 is
the Sign Bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration
occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have
one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is
loaded into the register, only the first 2 minutes in the 64 minutes cycle will be modified; if a
binary 6 is loaded, the first 12 will be affected, and so on.
Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator
cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or –2.034 ppm of
adjustment per calibration step in the calibration register. Assuming that the oscillator is in
fact running at exactly 32,768Hz, each of the 31 increments in the Calibration Byte would
represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or –
2.75 minutes per month.
Two methods are available for ascertaining how much calibration a given M41T56 may
require. The first involves simply setting the clock, letting it run for a month and comparing it
to a known accurate reference (like WWV broadcasts). While that may seem crude, it allows
the designer to give the end user the ability to calibrate his clock as his environment may
require, even after the final product is packaged in a non-user serviceable enclosure. All the
designer has to do is provide a simple utility that accessed the Calibration Byte.
The second approach is better suited to a manufacturing environment, and involves the use
of some test equipment. When the Frequency Test (FT) Bit, the seventh-most significant bit
in the Control Register, is set to a '1,' and the oscillator is running at 32,768Hz, the FT/OUT
pin of the device will toggle at 512Hz. Any deviation from 512Hz indicates the degree and
direction of oscillator frequency shift at the test temperature.
For example, a reading of 512.01024Hz would indicate a +20ppm oscillator frequency error,
requiring a –10(XX001010) to be loaded into the Calibration Byte for correction.
Note: Setting or changing the calibration byte does not affect the frequency test output frequency.
M41T56 Clock operation
15/25
Figure 11. Crystal accuracy across temperature
Figure 12. Clock calibration
3.2 Output driver pin
When the FT Bit is not set, the FT/OUT pin becomes an output driver that reflects the
contents of D7 of the Control Register. In other words, when D6 of location 7 is a '0' and D7
of location 7 is a '0' and then the FT/OUT pin will be driven low.
Note: The FT/OUT pin is open drain which requires an external pull-up resistor.
3.3 Initial power-on defaults
Upon initial application of power to the device, the FT Bit will be set to a '0' and the OUT Bit
will be set to a '1.' All other Register bits will initially power-on in a random state.
AI00999b
–160
0 10203040506070
Frequency (ppm)
Temperature °C
80–10–20–30–40
–100
–120
–140
–40
–60
–80
20
0
–20
ΔF= K x (T –TO)2
K = –0.036 ppm/°C2 ± 0.006 ppm/°C2
TO = 25°C ± 5°C
F
AI00594B
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
Maximum rating M41T56
16/25
4 Maximum rating
Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Caution: Negative undershoots below –0.3V are not allowed on any pin while in the battery back-up
mode.
Table 4. Absolute maximum ratings
Symbol Parameter Value Unit
TAAmbient operating temperature –40 to 85 °C
TSTG Storage temperature (VCC off, oscillator off) –55 to 125 °C
TSLD(1)
1. For SO package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260°C (total thermal
budget not to exceed 245°C for greater than 30 seconds).
Lead solder temperature for 10 seconds 260 °C
VIO Input or output voltages –0.3 to 7 V
VCC Supply voltage –0.3 to 7 V
IOOutput current 20 mA
PDPower dissipation 0.25 W
M41T56 DC and AC parameters
17/25
5 DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC Characteristic
tables are derived from tests performed under the Measurement Conditions listed in Tabl e 5 :
Operating and AC measurement conditions. Designers should check that the operating
conditions in their projects match the measurement conditions when using the quoted
parameters.
Figure 13. AC measurement I/O waveform
Table 5. Operating and AC measurement conditions(1)
1. Output Hi-Z is defined as the point where data is no longer driven.
Parameter Value Unit
Supply voltage (VCC) 4.5 to 5.5 V
Ambient operating temperature (TA) –40 to 85 °C
Load capacitance (CL) 100 pF
Input rise and fall times ≤ 5ns
Input pulse voltages 0 to 3 V
Input and output timing ref. voltages 1.5 V
Table 6. Capacitance
Symbol Parameter(1)(2)
1. Effective capacitance measured with power supply at 5V; sampled, not 100% tested.
2. At 25°C, f = 1MHz.
Min Max Unit
CIN Input capacitance (SCL) 7 pF
COUT(3)
3. Outputs deselected.
Output capacitance (SDA, FT/OUT) 10 pF
tLP Low-pass filter input time constant (SDA and SCL) 0.25 1 µs
AI02568
0.8VCC
0.2VCC
0.7VCC
0.3VCC
DC and AC parameters M41T56
18/25
Figure 14. Power down/up mode AC waveforms
Table 7. DC characteristics
Symbol Parameter Test condition(1)
1. Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 4.5 to 5.5V (except where noted).
Min Typ Max Unit
ILI Input leakage current 0V ≤ VIN ≤ VCC ±1 µA
ILO Output leakage current 0V ≤ VOUT ≤ VCC ±1 µA
ICC1 Supply current Switch frequency = 100kHz 300 µA
ICC2 Supply current (standby) SCL, SDA = VCC – 0.3V 100 µA
VIL Input low voltage –0.3 1.5 V
VIH Input high voltage 3 VCC + 0.8 V
VOL Output low voltage IOL = 5mA, VCC = 4.5V 0.4 V
VBAT(2)
2. STMicroelectronics recommends the RAYOVAC BR1225 or BR1632 (or equivalent) as the battery supply.
Battery supply voltage 2.5 3 3.5 V
IBAT Battery supply current TA = 25°C, VCC = 0V,
oscillator ON, VBAT = 3V 450 550 nA
Table 8. Crystal electrical characteristics
Symbol Parameter(1)(2)
1. These values are externally supplied for the SO8 package. STMicroelectronics recommends the KDS DT-
38: 1TA/1TC252E127, Tuning Fork Type (thru-hole) or the DMX-26S: 1TJS125FH2A212, (SMD) quartz
crystal for industrial temperature operations. For contact information on this crystal type, see Section 8:
References on page 23.
2. Load capacitors are integrated within the M41T56. Circuit board layout considerations for the 32.768 kHz
crystal of minimum trace lengths and isolation from RF generating signals should be taken into account.
Min Typ Max Unit
fOResonant frequency 32.768 kHz
RSSeries resistance 60 kΩ
CLLoad capacitance 12.5 pF
AI00595
VCC
tFB tREC
tPD tRB
VPFD
VSO
DATA RETENTION TIME
SDA
SCL
IBAT
M41T56 DC and AC parameters
19/25
Table 9. Power down/up mode AC characteristics
Symbol Parameter(1)
1. Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 4.5 to 5.5V (except where noted).
Min Max Unit
tPD SCL and SDA at VIH before power down 0 ns
tFB VPFD (min) to VSS VCC fall time 300 µs
tRB VSS to VPFD (min) VCC rise time 100 µs
tREC SCL and SDA at VIH after power up 10 µs
Table 10. Power down/up trip points DC characteristics
Symbol Parameter(1)(2)
1. All voltages referenced to VSS.
2. Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 4.5 to 5.5V (except where noted).
Min Typ Max Unit
VPFD Power-fail deselect voltage 1.2 VBAT 1.25 VBAT 1.285 VBAT V
VSO Battery back-up switchover voltage VBAT V
Package mechanical data M41T56
20/25
6 Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
M41T56 Package mechanical data
21/25
Figure 15. SO8 – 8-pin plastic small package outline
1. Drawing is not to scale.
1. Drawing is not to scale.
Table 11. SO8 – 8-pin plastic small outline, package mechanical data
Symbol
millimetres inches
Typ Min Max Typ Min Max
A1.750.069
A1 0.10 0.25 0.004 0.010
A2 1.25 0.049
b 0.28 0.48 0.011 0.019
c 0.17 0.23 0.007 0.009
ccc 0.10 0.004
D 4.90 4.80 5.00 0.193 0.189 0.197
E 6.00 5.80 6.20 0.236 0.228 0.244
E1 3.90 3.80 4.00 0.154 0.150 0.157
e1.27– –0.050– –
h 0.25 0.50 0.010 0.020
k 0°8° 0°8°
L 0.40 1.27 0.016 0.050
L1 1.04 0.041
SO-A
E1
8
ccc
b
e
A
D
c
1
E
h x 45˚
A2
k
0.25 mm
L
L1
A1
GAUGE PLANE
Part numbering M41T56
22/25
7 Part numbering
Table 12. Ordering information scheme
Example: M41T 56 M 6 E
Device type
M41T
Supply voltage and write protect voltage
56 = VCC = 4.5 to 5.5V
Package
M = SO8
Temperature range
6 = –40°C to 85°C
Shipping method
E = Lead-free package (ECOPACK®), tubes
F = Lead-free package (ECOPACK®), tape & reel
Revision history M41T56
24/25
9 Revision history
Table 13. Document revision history
Date Revision Changes
Mar-1999 1.0 First issue
23-Dec-1999 1.1 SOH28 package added
21-Mar-2000 1.2 Series resistance max value changed (Ta b l e 8 )
30-Nov-2000 1.3 Added PSDIP8 package
25-Jan-2001 1.4 Corrected graphic, measurements of PSDIP8 (Figure 18, Table 14)
16-Feb-2001 2.0 Reformatted, table added (Table 16).
06-Apr-2001 2.1 Add temp./voltage information to characteristics (Ta b l e 7 , Ta bl e 2 ); correct
series resistance (Ta bl e 8)
17-Jul-2001 2.2 Basic formatting changes
02-Aug-2002 2.3
Modify reflow time and temperature footnote (Ta b l e 4 ); modify crystal
electrical characteristics table footnotes (Ta bl e 8 ); removed PSDIP8
package
07-Nov-2002 2.4 Correct figure name (Features on page 1)
15-Jun-2004 3.0 Reformatted; add lead-free information; update characteristics (Figure 11;
Ta b l e 4 , Ta b l e 1 2 )
11-Sep-2006 4
Changed document to new template; amalgamated diagrams in Features
on page 1; amended footnotes in Table 3: Register map; updated Package
mechanical data in Section 6: Package mechanical data; small text
changes for entire document, removed lead packages from Ta b l e 1 2 ,
ECOPACK compliant
09-Oct-2006 5 Updated package mechanical data in Figure 15.: SO8 – 8-pin plastic small
package outline.
10-Apr-2007 6 Updated package information references that only SO8 available (cover
page, Section 1, Section 4, Table 4, Ta bl e 8 , and Ta b l e 1 2 ).
06-Nov-2007 7
Added lead-free second level interconnect information to cover page and
Section 6: Package mechanical data; updated Ta b l e 4 , footnote 1 in
Ta b l e 8 ; addition of Section 8: References.
13-Dec-2007 8 Updated cover page and Section 8: References.
M41T56
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