MB90V340E-101 - Fujitsu - Datasheet.Live

DS07-13749-1E

FUJITSU SEMICONDUCTOR

DATA SHEET

“Check Sheet” is seen at the following support page

URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html

“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system

development.

Be sure to refer to the “Check Sheet” for the latest cautions on development.

16-bit Microcontroller

CMOS

F2MC-16LX MB90960 Series

MB90F962(S)/V340E-101/V340E-102

■DESCRIPTION

The MB90960-series is a 16-bit general-purpose microcontroller. Fujitsu now offers on-chip Flash-ROM program

memory up to 64 Kbytes.

The power supply (3 V) is supplied to the internal MCU core from an internal regulator circuit. This creates

a major advantage in terms of EMI and power consumption.

The unit features a 4 channel input capture unit, 1 channel 16-bit free-run timer, 2-channel LIN-UART, and 16-

channel 8/10-bit A/D converter as the peripheral resource.

Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.

■FEATURES

• Clock

• Built-in PLL clock frequency multiplying circuit

• Machine clock (PLL clock) selectable from frequency division by 2 of oscillation clock or 1 to 6-multiplied

oscillation clock (4 MHz to 24 MHz when oscillation clock is 4 MHz) .

• Sub clock operation : Up to 50 kHz (devices without S-suffix only)

• Minimum instruction execution time : 42 ns (4 MHz oscillation clock and 6-multiplied PLL clock) .

(Continued)

MB90960 Series

• Instruction system optimized controllers

• 16 Mbytes CPU memory space : Internal 24-bit addressing

• Various data types (bit, byte, word, and long word)

• Various addressing modes (23 types)

• Enhanced signed instructions of multiplication/division and RETI

• Enhanced high-accuracy operations by 32-bit accumulator

• Instruction system for high-level language (C language) / multitask

• System stack pointer

• Enhanced pointer indirect instructions

• Barrel shift instructions

• Higher execution speed

• 4-byte instruction queue

• Powerful interrupt function

• Powerful interrupt function with 8 levels and 34 factors

• Corresponds to 8-channel external interrupt

• CPU-independent automatic data transfer function

• Expanded intelligent I/O service function (EI2OS) : Maximum 16 channels

• Low-power consumption mode

• Clock mode

PLL clock mode (a PLL clock that is a multiple of the oscillation clock is used to operate the CPU and peripheral

functions.)

Main clock mode (the main clock, with the oscillation clock frequency divided by 2 is used to operate the CPU

and peripheral functions.)

Sub clock mode (the sub clock is used to operate the CPU and peripheral functions.)

• Standby mode

Sleep mode (stops the operation clock to the CPU.)

Watch mode (operates the sub clock and watch timer only.)

Time-base timer mode (operates the oscillation clock, sub clock, time-base timer and watch timer only.)

Stop mode (stops the operates the oscillation clock and sub clock.)

• CPU intermittent operation mode

• I/O port

• General-purpose input/output ports (CMOS output)

- 34 ports (products without S-suffix)

- 36 ports (products with S-suffix)

• Sub clock pin (X0A, X1A)

• Yes : (external oscillator used), products without S-suffix

• No : products with S-suffix

• Timer

• Time-base timer, watch timer (products without S-suffix), watchdog timer : 1 channel

• 8/16-bit PPG timer : 8-bit × 4 channels or 16-bit × 2 channels

• 16-bit reload timer : 2 channels

• 16- bit input/output timer

- 16-bit free-run timer : 1 channel

- 16- bit input capture (ICU) : 4 channels

(Continued)

MB90960 Series

(Continued)

• LIN-UART (LIN/SCI) : Maximum 2 channels

• Full-duplex double buffer

• Clock-asynchronous or clock-synchronous serial transfer

• DTP/External interrupt : 8 channels

• Module for activation of expanded intelligent I/O service (EI2OS) and generation of external interrupt by external

input.

• Delayed interrupt generator module

• Generates interrupt request for task switching.

• 8/10-bit A/D converter : 16 channels

• 8-bit and 10-bit resolution.

• Start by external trigger input.

• Conversion time : 3 µs (frequency, including sampling time at 24 MHz machine clock)

• Program patch function

• Detects address match for 6 address pointers.

• Changeable port input voltage level

• Automotive input level/CMOS Schmitt input level (initial value in single-chip mode is Automotive level).

MB90960 Series

■PRODUCT LINEUP

(Continued)

Part number

Parameter MB90F962 MB90F962S MB90V340E-101 MB90V340E-102

Type Flash memory product Evaluation product

CPU F2MC-16LX CPU

System clock PLL clock multiplier ( × 1, × 2, × 3, × 4, × 6, 1/2 when PLL stops)

Minimum instruction execution time : 42 ns (4 MHz oscillation clock, PLL × 6)

ROM Flash memory

64 Kbytes (60 Kbytes + 4 Kbytes Sectors) External

RAM capacitance 3 Kbytes 30 Kbytes

Power supply for

emulator*1⎯Yes

Sub clock pin

(X0A, X1A) Yes No Yes

Operating

voltage range

3.5 V to 5.5 V : at normal operation

(not using A/D converter and not doing

flash programming)

4.0 V to 5.5 V : at normal operation

5 V ± 10%

Operating

temperature range − 40 °C to + 125°C *2⎯

Package LQFP-48P PGA-299C

LIN-UART

2 channels 5 channels

Wide range of baud rate settings using a dedicated reload timer

Special synchronous options for adapting to different synchronous serial protocols

LIN functionality working either as master or slave LIN device

8/10-bit

A/D Converter

16 channels 24 channels

10-bit or 8-bit resolution

Conversion time: Min. 3 µs includes sample time (per one channel)

16-bit Reload Timer

2 channels 4 channels

Operation clock frequency: fsys/21, fsys/23, fsys/25 (fsys = Machine clock frequency)

Supports External Event Count function

16-bit I/O Timer

1 channel 4 channels

Signals an interrupt when overflowing.

Operating clock frequency: fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27

(fsys = Machine clock frequency)

16-bit Input Capture

4 channels 6 channels

Maintains I/O timer value by pin input (rising edge, falling edge, or both edge),

and generates interrupt

MB90960 Series

(Continued)

*1 : It is setting of Jumper switch (TOOL VCC) when emulator (MB2147-01) is used. Please refer to the Emulator

hardware manual for the details.

*2 : If used exceeding TA = +105°C, be sure to contact Fujitsu for reliability limitations.

Part number

Parameter MB90F962 MB90F962S MB90V340E-101 MB90V340E-102

8/16-bit

PPG timer

2 channels (16-bit) / 4 channels (8-bit)

8-bit reload counters × 4

8-bit reload registers for

“L” pulse width × 4

8-bit reload registers for

“H” pulse width × 4

8 channels (16-bit) /

16 channels (8-bit)

8-bit reload counters × 16

8-bit reload registers for

“L” pulse width × 16

8-bit reload registers for

“H” pulse width × 16

Supports 8-bit and 16-bit operation modes.

A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as

8-bit prescaler + 8-bit reload counter.

Operating clock frequency: fsys, fsys/21, fsys/22, fsys/23, fsys/24, or 128 µs

@ fosc = 4 MHz

(fsys = Machine clock frequency, fosc = Oscillation clock frequency)

External Interrupts

8 channels

Can be used rising edge, falling edge, starting up by “H”/“L” level input, external

input,extended intelligent I/O services (EI2OS) and DMA.

Corresponding evaluation

product MB90V340E-102 MB90V340E-101 ⎯

MB90960 Series

■PIN ASSIGNMENT

• MB90F962(S)

(TOP VIEW)

(LQFP-48P)

(FPT-48P-M26)

* : MB90F962: X0A, X1A

MB90F962S: P40, P41

P66/AN6/PPGC(D)

AVss

RST

Vcc

Vss

X0A/P40

X1A/P41

P82/SIN0/INT14R/TIN2

P50/AN8

AVcc

P44/FRCK0

P80/ADTG/INT12R

P51/AN9

P67/AN7/PPGE(F)

AVR

P60/AN0

P61/AN1

P62/AN2

P63/AN3

P64/AN4

P65/AN5 P27/IN3

P26/IN2

P25/IN1

P24/IN0

P23/PPGF(E)

P22/PPGD(C)

P21

P20

MD2

MD1

MD0

P52/AN10

P53/AN11/TIN3

P54/AN12/TOT3/INT8

P55/AN13/INT10

P56/AN14/INT11

P57/AN15/INT13

P84/SCK0/INT15R

P83/SOT0/TOT2

P42/INT9R

P43

P86/SOT1

P87/SCK1

P85/SIN1

MB90960 Series

■PIN DESCRIPTION

(Continued)

Pin No. Pin name Circuit type Function

LQFP-48P*

1AV

CC IVCC power input pin for analog circuit.

2 AVR ⎯Power (Vref+) input pin for A/D converter.

AVR should not exceed VCC.

3 to 8 P60 to P65 HGeneral-purpose I/O ports.

AN0 to AN5 Analog input pins for A/D converter.

9, 10

P66, P67

General-purpose I/O ports.

AN6, AN7 Analog input pins for A/D converter.

PPGC (D) ,

PPGE (F) Output pins for PPG.

P80

General-purpose I/O port.

ADTG Trigger input pin for A/D converter.

INT12R External interrupt request input pin for INT12R.

12 to 14 P50 to P52 H

General-purpose I/O ports (I/O circuit type of P50 is different

from that of MB90V340E) .

AN8 to AN10 Analog input pins for A/D converter.

P53

General-purpose I/O port.

AN11 Analog input pin for A/D converter.

TIN3 Event input pin for reload timer 3.

P54

General-purpose I/O port.

AN12 Analog input pin for A/D converter.

TOT3 Output pin for reload timer 3.

INT8 External interrupt request input pin for INT8.

17 to 19

P55 to P57

General-purpose I/O ports.

AN13 to AN15 Analog input pins for A/D converter.

INT10, INT11,

INT13 External interrupt request input pins for INT10, INT11, INT13.

20 MD2 D Input pin for selecting operation mode.

21, 22 MD1, MD0 C Input pins for selecting operation mode.

23 RST E Reset input.

24 VCC ⎯Power input pin (3.5 V to 5.5 V) .

25 VSS ⎯Power input pin (0 V) .

26 C I Capacity pin for stabilizing power supply. It should be connect-

ed to a higher than or equal to 0.1 µF ceramic capacitor.

27 X0 AOscillation input pin.

28 X1 Oscillation output pin.

MB90960 Series

(Continued)

Pin No. Pin name Circuit type Function

LQFP-48P*

29 to 32 P27 to P24 G

General-purpose I/O ports.

The register can be set to select whether to use a pull-up resistor.

This function is enabled in single-chip mode.

IN3 to IN0 Event input pins for input capture 0 to 3.

33, 34

P23, P22

General-purpose I/O ports.

The register can be set to select whether to use a pull-up resistor.

This function is enabled in single-chip mode.

PPGF (E) ,

PPGD (C) Output pins for PPG.

35, 36 P21, P20 G

General-purpose I/O ports.

The register can be set to select whether to use a pull-up resistor.

This function is enabled in single-chip mode.

37 P85 KGeneral-purpose I/O port.

SIN1 Serial data input pin for LIN-UART1.

38 P87 FGeneral-purpose I/O port.

SCK1 Clock I/O pin for LIN-UART1.

39 P86 FGeneral-purpose I/O port.

SOT1 Serial data output pin for LIN-UART1.

40 P43 F General-purpose I/O port.

41 P42 FGeneral-purpose I/O port.

INT9R External interrupt request input pin for INT9R.

P83

General-purpose I/O port.

SOT0 Serial data output pin for LIN-UART0.

TOT2 Output pin for reload timer 2

P84

General-purpose I/O port.

SCK0 Clock I/O pin for LIN-UART0.

INT15R External interrupt request input pin for INT15R.

P82

General-purpose I/O port.

SIN0 Serial data input pin for LIN-UART0.

INT14R External interrupt request input pin for INT14R.

TIN2 Event input pin for reload timer 2.

45 P44 F

General-purpose I/O port (I/O circuit type of P44 is different from

that of MB90V340E) .

FRCK0 Free-run timer 0 clock input pin.

MB90960 Series

(Continued)

* : FPT-48P-M26

Pin No.

Pin name Circuit type Function

LQFP-48P*

46, 47

P40, P41 F General-purpose I/O ports.

(products with S-suffix and MB90V340E-101)

X0A, X1A B

X0A: Oscillation input pin for sub clock

X1A: Oscillation output pin for sub clock

(products without S-suffix and MB90V340E-102)

48 AVSS IVSS power input pin for analog circuit.

MB90960 Series

■I/O CIRCUIT TYPE

(Continued)

Type Circuit Remarks

Oscillation circuit

High-speed oscillation feedback

resistor = approx. 1 MΩ

Oscillation circuit

Low-speed oscillation feedback

resistor = approx. 10 MΩ

CMOS input

• CMOS input

• No Pull-down

CMOS hysteresis input

Pull-up resistor value : approx. 50 kΩ

Standby control signal

Xout

Standby control signal

X1A

X0A

Xout

CMOS Hysteresis

inputs

Pull-down

resistor

CMOS Hysteresis

inputs

Pull-up

resistor

CMOS Hysteresis

inputs

MB90960 Series

(Continued)

Type Circuit Remarks

• CMOS level output (IOL = 4 mA,

IOH = − 4 mA)

• CMOS hysteresis input (With the

standby-time input shutdown function)

• Automotive input (With the standby-

time input shutdown function)

• CMOS level output (IOL = 4 mA,

IOH = − 4 mA)

• CMOS hysteresis input (With the

standby-time input shutdown function)

• Automotive input (With the standby-

time input shutdown function)

• Programmable pull-up resistor :

approx. 50 kΩ

• CMOS level output (IOL = 4 mA,

IOH = − 4 mA)

• CMOS hysteresis input (With the

standby-time input shutdown function)

• Automotive input (With the standby-

time input shutdown function)

• A/D analog input

Pout

Nout

P-ch

N-ch

CMOS hysteresis input

Automotive input

Standby control for

input shutdown

Pull-up control

Pull-up

resistor

CMOS hysteresis input

Pout

Nout

P-ch P-ch

N-ch

Standby control for

input shutdown

Automotive input

Pout

Nout

P-ch

N-ch

CMOS hysteresis input

A/D analog input

Standby control for

input shutdown

Automotive input

MB90960 Series

(Continued)

Type Circuit Remarks

Power supply input protection circuit

• CMOS level output (IOL = 4 mA,

IOH = − 4 mA)

• CMOS input (With standby-time input

shutdown function)

• Automotive input (With the standby-

time input shutdown function)

N-ch

P-ch

Pout

Nout

P-ch

N-ch

CMOS input

Automotive input

Standby control for

input shutdown

MB90960 Series

■HANDLING DEVICES

Special care is required for the following when handling the device :

• Preventing latch-up

• Treatment of unused pins

• Using external clock

• Notes on during operation of PLL clock mode

• Power supply pins (VCC/VSS)

• Pull-up/down resistors

• Crystal oscillator circuit

• Turning-on sequence of power supply to A/D converter and analog inputs

• Connection of unused pins of A/D converter

• Notes on energization

• Stabilization of power supply voltage

• Initialization

• Correspondence with +105 °C or more

1. Preventing latch-up

CMOS IC chips may suffer latch-up under the following conditions :

• A voltage higher than VCC or lower than VSS is applied to an input or output pin.

• A voltage higher than the rated voltage is applied between VCC and VSS.

•The AVCC power supply is applied before the VCC voltage.

Latch-up may increase the power supply current drastically, causing thermal damage to the device.

When used, note that maximum rated voltage is not exceeded.

For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVR) exceed the digital

power-supply voltage.

2. Treatment of unused pins

Leaving unused input pins open may result in misbehavior or latch-up and possible permanent damage of the

device. Therefore, they must be pulled up or pulled down through resistors. In this case, those resistors should

be more than 2 kΩ .

Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above

described connection.

3. Using external clock

To use external clock, drive the X0 (X0A) pin and leave X1 (X1A) pin open.

MB90960 Series

X0 (X0A)

X1 (X1A)

Open

MB90960 Series

4. Notes on during operation of PLL clock mode

On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while

the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its

self-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs.

5. Power supply pins (VCC/VSS)

• If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential

are connected the inside of the device to prevent such malfunctioning as latch-up.

To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level,

and to keep the recommended DC characteristics specified as the total output current, be sure to connect the

VCC and VSS pins to the power supply and ground externally.

• Connect VCC and VSS to the device from the power supply source with lowest possible impedance.

• It is recommended to connect a capacitor of about 0.1 µF as a bypass capacitor between VCC and VSS in the

vicinity of VCC and VSS pins of the device.

6. Pull-up/down resistors

The MB90960 series does not support internal pull-up/down resistors (except Port 2 : programmable pull-up

resistors) . Use pull-up/down handling where needed.

7. Crystal oscillator circuit

Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass

capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and

make sure, to the utmost effort, that lines of oscillation circuit do not cross the lines of other circuits. It is highly

recommended to provide a printed circuit board artwork surrounding X0 and X1 pins with a ground area for

stabilizing the operation.

8. Turning-on sequence of power supply to A/D converter and analog inputs

Make sure to turn on the A/D converter power supply (AVCC, AVR) and analog inputs (AN0 to AN15) after turning-

on the digital power supply (VCC) . Turn-off the digital power supply after turning off the A/D converter power

supply and analog inputs. In this case, make sure that the voltage does not exceed AVR or AVCC (turning on/off

the analog and digital power supplies simultaneously is acceptable) .

9. Connection of unused pins of A/D converter if A/D converter is not used

Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVR = VSS.

VCC

VSS

MB90960

Series

MB90960 Series

10. Notes on energization

To prevent malfunction of the internal voltage regulator , supply voltage profile while turning on the power supply

should be slower than 50 µs (0.2 V to 2.7 V) .

11. Stabilization of power supply voltage

If the power supply voltage varies acutely even within the operation assurance range of the VCC power supply

voltage, a malfunction may occur. The VCC power supply voltage must therefore be stabilized. As stabilization

guide lines, stabilize the power supply voltage so that VCC ripple fluctuations (peak to peak value) in the

commercial frequencies (50 Hz/60 Hz) fall within 10% of the standard VCC power supply voltage and the transient

fluctuation rate becomes 0.1 V/ms or less in instantaneous fluctuation for power supply switching.

12. Initialization

In the device, there are internal registers which are initialized only by a power-on reset. To initialize these registers,

turn on the power again.

13. Correspondence with +105 °C or more

If used exceeding TA = +105 °C, please contact Fujitsu for reliability limitations.

MB90960 Series

■BLOCK DIAGRAMS

• MB90V340E-101/V340E-102

RST

RAM

30 Kbytes

LIN-UART

5 channels

DMA

SOT4 to SOT0

SCK4 to SCK0

SIN4 to SIN0

AVRH

AVRL

ADTG

DA01, DA00

PPGF to PPG0

SDA1, SDA0

SCL1, SCL0

FRCK0

IN7 to IN0

OUT7 to OUT0

FRCK1

RX2 to RX0

TX2 to TX0

TIN3 to TIN0

TOT3 to TOT0

AD15 to AD00

A23 to A16

ALE

WRL

WRH

HRQ

HAK

RDY

CLK

INT15 to INT8

(INT15R to INT8R)

INT7 to INT0

CKOT

AN23 to AN0

Clock

controller F

MC-16LX

core

16-bit

I/O timer 0

16-bit

I/O timer 1

Input

capture

8 channels

Output

compare

8 channels

CAN

controller

3 channels

16-bit

reload Timer

4 channels

External

bus

DTP/

External

interrupt

Clock

monitor

Prescaler

(5 channels)

8/10-bit

A/D

converter

24 channels

10-bit

D/A converter

2 channels

Internal data bus

8/16-bit

PPG timer

16/8 channels

interface

2 channels

X0A *

X1A*

* : Only for MB90V340E-102

MB90960 Series

• MB90F962(S)

RAM

3 Kbytes

ROM

64 Kbytes

LIN-UART

2 channels

8/16-bit

PPG

timer

4/2 channels

SOT0, SOT1

SCK0, SCK1

SIN0, SIN1

PPGF(E), PPGD(C),

PPGC(D), PPGE(F)

IN0 to IN3

FRCK0

TIN2, TIN3

TOT2, TOT3

INT8, INT9R

INT10, INT11

INT12R, INT13

INT14R, INT15R

AVCC

AVSS

AN15 to AN0

AVR

ADTG

Clock

controller

16-bit

I/O

timer 0

Input

capture

4 channels

16-bit

reload

timer

2 channels

DTP/

External

interrupt

Prescaler

(2 channels)

8/10-bit

A/D

converter

16 channels

F2MC-16LX

core

Internal data bus

RST

X0A*

X1A*

* : Only for MB90F962

MB90960 Series

■MEMORY MAP

Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C

compiler effective. Since the low-order 16 bits are the same, the table in ROM can be referred without using

the far specification in the pointer declaration.

For example, an attempt to access 00C000H accesses the value at FFC000H in ROM.

The ROM area in bank FF exceeds 32 Kbytes, and its entire image cannot be shown in bank 00.

The image between FF8000H and FFFFFFH is visible in bank 00, while the image between FF0000H and

FF7FFFH is visible only in bank FF.

FFFFFFH

FF0000H

FEFFFFH

FE0000H

FDFFFFH

FD0000H

FCFFFFH

FC0000H

FBFFFFH

FB0000H

FAFFFFH

FA0000H

F9FFFFH

0000EFH

000000H

F90000H

F8FFFFH

F80000H

00FFFFH

007FFFH

007900H

0078FFH

000100H

008000H

MB90V340E-101

MB90V340E-102

FFFFFFH

FF0000H

0000EFH

000000H

00FFFFH

007FFFH

007900H

000CFFH

000100H

008000H

MB90F962(S)

RAM 30 Kbytes

RAM 3 Kbytes

010000H

FEFFFFH

0000F0H

0000FFH

ROM (FF bank)

ROM (FE bank)

ROM (FD bank)

ROM (FC bank)

ROM (FB bank)

ROM (FA bank)

ROM (F9 bank)

ROM (F8 bank)

ROM (image

of FF bank)

Peripheral

ROM (FF bank)

ROM (image

of FF bank)

Peripheral

: Access prohibited

MB90960 Series

■I/O MAP

(Continued)

Address Register Abbreviation Access Resource name Initial value

000000H,

000001HReserved

000002HPort 2 Data Register PDR2 R/W Port 2 XXXXXXXXB

000003HReserved

000004HPort 4 Data Register PDR4 R/W Port 4 XXXXXXXXB

000005HPort 5 Data Register PDR5 R/W Port 5 XXXXXXXXB

000006HPort 6 Data Register PDR6 R/W Port 6 XXXXXXXXB

000007HReserved

000008HPort 8 Data Register PDR8 R/W Port 8 XXXXXXXXB

000009H,

00000AHReserved

00000BHPort 5 Analog Input Enable Register ADER5 R/W Port 5, A/D 11111111B

00000CHPort 6 Analog Input Enable Register ADER6 R/W Port 6, A/D 11111111B

00000DHReserved

00000EHInput Level Select Register 0 ILSR0 R/W Port 2, 4, 5, 6 X000X0XXB

00000FHInput Level Select Register 1 ILSR1 R/W Port 8 XXXXXXX0B

0000010H,

000011HReserved

000012HPort 2 Direction Register DDR2 R/W Port 2 00000000B

000013HReserved

000014HPort 4 Direction Register DDR4 R/W Port 4 XXX00000B

000015HPort 5 Direction Register DDR5 R/W Port 5 00000000B

000016HPort 6 Direction Register DDR6 R/W Port 6 00000000B

000017HReserved

000018HPort 8 Direction Register DDR8 R/W Port 8 000000X0B

000019HReserved

00001AHPort A Direction Register DDRA W Port A XXX00XXXB

00001BH

00001DH

Reserved

00001EHPort 2 Pull-up Control Register PUCR2 R/W Port 2 00000000B

00001FHReserved

MB90960 Series

(Continued)

Address Register Abbreviation Access Resource name Initial value

000020HSerial Mode Register 0 SMR0 W, R/W

LIN-UART0

00000000B

000021HSerial Control Register 0 SCR0 W, R/W 00000000B

000022HReception/Transmission Data Register 0 RDR0/TDR0 R/W 00000000B

000023HSerial Status Register 0 SSR0 R, R/W 00001000B

000024HExtended Communication Control

R/W 000000XXB

000025HExtended Status Control Register 0 ESCR0 R/W 00000100B

000026HBaud Rate Generator Register 00 BGR00 R/W, R 00000000B

000027HBaud Rate Generator Register 01 BGR01 R/W, R 00000000B

000028HSerial Mode Register 1 SMR1 W, R/W

LIN-UART1

00000000B

000029HSerial Control Register 1 SCR1 W, R/W 00000000B

00002AHReception/Transmission Data Register 1 RDR1/TDR1 R/W 00000000B

00002BHSerial Status Register 1 SSR1 R, R/W 00001000B

00002CHExtended Communication Control

R/W 000000XXB

00002DHExtended Status Control Register 1 ESCR1 R/W 00000100B

00002EHBaud Rate Generator Register 10 BGR10 R/W, R 00000000B

00002FHBaud Rate Generator Register 11 BGR11 R/W, R 00000000B

000030H

00003AH

Reserved

00003BHAddress Detect Control Register 1 PACSR1 R/W Address Match

Detection 1 00000000B

00003CH

000047H

Reserved

000048HPPGC Operation Mode Control Register PPGCC W, R/W

16-bit PPG C/D

0X000XX1B

000049HPPGD Operation Mode Control Register PPGCD W, R/W 0X000001B

00004AHPPGC/PPGD Count Clock Select

00004BHReserved

00004CHPPGE Operation Mode Control Register PPGCE W, R/W

16-bit PPG E/F

0X000XX1B

00004DHPPGF Operation Mode Control Register PPGCF W, R/W 0X000001B

00004EHPPGE/PPGF Count Clock Select

00004FHReserved

MB90960 Series

(Continued)

Address Register Abbreviation Access Resource name Initial value

000050HInput Capture Control Status 0/1 ICS01 R/W Input Capture 0/1 00000000B

000051HInput Capture Edge 0/1 ICE01 R/W, R XXX0X0XXB

000052HInput Capture Control Status 2/3 ICS23 R/W Input Capture 2/3 00000000B

000053HInput Capture Edge 2/3 ICE23 R XXXXXXXXB

000054H

000063H

Reserved

000064HTimer Control Status 2 TMCSR2 R/W 16-bit Reload Timer 2 00000000B

000065HTimer Control Status 2 TMCSR2 R/W XXXX0000B

000066HTimer Control Status 3 TMCSR3 R/W 16-bit Reload Timer 3 00000000B

000067HTimer Control Status 3 TMCSR3 R/W XXXX0000B

000068HA/D Control Status 0 ADCS0 R/W

A/D Converter

000XXXX0B

000069HA/D Control Status 1 ADCS1 R/W, W 0000000XB

00006AHA/D Data Register 0 ADCR0 R 00000000B

00006BHA/D Data Register 1 ADCR1 R XXXXXX00B

00006CHA/D Converter Setting 0 ADSR0 R/W 00000000B

00006DHA/D Converter Setting 1 ADSR1 R/W 00000000B

00006EHReserved

00006FHROM Mirror Function Select ROMM W ROM Mirror XXXXXXX1B

000070H

00009DH

Reserved

00009EHAddress Detect Control Register 0 PACSR0 R/W Address Match

Detection 0 00000000B

00009FHDelayed Interrupt/Release Register DIRR R/W Delayed Interrupt

generation module XXXXXXX0B

0000A0HLow-power Consumption Mode

Control Register LPMCR W, R/W

Low-Power

consumption

Control Circuit

00011000B

0000A1HClock Selection Register CKSCR R, R/W

Low-Power

consumption

Control Circuit

11111100B

0000A2H

0000A7H

Reserved

0000A8HWatchdog Timer Control Register WDTC R, W Watchdog Timer XXXXX111B

0000A9HTime-base Timer Control Register TBTC W, R/W Time-base Timer 1XX00100B

MB90960 Series

(Continued)

Address Register Abbreviation Access Resource name Initial value

0000AAHWatch Timer Control Register WTC R, R/W Watch Timer 1X001000B

0000ABH

0000ADH

Reserved

0000AEHFlash Control Status FMCS R, R/W Flash Memory 000X0000B

0000AFHReserved

0000B0HInterrupt Control Register 00 ICR00 W, R/W

Interrupt Control

00000111B

0000B1HInterrupt Control Register 01 ICR01 W, R/W 00000111B

0000B2HInterrupt Control Register 02 ICR02 W, R/W 00000111B

0000B3HInterrupt Control Register 03 ICR03 W, R/W 00000111B

0000B4HInterrupt Control Register 04 ICR04 W, R/W 00000111B

0000B5HInterrupt Control Register 05 ICR05 W, R/W 00000111B

0000B6HInterrupt Control Register 06 ICR06 W, R/W 00000111B

0000B7HInterrupt Control Register 07 ICR07 W, R/W 00000111B

0000B8HInterrupt Control Register 08 ICR08 W, R/W 00000111B

0000B9HInterrupt Control Register 09 ICR09 W, R/W 00000111B

0000BAHInterrupt Control Register 10 ICR10 W, R/W 00000111B

0000BBHInterrupt Control Register 11 ICR11 W, R/W 00000111B

0000BCHInterrupt Control Register 12 ICR12 W, R/W 00000111B

0000BDHInterrupt Control Register 13 ICR13 W, R/W 00000111B

0000BEHInterrupt Control Register 14 ICR14 W, R/W 00000111B

0000BFHInterrupt Control Register 15 ICR15 W, R/W 00000111B

0000C0H

0000C9H

Reserved

0000CAHDTP/External Interrupt Enable 1 ENIR1 R/W

External Interrupt 1

00000000B

0000CBHDTP/External Interrupt Source 1 EIRR1 R/W XXXXXXXXB

0000CCHDetection Level Setting 1 ELVR1 R/W 00000000B

0000CDHDetection Level Setting 1 ELVR1 R/W 00000000B

0000CEHExternal Interrupt factor Select EISSR R/W 00000000B

0000CFHPLL/Sub clock Control Register PSCCR W PLL XXXX0000B

0000D0H

0000FFH

Reserved

MB90960 Series

(Continued)

Address Register Abbreviation Access Resource name Initial value

007900H

007917H

Reserved

007918HReload Register LC PRLLC R/W

16-bit PPG C/D

XXXXXXXXB

007919HReload Register HC PRLHC R/W XXXXXXXXB

00791AHReload Register LD PRLLD R/W XXXXXXXXB

00791BHReload Register HD PRLHD R/W XXXXXXXXB

00791CHReload Register LE PRLLE R/W

16-bit PPG E/F

XXXXXXXXB

00791DHReload Register HE PRLHE R/W XXXXXXXXB

00791EHReload Register LF PRLLF R/W XXXXXXXXB

00791FHReload Register HF PRLHF R/W XXXXXXXXB

007920HInput Capture 0 IPCP0 R

Input Capture 0/1

XXXXXXXXB

007921HInput Capture 0 IPCP0 R XXXXXXXXB

007922HInput Capture 1 IPCP1 R XXXXXXXXB

007923HInput Capture 1 IPCP1 R XXXXXXXXB

007924HInput Capture 2 IPCP2 R

Input Capture 2/3

XXXXXXXXB

007925HInput Capture 2 IPCP2 R XXXXXXXXB

007926HInput Capture 3 IPCP3 R XXXXXXXXB

007927HInput Capture 3 IPCP3 R XXXXXXXXB

007928H

00793FH

Reserved

007940HTimer Data 0 TCDT0 R/W

I/O Timer 0

00000000B

007941HTimer Data 0 TCDT0 R/W 00000000B

007942HTimer Control Status 0 TCCSL0 R/W 00000000B

007943HTimer Control Status 0 TCCSH0 R/W 0XXXXXXXB

007944H

00794BH

Reserved

00794CHTimer 2/Reload 2 TMR2/TMRLR2 R/W 16-bit Reload

Timer 2

XXXXXXXXB

00794DHR/W XXXXXXXXB

00794EHTimer 3/Reload 3 TMR3/TMRLR3 R/W 16-bit Reload

Timer 3

XXXXXXXXB

00794FHR/W XXXXXXXXB

007950H

0079DFH

Reserved

MB90960 Series

(Continued)

Notes : •Initial value of “X” represents unknown value.

•Any write access to reserved addresses in I/O map should not be performed. A read access to reserved

addresses results in reading “X”.

Address Register Abbreviation Access Resource name Initial value

0079E0HDetect Address Setting 0 PADR0 R/W

Address Match

Detection 0

XXXXXXXXB

0079E1HDetect Address Setting 0 PADR0 R/W XXXXXXXXB

0079E2HDetect Address Setting 0 PADR0 R/W XXXXXXXXB

0079E3HDetect Address Setting 1 PADR1 R/W XXXXXXXXB

0079E4HDetect Address Setting 1 PADR1 R/W XXXXXXXXB

0079E5HDetect Address Setting 1 PADR1 R/W XXXXXXXXB

0079E6HDetect Address Setting 2 PADR2 R/W XXXXXXXXB

0079E7HDetect Address Setting 2 PADR2 R/W XXXXXXXXB

0079E8HDetect Address Setting 2 PADR2 R/W XXXXXXXXB

0079E9H

0079EFH

Reserved

0079F0HDetect Address Setting 3 PADR3 R/W

Address Match

Detection 1

XXXXXXXXB

0079F1HDetect Address Setting 3 PADR3 R/W XXXXXXXXB

0079F2HDetect Address Setting 3 PADR3 R/W XXXXXXXXB

0079F3HDetect Address Setting 4 PADR4 R/W XXXXXXXXB

0079F4HDetect Address Setting 4 PADR4 R/W XXXXXXXXB

0079F5HDetect Address Setting 4 PADR4 R/W XXXXXXXXB

0079F6HDetect Address Setting 5 PADR5 R/W XXXXXXXXB

0079F7HDetect Address Setting 5 PADR5 R/W XXXXXXXXB

0079F8HDetect Address Setting 5 PADR5 R/W XXXXXXXXB

0079F9H

007FFFH

Reserved

MB90960 Series

■INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER

(Continued)

Interrupt cause EI2OS

corresponding

Interrupt vector Interrupt control

Number Address Number Address

Reset N #08 FFFFDCH⎯⎯

INT9 instruction N #09 FFFFD8H⎯⎯

Exception processing N #10 FFFFD4H⎯⎯

Reserved N #11 FFFFD0HICR00 0000B0H

Reserved N #12 FFFFCCH

Reserved N #13 FFFFC8HICR01 0000B1H

Reserved N #14 FFFFC4H

Reserved N #15 FFFFC0HICR02 0000B2H

Reserved N #16 FFFFBCH

Reserved N #17 FFFFB8HICR03 0000B3H

Reserved N #18 FFFFB4H

16-bit reload timer 2 Y1 #19 FFFFB0HICR04 0000B4H

16-bit reload timer 3 Y1 #20 FFFFACH

Reserved N #21 FFFFA8HICR05 0000B5H

Reserved N #22 FFFFA4H

PPG C/D N #23 FFFFA0HICR06 0000B6H

PPG E/F N #24 FFFF9CH

Time-base timer N #25 FFFF98HICR07 0000B7H

External interrupt 8 to 11 Y1 #26 FFFF94H

Watch Timer N #27 FFFF90HICR08 0000B8H

External interrupt 12 to 15 Y1 #28 FFFF8CH

A/D converter Y1 #29 FFFF88HICR09 0000B9H

I/O timer 0 N #30 FFFF84H

Reserved N #31 FFFF80HICR10 0000BAH

Reserved N #32 FFFF7CH

Input capture 0 to 3 Y1 #33 FFFF78HICR11 0000BBH

Reserved N #34 FFFF74H

LIN-UART 0 reception Y2 #35 FFFF70HICR12 0000BCH

LIN-UART 0 transmission Y1 #36 FFFF6CH

LIN-UART 1 reception Y2 #37 FFFF68HICR13 0000BDH

LIN-UART 1 transmission Y1 #38 FFFF64H

MB90960 Series

(Continued)

Y1 : Usable

Y2 : Usable, with EI2OS stop function

N : Unusable

Notes : •The peripheral resources sharing the ICR register have the same interrupt level.

•When 2 peripheral resources share the ICR register, only one can use extended intelligent I/O service

at a time.

•When either of the 2 peripheral resources sharing the ICR register specifies extended intelligent I/O

service, the other one cannot use interrupts.

Interrupt cause EI2OS

corresponding

Interrupt vector Interrupt control

Number Address Number Address

Reserved N #39 FFFF60HICR14 0000BEH

Reserved N #40 FFFF5CH

Flash memory N #41 FFFF58HICR15 0000BFH

Delayed interrupt generation module N #42 FFFF54H

MB90960 Series

■ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

(Continued)

Parameter Symbol Rating Unit Remarks

Min Max

Power supply voltage*1

VCC VSS − 0.3 VSS + 6.0 V

AVCC VSS − 0.3 VSS + 6.0 V VCC = AVCC*2

AVR VSS − 0.3 VSS + 6.0 V AVCC ≥ AVR*2

Input voltage*1VIVSS − 0.3 VSS + 6.0 V *3

Output voltage*1VOVSS − 0.3 VSS + 6.0 V *3

Maximum clamp current ICLAMP −2.0 +2.0 mA *4

Total Maximum clamp current Σ|ICLAMP|⎯40 mA *4

“L” level maximum output current IOL ⎯15 mA *4

“L” level average output current IOLAV ⎯4mA*4

“L” level maximum overall output current ΣIOL ⎯125 mA *4

“L” level average overall output current ΣIOLAV ⎯40 mA *4

“H” level maximum output current IOH ⎯−15 mA *4

“H” level average output current IOHAV ⎯−4mA*4

“H” level maximum overall output current ΣIOH ⎯−125 mA *4

“H” level average overall output current ΣIOHAV ⎯−40 mA *4

Power consumption PD⎯300 mW

Operating temperature TA

−40 +105 °C

−40 +125 °C*5

Storage temperature TSTG −55 +150 °C

MB90960 Series

(Continued)

*1 : This parameter is based on VSS = AVSS = 0 V.

*2 : Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the

analog inputs does not exceed AVCC when the power is switched on.

*3 : VI and VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. However, if the maximum

current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the

VI rating.

*4 : Applicable to pins : P20 to P27, P40 to P44, P50 to P57, P60 to P67, P80, P82 to P87

*5 : If used exceeding TA = +105°C, be sure to contact Fujitsu for reliability limitations.

•Use within recommended operating conditions.

•Use at DC voltage (current) .

•The +B signal should always be applied a limiting resistance placed between the +B signal and the

microcontroller.

•The value of the limiting resistance should be set so that when the +B signal is applied the input current to

the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.

•Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input

potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect

other devices.

•Note that if a +B signal is inputted when the microcontroller power supply is off (not fixed at 0 V) , the power

supply is provided from the pins, so that incomplete operation may result.

•Note that if the +B input is applied during power-on, the power supply is provided from the pins and the

resulting power supply voltage may not be sufficient to operate the power-on reset.

•Care must be taken not to leave the +B input pin open.

•Sample recommended circuits :

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

P-ch

N-ch

VCC

• Input/output equivalent circuits

+B input (0 V to 16 V)

Limiting

resistance

Protective diode

MB90960 Series

2. Recommended Conditions

(VSS = AVSS = 0 V)

* : If used exceeding TA = +105 °C, please contact Fujitsu for reliability limitations.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

Parameter Symbol Value Unit Remarks

Min Typ Max

Power supply voltage VCC,

AVCC

4.0 5.0 5.5 V Under normal operation

3.5 5.0 5.5 V

Under normal operation when not using

the A/D converter and not Flash

programming.

3.0 ⎯5.5 V Maintains RAM data in stop mode

Smooth capacitor CS0.1 ⎯1.0 µF

Use a ceramic capacitor or capacitor of

better AC characteristics for the C pin.

Bypass capacitor at the VCC pin should

be greater than this capacitor.

Operating temperature TA

−40 ⎯+105 °C

−40 ⎯+125 °C*

• C Pin Connection Diagram

MB90960 Series

3. DC Characteristics

(TA = −40 °C to +125 °C*1, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

(Continued)

Parameter Sym-

bol Pin Condition Value Unit Remarks

Min Typ Max

Input “H”

voltage

VIHS

⎯⎯0.8 VCC ⎯VCC + 0.3 V

Pin inputs if CMOS

hysteresis levels are

selected (except P82,

P85)

⎯⎯0.7 VCC ⎯VCC + 0.3 V

P82, P85 inputs if

CMOS input levels are

selected

VIHA ⎯⎯0.8 VCC ⎯VCC + 0.3 V

Pin inputs if

Automotive input

levels are selected

VIHR ⎯⎯0.8 VCC ⎯VCC + 0.3 V RST input pin (CMOS

hysteresis)

VIHM ⎯⎯VCC − 0.3 ⎯VCC + 0.3 V MD input pin

Input “L”

voltage

VILS

⎯⎯VSS − 0.3 ⎯0.2 VCC V

Pin inputs if CMOS

hysteresis input levels

are selected (except

P82, P85)

⎯⎯VSS − 0.3 ⎯0.3 VCC V

P82, P85 inputs if

CMOS input levels are

selected

VILA ⎯⎯VSS − 0.3 ⎯0.5 VCC V

Pin inputs if

Automotive input

levels are selected

VILR ⎯⎯VSS − 0.3 ⎯0.2 VCC VRST input pin (CMOS

hysteresis)

VILM ⎯⎯VSS − 0.3 ⎯VSS + 0.3 V MD input pin

Output “H”

voltage VOH ⎯VCC = 4.5 V,

IOH = −4.0 mA VCC − 0.5 ⎯⎯V

Output “L”

voltage VOL ⎯VCC = 4.5 V,

IOL = 4.0 mA ⎯⎯0.4 V

Input leak

current IIL ⎯VCC = 5.5 V,

VSS < VI < VCC −1⎯ + 1 µA

Pull-up

resistance RUP P20 to P27,

RST ⎯25 50 100 kΩ

Pull-down

resistance RDOWN MD2 ⎯25 50 100 kΩExcept Flash memory

devices

MB90960 Series

(Continued)

(TA = −40 °C to +125 °C*1, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

*1 : If used exceeding TA = + 105 °C, please contact Fujitsu for reliability limitations.

*2 : The power supply current is measured with an external clock.

Parameter Sym-

bol Pin Condition Value Unit Remarks

Min Typ Max

Power supply

current*2

ICC

VCC

VCC = 5.0 V,

Internal frequency : 24 MHz,

At normal operation.

⎯35 45 mA MB90F962(S)

VCC = 5.0 V,

Internal frequency : 24 MHz,

At writing Flash memory.

⎯50 60 mA MB90F962(S)

VCC = 5.0 V,

Internal frequency : 24 MHz,

At erasing Flash memory.

⎯50 60 mA MB90F962(S)

ICCS

VCC = 5.0 V,

Internal frequency : 24 MHz,

At sleep mode.

⎯12 20 mA MB90F962(S)

ICTS

VCC = 5.0 V,

Internal frequency : 2 MHz,

At main timer mode

⎯0.3 0.8 mA MB90F962(S)

ICTSPLL6

VCC = 5.0 V,

Internal frequency : 24 MHz,

At PLL timer mode,

External frequency = 4 MHz

⎯47mAMB90F962(S)

ICCL

VCC = 5.0 V,

Internal frequency : 8 kHz,

At sub clock operation mode,

TA = + 25°C

⎯40 100 µAMB90F962

ICCLS

VCC = 5.0 V,

Internal frequency : 8 kHz,

At sub clock sleep mode,

TA = + 25°C

⎯10 50 µAMB90F962

ICCT

VCC = 5.0 V,

Internal frequency : 8 kHz,

At watch mode,

TA = + 25°C

⎯830µAMB90F962

ICCH VCC = 5.0 V,

At stop mode, TA = + 25°C⎯525µA MB90F962(S)

Input capacity CIN

Other

than

AVCC,

AVSS,

AVR,

VCC,

VSS, C

⎯⎯515pF

MB90960 Series

4. AC Characteristics

(1) Clock Timing

(TA = −40 °C to +125 °C*, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

*: If used exceeding TA = + 105 °C, please contact Fujitsu for reliability limitations.

Parameter Symbol Pin Value Unit Remarks

Min Typ Max

Clock frequency fC

X0, X1

⎯

MHz

1/2 when PLL stops,

When using an oscillation circuit

416

PLL × 1,

When using an oscillation circuit

412

PLL × 2,

When using an oscillation circuit

PLL × 3,

When using an oscillation circuit

PLL × 4,

When using an oscillation circuit

PLL × 6,

When using an oscillation circuit

X0, X1

⎯

MHz

1/2 when PLL stops,

When using an external clock

420

PLL × 1,

When using an external clock

412

PLL × 2,

When using an external clock

PLL × 3,

When using an external clock

PLL × 4,

When using an external clock

PLL × 6,

When using an external clock

fCL X0A, X1A ⎯32.768 100 kHz

Clock cycle time tCYL

X0, X1 62.5 ⎯333 ns When using an oscillation circuit

X0, X1 41.67 ⎯333 ns When using an external clock

tCYLL X0A, X1A 10 30.5 ⎯µs When using sub clock

Input clock pulse width PWH, PWL X0 10 ⎯⎯ns Duty ratio is about 30% to 70%.

PWHL, PWLL X0A 5 15.2 ⎯µs

Input clock rise and fall

time tCR, tCF X0 ⎯⎯ 5 ns When using external clock

Internal operating clock

frequency (machine clock)

fCP ⎯1.5 ⎯24 MHz When using main clock

fCPL ⎯⎯8.192 50 kHz When using sub clock

Internal operating clock

cycle time (machine clock)

tCP ⎯41.67 ⎯666 ns When using main clock

tCPL ⎯20 122.1 ⎯µs When using sub clock

MB90960 Series

CYL

0.8 V

0.2 V

• Clock Timing

X0A

CYLL

0.8 V

0.2 V

WHL

WLL

MB90960 Series

Guaranteed operation range of MB90960 series

• CS2 (bit 0 in PSCCR register) = 0

• CS2 (bit 0 in PSCCR register) = 1

* : When using a crystal oscillator or a ceramic oscillator, the maximum oscillation clock frequency is 16 MHz.

External clock frequency and Machine clock frequency

• Guaranteed PLL Operation Range

5.5

3.5

41.5 24

Guaranteed operation range

Power supply voltage V

(V)

Machine clock f

(MHz)

4.5

Guaranteed A/D converter

operation range

820

Guaranteed PLL operation range (CS2=1)

Guaranteed PLL operation range (CS2=0)

1.5

Machine clock fCP (MHz)

External clock fC (MHz)*

Guaranteed oscillation frequency range

x1 (CS=000)

x2 (CS=001)

x3 (CS=010)

x4 (CS=011)

x1/2 (PLL off)

4812 16 20 24

3610

1.5

x4 (CS=101)

Machine clock f

(MHz)

External clock f

(MHz)*

Guaranteed oscillation frequency range

x2 (CS=100)

x1/2 (PLL off)

4812 16 20 24

3610

x6 (CS=110)

MB90960 Series

(2) Reset Standby Input

(TA = −40 °C to +125 °C*1, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

*1: If used exceeding TA = + 105 °C, please contact Fujitsu for reliability limitations.

*2 : Oscillation time of oscillator is the time that the amplitude reaches 90%.

In the crystal oscillator, the oscillation time is between several ms and tens of ms. In ceramic oscillators,

the oscillation time is between hundreds of µs and several ms. With an external clock, the oscillation time is 0 ms.

Parameter Symbol Pin Value Unit Remarks

Min Max

Reset input

time tRSTL RST

500 ⎯ns Under normal operation

Oscillation time of oscillator*2 + 100 µs⎯ns In stop mode

100 ⎯µs In time-base timer mode

RST

tRSTL

0.2 VCC 0.2 VCC

100 µs

90% of

amplitude

Instruction execution

Oscillation stabilization

waiting time

Oscillation time

of oscillator

Internal operation

clock

Internal reset

RST

0.2 VCC

tRSTL

0.2 VCC

• Under normal operation :

• In stop mode :

MB90960 Series

(3) Power-on Reset

(TA = −40 °C to +125 °C*, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

*: If used exceeding TA = + 105 °C, please contact Fujitsu for reliability limitations.

Note : If you change the power supply voltage too rapidly, a power-on reset may occur. We recommend that you

start up smoothly by restraining voltages when changing the power supply voltage during operation, as

shown in the figure below. Perform while not using the PLL clock. However, if voltage drops are within

1 V/s, you can operate while using the PLL clock.

Parameter Symbol Pin Condition Value Unit Remarks

Min Max

Power on rise time tRVCC ⎯0.05 30 ms

Power off time tOFF VCC 1⎯ms Due to repetitive operation

tOFF

2.7 V

0.2 V 0.2 V0.2 V

3 V

Holds RAM data

We recommend a rise of

50 mV/ms maximum.

MB90960 Series

(4) LIN-UART0/1

• Bit setting: ESCR0/1:SCES = 0, ECCR0/1:SCDE = 0

(TA = −40 °C to +125 °C*, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V)

*: If used exceeding TA = + 105 °C, please contact Fujitsu for reliability limitations.

Notes : • AC characteristic in CLK synchronized mode.

• CL is load capacity value of pins when testing.

• tCP is internal operating clock cycle time (machine clock) . Refer to “ (1) Clock Timing”.

Parameter Symbol Pin Condition Value Unit

Min Max

Serial clock cycle time tSCYC SCK0, SCK1

Internal shift clock

mode output pins are

CL = 80 pF + 1 TTL.

5 tCP ⎯ns

SCK ↓ → SOT delay time tSLOVI SCK0, SCK1,

SOT0, SOT1 −50 +50 ns

Valid SIN → SCK ↑tIVSHI SCK0, SCK1,

SIN0, SIN1 tCP + 80 ⎯ns

SCK ↑ → Valid SIN hold time tSHIXI SCK0, SCK1,

SIN0, SIN1 0⎯ns

Serial clock “L” pulse width tSHSL SCK0, SCK1

External shift clock

mode output pins are

CL = 80 pF + 1 TTL.

3 tCP - tR⎯ns

Serial clock “H” pulse width tSLSH SCK0, SCK1 tCP + 10 ⎯ns

SCK ↓ → SOT delay time tSLOVE SCK0, SCK1,

SOT0, SOT1 ⎯2 tCP + 60 ns

Valid SIN → SCK ↑tIVSHE SCK0, SCK1,

SIN0, SIN1 30 ⎯ns

SCK ↑ → Valid SIN hold time tSHIXE SCK0, SCK1,

SIN0, SIN1 tCP + 30 ⎯ns

SCK fall time tFSCK0, SCK1 ⎯10 ns

SCK rise time tRSCK0, SCK1 ⎯10 ns

SCK

2.4 V

0.8 V

SOT

0.8 V

2.4 V

0.8 V

tSLOVI

SIN

VIL

VIH

VIL

VIH

tSCYC

tIVSHI tSHIXI

• Internal Shift Clock Mode

MB90960 Series

• Bit setting: ESCR0/1:SCES = 1, ECCR0/1:SCDE = 0

(TA = −40 °C to +125 °C*, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V)

* : If used exceeding TA = + 105 °C, please contact Fujitsu for reliability limitations.

Parameter Symbol Pin Condition Value Unit

Min Max

Serial clock cycle time tSCYC SCK0, SCK1

Internal shift clock

mode output pins are

CL = 80 pF + 1 TTL.

5 tCP ⎯ns

SCK ↑ → SOT delay time tSHOVI SCK0, SCK1,

SOT0, SOT1 −50 +50 ns

Valid SIN → SCK ↓tIVSLI SCK0, SCK1,

SIN0, SIN1 tCP + 80 ⎯ns

SCK ↓ → Valid SIN hold time tSLIXI SCK0, SCK1,

SIN0, SIN1 0⎯ns

Serial clock “H” pulse width tSHSL SCK0, SCK1

External shift clock

mode output pins are

CL = 80 pF + 1 TTL.

3 tCP - tR⎯ns

Serial clock “L” pulse width tSLSH SCK0, SCK1 tCP + 10 ⎯ns

SCK ↑ → SOT delay time tSHOVE SCK0, SCK1,

SOT0, SOT1 ⎯2 tCP + 60 ns

Valid SIN → SCK ↓tIVSLE SCK0, SCK1,

SIN0, SIN1 30 ⎯ns

SCK ↓ → Valid SIN hold time tSLIXE SCK0, SCK1,

SIN0, SIN1 tCP + 30 ⎯ns

SCK fall time tFSCK0, SCK1 ⎯10 ns

SCK rise time tRSCK0, SCK1 ⎯10 ns

• External Shift Clock Mode

SCK

SOT

0.8 V

2.4 V

SLOVE

SIN

SHSL

SLSH

IVSHE

SHIXE

MB90960 Series

• Internal Shift Clock Mode

SCK

2.4 V

tSCYC

0.8 V

SOT

0.8 V

2.4 V

tSHOVI

SIN

VIL

VIH

tIVSLI

VIL

VIH

tSLIXI

• External Shift Clock Mode

SCK V

SOT

0.8 V

2.4 V

SHOVE

SIN V

IVSLE

SLIXE

SHSL

SLSH

MB90960 Series

• Bit setting: ESCR0/1:SCES = 0, ECCR0/1:SCDE = 1

(TA = −40 °C to +125 °C*, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V)

* : If used exceeding TA = + 105 °C, please contact Fujitsu for reliability limitations.

Note : tCP is the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock Timing” rating for tCP.

• Bit setting: ESCR0/1:SCES = 1, ECCR0/1:SCDE = 1

(TA = −40 °C to +125 °C*, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V)

* : If used exceeding TA = + 105 °C, please contact Fujitsu for reliability limitations.

Parameter Symbol Pin Condition Value Unit

Min Max

Serial clock cycle time tSCYC SCK0,SCK1

Internal clock operation

output pins are

CL = 80 pF + 1 TTL.

5 tCP ⎯ns

SCK ↑ → SOT delay time tSHOVI SCK0,SCK1

SOT0,SOT1 −50 +50 ns

Valid SIN → SCK ↓tIVSLI SCK0,SCK1

SIN0,SIN1 tCP + 80 ⎯ns

SCK ↓ → Valid SIN hold time tSLIXI SCK0,SCK1

SIN0,SIN1 0⎯ns

SOT → SCK ↓ delay time tSOVLI SCK0,SCK1

SOT0,SOT1 3 tCP − 70 ⎯ns

Parameter Symbol Pin Condition Value Unit

Min Max

Serial clock cycle time tSCYC SCK0,SCK1

Internal clock operation

output pins are

CL = 80 pF + 1 TTL.

5 tCP ⎯ns

SCK ↓ → SOT delay time tSLOVI SCK0,SCK1

SOT0,SOT1 −50 +50 ns

Valid SIN → SCK ↑tIVSHI SCK0,SCK1

SIN0,SIN1 tCP + 80 ⎯ns

SCK ↑ → Valid SIN hold time tSHIXI SCK0,SCK1

SIN0,SIN1 0⎯ns

SOT → SCK ↑ delay time tSOVHI SCK0,SCK1

SOT0,SOT1 3 tCP − 70 ⎯ns

SCK 2.4 V

SCYC

0.8 V

SOT 0.8 V

2.4 V

SOVLI

SIN V

IVSLI

SLIXI

0.8 V

SHOVI

0.8 V

2.4 V

MB90960 Series

Note : tCP is the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock Timing” rating for tCP.

(5) Trigger Input Timing

(TA = −40 °C to +125 °C*, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V)

* : If used exceeding TA = + 105 °C, please contact Fujitsu for reliability limitations.

Note : tCP is internal operating clock cycle time (machine clock) . Refer to “ (1) Clock Timing”.

Parameter Symbol Pin Condition Value Unit

Min Max

Input pulse width tTRGH

tTRGL

INT8, INT9R

INT10, INT11

INT12R, INT13

INT14R, INT15R

⎯200 ⎯ns

ADTG ⎯tCP + 200 ⎯ns

SCK 2.4 V

tSCYC

2.4 V

SOT 0.8 V

2.4 V

tSOVHI

SIN VIL

VIH

tIVSHI

VIL

VIH

tSHIXI

0.8 V

tSLOVI

0.8 V

2.4 V

TRGH

TRGL

INT8, INT9R

INT10, INT11

INT12R, INT13

INT14R, INT15R

ADTG

MB90960 Series

(6) Timer Related Resource Input Timing

(TA = −40 °C to +125 °C*, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V)

* : If used exceeding TA = + 105 °C, please contact Fujitsu for reliability limitations.

Note : tCP is internal operating clock cycle time (machine clock) . Refer to “ (1) Clock Timing”.

(7) Timer Related Resource Output Timing

(TA = –40°C to +125 °C*, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V)

* : If used exceeding TA = + 105 °C, please contact Fujitsu for reliability limitations.

Parameter Symbol Pin Condition Value Unit

Min Max

Input pulse width tTIWH TIN2, TIN3

IN0 to IN3 ⎯4 tCP ⎯ns

tTIWL

Parameter Symbol Pin Condition Value Unit

Min Max

CLK ↑ → TOUT change time tTO TOT2, TOT3

PPGC to PPGF ⎯30 ⎯ns

VIL

VIH

tTIWH

VIL

VIH

tTIWL

TIN2, TIN3

IN0 to IN3

CLK 2.4 V

0.8 V

2.4 V

tTO

TOT2, TOT3

PPGC

PPGF

MB90960 Series

5. A/D Converter

(TA = −40 °C to +125 °C*1, 3.0 V ≤ AVR − AVSS, VCC = AVCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

*1 : If used exceeding TA = + 105 °C, please contact Fujitsu for reliability limitations.

*2 : If A/D converter is not operating, a current when CPU is stopped is applicable (VCC = AVCC = AVR = 5.0 V) .

(Continued)

Parameter Symbol Pin Value Unit Remarks

Min Typ Max

Resolution ⎯⎯ ⎯ ⎯10 bit

Total error ⎯⎯ ⎯ ⎯±3.0 LSB

Nonlinearity error ⎯⎯ ⎯ ⎯±2.5 LSB

Differential

nonlinearity error ⎯⎯ ⎯ ⎯±1.9 LSB

Zero reading voltage VOT AN0 to AN15 AVSS − 1.5 AVSS + 0.5 AVSS + 2.5 LSB

Full scale reading

voltage VFST AN0 to AN15 AVR − 3.5 AVR − 1.5 AVR + 0.5 LSB

Compare time ⎯⎯ 1.0 ⎯16500 µs4.5 V ≤ AVCC ≤ 5.5 V

2.0 4.0 V ≤ AVCC < 4.5 V

Sampling time ⎯⎯ 0.5 ⎯∞µs4.5 V ≤ AVCC ≤ 5.5 V

1.2 4.0 V ≤ AVCC < 4.5 V

Analog port input

current IAIN AN0 to AN15 −0.3 ⎯+0.3 µA

Analog input

voltage VAIN AN0 to AN15 AVSS ⎯AVR V

Reference

voltage ⎯AVR AVSS + 2.7 ⎯AVCC V

Power supply current IAAVCC ⎯3.5 7.5 mA

IAH AVCC ⎯⎯ 5µA*2

Reference

voltage supply current

IRAVR ⎯600 900 µA

IRH AVR ⎯⎯ 5µA*2

Offset between

input channels ⎯AN0 to AN15 ⎯⎯ 4LSB

MB90960 Series

• About the external impedance of analog input and its sampling time

• A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling

time, the analog voltage changed to the internal sample and hold capacitor is insufficient, adversely affecting

A/D conversion precision.

Use the device with external circuits of the following output impedance for analog inputs:

• Recommended output impedance of external circuits are : Approx. 1.5 kΩ or lower (4.0 V ≤ AVCC ≤ 5.5 V,

sampling period = 0.5 µs)

• If an external capacitor is used, in consideration of the effect by tap capacitance caused by external capacitors

an on-chip capacitors, capacitance of the external one is recommended to be several thousand times as high

as internal capacitor.

• If the output impedance of an external circuit is too high, the sampling period for the analog voltage may be

insufficient.

• If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.

• To satisfy the A/D conversion precision standard, consider the relationship between the external impedance

and minimum sampling time and either adjust the resistor value and operating frequency or decrease the

external impedance so that the sampling time is longer than the minimum value.

(Continued)

• Analog input circuit model

Analog input

During sampling : ON

Comparator

Part number Analog input R C

MB90F962(S) 4.5 V ≤ AVCC ≤ 5.5 V 2.0 kΩ (Max) 16.0 pF (Max)

4.0 V ≤ AVCC < 4.5 V 8.2 kΩ (Max) 16.0 pF (Max)

MB90V340E-101/V340-102 4.5 V ≤ AVCC ≤ 5.5 V 2.0 kΩ (Max) 14.4 pF (Max)

4.0 V ≤ AVCC < 4.5 V 8.2 kΩ (Max) 14.4 pF (Max)

Note : The values are reference values.

MB90960 Series

(Continued)

• About errors

As | AVR − AVSS | becomes smaller, values of relative errors grow larger.

• At 4.5 V ≤ AVCC ≤ 5.5 V

Minimum sampling time [µs]

(External impedance = 0 kΩ to 20 kΩ)

• At 4.0 V ≤ AVCC < 4.5 V

(External impedance = 0 kΩ to 100 kΩ) (External impedance = 0 kΩ to 20 kΩ)

• The relationship between external impedance and minimum sampling time

External impedance [kΩ]

(External impedance = 0 kΩ to 100 kΩ)

Minimum sampling time [µs]

External impedance [kΩ]

Minimum sampling time [µs]

External impedance [kΩ]

Minimum sampling time [µs]

External impedance [kΩ]

MB90V340E-101/V340-102

MB90F962(S)

100

0 5 10 15 20 25 3035

MB90V340E-101/V340-102

012345678

MB90F962(S)

MB90V340E-101/V340-102

100

0 5 10 15 20 25 3035

MB90F962(S)

MB90V340E-101/V340-102

012345678

MB90F962(S)

MB90960 Series

6. Definition of A/D Converter Terms

(Continued)

Resolution : Analog variation that is recognized by an A/D converter.

Non linearity

error

: Deviation between a line across zero-transition line ( “00 0000 0000B” ← → “00 0000 0001B” )

and full-scale transition line ( “11 1111 1110B” ← → “11 1111 1111B” ) and actual conversion

characteristics.

Differential

linearity error

: Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal

value.

Total error : Difference between an actual value and an theoretical value. A total error includes zero

transition error, full-scale transition error, and linear error.

3FFH

3FEH

3FDH

004H

003H

002H

001H

AVSS AVR

VNT

1.5 LSB

0.5 LSB

{1 LSB × (N − 1) + 0.5 LSB}

Actual conversion

characteristics

(Actually-measured value)

Actual conversion

characteristics

Ideal characteristics

Digital output

Analog input

Total error

Total error of digital output “N” = VNT − {1 LSB × (N − 1) + 0.5 LSB}

1 LSB [LSB]

1 LSB (Ideal value) = AVR − AVSS

1024 [V]

VOT (Ideal value) = AVSS + 0.5 LSB [V]

VFST (Ideal value) = AVR − 1.5 LSB [V]

VNT : A voltage at which digital output transits from (N − 1) H to NH.

MB90960 Series

(Continued)

3FF

3FE

3FD

004

003

002

001

AVR AV

AVR

(N + 1)

(N − 1)

(N − 2)

(actual measurement value)

{1 LSB × (N − 1)

+ V

}

Actual conversion

characteristics

FST

(actual

measurement

value)

(actual

measurement value)

Actual conversion

characteristics

Ideal characteristics

Actual conversion

characteristics

Actual conversion

characteristics

Ideal

characteristics

Digital output

Analog inputAnalog input

(actual measurement value)

(N + 1) T

(actual measurement

value)

Non linearity error Differential linearity error

Non linearity error of digital output N =VNT − {1 LSB × (N − 1) + VOT}

1 LSB [LSB]

Differential linearity error of digital output N =V (N+1) T − VNT

1 LSB −1 LSB [LSB]

VFST − VOT

1022 [V]

1 LSB =

VOT : Voltage at which digital output transits from “000H” to “001H.”

VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”

MB90960 Series

7. Flash Memory Program/Erase Characteristics

* : This value comes from the technology qualification (using Arrhenius equation to translate high temperature

measurements into normalized value at +85 °C) .

Parameter Conditions Value Unit Remarks

Min Typ Max

Sector erase time (60 Kbytes)

TA = +25 °C

VCC = 5.0 V

⎯115s

Excludes programming

prior to erasure

Sector erase time (4 Kbytes) ⎯0.2 0.5 s Excludes programming

prior to erasure

Byte programming time ⎯21 6100 μsExcept for the overhead

time of the system level

Machine clock frequency fCP at

Flash programming/erasing VCC = 5.0 V ⎯⎯24 MHz

Program/Erase cycle ⎯10000 ⎯⎯cycle

Flash memory data

retention time

Average

TA = +85 °C20 ⎯⎯year *

MB90960 Series

■ORDERING INFORMATION

Part number Package Remarks

MB90F962PMT 48-pin plastic LQFP

FPT-48P-M26

7 mm ❑, 0.50 mm pitch

Flash Memory Product

(64Kbytes)

MB90F962SPMT

MB90V340E-101 299-pin ceramic PGA

PGA-299C-A01 Evaluation product

MB90V340E-102

MB90960 Series

■PACKAGE DIMENSION

Please confirm the latest Package dimension by following URL.

http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html

48-pin plastic LQFP Lead pitch 0.50 mm

Package width ×

package length 7× 7 mm

Lead shape Gullwing

Sealing method Plastic mold

Mounting height 1.70 mm MAX

Weight 0.17 g

Code

(Reference) P-LFQFP48-7×7-0.50

48-pin plastic LQFP

(FPT-48P-M26)

2003 FUJITSU LIMITED F48040S-c-2-2

3625

INDEX

9.00±0.20(.354±.008)SQ

0.145±0.055

(.006±.002)

0.08(.003)

"A"

0˚~8˚

.059 –.004

+.008

–0.10

+0.20

1.50

0.60±0.15

(.024±.006)

0.10±0.10

(.004±.004)

(Stand off)

0.25(.010)

Details of "A" part

112

0.08(.003)M

(.008±.002)

0.20±0.05

0.50(.020)

LEAD No.

(Mounting height)

.276 –.004

+.016

–0.10

+0.40

7.00

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

Note 1) * : These dimensions include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

MB90960 Series

F0703

The information for microcontroller supports is shown in the following homepage.

http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html

FUJITSU LIMITED

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

The information, such as descriptions of function and application

circuit examples, in this document are presented solely for the

purpose of reference to show examples of operations and uses of

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operation of the device with respect to use based on such

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